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Memory Management patents



      
           
This page is updated frequently with new Memory Management-related patent applications. Subscribe to the Memory Management RSS feed to automatically get the update: related Memory RSS feeds. RSS updates for this page: Memory Management RSS RSS


Methods and apparatus for supporting persistent memory

Methods and apparatus for supporting persistent memory

International Business Machines

Memory management system, method and computer program product

Date/App# patent app List of recent Memory Management-related patents
01/29/15
20150032986
 Memory block management systems and methods patent thumbnailnew patent Memory block management systems and methods
A system for real-time operating system memory block and message management is disclosed. The real-time operating system enables different processes to migrate an allocated memory block from one type of memory block to another type of memory block, and to reliably release the block back to its correct pool of origin.
01/29/15
20150032977
 Memory management system, method and computer program product patent thumbnailnew patent Memory management system, method and computer program product
According to one aspect of the present disclosure a method and technique for managing memory access is disclosed. The method includes setting a memory databus utilization threshold for each of a plurality of processors of a data processing system to maintain memory databus utilization of the data processing system at or below a system threshold.
International Business Machines Corporation
01/29/15
20150032972
 Methods and  supporting persistent memory patent thumbnailnew patent Methods and supporting persistent memory
A processing device features a processing unit, a memory management system, and persistent memory in a persistent memory domain. The processing device provides an enhanced write-back (wb-e) memory space for an application running on the processing unit.
01/01/15
20150006844
 Methods, systems, and devices for management of a memory system patent thumbnailMethods, systems, and devices for management of a memory system
Methods, devices, and systems for a memory management system within an electronic device are disclosed, such as those wherein the memory management system is external to and compatible with architectures of currently existing operating systems. One such memory management system may include a power savings manager configured to be invoked by a memory allocation manager.
Micron Technology, Inc.
01/01/15
20150006843
 Thread-based memory management with garbage collection patent thumbnailThread-based memory management with garbage collection
Systems and methods for thread-based memory management may include activating a processing thread. The memory may include a first region and a second region with the first region having several segments.
Sap Ag
01/01/15
20150006557
 Conservative garbage collecting and tagged integers for memory management patent thumbnailConservative garbage collecting and tagged integers for memory management
Aspects for conservative garbage collecting are disclosed. In one aspect, root objects included in a call stack are identified, which comprise integers and pointers.
Microsoft Corporation
12/25/14
20140380017
 Memory management and  allocation using free-list patent thumbnailMemory management and allocation using free-list
A method of managing a memory of an apparatus includes maintaining a plurality of lists of identifiers that each has an associated size value, wherein each identifier identifies a corresponding region of the memory that had been allocated for a process but that is currently not required by any of the one or more processes. When a process requests allocation of a region of the memory: one of the lists is identified that has an associated size value suitable for the allocation request; and if that list is not empty, a region of the memory is identified to the process by one of the identifiers that identifier is removed from that list, and, otherwise, a region of the memory is allocated with a size of the identified associated size value and the allocated region of the memory is identified the process..
Freescale Semiconductor, Inc.
12/18/14
20140372726
 Memory management method and apparatus patent thumbnailMemory management method and apparatus
A method for managing memory using a virtual memory manager includes receiving a memory allocation request, allocating memory of a physical address space in response to the memory allocation request, mapping an address value of the memory allocated in the physical address space to consecutive primary virtual address space, and mapping the address value of the primary virtual address space to one of a first and second secondary virtual address spaces to process a new memory allocation request in a situation where memory a fragmentation occurs. Other embodiments are also disclosed.
Samsung Electronics Co., Ltd.
12/18/14
20140372694
 Methods and  cut-through cache management for a mirrored virtual volume of a virtualized storage system patent thumbnailMethods and cut-through cache management for a mirrored virtual volume of a virtualized storage system
Methods and apparatus for cut-through cache memory management in write command processing on a mirrored virtual volume of a virtualized storage system, the virtual volume comprising a plurality of physical storage devices coupled with the storage system. Features and aspects hereof within the storage system provide for receipt of a write command and associated write data from an attached host.
Netapp, Inc.
12/11/14
20140365834
 Memory management tools patent thumbnailMemory management tools
The present technology monitors events that allocate and deallocate virtual memory regions in a device, wherein the events include system calls from user space. The system can generate a log of events, and based on the log of events, track regions of virtual memory allocated and deallocated via the events.
12/11/14
20140365821

Independent management of data and parity logical block addresses


A data storage method includes identifying, in a set of data items associated with respective logical addresses for storage in a memory, a first subset of the logical addresses associated with the data items containing application data, and a second subset of the logical addresses associated with the data items containing parity information that has been calculated over the application data. The data items associated with the first identified subset are stored in one or more first physical memory areas of the memory, and the data items associated with the second identified subset are stored in one or more second physical memory areas of the memory, different from the first physical memory areas.
12/04/14
20140359240

Virtualizing processor memory protection with "l1 iterate and l2 drop/repopulate"


A computing system includes a guest domain access control register (dacr), and guest first and second level page tables, the page tables containing domain identifiers used to obtain domain access information and access permission information, and the domain access information and the access permission information providing an effective guest access permission. The computing system provides a shadow page table, in which domain identifiers are used to identify domain access information in a processor dacr that are mapped from domain access information in the guest dacr, and in which access permissions are mapped from effective access permission information in the guest page tables and guest dacr.
11/27/14
20140351550

Memory management threads of data distribution service middleware


Disclosed herein are a memory management apparatus and method for threads of data distribution service middleware. The apparatus includes a memory area management unit, one or more thread heaps, and a queue.
11/27/14
20140351549

Off-heap direct-memory data stores, methods of creating and/or managing off-heap direct-memory data stores, and/or systems including off-heap direct-memory data store


Certain example embodiments relate to a highly-concurrent, predictable, fast, self-managed, in-process space for storing data that is hidden away from the garbage collector and its related pauses. More particularly, certain example embodiments relate to improved memory management techniques for computer systems that leverage an off-heap direct-memory data store that is massively scalable and highly efficient.
11/27/14
20140351185

Machine learning memory management and distributed rule evaluation


Aspects of the present disclosure relate to management of evaluated rule data sets. Specifically, a unreduced evaluated rule data set may contain a number of items to be compared or analyzed according to a number of rules, and may also contain the results of such analysis.
11/13/14
20140337597

Computer, program, and memory management method


A computer capable of managing reference relationships between data executes access of first and second storage regions in which stored data can be altered and a third storage region in which stored data cannot be altered. The computer sets specification data in the first storage region for accessing data stored in the second and third storage regions, and shifts data having a reference relationship with the specification data from among the data stored in the third storage region to the second storage region.
10/30/14
20140325165

Memory apparatus and memory management method


A memory apparatus includes a detection unit, a storage unit, an update unit, and a determination unit. The detection unit is configured to detect a deterioration factor of a nonvolatile memory.
10/30/14
20140325152

Quadtree based data management for memory


A method for managing memory. The method includes executing a memory management function, and reading data from memory into a particular size array structure using the memory management function based on using quadtree structure sub-functions to scan the particular size array structure for filtering the data iteratively..
10/30/14
20140321281

Fifo buffer with multiple stream packet segmentation


An epoch-based network processor internally segments packets for processing and aggregation in epoch payloads. Fifo buffers interact with a memory management unit to efficiently manage the segmentation and aggregation process..
10/16/14
20140310502

Memory management apparatus and memory management method thereof


A memory management apparatus and method thereof are disclosed. The memory management apparatus includes a micro translation look-aside buffers, a main translation look-aside buffer, a page address history table and a controller.
10/16/14
20140310497

Method and memory management


A method for memory management, include allocating an empty page of a physical memory for reference data according to execution of an application program, and mapping the empty page to a virtual memory; checking a physical address of the physical memory to which the reference data has been loaded; mapping the checked physical address to the virtual memory to which the empty page has been mapped, and mapping the reference data; and releasing allocation of the allocated physical memory when the reference data is mapped to the virtual memory.. .
10/09/14
20140304485

Embedded memory management scheme for real-time applications


Memory is dynamically shared or allocated in an embedded computer system. The types of memory that are part of the system are first determined.
10/02/14
20140293706

Semiconductor memory device, memory management method, and electronic apparatus


There is provided a semiconductor memory device including a bit line configured to write data, and a time measurement unit configured to measure a write time of the bit line.. .
09/18/14
20140282583

Dynamic memory management with thread local storage usage


Methods and arrangements for dynamic memory management. Data are accepted for thread local storage, and memory usage is monitored in thread local storage.
09/18/14
20140282580

Method and apparatus to save and restore system memory management unit (mmu) contexts


A wireless mobile device includes a graphic processing unit (gpu) that has a system memory management unit (mmu) for saving and restoring system mmu translation contexts. The system mmu is coupled to a memory and the gpu.
09/18/14
20140281364

Microcontroller for memory management unit


One embodiment of the present invention includes a microcontroller coupled to a memory management unit (mmu). The mmu is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table.
09/18/14
20140281363

Multi-threaded memory management


Memory management includes maintaining a first mapping structure for each thread of a multi-threaded process. A second mapping structure is maintained for each core of a multi-core processing device.
09/18/14
20140281358

Migration scheme for unified virtual memory system


A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address.
09/18/14
20140281357

Common pointers in unified virtual memory system


A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address.
09/18/14
20140281356

Microcontroller for memory management unit


One embodiment of the present invention includes a microcontroller coupled to a memory management unit (mmu). The mmu is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table.
09/18/14
20140281332

Externally programmable memory management unit


A method includes reading, by a processor, one or more configuration values from a storage device or a memory management unit. The method also includes loading the one or more configuration values into one or more registers of the processor.
09/18/14
20140281303

Memory management for in-memory processing computing environments and systems


Data can be stored in a memory for in-memory processing system such the data is available for processing as soon as it is needed to be processed. By way of example, first portion and a second portion of the data can be stored in the memory of the in-memory processing system for processing by the in-memory processing system, such that the second portion of the data is stored in the memory before the in-memory processing system completes the processing of the first portion of the data, thereby allowing the in-memory processing system to process the second portion of the data when the processing system is able to process the second portion of the data.
09/18/14
20140281296

Fault buffer for tracking page faults in unified virtual memory system


A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address.
09/18/14
20140281256

Fault buffer for resolving page faults in unified virtual memory system


A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address.
09/18/14
20140281255

Page state directory for managing unified virtual memory


A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address.
09/18/14
20140281177

Hybrid memory management


Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi-level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed.
09/18/14
20140281058

Accelerator buffer access


Technologies are generally described for methods and systems effective to provide accelerator buffer access. An operating system may allocate a range of addresses in virtual address spaces and a range of addresses in a buffer mapped region of a physical (or main) memory.
09/18/14
20140278340

Dynamic memory management for a virtual supercomputer


Present invention embodiments enable the handling of various index-memory architectures for a virtual supercomputer that would allow for a heterogeneous storage of variable length index words with non-sequential addressing, and also dynamic changes to the index-memory architecture. A computer-implemented system, method, and apparatus allow for different types of node index memory (nim) architectures for the virtual supercomputer.
09/18/14
20140267230

Physical and environmental simulation using causality matrix


A simulation engine for causing a local or distributed computing system to produce a simulation of a virtual world includes one or more program modules that improve the realism and memory management of the simulation. An overworld object includes data pertaining to a world map and data pertaining to parameters for instantiating one or more npcs within the virtual world.
09/11/14
20140258674

System-on-chip and operating the same


A system on chip (soc) includes a central processing unit (cpu), an intellectual property (ip) block, and a memory management unit (mmu). The cpu is configured to set a prefetch direction corresponding to a working set of data.
09/11/14
20140258669

Memory management method, memory management apparatus and numa system


Embodiments of the present invention provide a memory management method, a memory management apparatus and a numa system. The memory management method includes: determining, according to a memory demand information which includes memory demand information sent by a processor, whether a memory controller meeting the memory demand information exists in a local processing node which the processor; and if exists, determining, in the memory controller meeting the memory demand information, a memory management area meeting the memory demand information, and allocating the memory management area meeting the memory demand information to the processor.
09/11/14
20140258605

Memory imbalance prediction based cache management


Embodiments of methods, apparatuses, and storage media for memory imbalance prediction-based cache memory management are disclosed herein. In one instance, the apparatus may include a memory controller associated with a memory having a plurality of storage units.
09/11/14
20140258603

Asymmetric memory migration in hybrid main memory


Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, the memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory.
09/04/14
20140250286

Computer and memory management method


A computer comprising: a processor; a memory; and an i/o device, the memory including at least one first memory element and at least one second memory element, wherein a memory area provided by the at least one second memory element includes a data storage area and a data compression area, wherein the computer comprises a virtualization management unit, and wherein the virtualization management unit is configured to: set a working set for storing data required for processing performed by a virtual machine in generating the virtual machine, and control data stored in the working set in such a manner that part of the data stored in the working set is stored in the data compression area based on a state of accesses to the data stored in the working set.. .
09/04/14
20140250037

Methods for memory management in parallel networks


A simple format is disclosed and referred to as elementary network description (end). The format can fully describe a large-scale neuronal model and embodiments of software or hardware engines to simulate such a model efficiently.
08/28/14
20140244960

Computing device, memory management method, and program


According to one embodiment, there is provided a computing device managing a first memory region and a second memory region, a power consumption to hold data stored in the second memory region being smaller than that of the first memory region, including: a data manager and a data processor. The data manager manages a referring number, which is a number of processes referring to first data existing in either one of the first memory region or the second memory region.
08/28/14
20140244916

Virtual memory management apparatus


A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages.
08/28/14
20140241435

Method for managing memory, and device for decoding video using same


The present invention relates to a method for managing memory, and to a device for decoding video using same. The method includes the marking of motion information stored in a first buffer in response to a memory management control command (mmco), and the deleting of the motion information from the first buffer or the moving of the motion information to a second buffer in response to the marked information..
08/28/14
20140241048

Phase change memory management


A three dimensional (3d) stack of phase change memory (pcm) devices which includes pcm devices stacked in a 3d array, the pcm devices having memory regions; a memory management unit on at least one of the pcm devices; a stack controller in the memory management unit to monitor an ambient device temperature (tambient) with respect to a neighborhood of memory regions in the pcm devices and to adjust a programming current with respect to at least one of the memory regions in the neighborhood of memory regions in accordance with the tambient. Also disclosed is a method of programming a pcm device..
08/21/14
20140237209

Memory management method, memory management apparatus and numa system


Embodiments of the present invention provide a memory management method, a memory management apparatus and a numa system. The memory management method includes: determining, according to a memory demand information which includes memory demand information sent by a processor, whether a memory controller meeting the memory demand information exists in a local processing node which the processor; and if exists, determining, in the memory controller meeting the memory demand information, a memory management area meeting the memory demand information, and allocating the memory management area meeting the memory demand information to the processor.
08/21/14
20140237190

Memory system and management method therof


A memory system having multiple memory layers is provided. The memory system includes an upper memory layer and an intermediate memory layer comprising a first sub-memory consisting of a nonvolatile memory and a second sub-memory consisting of a volatile memory in a parallel structure positioned below the upper memory layer, and a memory management unit that controls operations of the upper memory layer and the intermediate memory layer.
08/14/14
20140229689

System and ballooning wth assigned devices


A system and method for ballooning with assigned devices includes inflating a memory balloon, determining whether a first memory page is locked based on information associated with the first memory page, when the first memory page is locked unlocking the first memory page and removing first memory addresses associated with the first memory page from management by an input/output memory management unit (iommu), and reallocating the first memory page. The first memory page is associated with a first assigned device..
08/14/14
20140226727

Memory management for video decoding


Techniques and tools described herein help manage memory efficiently during video decoding, especially when multiple video clips are concurrently decoded. For example, with clip-adaptive memory usage, a decoder determines first memory usage settings expected to be sufficient for decoding of a video clip.
08/07/14
20140218767

Image forming apparatus, memory management image forming apparatus, and program


An image forming apparatus that performs image processing using information stored in a semiconductor memory includes an obtaining unit configured to obtain from the semiconductor memory a block size used for data reading and writing, and a management unit configured to discretely arrange and manage, with respect to a specific region set in the semiconductor memory, use-based information to be updated along with execution of the image processing, included in the stored information, according to the obtained block size.. .
07/31/14
20140215184

Memory management in a streaming application


One embodiment is directed to a method for processing a stream of tuples. The method may include receiving a stream of tuples to be processed by a plurality of processing elements operating on one or more computer processors.
07/31/14
20140215177

Methods and systems for managing heterogeneous memories


A system includes a processor and first and second memories coupled to the processor. The first and second memories have a hardware attribute, such as bandwidth, latency and/or power consumption, wherein a first value of the hardware attribute of the first memory is different from a second value of the hardware attribute of the second memory.
07/31/14
20140215165

Memory management in a streaming application


One embodiment is directed to a method for processing a stream of tuples. The method may include receiving a stream of tuples to be processed by a plurality of processing elements operating on one or more computer processors.
07/31/14
20140214658

Mobile device containing contactless payment card used in transit fare collection


An apparatus such as a mobile phone includes a contactless smart card or payment device, where the smart card is intended for use in both commerce transaction payment and transit fare payment (or other venue access) environments. The payment device may function as both an electronic wallet for commerce transactions and as a transit system card, for access to and fare payment of transit services.
07/24/14
20140208064

Virtual memory management system with reduced latency


A computer system using virtual memory provides hybrid memory access either through a conventional translation between virtual memory and physical memory using a page table possibly with a translation lookaside buffer, or a high-speed translation using a fixed offset value between virtual memory and physical memory. Selection between these modes of access may be encoded into the address space of virtual memory eliminating the need for a separate tagging operation of specific memory addresses..
07/24/14
20140208042

Providing hardware support for shared virtual memory between local and remote physical memory


In one embodiment, the present invention includes a memory management unit (mmu) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links.
07/24/14
20140208034

System and efficient paravirtualized os process switching


The exemplary embodiments described herein relate to systems and methods for improved process switching of a paravirtualized guest with a software-based memory management unit (“mmu”). One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, resulting in a performance of the following: create a plurality of new processes for each of a plurality of virtual environments, each of the virtual environments assigned one of a plurality of address space identifiers (“asids”) stored in a cache memory, perform a process switch to one of the virtual environments thereby designating the one of the virtual environments as the active virtual environment, determine whether the active virtual environment has exhausted each of the asids, and flush a cache memory when it is determined that the active virtual environment has exhausted each of the asids..
07/17/14
20140201126

Methods and systems for applications for z-numbers


Specification covers new algorithms, methods, and systems for artificial intelligence, soft computing, and deep learning/recognition, e.g., image recognition (e.g., for action, gesture, emotion, expression, biometrics, fingerprint, facial, ocr (text), background, relationship, position, pattern, and object), big data analytics, machine learning, training schemes, crowd-sourcing (experts), feature space, clustering, classification, svm, similarity measures, modified boltzmann machines, optimization, search engine, ranking, question-answering system, soft (fuzzy or unsharp) boundaries/impreciseness/ambiguities/fuzziness in language, natural language processing (nlp), computing-with-words (cww), parsing, machine translation, sound and speech recognition, video search and analysis (e.g. Tracking), image annotation, geometrical abstraction, image correction, semantic web, context analysis, data reliability, z-number, z-web, z-factor, rules engine, control system, autonomous vehicle, self-diagnosis and self-repair robots, system diagnosis, medical diagnosis, biomedicine, data mining, event prediction, financial forecasting, economics, risk assessment, e-mail management, database management, indexing and join operation, memory management, data compression, event-centric social network, image ad network..
07/17/14
20140199995

Methods and providing unified wireless communication through efficient memory management


A method, an apparatus, and a computer program product for wireless communication are provided in connection with improving interactions between various components within a wireless device to enable improved communications between wireless devices. In an example, a wireless device may include an application processor equipped to send first and second amounts of data to be buffered in a buffer associated with a controller, and cease communications with the controller after the second amount of data is sent.
07/10/14
20140196003

Image processing software development method, image processing software development device, and image processing software development program


The present invention includes four types of component diagrams, namely, an input/output data memory management component diagram, an input data value setup component diagram, a library execution component diagram, and an output data value acquisition component diagram, with respect to image processing library functions for a programming language and to an input/output data structure for the image processing library functions. The present invention also includes upper-level component diagrams, which are prepared by connecting the four types of component diagrams as lower-level component diagrams in the order of use, writes an algorithm by combining the lower- and upper-level component diagrams, and executes the written algorithm.
07/10/14
20140195837

Enhanced dynamic memory management with intelligent current/power consumption minimization


A low-power state current/power consumption for each volatile memory device in a plurality of volatile memory devices is obtained. Data is copied from a first set of the volatile memory devices to a second set of the volatile memory devices, where the second set of volatile memory devices has a lower current/power consumption than the first set of volatile memory devices.
07/10/14
20140195765

Implementing user mode foreign device attachment to memory channel


A method, system and computer program product are provided for implementing attachment of a user mode foreign device to a memory channel in a computer system. A user mode foreign device is attached to the memory channel using memory mapping of device registers and device buffers to the processor address space.
07/10/14
20140195742

System on chip including memory management unit and memory address translation method thereof


A system on chip (soc) including a memory management unit (mmu) and a memory address translation method thereof are provided. The soc includes a master intellectual property (ip) configured to output a request corresponding to each of a plurality of working sets; an mmu module comprising a plurality of mmus, each of which is allocated for one of the working sets and translates virtual addresses corresponding to the request into physical addresses; a first bus interconnect configured to connect the mmu module with a memory device and to transmit the request, on which address translation has been performed in at least one of the mmus, to the memory device; and a second bus interconnect configured to connect the master ip with the mmu module and to allocate one of the mmus for each of the working sets..
07/10/14
20140195480

Persistent memory management


Apparatuses, systems, methods, and computer program products are disclosed for persistent memory management. Persistent memory management may include providing a persistent data structure stored at least partially in volatile memory configured to ensure persistence of the data structure in a non-volatile memory medium.
07/10/14
20140192074

Memory management techniques


Memory management techniques that permit an executing process to store content in memory and later retrieve that content from the memory, but that also permit a memory manager to discard that content to address memory pressure. A process executing on a computing device may notify a memory manager of the computing device that first memory space allocated to the process contains first content that is available for discard.
07/03/14
20140189326

Memory management in secure enclaves


Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit.
07/03/14
20140189248

Efficient online construction of miss rate curves


Miss rate curves are constructed in a resource-efficient manner so that they can be constructed and memory management decisions can be made while the workloads are running. The resource-efficient technique includes the steps of selecting a subset of memory pages for the workload, maintaining a least recently used (lru) data structure for the selected memory pages, detecting accesses to the selected memory pages and updating the lru data structure in response to the detected accesses, and generating data for constructing a miss-rate curve for the workload using the lru data structure.


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Memory Management topics: Memory Management, Virtual Machine, Storage Device, Volatile Memory, Data Processing, Logical Unit, Virtual Memory, Computer System, Dynamic Data, Base Memory, Database Management System, Data Storage, Defragment, Compatibility, Object Code

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