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Memory Management patents

      

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 Memory management patent thumbnailMemory management
A memory management method and a device, where the method includes: receiving a memory access request, where the memory access request carries a virtual address; determining a page fault type of the virtual address if finding, in a translation lookaside buffer tlb and a memory, no page table entry corresponding to the virtual address; allocating a corresponding page to the virtual address if the page fault type of the virtual address is a blank-page-caused page fault, where the blank-page-caused page fault means that no corresponding page is allocated to the virtual address; and updating the page table entry corresponding to the virtual address to the memory and the tlb. The memory manager does not generate a page fault when a blank-page-caused page fault occurs, but allocates a corresponding page to the virtual address.
Huawei Technologies Co.,ltd.


 Memory management methods and systems patent thumbnailMemory management methods and systems
A method and an apparatus for determining a usage level of a memory device to notify a running application to perform memory reduction operations selected based on the memory usage level are described. An application calls apis (application programming interface) integrated with the application codes in the system to perform memory reduction operations.
Apple Inc.


 Memory management method patent thumbnailMemory management method
A method for managing main memory including dram and nvram in a computer depending on the operation state of the computer is provided. The method includes: (a) upon start of the computer, loading a program and the like into the dram, and loading predetermined read-only data and the like into the nvram; (b) in a state transition from a normal operation to a suspend state, moving data in the dram to the nvram; (c) in a state transition from the suspend state to the normal operation, reading data from the nvram for program execution; (d) in the case where a data write to the nvram occurs, stopping the data write, and moving data in a data area of the nvram subjected to the data write, to the dram; and (e) performing the data write to the dram to which the data has been moved..
International Business Machines Corporation


 Nonvolatile memory interface for metadata shadowing patent thumbnailNonvolatile memory interface for metadata shadowing
A method for memory management includes streaming bits to a memory buffer on a memory device using a write data channel that optimizes a speed of writing to the memory devices. The bits are written to non-volatile memory cells in the memory device at a first speed, using a bi-directional bus.
International Business Machines Corporation


 Hybrid heap memory management patent thumbnailHybrid heap memory management
A database memory manager determines a size class for each of a plurality of memory allocation requests. The memory manager then, based on the determined size classes, assigns which of a plurality of sub-allocators forming part of a plurality of memory pools should handle each memory allocation request.
Sap Se


 Low-power memory-access method and associated apparatus patent thumbnailLow-power memory-access method and associated apparatus
A low-power memory access method and associated apparatus are provided. The apparatus includes a memory controller and a processing unit.
Mediatek Inc.


 Cooperative overlay patent thumbnailCooperative overlay
An embedded system includes a program to be executed. The program is divided into overlays.
Macronix International Co., Ltd.


 Intelligent computer memory management patent thumbnailIntelligent computer memory management
A plurality of memory allocators are initialized within a computing system. At least a first memory allocator and a second memory allocator in the plurality of memory allocators are each customizable to efficiently handle a set of different memory request size distributions.
International Business Machines Corporation


 Limiting memory in a distributed environment at an operator or operator grouping level patent thumbnailLimiting memory in a distributed environment at an operator or operator grouping level
Techniques are disclosed for memory management in a streams processing environment. Certain aspects of the present disclosure provide a method generally including monitoring, via a streams manager for a distributed application, an amount of memory used by a group of executing processes, and for each group, comparing the amount of memory used by the group against a memory threshold, and determining whether the memory used by the group exceeds a first threshold, and reducing memory usage by the group when the memory used by the group exceeds the first threshold..
International Business Machines Corporation


 Limiting memory consumption in a distributed environment at a group level patent thumbnailLimiting memory consumption in a distributed environment at a group level
Techniques are disclosed for memory management in a streams processing environment. Certain aspects of the present disclosure provide a method generally including monitoring, via a streams manager for a distributed application, an amount of memory used by a group of executing processes, and for each group, comparing the amount of memory used by the group against a memory threshold, and determining whether the memory used by the group exceeds a first threshold, and reducing memory usage by the group when the memory used by the group exceeds the first threshold..
International Business Machines Corporation


Intelligent computer memory management

A plurality of memory allocators are initialized within a computing system. At least a first memory allocator and a second memory allocator in the plurality of memory allocators are each customizable to efficiently handle a set of different memory request size distributions.
International Business Machines Corporation

Memory management systems and methods

The present invention facilitates efficient and effective utilization of storage management features. In one embodiment, a system comprises: a storage component, a memory controller, and a communication link.
Nvidia Corporation

Method and managing applicaiton state in a network interface controller in a high performance computing system

Methods related to communication between and within nodes in a high performance computing system are presented. Processing time for message exchange between a processing unit and a network controller interface in a node is reduced.
Intel Corporation

Methods and systems for memory management in storage drives

This disclosure relates generally to storage drives and more particularly to methods and systems for memory management in storage drives. In one embodiment, a method for memory management in a storage drive is disclosed.
Wipro Limited

Memory management method, memory control circuit unit and memory storage device

The disclosure provides a memory management method, which includes: selecting at least one logical unit mapped to physical units programmed based on a first operating mode; determining a reference count according to a number of the selected logical unit; receiving a first write command; determining whether the reference count is greater than a threshold value; if the reference count is greater than the threshold value, programming first data into a first physical unit based on the first operating mode, and each memory cell in the first physical unit stores a first number of bit data; if the reference count is not greater than the threshold value, programming the first data into a second physical unit based on a second operating mode, and each memory cell in the second physical unit stores a second number of bit data, and the second number is greater than the first number.. .
Phison Electronics Corp.

Memory management unit and accessing data

A method for accessing data blocks stored in a computer system. The method may include hardware components for controlling access to a memory unit of the computer system.
International Business Machines Corporation

Memory management unit and accessing data

A method for accessing data blocks stored in a computer system. The method may include hardware components for controlling access to a memory unit of the computer system.
International Business Machines Corporation

Efficient utilization of memory gaps

Systems and methods pertain to a method of memory management. Gaps are unused portions of a physical memory in sections of the physical memory mapped to virtual addresses by entries of a translation look-aside buffer (tlb).
Qualcomm Incorporated

Memory management method, memory control circuit unit and memory storage device

A memory management method for a rewritable non-volatile memory module is provided. The method includes: selecting at least one first physical erasing unit from at least part of physical erasing units according to a first parameter.
Phison Electronics Corp.

System and thermoelectric memory temperature control

Systems, methods, and computer programs, embodied in or as a memory management module, are disclosed for thermally controlling memory to increase its performance. One exemplary embodiment includes a memory, one or more processors, and a thermoelectric cooling device.
Qualcomm Incorporated

Bank issued contactless payment card used in transit fare collection

An apparatus such as a mobile phone includes a contactless smart card or payment device, where the smart card is intended for use in both commerce transaction payment and transit fare payment (or other venue access) environments. The payment device may function as both an electronic wallet for commerce transactions and as a transit system card, for access to and fare payment of transit services.

Wand: concurrent boxing system for all pointers with or without garbage collection

Boxed pointers are disclosed, for all pointers, for safe and sequential or parallel use. Since a pointer box can be arbitrarily large, it supports any fat pointer encoding possible.

System and managing access requests to a memory storage subsystem

Embodiments of this disclosure relate to improving solid-state non-volatile memory management. Embodiments improve the management of solid-state non-volatile memory by providing an execution manager responsible for controlling the timing of providing a request to a memory unit for execution.
Western Digital Technologies, Inc.

Nonvolatile memory device and storage device comprising the same, storing bad block management information into the same

A nonvolatile memory device is provided. The nonvolatile memory device includes a memory cell array comprising a first area that stores memory management information and a second area that stores user data, a decoder configured to select at least one of rows of the first area or the second area based on an address, a page buffer configured to store data in memory cells connected to the selected at least one row or to detect data stored in the memory cells, and control logic configured to control the decoder and the page buffer in response to a specific command, to access the first area.
Samsung Electronics Co., Ltd.

Memory management

Apparatus, systems, and methods to manage memory operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to retrieve a global sequence number from a memory device, receive a read request for data stored in a logical block address in the memory device, retrieve a media sequence number from the logical block address in the memory device, and return a null response in lieu of the data stored in the logical block address when the media sequence number is older than the global sequence number.
Intel Corporation

Memory management method, memory control circuit unit and memory storage device

A memory management method, a memory control circuit unit and a memory storage device are provided. In an exemplary embodiment, the memory management method includes: receiving a first write command and first write data and obtaining a first number; programming the first write data and moving first storage data stored in a plurality of first physical programming units, where a total number of the first physical programming units conforms to the first number; receiving a second write command and second write data and obtaining a second number; programming the second write data and moving second storage data stored in a plurality of second physical programming units, where a total number of the second physical programming units conforms to the second number; and erasing at least one physical erasing unit.
Phison Electronics Corp.

Memory management within secure migratable architecture

Methods and systems for executing virtualized processes on a computing system are disclosed, including techniques for memory management when executing such processes. One method includes allocating a portion of memory to a process hosted by an operating system of a computing system having a first computing architecture, the process comprising a firmware environment implementing a second computing architecture different from the first computing architecture, the first computing architecture applying virtual addressing to the portion of memory.
Unisys Corporation

Method for memory management in virtual machines, and corresponding system and computer program product

A method for memory management includes in a virtual-machine monitor of a virtualization platform allocating in a guest operating system of the virtual machines guest balloon memory modules of variable memory size. Memory parameters of a given virtual machine are read.
Eco4cloud S.r.l.

Electronic devices and memory management methods thereof

Electronic devices and memory management methods thereof are provided. Memory management methods may include setting page data of a nonvolatile memory as a read/write mode, copying the page data of the nonvolatile memory to a dynamic random access memory (dram) and setting the page data of the dram copied from the nonvolatile memory as a read only mode..
Samsung Electronics Co., Ltd.

Cache decice and memory system

A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages.
Kabushiki Kaisha Toshiba

Memory management method, memory control circuit unit and memory storage apparatus

A memory management method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: receiving a first write command and writing data corresponding to the first write command into a first spare physical erasing unit; detecting an amount of second spare physical erasing units excluding the first spare physical erasing unit; determining whether the amount of the second spare physical erasing units is less than a threshold value; and performing a first procedure if the amount of the second spare physical erasing units is less than the threshold value.
Phison Electronics Corp.

Memory management for reception of wireless communications

A base station or user equipment (ue) may manage scheduling of code blocks to be transmitted and manage memory interface usage to enhance memory read and write operations and provide for enhanced efficiency for decoding of retransmissions of code blocks. In some aspects, a base station or ue may identify an available throughput, or budget, for performing read and write operations to a memory.
Qualcomm Incorporated

System and device for preventing attacks in real-time networked environments

Disclosed are various embodiments of a system or method for the transparent handling of real-time streaming application-level data. The disclosed embodiments permit the identification and modification of specified file patterns from within the live stateful data transactions across computer networks.
Board Of Regents, The University Of Texas System

Multi-page check hints for selective checking of protected container page versus regular page type indications for pages of convertible memory

A processor of an aspect includes at least one translation lookaside buffer (tlb) and a memory management unit (mmu). Each tlb is to store translations of logical addresses to corresponding physical addresses.
Intel Corporation

Access log and address translation log for a processor

A processor maintains an access log indicating a stream of cache misses at a cache of the processor. In response to each of at least a subset of cache misses at the cache, the processor records a corresponding entry in the access log, indicating a physical memory address of the memory access request that resulted in the corresponding miss.
Ati Technologies Ulc

Shared virtual address space for heterogeneous processors

A processor uses the same virtual address space for heterogeneous processing units of the processor. The processor employs different sets of page tables for different types of processing units, such as a cpu and a gpu, wherein a memory management unit uses each set of page tables to translate virtual addresses of the virtual address space to corresponding physical addresses of memory modules associated with the processor.
Advanced Micro Devices, Inc.

Application driven hardware cache management

A processor includes a processing core to generate a memory request for an application data in an application. The processor also includes a virtual page group memory management (vpgmm) unit coupled to the processing core to specify a caching priority (cp) to the application data for the application.
Intel Corporation

Light-weight on-chip signal monitor with integrated memory management and data collection

Embodiments of a device and method to automatically acquire signal quality metrics in a digital communication system are disclosed. The device may include acquisition means to sample the likelihood of a digital communication signal passing through a grid of time and amplitude regions, and storage means by which such likelihood measurements may be accumulated in a computer memory array for analysis.
Finisar Corporation

Memory management unit and operating method thereof

A memory management unit mmu for managing virtual memory for a plurality of cores includes a plurality of translation lookaside buffers tlbs each corresponding to each of the cores; a plurality of page tables each corresponding to each of the cores and to each of the tlbs, and each synchronized with a corresponding tlb, a meta page including virtual page-physical page mapping information included in the plurality of page tables, one of the plurality of page tables being a main page table; and the meta page including a shared bit field indicating whether or not the virtual page-physical page mapping information is stored in the plurality of tlbs.. .
Electronics And Telecommunications Research Institute

Memory allocation and recovery strategies for byte-addressable non-volatile ram (nvram)

Disclosed herein are innovations in memory management and data recovery for systems that operate using storage class memory (scm), such as non-volatile ram (nvram). The disclosed innovations have particular application to production database systems, where reducing database downtime in the event of a system crash is highly desirable.
Sap Se

Transactional memory management techniques

Techniques for improved transactional memory management are described. In one embodiment, for example, an apparatus may comprise a processor element, an execution component for execution by the processor element to concurrently execute a software transaction and a hardware transaction according to a transactional memory process, a tracking component for execution by the processor element to activate a global lock to indicate that the software transaction is undergoing execution, and a finalization component for execution by the processor element to commit the software transaction and deactivate the global lock when execution of the software transaction completes, the finalization component to abort the hardware transaction when the global lock is active when execution of the hardware transaction completes.
Intel Corporation

Potentate: a cryptography-obfuscating, self-policing, pervasive distribution system for digital content

A system and method for self-policed, authenticated, offline/online, viral marketing and distribution of content such as software, text, and multimedia with effective copyright and license enforcement and secure selling. The system is based on key and cryptography hiding techniques, using source-to-source transformation for efficient, holistic steganography that systematically inflates and hides critical code by: computation interleaving; flattening procedure calls and obfuscating stack by de-stacking arguments; obfuscating memory management; and encoding scalars as pointers to managed structures that may be distributed and migrated all over the heap using garbage collection.

Memory protection unit, memory management unit, and microcontroller

A memory protection unit including hardware registers for entering address tables, a configuration memory for storing the address tables, a preconfigured hardware logic for managing the configuration memory, a data connection between the configuration memory and the hardware logic for loading the hardware registers, a first interface for controlling the loading by a computing core, and a second interface for writing to the configuration memory by the computing core.. .
Robert Bosch Gmbh

Memory management method, memory control circuit unit, and memory storage apparatus

A memory management method is provided according to an exemplary embodiment. The method includes: receiving a write command and determining whether a usage status of physical units associated to a storage area conforms to a first predetermined status; storing write data corresponding to the write command to at least one of physical units associated to a temporary area if the usage status of the physical units associated to the storage area conforms to the first predetermined status; associating the at least one physical unit storing the write data to the storage area; and allocating at least one logical unit to map the at least one physical unit associated to the storage area..
Phison Electronics Corp.

Selective error coding

A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place.
International Business Machines Corporation

Selective error coding

A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place.
International Business Machines Corporation

Memory management of data processing systems

Techniques for memory management of a data processing system are described herein. According to one embodiment, a memory usage monitor executed by a processor of a data processing system monitors memory usages of groups of programs running within a memory of the data processing system.
Apple Inc.

Microcontroller simple memory relocation function

A method and apparatus for microcontroller (mcu) memory relocation. The mcu includes a central processing unit (cpu) and memory, but lacks a memory management unit (mmu).
Renesas Electronics America Inc.

Exit-less movement of guest memory assigned to a device in a virtualized environment

Embodiments of the disclosure enable exit-less movement of guest memory assigned to a device in a virtualized environment. An example method comprises detecting, by a processing device of a host computer system, an event triggering a move/copy of a memory page residing at a first memory location that is mapped to a virtual address space of a virtual machine being hosted by the host computer system.
Red Hat Israel, Ltd.

Multi-threaded translation and transaction re-ordering for memory management units

Systems and methods relate to performing address translations in a multithreaded memory management unit (mmu). Two or more address translation requests can be received by the multithreaded mmu and processed in parallel to retrieve address translations to addresses of a system memory.
Qualcomm Incorporated

Speculative pre-fetch of translations for a memory management unit (mmu)

Systems and methods for pre-fetching address translations in a memory management unit (mmu) are disclosed. The mmu detects a triggering condition related to one or more translation caches associated with the mmu, the triggering condition associated with a trigger address, generates a sequence descriptor describing a sequence of address translations to pre-fetch into the one or more translation caches, the sequence of address translations comprising a plurality of address translations corresponding to a plurality of address ranges adjacent to an address range containing the trigger address, and issues an address translation request to the one or more translation caches for each of the plurality of address translations, wherein the one or more translation caches pre-fetch at least one address translation of the plurality of address translations into the one or more translation caches when the at least one address translation is not present in the one or more translation caches..
Qualcomm Incorporated

Providing memory management unit (mmu) partitioned translation caches, and related apparatuses, methods, and computer-readable media

Providing memory management unit (mmu) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, in one aspect, an apparatus comprising an mmu is provided.
Qualcomm Incorporated

Memory management method, memory storage device and memory control circuit unit

A memory management method, a memory storage device and a memory control circuit unit are provided. The memory management method includes: detecting a replacement physical unit number of a rewritable non-volatile memory module; adjusting an available capacity of the rewritable non-volatile memory module from a first available capacity to a second available capacity if the replacement physical unit number meets a default condition.
Phison Electronics Corp.

Access control for memory protection key architecture

A processing system includes a processing core to execute a task and a memory management unit, coupled to the core. The memory management unit includes a protection key register comprising a plurality of fields.
Intel Corporation



Memory Management topics:
  • Memory Management
  • Virtual Machine
  • Storage Device
  • Volatile Memory
  • Data Processing
  • Logical Unit
  • Virtual Memory
  • Computer System
  • Dynamic Data
  • Base Memory
  • Database Management System
  • Data Storage
  • Defragment
  • Compatibility
  • Object Code


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