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 Memory management in virtualized computing patent thumbnailMemory management in virtualized computing
Apparatuses, methods and storage media associated with memory management in virtualized computing are disclosed herein. In embodiments, an apparatus may include a virtual machine manager to manage operations of a plurality of virtual machines, having a memory manager to manage allocation and de-allocation of physical memory to and from the plurality of virtual machines.
Intel Corporation


 Apparatuses for securing program code stored in a non-volatile memory patent thumbnailApparatuses for securing program code stored in a non-volatile memory
An embodiment of an apparatus for securing program code stored in a non-volatile memory is introduced. A non-volatile memory contains a first region and a second region.
Nuvoton Technology Corporation


 Method and  memory management patent thumbnailMethod and memory management
One or more circuits of a device may comprise a memory. A first portion of a first block of the memory may store program code and/or program data, a second portion of the first block may store an index associated with a second block of the memory, and a third portion of the first block may store an indication of a write status of the first portion.
Blackbird Technology Holdings, Inc.


 Handling address translation requests patent thumbnailHandling address translation requests
A memory management unit comprises an interface for receiving an address translation request from a device, the address translation request specifying a virtual request to be translated. Translation circuitry translates the virtual address into an intermediate address different from a physical address directly specifying a memory location.
Arm Limited


 Memory management patent thumbnailMemory management
A method of operation of a host data processing system which provides a virtual operating environment for one or more guest data processing systems comprises: initiating a transaction for translation of a guest system memory address to a host system physical address in response to a transaction request from a device overseen by a guest system for access to system memory at that guest system memory address; storing identification information relating to that transaction including at least data identifying device which requested the transaction; detecting a translation error condition in respect of that transaction; and handling a detected error condition by: (i) providing information indicative of the translation error condition to the guest system overseeing the device which requested the transaction; (ii) receiving a command from the guest system in respect of that transaction, the command from the guest system comprising information identifying the device which requested the transaction; and (iii) validating the received command for execution, by comparing the stored identification information for that transaction with at least the identity of the device identified by the command.. .
Arm Limited


 Memory management patent thumbnailMemory management
A method of operation of a host data processing system which provides a virtual operating environment for one or more guest data processing systems comprises: initiating a transaction for translation of a guest system memory address to a host system physical address in response to a transaction request from a device overseen by a guest system for access to system memory according to that guest system memory address; storing identification information relating to each transaction including at least data identifying the device which requested the transaction; for a stalled transaction, being a transaction incurring an error condition which is potentially resolvable by the guest system overseeing the device which requested the transaction: (i) storing identification information relating to that transaction including at least data identifying the device which requested the transaction; (ii) providing information indicative of the translation error condition to the guest system overseeing the device which requested the transaction; and (iii) deferring continued handling of the stalled transaction until a subsequent command is received from that guest system relating to the stalled transaction; detecting initiation of a closure process relating to a guest system; and in response to initiation of the closure process, initiating cancellation of any currently stalled transactions for devices overseen by that guest system for which a command has not yet been received from that guest system.. .
Arm Limited


 Systems and methods for implementing power collapse in a memory patent thumbnailSystems and methods for implementing power collapse in a memory
A power management system for stack memory thread tasks according to some examples of the disclosure may include a non-collapsible memory region, a collapsible memory region configured below the non-collapsible memory region, a memory management unit in communication with the non-collapsible memory region and the collapsible memory region, the memory management unit operable to allocate a portion of the non-collapsible memory region and a portion of the collapsible memory region to a thread task upon initialization of the thread task and power down the portion of the collapsible memory region allocated to the thread task upon receiving a power down command.. .
Qualcomm Incorporated


 Efficient memory management system for computers supporting virtual machines patent thumbnailEfficient memory management system for computers supporting virtual machines
The translation of virtual guest addresses to host physical addresses in a virtualized computer system provides a compound page table that may simultaneously support nested-paging and shadow-paging for different memory regions. Memory regions with stable address mapping, for example, holding program code, may be treated using shadow-paging while memory regions with dynamic address mapping, for example, variable storage, may be treated using nested-paging thereby obtaining the benefits of both techniques..
Wisconsin Alumni Research Foundation


 Role based cache coherence bus traffic control patent thumbnailRole based cache coherence bus traffic control
A method for controlling cache snoop and/or invalidate coherence traffic for specific caches based on transaction attributes is described. A memory management unit (mmu) determines one or more transaction attributes for a cache coherence transaction from a requesting processor.
Qualcomm Incorporated


 Memory management system and method patent thumbnailMemory management system and method
A memory system and method of operating the same is described, where the memory system is used to store data in a raided manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received.
Violin Memory Inc:


Method and system for contiguous harq memory management with memory splitting


Apparatuses (including user equipment (ue) and modem chips for ues), systems, and methods for ue downlink hybrid automatic repeat request (harq) buffer memory management are described. In one method, the entire ue dl harq buffer memory space is pre-partitioned according to the number and capacities of the ue's active carrier components.
Samsung Electronics Co., Ltd.


Parallel garbage collection implemented in hardware


Embodiments of the invention provide a method and system for dynamic memory management implemented in hardware. In an embodiment, the method comprises storing objects in a plurality of heaps, and operating a hardware garbage collector to free heap space.
International Business Machines Corporation


Bifurcated memory management for memory elements


Bifurcated memory management for memory elements techniques are disclosed. In one aspect, a memory element includes a self-managed portion and a portion that is managed by a remote host.
Qualcomm Incorporated


Mechanism for tracking tainted data


The disclosure relates in some aspects to protecting systems and data from maliciously caused destruction. Data integrity is maintained by monitoring data to detect and prevent potential attacks.
Qualcomm Incorporated


Memory management method, memory control circuit unit and memory storage apparatus


The present disclosure provides a memory management method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes physical programming units, each of which includes multiple bits.
Phison Electronics Corp.


Dynamic code generation and memory management for component object model data constructs


Dynamic code generation and memory management techniques are provided for component object model (com) objects with corresponding representations in script code and native code. A browser component can receive script code including the code representing the com object and a marshaling component is provided that marshals, based on a request for native code representing the com object, the code representing the com object to the native code based on a pre-constructed intermediate data structure.
Microsoft Technology Licensing, Llc


Techniques for mapping device addresses to physical memory addresses


A data processing system includes a main storage, an input/output memory management unit (iommu) coupled to the main storage, a peripheral component interconnect (pci) device coupled to the iommu, and a mapper. The system is configured to allocate an amount of physical memory in the main storage and the iommu is configured to provide access to the main storage and to map a pci address from the pci device to a physical memory address within the main storage.
International Business Machines Corporation


Memory management method, memory control circuit unit and memory storage apparatus


A memory management method for a rewritable non-volatile memory module is provided. The rewritable non-volatile memory module has a plurality of devices.
Phison Electronics Corp.


Object memory fabric performance acceleration


Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. Embodiments described herein can provide transparent and dynamic performance acceleration, especially with big data or other memory intensive applications, by reducing or eliminating overhead typically associated with memory management, storage management, networking, and data directories.
Ultrata Llc


Cache operations for memory management


In accordance with the present description, cache operations for a memory-sided cache in front of a backing memory such as a byte-addressable non-volatile memory, include combining at least two of a first operation, a second operation and a third operation, wherein the first operation includes evicting victim cache entries from the cache memory in accordance with a replacement policy which is biased to evict cache entries having clean cache lines over evicting cache entries having dirty cache lines. The second operation includes evicting victim cache entries from the primary cache memory to a victim cache memory of the cache memory, and the third operation includes translating memory location addresses to shuffle and spread the memory location addresses within an address range of the backing memory.

Memory management in secure enclaves


Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit.
Intel Corporation


Moving picture coding apparatus and moving picture decoding apparatus


A video encoder (70) for coding moving pictures comprising a buffer (16c) with a plurality of memory areas capable of storing frames composed of top fields and bottom fields, a motion estimation unit (19) operable to code, field by field, inputted pictures performing moving estimation and moving compensation by referring, field by field, to the picture data stored in a memory area, a motion compensation unit (16d), a subtractor (11), a transformation unit (13) and a quantization unit (14), a memory management unit (71) operable to manage, frame by frame, a plurality of memory areas, an inverse quantization unit (16a) and inverse discrete cosine transform unit (16b) operable to decode picture data in coded fields and store the picture data in the decoded field in any of the plurality of memory areas under the management by the memory management unit (71).. .
Godo Kaisha Ip Bridge 1


Apparatus and managing buffer having three states on the basis of flash memory


The present invention relates to an apparatus and a method for managing a buffer having three states on the basis of a flash memory and, more specifically, to an apparatus and a method for improving the performance of a database management system (dbms) on the basis of the flash memory and a use life span of a storage device by reducing a writing operation for a flash memory device in which the writing operation is very slow in comparison with a reading operation, through an efficient buffer managing method and a new index node split policy. To this end, the buffer management device having three states on the basis of the flash memory according to an embodiment of the present invention comprises: a buffer memory unit; a list management unit; a buffer memory management unit; and a log buffer unit..
Ajou University Industry-academic Cooperation Foundation


Systems and methods for choosing a memory block for the storage of data based on a frequency with which the data is updated


Systems and methods for choosing a memory block for the storage of data based on a frequency with which data is updated are disclosed. In one implementation, a memory management module of a non-volatile memory system receives a request to open a free memory block for the storage of data.

Memory management model and interface for new applications


A memory management system is described herein that receives information from applications describing how memory is being used and that allows an application host to exert more control over application requests for using memory. The system provides an application memory management application-programming interface (api) that allows the application to specify more information about memory allocations that is helpful for managing memory later.

Memory management in presence of asymmetrical memory transfer cost


A computer-implemented method includes assigning a threshold value to a memory consumer and assigning a bias value to the threshold value. The ability to free memory of the consumer by the consumer is monitored.

Method and memory management


One or more circuits of a device may comprise a memory. A first portion of a first block of the memory may store program code and/or program data, a second portion of the first block may store an index associated with a second block of the memory, and a third portion of the first block may store an indication of a write status of the first portion.

Memory management method, memory storage device and memory controlling circuit unit


A memory management method, a memory storage device and a memory controlling circuit unit are provided. The method includes: programming data into a plurality of memory cells of a rewritable non-volatile memory module; determining whether a storage state of the data conforms with a first condition or a second condition based on a default bias range and a threshold voltage distribution of the memory cells storing the data; performing a first operation if the storage state of the data conforms with the first condition; and performing a second operation if the storage state of the data conforms with the second condition.

Memory block cycling based on memory wear or data retention


A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (dr), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells.

Dynamically compensating for degradation of a non-volatile memory device


Apparatus, systems, and methods to implement dynamic memory management in nonvolatile memory devices are described. In one example, a controller comprises logic to monitor at least one performance parameter of a nonvolatile memory, determine when the at least one performance parameter passes a threshold which indicates a degradation in performance for the nonvolatile memory, and in response to the at least one performance parameter passing the threshold, to modify at least one operational attribute of the nonvolatile memory.

Predicting memory data loss based on temperature accelerated stress time


A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (dr), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells.

End of life prediction based on memory wear


A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (dr), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells.

Measuring memory wear and data retention individually based on cell voltage distributions


A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (dr), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells.

Mini-barcode reading module with flash memory management


A miniature barcode reading module for an electronic device minimizes the size of the memory of the processor die allowing the module to be used in small form factor electronic devices. The module may include an image sensor package operative to scan a barcode and a processor die coupled to the image sensor package.

Memory management supporting shared virtual memories with hybrid page table utilization and related machine readable medium


A memory management method includes: checking shared virtual memory (svm) support ability of at least one device participating in data access of a buffer; referring to a checking result to adaptively select an svm mode; and allocating the buffer in a physical memory region of a memory device, and configuring the buffer to operate in the selected svm mode.. .

Instruction and logic for flush-on-fail operation


A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (foc) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the foc instruction.

Instruction and logic for page table walk change-bits


A processor includes a binary translator, a memory management unit, and a monitor unit. The binary translator includes logic to translate a region of code and to reorder translated instructions within the region to produce a transaction.

Removing read disturb signatures for memory analytics


A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (dr), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells.

End of life prediction to reduce retention triggered operations


A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (dr), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells.

Failed bit count memory analytics


A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (dr), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells.

Information processing apparatus and memory management method


Each of a plurality of, as many as three or more, processes is executed by one of a first virtual machine and a second virtual machine, and each of the first and second virtual machines executes at least one of the processes. At the execution of each of the processes, a virtual memory unit corresponding to the process is referred to.

Dynamic programming adjustments in memory for non-critical or low power mode tasks


A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (dr), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells.

Checkpointing module and storing checkpoints


A checkpointing module, a method for storing checkpoints and a microserver including a checkpointing module for storing checkpoints are proposed. The checkpointing module includes an interconnect interface configured to receive checkpoints from at least one compute module, one or more non-volatile random access memory devices configured to store the received checkpoints, a memory management entity configured to assign storage locations for the received checkpoints in the one or more non-volatile random access memory devices, and a memory controller configured to store the received checkpoints at the assigned storage locations..

Trade-off adjustments of memory parameters based on memory wear or data retention


A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (dr), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells.

Dynamic programming adjustments based on memory wear, health, and endurance


A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (dr), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells.

Instruction and logic for managing cumulative system bandwidth through dynamic request partitioning


A processor includes an execution unit, a memory subsystem, and a memory management unit (mmu). The mmu includes logic to evaluate a first bandwidth usage of the memory subsystem and logic to evaluate a second bandwidth usage between the processor and a memory.

Techniques for changing management modes of multilevel memory hierarchy


A processor modifies memory management mode for a range of memory locations of a multilevel memory hierarchy based on changes in an application phase of an application executing at a processor. The processor monitors the application phase (e.g.,.

Embedded device and memory management method thereof


An embedded device and a memory management method of the embedded device are provided. The embedded device includes a system memory and hardware memory.
Mstar Semiconductor, Inc.


Hierarchy memory management


In one embodiment, a storage system comprises: a first type interface being operable to communicate with a server using a remote memory access; a second type interface being operable to communicate with the server using a block i/o (input/output) access; a memory; and a controller being operable to manage (1) a first portion of storage areas of the memory to allocate for storing data, which is to be stored in a physical address space managed by an operating system on the server and which is sent from the server via the first type interface, and (2) a second portion of the storage areas of the memory to allocate for caching data, which is sent from the server to a logical volume of the storage system via the second type interface and which is to be stored in a storage device of the storage system corresponding to the logical volume.. .
Hitachi, Ltd.


Secondary cpu mmu initialization using page fault exception


In a computer system with multiple central processing units (cpus), initialization of a memory management unit (mmu) for a secondary cpu is performed using an exception generated by the mmu. In general, this technique leverages the exception handling features of the secondary cpu to switch the cpu from executing secondary cpu initialization code with the mmu “off” to executing secondary cpu initialization code with the mmu “on.” advantageously, in contrast to conventional techniques for mmu initialization, this exception-based technique does not require identity mapping of the secondary cpu initialization code to ensure proper execution of the secondary cpu initialization code..
Vmware, Inc.


System and ballooning wth assigned devices


A system and method for ballooning with assigned devices includes inflating a memory balloon, determining whether a first memory page is locked based on information associated with the first memory page, when the first memory page is locked unlocking the first memory page and removing first memory addresses associated with the first memory page from management by an input/output memory management unit (iommu), and reallocating the first memory page. The first memory page is associated with a first assigned device..
Red Hat Israel, Ltd.


Power saving multi-width processor core


A single core, multi-width merged architecture processor using industry standard instructions to provide power savings and higher performance at lower clock rates. The processor core has two separate decode blocks that share internal memory work space, memory management, and i/o processing.

Memory management of a device accessing applications


Various embodiments of systems and methods to provide memory management of a device accessing applications are described herein. In one aspect, a request is received to access an application on a device.

Memory management in graphics and compute application programming interfaces


Methods are provided for creating objects in a way that permits an api client to explicitly participate in memory management for an object created using the api. Methods for managing data object memory include requesting memory requirements for an object using an api and expressly allocating a memory location for the object based on the memory requirements.
Advanced Micro Devices, Inc.


Method and memory management


One or more circuits of a device may comprise a memory. A first portion of a first block of the memory may store program code and/or program data, a second portion of the first block may store an index associated with a second block of the memory, and a third portion of the first block may store an indication of a write status of the first portion.
Blackbird Technology Holdings, Inc.


Memory management


memory management is provided within a data processing system 2 which includes a memory protection unit 8 and defines memory regions within the memory address space which extend between base addresses and limit addresses and have respective attributes associated therewith. When a hit occurs within a memory region which is a valid hit, then block data is generated comprising a mask value and a tag value (derived from the original query address) which may then be used to identify subsequent hits within at least a portion of that region using a bitwise and.
Arm Limited


Method and memory management


A method and apparatus of memory management are disclosed. Pooling of at least one memory to generate a memory pool, dividing the memory pool to generate at least one memory space, and allocating a respective memory space to a respective cpu in a one-to-one correspondence manner are performed.
Alibaba Group Holding Limited


Memory management schemes for non-volatile memory devices


A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory.
Apple Inc.


Multiple memory management units


In an embodiment, interfacing a pipeline with two or more interfaces in a hardware processor includes providing a single pipeline in a hardware processor. The single pipeline presents at least two visible units.
Cavium, Inc.


Caching tlb translations using a unified page table walker cache


A core executes memory instructions. A memory management unit (mmu) coupled to the core includes a first cache that stores a plurality of final mappings of a hierarchical page table, a page table walker that traverses levels of the page table to provide intermediate results associated with respective levels for determining the final mappings, and a second cache that stores a limited number of intermediate results provided by the page table walker.
Cavium, Inc.


Instruction ordering for in-progress operations


Execution of the memory instructions is managed using memory management circuitry including a first cache that stores a plurality of the mappings in the page table, and a second cache that stores entries based on virtual addresses. The memory management circuitry executes operations from the one or more modules, including, in response to a first operation that invalidates at least a first virtual address, selectively ordering each of a plurality of in progress operations that were in progress when the first operation was received by the memory management circuitry, wherein a position in the ordering of a particular in progress operation depends on either or both of: (1) which of one or more modules initiated the particular in progress operation, or (2) whether or not the particular in progress operation provides results to the first cache or second cache..
Cavium, Inc.


Memory management techniques


memory management techniques that permit an executing process to store content in memory and later retrieve that content from the memory, but that also permit a memory manager to discard that content to address memory pressure. A process executing on a computing device may notify a memory manager of the computing device that first memory space allocated to the process contains first content that is available for discard.
Microsoft Technology Licensing, Llc


Information processing device, information procesing method, and program


An information processing device including an nv memory that is a non-volatile recording medium, a file system unit that manages one or more files stored in the nv memory, and a memory management unit that allocates one or more areas of the nv memory, that are ready to be used by the file system unit to store a file, to a running process in response to a request from the running process. The file system unit accesses areas of the nv memory storing unused area management data sets for managing unused areas of the nv memory.
Fixstars Corporation


Memory management for graphics processing unit workloads


A method, a device, and a non-transitory computer readable medium for performing memory management in a graphics processing unit are presented. Hints about the memory usage of an application are provided to a page manager.
Advanced Micro Devices, Inc.


Memory system and memory management method thereof


A memory system include a memory device including a plurality of blocks, each of the blocks having a plurality of pages, and a controller suitable for determining valid pages from among the plurality of pages based on data temperature, and performing a garbage collection process based on a number of valid pages and data temperature of the valid pages.. .
Sk Hynix Memory Solutions Inc.


Memory management in event recording systems


A vehicle event recorder is provided that includes a camera for capturing a video as discrete image frames, and that further includes a managed loop memory and a management system for generating a virtual ‘timeline dilation’ effect. To overcome size limits in the buffer memory of the video event recorder, the maximum time extension of a video series is increased by enabling a reduction in temporal resolution in exchange for an increase in the temporal extension.
Smartdrive Systems, Inc.


Asymmetric memory migration in hybrid main memory


Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, the memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory.
Virident Systems Inc.


Memory protection key architecture with independent user and supervisor domains


A processing system includes a processing core to execute a task and a memory management unit, coupled to the core. The memory management unit includes a storage unit to store a page table entry including one or more identifiers of memory frames, a protection key, and an access mode bit indicating whether the one or more memory frames are accessible according to a user mode or according to a supervisor mode, a first permission register including a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the user mode, and a second permission register storing a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the supervisor mode..

System and improving memory usage in virtual machines


An apparatus includes at least one processor executing a method for managing memory among a plurality of concurrently-running virtual machines, and a non-transitory memory device that stores a set of computer readable instructions for implementing and executing said memory management method. A memory optimization mechanism can reduce a memory usage of a virtual machine at a cost of increasing a central processing unit (cpu) usage.

Hardware-assisted memory compression management using page filter and system mmu


Provided are methods and systems for managing memory using a hardware-based page filter designed to distinguish between active and inactive pages (“hot” and “cold” pages, respectively) so that inactive pages can be compressed prior to the occurrence of a page fault. The methods and systems are designed to achieve, among other things, lower cost, longer battery life, and faster user response.
Google Inc.


Memory management apparatus and method


A memory management apparatus and method are provided herein. The memory management apparatus includes a memory management list generation unit, a memory allocation unit, and a memory release unit.
Electronics And Telecommunications Research Institute


Hardware automation for memory management


A storage module may include a controller that has hardware path that includes a plurality of hardware modules configured to perform a plurality of processes associated with execution of a host request. The storage module may also include a firmware module having a processor that executes firmware to perform at least some of the plurality of processes performed by the hardware modules.
Sandisk Technologies Inc.


Automatic analysis of issues concerning automatic memory management


Systems and methods are provided to automatically analyze performance of an automatic memory management system. One example embodiment involves automatically gathering, using at least one processor of the server, garbage collection information associated with the garbage collection process and storing the garbage collection information in a garbage collection output file of a file system.

System and managing the allocating and freeing of objects in a multi-threaded system


A memory management system for managing objects which represent memory in a multi-threaded operating system extracts the id of the home free-list from the object header to determine whether the object is remote and adds the object to a remote object list if the object is determined to be remote. The memory management system determines whether the number of objects on the remote object list exceeds a threshold.
Software Ag


Information processing device, information procesing method, and program


There is provided an information processing device comprising an nv memory that is a non-volatile recording medium, a file system unit that manages one or more files stored in the nv memory, and a memory management unit that secures one or more areas of the nv memory that are ready to be used by the file system unit to store a file, and allocates the secured one or more areas to a running process in response to a request from the running process. According to the information processing device, when the nv memory is used both as a main memory and a storage, inconsistencies in the file system caused by an abnormal termination of the system are reduced..
Fixstars Corporation


Multi-source address translation service (ats) with a single ats resource


Disclosed is an address translation system. The apparatus includes a memory management unit (mmu) that is operable to receive a translation request for an original address and translate the original address to a translated address as a second-level address translation service (ats).

Memory management component


A memory management component arranged to receive memory access transactions and provide memory management functionality therefor, and a method of providing memory management functionality within a processing system are disclosed. The memory management component comprises a first memory management module arranged to provide memory management functionality for received memory access transactions in accordance with a paging memory management scheme, and at least one further memory management module arranged to provide memory management functionality for received memory access transactions in accordance with an address range memory management scheme..
Freescale Semiconductor, Inc.


Descriptor ring management


A data processing system utilising a descriptor ring 24 to facilitate communication between one or more general purpose processors 4, 6 and one or more devices 20, 22 employs a system memory management unit 18 for managing access by the devices 20, 22 to a main memory 16. The system memory management unit 18 uses address translation data for translating memory addresses generated by the devices 20, 22 into addresses supplied to the main memory 16.
Arm Limited


Memory management for video decoding


Techniques and tools described herein help manage memory efficiently during video decoding, especially when multiple video clips are concurrently decoded. For example, with clip-adaptive memory usage, a decoder determines first memory usage settings expected to be sufficient for decoding of a video clip.
Microsoft Technology Licensing, Llc


Embedded processor with virtualized security controls using guest identifications, a common kernel address space and operational permissions


A method includes assigning unique guest identifications to different guests, specifying an address region and permissions for the different guests and controlling a guest jump from one physical memory segment to a second physical memory segment through operational permissions defined in a root memory management unit that supports guest isolation and protection.. .
Arm Finance Overseas Limited


Memory management method, apparatus, and system


A memory management method implemented by a requesting node includes sending first indication information used for indicating a length of memory required by the requesting node and receiving second indication information used for indicating first remote memory provided to the requesting node by a target contributing node in at least one contributing node that can provide remote memory. The method also includes determining, from available virtual addresses, a first virtual address corresponding to the first remote memory, and sending a first data read/write instruction for the first data when first data whose pointer is within a range of the first virtual address needs to be read/written, where the first data read/write instruction includes third indication information, and the third indication information is used for indicating storage space, for storing the first data, in the first remote memory..
Huawei Technologies Co., Ltd.


Systems and methods for object classification, object detection and memory management


A method for object classification by an electronic device is described. The method includes obtaining an image frame that includes an object.
Qualcomm Incorporated


Method for controlling memory device to achieve more power saving and related apparatus thereof


A memory management method includes: performing a first-level collection operation upon first storage units in a memory pool allocated in a memory device; and after the first storage units are processed by the first-level collection operation, performing a second-level collection operation upon second storage units in the memory pool allocated in the memory device, wherein one of the first-level collection operation and the second-level collection operation is a page-level collection operation, and another of the first-level collection operation and the second-level collection operation is a bank-level collection operation.. .
Mediatek Inc.


Memory management device


A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory..
Kabushiki Kaisha Toshiba


Memory management device and method


According to one embodiment, a device includes a determination unit, compression unit, selecting unit, write updating unit, writing unit. The determination unit determines whether to compress write data based on specific information.
Kabushiki Kaisha Toshiba


Temperature accelerated stress time


A memory system or flash card may be exposed to elapsed time or increased temperature conditions which may degrade the memory. For example, extended time periods or high temperature conditions may hinder data retention in a memory device.
Sandisk Technologies Inc.


Storage devices and methods for optimizing use of storage devices based on storage device parsing of file system metadata in host write operations


The subject matter described herein includes processing file system metadata in host write requests to determine information about future host write operations. The information regarding future host write operations can be used by a device controller to prepare the non-volatile memory for the future host write operations.
Sandisk Technologies Inc.


Data management scheme in virtualized hyperscale environments


According to one general aspect, a memory management unit (mmu) may be configured to interface with a heterogeneous memory system that comprises a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with performance characteristic(s).

Memory management method, memory storage device and memory controlling circuit unit


A memory management method, a memory storage device and a memory controlling circuit unit are provided. The method includes: defining a first data management rule for a first type physical unit and a second data management rule for a second type physical unit, and a data density of the first type physical unit is lower than the data density of the second type physical unit; if a first physical unit belongs to the first type physical unit, managing the first physical unit according to the first data management rule to make the data stored in the first physical unit conforming to a first reliability level; and if the first physical unit belongs to the second type physical unit, managing the first physical unit according to the second data management rule to make the data stored in the first physical unit conforming to a second reliability level..
Phison Electronics Corp.


Memory management of digital audio data


A system, method and computer-readable code for the management of digital media on a device with memory and storage restrictions. As with any device, memory and storage is limited.
Audio Pod Inc.


Computer security systems and methods using hardware-accelerated access to guest memory from below the operating system


Described systems and methods allow computer security software to access a memory of a host system with improved efficiency. A processor and a memory management unit (mmu) of the host system may be configured to perform memory access operations (read/write) in a target memory context, which may differ from the implicit memory context of the currently executing process.
Bitdefender Ipr Management Ltd.


Intelligent computer memory management


A plurality of memory allocators are initialized within a computing system. At least a first memory allocator and a second memory allocator in the plurality of memory allocators are each customizable to efficiently handle a set of different memory request size distributions.
International Business Machines Corporation


Method and system for generating object code to facilitate predictive memory retrieval


A method and system are described for generating reference tables in object code which specify the addresses of branches, routines called, and data references used by routines in the code. In a suitably equipped processing system, the reference tables can be passed to a memory management processor which can open the appropriate memory pages to expedite the retrieval of data referenced in the execution pipeline.
Micron Technology, Inc.


System and multistage processing in a memory storage subsystem


Embodiments of this disclosure relate to improving solid-state non-volatile memory management. Embodiments improve the management of solid-state non-volatile memory by providing an execution manager responsible for controlling the timing of providing a request to a memory unit for execution.
Western Digital Technologies, Inc.


Method and memory management


One or more circuits of a device may comprise a memory. A first portion of a first block of the memory may store program code and/or program data, a second portion of the first block may store an index associated with a second block of the memory, and a third portion of the first block may store an indication of a write status of the first portion.
Blackbird Technology Holdings, Inc.


Memory management techniques and related systems for block-based convolution


A processor can be associated with a memory for storing convolution data. A plurality of m filters from a corresponding plurality of m input channels to a selected one output channel can be provided, wherein each filter can be represented by a corresponding index, m.

Memory management for systems for generating 3-dimensional computer images


A memory management system for generating 3-dimensional computer images is provided. The memory management system includes a device for subdividing an image into a plurality of rectangular areas, a memory for storing object data pertaining to objects in the image which fall in each rectangular area, a device for storing the object data in the memory, a device for deriving image data and shading data for each rectangular area from the object data, a device for supplying object data for each rectangular area from the respective portion of the memory and, if the rectangular area contains objects also falling in at least one other rectangular area, also from the global list, to the deriving device, and a device for storing the image data and shading data derived by the deriving device for display.
Imagination Technologies Limited


Technique for synchronizing iommu memory de-registration and incoming i/o data


A technique synchronizes de-registration of registered memory and incoming input/output (i/o) data received from an i/0 device for storage in a memory of a computer system. Registration and de-registration of the memory with an i/o memory management unit (iommu) are illustratively performed by an i/o device driver of the computer system in anticipation of (or in response to) an i/o request to store the incoming i/o data in buffers of the memory.
Netapp, Inc.


Off-heap direct-memory data stores, methods of creating and/or managing off-heap direct-memory data stores, and/or systems including off-heap direct-memory data store


Certain example embodiments relate to a highly-concurrent, predictable, fast, self-managed, in-process space for storing data that is hidden away from the garbage collector and its related pauses. More particularly, certain example embodiments relate to improved memory management techniques for computer systems that leverage an off-heap direct-memory data store that is massively scalable and highly efficient.
Software Ag Usa, Inc.


On-demand shareability conversion in a heterogeneous shared virtual memory


The aspects include systems and methods of managing virtual memory page shareability. A processor or memory management unit may set in a page table an indication that a virtual memory page is not shareable with an outer domain processor.
Qualcomm Incorporated


Systems and/or methods for enabling storage tier selection and usage at a granular level


Certain example embodiments relate to memory management techniques that enable users to “pin” elements to particular storage tiers (e.g., ram, ssd, hdd, tape, or the like). Once pinned, elements are not moved from tier-to-tier during application execution.
Software Ag Usa, Inc.


Method and system for processing memory


A method and system for memory management is disclosed. The disclosed method and system can prevent performance degradation due to automatic garbage collection associated with memory allocation for image processing.
Quram Co., Ltd.




Memory Management topics:
  • Memory Management
  • Virtual Machine
  • Storage Device
  • Volatile Memory
  • Data Processing
  • Logical Unit
  • Virtual Memory
  • Computer System
  • Dynamic Data
  • Base Memory
  • Database Management System
  • Data Storage
  • Defragment
  • Compatibility
  • Object Code


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