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Memory Management patents



      
           
This page is updated frequently with new Memory Management-related patent applications. Subscribe to the Memory Management RSS feed to automatically get the update: related Memory RSS feeds. RSS updates for this page: Memory Management RSS RSS


Method and system for implementing multi-stage translation of virtual addresses

Nvidia

Method and system for implementing multi-stage translation of virtual addresses

Method and system for method for tracking transactions associated with a system memory management unit of a portable…

Qualcomm

Method and system for method for tracking transactions associated with a system memory management unit of a portable…

Method and system for method for tracking transactions associated with a system memory management unit of a portable…

International Business Machines

Implicit i/o send on cache operations


Date/App# patent app List of recent Memory Management-related patents
07/23/15
20150208075 
 Memory management of motion vectors in high efficiency video coding motion vector prediction patent thumbnailMemory management of motion vectors in high efficiency video coding motion vector prediction
In one embodiment of the present invention, a high efficiency video coding codec optimizes the memory resources used during motion vector (mv) prediction. As the codec processes block of pixels, known as coding units (cus), the codec performs read and write operations on a fixed-sized neighbor union buffer representing the mvs associated with processed cus.
Nvidia Corporation


07/16/15
20150199280 
 Method and system for implementing multi-stage translation of virtual addresses patent thumbnailMethod and system for implementing multi-stage translation of virtual addresses
A system and method are provided for implementing multi-stage translation of virtual addresses. The method includes the steps of receiving, at a first memory management unit, a memory request including a virtual address in a first address space, translating the virtual address to generate a second virtual address in a second address space, and transmitting a modified memory request including the second virtual address to a second memory management unit.
Nvidia Corporation


07/16/15
20150199279 
 Method and system for  tracking transactions associated with a system memory management unit of a portable computing device patent thumbnailMethod and system for tracking transactions associated with a system memory management unit of a portable computing device
A method and system for tracking transactions associated with a system memory management unit (“smmu”) includes receiving a plurality of memory requests from a plurality of processing elements and storing contents of each memory request in a transaction history buffer (“thb”). The contents of a memory request stored in the thb may comprise at least one of a security bit; a virtual machine identifier (“vmid”); a stream identifier (“sid”); a smmu context bank that was used; and whether or not the virtual address was present in the translation look-aside buffer.
Qualcomm Incorporated


07/16/15
20150199274 
 Implicit i/o send on cache operations patent thumbnailImplicit i/o send on cache operations
A computer system for implicit input-output send on cache operations of a central processing unit is provided. The computer system comprises an aggregation queue of a central processing unit, storing input-output data of the central processing unit, wherein the aggregation queue transmits the input-output data to an input-output adaptor, and wherein the input-output data is transmitted in parallel with operations of the central processing unit.
International Business Machines Corporation


07/16/15
20150199273 
 Implicit i/o send on cache operations patent thumbnailImplicit i/o send on cache operations
A method for implicit input-output send on cache operations of a central processing unit is provided. The method comprises an aggregation queue of a central processing unit, storing input-output data of the central processing unit, wherein the aggregation queue transmits the input-output data to an input-output adaptor, and wherein the input-output data is transmitted in parallel with operations of the central processing unit.
International Business Machines Corporation


07/09/15
20150194213 
 Hierarchical immutable content-addressable memory processor patent thumbnailHierarchical immutable content-addressable memory processor
Improved memory management is provided according to a hierarchical immutable content addressable memory processor (hicamp) architecture. In hicamp, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity.

07/09/15
20150193302 
 Selective ecc refresh for on die buffered non-volatile memory patent thumbnailSelective ecc refresh for on die buffered non-volatile memory
Apparatuses, systems, methods, and computer program products are disclosed for on die buffered non-volatile memory management. A method includes storing data in a first set of non-volatile memory cells.
Sandisk Technologies Inc.


07/09/15
20150193299 
 Selective copyback for on die buffered non-volatile memory patent thumbnailSelective copyback for on die buffered non-volatile memory
Apparatuses, systems, methods, and computer program products are disclosed for on die buffered non-volatile memory management. A method includes storing data in a first set of non-volatile memory cells.
Sandisk Technologies, Inc.


07/02/15
20150187435 
 Systems and methods for memory management in a dynamic translation computer system patent thumbnailSystems and methods for memory management in a dynamic translation computer system
Systems and methods for managing memory in a dynamic translation computer system are provided. Embodiments may include receiving an instruction packet and processing the instruction packet.
Unisys Corporation


07/02/15
20150186291 
 Systems and methods for memory management in a dynamic translation computer system patent thumbnailSystems and methods for memory management in a dynamic translation computer system
Systems and methods for managing memory in a dynamic translation computer system are provided. Embodiments may include receiving an instruction packet and processing the instruction packet.
Unisys Corporation


07/02/15
20150186059 

Memory management program, memory management method, and memory management device


A non-transitory computer-readable recording medium stores a memory management program that causes a computer to execute a process. The process includes detecting writing into a memory; and saving, in association with each other in a predetermined storage area, data before the writing which is stored in a data area of a write destination of the detected writing, and context information of a processor at a time of detecting the writing into the memory..
Fujitsu Limited


06/25/15
20150180504 

Method and compressing/decompressing data using floating point


Disclosed are a method and apparatus for compressing/decompressing data using floating points. As technology for compressing/decompressing data using floating points for efficient memory management, there are provided a method and apparatus for compressing/decompressing data using floating points, in which a log table is used to compress/decompress data, whereby not only data loss caused by compression/decompression can be minimized, but also degradation of performance can be prevented through a floating point representation even though the same number of bits are used for compression..
Fci Inc


06/25/15
20150178242 

System and a a remote direct memory access over converged ethernet


A method and a system embodying the method for receiving a remote direct memory access packet comprising an opaque data, a virtual address, and a payload at a virtual network interface card that generated the opaque data; reconstructing a stream identifier by separating the opaque data into an encrypted stream identifier and a first digest; decrypting the encrypted stream identifier; verifying the decrypted stream identifier using the first digest; providing the verified stream identifier to a system memory management unit; and mapping the virtual address and the provided stream identifier by the system memory management unit to a physical address, is disclosed.. .
Cavium, Inc.


06/25/15
20150178198 

Hypervisor managing memory addressed above four gigabytes


Approaches for performing memory management by a hypervisor. A host operating system and a hypervisor are executed on a device.
Bromium, Inc.


06/25/15
20150178190 

Detecting hot spots through flash memory management table snapshots


Decisions about how to correlate logical address to physical addresses in a flash memory (or other non-volatile random access memory) is based at least in part upon how frequently a logical address is accessed over time. Accordingly, software tracks accesses, by logical address, to the stored data using a flash memory metadata structure, and calculates a frequency-of-access value for each logical address of the set of logical addresses corresponding to the relative frequency with which the corresponding logical address is accessed, based, at least in part, on the flash memory metadata structure.
International Business Machines Corporation


06/25/15
20150178157 

Memory management system and method


A memory system and method of operating the same is described, where the memory system is used to store data in a raided manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received.
Violin Memory Inc.


06/25/15
20150178010 

Memory management based on usage specifications


A method is provided for managing a memory device including a plurality of physical memory segments. A logical memory space is classified into a plurality of classifications based on usage specifications.
Macronix International Co., Ltd.


06/18/15
20150172725 

Moving picture coding apparatus and moving picture decoding apparatus


A video encoder (70) for coding moving pictures comprising a buffer (16c) with a plurality of memory areas capable of storing frames composed of top fields and bottom fields, a motion estimation unit (19) operable to code, field by field, inputted pictures performing moving estimation and moving compensation by referring, field by field, to the picture data stored in a memory area, a motion compensation unit (16d), a subtractor (11), a transformation unit (13) and a quantization unit (14), a memory management unit (71) operable to manage, frame by frame, a plurality of memory areas, an inverse quantization unit (16a) and inverse discrete cosine transform unit (16b) operable to decode picture data in coded fields and store the picture data in the decoded field in any of the plurality of memory areas under the management by the memory management unit (71).. .
Panasonic Intellectual Property Corporation Of America


06/18/15
20150172700 

Moving picture coding apparatus and moving picture decoding apparatus


A video encoder (70) for coding moving pictures comprising a buffer (16c) with a plurality of memory areas capable of storing frames composed of top fields and bottom fields, a motion estimation unit (19) operable to code, field by field, inputted pictures performing moving estimation and moving compensation by referring, field by field, to the picture data stored in a memory area, a motion compensation unit (16d), a subtractor (11), a transformation unit (13) and a quantization unit (14), a memory management unit (71) operable to manage, frame by frame, a plurality of memory areas, an inverse quantization unit (16a) and inverse discrete cosine transform unit (16b) operable to decode picture data in coded fields and store the picture data in the decoded field in any of the plurality of memory areas under the management by the memory management unit (71).. .
Panasonic Intellectual Property Corporation Of America


06/18/15
20150172686 

Moving picture coding apparatus and moving picture decoding apparatus


A video encoder (70) for coding moving pictures comprising a buffer (16c) with a plurality of memory areas capable of storing frames composed of top fields and bottom fields, a motion estimation unit (19) operable to code, field by field, inputted pictures performing moving estimation and moving compensation by referring, field by field, to the picture data stored in a memory area, a motion compensation unit (16d), a subtractor (11), a transformation unit (13) and a quantization unit (14), a memory management unit (71) operable to manage, frame by frame, a plurality of memory areas, an inverse quantization unit (16a) and inverse discrete cosine transform unit (16b) operable to decode picture data in coded fields and store the picture data in the decoded field in any of the plurality of memory areas under the management by the memory management unit (71).. .
Panasonic Intellectual Property Corporation Of America


06/18/15
20150172685 

Moving picture coding apparatus and moving picture decoding apparatus


A video encoder (70) for coding moving pictures comprising a buffer (16c) with a plurality of memory areas capable of storing frames composed of top fields and bottom fields, a motion estimation unit (19) operable to code, field by field, inputted pictures performing moving estimation and moving compensation by referring, field by field, to the picture data stored in a memory area, a motion compensation unit (16d), a subtractor (11), a transformation unit (13) and a quantization unit (14), a memory management unit (71) operable to manage, frame by frame, a plurality of memory areas, an inverse quantization unit (16a) and inverse discrete cosine transform unit (16b) operable to decode picture data in coded fields and store the picture data in the decoded field in any of the plurality of memory areas under the management by the memory management unit (71).. .
Panasonic Intellectual Property Corporation Of America


06/18/15
20150172684 

Moving picture coding apparatus and moving picture decoding apparatus


A video encoder (70) for coding moving pictures comprising a buffer (16c) with a plurality of memory areas capable of storing frames composed of top fields and bottom fields, a motion estimation unit (19) operable to code, field by field, inputted pictures performing moving estimation and moving compensation by referring, field by field, to the picture data stored in a memory area, a motion compensation unit (16d), a subtractor (11), a transformation unit (13) and a quantization unit (14), a memory management unit (71) operable to manage, frame by frame, a plurality of memory areas, an inverse quantization unit (16a) and inverse discrete cosine transform unit (16b) operable to decode picture data in coded fields and store the picture data in the decoded field in any of the plurality of memory areas under the management by the memory management unit (71).. .
Panasonic Intellectual Property Corporation Of America


06/18/15
20150169223 

Dynamic processor-memory revectoring architecture


A global navigation satellite system (gnss) includes an efficient memory sharing architecture that provides additional search capacity by, e.g., sharing a portion of gnss receiver processor memory with a general processor. A memory management unit dynamically revectors memory accesses in accordance with the various states of the gnss receiver processor and arranging the available memory as a shared memory bank that can be efficiently shared between the general processor and the gnss receiver processor.
Texas Instruments, Incorporated


06/11/15
20150161385 

Memory management parameters derived from system modeling


Optimized memory management settings may be derived from a mathematical model of an execution environment. The settings may be optimized for each application or workload, and the settings may be implemented per application, per process, or with other granularity.
Concurix Corporation


06/11/15
20150161057 

System and providing client-side address translation in a memory management system


Systems and methods are disclosed for providing memory address translation for a memory management system. One embodiment of such a system comprises a memory device and an application processor in communication via a system interconnect.
Qualcomm Incorporated


06/11/15
20150161042 

Memory management method, memory controlling circuit unit, and memory storage device


A memory management method, a memory controlling circuit unit and a memory storage device are provided. The method includes: configuring a plurality of super physical erasing units, wherein each of the super physical erasing units includes at least two physical erasing units.
Phison Electronics Corp.


06/11/15
20150160940 

Method for changing the software in the memory of an electronic control unit


A method for changing a software in the memory of an electronic control unit. A bypass routine is stored in the working memory of the electronic control unit, and the address of the bypass function is stored in a table.
Dspace Digital Signal Processing And Control Engineering Gmbh


06/11/15
20150160862 

Memory arrangement for implementation of high-throughput key-value stores


A circuit for processing data is described. The circuit comprises an input for receiving a request for implementing a key-value store data transaction; a plurality of memory interfaces associated with different memory types enabling access to a plurality of memory devices associated with a key-value store; and a memory management circuit controlling the routing of data by way of the plurality of memory interfaces based upon a data transfer criterion..
Xilinx, Inc.


06/11/15
20150160860 

Memory management using enlarged address space


A storage device comprises a storage unit having a first size, and a storage controller configured to control data transfer between the storage unit and a host in response to a request from the host, and further configured to convey size information of the storage unit to the host such that the host perceives the storage unit to have a second size different from the first size.. .
Samsung Electronics Co., Ltd.


06/04/15
20150154119 

Memory allocation and page address translation system and method


A memory allocation and page address translation system includes a buddy memory allocator, a plurality of guest page tables, a memory management unit and a buddy translation lookaside buffer. The buddy memory allocator is configured for allocating machine physical memory space to a virtual machine monitor and a plurality of virtual machines.
National Taiwan University


06/04/15
20150154068 

Memory device having address and command selectable capabilities


Subject matter disclosed herein relates to memory management, and more particularly to partitioning a memory based on memory attributes.. .
Micron Technology, Inc.


05/28/15
20150150145 

Method and system for fast permission changes for virtual addresses


A method for accessing shared memory, the method includes loading a private context id into a private context id register, where the first private context id enables a thread to access a private memory region only accessible by the thread. The method further includes receiving, from the thread, a first request to access a shared memory region, loading a shared context id into a shared context register, permitting, by a memory management unit (mmu), the thread to access the shared memory region using the shared context id, and receiving, from the thread, a second request to disable access to the shared memory region.
Oracle International Corporation


05/28/15
20150149742 

Memory unit and method


A memory unit and method are disclosed. The memory unit comprises: at least one controller interfaced with at least one corresponding persistent memory device operable to store files in accordance with a file system; and a file mapping unit operable, in response to a virtual file access request from a memory management unit of a processor, the virtual file access request having a virtual address within a virtual address space associated with one of the files identifying data to be accessed, to map the virtual address to a physical address of the data within the one of the files using pre-stored mapping information and to issue a physical access request having the physical address to access the data within the one of the files..
Swarm64 As


05/28/15
20150149711 

Cache decice and memory system


A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages.
Kabushiki Kaisha Toshiba


05/28/15
20150149703 

Apparatuses for securing program code stored in a non-volatile memory


An embodiment of an apparatus for securing program code stored in a non-volatile memory is introduced. A non-volatile memory contains a first region and a second region.
Nuvoton Technology Corporation


05/28/15
20150149446 

Circuitry for a computing system and computing system


Circuitry for a computing system includes a memory arrangement having at least one memory management unit and at least one processor. The at least one processor is arranged to issue a memory query to the memory management unit.
Freescale Semiconductor, Inc.


05/28/15
20150149155 

Methods and systems for applications for z-numbers


Specification covers new algorithms, methods, and systems for artificial intelligence, soft computing, and deep learning/recognition, e.g., image recognition (e.g., for action, gesture, emotion, expression, biometrics, fingerprint, facial, ocr (text), background, relationship, position, pattern, and object), large number of images (“big data”) analytics, machine learning, training schemes, crowd-sourcing (using experts or humans), feature space, clustering, classification, similarity measures, optimization, search engine, ranking, question-answering system, soft (fuzzy or unsharp) boundaries/impreciseness/ambiguities/fuzziness in language, natural language processing (nlp), computing-with-words (cww), parsing, machine translation, sound and speech recognition, video search and analysis (e.g. Tracking), image annotation, geometrical abstraction, image correction, semantic web, context analysis, data reliability (e.g., using z-number (e.g., “about 45 minutes; very sure”)), rules engine, control system, autonomous vehicle, self-diagnosis and self-repair robots, system diagnosis, medical diagnosis, biomedicine, data mining, event prediction, financial forecasting, economics, risk assessment, e-mail management, database management, indexing and join operation, memory management, and data compression..

05/21/15
20150143072 

Method in a memory management unit for managing address translations in two stages


A memory management unit (mmu) may manage address translations. The mmu may obtain a first intermediate physical address (ipa) based on a first virtual address (va) relating to a first memory access request.
Stmicroelectronics International N.v.


05/21/15
20150142908 

Computer device and memory management method thereof


A memory management method includes sharing a memory space of a memory component via a network through a host operating system, mounting the shared memory space via the network through a virtual machine, monitoring an memory utilization of a virtual memory of the virtual machine, and allocating a storage block to the virtual machine in a condition that the memory utilization of the virtual memory of the virtual machine is greater than an upper bound. As such, a capacity of the virtual memory of the virtual machine is increased..
Inventec (pudong) Technology Corporation


05/14/15
20150134887 

Data writing method, memory control circuit unit and memory storage apparatus


A data writing method for a rewritable non-volatile memory module having a plurality of physical erasing units, and a memory control circuit unit and the memory storage apparatus are provided. The method includes: grouping the physical erasing units into at least a data area and a spare area; configuring a plurality of logical units for mapping to the physical erasing units of the data area; and dynamically reserving a predetermined number of physical erasing units dedicating to write sequential data.

05/07/15
20150128147 

Modified jvm with multi-tenant application domains and memory management


A method and system for operating a modified java virtual machine (jvm) which is able to simultaneously host multiple java application programs, are disclosed. The jvm is modified to maintain a computer record of one or more application domains, each having one or more classes.
Waratek Limited A Corporation


05/07/15
20150127871 

Updated io memory management unit identity settings for dma remapping


Disclosed is a system and method for updating iommu (input output memory management unit) tables for remapping dma (direct memory access) range for a requested bus device when the device is active.. .
Lsi Corporation


04/30/15
20150121029 

Memory management with priority-based memory reclamation


A memory buffer with a set of one or more structures is created by a process of a first software program. The first memory buffer comprises a predetermined amount of memory.
International Business Machines Corporation


04/30/15
20150121024 

Operating a memory management controller


A memory management controller operatively coupled to a plurality of memory modules, the memory management controller including processing logic configured to: identify a plurality of memory tiers in the plurality of memory modules, each memory tier characterized by different operational characteristics; allocate a spare block of memory in each memory tier; identify a data characteristic for each of the one or more blocks of data in a plurality of memory tiers; migrate, in dependence upon the operational characteristics of each memory tier and the data characteristic for each of the one or more data blocks in the plurality of memory tiers, data in a first memory tier to the spare block of memory in a second memory tier; and migrate data in the second memory tier to the spare block of memory in the first memory tier.. .
Lenovo Enterprise Solutions (singapore) Ptw. Ltd.


04/30/15
20150121023 

Operating a memory management controller


A memory management controller operatively coupled to a plurality of memory modules, the memory management controller including processing logic configured to: identify a plurality of memory tiers in the plurality of memory modules, each memory tier characterized by different operational characteristics; allocate a spare block of memory in each memory tier; identify a data characteristic for each of the one or more blocks of data in a plurality of memory tiers; migrate, in dependence upon the operational characteristics of each memory tier and the data characteristic for each of the one or more data blocks in the plurality of memory tiers, data in a first memory tier to the spare block of memory in a second memory tier; and migrate data in the second memory tier to the spare block of memory in the first memory tier.. .
International Business Machines Corporation


04/23/15
20150113210 

Data storage flash memory management method and program


There is provided a data storage flash memory management method that does not require a management area and can reduce an access load. A data storage flash memory management method for storing k time-varying parameters (k is a positive integer) in a flash memory including j blocks (j is an even number not less than 2) as erase units is configured as follows.
Renesas Electronics Corporation


04/23/15
20150109314 

Memory management system and method


There is provided a method and apparatus for managing memory in a system for generating 3-dimensional computer images. The image is subdivided into a plurality of rectangular areas.
Imagination Technologies, Limited


04/16/15
20150106556 

Endurance translation layer (etl) and diversion of temp files for reduced flash wear of a super-endurance solid-state drive


A flash drive has increased endurance and longevity by reducing writes to flash. An endurance translation layer (etl) is created in a dram buffer and provides temporary storage to reduce flash wear.
Super Talent Electronics, Inc.


04/09/15
20150100818 

Back-off mechanism for a peripheral page request log


A system and method of managing requests from peripherals in a computer system are provided. In the system and method, an input/output memory management unit (iommu) receives a peripheral page request (ppr) from a peripheral.
Advanced Micro Devices, Inc.


04/09/15
20150100741 

Transactional memory management techniques


Techniques for improved transactional memory management are described. In one embodiment, for example, an apparatus may comprise a processor element, an execution component for execution by the processor element to concurrently execute a software transaction and a hardware transaction according to a transactional memory process, a tracking component for execution by the processor element to activate a global lock to indicate that the software transaction is undergoing execution, and a finalization component for execution by the processor element to commit the software transaction and deactivate the global lock when execution of the software transaction completes, the finalization component to abort the hardware transaction when the global lock is active when execution of the hardware transaction completes.

04/09/15
20150100708 

Methods and systems for moving and resizing i/o activity logs


A method of managing peripherals is performed in a device coupled to a processor in a computer system. For example, the method is performed in an input/output memory management unit (iommu) or a peripheral.
Advanced Micro Devices, Inc.


04/09/15
20150097847 

Managing memory regions to support sparse mappings


One embodiment of the present invention includes a memory management unit (mmu) that is configured to manage sparse mappings. The mmu processes requests to translate virtual addresses to physical addresses based on page table entries (ptes) that indicate a sparse status.
Nvidia Corporation


04/02/15
20150095611 

Method and processor for reducing code and latency of tlb maintenance operations in a configurable processor


A memory management unit (mmu) is disclosed for storing mappings between virtual addresses and physical addresses. The mmu includes a translation look-aside buffer (tlb) and a memory management unit controller.
Synopsys, Inc.


04/02/15
20150095610 

Multi-stage address translation for a computing device


Providing for address translation in a virtualized system environment is disclosed herein. By way of example, a memory management apparatus is provided that comprises a shared translation look-aside buffer (tlb) that includes a plurality of translation types, each supporting a plurality of page sizes, one or more processors, and a memory management controller configured to work with the one or more processors.
Applied Micro Circuits Corporation


04/02/15
20150095563 

Memory management


Apparatus, systems, and methods to manage memory operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to retrieve a global sequence number from a memory device, receive a read request for data stored in a logical block address in the memory device, retrieve a media sequence number from the logical block address in the memory device, and return a null response in lieu of the data stored in the logical block address when the media sequence number is older than the global sequence number.

03/26/15
20150089148 

Memory management unit


A data processing apparatus is provided comprising a plurality of master devices configured to issue memory access requests including virtual addresses. A memory management unit is configured to receive memory access requests and to translate a virtual address included in a memory access request from a requesting master device into a physical address indicating a storage location in memory.
Arm Limited


03/26/15
20150089117 

Computer system, memory management method and program thereof


A computer system, having a non-volatile storage unit (152), a main storage unit (151), and a data processor (102) including a memory management unit (102a) for managing a program stored in the non-volatile storage unit and the main storage unit to transfer a program stored in the non-volatile storage unit to the main storage unit, wherein the memory management unit (102a) includes a program storage control function of storing a program subjected to predetermined data conversion and a program yet to be subjected to predetermined data conversion in the non-volatile storage unit, and a function of combining programs subjected to predetermined data conversion so as not to bridge over a boundary between blocks at the execution of the program storage control function, as well as, at a first access to a certain block, expanding all the data included in the block to a corresponding block of the main storage unit.. .
Nec Corporation


03/19/15
20150082000 

System-on-chip and address translation method thereof


A memory management unit comprises an address translation unit that receives a memory access request as a virtual address and translates the virtual address to a physical address. A translation lookaside buffer stores page descriptors of a plurality of physical addresses, the address translation unit determining whether a page descriptor of a received virtual address is present in the translation lookaside buffer.
Samsung Electronics Co., Ltd.


03/19/15
20150081983 

Pre-fetch in a multi-stage memory management system


A memory management system for managing a memory and includes a multi-stage memory management unit including control circuitry and cache memory. The cache memory may have a respective translation look-aside buffer for each stage of the multi-stage memory management unit.
Stmicroelectronics International N.v.


03/12/15
20150070370 

Memory management techniques


memory management techniques that permit an executing process to store content in memory and later retrieve that content from the memory, but that also permit a memory manager to discard that content to address memory pressure. A process executing on a computing device may notify a memory manager of the computing device that first memory space allocated to the process contains first content that is available for discard.
Microsoft Corporation


03/05/15
20150067296 

I/o memory management unit providing self invalidated mapping


A memory management unit for 110 devices uses page table entries to translate virtual addresses to physical addresses. The page table entries include removal rules allowing the i/o memory management unit to delete page table entries without cpu involvement significantly reducing the cpu overhead involved in virtualized i/o data transactions..
Wisconsin Alumni Research Foundation


03/05/15
20150067289 

Method and implementing garbage collection within a computing environment


An approach is provided for obtaining memory management information associated with a computing environment, processing the memory management information to determine one or more computing devices within the computing environment experiencing full garbage collection, and resetting memory of the one or more computing devices to correct the full garbage collection.. .
Verizon Patent And Licensing Inc.


03/05/15
20150067287 

Distributed dynamic memory management unit (mmu)-based secure inter-processor communication


A first processor and a second processor are configured to communicate secure inter-processor communications (ipcs) with each other. The first processor effects secure ipcs and non-secure ipcs using a first memory management unit (mmu) to route the secure and non-secure ipcs via a memory system.
Qualcomm Incorporated


03/05/15
20150067264 

Method and memory management


In some embodiments, a method of managing cache memory includes identifying a group of cache lines in a cache memory, based on a correlation between the cache lines. The method also includes tracking evictions of cache lines in the group from the cache memory and, in response to a determination that a criterion regarding eviction of cache lines in the group from the cache memory is satisfied, selecting one or more (e.g., all) remaining cache lines in the group for eviction..
Advanced Micro Devices, Inc.


03/05/15
20150067234 

Unified memory controller for heterogeneous memory on a multi-chip package


An enhanced multi chip package (emcp) is provided including a unified memory controller. The umc is configured to manage different types of memory, such as nand flash memory and dram on the emcp.
Qualcomm Incorporated


03/05/15
20150067200 

Memory management for finite automata processing


Matching at least one regular expression pattern in an input stream may be optimized by initializing a search context in a run stack based on (i) partial match results determined from walking segments of a payload of a flow through a first finite automation and (ii) a historical search context associated with the flow. The search context may be modified via push or pop operations to direct at least one processor to walk segments of the payload through the at least one second finite automation.
Cavium, Inc.


03/05/15
20150063367 

Providing oversubscription of pipeline bandwidth


A system for providing oversubscription of pipeline bandwidth comprises a steer module, an absorption buffer, an ingress packet processor (ipp), a memory management unit (mmu), and a main packet buffer. The steer module receives packets that include start of packet (sop), middle of packet (mop), and end of packet (eop) cells, attaches a packet identifier to the cells, passes the mop and eop cells to the mmu, and stores the sop cells and eop metadata in the absorption buffer.
Broadcom Corporation


02/26/15
20150058717 

Document editing apparatus, non-transitory computer-readable recording medium and document editing method


Disclosed is a document editing apparatus including: a display unit; a page changing unit; an operating unit; an editing unit; an undo and redo memory; an undo and redo instruction unit; a memory management unit to manage an upper limit of number of storable editing history data including the editing history data of the editing operation performed in the displayed part; and an undo and redo performance unit to perform the undo operation by tracing back only the editing history data of the editing operation performed in the part displayed when the instruction to perform the undo operation is received, and to perform the redo operation by tracing back only the editing history data of the editing operation performed in the part displayed when the instruction to perform the redo operation is received.. .
Konica Minolta, Inc.


02/26/15
20150058578 

Enhanced pre-fetch in a memory management system


A memory management unit may send page table walk requests to a page table descriptor in a main memory system and receive address translation information, with the page table walk requests including information that specifies an amount of further address translation information, and receive the further address translation information. The cache unit may intercept the page table walk requests, and modify content of the intercepted page table walk requests so the information that specifies the amount of further address translation information is extended from a first amount to a second amount greater than the first amount.
Stmicroelectronics International N.v.


02/26/15
20150058541 

Memory management device and method


According to one embodiment, a device includes a determination unit, compression unit, selecting unit, write updating unit, writing unit. The determination unit determines whether to compress write data based on specific information.
Kabushiki Kaisha Toshiba


02/19/15
20150052506 

Runtime memory throttling


A system that implements a memory management policy at runtime when receiving a syntax tree in response to initiating the compiling of software code identifies a plurality of calls within the syntax tree and modifies each the plurality of calls with a corresponding memory-modified call to create a plurality of memory-modified calls. Each memory-modified call is linked with a memory management class and the modifying occurs during the compiling of the software code.
Oracle International Corporation


02/19/15
20150052319 

Memory management methods and systems for page-out mechanism


memory management methods and systems for page-out mechanism are provided. A page-out mechanism is performed via an os (operating system) based on a parameter of the page-out mechanism, wherein the page-out mechanism moves data from a memory to a storage unit.
Htc Corporation


02/12/15
20150046702 

Embedded encryption/secure memory management unit for peripheral interface controller


In an embodiment, a peripheral interface controller may include an inline cryptographic engine which may encrypt data being sent over a peripheral interface and decrypt data received from the peripheral interface. The encryption may be transparent to the device connected to the peripheral interface that is receiving/supplying the data.
Apple Inc.


02/12/15
20150046651 

Method for storing modified instruction data in a shared cache


A processor may include a cache configured to store instructions and memory data for the processor. The cache may store instructions in which a relative address, such as for a branch instruction has been calculated, such that the instruction stored in the cache is modified from how the instruction is stored in main memory.
Oracle International Corporation


02/05/15
20150040146 

Memory management


At least certain embodiments of the present disclosure include a method for memory management of a view of an application displayed on a display of a device. The method includes constructing a data structure having a hierarchy of layers with at least one layer being associated with the view.
Apple Inc.


02/05/15
20150039793 

Network interface card for a computing node of a parallel computer accelerated by general purpose graphics processing units, and related inter-node communication method


A network interface card (nic) for a cluster node for parallel calculation on multi-core gpu is described. The nic has a cluster network including a host and a host memory, a graphics processing unit (gpu) with a gpu memory, a bus and the nic.
Istituto Nazionale Di Fisica Nucleare


01/29/15
20150032986 

Memory block management systems and methods


A system for real-time operating system memory block and message management is disclosed. The real-time operating system enables different processes to migrate an allocated memory block from one type of memory block to another type of memory block, and to reliably release the block back to its correct pool of origin.

01/29/15
20150032977 

Memory management system, method and computer program product


According to one aspect of the present disclosure a method and technique for managing memory access is disclosed. The method includes setting a memory databus utilization threshold for each of a plurality of processors of a data processing system to maintain memory databus utilization of the data processing system at or below a system threshold.
International Business Machines Corporation


01/29/15
20150032972 

Methods and supporting persistent memory


A processing device features a processing unit, a memory management system, and persistent memory in a persistent memory domain. The processing device provides an enhanced write-back (wb-e) memory space for an application running on the processing unit.

01/01/15
20150006844 

Methods, systems, and devices for management of a memory system


Methods, devices, and systems for a memory management system within an electronic device are disclosed, such as those wherein the memory management system is external to and compatible with architectures of currently existing operating systems. One such memory management system may include a power savings manager configured to be invoked by a memory allocation manager.
Micron Technology, Inc.


01/01/15
20150006843 

Thread-based memory management with garbage collection


Systems and methods for thread-based memory management may include activating a processing thread. The memory may include a first region and a second region with the first region having several segments.
Sap Ag


01/01/15
20150006557 

Conservative garbage collecting and tagged integers for memory management


Aspects for conservative garbage collecting are disclosed. In one aspect, root objects included in a call stack are identified, which comprise integers and pointers.
Microsoft Corporation


12/25/14
20140380017 

Memory management and allocation using free-list


A method of managing a memory of an apparatus includes maintaining a plurality of lists of identifiers that each has an associated size value, wherein each identifier identifies a corresponding region of the memory that had been allocated for a process but that is currently not required by any of the one or more processes. When a process requests allocation of a region of the memory: one of the lists is identified that has an associated size value suitable for the allocation request; and if that list is not empty, a region of the memory is identified to the process by one of the identifiers that identifier is removed from that list, and, otherwise, a region of the memory is allocated with a size of the identified associated size value and the allocated region of the memory is identified the process..
Freescale Semiconductor, Inc.


12/18/14
20140372726 

Memory management method and apparatus


A method for managing memory using a virtual memory manager includes receiving a memory allocation request, allocating memory of a physical address space in response to the memory allocation request, mapping an address value of the memory allocated in the physical address space to consecutive primary virtual address space, and mapping the address value of the primary virtual address space to one of a first and second secondary virtual address spaces to process a new memory allocation request in a situation where memory a fragmentation occurs. Other embodiments are also disclosed.
Samsung Electronics Co., Ltd.


12/18/14
20140372694 

Methods and cut-through cache management for a mirrored virtual volume of a virtualized storage system


Methods and apparatus for cut-through cache memory management in write command processing on a mirrored virtual volume of a virtualized storage system, the virtual volume comprising a plurality of physical storage devices coupled with the storage system. Features and aspects hereof within the storage system provide for receipt of a write command and associated write data from an attached host.
Netapp, Inc.


12/11/14
20140365834 

Memory management tools


The present technology monitors events that allocate and deallocate virtual memory regions in a device, wherein the events include system calls from user space. The system can generate a log of events, and based on the log of events, track regions of virtual memory allocated and deallocated via the events.

12/11/14
20140365821 

Independent management of data and parity logical block addresses


A data storage method includes identifying, in a set of data items associated with respective logical addresses for storage in a memory, a first subset of the logical addresses associated with the data items containing application data, and a second subset of the logical addresses associated with the data items containing parity information that has been calculated over the application data. The data items associated with the first identified subset are stored in one or more first physical memory areas of the memory, and the data items associated with the second identified subset are stored in one or more second physical memory areas of the memory, different from the first physical memory areas.

12/04/14
20140359240 

Virtualizing processor memory protection with "l1 iterate and l2 drop/repopulate"


A computing system includes a guest domain access control register (dacr), and guest first and second level page tables, the page tables containing domain identifiers used to obtain domain access information and access permission information, and the domain access information and the access permission information providing an effective guest access permission. The computing system provides a shadow page table, in which domain identifiers are used to identify domain access information in a processor dacr that are mapped from domain access information in the guest dacr, and in which access permissions are mapped from effective access permission information in the guest page tables and guest dacr.

11/27/14
20140351550 

Memory management threads of data distribution service middleware


Disclosed herein are a memory management apparatus and method for threads of data distribution service middleware. The apparatus includes a memory area management unit, one or more thread heaps, and a queue.

11/27/14
20140351549 

Off-heap direct-memory data stores, methods of creating and/or managing off-heap direct-memory data stores, and/or systems including off-heap direct-memory data store


Certain example embodiments relate to a highly-concurrent, predictable, fast, self-managed, in-process space for storing data that is hidden away from the garbage collector and its related pauses. More particularly, certain example embodiments relate to improved memory management techniques for computer systems that leverage an off-heap direct-memory data store that is massively scalable and highly efficient.

11/27/14
20140351185 

Machine learning memory management and distributed rule evaluation


Aspects of the present disclosure relate to management of evaluated rule data sets. Specifically, a unreduced evaluated rule data set may contain a number of items to be compared or analyzed according to a number of rules, and may also contain the results of such analysis.

11/13/14
20140337597 

Computer, program, and memory management method


A computer capable of managing reference relationships between data executes access of first and second storage regions in which stored data can be altered and a third storage region in which stored data cannot be altered. The computer sets specification data in the first storage region for accessing data stored in the second and third storage regions, and shifts data having a reference relationship with the specification data from among the data stored in the third storage region to the second storage region.

10/30/14
20140325165 

Memory apparatus and memory management method


A memory apparatus includes a detection unit, a storage unit, an update unit, and a determination unit. The detection unit is configured to detect a deterioration factor of a nonvolatile memory.

10/30/14
20140325152 

Quadtree based data management for memory


A method for managing memory. The method includes executing a memory management function, and reading data from memory into a particular size array structure using the memory management function based on using quadtree structure sub-functions to scan the particular size array structure for filtering the data iteratively..

10/30/14
20140321281 

Fifo buffer with multiple stream packet segmentation


An epoch-based network processor internally segments packets for processing and aggregation in epoch payloads. Fifo buffers interact with a memory management unit to efficiently manage the segmentation and aggregation process..



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Memory Management topics: Memory Management, Virtual Machine, Storage Device, Volatile Memory, Data Processing, Logical Unit, Virtual Memory, Computer System, Dynamic Data, Base Memory, Database Management System, Data Storage, Defragment, Compatibility, Object Code

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