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Memory Management patents



      

This page is updated frequently with new Memory Management-related patent applications.




Date/App# patent app List of recent Memory Management-related patents
05/19/16
20160140059 
 Multiple memory management units patent thumbnailnew patent Multiple memory management units
In an embodiment, interfacing a pipeline with two or more interfaces in a hardware processor includes providing a single pipeline in a hardware processor. The single pipeline presents at least two visible units.
Cavium, Inc.


05/19/16
20160140048 
 Caching tlb translations using a unified page table walker cache patent thumbnailnew patent Caching tlb translations using a unified page table walker cache
A core executes memory instructions. A memory management unit (mmu) coupled to the core includes a first cache that stores a plurality of final mappings of a hierarchical page table, a page table walker that traverses levels of the page table to provide intermediate results associated with respective levels for determining the final mappings, and a second cache that stores a limited number of intermediate results provided by the page table walker.
Cavium, Inc.


05/19/16
20160140043 
 Instruction ordering for in-progress operations patent thumbnailnew patent Instruction ordering for in-progress operations
Execution of the memory instructions is managed using memory management circuitry including a first cache that stores a plurality of the mappings in the page table, and a second cache that stores entries based on virtual addresses. The memory management circuitry executes operations from the one or more modules, including, in response to a first operation that invalidates at least a first virtual address, selectively ordering each of a plurality of in progress operations that were in progress when the first operation was received by the memory management circuitry, wherein a position in the ordering of a particular in progress operation depends on either or both of: (1) which of one or more modules initiated the particular in progress operation, or (2) whether or not the particular in progress operation provides results to the first cache or second cache..
Cavium, Inc.


05/19/16
20160140035 
 Memory management techniques patent thumbnailnew patent Memory management techniques
memory management techniques that permit an executing process to store content in memory and later retrieve that content from the memory, but that also permit a memory manager to discard that content to address memory pressure. A process executing on a computing device may notify a memory manager of the computing device that first memory space allocated to the process contains first content that is available for discard.
Microsoft Technology Licensing, Llc


05/12/16
20160132270 
 Information processing device, information procesing method, and program patent thumbnailInformation processing device, information procesing method, and program
An information processing device including an nv memory that is a non-volatile recording medium, a file system unit that manages one or more files stored in the nv memory, and a memory management unit that allocates one or more areas of the nv memory, that are ready to be used by the file system unit to store a file, to a running process in response to a request from the running process. The file system unit accesses areas of the nv memory storing unused area management data sets for managing unused areas of the nv memory.
Fixstars Corporation


05/05/16
20160124852 
 Memory management for graphics processing unit workloads patent thumbnailMemory management for graphics processing unit workloads
A method, a device, and a non-transitory computer readable medium for performing memory management in a graphics processing unit are presented. Hints about the memory usage of an application are provided to a page manager.
Advanced Micro Devices, Inc.


05/05/16
20160124848 
 Memory system and memory management method thereof patent thumbnailMemory system and memory management method thereof
A memory system include a memory device including a plurality of blocks, each of the blocks having a plurality of pages, and a controller suitable for determining valid pages from among the plurality of pages based on data temperature, and performing a garbage collection process based on a number of valid pages and data temperature of the valid pages.. .
Sk Hynix Memory Solutions Inc.


04/28/16
20160117872 
 Memory management in event recording systems patent thumbnailMemory management in event recording systems
A vehicle event recorder is provided that includes a camera for capturing a video as discrete image frames, and that further includes a managed loop memory and a management system for generating a virtual ‘timeline dilation’ effect. To overcome size limits in the buffer memory of the video event recorder, the maximum time extension of a video series is increased by enabling a reduction in temporal resolution in exchange for an increase in the temporal extension.
Smartdrive Systems, Inc.


04/28/16
20160117131 
 Asymmetric memory migration in hybrid main memory patent thumbnailAsymmetric memory migration in hybrid main memory
Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, the memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory.
Virident Systems Inc.


04/21/16
20160110298 
 Memory protection key architecture with independent user and supervisor domains patent thumbnailMemory protection key architecture with independent user and supervisor domains
A processing system includes a processing core to execute a task and a memory management unit, coupled to the core. The memory management unit includes a storage unit to store a page table entry including one or more identifiers of memory frames, a protection key, and an access mode bit indicating whether the one or more memory frames are accessible according to a user mode or according to a supervisor mode, a first permission register including a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the user mode, and a second permission register storing a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the supervisor mode..

04/21/16
20160110225 

System and improving memory usage in virtual machines


An apparatus includes at least one processor executing a method for managing memory among a plurality of concurrently-running virtual machines, and a non-transitory memory device that stores a set of computer readable instructions for implementing and executing said memory management method. A memory optimization mechanism can reduce a memory usage of a virtual machine at a cost of increasing a central processing unit (cpu) usage.

04/07/16
20160098356 

Hardware-assisted memory compression management using page filter and system mmu


Provided are methods and systems for managing memory using a hardware-based page filter designed to distinguish between active and inactive pages (“hot” and “cold” pages, respectively) so that inactive pages can be compressed prior to the occurrence of a page fault. The methods and systems are designed to achieve, among other things, lower cost, longer battery life, and faster user response.
Google Inc.


04/07/16
20160098345 

Memory management apparatus and method


A memory management apparatus and method are provided herein. The memory management apparatus includes a memory management list generation unit, a memory allocation unit, and a memory release unit.
Electronics And Telecommunications Research Institute


04/07/16
20160098344 

Hardware automation for memory management


A storage module may include a controller that has hardware path that includes a plurality of hardware modules configured to perform a plurality of processes associated with execution of a host request. The storage module may also include a firmware module having a processor that executes firmware to perform at least some of the plurality of processes performed by the hardware modules.
Sandisk Technologies Inc.


04/07/16
20160098229 

Automatic analysis of issues concerning automatic memory management


Systems and methods are provided to automatically analyze performance of an automatic memory management system. One example embodiment involves automatically gathering, using at least one processor of the server, garbage collection information associated with the garbage collection process and storing the garbage collection information in a garbage collection output file of a file system.

03/31/16
20160092273 

System and managing the allocating and freeing of objects in a multi-threaded system


A memory management system for managing objects which represent memory in a multi-threaded operating system extracts the id of the home free-list from the object header to determine whether the object is remote and adds the object to a remote object list if the object is determined to be remote. The memory management system determines whether the number of objects on the remote object list exceeds a threshold.
Software Ag


03/24/16
20160085771 

Information processing device, information procesing method, and program


There is provided an information processing device comprising an nv memory that is a non-volatile recording medium, a file system unit that manages one or more files stored in the nv memory, and a memory management unit that secures one or more areas of the nv memory that are ready to be used by the file system unit to store a file, and allocates the secured one or more areas to a running process in response to a request from the running process. According to the information processing device, when the nv memory is used both as a main memory and a storage, inconsistencies in the file system caused by an abnormal termination of the system are reduced..
Fixstars Corporation


03/24/16
20160085688 

Multi-source address translation service (ats) with a single ats resource


Disclosed is an address translation system. The apparatus includes a memory management unit (mmu) that is operable to receive a translation request for an original address and translate the original address to a translated address as a second-level address translation service (ats).

03/24/16
20160085687 

Memory management component


A memory management component arranged to receive memory access transactions and provide memory management functionality therefor, and a method of providing memory management functionality within a processing system are disclosed. The memory management component comprises a first memory management module arranged to provide memory management functionality for received memory access transactions in accordance with a paging memory management scheme, and at least one further memory management module arranged to provide memory management functionality for received memory access transactions in accordance with an address range memory management scheme..
Freescale Semiconductor, Inc.


03/24/16
20160085669 

Descriptor ring management


A data processing system utilising a descriptor ring 24 to facilitate communication between one or more general purpose processors 4, 6 and one or more devices 20, 22 employs a system memory management unit 18 for managing access by the devices 20, 22 to a main memory 16. The system memory management unit 18 uses address translation data for translating memory addresses generated by the devices 20, 22 into addresses supplied to the main memory 16.
Arm Limited


03/17/16
20160080756 

Memory management for video decoding


Techniques and tools described herein help manage memory efficiently during video decoding, especially when multiple video clips are concurrently decoded. For example, with clip-adaptive memory usage, a decoder determines first memory usage settings expected to be sufficient for decoding of a video clip.
Microsoft Technology Licensing, Llc


03/17/16
20160077866 

Embedded processor with virtualized security controls using guest identifications, a common kernel address space and operational permissions


A method includes assigning unique guest identifications to different guests, specifying an address region and permissions for the different guests and controlling a guest jump from one physical memory segment to a second physical memory segment through operational permissions defined in a root memory management unit that supports guest isolation and protection.. .
Arm Finance Overseas Limited


03/10/16
20160070475 

Memory management method, apparatus, and system


A memory management method implemented by a requesting node includes sending first indication information used for indicating a length of memory required by the requesting node and receiving second indication information used for indicating first remote memory provided to the requesting node by a target contributing node in at least one contributing node that can provide remote memory. The method also includes determining, from available virtual addresses, a first virtual address corresponding to the first remote memory, and sending a first data read/write instruction for the first data when first data whose pointer is within a range of the first virtual address needs to be read/written, where the first data read/write instruction includes third indication information, and the third indication information is used for indicating storage space, for storing the first data, in the first remote memory..
Huawei Technologies Co., Ltd.


03/03/16
20160063357 

Systems and methods for object classification, object detection and memory management


A method for object classification by an electronic device is described. The method includes obtaining an image frame that includes an object.
Qualcomm Incorporated


03/03/16
20160062691 

Method for controlling memory device to achieve more power saving and related apparatus thereof


A memory management method includes: performing a first-level collection operation upon first storage units in a memory pool allocated in a memory device; and after the first storage units are processed by the first-level collection operation, performing a second-level collection operation upon second storage units in the memory pool allocated in the memory device, wherein one of the first-level collection operation and the second-level collection operation is a page-level collection operation, and another of the first-level collection operation and the second-level collection operation is a bank-level collection operation.. .
Mediatek Inc.


03/03/16
20160062660 

Memory management device


A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory..
Kabushiki Kaisha Toshiba


02/25/16
20160054938 

Memory management device and method


According to one embodiment, a device includes a determination unit, compression unit, selecting unit, write updating unit, writing unit. The determination unit determines whether to compress write data based on specific information.
Kabushiki Kaisha Toshiba


02/25/16
20160054937 

Temperature accelerated stress time


A memory system or flash card may be exposed to elapsed time or increased temperature conditions which may degrade the memory. For example, extended time periods or high temperature conditions may hinder data retention in a memory device.
Sandisk Technologies Inc.


02/25/16
20160054931 

Storage devices and methods for optimizing use of storage devices based on storage device parsing of file system metadata in host write operations


The subject matter described herein includes processing file system metadata in host write requests to determine information about future host write operations. The information regarding future host write operations can be used by a device controller to prepare the non-volatile memory for the future host write operations.
Sandisk Technologies Inc.


02/25/16
20160054922 

Data management scheme in virtualized hyperscale environments


According to one general aspect, a memory management unit (mmu) may be configured to interface with a heterogeneous memory system that comprises a plurality of types of storage mediums. Each type of storage medium may be based upon a respective memory technology and may be associated with performance characteristic(s).

02/25/16
20160054921 

Memory management method, memory storage device and memory controlling circuit unit


A memory management method, a memory storage device and a memory controlling circuit unit are provided. The method includes: defining a first data management rule for a first type physical unit and a second data management rule for a second type physical unit, and a data density of the first type physical unit is lower than the data density of the second type physical unit; if a first physical unit belongs to the first type physical unit, managing the first physical unit according to the first data management rule to make the data stored in the first physical unit conforming to a first reliability level; and if the first physical unit belongs to the second type physical unit, managing the first physical unit according to the second data management rule to make the data stored in the first physical unit conforming to a second reliability level..
Phison Electronics Corp.


02/18/16
20160050250 

Memory management of digital audio data


A system, method and computer-readable code for the management of digital media on a device with memory and storage restrictions. As with any device, memory and storage is limited.
Audio Pod Inc.


02/18/16
20160048458 

Computer security systems and methods using hardware-accelerated access to guest memory from below the operating system


Described systems and methods allow computer security software to access a memory of a host system with improved efficiency. A processor and a memory management unit (mmu) of the host system may be configured to perform memory access operations (read/write) in a target memory context, which may differ from the implicit memory context of the currently executing process.
Bitdefender Ipr Management Ltd.


02/18/16
20160048339 

Intelligent computer memory management


A plurality of memory allocators are initialized within a computing system. At least a first memory allocator and a second memory allocator in the plurality of memory allocators are each customizable to efficiently handle a set of different memory request size distributions.
International Business Machines Corporation


02/11/16
20160041828 

Method and system for generating object code to facilitate predictive memory retrieval


A method and system are described for generating reference tables in object code which specify the addresses of branches, routines called, and data references used by routines in the code. In a suitably equipped processing system, the reference tables can be passed to a memory management processor which can open the appropriate memory pages to expedite the retrieval of data referenced in the execution pipeline.
Micron Technology, Inc.


02/11/16
20160041773 

System and multistage processing in a memory storage subsystem


Embodiments of this disclosure relate to improving solid-state non-volatile memory management. Embodiments improve the management of solid-state non-volatile memory by providing an execution manager responsible for controlling the timing of providing a request to a memory unit for execution.
Western Digital Technologies, Inc.


02/11/16
20160041766 

Method and memory management


One or more circuits of a device may comprise a memory. A first portion of a first block of the memory may store program code and/or program data, a second portion of the first block may store an index associated with a second block of the memory, and a third portion of the first block may store an indication of a write status of the first portion.
Blackbird Technology Holdings, Inc.


02/04/16
20160037281 

Memory management techniques and related systems for block-based convolution


A processor can be associated with a memory for storing convolution data. A plurality of m filters from a corresponding plurality of m input channels to a selected one output channel can be provided, wherein each filter can be represented by a corresponding index, m.

02/04/16
20160035324 

Memory management for systems for generating 3-dimensional computer images


A memory management system for generating 3-dimensional computer images is provided. The memory management system includes a device for subdividing an image into a plurality of rectangular areas, a memory for storing object data pertaining to objects in the image which fall in each rectangular area, a device for storing the object data in the memory, a device for deriving image data and shading data for each rectangular area from the object data, a device for supplying object data for each rectangular area from the respective portion of the memory and, if the rectangular area contains objects also falling in at least one other rectangular area, also from the global list, to the deriving device, and a device for storing the image data and shading data derived by the deriving device for display.
Imagination Technologies Limited


02/04/16
20160034407 

Technique for synchronizing iommu memory de-registration and incoming i/o data


A technique synchronizes de-registration of registered memory and incoming input/output (i/o) data received from an i/0 device for storage in a memory of a computer system. Registration and de-registration of the memory with an i/o memory management unit (iommu) are illustratively performed by an i/o device driver of the computer system in anticipation of (or in response to) an i/o request to store the incoming i/o data in buffers of the memory.
Netapp, Inc.


01/28/16
20160026392 

Off-heap direct-memory data stores, methods of creating and/or managing off-heap direct-memory data stores, and/or systems including off-heap direct-memory data store


Certain example embodiments relate to a highly-concurrent, predictable, fast, self-managed, in-process space for storing data that is hidden away from the garbage collector and its related pauses. More particularly, certain example embodiments relate to improved memory management techniques for computer systems that leverage an off-heap direct-memory data store that is massively scalable and highly efficient.
Software Ag Usa, Inc.


01/21/16
20160019168 

On-demand shareability conversion in a heterogeneous shared virtual memory


The aspects include systems and methods of managing virtual memory page shareability. A processor or memory management unit may set in a page table an indication that a virtual memory page is not shareable with an outer domain processor.
Qualcomm Incorporated


01/21/16
20160019144 

Systems and/or methods for enabling storage tier selection and usage at a granular level


Certain example embodiments relate to memory management techniques that enable users to “pin” elements to particular storage tiers (e.g., ram, ssd, hdd, tape, or the like). Once pinned, elements are not moved from tier-to-tier during application execution.
Software Ag Usa, Inc.


01/21/16
20160019031 

Method and system for processing memory


A method and system for memory management is disclosed. The disclosed method and system can prevent performance degradation due to automatic garbage collection associated with memory allocation for image processing.
Quram Co., Ltd.


01/14/16
20160012241 

Distributed dynamic memory management unit (mmu)-based secure inter-processor communication


A first processor and a second processor are configured to communicate secure inter-processor communications (ipcs) with each other. The first processor effects secure ipcs and non-secure ipcs using a first memory management unit (mmu) to route the secure and non-secure ipcs via a memory system.
Qualcomm Incorporated


01/14/16
20160011649 

Electronic apparatus, power supply control method, and program


An electronic apparatus equipped with a power source, a storage section, a memory management section, and a control section. The storage section is provided with a predetermined memory space.
Nec Corporation


01/07/16
20160004654 

System for migrating stash transactions


A system for migrating stash transactions includes first and second cores, an input/output memory management unit (iommu), an iommu mapping table, an input/output (i/o) device, a stash transaction migration management unit (stmmu), a queue manager and an operating system (os) scheduler. The i/o device generates a first stash transaction request for a first data frame.
Freescale Semiconductor, Inc.


01/07/16
20160004453 

Snapshot management using extended data units


A method for memory management, the method may include receiving an updated portion of a data unit, the data unit is associated with a logical data entity; wherein the updated portion is smaller than a granularity of a mapping data structure used for retrieval of the data unit; and creating, by the storage system an extended data unit that comprises (i) an original content of the data unit, (ii) the updated portion and, (iii) updated portion metadata; wherein the updated portion metadata comprises (a) updated portion retrieval information for retrieving the updated portion, and (b) updated portion snapshot information indicative of at least one snapshot associated with the updated portion.. .
Infinidat Ltd.


12/31/15
20150381728 

Systems and methods for performing memory management in a distributed environment


Systems and methods for performing memory management among a plurality of devices in a network are described. In one implementation, the method for performing memory management comprises obtaining memory requirements for execution of an application.
Wipro Limited


12/31/15
20150378889 

Persistent content in nonvolatile memory


Applications may request persistent storage in nonvolatile memory. The persistent storage is maintained across power events and application instantiations.
Micron Technology, Inc.


12/31/15
20150378762 

Monitoring and dynamic configuration of virtual-machine memory-management


The current document is directed to methods and systems for monitoring the performance of memory management in virtual machines. By accurately measuring the performance of memory management in virtual machines, a virtualization layer can dynamically reconfigure virtual machines to use more optimal memory-management methods, intelligently schedule execution of virtual machines to increase memory-management performance, and migrate virtual machines among different servers and computer systems to increase memory-management performance..
Vmware, Inc.


12/31/15
20150378731 

Apparatus and efficiently implementing a processor pipeline


Various different embodiments of the invention are described including: (1) a method and apparatus for intelligently allocating threads within a binary translation system; (2) data cache way prediction guided by binary translation code morphing software; (3) fast interpreter hardware support on the data-side; (4) out-of-order retirement; (5) decoupled load retirement in an atomic ooo processor; (6) handling transactional and atomic memory in an out-of-order binary translation based processor; and (7) speculative memory management in a binary translation based out of order processor.. .

12/31/15
20150378424 

Memory management based on bandwidth utilization


A processing system includes a memory circuit configured for operation at a plurality of frequency-voltage operating points and one or more processing elements operatively coupled to the memory circuit. A memory-bandwidth measurement circuit repeatedly measures run-time bandwidth utilization of the memory circuit, while a controller circuit dynamically adjusts the voltage-frequency operating point of the memory circuit as a function of the measured run-time bandwidth utilization.
Telefonaktiebolaget L M Ericsson (publ)


12/24/15
20150372896 

Packet segmentation with different segment sizes for a switch fabric


An epoch-based network processor internally segments packets for processing and aggregation in epoch payloads. Fifo buffers interact with a memory management unit to efficiently manage the segmentation and aggregation process..
Force10 Networks, Inc.


12/24/15
20150370728 

Memory management device and non-transitory computer readable storage medium


In one embodiment, a device executes reading and writing for a storage unit storing a table tree and verifier tree. The table tree includes a parent table and child table.
Kabushiki Kaisha Toshiba


12/24/15
20150370727 

Memory management device and non-transitory computer readable storage medium


In one embodiment, a device executes reading and writing for a storage unit storing a table tree and verifier tree. The table tree includes a parent table and child table.
Kabushiki Kaisha Toshiba


12/24/15
20150370726 

Memory management device and non-transitory computer readable storage medium


In one embodiment, a storage unit stores a table tree and verifier tree. The table tree includes parent and child tables.
Kabushiki Kaisha Toshiba


12/24/15
20150370709 

Reduction of evictions in cache memory management directories


A module of cache coherence management by directory, in which each datum stored in cache memory is associated with a state, at least one of which indicates data sharing among a plurality of processors, the module including a storage unit to store a directory containing a list of cache memory addresses, each address possibly associated with a state corresponding to the state of the datum available at this address, and a processing unit configured to update said list, said processing unit being configured so as not to list the address lines related to data associated with the first state.. .
Bull Sas


12/17/15
20150363594 

System and secure loading data in a cache memory


A system and method for securely loading data in a cache memory associated with at least one secure processor that performs data processing by using at least one untrusted external memory storing data to be processed, at least one secure internal cache memory to load or store data, and at least one secure cache translator operating as a memory management unit. The secure cache translator stores, into a secure cache digest table, parameters arranged on persistent and variable data pages.
Nagravision Sa


12/17/15
20150363311 

Memory management method


A method for managing main memory including dram and nvram in a computer depending on the operation state of the computer is provided. The method includes: (a) upon start of the computer, loading a program and the like into the dram, and loading predetermined read-only data and the like into the nvram; (b) in a state transition from a normal operation to a suspend state, moving data in the dram to the nvram; (c) in a state transition from the suspend state to the normal operation, reading data from the nvram for program execution; (d) in the case where a data write to the nvram occurs, stopping the data write, and moving data in a data area of the nvram subjected to the data write, to the dram; and (e) performing the data write to the dram to which the data has been moved..
International Business Machines Corporation


12/10/15
20150357025 

Device, system, and memory allocation


Device, system, and method of memory allocation. For example, an apparatus includes: a dual in-line memory module (dimm) including a plurality of dynamic random access memory (dram) units to store data, wherein each dram unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said dimm to a memory page of an operating system, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the operating system..
Intel Corporation


12/10/15
20150356023 

Paravirtualization-based interface for memory management in virtual machines


A method for memory virtualization in a system including guest virtual, guest physical and host physical address spaces, a guest pagetable for translating addresses of the guest virtual address space into addresses of the guest physical address space, a shadow pagetable for translating addresses of the guest virtual address space into addresses of the host physical address space, and a hypervisor configured for calculating address entries for the shadow pagetable from valid address entries in the guest pagetable, includes managing, by the hypervisor, one or more shadow pagetable(s) by the hypervisor while a guest context is executed by a guest operating system, wherein the number of shadow pagetable(s) is smaller than or equal to the number of guest contexts in a current working set.. .
Deutsche Telekom Ag


12/10/15
20150356007 

Parallel garbage collection implemented in hardware


Embodiments of the invention provide a method and system for dynamic memory management implemented in hardware. In an embodiment, the method comprises storing objects in a plurality of heaps, and operating a hardware garbage collector to free heap space.
International Business Machines Corporation


12/10/15
20150355851 

Dynamic selection of memory management algorithm


A data processing system 2 includes a memory controller 20 which dynamically selects from a plurality of candidate management algorithms a selected management algorithm to be used for managing memory access conflicts. The memory management algorithms may include various versions of speculative memory access issue and/or memory access issue using memory locks.
Arm Limited


12/03/15
20150350644 

Moving image prediction encoding/decoding system


A moving image encoding/decoding system may include a video predictive encoding device, which may include: an encoding device which encodes each of a plurality of input pictures to generate compressed picture data including a random access picture, and encodes data about display order information of each picture; a restoration device which decodes the compressed picture data to restore a reproduced picture; a picture storage device which stores the reproduced picture as a reference picture; and a memory management device which controls the picture storage device. Following completion of an encoding process of generating the random access picture, the memory management device refreshes the picture storage device by setting every reference picture in the picture storage device, except for the random access picture, as unnecessary immediately before or immediately after encoding a picture with display order information larger than the display order information of the random access picture..
Ntt Docomo, Inc.


12/03/15
20150347434 

Reducing metadata in a write-anywhere storage system


Systems and methods for reducing metadata in a write-anywhere storage system are disclosed herein. The system includes a plurality of clients coupled with a plurality of storage nodes, each storage node having a plurality of primary storage devices coupled thereto.
Datadirect Networks, Inc.


12/03/15
20150347322 

Speculative querying the main memory of a multiprocessor system


A method of accessing data in a multiprocessor system, wherein the system includes a plurality of processors, with each processor being associated with a respective cache memory, a cache memory management module, a main memory and a main memory management module, the method including: receiving by the cache memory management module an initial request for access to data by a processor; first transmitting by the cache memory management module a first request with respect to the data to at least one cache memory; second transmitting in parallel to the first transmitting by the cache memory management module, a second request with respect to the data to the main memory management module; checking by the main memory management module, whether to initiate querying of the main memory or not, and querying or not by the main memory management module, of the main memory in accordance with the said checking.. .
Bull Sas


12/03/15
20150347306 

Synchronizing updates of page table status indicators in a multiprocessing environment


A synchronization capability to synchronize updates to page tables by forcing updates in cached entries to be made visible in memory (i.e., in in-memory page table entries). A synchronization instruction is used that ensures after the instruction has completed that updates to the cached entries that occurred prior to the synchronization instruction are made visible in memory.
International Business Machines Corporation


12/03/15
20150347301 

Synchronizing updates of page table status indicators and performing bulk operations


A synchronization capability to synchronize updates to page tables by forcing updates in cached entries to be made visible in memory (i.e., in in-memory page table entries). A synchronization instruction is used that ensures after the instruction has completed that updates to the cached entries that occurred prior to the synchronization instruction are made visible in memory.
International Business Machines Corporation


12/03/15
20150347300 

Synchronizing updates of page table status indicators in a multiprocessing environment


A synchronization capability to synchronize updates to page tables by forcing updates in cached entries to be made visible in memory (i.e., in in-memory page table entries). A synchronization instruction is used that ensures after the instruction has completed that updates to the cached entries that occurred prior to the synchronization instruction are made visible in memory.
International Business Machines Corporation


12/03/15
20150347190 

System and coordinating process and memory management across domains


A method at a computing device having a plurality of concurrently operative operating systems, the method comprising: operating a proxy process within a target operating system on the computing device; receiving, from an originating operating system, a request for resources from a target process within the target operating system at the proxy process; requesting, from the proxy process, the resources of the target process; and returning a handle to the target process from the proxy process to the originating operating system.. .
2236008 Ontario Inc.


12/03/15
20150347052 

Virtualisation supporting guest operating systems using memory protection units


A processor (20) is provided with a first memory protection unit (38) applying a first set of permissions and a second memory protection unit (40) applying a second set of permissions. A memory access will only be permitted if both the first set of permissions and the second set of permissions are satisfied.
Arm Limited


12/03/15
20150347044 

Synchronizing updates of page table status indicators and performing bulk operations


A synchronization capability to synchronize updates to page tables by forcing updates in cached entries to be made visible in memory (i.e., in in-memory page table entries). A synchronization instruction is used that ensures after the instruction has completed that updates to the cached entries that occurred prior to the synchronization instruction are made visible in memory.
International Business Machines Corporation


12/03/15
20150347023 

Memory coalescing computer-implemented method, system, apparatus and computer-readable media


Embodiments of computer-implemented methods, apparatus and computer-readable media associated with memory management are disclosed herein. A computer-implemented method to coalesce free intervals of a memory may include ascertaining that a first interval of the memory is free (302, 304).

11/26/15
20150339225 

Memory management method, memory storage device and memory control circuit unit


A memory management method, a memory storage device and a memory control circuit unit are provided. The memory management method includes: grouping a plurality of non-spare physical erasing units into a first physical erasing unit and a second physical erasing unit, and a data updating frequency of the first physical erasing unit is lower than the data updating frequency of the second physical erasing unit; selecting a third physical erasing unit from the physical erasing units belonging to the first physical erasing unit; selecting a fourth physical erasing unit from spare physical erasing units, and copying valid data stored in the third physical erasing unit to the fourth physical erasing unit..
Phison Electronics Corp.


11/26/15
20150339166 

Memory management for virtual machines


Embodiments of the disclosure relate to managing a memory of a server hosting a plurality of virtual machines. Aspects include receiving a plurality of data pages from each of the plurality of virtual machines to be stored in the memory, filtering each the plurality of data pages into one of a plurality of pools of data pages including a pool of potentially identical data pages, and evaluating the data pages in the pool of potentially identical data pages to identify one or more duplicate data pages and one or more similar data pages.
International Business Machines Corporation


11/26/15
20150339141 

Memory management for virtual machines


Embodiments of the disclosure relate to managing a memory of a server hosting a plurality of virtual machines. Aspects include receiving a plurality of data pages from each of the plurality of virtual machines to be stored in the memory, filtering each the plurality of data pages into one of a plurality of pools of data pages including a pool of potentially identical data pages, and evaluating the data pages in the pool of potentially identical data pages to identify one or more duplicate data pages and one or more similar data pages.
International Business Machines Corporation


11/12/15
20150324299 

Temporal standby list


In one embodiment, a memory management system temporarily maintains a memory page at an artificially high priority level. The memory management system may assign an initial priority level to a memory page in a page priority list.
Microsoft Technology Licensing, Llc


11/12/15
20150324286 

Memory management method in embedded system


A memory management method in an embedded system is provided. The method includes a first iteration step that sequentially allocates and deletes memory, and recognizes an area where the first to last sections of the memory were located as a hollow space list a second iteration step sequentially allocates the memory in an area of the hollow space list by starting the memory allocation from an end point of the hollow space list.
Hyundai Motor Company


11/12/15
20150323969 

Memory storage device, memory control circuit unit and power supply method


A memory storage device, a memory control circuit unit and a power supply method are provided. The power supply method includes: providing a first power voltage to a host interface circuit of the memory storage device; providing a second power voltage to a memory management circuit of the memory storage device; providing a third power voltage to a memory interface circuit of the memory storage device, wherein a reference voltage terminal of the memory interface circuit is coupled to a power input terminal of the memory management circuit.
Phison Electronics Corp.


11/05/15
20150317271 

Graphics processing microprocessor system having a master device communicate with a slave device


A slave device communicates with a host system via a host communications bus. The host system includes one processor that can act as bus master and send access requests for slave resources on the slave device via the communications bus.
Arm Norway As


11/05/15
20150317259 

Memory management unit that applies rules based on privilege identifier


A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the master, usually a cpu originating the request based on a privilege identifier that accompanies each memory access request.
Texas Instruments Incorporated


11/05/15
20150317080 

Apparatus including memory system controllers and related methods


Memory system controllers can include non-volatile memory control circuitry including a plurality of channel control circuits. Each of the plurality of channel control circuits can be configured to be coupled to a respective number of logical units (luns).
Micron Technology, Inc.


10/29/15
20150310301 

Analyzing or resolving ambiguities in an image for object or pattern recognition


Specification covers new algorithms, methods, and systems for artificial intelligence, soft computing, and deep learning/recognition, e.g., image recognition (e.g., for action, gesture, emotion, expression, biometrics, fingerprint, facial, ocr (text), background, relationship, position, pattern, and object), large number of images (“big data”) analytics, machine learning, training schemes, crowd-sourcing (using experts or humans), feature space, clustering, classification, similarity measures, optimization, search engine, ranking, question-answering system, soft (fuzzy or unsharp) boundaries/impreciseness/ambiguities/fuzziness in language, natural language processing (nlp), computing-with-words (cww), parsing, machine translation, sound and speech recognition, video search and analysis (e.g. Tracking), image annotation, geometrical abstraction, image correction, semantic web, context analysis, data reliability (e.g., using z-number (e.g., “about 45 minutes; very sure”)), rules engine, control system, autonomous vehicle, self-diagnosis and self-repair robots, system diagnosis, medical diagnosis, biomedicine, data mining, event prediction, financial forecasting, economics, risk assessment, e-mail management, database management, indexing and join operation, memory management, and data compression..

10/29/15
20150309948 

Tracking statistics corresponding to data access in a computer system


Embodiments of the present invention disclose a method, computer program product, and system for determining statistics corresponding to data transfer operations. In one embodiment, the computer implemented method includes the steps of receiving a request from an input/output (i/o) device to perform a data transfer operation between the i/o device and a memory, generating an entry in an input/output memory management unit (iommu) corresponding to the data transfer operation, wherein the entry in the iommu includes at least an indication of a processor chip that corresponds to the memory of the data transfer operation, monitoring the data transfer operation between the i/o device and the memory, determining statistics corresponding to the monitored data transfer operation, wherein the determined statistics include at least: the i/o device that performed the data transfer operation, the processor chip that corresponds to the memory of the data transfer operation, and an amount of data transferred..
International Business Machines Corporation


10/29/15
20150309947 

Tracking statistics corresponding to data access in a computer system


Embodiments of the present invention disclose a method, computer program product, and system for determining statistics corresponding to data transfer operations. In one embodiment, the computer implemented method includes the steps of receiving a request from an input/output (i/o) device to perform a data transfer operation between the i/o device and a memory, generating an entry in an input/output memory management unit (iommu) corresponding to the data transfer operation, wherein the entry in the iommu includes at least an indication of a processor chip that corresponds to the memory of the data transfer operation, monitoring the data transfer operation between the i/o device and the memory, determining statistics corresponding to the monitored data transfer operation, wherein the determined statistics include at least: the i/o device that performed the data transfer operation, the processor chip that corresponds to the memory of the data transfer operation, and an amount of data transferred..
International Business Machines Corporation


10/29/15
20150309741 

Apparatuses and methods for memory management


Some embodiments include apparatuses and methods to select a target memory portion in a first memory location to store information. One such method can conditionally store the information in a second memory location when the information is stored in the target memory portion.
Micron Technology, Inc.


10/22/15
20150304687 

Low complex deblocking filter decisions


The present disclosure relates to deblocking filtering, which may be advantageously applied for block-wise encoding and decoding of images or video signals. In particular, the present disclosure relates to an improved memory management in an automated decision on whether to apply or skip deblocking filtering for a block and to selection of the deblocking filter.
Panasonic Intellectual Property Corporation Of America


10/22/15
20150302903 

System and deep coalescing memory management in a portable computing device


Various embodiments of methods and systems for deep coalescing memory management (“dcmm”) in a portable computing device (“pcd”) are disclosed. Because multiple active multimedia (“mm”) clients running on the pcd may generate a random stream of mixed read and write requests associated with data stored at non-contiguous addresses in a double data rate (“ddr”) memory component, dcmm solutions triage the requests into dedicated deep coalescing (“dc”) cache buffers, sequentially ordering the requests and/or the dc buffers based on associated addresses for the data in the ddr, to optimize read and write transactions from and to the ddr memory component in blocks of contiguous data addresses..
Qualcomm Incorporated


10/22/15
20150301947 

Controlling access to groups of memory pages in a virtualized environment


Embodiments of an invention for controlling access to groups of memory pages in a virtualized environment are disclosed. In one embodiment, a processor includes a virtualization unit and a memory management unit.
Intel Corporation


10/22/15
20150301932 

Nonvolatile memory system and performing operation of the nonvolatile memory system


According to example embodiments, a nonvolatile memory system includes a nonvolatile memory device includes a nonvolatile memory cell array, a temperature sensor configured to measure a temperature of the nonvolatile memory device, and a memory controller configured to adjust an execution frequency of a memory management operation based on a desired (and/or alternatively predetermined) temperature range and the measured temperature.. .

10/22/15
20150301917 

Memory monitoring method and related apparatus


A memory monitoring method and a computing system. The computing system includes a processor, a memory and a monitor.
Huawei Technologies Co., Ltd.


10/15/15
20150293790 

Method and system for driving virtual machine


Provided herein a method for driving a virtual machine, the method including providing a plurality of virtual machines and a virtual machine monitor configured to manage the plurality of virtual machines; generating, by the plurality of virtual machines, memory management information, that is information on memory being used by the plurality of virtual machines; and determining, by the virtual machine monitor, whether or not a virtual machine is a victim virtual machine from which memory needs to be retrieved or whether or not the virtual machine is a beneficiary virtual machine where memory needs to be allocated, based on the memory management information.. .

10/15/15
20150293776 

Data processing systems


A data processing system includes one or more processors that each execute one or more operating systems. Each operating system includes one or more applications.

10/15/15
20150293736 

Electronic device and memory management method that improves usage efficiency of memory


A first-region allocating unit of an electronic device allocates a first region having a size required for a first process. The first process includes at least one second process in a region of the memory.

10/08/15
20150286564 

Hardware-based memory management apparatus and memory management method thereof


A hardware-based memory management apparatus and method is provided. The apparatus includes a memory allocation module, a memory reclamation module, and a memory compaction module, based on hardware to accelerate a memory manger of an operating system.

10/08/15
20150286442 

Cluster-wide memory management using similarity-preserving signatures


A method includes, in a computing system that includes one or more compute nodes that run clients, defining memory chunks, each memory chunk including multiple memory pages accessed by a respective client. Respective similarity-preserving signatures are computed for one or more of the memory chunks.

10/08/15
20150286270 

Method and system for reducing power consumption while improving efficiency for a memory management unit of a portable computing device


A method and system for reducing power consumption while improving efficiency of a memory management unit of a portable computing device include determining if data of a memory request exists within a first memory element external to the memory management unit. The first memory element may include a cache.

10/08/15
20150286269 

Method and system for reducing power consumption while improving efficiency for a memory management unit of a portable computing device


A method and system for reducing power consumption while improving efficiency of a memory management unit of a portable computing device are described. The method and system include determining if data of a memory request exists within a first memory element external to the memory management unit.

10/01/15
20150278083 

Conditional processing method and apparatus


A conditional processing method and apparatus for efficient memory management are provided. A conditional processing method includes receiving a data stream including a plurality of elements; decoding the received data stream; generating a parse tree by loading the decoded data stream; determining whether a parsingswitch element is detected while generating the parse tree; and if the parsingswitch element is detected, loading at least one child element of the detected parsingswitch element in a memory, based on at least one attribute of the detected parsingswitch element..
Samsung Electronics Co., Ltd.


10/01/15
20150278082 

Information processing device, memory management method, and recording medium that ensure versatile memory management


An information processing device includes a memory and a control unit. The memory is employed as a program work area.
Kyocera Document Solutions Inc.




Memory Management topics: Memory Management, Virtual Machine, Storage Device, Volatile Memory, Data Processing, Logical Unit, Virtual Memory, Computer System, Dynamic Data, Base Memory, Database Management System, Data Storage, Defragment, Compatibility, Object Code

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