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Memory Management patents

      

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 Extended error correction coding data storage patent thumbnailExtended error correction coding data storage
A memory management system and a method of managing a memory device are described. The system includes a memory device with a memory array to store data and associated error correction coding (ecc) bits and an extended correction table.
International Business Machines Corporation


 Extended error correction coding data storage patent thumbnailExtended error correction coding data storage
A memory management system and a method of managing a memory device are described. The system includes a memory device with a memory array to store data and associated error correction coding (ecc) bits and an extended correction table.
International Business Machines Corporation


 Virtual one-time programmable memory management patent thumbnailVirtual one-time programmable memory management
A virtual memory including virtual addresses may be generated. A first virtual address of the virtual memory may be mapped to a first physical address of a one-time programmable (otp) memory of a device.
Cryptography Research, Inc.


 Memory management method and apparatus patent thumbnailMemory management method and apparatus
A memory management method includes determining a stride value for stride access by referring to a size of two-dimensional (2d) data, and allocating neighboring data in a vertical direction of the 2d data to a plurality of banks that are different from one another according to the determined stride value. Thus, the data in the vertical direction may be efficiently accessed by using a memory having a large data width..
Samsung Electronics Co., Ltd.


 Systems and methods for utilizing wear leveling windows with non-volatile memory systems patent thumbnailSystems and methods for utilizing wear leveling windows with non-volatile memory systems
Systems and methods for utilizing wear leveling windows with non-volatile memory systems are disclosed. In one implementation, a memory management module of a non-volatile memory system compares a metric reflecting wear of a memory block to a wear leveling window and determines whether a wear leveling indicator associated with the memory block restricts performing a wear leveling operation on the memory block.
Sandisk Technologies Inc.


 Memory management method, memory storage device and memory controlling circuit unit patent thumbnailMemory management method, memory storage device and memory controlling circuit unit
A memory management method, a memory storage device and a memory controlling circuit unit are provided. The method comprises: obtaining an erased state voltage of a first memory cell and a programmed state voltage of the first memory cell, where the first memory cell is operated in a first programming mode; and operating the first memory cell in a second programming mode if a width of a gap between the erased state voltage and the programmed state voltage is larger than a first threshold value.
Phison Electronics Corp.


 Error vector readout from a memory device patent thumbnailError vector readout from a memory device
A memory management system and method of managing output data resulting from a memory device storing raw data and error correction coding (ecc) bits are described. The system includes a controller to receive a read command and control a memory device based on the read command, the memory device to store raw data and error correction coding (ecc) bits and output the raw data and the ecc bits corresponding with memory addresses specified in the read command, and an ecc decoder to output an error vector associated with the memory addresses based on the raw data and the ecc bits corresponding with the memory addresses output by the memory device, the error vector associated with the memory addresses indicating errors in the raw data corresponding with the memory addresses.
International Business Machines Corporation


 Error vector readout from a memory device patent thumbnailError vector readout from a memory device
A memory management system and method of managing output data resulting from a memory device storing raw data and error correction coding (ecc) bits are described. The system includes a controller to receive a read command and control a memory device based on the read command, the memory device to store raw data and error correction coding (ecc) bits and output the raw data and the ecc bits corresponding with memory addresses specified in the read command, and an ecc decoder to output an error vector associated with the memory addresses based on the raw data and the ecc bits corresponding with the memory addresses output by the memory device, the error vector associated with the memory addresses indicating errors in the raw data corresponding with the memory addresses.
International Business Machines Corporation


 Memory data versioning patent thumbnailMemory data versioning
A memory management unit receives a transaction request to perform an operation with respect to data in memory, the transaction request including control information. The memory management unit identifies, based on the control information, one of a plurality of versions of a given memory data, where the plurality of versions of the given memory data include a first version of the given memory data and a second version of the given memory data that is modified from the first version.
Hewlett Packard Enterprise Development Lp


 Systems, methods and devices for integrating end-host and network resources in distributed memory patent thumbnailSystems, methods and devices for integrating end-host and network resources in distributed memory
Systems, methods and devices for distributed memory management comprising a network component configured for network communication with one or more memory resources that store data and one or more consumer devices that use data, the network component comprising a switching device in operative communication with a mapping resource, wherein the mapping resource is configured to associate mappings between data addresses associated with memory requests from a consumer device relating to a data object and information relating to a storage location in the one or more memory resources associated with the data from the data object, wherein each data address has contained therein identification information for identifying the data from the data object associated with that data address; and the switching device is configured to route memory requests based on the mappings.. .
Coho Data, Inc.


Object memory management unit

Techniques to facilitate enhanced addressing of local and network resources from a computing system are provided herein. In one implementation, a method of operating an object-based memory management unit on a computing system to unify addressing of local and network resources includes maintaining a mapping of virtual addresses to local addresses and network addresses, and identifying resource requests that use the virtual addresses.
Colortokens, Inc.

System and memory management

Embodiments of system and methods for managing memory cells are disclosed, where a memory priority map is generated based on at least one testing procedure, and memory cells of a memory device are allocated to at least one application executed in a computing system by the memory priority map and defined allocating regulations. Further, whenever a fresh memory testing procedure is executed, the memory priority map is updated..
Hermes Testing Solutions Inc.

Object memory management unit

Techniques to facilitate enhanced addressing of local and network resources from a computing system are provided herein. In one implementation, a method of configuring an object memory management unit (ommu) for a computing system includes transferring a request to at least one network configuration resource for ommu configuration information, and receiving the ommu configuration information from the at least one network resource.
Colortokens, Inc.

Memory management

A data processing system 4 includes a translation lookaside buffer 6 storing mapping data entries 10 indicative of virtual-to-physical address mappings for different regions of physical addresses. A hint generator 20 coupled to the translation lookaside buffer 6 generates hint data in dependence upon the storage of mapping data entries within the translation lookaside buffer 6.
Arm Limited

Object memory management unit

Techniques to facilitate enhanced addressing of local and network resources from a computing system are provided herein. In one implementation, a method of operating an object-based memory management unit on a computing system to unify addressing of local and network resources includes maintaining a mapping of virtual addresses to local addresses and network addresses, and identifying resource requests that use the virtual addresses.
Colortokens, Inc.

Moving picture coding apparatus and moving picture decoding apparatus

A video encoder (70) for coding moving pictures comprising a buffer (16c) with a plurality of memory areas capable of storing frames composed of top fields and bottom fields, a motion estimation unit (19) operable to code, field by field, inputted pictures performing moving estimation and moving compensation by referring, field by field, to the picture data stored in a memory area, a motion compensation unit (16d), a subtractor (11), a transformation unit (13) and a quantization unit (14), a memory management unit (71) operable to manage, frame by frame, a plurality of memory areas, an inverse quantization unit (16a) and inverse discrete cosine transform unit (16b) operable to decode picture data in coded fields and store the picture data in the decoded field in any of the plurality of memory areas under the management by the memory management unit (71).. .
Godo Kaisha Ip Bridge 1

Moving picture coding apparatus and moving picture decoding apparatus

A video encoder (70) for coding moving pictures comprising a buffer (16c) with a plurality of memory areas capable of storing frames composed of top fields and bottom fields, a motion estimation unit (19) operable to code, field by field, inputted pictures performing moving estimation and moving compensation by referring, field by field, to the picture data stored in a memory area, a motion compensation unit (16d), a subtractor (11), a transformation unit (13) and a quantization unit (14), a memory management unit (71) operable to manage, frame by frame, a plurality of memory areas, an inverse quantization unit (16a) and inverse discrete cosine transform unit (16b) operable to decode picture data in coded fields and store the picture data in the decoded field in any of the plurality of memory areas under the management by the memory management unit (71).. .
Godo Kaisha Ip Bridge 1

Synchronizing updates of page table status indicators and performing bulk operations

A synchronization capability to synchronize updates to page tables by forcing updates in cached entries to be made visible in memory (i.e., in in-memory page table entries). A synchronization instruction is used that ensures after the instruction has completed that updates to the cached entries that occurred prior to the synchronization instruction are made visible in memory.
International Business Machines Corporation

Low complex deblocking filter decisions

The present disclosure relates to deblocking filtering, which may be advantageously applied for block-wise encoding and decoding of images or video signals. In particular, the present disclosure relates to an improved memory management in an automated decision on whether to apply or skip deblocking filtering for a block and to selection of the deblocking filter.
Sun Patent Trust

Method and selective and power-aware memory error protection and memory management

A method for providing selective memory error protection responsive to a predictable failure notification associated with at least one portion of a memory in a computing system includes: obtaining an active error correcting code (ecc) configuration corresponding to the portion of the memory; determining whether the active ecc configuration is sufficient to correct at least one error in the portion of the memory affected by the predictable failure notification; when the active ecc configuration is insufficient to correct the error, determining whether data corruption can be tolerated by an application running on the computing system; when data corruption cannot be tolerated by the application, determining whether a stronger ecc level is available and, if a stronger ecc level is available, increasing a strength of the active ecc configuration; and when data corruption can be tolerated, performing page reassignment and aggregation of non-critical data.. .
International Business Machines Corporation

Lambdalib: in-memory view management and query processing library for realizing portable, real-time big data applications

A big data processing system includes a memory management engine having stream buffers, realtime views and models, and batch views and models, the stream buffers coupleable to one or more stream processing frameworks to process stream data, the batch models coupleable to one or more batch processing frameworks; one or more processing engines including join, group, filter, aggregate, project functional units and classifiers; and a client layer engine communicating with one or more big data applications, the client layer engine handling an output layer, an api layer, and an unified query layer.. .
Nec Laboratories America, Inc.

Coalition based memory management

One or more memory coalitions of software processes are created and used to decide whether to perform memory reduction operations on a data processing system. One method in one embodiment includes adding a newly launched second process to an existing memory coalition in response to determining that the second process should be part of a memory coalition that includes a first process.
Apple Inc.

Nonvolatle memory device and memory system having the same, and related memory management, erase and programming methods

An erase method of a nonvolatile memory device includes setting an erase mode, and performing one of a normal erase operation and a quick erase operation according to the set erase mode. The normal erase operation is performed to set a threshold voltage of a memory cell to an erase state which is lower than a first erase verification level.
Samsung Electronics Co., Ltd.

Conservative garbage collection and access protection

A method of memory management can include creating an initial root set of pointers for a program during execution of the program and performing a marking process by iteratively marking referred objects of each pointer of the root set and expanding the root set with filtered, encoded pointers. The method also can include identifying each non-live object for any marked object as red-marked and performing, using a processor, a re-marking process on the root set in which red-marked objects are excluded.
International Business Machines Corporation

Memory and resource management in a virtual computing environment

Systems and techniques for memory and resource management in a virtual computing environment are disclosed herein. For example, in some embodiments, an apparatus for memory management in a virtual computing environment may include: a storage device; memory page comparison logic, coupled to the storage device, to determine that a first memory page of instructions, stored in the storage device, for a guest machine in the virtual computing environment is identical to a second memory page of instructions, stored in the storage device, for a host machine in the virtual computing environment, wherein the guest machine is hosted by the host machine; and merge logic, coupled to the memory page comparison logic, to, in response to a determination that the first memory page is identical to the second memory page, map the first memory page to the second memory page.
Intel Corporation

Data storage device and data processing system including the same

A data storage device includes a first scale-out controller configured to control a first non-volatile memory and a first volatile memory, a second scale-out controller configured to control a second non-volatile memory and a second volatile memory, and a controller configured to set a first memory management policy for the first non-volatile memory to be different from a second memory management policy for the second non-volatile memory.. .
Samsung Electronics Co., Ltd.

Integrated circuit device, information processing apparatus, memory management information storage device, mobile terminal apparatus, semiconductor integrated circuit device, and communication method using mobile terminal apparatus

A memory region on an ic card has a hierarchical structure. Each application allocated on the memory region is registered in a directory, and the memory region is managed in directory units.
Sony Corporation

Effective memory management for host objects in a runtime environment with embedded garbage-collected based dynamic language

A system for improving memory management in a hybrid programming environment where a server program receives a request to execute a script. The server program instructs an embedded script engine to execute the script.
International Business Machines Corporation

Memory management

A multiple stage memory management unit (mmu) comprises a first mmu stage configured to translate an input virtual memory address to a corresponding intermediate memory address, the first mmu stage generating a set of two or more intermediate memory addresses including the corresponding intermediate memory address; and a second mmu stage configured to translate an intermediate memory address provided by the first mmu stage to a physical memory address, the second mmu stage providing, in response to an intermediate memory address received from the first mmu stage, a set of two or more physical memory addresses including the physical memory address corresponding to the intermediate memory address received from the first mmu stage; the first mmu stage being configured to provide to the second mmu stage for translation, intermediate memory addresses in the set other than any intermediate memory addresses in the set for which the second mmu stage will provide a physical memory address as a response to translation of one of the other intermediate memory addresses in the set.. .
Arm Limited

Command-driven translation pre-fetch for memory management units

Methods and systems for pre-fetching address translations in a memory management unit (mmu) of a device are disclosed. In an embodiment, the mmu receives a pre-fetch command from an upstream component of the device, the pre-fetch command including an address of an instruction, pre-fetches a translation of the instruction from a translation table in a memory of the device, and stores the translation of the instruction in a translation cache associated with the mmu..
Qualcomm Incorporated

Runtime memory management using multiple memory managers

Embodiments are directed towards managing memory for an application be executing in a managed runtime environment. Managed peer objects may be generated to correspond to native objects executing in a native runtime environment such that memory may be allocated for managed peer objects.
Xamarin Inc.

Memory management in virtualized computing

Apparatuses, methods and storage media associated with memory management in virtualized computing are disclosed herein. In embodiments, an apparatus may include a virtual machine manager to manage operations of a plurality of virtual machines, having a memory manager to manage allocation and de-allocation of physical memory to and from the plurality of virtual machines.
Intel Corporation

Apparatuses for securing program code stored in a non-volatile memory

An embodiment of an apparatus for securing program code stored in a non-volatile memory is introduced. A non-volatile memory contains a first region and a second region.
Nuvoton Technology Corporation

Method and memory management

One or more circuits of a device may comprise a memory. A first portion of a first block of the memory may store program code and/or program data, a second portion of the first block may store an index associated with a second block of the memory, and a third portion of the first block may store an indication of a write status of the first portion.
Blackbird Technology Holdings, Inc.

Handling address translation requests

A memory management unit comprises an interface for receiving an address translation request from a device, the address translation request specifying a virtual request to be translated. Translation circuitry translates the virtual address into an intermediate address different from a physical address directly specifying a memory location.
Arm Limited

Memory management

A method of operation of a host data processing system which provides a virtual operating environment for one or more guest data processing systems comprises: initiating a transaction for translation of a guest system memory address to a host system physical address in response to a transaction request from a device overseen by a guest system for access to system memory at that guest system memory address; storing identification information relating to that transaction including at least data identifying device which requested the transaction; detecting a translation error condition in respect of that transaction; and handling a detected error condition by: (i) providing information indicative of the translation error condition to the guest system overseeing the device which requested the transaction; (ii) receiving a command from the guest system in respect of that transaction, the command from the guest system comprising information identifying the device which requested the transaction; and (iii) validating the received command for execution, by comparing the stored identification information for that transaction with at least the identity of the device identified by the command.. .
Arm Limited

Memory management

A method of operation of a host data processing system which provides a virtual operating environment for one or more guest data processing systems comprises: initiating a transaction for translation of a guest system memory address to a host system physical address in response to a transaction request from a device overseen by a guest system for access to system memory according to that guest system memory address; storing identification information relating to each transaction including at least data identifying the device which requested the transaction; for a stalled transaction, being a transaction incurring an error condition which is potentially resolvable by the guest system overseeing the device which requested the transaction: (i) storing identification information relating to that transaction including at least data identifying the device which requested the transaction; (ii) providing information indicative of the translation error condition to the guest system overseeing the device which requested the transaction; and (iii) deferring continued handling of the stalled transaction until a subsequent command is received from that guest system relating to the stalled transaction; detecting initiation of a closure process relating to a guest system; and in response to initiation of the closure process, initiating cancellation of any currently stalled transactions for devices overseen by that guest system for which a command has not yet been received from that guest system.. .
Arm Limited

Systems and methods for implementing power collapse in a memory

A power management system for stack memory thread tasks according to some examples of the disclosure may include a non-collapsible memory region, a collapsible memory region configured below the non-collapsible memory region, a memory management unit in communication with the non-collapsible memory region and the collapsible memory region, the memory management unit operable to allocate a portion of the non-collapsible memory region and a portion of the collapsible memory region to a thread task upon initialization of the thread task and power down the portion of the collapsible memory region allocated to the thread task upon receiving a power down command.. .
Qualcomm Incorporated

Efficient memory management system for computers supporting virtual machines

The translation of virtual guest addresses to host physical addresses in a virtualized computer system provides a compound page table that may simultaneously support nested-paging and shadow-paging for different memory regions. Memory regions with stable address mapping, for example, holding program code, may be treated using shadow-paging while memory regions with dynamic address mapping, for example, variable storage, may be treated using nested-paging thereby obtaining the benefits of both techniques..
Wisconsin Alumni Research Foundation

Role based cache coherence bus traffic control

A method for controlling cache snoop and/or invalidate coherence traffic for specific caches based on transaction attributes is described. A memory management unit (mmu) determines one or more transaction attributes for a cache coherence transaction from a requesting processor.
Qualcomm Incorporated

Memory management system and method

A memory system and method of operating the same is described, where the memory system is used to store data in a raided manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received.
Violin Memory Inc:

Method and system for contiguous harq memory management with memory splitting

Apparatuses (including user equipment (ue) and modem chips for ues), systems, and methods for ue downlink hybrid automatic repeat request (harq) buffer memory management are described. In one method, the entire ue dl harq buffer memory space is pre-partitioned according to the number and capacities of the ue's active carrier components.
Samsung Electronics Co., Ltd.

Parallel garbage collection implemented in hardware

Embodiments of the invention provide a method and system for dynamic memory management implemented in hardware. In an embodiment, the method comprises storing objects in a plurality of heaps, and operating a hardware garbage collector to free heap space.
International Business Machines Corporation

Bifurcated memory management for memory elements

Bifurcated memory management for memory elements techniques are disclosed. In one aspect, a memory element includes a self-managed portion and a portion that is managed by a remote host.
Qualcomm Incorporated

Mechanism for tracking tainted data

The disclosure relates in some aspects to protecting systems and data from maliciously caused destruction. Data integrity is maintained by monitoring data to detect and prevent potential attacks.
Qualcomm Incorporated

Memory management method, memory control circuit unit and memory storage apparatus

The present disclosure provides a memory management method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes physical programming units, each of which includes multiple bits.
Phison Electronics Corp.

Dynamic code generation and memory management for component object model data constructs

Dynamic code generation and memory management techniques are provided for component object model (com) objects with corresponding representations in script code and native code. A browser component can receive script code including the code representing the com object and a marshaling component is provided that marshals, based on a request for native code representing the com object, the code representing the com object to the native code based on a pre-constructed intermediate data structure.
Microsoft Technology Licensing, Llc

Techniques for mapping device addresses to physical memory addresses

A data processing system includes a main storage, an input/output memory management unit (iommu) coupled to the main storage, a peripheral component interconnect (pci) device coupled to the iommu, and a mapper. The system is configured to allocate an amount of physical memory in the main storage and the iommu is configured to provide access to the main storage and to map a pci address from the pci device to a physical memory address within the main storage.
International Business Machines Corporation

Memory management method, memory control circuit unit and memory storage apparatus

A memory management method for a rewritable non-volatile memory module is provided. The rewritable non-volatile memory module has a plurality of devices.
Phison Electronics Corp.

Object memory fabric performance acceleration

Embodiments of the invention provide systems and methods for managing processing, memory, storage, network, and cloud computing to significantly improve the efficiency and performance of processing nodes. Embodiments described herein can provide transparent and dynamic performance acceleration, especially with big data or other memory intensive applications, by reducing or eliminating overhead typically associated with memory management, storage management, networking, and data directories.
Ultrata Llc

Cache operations for memory management

In accordance with the present description, cache operations for a memory-sided cache in front of a backing memory such as a byte-addressable non-volatile memory, include combining at least two of a first operation, a second operation and a third operation, wherein the first operation includes evicting victim cache entries from the cache memory in accordance with a replacement policy which is biased to evict cache entries having clean cache lines over evicting cache entries having dirty cache lines. The second operation includes evicting victim cache entries from the primary cache memory to a victim cache memory of the cache memory, and the third operation includes translating memory location addresses to shuffle and spread the memory location addresses within an address range of the backing memory.



Memory Management topics:
  • Memory Management
  • Virtual Machine
  • Storage Device
  • Volatile Memory
  • Data Processing
  • Logical Unit
  • Virtual Memory
  • Computer System
  • Dynamic Data
  • Base Memory
  • Database Management System
  • Data Storage
  • Defragment
  • Compatibility
  • Object Code


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    This listing is a sample listing of patent applications related to Memory Management for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Memory Management with additional patents listed. Browse our RSS directory or Search for other possible listings.


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