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Memory Management patents

      

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 Bank issued contactless payment card used in transit fare collection patent thumbnailBank issued contactless payment card used in transit fare collection
An apparatus such as a mobile phone includes a contactless smart card or payment device, where the smart card is intended for use in both commerce transaction payment and transit fare payment (or other venue access) environments. The payment device may function as both an electronic wallet for commerce transactions and as a transit system card, for access to and fare payment of transit services.

 Wand: concurrent boxing system for all pointers with or without garbage collection patent thumbnailWand: concurrent boxing system for all pointers with or without garbage collection
Boxed pointers are disclosed, for all pointers, for safe and sequential or parallel use. Since a pointer box can be arbitrarily large, it supports any fat pointer encoding possible.

 System and  managing access requests to a memory storage subsystem patent thumbnailSystem and managing access requests to a memory storage subsystem
Embodiments of this disclosure relate to improving solid-state non-volatile memory management. Embodiments improve the management of solid-state non-volatile memory by providing an execution manager responsible for controlling the timing of providing a request to a memory unit for execution.
Western Digital Technologies, Inc.


 Nonvolatile memory device and storage device comprising the same,  storing bad block management information into the same patent thumbnailNonvolatile memory device and storage device comprising the same, storing bad block management information into the same
A nonvolatile memory device is provided. The nonvolatile memory device includes a memory cell array comprising a first area that stores memory management information and a second area that stores user data, a decoder configured to select at least one of rows of the first area or the second area based on an address, a page buffer configured to store data in memory cells connected to the selected at least one row or to detect data stored in the memory cells, and control logic configured to control the decoder and the page buffer in response to a specific command, to access the first area.
Samsung Electronics Co., Ltd.


 Memory management patent thumbnailMemory management
Apparatus, systems, and methods to manage memory operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to retrieve a global sequence number from a memory device, receive a read request for data stored in a logical block address in the memory device, retrieve a media sequence number from the logical block address in the memory device, and return a null response in lieu of the data stored in the logical block address when the media sequence number is older than the global sequence number.
Intel Corporation


 Memory management method, memory control circuit unit and memory storage device patent thumbnailMemory management method, memory control circuit unit and memory storage device
A memory management method, a memory control circuit unit and a memory storage device are provided. In an exemplary embodiment, the memory management method includes: receiving a first write command and first write data and obtaining a first number; programming the first write data and moving first storage data stored in a plurality of first physical programming units, where a total number of the first physical programming units conforms to the first number; receiving a second write command and second write data and obtaining a second number; programming the second write data and moving second storage data stored in a plurality of second physical programming units, where a total number of the second physical programming units conforms to the second number; and erasing at least one physical erasing unit.
Phison Electronics Corp.


 Memory management within secure migratable architecture patent thumbnailMemory management within secure migratable architecture
Methods and systems for executing virtualized processes on a computing system are disclosed, including techniques for memory management when executing such processes. One method includes allocating a portion of memory to a process hosted by an operating system of a computing system having a first computing architecture, the process comprising a firmware environment implementing a second computing architecture different from the first computing architecture, the first computing architecture applying virtual addressing to the portion of memory.
Unisys Corporation


 Method for memory management in virtual machines, and corresponding system and computer program product patent thumbnailMethod for memory management in virtual machines, and corresponding system and computer program product
A method for memory management includes in a virtual-machine monitor of a virtualization platform allocating in a guest operating system of the virtual machines guest balloon memory modules of variable memory size. Memory parameters of a given virtual machine are read.
Eco4cloud S.r.l.


 Electronic devices and memory management methods thereof patent thumbnailElectronic devices and memory management methods thereof
Electronic devices and memory management methods thereof are provided. Memory management methods may include setting page data of a nonvolatile memory as a read/write mode, copying the page data of the nonvolatile memory to a dynamic random access memory (dram) and setting the page data of the dram copied from the nonvolatile memory as a read only mode..
Samsung Electronics Co., Ltd.


 Cache decice and memory system patent thumbnailCache decice and memory system
A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages.
Kabushiki Kaisha Toshiba


Memory management method, memory control circuit unit and memory storage apparatus

A memory management method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: receiving a first write command and writing data corresponding to the first write command into a first spare physical erasing unit; detecting an amount of second spare physical erasing units excluding the first spare physical erasing unit; determining whether the amount of the second spare physical erasing units is less than a threshold value; and performing a first procedure if the amount of the second spare physical erasing units is less than the threshold value.
Phison Electronics Corp.

Memory management for reception of wireless communications

A base station or user equipment (ue) may manage scheduling of code blocks to be transmitted and manage memory interface usage to enhance memory read and write operations and provide for enhanced efficiency for decoding of retransmissions of code blocks. In some aspects, a base station or ue may identify an available throughput, or budget, for performing read and write operations to a memory.
Qualcomm Incorporated

System and device for preventing attacks in real-time networked environments

Disclosed are various embodiments of a system or method for the transparent handling of real-time streaming application-level data. The disclosed embodiments permit the identification and modification of specified file patterns from within the live stateful data transactions across computer networks.
Board Of Regents, The University Of Texas System

Multi-page check hints for selective checking of protected container page versus regular page type indications for pages of convertible memory

A processor of an aspect includes at least one translation lookaside buffer (tlb) and a memory management unit (mmu). Each tlb is to store translations of logical addresses to corresponding physical addresses.
Intel Corporation

Access log and address translation log for a processor

A processor maintains an access log indicating a stream of cache misses at a cache of the processor. In response to each of at least a subset of cache misses at the cache, the processor records a corresponding entry in the access log, indicating a physical memory address of the memory access request that resulted in the corresponding miss.
Ati Technologies Ulc

Shared virtual address space for heterogeneous processors

A processor uses the same virtual address space for heterogeneous processing units of the processor. The processor employs different sets of page tables for different types of processing units, such as a cpu and a gpu, wherein a memory management unit uses each set of page tables to translate virtual addresses of the virtual address space to corresponding physical addresses of memory modules associated with the processor.
Advanced Micro Devices, Inc.

Application driven hardware cache management

A processor includes a processing core to generate a memory request for an application data in an application. The processor also includes a virtual page group memory management (vpgmm) unit coupled to the processing core to specify a caching priority (cp) to the application data for the application.
Intel Corporation

Light-weight on-chip signal monitor with integrated memory management and data collection

Embodiments of a device and method to automatically acquire signal quality metrics in a digital communication system are disclosed. The device may include acquisition means to sample the likelihood of a digital communication signal passing through a grid of time and amplitude regions, and storage means by which such likelihood measurements may be accumulated in a computer memory array for analysis.
Finisar Corporation

Memory management unit and operating method thereof

A memory management unit mmu for managing virtual memory for a plurality of cores includes a plurality of translation lookaside buffers tlbs each corresponding to each of the cores; a plurality of page tables each corresponding to each of the cores and to each of the tlbs, and each synchronized with a corresponding tlb, a meta page including virtual page-physical page mapping information included in the plurality of page tables, one of the plurality of page tables being a main page table; and the meta page including a shared bit field indicating whether or not the virtual page-physical page mapping information is stored in the plurality of tlbs.. .
Electronics And Telecommunications Research Institute

Memory allocation and recovery strategies for byte-addressable non-volatile ram (nvram)

Disclosed herein are innovations in memory management and data recovery for systems that operate using storage class memory (scm), such as non-volatile ram (nvram). The disclosed innovations have particular application to production database systems, where reducing database downtime in the event of a system crash is highly desirable.
Sap Se

Transactional memory management techniques

Techniques for improved transactional memory management are described. In one embodiment, for example, an apparatus may comprise a processor element, an execution component for execution by the processor element to concurrently execute a software transaction and a hardware transaction according to a transactional memory process, a tracking component for execution by the processor element to activate a global lock to indicate that the software transaction is undergoing execution, and a finalization component for execution by the processor element to commit the software transaction and deactivate the global lock when execution of the software transaction completes, the finalization component to abort the hardware transaction when the global lock is active when execution of the hardware transaction completes.
Intel Corporation

Potentate: a cryptography-obfuscating, self-policing, pervasive distribution system for digital content

A system and method for self-policed, authenticated, offline/online, viral marketing and distribution of content such as software, text, and multimedia with effective copyright and license enforcement and secure selling. The system is based on key and cryptography hiding techniques, using source-to-source transformation for efficient, holistic steganography that systematically inflates and hides critical code by: computation interleaving; flattening procedure calls and obfuscating stack by de-stacking arguments; obfuscating memory management; and encoding scalars as pointers to managed structures that may be distributed and migrated all over the heap using garbage collection.

Memory protection unit, memory management unit, and microcontroller

A memory protection unit including hardware registers for entering address tables, a configuration memory for storing the address tables, a preconfigured hardware logic for managing the configuration memory, a data connection between the configuration memory and the hardware logic for loading the hardware registers, a first interface for controlling the loading by a computing core, and a second interface for writing to the configuration memory by the computing core.. .
Robert Bosch Gmbh

Memory management method, memory control circuit unit, and memory storage apparatus

A memory management method is provided according to an exemplary embodiment. The method includes: receiving a write command and determining whether a usage status of physical units associated to a storage area conforms to a first predetermined status; storing write data corresponding to the write command to at least one of physical units associated to a temporary area if the usage status of the physical units associated to the storage area conforms to the first predetermined status; associating the at least one physical unit storing the write data to the storage area; and allocating at least one logical unit to map the at least one physical unit associated to the storage area..
Phison Electronics Corp.

Selective error coding

A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place.
International Business Machines Corporation

Selective error coding

A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place.
International Business Machines Corporation

Memory management of data processing systems

Techniques for memory management of a data processing system are described herein. According to one embodiment, a memory usage monitor executed by a processor of a data processing system monitors memory usages of groups of programs running within a memory of the data processing system.
Apple Inc.

Microcontroller simple memory relocation function

A method and apparatus for microcontroller (mcu) memory relocation. The mcu includes a central processing unit (cpu) and memory, but lacks a memory management unit (mmu).
Renesas Electronics America Inc.

Exit-less movement of guest memory assigned to a device in a virtualized environment

Embodiments of the disclosure enable exit-less movement of guest memory assigned to a device in a virtualized environment. An example method comprises detecting, by a processing device of a host computer system, an event triggering a move/copy of a memory page residing at a first memory location that is mapped to a virtual address space of a virtual machine being hosted by the host computer system.
Red Hat Israel, Ltd.

Multi-threaded translation and transaction re-ordering for memory management units

Systems and methods relate to performing address translations in a multithreaded memory management unit (mmu). Two or more address translation requests can be received by the multithreaded mmu and processed in parallel to retrieve address translations to addresses of a system memory.
Qualcomm Incorporated

Speculative pre-fetch of translations for a memory management unit (mmu)

Systems and methods for pre-fetching address translations in a memory management unit (mmu) are disclosed. The mmu detects a triggering condition related to one or more translation caches associated with the mmu, the triggering condition associated with a trigger address, generates a sequence descriptor describing a sequence of address translations to pre-fetch into the one or more translation caches, the sequence of address translations comprising a plurality of address translations corresponding to a plurality of address ranges adjacent to an address range containing the trigger address, and issues an address translation request to the one or more translation caches for each of the plurality of address translations, wherein the one or more translation caches pre-fetch at least one address translation of the plurality of address translations into the one or more translation caches when the at least one address translation is not present in the one or more translation caches..
Qualcomm Incorporated

Providing memory management unit (mmu) partitioned translation caches, and related apparatuses, methods, and computer-readable media

Providing memory management unit (mmu) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, in one aspect, an apparatus comprising an mmu is provided.
Qualcomm Incorporated

Memory management method, memory storage device and memory control circuit unit

A memory management method, a memory storage device and a memory control circuit unit are provided. The memory management method includes: detecting a replacement physical unit number of a rewritable non-volatile memory module; adjusting an available capacity of the rewritable non-volatile memory module from a first available capacity to a second available capacity if the replacement physical unit number meets a default condition.
Phison Electronics Corp.

Access control for memory protection key architecture

A processing system includes a processing core to execute a task and a memory management unit, coupled to the core. The memory management unit includes a protection key register comprising a plurality of fields.
Intel Corporation

Extended error correction coding data storage

A memory management system and a method of managing a memory device are described. The system includes a memory device with a memory array to store data and associated error correction coding (ecc) bits and an extended correction table.
International Business Machines Corporation

Extended error correction coding data storage

A memory management system and a method of managing a memory device are described. The system includes a memory device with a memory array to store data and associated error correction coding (ecc) bits and an extended correction table.
International Business Machines Corporation

Virtual one-time programmable memory management

A virtual memory including virtual addresses may be generated. A first virtual address of the virtual memory may be mapped to a first physical address of a one-time programmable (otp) memory of a device.
Cryptography Research, Inc.

Memory management method and apparatus

A memory management method includes determining a stride value for stride access by referring to a size of two-dimensional (2d) data, and allocating neighboring data in a vertical direction of the 2d data to a plurality of banks that are different from one another according to the determined stride value. Thus, the data in the vertical direction may be efficiently accessed by using a memory having a large data width..
Samsung Electronics Co., Ltd.

Systems and methods for utilizing wear leveling windows with non-volatile memory systems

Systems and methods for utilizing wear leveling windows with non-volatile memory systems are disclosed. In one implementation, a memory management module of a non-volatile memory system compares a metric reflecting wear of a memory block to a wear leveling window and determines whether a wear leveling indicator associated with the memory block restricts performing a wear leveling operation on the memory block.
Sandisk Technologies Inc.

Memory management method, memory storage device and memory controlling circuit unit

A memory management method, a memory storage device and a memory controlling circuit unit are provided. The method comprises: obtaining an erased state voltage of a first memory cell and a programmed state voltage of the first memory cell, where the first memory cell is operated in a first programming mode; and operating the first memory cell in a second programming mode if a width of a gap between the erased state voltage and the programmed state voltage is larger than a first threshold value.
Phison Electronics Corp.

Error vector readout from a memory device

A memory management system and method of managing output data resulting from a memory device storing raw data and error correction coding (ecc) bits are described. The system includes a controller to receive a read command and control a memory device based on the read command, the memory device to store raw data and error correction coding (ecc) bits and output the raw data and the ecc bits corresponding with memory addresses specified in the read command, and an ecc decoder to output an error vector associated with the memory addresses based on the raw data and the ecc bits corresponding with the memory addresses output by the memory device, the error vector associated with the memory addresses indicating errors in the raw data corresponding with the memory addresses.
International Business Machines Corporation

Error vector readout from a memory device

A memory management system and method of managing output data resulting from a memory device storing raw data and error correction coding (ecc) bits are described. The system includes a controller to receive a read command and control a memory device based on the read command, the memory device to store raw data and error correction coding (ecc) bits and output the raw data and the ecc bits corresponding with memory addresses specified in the read command, and an ecc decoder to output an error vector associated with the memory addresses based on the raw data and the ecc bits corresponding with the memory addresses output by the memory device, the error vector associated with the memory addresses indicating errors in the raw data corresponding with the memory addresses.
International Business Machines Corporation

Memory data versioning

A memory management unit receives a transaction request to perform an operation with respect to data in memory, the transaction request including control information. The memory management unit identifies, based on the control information, one of a plurality of versions of a given memory data, where the plurality of versions of the given memory data include a first version of the given memory data and a second version of the given memory data that is modified from the first version.
Hewlett Packard Enterprise Development Lp

Systems, methods and devices for integrating end-host and network resources in distributed memory

Systems, methods and devices for distributed memory management comprising a network component configured for network communication with one or more memory resources that store data and one or more consumer devices that use data, the network component comprising a switching device in operative communication with a mapping resource, wherein the mapping resource is configured to associate mappings between data addresses associated with memory requests from a consumer device relating to a data object and information relating to a storage location in the one or more memory resources associated with the data from the data object, wherein each data address has contained therein identification information for identifying the data from the data object associated with that data address; and the switching device is configured to route memory requests based on the mappings.. .
Coho Data, Inc.

Object memory management unit

Techniques to facilitate enhanced addressing of local and network resources from a computing system are provided herein. In one implementation, a method of operating an object-based memory management unit on a computing system to unify addressing of local and network resources includes maintaining a mapping of virtual addresses to local addresses and network addresses, and identifying resource requests that use the virtual addresses.
Colortokens, Inc.

System and memory management

Embodiments of system and methods for managing memory cells are disclosed, where a memory priority map is generated based on at least one testing procedure, and memory cells of a memory device are allocated to at least one application executed in a computing system by the memory priority map and defined allocating regulations. Further, whenever a fresh memory testing procedure is executed, the memory priority map is updated..
Hermes Testing Solutions Inc.

Object memory management unit

Techniques to facilitate enhanced addressing of local and network resources from a computing system are provided herein. In one implementation, a method of configuring an object memory management unit (ommu) for a computing system includes transferring a request to at least one network configuration resource for ommu configuration information, and receiving the ommu configuration information from the at least one network resource.
Colortokens, Inc.

Memory management

A data processing system 4 includes a translation lookaside buffer 6 storing mapping data entries 10 indicative of virtual-to-physical address mappings for different regions of physical addresses. A hint generator 20 coupled to the translation lookaside buffer 6 generates hint data in dependence upon the storage of mapping data entries within the translation lookaside buffer 6.
Arm Limited

Object memory management unit

Techniques to facilitate enhanced addressing of local and network resources from a computing system are provided herein. In one implementation, a method of operating an object-based memory management unit on a computing system to unify addressing of local and network resources includes maintaining a mapping of virtual addresses to local addresses and network addresses, and identifying resource requests that use the virtual addresses.
Colortokens, Inc.

Moving picture coding apparatus and moving picture decoding apparatus

A video encoder (70) for coding moving pictures comprising a buffer (16c) with a plurality of memory areas capable of storing frames composed of top fields and bottom fields, a motion estimation unit (19) operable to code, field by field, inputted pictures performing moving estimation and moving compensation by referring, field by field, to the picture data stored in a memory area, a motion compensation unit (16d), a subtractor (11), a transformation unit (13) and a quantization unit (14), a memory management unit (71) operable to manage, frame by frame, a plurality of memory areas, an inverse quantization unit (16a) and inverse discrete cosine transform unit (16b) operable to decode picture data in coded fields and store the picture data in the decoded field in any of the plurality of memory areas under the management by the memory management unit (71).. .
Godo Kaisha Ip Bridge 1

Moving picture coding apparatus and moving picture decoding apparatus

A video encoder (70) for coding moving pictures comprising a buffer (16c) with a plurality of memory areas capable of storing frames composed of top fields and bottom fields, a motion estimation unit (19) operable to code, field by field, inputted pictures performing moving estimation and moving compensation by referring, field by field, to the picture data stored in a memory area, a motion compensation unit (16d), a subtractor (11), a transformation unit (13) and a quantization unit (14), a memory management unit (71) operable to manage, frame by frame, a plurality of memory areas, an inverse quantization unit (16a) and inverse discrete cosine transform unit (16b) operable to decode picture data in coded fields and store the picture data in the decoded field in any of the plurality of memory areas under the management by the memory management unit (71).. .
Godo Kaisha Ip Bridge 1



Memory Management topics:
  • Memory Management
  • Virtual Machine
  • Storage Device
  • Volatile Memory
  • Data Processing
  • Logical Unit
  • Virtual Memory
  • Computer System
  • Dynamic Data
  • Base Memory
  • Database Management System
  • Data Storage
  • Defragment
  • Compatibility
  • Object Code


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