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Memory Management patents



      
           
This page is updated frequently with new Memory Management-related patent applications. Subscribe to the Memory Management RSS feed to automatically get the update: related Memory RSS feeds. RSS updates for this page: Memory Management RSS RSS


Back-off mechanism for a peripheral page request log

Advanced Micro Devices

Back-off mechanism for a peripheral page request log

Transactional memory management techniques

Transactional memory management techniques

Transactional memory management techniques

Advanced Micro Devices

Methods and systems for moving and resizing i/o activity logs

Date/App# patent app List of recent Memory Management-related patents
04/16/15
20150106556
 Endurance translation layer (etl) and diversion of temp files for reduced flash wear of a super-endurance solid-state drive patent thumbnailnew patent Endurance translation layer (etl) and diversion of temp files for reduced flash wear of a super-endurance solid-state drive
A flash drive has increased endurance and longevity by reducing writes to flash. An endurance translation layer (etl) is created in a dram buffer and provides temporary storage to reduce flash wear.
Super Talent Electronics, Inc.
04/09/15
20150100818
 Back-off mechanism for a peripheral page request log patent thumbnailBack-off mechanism for a peripheral page request log
A system and method of managing requests from peripherals in a computer system are provided. In the system and method, an input/output memory management unit (iommu) receives a peripheral page request (ppr) from a peripheral.
Advanced Micro Devices, Inc.
04/09/15
20150100741
 Transactional memory management techniques patent thumbnailTransactional memory management techniques
Techniques for improved transactional memory management are described. In one embodiment, for example, an apparatus may comprise a processor element, an execution component for execution by the processor element to concurrently execute a software transaction and a hardware transaction according to a transactional memory process, a tracking component for execution by the processor element to activate a global lock to indicate that the software transaction is undergoing execution, and a finalization component for execution by the processor element to commit the software transaction and deactivate the global lock when execution of the software transaction completes, the finalization component to abort the hardware transaction when the global lock is active when execution of the hardware transaction completes.
04/09/15
20150100708
 Methods and systems for moving and resizing i/o activity logs patent thumbnailMethods and systems for moving and resizing i/o activity logs
A method of managing peripherals is performed in a device coupled to a processor in a computer system. For example, the method is performed in an input/output memory management unit (iommu) or a peripheral.
Advanced Micro Devices, Inc.
04/09/15
20150097847
 Managing memory regions to support sparse mappings patent thumbnailManaging memory regions to support sparse mappings
One embodiment of the present invention includes a memory management unit (mmu) that is configured to manage sparse mappings. The mmu processes requests to translate virtual addresses to physical addresses based on page table entries (ptes) that indicate a sparse status.
Nvidia Corporation
04/02/15
20150095611
 Method and processor for reducing code and latency of tlb maintenance operations in a configurable processor patent thumbnailMethod and processor for reducing code and latency of tlb maintenance operations in a configurable processor
A memory management unit (mmu) is disclosed for storing mappings between virtual addresses and physical addresses. The mmu includes a translation look-aside buffer (tlb) and a memory management unit controller.
Synopsys, Inc.
04/02/15
20150095610
 Multi-stage address translation for a computing device patent thumbnailMulti-stage address translation for a computing device
Providing for address translation in a virtualized system environment is disclosed herein. By way of example, a memory management apparatus is provided that comprises a shared translation look-aside buffer (tlb) that includes a plurality of translation types, each supporting a plurality of page sizes, one or more processors, and a memory management controller configured to work with the one or more processors.
Applied Micro Circuits Corporation
04/02/15
20150095563
 Memory management patent thumbnailMemory management
Apparatus, systems, and methods to manage memory operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to retrieve a global sequence number from a memory device, receive a read request for data stored in a logical block address in the memory device, retrieve a media sequence number from the logical block address in the memory device, and return a null response in lieu of the data stored in the logical block address when the media sequence number is older than the global sequence number.
03/26/15
20150089148
 Memory management unit patent thumbnailMemory management unit
A data processing apparatus is provided comprising a plurality of master devices configured to issue memory access requests including virtual addresses. A memory management unit is configured to receive memory access requests and to translate a virtual address included in a memory access request from a requesting master device into a physical address indicating a storage location in memory.
Arm Limited
03/26/15
20150089117
 Computer system, memory management method and program thereof patent thumbnailComputer system, memory management method and program thereof
A computer system, having a non-volatile storage unit (152), a main storage unit (151), and a data processor (102) including a memory management unit (102a) for managing a program stored in the non-volatile storage unit and the main storage unit to transfer a program stored in the non-volatile storage unit to the main storage unit, wherein the memory management unit (102a) includes a program storage control function of storing a program subjected to predetermined data conversion and a program yet to be subjected to predetermined data conversion in the non-volatile storage unit, and a function of combining programs subjected to predetermined data conversion so as not to bridge over a boundary between blocks at the execution of the program storage control function, as well as, at a first access to a certain block, expanding all the data included in the block to a corresponding block of the main storage unit.. .
Nec Corporation
03/19/15
20150082000

System-on-chip and address translation method thereof


A memory management unit comprises an address translation unit that receives a memory access request as a virtual address and translates the virtual address to a physical address. A translation lookaside buffer stores page descriptors of a plurality of physical addresses, the address translation unit determining whether a page descriptor of a received virtual address is present in the translation lookaside buffer.
Samsung Electronics Co., Ltd.
03/19/15
20150081983

Pre-fetch in a multi-stage memory management system


A memory management system for managing a memory and includes a multi-stage memory management unit including control circuitry and cache memory. The cache memory may have a respective translation look-aside buffer for each stage of the multi-stage memory management unit.
Stmicroelectronics International N.v.
03/12/15
20150070370

Memory management techniques


memory management techniques that permit an executing process to store content in memory and later retrieve that content from the memory, but that also permit a memory manager to discard that content to address memory pressure. A process executing on a computing device may notify a memory manager of the computing device that first memory space allocated to the process contains first content that is available for discard.
Microsoft Corporation
03/05/15
20150067296

I/o memory management unit providing self invalidated mapping


A memory management unit for 110 devices uses page table entries to translate virtual addresses to physical addresses. The page table entries include removal rules allowing the i/o memory management unit to delete page table entries without cpu involvement significantly reducing the cpu overhead involved in virtualized i/o data transactions..
Wisconsin Alumni Research Foundation
03/05/15
20150067289

Method and implementing garbage collection within a computing environment


An approach is provided for obtaining memory management information associated with a computing environment, processing the memory management information to determine one or more computing devices within the computing environment experiencing full garbage collection, and resetting memory of the one or more computing devices to correct the full garbage collection.. .
Verizon Patent And Licensing Inc.
03/05/15
20150067287

Distributed dynamic memory management unit (mmu)-based secure inter-processor communication


A first processor and a second processor are configured to communicate secure inter-processor communications (ipcs) with each other. The first processor effects secure ipcs and non-secure ipcs using a first memory management unit (mmu) to route the secure and non-secure ipcs via a memory system.
Qualcomm Incorporated
03/05/15
20150067264

Method and memory management


In some embodiments, a method of managing cache memory includes identifying a group of cache lines in a cache memory, based on a correlation between the cache lines. The method also includes tracking evictions of cache lines in the group from the cache memory and, in response to a determination that a criterion regarding eviction of cache lines in the group from the cache memory is satisfied, selecting one or more (e.g., all) remaining cache lines in the group for eviction..
Advanced Micro Devices, Inc.
03/05/15
20150067234

Unified memory controller for heterogeneous memory on a multi-chip package


An enhanced multi chip package (emcp) is provided including a unified memory controller. The umc is configured to manage different types of memory, such as nand flash memory and dram on the emcp.
Qualcomm Incorporated
03/05/15
20150067200

Memory management for finite automata processing


Matching at least one regular expression pattern in an input stream may be optimized by initializing a search context in a run stack based on (i) partial match results determined from walking segments of a payload of a flow through a first finite automation and (ii) a historical search context associated with the flow. The search context may be modified via push or pop operations to direct at least one processor to walk segments of the payload through the at least one second finite automation.
Cavium, Inc.
03/05/15
20150063367

Providing oversubscription of pipeline bandwidth


A system for providing oversubscription of pipeline bandwidth comprises a steer module, an absorption buffer, an ingress packet processor (ipp), a memory management unit (mmu), and a main packet buffer. The steer module receives packets that include start of packet (sop), middle of packet (mop), and end of packet (eop) cells, attaches a packet identifier to the cells, passes the mop and eop cells to the mmu, and stores the sop cells and eop metadata in the absorption buffer.
Broadcom Corporation
02/26/15
20150058717

Document editing apparatus, non-transitory computer-readable recording medium and document editing method


Disclosed is a document editing apparatus including: a display unit; a page changing unit; an operating unit; an editing unit; an undo and redo memory; an undo and redo instruction unit; a memory management unit to manage an upper limit of number of storable editing history data including the editing history data of the editing operation performed in the displayed part; and an undo and redo performance unit to perform the undo operation by tracing back only the editing history data of the editing operation performed in the part displayed when the instruction to perform the undo operation is received, and to perform the redo operation by tracing back only the editing history data of the editing operation performed in the part displayed when the instruction to perform the redo operation is received.. .
Konica Minolta, Inc.
02/26/15
20150058578

Enhanced pre-fetch in a memory management system


A memory management unit may send page table walk requests to a page table descriptor in a main memory system and receive address translation information, with the page table walk requests including information that specifies an amount of further address translation information, and receive the further address translation information. The cache unit may intercept the page table walk requests, and modify content of the intercepted page table walk requests so the information that specifies the amount of further address translation information is extended from a first amount to a second amount greater than the first amount.
Stmicroelectronics International N.v.
02/26/15
20150058541

Memory management device and method


According to one embodiment, a device includes a determination unit, compression unit, selecting unit, write updating unit, writing unit. The determination unit determines whether to compress write data based on specific information.
Kabushiki Kaisha Toshiba
02/19/15
20150052506

Runtime memory throttling


A system that implements a memory management policy at runtime when receiving a syntax tree in response to initiating the compiling of software code identifies a plurality of calls within the syntax tree and modifies each the plurality of calls with a corresponding memory-modified call to create a plurality of memory-modified calls. Each memory-modified call is linked with a memory management class and the modifying occurs during the compiling of the software code.
Oracle International Corporation
02/19/15
20150052319

Memory management methods and systems for page-out mechanism


memory management methods and systems for page-out mechanism are provided. A page-out mechanism is performed via an os (operating system) based on a parameter of the page-out mechanism, wherein the page-out mechanism moves data from a memory to a storage unit.
Htc Corporation
02/12/15
20150046702

Embedded encryption/secure memory management unit for peripheral interface controller


In an embodiment, a peripheral interface controller may include an inline cryptographic engine which may encrypt data being sent over a peripheral interface and decrypt data received from the peripheral interface. The encryption may be transparent to the device connected to the peripheral interface that is receiving/supplying the data.
Apple Inc.
02/12/15
20150046651

Method for storing modified instruction data in a shared cache


A processor may include a cache configured to store instructions and memory data for the processor. The cache may store instructions in which a relative address, such as for a branch instruction has been calculated, such that the instruction stored in the cache is modified from how the instruction is stored in main memory.
Oracle International Corporation
02/05/15
20150040146

Memory management


At least certain embodiments of the present disclosure include a method for memory management of a view of an application displayed on a display of a device. The method includes constructing a data structure having a hierarchy of layers with at least one layer being associated with the view.
Apple Inc.
02/05/15
20150039793

Network interface card for a computing node of a parallel computer accelerated by general purpose graphics processing units, and related inter-node communication method


A network interface card (nic) for a cluster node for parallel calculation on multi-core gpu is described. The nic has a cluster network including a host and a host memory, a graphics processing unit (gpu) with a gpu memory, a bus and the nic.
Istituto Nazionale Di Fisica Nucleare
01/29/15
20150032986

Memory block management systems and methods


A system for real-time operating system memory block and message management is disclosed. The real-time operating system enables different processes to migrate an allocated memory block from one type of memory block to another type of memory block, and to reliably release the block back to its correct pool of origin.
01/29/15
20150032977

Memory management system, method and computer program product


According to one aspect of the present disclosure a method and technique for managing memory access is disclosed. The method includes setting a memory databus utilization threshold for each of a plurality of processors of a data processing system to maintain memory databus utilization of the data processing system at or below a system threshold.
International Business Machines Corporation
01/29/15
20150032972

Methods and supporting persistent memory


A processing device features a processing unit, a memory management system, and persistent memory in a persistent memory domain. The processing device provides an enhanced write-back (wb-e) memory space for an application running on the processing unit.
01/01/15
20150006844

Methods, systems, and devices for management of a memory system


Methods, devices, and systems for a memory management system within an electronic device are disclosed, such as those wherein the memory management system is external to and compatible with architectures of currently existing operating systems. One such memory management system may include a power savings manager configured to be invoked by a memory allocation manager.
Micron Technology, Inc.
01/01/15
20150006843

Thread-based memory management with garbage collection


Systems and methods for thread-based memory management may include activating a processing thread. The memory may include a first region and a second region with the first region having several segments.
Sap Ag
01/01/15
20150006557

Conservative garbage collecting and tagged integers for memory management


Aspects for conservative garbage collecting are disclosed. In one aspect, root objects included in a call stack are identified, which comprise integers and pointers.
Microsoft Corporation
12/25/14
20140380017

Memory management and allocation using free-list


A method of managing a memory of an apparatus includes maintaining a plurality of lists of identifiers that each has an associated size value, wherein each identifier identifies a corresponding region of the memory that had been allocated for a process but that is currently not required by any of the one or more processes. When a process requests allocation of a region of the memory: one of the lists is identified that has an associated size value suitable for the allocation request; and if that list is not empty, a region of the memory is identified to the process by one of the identifiers that identifier is removed from that list, and, otherwise, a region of the memory is allocated with a size of the identified associated size value and the allocated region of the memory is identified the process..
Freescale Semiconductor, Inc.
12/18/14
20140372726

Memory management method and apparatus


A method for managing memory using a virtual memory manager includes receiving a memory allocation request, allocating memory of a physical address space in response to the memory allocation request, mapping an address value of the memory allocated in the physical address space to consecutive primary virtual address space, and mapping the address value of the primary virtual address space to one of a first and second secondary virtual address spaces to process a new memory allocation request in a situation where memory a fragmentation occurs. Other embodiments are also disclosed.
Samsung Electronics Co., Ltd.
12/18/14
20140372694

Methods and cut-through cache management for a mirrored virtual volume of a virtualized storage system


Methods and apparatus for cut-through cache memory management in write command processing on a mirrored virtual volume of a virtualized storage system, the virtual volume comprising a plurality of physical storage devices coupled with the storage system. Features and aspects hereof within the storage system provide for receipt of a write command and associated write data from an attached host.
Netapp, Inc.
12/11/14
20140365834

Memory management tools


The present technology monitors events that allocate and deallocate virtual memory regions in a device, wherein the events include system calls from user space. The system can generate a log of events, and based on the log of events, track regions of virtual memory allocated and deallocated via the events.
12/11/14
20140365821

Independent management of data and parity logical block addresses


A data storage method includes identifying, in a set of data items associated with respective logical addresses for storage in a memory, a first subset of the logical addresses associated with the data items containing application data, and a second subset of the logical addresses associated with the data items containing parity information that has been calculated over the application data. The data items associated with the first identified subset are stored in one or more first physical memory areas of the memory, and the data items associated with the second identified subset are stored in one or more second physical memory areas of the memory, different from the first physical memory areas.
12/04/14
20140359240

Virtualizing processor memory protection with "l1 iterate and l2 drop/repopulate"


A computing system includes a guest domain access control register (dacr), and guest first and second level page tables, the page tables containing domain identifiers used to obtain domain access information and access permission information, and the domain access information and the access permission information providing an effective guest access permission. The computing system provides a shadow page table, in which domain identifiers are used to identify domain access information in a processor dacr that are mapped from domain access information in the guest dacr, and in which access permissions are mapped from effective access permission information in the guest page tables and guest dacr.
11/27/14
20140351550

Memory management threads of data distribution service middleware


Disclosed herein are a memory management apparatus and method for threads of data distribution service middleware. The apparatus includes a memory area management unit, one or more thread heaps, and a queue.
11/27/14
20140351549

Off-heap direct-memory data stores, methods of creating and/or managing off-heap direct-memory data stores, and/or systems including off-heap direct-memory data store


Certain example embodiments relate to a highly-concurrent, predictable, fast, self-managed, in-process space for storing data that is hidden away from the garbage collector and its related pauses. More particularly, certain example embodiments relate to improved memory management techniques for computer systems that leverage an off-heap direct-memory data store that is massively scalable and highly efficient.
11/27/14
20140351185

Machine learning memory management and distributed rule evaluation


Aspects of the present disclosure relate to management of evaluated rule data sets. Specifically, a unreduced evaluated rule data set may contain a number of items to be compared or analyzed according to a number of rules, and may also contain the results of such analysis.
11/13/14
20140337597

Computer, program, and memory management method


A computer capable of managing reference relationships between data executes access of first and second storage regions in which stored data can be altered and a third storage region in which stored data cannot be altered. The computer sets specification data in the first storage region for accessing data stored in the second and third storage regions, and shifts data having a reference relationship with the specification data from among the data stored in the third storage region to the second storage region.
10/30/14
20140325165

Memory apparatus and memory management method


A memory apparatus includes a detection unit, a storage unit, an update unit, and a determination unit. The detection unit is configured to detect a deterioration factor of a nonvolatile memory.
10/30/14
20140325152

Quadtree based data management for memory


A method for managing memory. The method includes executing a memory management function, and reading data from memory into a particular size array structure using the memory management function based on using quadtree structure sub-functions to scan the particular size array structure for filtering the data iteratively..
10/30/14
20140321281

Fifo buffer with multiple stream packet segmentation


An epoch-based network processor internally segments packets for processing and aggregation in epoch payloads. Fifo buffers interact with a memory management unit to efficiently manage the segmentation and aggregation process..
10/16/14
20140310502

Memory management apparatus and memory management method thereof


A memory management apparatus and method thereof are disclosed. The memory management apparatus includes a micro translation look-aside buffers, a main translation look-aside buffer, a page address history table and a controller.
10/16/14
20140310497

Method and memory management


A method for memory management, include allocating an empty page of a physical memory for reference data according to execution of an application program, and mapping the empty page to a virtual memory; checking a physical address of the physical memory to which the reference data has been loaded; mapping the checked physical address to the virtual memory to which the empty page has been mapped, and mapping the reference data; and releasing allocation of the allocated physical memory when the reference data is mapped to the virtual memory.. .
10/09/14
20140304485

Embedded memory management scheme for real-time applications


Memory is dynamically shared or allocated in an embedded computer system. The types of memory that are part of the system are first determined.
10/02/14
20140293706

Semiconductor memory device, memory management method, and electronic apparatus


There is provided a semiconductor memory device including a bit line configured to write data, and a time measurement unit configured to measure a write time of the bit line.. .
09/18/14
20140282583

Dynamic memory management with thread local storage usage


Methods and arrangements for dynamic memory management. Data are accepted for thread local storage, and memory usage is monitored in thread local storage.
09/18/14
20140282580

Method and apparatus to save and restore system memory management unit (mmu) contexts


A wireless mobile device includes a graphic processing unit (gpu) that has a system memory management unit (mmu) for saving and restoring system mmu translation contexts. The system mmu is coupled to a memory and the gpu.
09/18/14
20140281364

Microcontroller for memory management unit


One embodiment of the present invention includes a microcontroller coupled to a memory management unit (mmu). The mmu is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table.
09/18/14
20140281363

Multi-threaded memory management


memory management includes maintaining a first mapping structure for each thread of a multi-threaded process. A second mapping structure is maintained for each core of a multi-core processing device.
09/18/14
20140281358

Migration scheme for unified virtual memory system


A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address.
09/18/14
20140281357

Common pointers in unified virtual memory system


A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address.
09/18/14
20140281356

Microcontroller for memory management unit


One embodiment of the present invention includes a microcontroller coupled to a memory management unit (mmu). The mmu is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table.
09/18/14
20140281332

Externally programmable memory management unit


A method includes reading, by a processor, one or more configuration values from a storage device or a memory management unit. The method also includes loading the one or more configuration values into one or more registers of the processor.
09/18/14
20140281303

Memory management for in-memory processing computing environments and systems


Data can be stored in a memory for in-memory processing system such the data is available for processing as soon as it is needed to be processed. By way of example, first portion and a second portion of the data can be stored in the memory of the in-memory processing system for processing by the in-memory processing system, such that the second portion of the data is stored in the memory before the in-memory processing system completes the processing of the first portion of the data, thereby allowing the in-memory processing system to process the second portion of the data when the processing system is able to process the second portion of the data.
09/18/14
20140281296

Fault buffer for tracking page faults in unified virtual memory system


A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address.
09/18/14
20140281256

Fault buffer for resolving page faults in unified virtual memory system


A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address.
09/18/14
20140281255

Page state directory for managing unified virtual memory


A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address.
09/18/14
20140281177

Hybrid memory management


Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi-level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed.
09/18/14
20140281058

Accelerator buffer access


Technologies are generally described for methods and systems effective to provide accelerator buffer access. An operating system may allocate a range of addresses in virtual address spaces and a range of addresses in a buffer mapped region of a physical (or main) memory.
09/18/14
20140278340

Dynamic memory management for a virtual supercomputer


Present invention embodiments enable the handling of various index-memory architectures for a virtual supercomputer that would allow for a heterogeneous storage of variable length index words with non-sequential addressing, and also dynamic changes to the index-memory architecture. A computer-implemented system, method, and apparatus allow for different types of node index memory (nim) architectures for the virtual supercomputer.
09/18/14
20140267230

Physical and environmental simulation using causality matrix


A simulation engine for causing a local or distributed computing system to produce a simulation of a virtual world includes one or more program modules that improve the realism and memory management of the simulation. An overworld object includes data pertaining to a world map and data pertaining to parameters for instantiating one or more npcs within the virtual world.


Popular terms: [SEARCH]

Memory Management topics: Memory Management, Virtual Machine, Storage Device, Volatile Memory, Data Processing, Logical Unit, Virtual Memory, Computer System, Dynamic Data, Base Memory, Database Management System, Data Storage, Defragment, Compatibility, Object Code

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