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Memory Management patents



      
           
This page is updated frequently with new Memory Management-related patent applications. Subscribe to the Memory Management RSS feed to automatically get the update: related Memory RSS feeds. RSS updates for this page: Memory Management RSS RSS


Memory management for video decoding

Image forming apparatus, memory management method for image forming apparatus, and program

Memory management in a streaming application

Date/App# patent app List of recent Memory Management-related patents
08/14/14
20140229689
 System and method for ballooning wth assigned devices patent thumbnailSystem and method for ballooning wth assigned devices
A system and method for ballooning with assigned devices includes inflating a memory balloon, determining whether a first memory page is locked based on information associated with the first memory page, when the first memory page is locked unlocking the first memory page and removing first memory addresses associated with the first memory page from management by an input/output memory management unit (iommu), and reallocating the first memory page. The first memory page is associated with a first assigned device..
08/14/14
20140226727
 Memory management for video decoding patent thumbnailMemory management for video decoding
Techniques and tools described herein help manage memory efficiently during video decoding, especially when multiple video clips are concurrently decoded. For example, with clip-adaptive memory usage, a decoder determines first memory usage settings expected to be sufficient for decoding of a video clip.
08/07/14
20140218767
 Image forming apparatus, memory management method for image forming apparatus, and program patent thumbnailImage forming apparatus, memory management method for image forming apparatus, and program
An image forming apparatus that performs image processing using information stored in a semiconductor memory includes an obtaining unit configured to obtain from the semiconductor memory a block size used for data reading and writing, and a management unit configured to discretely arrange and manage, with respect to a specific region set in the semiconductor memory, use-based information to be updated along with execution of the image processing, included in the stored information, according to the obtained block size.. .
07/31/14
20140215184
 Memory management in a streaming application patent thumbnailMemory management in a streaming application
One embodiment is directed to a method for processing a stream of tuples. The method may include receiving a stream of tuples to be processed by a plurality of processing elements operating on one or more computer processors.
07/31/14
20140215177
 Methods and systems for managing heterogeneous memories patent thumbnailMethods and systems for managing heterogeneous memories
A system includes a processor and first and second memories coupled to the processor. The first and second memories have a hardware attribute, such as bandwidth, latency and/or power consumption, wherein a first value of the hardware attribute of the first memory is different from a second value of the hardware attribute of the second memory.
07/31/14
20140215165
 Memory management in a streaming application patent thumbnailMemory management in a streaming application
One embodiment is directed to a method for processing a stream of tuples. The method may include receiving a stream of tuples to be processed by a plurality of processing elements operating on one or more computer processors.
07/31/14
20140214658
 Mobile device containing contactless payment card used in transit fare collection patent thumbnailMobile device containing contactless payment card used in transit fare collection
An apparatus such as a mobile phone includes a contactless smart card or payment device, where the smart card is intended for use in both commerce transaction payment and transit fare payment (or other venue access) environments. The payment device may function as both an electronic wallet for commerce transactions and as a transit system card, for access to and fare payment of transit services.
07/24/14
20140208064
 Virtual memory management system with reduced latency patent thumbnailVirtual memory management system with reduced latency
A computer system using virtual memory provides hybrid memory access either through a conventional translation between virtual memory and physical memory using a page table possibly with a translation lookaside buffer, or a high-speed translation using a fixed offset value between virtual memory and physical memory. Selection between these modes of access may be encoded into the address space of virtual memory eliminating the need for a separate tagging operation of specific memory addresses..
07/24/14
20140208042
 Providing hardware support for shared virtual memory between local and remote physical memory patent thumbnailProviding hardware support for shared virtual memory between local and remote physical memory
In one embodiment, the present invention includes a memory management unit (mmu) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links.
07/24/14
20140208034
 System and method for efficient paravirtualized os process switching patent thumbnailSystem and method for efficient paravirtualized os process switching
The exemplary embodiments described herein relate to systems and methods for improved process switching of a paravirtualized guest with a software-based memory management unit (“mmu”). One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, resulting in a performance of the following: create a plurality of new processes for each of a plurality of virtual environments, each of the virtual environments assigned one of a plurality of address space identifiers (“asids”) stored in a cache memory, perform a process switch to one of the virtual environments thereby designating the one of the virtual environments as the active virtual environment, determine whether the active virtual environment has exhausted each of the asids, and flush a cache memory when it is determined that the active virtual environment has exhausted each of the asids..
07/17/14
20140201126
Methods and systems for applications for z-numbers
Specification covers new algorithms, methods, and systems for artificial intelligence, soft computing, and deep learning/recognition, e.g., image recognition (e.g., for action, gesture, emotion, expression, biometrics, fingerprint, facial, ocr (text), background, relationship, position, pattern, and object), big data analytics, machine learning, training schemes, crowd-sourcing (experts), feature space, clustering, classification, svm, similarity measures, modified boltzmann machines, optimization, search engine, ranking, question-answering system, soft (fuzzy or unsharp) boundaries/impreciseness/ambiguities/fuzziness in language, natural language processing (nlp), computing-with-words (cww), parsing, machine translation, sound and speech recognition, video search and analysis (e.g. Tracking), image annotation, geometrical abstraction, image correction, semantic web, context analysis, data reliability, z-number, z-web, z-factor, rules engine, control system, autonomous vehicle, self-diagnosis and self-repair robots, system diagnosis, medical diagnosis, biomedicine, data mining, event prediction, financial forecasting, economics, risk assessment, e-mail management, database management, indexing and join operation, memory management, data compression, event-centric social network, image ad network..
07/17/14
20140199995
Methods and apparatus for providing unified wireless communication through efficient memory management
A method, an apparatus, and a computer program product for wireless communication are provided in connection with improving interactions between various components within a wireless device to enable improved communications between wireless devices. In an example, a wireless device may include an application processor equipped to send first and second amounts of data to be buffered in a buffer associated with a controller, and cease communications with the controller after the second amount of data is sent.
07/10/14
20140196003
Image processing software development method, image processing software development device, and image processing software development program
The present invention includes four types of component diagrams, namely, an input/output data memory management component diagram, an input data value setup component diagram, a library execution component diagram, and an output data value acquisition component diagram, with respect to image processing library functions for a programming language and to an input/output data structure for the image processing library functions. The present invention also includes upper-level component diagrams, which are prepared by connecting the four types of component diagrams as lower-level component diagrams in the order of use, writes an algorithm by combining the lower- and upper-level component diagrams, and executes the written algorithm.
07/10/14
20140195837
Enhanced dynamic memory management with intelligent current/power consumption minimization
A low-power state current/power consumption for each volatile memory device in a plurality of volatile memory devices is obtained. Data is copied from a first set of the volatile memory devices to a second set of the volatile memory devices, where the second set of volatile memory devices has a lower current/power consumption than the first set of volatile memory devices.
07/10/14
20140195765
Implementing user mode foreign device attachment to memory channel
A method, system and computer program product are provided for implementing attachment of a user mode foreign device to a memory channel in a computer system. A user mode foreign device is attached to the memory channel using memory mapping of device registers and device buffers to the processor address space.
07/10/14
20140195742
System on chip including memory management unit and memory address translation method thereof
A system on chip (soc) including a memory management unit (mmu) and a memory address translation method thereof are provided. The soc includes a master intellectual property (ip) configured to output a request corresponding to each of a plurality of working sets; an mmu module comprising a plurality of mmus, each of which is allocated for one of the working sets and translates virtual addresses corresponding to the request into physical addresses; a first bus interconnect configured to connect the mmu module with a memory device and to transmit the request, on which address translation has been performed in at least one of the mmus, to the memory device; and a second bus interconnect configured to connect the master ip with the mmu module and to allocate one of the mmus for each of the working sets..
07/10/14
20140195480
Persistent memory management
Apparatuses, systems, methods, and computer program products are disclosed for persistent memory management. Persistent memory management may include providing a persistent data structure stored at least partially in volatile memory configured to ensure persistence of the data structure in a non-volatile memory medium.
07/10/14
20140192074
Memory management techniques
Memory management techniques that permit an executing process to store content in memory and later retrieve that content from the memory, but that also permit a memory manager to discard that content to address memory pressure. A process executing on a computing device may notify a memory manager of the computing device that first memory space allocated to the process contains first content that is available for discard.
07/03/14
20140189326
Memory management in secure enclaves
Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit.
07/03/14
20140189248
Efficient online construction of miss rate curves
Miss rate curves are constructed in a resource-efficient manner so that they can be constructed and memory management decisions can be made while the workloads are running. The resource-efficient technique includes the steps of selecting a subset of memory pages for the workload, maintaining a least recently used (lru) data structure for the selected memory pages, detecting accesses to the selected memory pages and updating the lru data structure in response to the detected accesses, and generating data for constructing a miss-rate curve for the workload using the lru data structure.
07/03/14
20140188462
Methods and systems for applications for z-numbers
Specification covers new algorithms, methods, and systems for artificial intelligence, soft computing, and deep learning/recognition, e.g., image recognition (e.g., for action, gesture, emotion, expression, biometrics, fingerprint, facial, ocr (text), background, relationship, position, pattern, and object), large number of images (“big data”) analytics, machine learning, training schemes, crowd-sourcing (using experts or humans), feature space, clustering, classification, similarity measures, optimization, search engine, ranking, question-answering system, soft (fuzzy or unsharp) boundaries/impreciseness/ambiguities/fuzziness in language, natural language processing (nlp), computing-with-words (cww), parsing, machine translation, sound and speech recognition, video search and analysis (e.g. Tracking), image annotation, geometrical abstraction, image correction, semantic web, context analysis, data reliability (e.g., using z-number (e.g., “about 45 minutes; very sure”)), rules engine, control system, autonomous vehicle, self-diagnosis and self-repair robots, system diagnosis, medical diagnosis, biomedicine, data mining, event prediction, financial forecasting, economics, risk assessment, e-mail management, database management, indexing and join operation, memory management, and data compression..
07/03/14
20140185689
Low complex deblocking filter decisions
The present disclosure relates to deblocking filtering, which may be advantageously applied for block-wise encoding and decoding of images or video signals. In particular, the present disclosure relates to an improved memory management in an automated decision on whether to apply or skip deblocking filtering for a block and to selection of the deblocking filter.
07/03/14
20140185442
Supporting quality of service differentiation using a single shared buffer
An example method, system, and switching element are provided and may provide for an egress port to be configured to receive a plurality of data packets, each of the plurality of data packets being a class of a plurality of classes. A buffer may communicate with the at least one data port interface.
06/26/14
20140181461
Reporting access and dirty pages
A method and apparatus for reporting events into at least one event log are presented. An “access” event entry may be added to an event log stored in memory when a peripheral device accesses an address of a memory page described by a page table entry (pte).
06/26/14
20140181024
Approach for modularized sychronization and memory management
Approaches to memory management and synchronization are described relating to provision of highly robust and highly available servers that can serve multiple requests in parallel. Programming objects can be analyzed at design time by comparison to predefined patterns to identify a set of requirements and rules that must be followed to ensure that all part of a program cooperate.
06/19/14
20140173265
Protecting memory contents during boot process
Embodiments include methods, systems, and computer storage devices directed to identifying that a trusted boot mode (tbm) control bit is set in an input/output memory management unit (iommu) and configuring the iommu to block a dma request received by the iommu from a peripheral in response to the identifying.. .
06/19/14
20140173236
Secure computer system for preventing access requests to portions of system memory by peripheral devices and/or processor cores
A computer system is provided for preventing peripheral devices and/or processor cores from accessing restricted portions of system memory. For example, the computer system can include a host bridge, system memory coupled to the host bridge via a first access bus, a security processor coupled to the host bridge via a memory access bus that allows the security processor to access system memory and to access the peripheral device, and a security processor memory management unit (spmmu) coupled between the peripheral device and the host bridge.
06/19/14
20140173169
Controlling access to groups of memory pages in a virtualized environment
Embodiments of an invention for controlling access to groups of memory pages in a virtualized environment are disclosed. In one embodiment, a processor includes a virtualization unit and a memory management unit.
06/12/14
20140164824
Error detection/correction based memory management
The present disclosure includes methods, devices, and systems for error detection/correction based memory management. One embodiment includes performing a read operation with respect to a particular group of memory cells of a memory device and, if the read operation results in an uncorrectable error, determining whether to retire the particular group of memory cells in response to a status of an indicator corresponding to the particular group of memory cells, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith..
06/12/14
20140164716
Override system and method for memory access management
A memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for virtualizing context memory storage and independently controlling access to the context memory without interference from other engine activities.
06/12/14
20140164688
Soc system and method for operating the same
A soc system includes a central processing unit; a memory management unit receiving a virtual address from the central processing unit and converting the virtual address into a physical address; a main memory implemented by a volatile memory and directly accessed through the physical address converted by the memory management unit; and a storage implemented by a nonvolatile memory separate from the main memory and including a first area directly accessed through the physical address converted by the memory management unit.. .
06/05/14
20140156944
Memory management apparatus, method, and system
The present invention discloses a memory management apparatus, method, and system. An os-based memory management apparatus associated with main memory includes a memory allocation controller configured to control a first memory region within the main memory such that the first memory region is used as a buffer cache depending on whether an input/output device is active or not in order to use the first memory region, allowing memory reservation for the input/output device, in the os.
06/05/14
20140156935
Unified exclusive memory
In one embodiment, a processor includes at least one execution unit, a near memory, and memory management logic. The memory management logic may be to manage the near memory and a far memory as a unified exclusive memory, where the far memory is external to the processor.
06/05/14
20140156912
Memory management method, and memory controller and memory storage apparatus using the same
A memory management method and a memory controller and a memory storage apparatus using the same are provided. The method includes applying different detection biases to read data stored in physical pages of a rewritable non-volatile memory module and calculating the number of error bits according the read data.
05/29/14
20140149709
Method and system for dynamically updating data fields of buffers
A computing system can include memory management capabilities. In one embodiment, the system receives a request to update a first size of each of a plurality of portions of memory to a second size.
05/29/14
20140149704
Memory access authority control method and memory management system thereof
A memory access authority control method and a memory management system utilizing the method. By partitioning and designating permissible memory access intervals to different service programs in one system, it is ensured that each service program cannot access other service programs' confidential data.
05/29/14
20140149685
Memory management using dynamically allocated dirty mask space
Systems and methods related to a memory system including a cache memory are disclosed. The cache memory system includes a cache memory including a plurality of cache memory lines and a dirty buffer including a plurality of dirty masks.
05/29/14
20140149656
Hierarchical immutable content-addressable memory processor
Improved memory management is provided according to a hierarchical immutable content addressable memory processor (hicamp) architecture. In hicamp, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity.
05/29/14
20140146624
Memory modules and memory systems
In one example embodiment, a memory module includes a plurality of memory devices and a buffer chip configured to manage the plurality of memory device. The buffer chip includes a memory management unit having an error correction unit configured to perform error correction operation on each of the plurality of memory devices.
05/22/14
20140143518
Memory system and method for operating the same
A memory system comprises a central processing unit. A memory management unit receives a virtual address from the central processing unit.
05/22/14
20140143483
Memory management schemes for non-volatile memory devices
A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory.
05/22/14
20140143482
Memory management schemes for non-volatile memory devices
A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory.
05/22/14
20140143271
Multi-level medical image viewer memory management
An example multi-level image data cache system includes a memory layer associated with a first portion of a server memory, the memory layer having a fastest access speed and least available storage space of the layers in the multi-level image data cache system. The example system includes a disk layer associated with a second portion of server memory, the memory layer having a slower access speed than the memory layer and more storage space than the memory layer.
05/15/14
20140137131
Framework for java based application memory management
A memory management system is implemented at an application server. The management system includes a configuration file including configuration settings for the application server and applications.
05/15/14
20140137105
Virtual memory management to reduce power consumption in the memory
Reducing virtual memory power consumption during idle states in virtual memory systems comprising tracking the topology of the system memory by the system hypervisor and operating system running on any selected virtual machine hosted by the system hypervisor. The idle states in the system memory are dynamically monitored and then the power consumption states in the system memory are dynamically reduced through the interaction of the hypervisor and the operation system running on the selected virtual machine..
05/08/14
20140129757
System and method for dynamic memory power management
Various embodiments of methods and systems for hardware (“hw”) based dynamic memory management in a portable computing device (“pcd”) are disclosed. One exemplary method includes generating a lookup table (“lut”) to track each memory page located across multiple portions of a volatile memory.
05/08/14
20140128999
Recording of operating parameters of an intelligent electronic device
The present disclosure provides systems and methods for recording operating parameters of an intelligent electronic device (ied). A system may include a parameter acquisition module, a parameter storage module, and a memory management module.
05/01/14
20140122854
Information processing apparatus and activation method therefor
When an information processing apparatus is requested to transfer to a system interruption state, the information processing apparatus determines whether to compress data at each page, and generates a hibernation image configured of compressed data and non-compressed data. In an operating system activation period, the information processing apparatus determines whether to execute hibernation activation processing before initializing a memory management mechanism.
05/01/14
20140122820
System-on-chip processing secure contents and mobile device comprising the same
A mobile device is provided which includes a working memory having a memory area divided into a secure domain and a non-secure domain; and a system-on-chip configured to access and process contents stored in the secure domain. The system-on-chip includes a processing unit driven by at least one of a secure operating system and a non-secure operating system; at least one hardware block configured to access the contents according to control of the processing unit comprising a master port and a slave port which are set to have different security attributes; at least one memory management unit configured to control access of the at least one hardware block to the working memory; and an access control unit configured to set security attributes of the slave port and the master port or an access authority on each of the secure domain and the non-secure domain of the working memory..
05/01/14
20140122642
Remote memory management in distributed m2m systems
The embodiments herein relate to machine to machine (m2m) based systems and, more particularly, to managing application and services data in m2m based systems. The embodiments herein disclose a system and method for managing application and services data in a distributed wireless m2m system.
04/24/14
20140115248
Device, system, and method of memory allocation
Device, system, and method of memory allocation. For example, an apparatus includes: a dual in-line memory module (dimm) including a plurality of dynamic random access memory (dram) units to store data, wherein each dram unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said dimm to a memory page of an operating system, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the operating system..
04/24/14
20140115231
Nand memory management
Apparatus, systems, and methods manage nand memory are described. In one embodiment, an apparatus comprises a memory controller logic to apply a binary parity check code to a binary string and convert the binary string to a ternary string.
04/17/14
20140108765
Method and computer system for memory management on virtual machine system
A method and a computer system for memory management on a virtual machine system are provided. The memory management method includes the following steps.
04/17/14
20140108764
Method and computer system for memory management on virtual machine
A memory management method for a virtual machine system is provided. First, a first threshold value is set by a processor.
04/17/14
20140108723
Reducing metadata in a write-anywhere storage system
Systems and methods for reducing metadata in a write-anywhere storage system are disclosed herein. The system includes a plurality of clients coupled with a plurality of storage nodes, each storage node having a plurality of primary storage devices coupled thereto.
04/17/14
20140108701
Memory protection unit in a virtual processing environment
Some implementations may include a memory management system in a virtualized environment that includes a virtual address, a virtual machine exposed by a virtual machine monitor, a translation lookaside buffer to store virtual address to physical address translations, and a memory protection unit to verify whether a physical address obtained from the virtual address is within boundaries of one or more physical system memory regions assigned to a virtual machine.. .
04/17/14
20140108700
Method and computer system for memory management on virtual machine
A method and a computer system for memory management on a virtual machine system are provided. The memory management method includes the following steps.
04/10/14
20140098228
Memory management in event recording systems
A vehicle event recorder is provided that includes a camera for capturing a video as discrete image frames, and that further includes a managed loop memory and a management system for generating a virtual ‘timeline dilation’ effect. To overcome size limits in the buffer memory of the video event recorder, the maximum time extension of a video series is increased by enabling a reduction in temporal resolution in exchange for an increase in the temporal extension.
04/03/14
20140096235
Method and apparatus for dishonest hardware policies
A system implements dishonest policies for managing unauthorized access requests. The system includes memory management hardware to store a set of dishonest policy bits, each dishonest policy bit that is configured to a predetermined value indicating disallowed access for one of a set of memory ranges.
03/27/14
20140089611
Memory management control system, memory management control method, and storage medium storing memory management control program
The memory management control system 1 includes an instruction unit 2. In the case that reference data referred to by a job, and first data existing in an area collected by a storage apparatus are identical, the instruction unit 2 issues a first instruction to write the first data in the storage apparatus, and in the case of not being identical, the instruction unit 2 does not issue the first instruction..
03/27/14
20140089585
Hierarchy memory management
In one embodiment, a storage system comprises: a first type interface being operable to communicate with a server using a remote memory access; a second type interface being operable to communicate with the server using a block i/o (input/output) access; a memory; and a controller being operable to manage (1) a first portion of storage areas of the memory to allocate for storing data, which is to be stored in a physical address space managed by an operating system on the server and which is sent from the server via the first type interface, and (2) a second portion of the storage areas of the memory to allocate for caching data, which is sent from the server to a logical volume of the storage system via the second type interface and which is to be stored in a storage device of the storage system corresponding to the logical volume.. .
03/27/14
20140089567
Hardware integrity verification
A flash memory management method and apparatus provides for the separation of the command and data paths so that communication paths may be used more efficiently, taking account of the characteristics of nand flash circuits where the times to read, write and erase data differ substantially. A unique sequence identifier is assigned to a write command and associated data and association of the data and commands are validated prior to writing to the memory by comparing the unique sequence numbers of the data and command prior to executing the command.
03/27/14
20140089455
Method and system for memory management
One embodiment comprises a machine implemented method. The method comprises providing a first memory slice having a plurality of blocks configured for storing information on behalf of a plurality of clients.
03/20/14
20140082320
State memory management
The present invention relates to management of a state memory in a communications unit. The state memory then stores states that are used in message-based communication with external units in a communications system.
03/13/14
20140075265
Outputting information of ecc corrected bits
The present invention provides a method of operating a memory device storing error correcting codes eccs for corresponding data and including ecc logic to correct errors using the eccs. The method includes correcting data using eccs for the data on the memory device, and producing information on the memory device about the use of the eccs.
03/13/14
20140075208
Data whitening for writing and reading data to and from a non-volatile memory
Systems, apparatuses, and methods are provided for whitening and managing data for storage in non-volatile memories, such as flash memory. In some embodiments, an electronic device such as media player is provided, which may include a system-on-a-chip (soc) and a non-volatile memory.
03/13/14
20140075100
Memory system, computer system, and memory management method
A memory system includes a non-volatile memory having a physical memory region and a controller for conducting data transmission between the non-volatile memory and a host. The controller includes a section management module and a wear leveling module.
03/06/14
20140068396
Memory management method and apparatus for receiving multi channel hybrid automatic repeat request (harq) packet
A memory management method for receiving a multi channel hybrid automatic repeat request (harq) packet may enable smooth communication and reduce costs by maintaining a small memory size of a receiver in a communication system using a harq including a plurality of channels.. .
03/06/14
20140068194
Processor, information processing apparatus, and control method of processor
A processor is includes cache memory; an arithmetic processing section that a load request loading an object data stored at a memory to the cache memory; a cache control part patent a process corresponding to the received load request; a memory management part which requests the object data corresponding to the request from the cache control part and header information containing information indicating whether or not the object data is a latest for the memory, and receives the header information responded by the memory; and a data management part that manages a write control of the data to the cache memory, and receives the object data responded by the memory based on the request. The requested data is transmitted from the memory to the data management part held by a cpu node without being intervened by the memory management part..
03/06/14
20140068138
Embedded processor with virtualized security controls using guest identifications, a common kernel address space and operational permissions
A method includes assigning unique guest identifications to different guests, specifying an address region and permissions for the different guests and controlling a guest jump from one physical memory segment to a second physical memory segment through operational permissions defined in a root memory management unit that supports guest isolation and protection.. .
03/06/14
20140068137
Virtual input/output memory management unit within a guest virtual machine
A virtual input/output memory management unit (iommu) is configured to provide a firewall around memory requests associated with an input/output (i/o) device. The virtual iommu uses data structures including a guest page table, a host page table and a general control register (i.e., gcr3) table.


Popular terms: [SEARCH]

Memory Management topics: Memory Management, Virtual Machine, Storage Device, Volatile Memory, Data Processing, Logical Unit, Virtual Memory, Computer System, Dynamic Data, Base Memory, Database Management System, Data Storage, Defragment, Compatibility, Object Code

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