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Memory Management patents



      
           
This page is updated frequently with new Memory Management-related patent applications.



Date/App# patent app List of recent Memory Management-related patents
02/04/16
20160037281 
 Memory management techniques and related systems for block-based convolution patent thumbnailnew patent Memory management techniques and related systems for block-based convolution
A processor can be associated with a memory for storing convolution data. A plurality of m filters from a corresponding plurality of m input channels to a selected one output channel can be provided, wherein each filter can be represented by a corresponding index, m.

02/04/16
20160035324 
 Memory management for systems for generating 3-dimensional computer images patent thumbnailnew patent Memory management for systems for generating 3-dimensional computer images
A memory management system for generating 3-dimensional computer images is provided. The memory management system includes a device for subdividing an image into a plurality of rectangular areas, a memory for storing object data pertaining to objects in the image which fall in each rectangular area, a device for storing the object data in the memory, a device for deriving image data and shading data for each rectangular area from the object data, a device for supplying object data for each rectangular area from the respective portion of the memory and, if the rectangular area contains objects also falling in at least one other rectangular area, also from the global list, to the deriving device, and a device for storing the image data and shading data derived by the deriving device for display.
Imagination Technologies Limited


02/04/16
20160034407 
 Technique for synchronizing iommu memory de-registration and incoming i/o data patent thumbnailnew patent Technique for synchronizing iommu memory de-registration and incoming i/o data
A technique synchronizes de-registration of registered memory and incoming input/output (i/o) data received from an i/0 device for storage in a memory of a computer system. Registration and de-registration of the memory with an i/o memory management unit (iommu) are illustratively performed by an i/o device driver of the computer system in anticipation of (or in response to) an i/o request to store the incoming i/o data in buffers of the memory.
Netapp, Inc.


01/28/16
20160026392 
 Off-heap direct-memory data stores, methods of creating and/or managing off-heap direct-memory data stores, and/or systems including off-heap direct-memory data store patent thumbnailOff-heap direct-memory data stores, methods of creating and/or managing off-heap direct-memory data stores, and/or systems including off-heap direct-memory data store
Certain example embodiments relate to a highly-concurrent, predictable, fast, self-managed, in-process space for storing data that is hidden away from the garbage collector and its related pauses. More particularly, certain example embodiments relate to improved memory management techniques for computer systems that leverage an off-heap direct-memory data store that is massively scalable and highly efficient.
Software Ag Usa, Inc.


01/21/16
20160019168 
 On-demand shareability conversion in a heterogeneous shared virtual memory patent thumbnailOn-demand shareability conversion in a heterogeneous shared virtual memory
The aspects include systems and methods of managing virtual memory page shareability. A processor or memory management unit may set in a page table an indication that a virtual memory page is not shareable with an outer domain processor.
Qualcomm Incorporated


01/21/16
20160019144 
 Systems and/or methods for enabling storage tier selection and usage at a granular level patent thumbnailSystems and/or methods for enabling storage tier selection and usage at a granular level
Certain example embodiments relate to memory management techniques that enable users to “pin” elements to particular storage tiers (e.g., ram, ssd, hdd, tape, or the like). Once pinned, elements are not moved from tier-to-tier during application execution.
Software Ag Usa, Inc.


01/21/16
20160019031 
 Method and system for processing memory patent thumbnailMethod and system for processing memory
A method and system for memory management is disclosed. The disclosed method and system can prevent performance degradation due to automatic garbage collection associated with memory allocation for image processing.
Quram Co., Ltd.


01/14/16
20160012241 
 Distributed dynamic memory management unit (mmu)-based secure inter-processor communication patent thumbnailDistributed dynamic memory management unit (mmu)-based secure inter-processor communication
A first processor and a second processor are configured to communicate secure inter-processor communications (ipcs) with each other. The first processor effects secure ipcs and non-secure ipcs using a first memory management unit (mmu) to route the secure and non-secure ipcs via a memory system.
Qualcomm Incorporated


01/14/16
20160011649 
 Electronic apparatus, power supply control method, and program patent thumbnailElectronic apparatus, power supply control method, and program
An electronic apparatus equipped with a power source, a storage section, a memory management section, and a control section. The storage section is provided with a predetermined memory space.
Nec Corporation


01/07/16
20160004654 
 System for migrating stash transactions patent thumbnailSystem for migrating stash transactions
A system for migrating stash transactions includes first and second cores, an input/output memory management unit (iommu), an iommu mapping table, an input/output (i/o) device, a stash transaction migration management unit (stmmu), a queue manager and an operating system (os) scheduler. The i/o device generates a first stash transaction request for a first data frame.
Freescale Semiconductor, Inc.


01/07/16
20160004453 

Snapshot management using extended data units


A method for memory management, the method may include receiving an updated portion of a data unit, the data unit is associated with a logical data entity; wherein the updated portion is smaller than a granularity of a mapping data structure used for retrieval of the data unit; and creating, by the storage system an extended data unit that comprises (i) an original content of the data unit, (ii) the updated portion and, (iii) updated portion metadata; wherein the updated portion metadata comprises (a) updated portion retrieval information for retrieving the updated portion, and (b) updated portion snapshot information indicative of at least one snapshot associated with the updated portion.. .
Infinidat Ltd.


12/31/15
20150381728 

Systems and methods for performing memory management in a distributed environment


Systems and methods for performing memory management among a plurality of devices in a network are described. In one implementation, the method for performing memory management comprises obtaining memory requirements for execution of an application.
Wipro Limited


12/31/15
20150378889 

Persistent content in nonvolatile memory


Applications may request persistent storage in nonvolatile memory. The persistent storage is maintained across power events and application instantiations.
Micron Technology, Inc.


12/31/15
20150378762 

Monitoring and dynamic configuration of virtual-machine memory-management


The current document is directed to methods and systems for monitoring the performance of memory management in virtual machines. By accurately measuring the performance of memory management in virtual machines, a virtualization layer can dynamically reconfigure virtual machines to use more optimal memory-management methods, intelligently schedule execution of virtual machines to increase memory-management performance, and migrate virtual machines among different servers and computer systems to increase memory-management performance..
Vmware, Inc.


12/31/15
20150378731 

Apparatus and efficiently implementing a processor pipeline


Various different embodiments of the invention are described including: (1) a method and apparatus for intelligently allocating threads within a binary translation system; (2) data cache way prediction guided by binary translation code morphing software; (3) fast interpreter hardware support on the data-side; (4) out-of-order retirement; (5) decoupled load retirement in an atomic ooo processor; (6) handling transactional and atomic memory in an out-of-order binary translation based processor; and (7) speculative memory management in a binary translation based out of order processor.. .

12/31/15
20150378424 

Memory management based on bandwidth utilization


A processing system includes a memory circuit configured for operation at a plurality of frequency-voltage operating points and one or more processing elements operatively coupled to the memory circuit. A memory-bandwidth measurement circuit repeatedly measures run-time bandwidth utilization of the memory circuit, while a controller circuit dynamically adjusts the voltage-frequency operating point of the memory circuit as a function of the measured run-time bandwidth utilization.
Telefonaktiebolaget L M Ericsson (publ)


12/24/15
20150372896 

Packet segmentation with different segment sizes for a switch fabric


An epoch-based network processor internally segments packets for processing and aggregation in epoch payloads. Fifo buffers interact with a memory management unit to efficiently manage the segmentation and aggregation process..
Force10 Networks, Inc.


12/24/15
20150370728 

Memory management device and non-transitory computer readable storage medium


In one embodiment, a device executes reading and writing for a storage unit storing a table tree and verifier tree. The table tree includes a parent table and child table.
Kabushiki Kaisha Toshiba


12/24/15
20150370727 

Memory management device and non-transitory computer readable storage medium


In one embodiment, a device executes reading and writing for a storage unit storing a table tree and verifier tree. The table tree includes a parent table and child table.
Kabushiki Kaisha Toshiba


12/24/15
20150370726 

Memory management device and non-transitory computer readable storage medium


In one embodiment, a storage unit stores a table tree and verifier tree. The table tree includes parent and child tables.
Kabushiki Kaisha Toshiba


12/24/15
20150370709 

Reduction of evictions in cache memory management directories


A module of cache coherence management by directory, in which each datum stored in cache memory is associated with a state, at least one of which indicates data sharing among a plurality of processors, the module including a storage unit to store a directory containing a list of cache memory addresses, each address possibly associated with a state corresponding to the state of the datum available at this address, and a processing unit configured to update said list, said processing unit being configured so as not to list the address lines related to data associated with the first state.. .
Bull Sas


12/17/15
20150363594 

System and secure loading data in a cache memory


A system and method for securely loading data in a cache memory associated with at least one secure processor that performs data processing by using at least one untrusted external memory storing data to be processed, at least one secure internal cache memory to load or store data, and at least one secure cache translator operating as a memory management unit. The secure cache translator stores, into a secure cache digest table, parameters arranged on persistent and variable data pages.
Nagravision Sa


12/17/15
20150363311 

Memory management method


A method for managing main memory including dram and nvram in a computer depending on the operation state of the computer is provided. The method includes: (a) upon start of the computer, loading a program and the like into the dram, and loading predetermined read-only data and the like into the nvram; (b) in a state transition from a normal operation to a suspend state, moving data in the dram to the nvram; (c) in a state transition from the suspend state to the normal operation, reading data from the nvram for program execution; (d) in the case where a data write to the nvram occurs, stopping the data write, and moving data in a data area of the nvram subjected to the data write, to the dram; and (e) performing the data write to the dram to which the data has been moved..
International Business Machines Corporation


12/10/15
20150357025 

Device, system, and memory allocation


Device, system, and method of memory allocation. For example, an apparatus includes: a dual in-line memory module (dimm) including a plurality of dynamic random access memory (dram) units to store data, wherein each dram unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said dimm to a memory page of an operating system, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the operating system..
Intel Corporation


12/10/15
20150356023 

Paravirtualization-based interface for memory management in virtual machines


A method for memory virtualization in a system including guest virtual, guest physical and host physical address spaces, a guest pagetable for translating addresses of the guest virtual address space into addresses of the guest physical address space, a shadow pagetable for translating addresses of the guest virtual address space into addresses of the host physical address space, and a hypervisor configured for calculating address entries for the shadow pagetable from valid address entries in the guest pagetable, includes managing, by the hypervisor, one or more shadow pagetable(s) by the hypervisor while a guest context is executed by a guest operating system, wherein the number of shadow pagetable(s) is smaller than or equal to the number of guest contexts in a current working set.. .
Deutsche Telekom Ag


12/10/15
20150356007 

Parallel garbage collection implemented in hardware


Embodiments of the invention provide a method and system for dynamic memory management implemented in hardware. In an embodiment, the method comprises storing objects in a plurality of heaps, and operating a hardware garbage collector to free heap space.
International Business Machines Corporation


12/10/15
20150355851 

Dynamic selection of memory management algorithm


A data processing system 2 includes a memory controller 20 which dynamically selects from a plurality of candidate management algorithms a selected management algorithm to be used for managing memory access conflicts. The memory management algorithms may include various versions of speculative memory access issue and/or memory access issue using memory locks.
Arm Limited


12/03/15
20150350644 

Moving image prediction encoding/decoding system


A moving image encoding/decoding system may include a video predictive encoding device, which may include: an encoding device which encodes each of a plurality of input pictures to generate compressed picture data including a random access picture, and encodes data about display order information of each picture; a restoration device which decodes the compressed picture data to restore a reproduced picture; a picture storage device which stores the reproduced picture as a reference picture; and a memory management device which controls the picture storage device. Following completion of an encoding process of generating the random access picture, the memory management device refreshes the picture storage device by setting every reference picture in the picture storage device, except for the random access picture, as unnecessary immediately before or immediately after encoding a picture with display order information larger than the display order information of the random access picture..
Ntt Docomo, Inc.


12/03/15
20150347434 

Reducing metadata in a write-anywhere storage system


Systems and methods for reducing metadata in a write-anywhere storage system are disclosed herein. The system includes a plurality of clients coupled with a plurality of storage nodes, each storage node having a plurality of primary storage devices coupled thereto.
Datadirect Networks, Inc.


12/03/15
20150347322 

Speculative querying the main memory of a multiprocessor system


A method of accessing data in a multiprocessor system, wherein the system includes a plurality of processors, with each processor being associated with a respective cache memory, a cache memory management module, a main memory and a main memory management module, the method including: receiving by the cache memory management module an initial request for access to data by a processor; first transmitting by the cache memory management module a first request with respect to the data to at least one cache memory; second transmitting in parallel to the first transmitting by the cache memory management module, a second request with respect to the data to the main memory management module; checking by the main memory management module, whether to initiate querying of the main memory or not, and querying or not by the main memory management module, of the main memory in accordance with the said checking.. .
Bull Sas


12/03/15
20150347306 

Synchronizing updates of page table status indicators in a multiprocessing environment


A synchronization capability to synchronize updates to page tables by forcing updates in cached entries to be made visible in memory (i.e., in in-memory page table entries). A synchronization instruction is used that ensures after the instruction has completed that updates to the cached entries that occurred prior to the synchronization instruction are made visible in memory.
International Business Machines Corporation


12/03/15
20150347301 

Synchronizing updates of page table status indicators and performing bulk operations


A synchronization capability to synchronize updates to page tables by forcing updates in cached entries to be made visible in memory (i.e., in in-memory page table entries). A synchronization instruction is used that ensures after the instruction has completed that updates to the cached entries that occurred prior to the synchronization instruction are made visible in memory.
International Business Machines Corporation


12/03/15
20150347300 

Synchronizing updates of page table status indicators in a multiprocessing environment


A synchronization capability to synchronize updates to page tables by forcing updates in cached entries to be made visible in memory (i.e., in in-memory page table entries). A synchronization instruction is used that ensures after the instruction has completed that updates to the cached entries that occurred prior to the synchronization instruction are made visible in memory.
International Business Machines Corporation


12/03/15
20150347190 

System and coordinating process and memory management across domains


A method at a computing device having a plurality of concurrently operative operating systems, the method comprising: operating a proxy process within a target operating system on the computing device; receiving, from an originating operating system, a request for resources from a target process within the target operating system at the proxy process; requesting, from the proxy process, the resources of the target process; and returning a handle to the target process from the proxy process to the originating operating system.. .
2236008 Ontario Inc.


12/03/15
20150347052 

Virtualisation supporting guest operating systems using memory protection units


A processor (20) is provided with a first memory protection unit (38) applying a first set of permissions and a second memory protection unit (40) applying a second set of permissions. A memory access will only be permitted if both the first set of permissions and the second set of permissions are satisfied.
Arm Limited


12/03/15
20150347044 

Synchronizing updates of page table status indicators and performing bulk operations


A synchronization capability to synchronize updates to page tables by forcing updates in cached entries to be made visible in memory (i.e., in in-memory page table entries). A synchronization instruction is used that ensures after the instruction has completed that updates to the cached entries that occurred prior to the synchronization instruction are made visible in memory.
International Business Machines Corporation


12/03/15
20150347023 

Memory coalescing computer-implemented method, system, apparatus and computer-readable media


Embodiments of computer-implemented methods, apparatus and computer-readable media associated with memory management are disclosed herein. A computer-implemented method to coalesce free intervals of a memory may include ascertaining that a first interval of the memory is free (302, 304).

11/26/15
20150339225 

Memory management method, memory storage device and memory control circuit unit


A memory management method, a memory storage device and a memory control circuit unit are provided. The memory management method includes: grouping a plurality of non-spare physical erasing units into a first physical erasing unit and a second physical erasing unit, and a data updating frequency of the first physical erasing unit is lower than the data updating frequency of the second physical erasing unit; selecting a third physical erasing unit from the physical erasing units belonging to the first physical erasing unit; selecting a fourth physical erasing unit from spare physical erasing units, and copying valid data stored in the third physical erasing unit to the fourth physical erasing unit..
Phison Electronics Corp.


11/26/15
20150339166 

Memory management for virtual machines


Embodiments of the disclosure relate to managing a memory of a server hosting a plurality of virtual machines. Aspects include receiving a plurality of data pages from each of the plurality of virtual machines to be stored in the memory, filtering each the plurality of data pages into one of a plurality of pools of data pages including a pool of potentially identical data pages, and evaluating the data pages in the pool of potentially identical data pages to identify one or more duplicate data pages and one or more similar data pages.
International Business Machines Corporation


11/26/15
20150339141 

Memory management for virtual machines


Embodiments of the disclosure relate to managing a memory of a server hosting a plurality of virtual machines. Aspects include receiving a plurality of data pages from each of the plurality of virtual machines to be stored in the memory, filtering each the plurality of data pages into one of a plurality of pools of data pages including a pool of potentially identical data pages, and evaluating the data pages in the pool of potentially identical data pages to identify one or more duplicate data pages and one or more similar data pages.
International Business Machines Corporation


11/12/15
20150324299 

Temporal standby list


In one embodiment, a memory management system temporarily maintains a memory page at an artificially high priority level. The memory management system may assign an initial priority level to a memory page in a page priority list.
Microsoft Technology Licensing, Llc


11/12/15
20150324286 

Memory management method in embedded system


A memory management method in an embedded system is provided. The method includes a first iteration step that sequentially allocates and deletes memory, and recognizes an area where the first to last sections of the memory were located as a hollow space list a second iteration step sequentially allocates the memory in an area of the hollow space list by starting the memory allocation from an end point of the hollow space list.
Hyundai Motor Company


11/12/15
20150323969 

Memory storage device, memory control circuit unit and power supply method


A memory storage device, a memory control circuit unit and a power supply method are provided. The power supply method includes: providing a first power voltage to a host interface circuit of the memory storage device; providing a second power voltage to a memory management circuit of the memory storage device; providing a third power voltage to a memory interface circuit of the memory storage device, wherein a reference voltage terminal of the memory interface circuit is coupled to a power input terminal of the memory management circuit.
Phison Electronics Corp.


11/05/15
20150317271 

Graphics processing microprocessor system having a master device communicate with a slave device


A slave device communicates with a host system via a host communications bus. The host system includes one processor that can act as bus master and send access requests for slave resources on the slave device via the communications bus.
Arm Norway As


11/05/15
20150317259 

Memory management unit that applies rules based on privilege identifier


A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the master, usually a cpu originating the request based on a privilege identifier that accompanies each memory access request.
Texas Instruments Incorporated


11/05/15
20150317080 

Apparatus including memory system controllers and related methods


Memory system controllers can include non-volatile memory control circuitry including a plurality of channel control circuits. Each of the plurality of channel control circuits can be configured to be coupled to a respective number of logical units (luns).
Micron Technology, Inc.


10/29/15
20150310301 

Analyzing or resolving ambiguities in an image for object or pattern recognition


Specification covers new algorithms, methods, and systems for artificial intelligence, soft computing, and deep learning/recognition, e.g., image recognition (e.g., for action, gesture, emotion, expression, biometrics, fingerprint, facial, ocr (text), background, relationship, position, pattern, and object), large number of images (“big data”) analytics, machine learning, training schemes, crowd-sourcing (using experts or humans), feature space, clustering, classification, similarity measures, optimization, search engine, ranking, question-answering system, soft (fuzzy or unsharp) boundaries/impreciseness/ambiguities/fuzziness in language, natural language processing (nlp), computing-with-words (cww), parsing, machine translation, sound and speech recognition, video search and analysis (e.g. Tracking), image annotation, geometrical abstraction, image correction, semantic web, context analysis, data reliability (e.g., using z-number (e.g., “about 45 minutes; very sure”)), rules engine, control system, autonomous vehicle, self-diagnosis and self-repair robots, system diagnosis, medical diagnosis, biomedicine, data mining, event prediction, financial forecasting, economics, risk assessment, e-mail management, database management, indexing and join operation, memory management, and data compression..

10/29/15
20150309948 

Tracking statistics corresponding to data access in a computer system


Embodiments of the present invention disclose a method, computer program product, and system for determining statistics corresponding to data transfer operations. In one embodiment, the computer implemented method includes the steps of receiving a request from an input/output (i/o) device to perform a data transfer operation between the i/o device and a memory, generating an entry in an input/output memory management unit (iommu) corresponding to the data transfer operation, wherein the entry in the iommu includes at least an indication of a processor chip that corresponds to the memory of the data transfer operation, monitoring the data transfer operation between the i/o device and the memory, determining statistics corresponding to the monitored data transfer operation, wherein the determined statistics include at least: the i/o device that performed the data transfer operation, the processor chip that corresponds to the memory of the data transfer operation, and an amount of data transferred..
International Business Machines Corporation


10/29/15
20150309947 

Tracking statistics corresponding to data access in a computer system


Embodiments of the present invention disclose a method, computer program product, and system for determining statistics corresponding to data transfer operations. In one embodiment, the computer implemented method includes the steps of receiving a request from an input/output (i/o) device to perform a data transfer operation between the i/o device and a memory, generating an entry in an input/output memory management unit (iommu) corresponding to the data transfer operation, wherein the entry in the iommu includes at least an indication of a processor chip that corresponds to the memory of the data transfer operation, monitoring the data transfer operation between the i/o device and the memory, determining statistics corresponding to the monitored data transfer operation, wherein the determined statistics include at least: the i/o device that performed the data transfer operation, the processor chip that corresponds to the memory of the data transfer operation, and an amount of data transferred..
International Business Machines Corporation


10/29/15
20150309741 

Apparatuses and methods for memory management


Some embodiments include apparatuses and methods to select a target memory portion in a first memory location to store information. One such method can conditionally store the information in a second memory location when the information is stored in the target memory portion.
Micron Technology, Inc.


10/22/15
20150304687 

Low complex deblocking filter decisions


The present disclosure relates to deblocking filtering, which may be advantageously applied for block-wise encoding and decoding of images or video signals. In particular, the present disclosure relates to an improved memory management in an automated decision on whether to apply or skip deblocking filtering for a block and to selection of the deblocking filter.
Panasonic Intellectual Property Corporation Of America


10/22/15
20150302903 

System and deep coalescing memory management in a portable computing device


Various embodiments of methods and systems for deep coalescing memory management (“dcmm”) in a portable computing device (“pcd”) are disclosed. Because multiple active multimedia (“mm”) clients running on the pcd may generate a random stream of mixed read and write requests associated with data stored at non-contiguous addresses in a double data rate (“ddr”) memory component, dcmm solutions triage the requests into dedicated deep coalescing (“dc”) cache buffers, sequentially ordering the requests and/or the dc buffers based on associated addresses for the data in the ddr, to optimize read and write transactions from and to the ddr memory component in blocks of contiguous data addresses..
Qualcomm Incorporated


10/22/15
20150301947 

Controlling access to groups of memory pages in a virtualized environment


Embodiments of an invention for controlling access to groups of memory pages in a virtualized environment are disclosed. In one embodiment, a processor includes a virtualization unit and a memory management unit.
Intel Corporation


10/22/15
20150301932 

Nonvolatile memory system and performing operation of the nonvolatile memory system


According to example embodiments, a nonvolatile memory system includes a nonvolatile memory device includes a nonvolatile memory cell array, a temperature sensor configured to measure a temperature of the nonvolatile memory device, and a memory controller configured to adjust an execution frequency of a memory management operation based on a desired (and/or alternatively predetermined) temperature range and the measured temperature.. .

10/22/15
20150301917 

Memory monitoring method and related apparatus


A memory monitoring method and a computing system. The computing system includes a processor, a memory and a monitor.
Huawei Technologies Co., Ltd.


10/15/15
20150293790 

Method and system for driving virtual machine


Provided herein a method for driving a virtual machine, the method including providing a plurality of virtual machines and a virtual machine monitor configured to manage the plurality of virtual machines; generating, by the plurality of virtual machines, memory management information, that is information on memory being used by the plurality of virtual machines; and determining, by the virtual machine monitor, whether or not a virtual machine is a victim virtual machine from which memory needs to be retrieved or whether or not the virtual machine is a beneficiary virtual machine where memory needs to be allocated, based on the memory management information.. .

10/15/15
20150293776 

Data processing systems


A data processing system includes one or more processors that each execute one or more operating systems. Each operating system includes one or more applications.

10/15/15
20150293736 

Electronic device and memory management method that improves usage efficiency of memory


A first-region allocating unit of an electronic device allocates a first region having a size required for a first process. The first process includes at least one second process in a region of the memory.

10/08/15
20150286564 

Hardware-based memory management apparatus and memory management method thereof


A hardware-based memory management apparatus and method is provided. The apparatus includes a memory allocation module, a memory reclamation module, and a memory compaction module, based on hardware to accelerate a memory manger of an operating system.

10/08/15
20150286442 

Cluster-wide memory management using similarity-preserving signatures


A method includes, in a computing system that includes one or more compute nodes that run clients, defining memory chunks, each memory chunk including multiple memory pages accessed by a respective client. Respective similarity-preserving signatures are computed for one or more of the memory chunks.

10/08/15
20150286270 

Method and system for reducing power consumption while improving efficiency for a memory management unit of a portable computing device


A method and system for reducing power consumption while improving efficiency of a memory management unit of a portable computing device include determining if data of a memory request exists within a first memory element external to the memory management unit. The first memory element may include a cache.

10/08/15
20150286269 

Method and system for reducing power consumption while improving efficiency for a memory management unit of a portable computing device


A method and system for reducing power consumption while improving efficiency of a memory management unit of a portable computing device are described. The method and system include determining if data of a memory request exists within a first memory element external to the memory management unit.

10/01/15
20150278083 

Conditional processing method and apparatus


A conditional processing method and apparatus for efficient memory management are provided. A conditional processing method includes receiving a data stream including a plurality of elements; decoding the received data stream; generating a parse tree by loading the decoded data stream; determining whether a parsingswitch element is detected while generating the parse tree; and if the parsingswitch element is detected, loading at least one child element of the detected parsingswitch element in a memory, based on at least one attribute of the detected parsingswitch element..
Samsung Electronics Co., Ltd.


10/01/15
20150278082 

Information processing device, memory management method, and recording medium that ensure versatile memory management


An information processing device includes a memory and a control unit. The memory is employed as a program work area.
Kyocera Document Solutions Inc.


10/01/15
20150277977 

Method and system for providing stack memory management in real-time operating systems


A method and system for providing memory management in a real-time operating system (rtos) based system are provided. The method includes creating a plurality of tasks with a two level stack scheme comprising a first level stack and a second level stack, scheduling a first task for execution by moving a stack pointer from the first level stack to the second level stack, determining whether the first task is pre-empted, allocating the second level stack to the first task in a second state if the first task is not pre-empted, changing an active task for execution, determining whether the first task relinquishes control from the second state and is waiting for a resource, moving the stack pointer back from the second level stack to the first level stack if the first task relinquishes itself and providing the second level stack for use by a second task..
Samsung Electronics Co., Ltd.


10/01/15
20150277772 

Global memory sharing method and apparatus, and communications system


A global memory sharing method includes counting, by the sub-operating system, a page replacement rate in a task scheduling period of a predetermined quantity of times, and a memory residence time ratio in a page replacement period; calculating, by the sub-operating system, a memory pressure index according to the page replacement rate and the memory residence time ratio; and if the memory pressure index is greater than a memory pressure threshold, sending, by the sub-operating system, an application to a global memory management service module. According to the forgoing method, in an architecture of multiple operating systems, each sub-operating system can complete much adaptive work, which reduces complexity of the global memory management service module and improves system performance.
Huawei Technologies Co., Ltd.


09/24/15
20150269097 

System and elastic despreader memory management


The disclosure is directed to a system and method of managing memory resources in a communication channel. According to various embodiments, incoming memory slices associated with a plurality of data sectors are de-interleaved and transferred sequentially through a buffer to a decoder for further processing.
Lsi Corporation


09/24/15
20150269092 

Information processing device and shared memory management method


An access blocking unit blocks an access to a failed segment by using tokens in hardware and a replacing unit performs a process for replacing the failed segment with a replacement segment. For each segment of a shared memory, an application recognizing unit recognizes the node numbers of nodes that are given access permission and pids of applications and records them in the management table.
Fujitsu Limited


09/24/15
20150269066 

Indirect resource management


A method for memory management includes allocating an available block of memory for use by a first object, determining that the block of memory includes at least a portion of a second object, the second object no longer being used by an application associated with the second object, determining that the second object utilized at least one resource that was not shutdown, releasing the at least one resource, and writing to the block of memory with the first object.. .
Red Hat Israel, Ltd.


09/24/15
20150268879 

Memory management method, memory storage device and memory control circuit unit


A memory management method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving a write command to write first data into a first spare physical erasing unit; selecting a first physical erasing unit, wherein the first physical erasing unit does not include the first spare physical erasing unit and stores a plurality of data in which at least two data belong to different logical erasing units; copying and writing a valid data among the plurality of data into a second spare physical erasing unit, wherein the second spare physical erasing unit is different from the first spare physical erasing unit..
Phison Electronics Corp.


09/17/15
20150261686 

Systems and methods for supporting demand paging for subsystems in a portable computing environment with restricted memory resources


A portable computing device is arranged with one or more subsystems that include a processor and a memory management unit arranged to execute threads under a subsystem level operating system. The processor is in communication with a primary memory.
Qualcomm Incorporated


09/17/15
20150261684 

Memory management with priority-based memory reclamation


A memory buffer with a set of one or more structures is created by a process of a first software program. The first memory buffer comprises a predetermined amount of memory.
International Business Machines Corporation


09/17/15
20150261463 

Asynchronous consistent snapshots in persistent memory stores


Crash recovery with asynchronous consistent snapshots in persistent memory stores of a processing environment. A processing environment includes a user program and infrastructure-maintained data structures.
Hewlett-packard Development Company, L.p.


09/03/15
20150248355 

Memory management unit for a microprocessor system, microprocessor managing memory


A first storage location at a memory management unit stores physical address information mapping logical physical addresses to actual physical addresses. A second storage location stores an allowed address range of actual physical addresses.
Freescale Semiconductor, Inc.


09/03/15
20150248231 

Apparatus and methods for widget-related memory management


Apparatus and methods for changing operational modes of a widget and changing content feed to a widget based on operational mode changes and/or memory availability on the wireless device are provided. Apparatus and methods for managing the runtime memory usage of mobile widgets on a wireless device by changing widget states based on widget usage data are also provided..
Qualcomm Incorporated


08/27/15
20150244801 

Dynamic ad hoc cloud based memory management for mobile devices


Mechanisms are provided for generating a dynamically generated ad hoc cloud storage system of mobile devices. A mobile device transmits a request to dynamically generate an ad hoc cloud storage system, to other devices within a local vicinity of the mobile device.
International Business Machines Corporation


08/27/15
20150242271 

Memory management system and method


A memory system and method of operating the same is described, where the memory system is used to store data in a raided manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received.
Violin Memory Inc


08/20/15
20150235488 

Memory management for fleet operation of peps vehicles


Methods and apparatus are provided to dynamically configure a passive entry, passive start system to issue passive and active commands upon authentication of a remote keyless fob with a body control module in a given vehicle selected from a fleet of vehicles. In particular, a uid secret key data field is generated in the fob data store using a fleet secret key data field and a vehicle secret key field retrieved from the bcm data store.
Gm Global Technology Operations Llc


08/20/15
20150234692 

Memory management method, memory control circuit unit and memory storage apparatus


A memory management method, a memory control circuit unit using the method, and a memory storage apparatus using the method are provided. The memory management method includes determining whether a use count of the rewritable non-volatile memory module is greater than a use count threshold; based on a result of the determination, sorting each physical erasing unit in a spare area in an ascending manner according to an erasing count of each physical erasing unit in the spare area or according to the number of maximum bit errors of the physical erasing units in the spare area, so as to form a plurality of sorted physical erasing units; and selecting the foremost physical erasing unit from the spare area to write data according to the sorted physical erasing units.
Phison Electronics Corp.


08/06/15
20150220432 

Method and managing at least one non-volatile memory


A method and apparatus for managing at least one nv memory are provided. Each nv memory comprises a plurality of physical blocks.
Mediatek Inc.


07/23/15
20150208075 

Memory management of motion vectors in high efficiency video coding motion vector prediction


In one embodiment of the present invention, a high efficiency video coding codec optimizes the memory resources used during motion vector (mv) prediction. As the codec processes block of pixels, known as coding units (cus), the codec performs read and write operations on a fixed-sized neighbor union buffer representing the mvs associated with processed cus.
Nvidia Corporation


07/16/15
20150199280 

Method and system for implementing multi-stage translation of virtual addresses


A system and method are provided for implementing multi-stage translation of virtual addresses. The method includes the steps of receiving, at a first memory management unit, a memory request including a virtual address in a first address space, translating the virtual address to generate a second virtual address in a second address space, and transmitting a modified memory request including the second virtual address to a second memory management unit.
Nvidia Corporation


07/16/15
20150199279 

Method and system for tracking transactions associated with a system memory management unit of a portable computing device


A method and system for tracking transactions associated with a system memory management unit (“smmu”) includes receiving a plurality of memory requests from a plurality of processing elements and storing contents of each memory request in a transaction history buffer (“thb”). The contents of a memory request stored in the thb may comprise at least one of a security bit; a virtual machine identifier (“vmid”); a stream identifier (“sid”); a smmu context bank that was used; and whether or not the virtual address was present in the translation look-aside buffer.
Qualcomm Incorporated


07/16/15
20150199274 

Implicit i/o send on cache operations


A computer system for implicit input-output send on cache operations of a central processing unit is provided. The computer system comprises an aggregation queue of a central processing unit, storing input-output data of the central processing unit, wherein the aggregation queue transmits the input-output data to an input-output adaptor, and wherein the input-output data is transmitted in parallel with operations of the central processing unit.
International Business Machines Corporation


07/16/15
20150199273 

Implicit i/o send on cache operations


A method for implicit input-output send on cache operations of a central processing unit is provided. The method comprises an aggregation queue of a central processing unit, storing input-output data of the central processing unit, wherein the aggregation queue transmits the input-output data to an input-output adaptor, and wherein the input-output data is transmitted in parallel with operations of the central processing unit.
International Business Machines Corporation


07/09/15
20150194213 

Hierarchical immutable content-addressable memory processor


Improved memory management is provided according to a hierarchical immutable content addressable memory processor (hicamp) architecture. In hicamp, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity.

07/09/15
20150193302 

Selective ecc refresh for on die buffered non-volatile memory


Apparatuses, systems, methods, and computer program products are disclosed for on die buffered non-volatile memory management. A method includes storing data in a first set of non-volatile memory cells.
Sandisk Technologies Inc.


07/09/15
20150193299 

Selective copyback for on die buffered non-volatile memory


Apparatuses, systems, methods, and computer program products are disclosed for on die buffered non-volatile memory management. A method includes storing data in a first set of non-volatile memory cells.
Sandisk Technologies, Inc.


07/02/15
20150187435 

Systems and methods for memory management in a dynamic translation computer system


Systems and methods for managing memory in a dynamic translation computer system are provided. Embodiments may include receiving an instruction packet and processing the instruction packet.
Unisys Corporation


07/02/15
20150186291 

Systems and methods for memory management in a dynamic translation computer system


Systems and methods for managing memory in a dynamic translation computer system are provided. Embodiments may include receiving an instruction packet and processing the instruction packet.
Unisys Corporation


07/02/15
20150186059 

Memory management program, memory management method, and memory management device


A non-transitory computer-readable recording medium stores a memory management program that causes a computer to execute a process. The process includes detecting writing into a memory; and saving, in association with each other in a predetermined storage area, data before the writing which is stored in a data area of a write destination of the detected writing, and context information of a processor at a time of detecting the writing into the memory..
Fujitsu Limited


06/25/15
20150180504 

Method and compressing/decompressing data using floating point


Disclosed are a method and apparatus for compressing/decompressing data using floating points. As technology for compressing/decompressing data using floating points for efficient memory management, there are provided a method and apparatus for compressing/decompressing data using floating points, in which a log table is used to compress/decompress data, whereby not only data loss caused by compression/decompression can be minimized, but also degradation of performance can be prevented through a floating point representation even though the same number of bits are used for compression..
Fci Inc


06/25/15
20150178242 

System and a a remote direct memory access over converged ethernet


A method and a system embodying the method for receiving a remote direct memory access packet comprising an opaque data, a virtual address, and a payload at a virtual network interface card that generated the opaque data; reconstructing a stream identifier by separating the opaque data into an encrypted stream identifier and a first digest; decrypting the encrypted stream identifier; verifying the decrypted stream identifier using the first digest; providing the verified stream identifier to a system memory management unit; and mapping the virtual address and the provided stream identifier by the system memory management unit to a physical address, is disclosed.. .
Cavium, Inc.


06/25/15
20150178198 

Hypervisor managing memory addressed above four gigabytes


Approaches for performing memory management by a hypervisor. A host operating system and a hypervisor are executed on a device.
Bromium, Inc.


06/25/15
20150178190 

Detecting hot spots through flash memory management table snapshots


Decisions about how to correlate logical address to physical addresses in a flash memory (or other non-volatile random access memory) is based at least in part upon how frequently a logical address is accessed over time. Accordingly, software tracks accesses, by logical address, to the stored data using a flash memory metadata structure, and calculates a frequency-of-access value for each logical address of the set of logical addresses corresponding to the relative frequency with which the corresponding logical address is accessed, based, at least in part, on the flash memory metadata structure.
International Business Machines Corporation


06/25/15
20150178157 

Memory management system and method


A memory system and method of operating the same is described, where the memory system is used to store data in a raided manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received.
Violin Memory Inc.


06/25/15
20150178010 

Memory management based on usage specifications


A method is provided for managing a memory device including a plurality of physical memory segments. A logical memory space is classified into a plurality of classifications based on usage specifications.
Macronix International Co., Ltd.


06/18/15
20150172725 

Moving picture coding apparatus and moving picture decoding apparatus


A video encoder (70) for coding moving pictures comprising a buffer (16c) with a plurality of memory areas capable of storing frames composed of top fields and bottom fields, a motion estimation unit (19) operable to code, field by field, inputted pictures performing moving estimation and moving compensation by referring, field by field, to the picture data stored in a memory area, a motion compensation unit (16d), a subtractor (11), a transformation unit (13) and a quantization unit (14), a memory management unit (71) operable to manage, frame by frame, a plurality of memory areas, an inverse quantization unit (16a) and inverse discrete cosine transform unit (16b) operable to decode picture data in coded fields and store the picture data in the decoded field in any of the plurality of memory areas under the management by the memory management unit (71).. .
Panasonic Intellectual Property Corporation Of America


06/18/15
20150172700 

Moving picture coding apparatus and moving picture decoding apparatus


A video encoder (70) for coding moving pictures comprising a buffer (16c) with a plurality of memory areas capable of storing frames composed of top fields and bottom fields, a motion estimation unit (19) operable to code, field by field, inputted pictures performing moving estimation and moving compensation by referring, field by field, to the picture data stored in a memory area, a motion compensation unit (16d), a subtractor (11), a transformation unit (13) and a quantization unit (14), a memory management unit (71) operable to manage, frame by frame, a plurality of memory areas, an inverse quantization unit (16a) and inverse discrete cosine transform unit (16b) operable to decode picture data in coded fields and store the picture data in the decoded field in any of the plurality of memory areas under the management by the memory management unit (71).. .
Panasonic Intellectual Property Corporation Of America


06/18/15
20150172686 

Moving picture coding apparatus and moving picture decoding apparatus


A video encoder (70) for coding moving pictures comprising a buffer (16c) with a plurality of memory areas capable of storing frames composed of top fields and bottom fields, a motion estimation unit (19) operable to code, field by field, inputted pictures performing moving estimation and moving compensation by referring, field by field, to the picture data stored in a memory area, a motion compensation unit (16d), a subtractor (11), a transformation unit (13) and a quantization unit (14), a memory management unit (71) operable to manage, frame by frame, a plurality of memory areas, an inverse quantization unit (16a) and inverse discrete cosine transform unit (16b) operable to decode picture data in coded fields and store the picture data in the decoded field in any of the plurality of memory areas under the management by the memory management unit (71).. .
Panasonic Intellectual Property Corporation Of America


06/18/15
20150172685 

Moving picture coding apparatus and moving picture decoding apparatus


A video encoder (70) for coding moving pictures comprising a buffer (16c) with a plurality of memory areas capable of storing frames composed of top fields and bottom fields, a motion estimation unit (19) operable to code, field by field, inputted pictures performing moving estimation and moving compensation by referring, field by field, to the picture data stored in a memory area, a motion compensation unit (16d), a subtractor (11), a transformation unit (13) and a quantization unit (14), a memory management unit (71) operable to manage, frame by frame, a plurality of memory areas, an inverse quantization unit (16a) and inverse discrete cosine transform unit (16b) operable to decode picture data in coded fields and store the picture data in the decoded field in any of the plurality of memory areas under the management by the memory management unit (71).. .
Panasonic Intellectual Property Corporation Of America


06/18/15
20150172684 

Moving picture coding apparatus and moving picture decoding apparatus


A video encoder (70) for coding moving pictures comprising a buffer (16c) with a plurality of memory areas capable of storing frames composed of top fields and bottom fields, a motion estimation unit (19) operable to code, field by field, inputted pictures performing moving estimation and moving compensation by referring, field by field, to the picture data stored in a memory area, a motion compensation unit (16d), a subtractor (11), a transformation unit (13) and a quantization unit (14), a memory management unit (71) operable to manage, frame by frame, a plurality of memory areas, an inverse quantization unit (16a) and inverse discrete cosine transform unit (16b) operable to decode picture data in coded fields and store the picture data in the decoded field in any of the plurality of memory areas under the management by the memory management unit (71).. .
Panasonic Intellectual Property Corporation Of America




Memory Management topics: Memory Management, Virtual Machine, Storage Device, Volatile Memory, Data Processing, Logical Unit, Virtual Memory, Computer System, Dynamic Data, Base Memory, Database Management System, Data Storage, Defragment, Compatibility, Object Code

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