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Memory Device

Memory Device-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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NEW Systems and methods for establishing a communication link between an implantable medical device and an ...
Pacesetter, Inc.
February 15, 2018 - N°20180049251

Systems and methods are provided for establishing a bi-directional communication link with an implantable medical device. The systems and methods include an implantable medical device (imd) and an external instrument configured to establish a wireless bi-directional communication link there between over a wireless protocol. The wireless bi-directional communication link is established based on a scanning interval. The external instrument includes ...
NEW Video coding tools for in-loop sample processing
Qualcomm Incorporated
February 15, 2018 - N°20180048907

A device includes a memory device configured to store video data including a current block, and processing circuitry in communication with the memory. The processing circuitry configured to obtain a parameter value that is based on one or more corresponding parameter values associated with one or more neighbor blocks of the video data stored to the memory device, the one ...
NEW Page health prediction using product codes decoder in nand flash storage
Sk Hynix Memory Solutions Inc.
February 15, 2018 - N°20180048434

An apparatus of a memory system and an operating method thereof includes: a plurality of memory devices; and a controller including a decoder and a ber predictor, coupled with the plurality of memory devices, configured to perform a decoding iteration includes to conduct nand read and generate nand data; decode in accordance with the nand data and generate decoder information ...
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NEW Process for depositing porous organosilicate glass films for use as resistive random access memory
Versum Materials Us, Llc
February 15, 2018 - N°20180047898

A process for forming a resistive random-access memory device, the process comprising the steps of: depositing a first electrode on a substrate; forming a porous resistive memory material layer on the first electrode, wherein the porous resistive memory layer is formed by (i) depositing a gaseous composition comprising a silicon precursor and a porogen precursor and, once deposited, (ii) removing ...
NEW Semiconductor memory device and method of manufacturing the same
Toshiba Memory Corporation
February 15, 2018 - N°20180047786

According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their ...
NEW Memory devices and memory device forming methods
Micron Technology, Inc.
February 15, 2018 - N°20180047783

Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the ...
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Memory Device Patent Applications
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NEW Three dimensional memory and methods of forming the same
Micron Technology, Inc.
February 15, 2018 - N°20180047747

Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group ...
NEW Semiconductor memory device
Toshiba Memory Corporation
February 15, 2018 - N°20180047744

A semiconductor memory device includes a semiconductor substrate, transistors formed in an upper surface of the semiconductor substrate, a stacked body provided on the semiconductor substrate, a first contact, and a second contact. The transistors are arranged along a first direction. A minimum period of an arrangement of the transistors is a first period. The stacked body includes electrode films. ...
NEW 3d ctf integration using hybrid charge trap layer of sin and self aligned sige nanodot
Applied Materials, Inc.
February 15, 2018 - N°20180047743

Provided are an improved memory device and a method of manufacturing the same. In one embodiment, the memory device may include a vertical stack of alternating oxide layer and nitride layer, the vertical stack having a channel region formed therethrough, a plurality of nanostructures selectively formed on nitride layer of the vertical stack, and a gate oxide layer disposed on ...
NEW Semiconductor memory device and method for manufacturing same
Toshiba Memory Corporation
February 15, 2018 - N°20180047741

A semiconductor memory device includes a stacked body including a plurality of word lines; a semiconductor layer extending through the word lines; a memory cell provided at a part where the semiconductor layer crosses one of the word lines, the memory cell including a plurality of cell layers, the cell layers including a first insulating layer; and at least one ...
NEW Semiconductor device comprising a floating gate flash memory device
Globalfoundries Inc.
February 15, 2018 - N°20180047738

A method of manufacturing a semiconductor device is provided including providing a silicon-on-insulator (soi) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, forming a first transistor device on and in the soi substrate in a logic area of the soi substrate, removing ...
NEW Memory device and method of manufacturing the same
Winbond Electronics Corp.
February 15, 2018 - N°20180047737

Provided is a memory device including a substrate and a gate structure. The gate structure is located on the substrate. The gate structure includes a stack gate and a selection gate aside the stack structure. A topmost surface of the selection gate is lower than a topmost surface of the stack gate.
NEW Memory device having vertical structure
Samsung Electronics Co., Ltd.
February 15, 2018 - N°20180047732

A semiconductor device includes a substrate with an active region, a plurality of conductive line structures on the substrate, an insulating layer separating the plurality of conductive line structures from the substrate, a contact plug between every two adjacent conductive line structures, an insulating spacer structure between each conductive line structure and a corresponding contact plug, a landing pad connected ...
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Memory Device Patent Applications
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  • 2989+ full patent PDF documents of Memory Device-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
NEW Semiconductor memory device and test method therefor
Renesas Electronics Corporation
February 15, 2018 - N°20180047457

A test method for a semiconductor memory device having a plurality of memory cells arranged in a matrix form, the test method including writing first data into a plurality of memory cells, while a plurality of word lines disposed in the columns of the memory cells are deselected, driving the low-potential side bit line of a bit line pair in ...
NEW Memory device with progressive row reading and related reading method
Stmicroelectronics S.r.l.
February 15, 2018 - N°20180047455

A memory device includes a memory array with memory cells arranged in rows and columns and with word lines and bit lines. A dummy structure includes a dummy row of dummy cells and a dummy word line. A first pre-charging stage biases a word line of the memory array. An output stage includes a plurality of sense amplifiers. Each sense ...
NEW High speed sensing for advanced nanometer flash memory device
Silicon Storage Technology, Inc.
February 15, 2018 - N°20180047454

Improved flash memory sensing circuits are disclosed. In one embodiment, a sensing circuit comprises a memory data read block, a memory reference block, a differential amplifier, and a precharge circuit. The precharge circuit compensates for parasitic capacitance between a bit line coupled to a selected memory cell and adjacent bit lines.
NEW Semiconductor memory device
Toshiba Memory Corporation
February 15, 2018 - N°20180047451

A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction ...
NEW Semiconductor memory device
Sk Hynix Inc.
February 15, 2018 - N°20180047450

Provided herein is a semiconductor memory device including a memory cell array including a drain select transistor and a plurality of memory cells, a voltage generator configured to apply a program voltage, first and second pass voltages, and a drain control voltage to the memory cell array, a control logic configured to control the voltage generator so that during a ...
NEW Nonvolatile memory device and storage device including nonvolatile memory device
February 15, 2018 - N°20180047449

A nonvolatile memory device includes a memory cell array, a row decoder circuit, a page buffer circuit, and a control logic circuit. The control logic circuit controls the row decoder circuit and the page buffer circuit to perform: (1) a pre-program of sequentially selecting a plurality of memory blocks and increasing threshold voltages of string selection transistors or ground selection transistors ...
NEW Three-dimensional nonvolatile memory and related read method designed to reduce read disturbance
Samsung Electronics Co., Ltd.
February 15, 2018 - N°20180047448

A nonvolatile memory device performs a read operation comprising first and second intervals. In the first interval the device applies a turn-on voltage to string selection lines and ground selection lines connected to the string selection transistors and the ground selection transistors, respectively. In the second interval, the device applies a turn-off voltage to unselected string selection lines and unselected ...
NEW Memory system with read threshold estimation and operating method thereof
Sk Hynix Memory Solutions Inc.
February 15, 2018 - N°20180047444

An apparatus of a memory system and an operating method thereof includes a plurality of memory devices; and a controller coupled to the plurality of memory devices, wherein the controller is configured to perform a symmetric ovs read with at least an initial read threshold, and create a symmetric read result; perform an asymmetric ovs read with at least the ...
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