|| List of recent Memory Device-related patents
|Alpha ii license management system|
The alpha ii installation architecture requires extra management of per-seat installations to ensure the games are only installed with as many instances as were sold to the site. The license management method manages and enforces proper per-license activation since a mechanism is present on the gaming machines to copy the software which is sold on compact flashes and installed onto hard drives.
|Semiconductor apparatus and method of operating the same|
A semiconductor apparatus includes a memory device configured to include a buffer memory block and a main memory block, and to correct data read from the buffer memory block based on error information, and to perform a program loop to store corrected data in the main memory block, and a memory controller configured to perform an error checking and correction (ecc) operation on the data and to output the error information obtained through the ecc operation to the memory device.. .
|Storage control system with data management mechanism and method of operation thereof|
A method of operation of a storage control system includes: determining a bit error rate of a page; calculating a slope based on the bit error rate; and adjusting a threshold voltage for the page based on the slope for reading a memory device.. .
|Method and device to distribute code and data stores between volatile memory and non-volatile memory|
A method, device, and system to distribute code and data stores between volatile and non-volatile memory are described. In one embodiment, the method includes storing one or more static code segments of a software application in a phase change memory with switch (pcms) device, storing one or more static data segments of the software application in the pcms device, and storing one or more volatile data segments of the software application in a volatile memory device.
|Techniques for surfacing host-side flash storage capacity to virtual machines|
Techniques for surfacing host-side flash storage capacity to a plurality of vms running on a host system are provided. In one embodiment, the host system creates, for each vm in the plurality of vms, a flash storage space allocation in a flash storage device that is locally attached to the host system.
|Configurable light timer and method of receiving data to control the operation of a configurable light timer|
A configurable light timer adapted to receive data to control the operation of the configurable light timer is disclosed. The configurable light timer comprises a control circuit; an input portion coupled to receive a portable memory device by way of a connector on the configurable light timer, wherein the portable memory device stores data to be used by the configurable light timer and is adapted to be removed after the data is downloaded; and a memory coupled to receive the data stored on the portable memory device; wherein control circuit accesses the data from the memory after the data is downloaded and the portable memory device is removed.
|Money transfer smart phone methods and systems|
A mobile device for providing currency exchange, is described. The mobile device includes a computer processor, a memory device having sets of instructions stored thereon, and a camera device configured to photograph an image of currency of a first country's currency.
|Systems and methods for determining consumer shopping corridors|
The disclosed embodiments include systems and methods for determining shopping corridor. In one embodiment, a system is disclosed that may include one or more processors and one or more memory devices storing instructions that, when executed by the one or more processors, performs operations consistent with the disclosed embodiments.
|Devices, systems, and methods for epicardial cardiac monitoring|
Devices, systems, and methods for remotely monitoring physiologic cardiovascular data are disclosed. At least some of the embodiments disclosed herein provide access to the external surface of the heart through the pericardial space for the delivery of the sensor to the epicardial surface of the heart.
|Gaming device and method providing slot game having virtual map driven reel stop position determinations|
Various embodiments of the disclosed gaming device include a housing which supports a plurality of mechanical reels and a plurality of stop input devices which are configured to provide a pachisuro-style slot game. Each of the plurality of reels is associated with a different one of the plurality of stop input devices.
|Method and apparatus for interactive play|
An interactive toy object apparatus having a toy body that includes a plurality of object body portions, an object control circuit secured to the body that includes an object processor, an object memory device, and one or more object transceivers, a plurality of object inputs and object outputs secured to one or more of the object body portions and in communication with the object control circuit; and a first control program stored in the object memory device and operable by the object processor, wherein the interactive object is capable of communicating with a controller, via the one or more object transceivers, to receive or transmit at least one of commands, inputs, and outputs, therebetween.. .
|Methods of forming semiconductor structures including bodies of semiconductor material|
Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material.
|Complementary metal oxide heterojunction memory devices and methods for cycling robustness and data retention|
A memory device is disclosed. The memory device comprises a first metal layer and a first metal oxide layer coupled to the first metal layer.
|Memory device and semiconductor device|
Provided is a memory device with reduced overhead power. A memory device includes a first circuit retaining data in a first period during which a power supply voltage is supplied; a second circuit saving the data retained in the first circuit in the first period and retaining the data saved from the first circuit in a second period during which the power supply voltage is not supplied; and a third circuit saving the data retained in the second circuit in the second period and retaining the data saved from the second circuit in a third period during which the power supply voltage is not supplied.
|Semiconductor memory device and method with auxiliary i/o line assist circuit and functionality|
A semiconductor memory device includes an i/o line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the i/o line on the basis of the read data, a read circuit for receiving the read data transmitted through the i/o line, and an assist circuit for amplifying the read data transmitted through the i/o line. The assist circuit is disposed farther away from a prescribed drive circuit included in the plurality of drive circuits as viewed from the read circuit.
|Nonvolatile memory devices, memory systems and related control methods|
A nonvolatile memory device includes a cell array including a plurality of cell strings extending on a substrate in a vertical direction, a page buffer connected to a plurality of bit lines and configured to store sensing data of the cell array in a sensing operation, a voltage generator configured to provide voltages to a plurality of word lines and the plurality of bit lines, and an input/output buffer configured to temporarily store the sensing data received in a data dump from the page buffer and to output the temporarily stored data to an external device. The nonvolatile memory device further includes control logic configured to set a status of the nonvolatile memory device to a ready state after the sensing data is dumped to the input/output buffer and before recovery of the cell array from a bias voltage of the sensing operation is complete..
|Semiconductor memory device and method of operating the same|
A semiconductor memory device includes strings each configured to include a drain select transistor, memory cells, and a source select transistor coupled in series between a bit line and a common source line and peripheral circuits configured to perform an operation of precharging a bit line so that the precharge level of the bit line varies depending on whether an adjacent unselected memory cell, which is adjacent to a selected memory cell, is in the program state or the erase state, by supplying a first voltage to the adjacent unselected memory cell arranged toward the drain select transistor, a second voltage to the remaining memory cells in order to turn on the remaining memory cells, and a third voltage higher than a bit line precharge voltage to the common source line and perform a read operation of supplying a read voltage lower than the second voltage to the selected memory cell, the second voltage to the remaining memory cells including the adjacent unselected memory cell, and a ground voltage to the common source line.. .
|Nonvolatile memory device, memory system having the same, external power controlling method thereof|
An external power control method includes determining whether to apply a second external voltage to a first node according to a drop of a first external voltage; generating a flag signal according to a drop of the second external voltage when the second external voltage is applied to the first node; transferring a voltage of the first node to a second node in response to the flag signal; and discharging at least one voltage of an internal circuit connected to the second node in response to the flag signal.. .
|Programming and/or erasing a memory device in response to its program and/or erase history|
For one embodiment, a programming method includes programming one or more memory cells of a memory device during a programming operation, determining, internal to the memory device, a number of program pulses required to program a sample of the one or more memory cells of the memory device during the programming operation, and adjusting a program starting voltage level of one or more program pulses applied to the one or more memory cells during a subsequent programming operation in response, at least in part, to the number of program pulses required to program the sample of the one or more memory cells programed during the prior programming operation.. .
|High voltage switch and a nonvolatile memory device including the same|
A high voltage switch of a nonvolatile memory device includes a depletion type nmos transistor configured to switch a second driving voltage in response to an output signal of the high voltage switch; at least one inverter configured to convert a voltage of an input signal of the high voltage switch into a first driving voltage or a ground voltage, wherein the first and second driving voltages are received from an external device; and a pmos transistor configured to transfer the second driving voltage provided to a first terminal of the pmos transistor from the depletion type nmos transistor to a second terminal of the pmos transistor as the output signal in response to an output of the at least one inverter, wherein the output of the at least one inverter is transferred to a gate terminal of the pmos transistor.. .
|Multi-page program method, non-volatile memory device using the same, and data storage system including the same|
A method of programming a non-volatile memory device including a plurality of strings arranged in rows and columns comprises activating all or a part of selection lines in one column at the same time depending upon data to be programmed, driving a bit line corresponding to the one column with a bit line program voltage, and repeating the activating and the driving until bit lines corresponding to the columns are all driven.. .
|Line voltage boost system and method for non-volatile memory devices and memory devices and processor-based system using same|
The voltage of a selected word line is increased beyond the voltage to which a respective string driver transistor is capable of driving the word line by capacitively coupling a voltage to the selected word line from adjacent word lines. The voltage is capacitively coupled to the selected word line by increasing the voltages of the adjacent word lines after a programming voltage has been applied to a string driver transistor for the selected word line and after a string driver voltage has been applied to the gates of all of the string driver transistors in an array..
|Semiconductor memory device using only single-channel transistor to apply voltage to selected word line|
A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines.
|Method of driving phase change memory device capable of reducing heat disturbance|
A method of driving phase change memory device includes initializing all memory cells and programming individually at least two selected memory cells disposed at random positions, wherein the selected memory cells are selected among the initialized memory cells.. .
|Efficient pcms refresh mechanism|
An apparatus is described having invert determination logic circuitry to determine if a read data path that transports data read from a pcms memory device is to be inverted or not inverted as a function of whether information represented by the data was last written in an inverted or non inverted logical state to the pcms memory device during a refresh of said pcms memory device.. .
|Memory device, semiconductor device, and detecting method|
To provide a memory device which can perform verification operation for detecting a memory cell whose data holding time is shorter than a predetermined length, accurately in a short time. Each memory cell includes at least a first capacitor, a second capacitor, and a transistor which functions as a switching element for controlling supply, storage, and release of charge in the first capacitor and the second capacitor.
|Semiconductor memory device|
A semiconductor memory device includes: a plurality of word lines extending in a first direction; first to third bit lines extending in a second direction that intersects with the first direction; a plurality of variable resistance elements each having a first terminal connected to either one of the first and third bit lines; a plurality of active areas extending in a direction oblique to the first direction while intersecting with the first to third bit lines; a plurality of select transistors provided on the active areas and each having a gate connected to a corresponding one of the word lines, and a current path whose one end is connected to a second terminal of a corresponding one of the variable resistance elements; and a plurality of contact plugs each connecting the other end of the current path of a corresponding one of the select transistors to the second bit line, wherein each of the active areas includes two select transistors sharing a diffusion region, the variable resistance elements includes a first variable resistance element group and a second variable resistance element group, the first variable resistance element group including variable resistance elements aligned in the second direction below the first bit line, and each disposed between adjacent two of the word lines, the second variable resistance element group including variable resistance elements aligned in the second direction below the third bit line, and each disposed between adjacent two of the word lines, and the contact plugs are aligned in the second direction below the second bit line, and are each disposed between adjacent two of the word lines.. .
|Resistive memory device|
A resistive memory device includes memory cell array blocks, a reference cell array block, two first and second sink transistors, and a word line. Each of the memory cell array blocks includes a row line, and the reference cell array block includes a reference row line.
|Nonvolatile resistive memory device and writing method|
A writing method for a resistive nonvolatile memory device includes writing data to a resistive nonvolatile memory cell using an up/down write pulse signal when the data is first data type, and writing data to the resistive nonvolatile memory cell using only one of an up write pulse signal and a down write pulse signal when the data is second data type.. .
|Method of making a non-volatile memory (nvm) cell structure|
A non-volatile memory device includes a substrate and a charge storage layer. The charge storage layer comprises a bottom layer of oxide, a layer of discrete charge storage elements on the bottom layer of oxide, and a top layer of oxide on the charge storage elements.
|Non-volatile semiconductor memory device|
A non-volatile semiconductor memory device is proposed whereby voltage can be more flexibly set in accumulating electric charges into a selected memory cell transistor in comparison with a conventional device. In a non-volatile semiconductor memory device (1), when a selected memory cell transistor (115) is caused to accumulate electric charges, high voltage as writing prevention voltage is applied from a pmos transistor (9b) while low voltage as writing voltage is applied from an nmos transistor (15a).
|Ferroelectric random access memory with optimized hardmask|
Device structures, fabrication methods, and design structures for a capacitor of a memory cell of ferroelectric random access memory device. The capacitor may include a first electrode comprised of a first conductor, a ferroelectric layer on the first electrode, a second electrode on the ferroelectric layer, and a cap layer on an upper surface of the second electrode.
|Conductive bridge resistive memory device and method of manufacturing the same|
A conductive bridge resistive memory device is provided, comprising a first electrode, a memory layer electrically coupled to the first electrode, an ion-supplying layer containing a source of ions of a first metal element capable of diffusion into and out of the memory layer, a semiconductor layer disposed between the memory layer and the ion-supplying layer, and a second electrode electrically coupled to the ion-supplying layer.. .
|System and method for integrating a single nanowire into a nanocircuit|
A non-volatile bistable nano-electromechanical switch is provided for use in memory devices and microprocessors. The switch employs carbon nanotubes as the actuation element.
|Heat dissipation unit used in memory device|
A heat dissipation unit used in a memory device includes two heat dissipation sheets, two sides at the top edge of each heat dissipation sheet are bent for respectively forming two lugs having a height difference, and two buckle pieces having a height difference between the two lugs, wherein each lug and each buckle piece of a heat dissipating sheet is mutually stacked onto a corresponding lug and buckle piece of the other heat dissipating sheet, respectively.. .
|Software update methodology|
Software update information is communicated to a network appliance either across a network or from a local memory device. The software update information includes kernel data, application data, or indicator data.
|Multi-element memory device with power control for individual elements|
A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value.
|Selective precharge for power savings|
Embodiments of a memory device are disclosed that may allow for detecting the opportunity for energy savings and implementing the energy savings for each access to the memory device. The memory device may include a plurality of columns, an address comparator, and a timing and control circuit.
|System, method, and apparatus for data, data structure, or encryption key cognition incorporating autonomous security protection|
A system, method, and apparatus for securing a date file or a cognitive encryption key data file stored in a storage medium or memory device. The date file or encryption key file having stored instructions for an embedded autonomous executable program which is executed each time there is an attempt to access, control, or manipulate the encryption key file includes querying a user of the date file or encryption key file, the user environment of the date file or encryption key file, or both, for information required for analyzing a computational environment in relation to required security parameters for the cognitive date file or encryption key file.
|Page miss handler including wear leveling logic|
Embodiments of the invention describe an apparatus, system and method for utilizing a page miss handler having wear leveling logic/modules for memory devices. Embodiments of the invention may track an amount of writes directed towards cells of a memory device, and determine whether a linear address specified by a system write transaction is included in a translation-lookaside buffer (tlb).
|Host controlled enablement of automatic background operations in a memory device|
A host that is coupled to a memory device is configured to read a status register of the memory device to determine if the memory device supports host controlled enablement of automatic background operations. The memory device responds to the host regarding whether the memory device supports host controlled enablement of automatic background operations.
|Dram memory interface|
It is proposed a dram memory interface (40) for transmitting signals between a memory controller device (50) and a dram memory device (52). The dram memory interface comprises: data lines (44) for transmitting data signals; one or more control line(s) for transmitting control signals; one or more address line(s) for transmitting address signals; for each line, a transmitter device (41) connected to a first end of the line and a receiver device (42) connected to a second end of the line; wherein: each line is a single ended line wherein a signal transmitted on the line is referenced to a first reference voltage line (46); and —each line has an termination (z1, z2) on both the first and second ends of the line by connecting a first impedance (z1) to the first end of the line and a second impedance (z2) to the second end of the line..
|Method and system for vicarious downloading or uploading of information|
Methods and systems for vicarious downloading or uploading of information are disclosed herein. In one embodiment, such a system involves a mobile device that includes a memory device capable of storing information or content, and at least one wireless communication component.
|Time controlled switch|
A time controlled electrical switch operable in a sabbath state and in a working day state, comprising a switching component for selectively directing the supply of electrical power, or for selectively transmitting a logical input, to a device; a memory device in which is stored local sunset information, calendar information, and predetermined rules for initiating a state changing event relating to a sabbath state and a working day state; a logical circuit in data communication with the switching component, and a time supplying device. The logical circuit is operable to transmit a signal to the switching component for initiating the state changing event in response to an instantaneous time indicated by the time supplying device and the stored local sunset information, calendar information, and predetermined rules..
|Detection of sleep apnea using respiratory signals|
A method and system for sleep apnea detection are disclosed. The method comprises detecting at least one respiratory signal and utilizing a detection algorithm to automatically detect at least one sleep apnea event from the at least one respiratory signal.
|Methods of manufacturing a semiconductor device|
A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion.
|Low symmetry molecules and phosphonium salts, methods of making and devices formed there from|
Synthesis of molecules and salts is disclosed having low average symmetry and their use in many applications, including but not limited to: as electrolytes in electronic devices such as memory devices including static, permanent and dynamic random access memory, as electrolytes in energy storage devices such as batteries, electrochemical double layer capacitors (edlcs) or supercapacitors or ultracapacitors, electrolytic capacitors, as electrolytes in dye-sensitized solar cells (dsscs), as electrolytes in fuel cells, as a heat transfer medium, high temperature reaction and/or extraction media, among other applications. In particular, synthesis methods and processes to form molecules and salts having low average symmetry using mixed grignard reagents are disclosed..
|Methods and systems for chip-to-chip communication with reduced simultaneous switching noise|
Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated simultaneous switching output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency.
|System and method of performing power on reset for memory array circuits|
The disclosure relates to an apparatus for deactivating one or more predecoded address lines of a memory circuit in response to one or more of the predecoded address lines being activated upon powering on of at least a portion of the apparatus. In particular, the apparatus includes a memory device; an address predecoder configured to activate one or more of a plurality of predecoded address lines based on an input address, wherein the plurality of predecoded address lines are coupled to the memory device for accessing one or more memory cells associated with the one or more activated predecoded address lines; and a power-on-reset circuit configured to deactivate one or more of the predecoded address lines in response to the one or more of the predecoded address lines being activated upon powering on the at least portion of the apparatus..
|Circuit for controlling sense amplifier source node in semiconductor memory device and controlling method thereof|
Provided is a bit line sense amplifier source node control circuit of a semiconductor memory device. The sense amplifier source node control circuit may include a source driver connected between a source node of a sense amplifier and a sense amplifier driving signal line, for driving the source node of the sense amplifier to a set voltage level.
|Variable pre-charge levels for improved cell stability|
Embodiments of a memory device are disclosed that may allow for multiple pre-charge voltages. The memory device may include a plurality of data lines, and a plurality of pre-charge circuits.
|Redundancy circuit and semiconductor memory device including the same|
A redundancy circuit includes a redundancy decoder, a fuse array, and a decoder. The redundancy decoder decodes a redundancy enable signal generated when an address of a defective cell matches an input address.
|Memory core and semiconductor memory device including the same|
A semiconductor device may include a first memory cell connected to a bit-line and a first word-line, a second memory cell connected to a complementary bit-line and a second word-line, and an equalizer. The equalizer may be configured to transition a voltage of the bit-line and the complementary bit-line from a first voltage to a second voltage different from the first voltage at a first time period when the bit-line and complementary bit line are floating, and to transition the voltage of at least one of the bit-line and the complementary bit-line from the second voltage to a third voltage at a second time period after the first time period when the bit-line and complementary bit line are floating, the third voltage being different from the first and second voltages..
|Capacitor structures having improved area efficiency|
Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric material spacing apart the conductive structures may be adjusted to provide optimization of capacitance and voltage threshold.
|Method of storing data in nonvolatile memory device and method of testing nonvolatile memory device|
A method of storing data in a nonvolatile memory device comprises performing a program operation on target memory cells among multiple memory cells, performing a first verify operation to determine whether the target memory cells are in a program pass state or a program fail state, and as a consequence of determining that the target memory cells are in the program pass state, performing a second verify operation to determine whether the target memory cells exhibit a program error symptom.. .
|Data path integrity verification|
Methods and memories for verifying data path integrity are provided. In one such method, a first set of data are read from a first register of a memory device while a second set of data are written to an array of the memory device.
|Memory system and method of operation thereof|
A method of operating a memory system including a non-volatile memory device and a memory controller controlling the non-volatile memory device, includes reading data from a memory cell array in a unit of a page which includes a plurality of sectors; performing error correction decoding on the read data in a unit of a sector of the page; selecting at least one target sector which includes at least one uncorrectable error and selecting at least one pass sector wherein all errors of the pass sector are correctable by the error correction decoding; inhibiting precharging of bit-lines connected to the at least one pass sector while precharging target bit lines connected to the at least one target sector; and performing a read retry operation for data in the at least one target sector.. .
|Selecting memory cells|
A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section.
|Memory cell and memory device having the same|
A memory cell includes a metal oxide semiconductor (mos) capacitor including a gate coupled to a storage node and an electrode coupled to a synchronization control line. The mos capacitor adds a coupling voltage to the gate based on a change in voltage on the synchronization control line.
|Nonvolatile memory device using variable resistive element and memory system having the same|
A nonvolatile memory device, which has an improved read reliability through a refresh operation, and a memory system, are provided. The nonvolatile memory device includes a resistive memory cell, a reference resistor corresponding to the resistive memory cell, a reference sense amplifier electrically connected to the reference resistor and configured to change a transition time of an output value of the reference resistor, and a refresh request signal generator configured to output the refresh request signal for the resistive memory cell when the transition time of an output value of the reference resistor is in a preset refresh requiring period..
|Integrated circuit 3d phase change memory array and manufacturing method|
A 3d phase change memory device can store multiple bits per cell represented by a plurality of non-overlapping ranges of resistance all of which are established by different resistance ranges corresponding to respective amorphous phase thickness of the phase change memory material. An array of access devices can underlie a plurality of conductive layers, separated from each other and from the array of access devices by insulating layers.
|Content addressable memory device having electrically floating body transistor|
A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node.
|Pad structures and wiring structures in a vertical type semiconductor device|
Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position.
|Vertical type semiconductor devices|
A vertical type semiconductor device includes first and second word line structures that include first and second word lines. The word lines surround a plurality of pillar structures, which are provided to connect the word lines to corresponding string select lines.
|Non-volatile memory devices having reduced susceptibility to leakage of stored charges and methods of forming same|
Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode.
|Nonvolatile memory devices with aligned trench isolation regions|
A nonvolatile memory device includes a substrate, an elongate isolation region including a field insulation film disposed in a trench in the substrate, and a word line crossing the insulation region and including a tunneling insulation layer on an active region of the substrate adjacent the isolation region, a charge storage layer on the tunneling insulation layer and a blocking insulation layer on the charge storage layer. A first plane index of a bottom surface of the trench has a first interface trap density and a second plane index of a sidewall of the trench has a second interface trap density equal to or less than the first interface trap density.
|Nonvolatile memory element, nonvolatile memory device, nonvolatile memory element manufacturing method, and nonvolatile memory device manufacturing method|
A nonvolatile memory element including: a first electrode; a second electrode; a variable resistance layer that is between the first electrode and the second electrode and includes, as stacked layers, a first variable resistance layer connected to the first electrode and a second variable resistance layer connected to the second electrode; and a side wall protecting layer that has oxygen barrier properties and covers a side surface of the variable resistance layer. The first variable resistance layer includes a first metal oxide and a third metal oxide formed around the first metal oxide and having an oxygen deficiency lower than that of the first metal oxide, and the second variable resistance layer includes a second metal oxide having an oxygen deficiency lower than that of the first metal oxide..
According to one embodiment, a memory device includes a memory unit including a first subunit and a second subunit, a code encoding unit configured to calculate first redundant data based on first write data and second redundant data based on second write data, and a control unit configured to cause the first write data and the first redundant data to be written in the first subunit and the second write data and the second redundant data to be written in the second subunit. The control unit is configured to control the code encoding unit to start calculation of the second redundant data after all of the writing steps for writing the first write data and the first redundant data have been carried out..
|Memory testing with selective use of an error correction code decoder|
A method includes directing an access of a memory location of a memory device to an error correction code (ecc) decoder in response to receiving a test activation request indicating the memory location. The method also includes writing a test pattern to the memory location and reading a value from the memory location.
|Enhanced dynamic memory management with intelligent current/power consumption minimization|
A low-power state current/power consumption for each volatile memory device in a plurality of volatile memory devices is obtained. Data is copied from a first set of the volatile memory devices to a second set of the volatile memory devices, where the second set of volatile memory devices has a lower current/power consumption than the first set of volatile memory devices.
|Line termination methods and apparatus|
Methods and apparatus for termination of signal lines coupled to a number of memory devices are disclosed. One such method includes adjusting an input impedance of one or more terminals of an interface of a memory device in response to the memory device receiving a particular address.
|Memory device having an adaptable number of open rows|
A memory device comprises a memory array, at least one row address buffer, a set of row data buffers, a row decoder, an array of sense amplifiers, and a demultiplexer. The memory array comprises data elements organized into rows and columns.
|Block or page lock features in serial interface memory|
Embodiments are provided for protecting boot block space in a memory device. Such a memory device may include a memory array having a protected portion and a serial interface controller.
|On-chip traffic prioritization in memory|
According to one embodiment, a memory device is provided. The memory device includes a processing element coupled to a crossbar interconnect.
|On-chip traffic prioritization in memory|
According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to a memory controller in the memory device associated with the memory access request.
|System on chip including memory management unit and memory address translation method thereof|
A system on chip (soc) including a memory management unit (mmu) and a memory address translation method thereof are provided. The soc includes a master intellectual property (ip) configured to output a request corresponding to each of a plurality of working sets; an mmu module comprising a plurality of mmus, each of which is allocated for one of the working sets and translates virtual addresses corresponding to the request into physical addresses; a first bus interconnect configured to connect the mmu module with a memory device and to transmit the request, on which address translation has been performed in at least one of the mmus, to the memory device; and a second bus interconnect configured to connect the master ip with the mmu module and to allocate one of the mmus for each of the working sets..
|Robust and secure memory subsystem|
The present disclosure is generally directed to a more robust memory subsystem having a an improved architecture for managing a memory space. In one embodiment, a method is provided that includes receiving a memory access request from a memory controller and attempting to access the requested data from a first level of memory maintained on the memory device that contains the map cache.
|Non-volatile configuration for serial non-volatile memory|
Example embodiments for configuring a serial non-volatile memory device may comprise a non-volatile configuration register to store a configuration value received from the processor, the configuration value to specify one or more attributes of a memory access operation. The configuration value may be read at least in part in response to power being applied to the memory device..
|Scalable memory system|
A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign.
|Maintaining i/o priority and i/o sorting|
Multiple variants of a data processing system, which maintains i/o priority from the time a process makes an i/o request until the hardware services that request, will be described. In one embodiment, a data processing system has one or more processors having one or more processor cores, which execute an operating system and one or more applications of the data processing system.
|System and method for customized prompting|
A method for providing an audible prompt to a user within a vehicle. The method includes retrieving one or more data files from a memory device.
|Translation quality quantifying apparatus and method|
A system for automating the quality evaluation of a translation. The system may include a computer having a processor and memory device operably connected to one another.