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Memory Device patents



      
           
This page is updated frequently with new Memory Device-related patents. Subscribe to the Memory Device RSS feed to automatically get the update: related Memory RSS feeds.

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Date/App# patent app List of recent Memory Device-related patents
04/17/14
20140109234
 Systems and methods for limiting the number of electronic devices accessing digital rights management (drm) content in a portable memory device patent thumbnailnew patent Systems and methods for limiting the number of electronic devices accessing digital rights management (drm) content in a portable memory device
A system for managing access to drm content is provided with a portable memory device and an electronic device coupled to the portable memory device. The portable memory device includes a public area for storing software and the drm content, and a hidden area for storing data on predetermined addresses among all addresses in the hidden area.
04/17/14
20140108895
 Error correction code circuit and memory device including the same patent thumbnailnew patent Error correction code circuit and memory device including the same
The ecc circuit includes a chien search unit configured to determine whether there is an error in each bit of a data sequence. The chien search unit selects a coefficient of a nonlinear term from among terms of an error locator polynomial as a nonlinear coefficient, separates the error locator polynomial into a first location equation including only linear terms and a second location equation including only nonlinear terms, determines a third location equation by dividing the first location equation by the nonlinear coefficient, determines a fourth location equation by dividing the second location equation by the nonlinear coefficient, and determines whether there is an error for each of the bits by performing an xor operation on a result of the third location equation using the substitution value and a result of the fourth location equation using an arbitrary element of the error locator polynomial as a substitution value..
04/17/14
20140108889
 Memory system for error detection and correction coverage patent thumbnailnew patent Memory system for error detection and correction coverage
A memory system supporting error detection and correction (edc) coverage. The system includes a memory controller and a memory buffer.
04/17/14
20140108884
 Method and apparatus for controlling parity check function of content addressable memory device supporting partial write operation patent thumbnailnew patent Method and apparatus for controlling parity check function of content addressable memory device supporting partial write operation
A method for managing data stored in a content addressable memory (cam) device includes at least the following steps: performing a partial write operation to overwrite only a portion of original write data stored in an entry of the cam device, and storing updated write data in the entry; and updating a parity flag by a first value to indicate that parity data corresponding to the entry of the cam device is invalid. Besides, a cam system employing the method has a cam device, a storage device and a parity flag controller..
04/17/14
20140108841
 Information processing apparatus, control method for the same and storage   medium patent thumbnailnew patent Information processing apparatus, control method for the same and storage medium
An information processing apparatus according to an aspect of this invention includes a wide io memory device stacked on an soc die that includes a cpu, detects the temperatures of multiple memories included in the wide io memory device, and when transitioning to a power saving mode, specifies a memory with a lower temperature, based on the detected temperatures, as the memory to be used with priority in the power saving mode, and stores information for returning from the power saving mode to a normal mode in the specified memory.. .
04/17/14
20140108823
 Security protection for memory content of processor main memory patent thumbnailnew patent Security protection for memory content of processor main memory
Subject matter disclosed herein relates to memory devices and security of same.. .
04/17/14
20140108808
 Host device, semiconductor memory device, and authentication method patent thumbnailnew patent Host device, semiconductor memory device, and authentication method
According to one embodiment, encrypted secret identification information (e-secretid) and the key management information (fkb) are read from a memory device. Encrypted management key (e-fkey) is obtained using the key management information (fkb) and index information (k).
04/17/14
20140108748
 Controllers controlling nonvolatile memory devices and operating methods for controllers patent thumbnailnew patent Controllers controlling nonvolatile memory devices and operating methods for controllers
An operating method of a controller includes selecting bits of code word to be punctured; detecting locations of incapable bits of an input word based on locations of the bits to be punctured and a structure of a generation matrix calculation unit; refreezing the input word such that frozen bits and incapable bits of the input word overlap; generating input word bits by replacing information word bits with frozen bits based on the refreezing result; generating the code word by performing generation matrix calculation on the input word bits; generating output bits by puncturing the code word based on locations of the bits to be punctured; and transmitting the output bits to a nonvolatile memory device.. .
04/17/14
20140108747
 Method of determining deterioration state of memory device and memory system using the same patent thumbnailnew patent Method of determining deterioration state of memory device and memory system using the same
A method is provided for determining a deterioration condition of a memory device. The method includes calculating first information corresponding to a number of bits having a first logic value from data obtained by performing a first read operation on target storage region of the memory device using a first reference voltage as a read voltage, and calculating second information corresponding to a number of bits having a second logic value from data obtained by performing a second read operation on the target storage region using a second reference voltage as the read voltage.
04/17/14
20140108725
 Semiconductor memory device patent thumbnailnew patent Semiconductor memory device
A semiconductor memory device includes a memory cell array configured to include sub memory blocks and a redundancy memory block, data line groups configured to deliver data to be programmed into the sub memory blocks and data read from the sub memory blocks, a redundancy data line group configured to deliver data to be programmed into the redundancy memory block and data read from the redundancy memory block, and switching circuits configured to couple selectively the data line groups to the redundancy data line group.. .
04/17/14
20140108712
new patent Programming mode for multi-layer storage flash memory array and switching control method thereof
The present invention relates to a programming mode for improving the reliability of a multi-layer storage flash memory device in a semiconductor storage field. The present invention provides several programming modes for improving the reliability of a multi-layer storage flash memory device and switching control methods thereof, based on the technical conception of skipping some specific logic pages in the programming process to reduce the impact of the floating gate coupling effect on the operation of the flash memory.
04/17/14
20140108678
new patent Host controller
The present disclosure includes methods, devices, and systems for controlling a memory device. One method for controlling a memory device embodiment includes storing device class dependent information and a command in one or more of host system memory and host controller memory, setting a pointer to the command in a register in a host controller, directing access to the one or more of host system memory and host controller memory with the memory device via the host controller; and executing the command with the memory device..
04/17/14
20140108107
new patent System and method for direct transfer of electronic parking meter data
A single space electronic parking meter mechanism for inserting into an outer parking meter housing is provided. The mechanism includes an inner housing, a payment receiving structure supported by the inner housing and an electronic display screen supported by the inner housing.
04/17/14
20140107401
new patent Digital sound relaxation and sleep-inducing system and method
In one embodiment, an improved-customizability digital sound relaxation system having a sound card receiving port and a collectable sound card are cooperative to play prerecorded natural or other sounds by depressing one of a plurality of sound selector switches and a sound card selector switch. The new sounds of each collectable sound card customize the library of available sounds to individual taste.
04/17/14
20140106549
new patent Low temperature gst process
A deposition process to form a conformal phase change material film on the surface of a substrate to produce a memory device wafer comprises providing a substrate to a chamber of a deposition system; providing an activation region; introducing one or more precursors into the chamber upstream of the substrate; optionally introducing one or more co-reactants upstream of the substrate; activating the one or more precursors; heating the substrate; and depositing the phase change material film on the substrate from the one or more precursors by chemical vapor deposition. The deposited phase change material film comprises gexsbytezam in which a is a dopant selected from the group of n, c, in, sn, and se.
04/17/14
20140106539
new patent Semiconductor isolation structure and method of manufacture
A method of formation of an isolation structure for vertical semiconductor devices, the resulting isolation structure, and a memory device to prevent leakage among adjacent vertical semiconductor devices are described.. .
04/17/14
20140106535
new patent Methods of manufacturing semiconductor devices
A memory device includes a lower interconnection in a semiconductor substrate, the lower interconnection being made of a material different from the semiconductor substrate, a selection element on the lower interconnection, and a memory element on the selection element.. .
04/17/14
20140106518
new patent Nonvolatile memory devices
A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors.
04/17/14
20140104971
new patent Semiconductor memory device
Disclosed is a semiconductor memory device that includes a sense amplifier section. The sense amplifier section includes first n-type diffusion layers, second n-type diffusion layers, first to fifth gates, and first to eighth contacts.
04/17/14
20140104966
new patent Data loading circuit and semiconductor memory device comprising same
A data loading circuit comprises a non-volatile memory configured to store non-volatile data and output a serial data signal based on the stored non-volatile data in response to a power-up operation, a deserializer configured to receive the serial data signal and output multiple data bits at intervals of a unit period based on the received serial data signal, a load controller configured to generate multiple loading selection signals that are sequentially activated one-by-one at each interval of the unit period, and a loading memory unit configured to sequentially store the data bits at each interval of the unit period in response to the loading selection signals.. .
04/17/14
20140104965
new patent Non-volatile memory array and method of using same for fractional word programming
A non-volatile memory device that includes n planes of non-volatile memory cells (where n is an integer greater than 1). Each plane of non-volatile memory cells includes a plurality of memory cells configured in rows and columns.
04/17/14
20140104963
new patent Memory device with reduced on-chip noise
In some examples, a memory device includes multiple memory banks equipped with an isolation switch and dedicated power supply pins. The isolation switch of each memory bank is configured to isolate the memory bank from global signals.
04/17/14
20140104961
new patent Non-volatile memory device with plural reference cells, and method of setting the reference cells
A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells..
04/17/14
20140104959
new patent Memory apparatus and methods
Embodiments of apparatus and methods having a memory device can include a line to exchange information with a string of memory cells and a transistor coupled between the string of memory cells and the line. Such a memory device can also include a module configured to couple a gate of the transistor to a node during a first time interval of a memory operation and decouple the gate from the node during a second time interval of the memory operation.
04/17/14
20140104956
new patent Sensing operations in a memory device
Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output.
04/17/14
20140104955
new patent Programming nonvolatile memory device using program voltage with variable offset
A method of programming a nonvolatile memory device comprises applying at least one test program pulse to selected memory cells located in a scan read area, performing a scan read operation on the selected memory cells following application of the at least one test program pulse to detect at least one one-shot upper cell, calculating an offset voltage corresponding to a scan read region at which the scan read operation is performed, setting a program start bias using the offset voltage, and executing at least one program loop using the program start bias.. .
04/17/14
20140104954
new patent Non-volatile semiconductor memory having multiple external power supplies
A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory.
04/17/14
20140104949
new patent Reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device
A solution for reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device is disclosed.. .
04/17/14
20140104948
new patent Split block decoder for a nonvolatile memory device
A non-volatile memory device having a memory array organized into a plurality of memory blocks, having either planar memory cells or stacks of cells. Row decoding circuitry of the memory device is configured to select a group of the plurality of memory blocks in response to a first row address, and to select a memory block of the group for receiving row signals in response to a second row address.
04/17/14
20140104945
new patent Nonvolatile memory devices and methods forming the same
Provided are nonvolatile memory devices and methods of forming the same. The nonvolatile memory device includes a plurality of word lines, a ground select line, string select line, and a dummy word line.
04/17/14
20140104943
new patent Accelerated soft read for multi-level cell nonvolatile memories
A memory device includes a memory array comprising multi-level memory cells, and control circuitry coupled to the memory array. The control circuitry is configured to perform accelerated soft read operations on at least a portion of the memory array.
04/17/14
20140104940
new patent Internal voltage generating circuit of phase change random access memory device and method thereof
An internal voltage generating circuit includes a divided voltage generator configured to generate a divided voltage by dividing a feedback internal voltage level at a division ratio corresponding to an operation mode control signal, a voltage detector configured to detect a level of the divided voltage based on a reference voltage level, an internal voltage generator configured to receive a supply voltage as power source and generate the internal voltage in response to an output signal of the voltage detector, and an under-driving unit configured to under-drive an internal voltage terminal to a supply voltage in an under-driving operation region that is determined in response to the operation mode control signal.. .
04/17/14
20140104938
new patent Memory device architecture
Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.. .
04/17/14
20140104937
new patent Memory device with timing overlap mode
In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command.
04/17/14
20140104931
new patent Nonvolatile memory device and method of performing forming the same
A nonvolatile memory device including a control unit configured to read resistance value information for each of memory cells as initial resistance value information and store it temporarily before a voltage pulse for forming is applied, to set resistance value information as a threshold value serving as a target for completion of the forming, the resistance value information being obtained by multiplying the initial resistance value information by a predetermined coefficient, and to repeat application of the voltage pulse for forming and reading of the resistance value information until a resistance value indicated by the resistance value information on the memory cell becomes lower than a resistance value indicated by the threshold value.. .
04/17/14
20140104930
new patent Semiconductor memory device
A semiconductor memory device comprises a memory cell array including plural memory cells provided at the intersections of plural first lines and plural second lines; and a write circuit. The write circuit, on execution of a write operation, executes a first step of applying a voltage across the first and second lines connected to a data-write-targeted, selected memory cell, and a different voltage across the first and second lines connected to a data-write-untargeted, unselected memory cell of the plural memory cells and, after execution of the first step, executes a second step of applying a voltage, required for data write, across the first and second lines connected to the selected memory cell, and bringing at least one of the first and second lines connected to the unselected memory cell into the floating state..
04/17/14
20140104925
new patent Cross-point variable resistance nonvolatile memory device and reading method for cross-point variable resistance nonvolatile memory device
A cross-point variable resistance nonvolatile memory device comprises: a memory cell array; a column decoder and pre-charge circuit which pre-charges a selected word line to a first voltage in a period p1 among the period p1, a period p2, and a period s that are included in this order in a read operation of a memory cell; a low decoder driver which pre-charges a selected word line to the first voltage in the periods p1 and p2 and sets the selected word line to a third voltage different from the first voltage in the period s; a feedback controlled bit line voltage clamp circuit which sets the selected bit line to a second voltage in the periods p2 and s; and a sense amplifier which determines the resistance state in a memory cell at a cross-point of the selected word line and the selected bit line in the period s.. .
04/17/14
20140104923
new patent Resistive memory devices and methods of operating the same
Resistive memory driving methods are provided. The methods may include applying an operating voltage set according to a mode of operation to a selected word line among the plurality of word lines and a selected bit line among the plurality of bit lines within a line delay period..
04/17/14
20140104921
new patent Semiconductor memory device having otp cell array
Provided is a semiconductor memory device. The semiconductor includes a one time programmable (otp) cell array, a converging circuit and a sense amplifier circuit.
04/17/14
20140104918
new patent Interconnection for memory electrodes
Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level..
04/17/14
20140104917
new patent Semiconductor memory device including plurality of memory chips
A semiconductor memory device includes a plurality of memory chips each including a chip identification (id) generation circuit. The chip id generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip id generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip id numbers of the plurality of device chips.
04/17/14
20140104915
new patent Semiconductor memory device
A semiconductor memory device includes a memory cell, a pair of local bit lines connected to the memory cell, first and second transistors, one end of the current channel of each connected to a power supply and the other end of the current channel of each connected to one of the local bit lines, third and fourth transistors, one end of the current channel of each connected to one of the local bit lines, the other end of the current channel of each connected to one of the global bit lines, fifth and sixth transistors, one end of the current channel of each connected to one of the global bit lines and the other end of the current channel of which connected to the power supply. The device further includes a control unit configured to control the transistors..
04/17/14
20140104263
new patent Semiconductor devices having image sensor and memory device operation modes
A semiconductor device may include a plurality of banks; and a control unit configured to receive a command from an external device and independently control the plurality of banks according to the received command. Each bank comprises a pixel array including a plurality of pixels; a row decoder configured to activate word lines connected to the plurality of pixels under control of the control unit; a column decoder configured to activate bit lines connected to the plurality of pixels under control of the control unit; a sense amplifier and write driver configured to control and detect respective voltages of the activated bit lines to provide respective amplified voltages; and an input/output buffer configured to output data states of the pixels based on the respective amplified voltages.
04/17/14
20140104176
new patent Ultra-compact keyboard
An embodiment of the invention provides a method of character recognition where input is received from an actuated key. The angle of the input is determined with a sensor, wherein the angle of the input includes pressure on a first axis, pressure on a second axis, and/or pressure on an additional axis.
04/17/14
20140104174
new patent Ultra-compact keyboard
An embodiment of the invention provides a method of character recognition where input is received from an actuated key. The angle of the input is determined with a sensor, wherein the angle of the input includes pressure on a first axis, pressure on a second axis, and/or pressure on an additional axis.
04/17/14
20140103955
new patent System and method for automated failure detection of hold-up power storage devices
A fault detection circuit is utilized to automatically detect faults in hold-up power storage devices. The fault detection circuit includes a hold-up monitoring circuit and a memory device.
04/17/14
20140103509
new patent Semiconductor device and method of forming conductive ink layer as interconnect structure between semiconductor packages
A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An opening is formed in a first surface of the encapsulant by etching or lda.
04/17/14
20140103419
new patent Non-volatile memory device and method for forming the same
A method for forming a non-volatile memory device includes: (a) forming an isolation structure on a circuit-forming surface of a semiconductor substrate to define an array of cell forming regions; (b) forming a gate structure array including a plurality of gate structures disposed above the cell forming regions and each having a first side and a second side; (c) performing ion implantation to form drain regions and a common source region; and (d) forming drain contacts to the drain regions, and a common source contact to the common source region.. .
04/17/14
20140103418
new patent Sonos type stacks for nonvolatile changetrap memory devices and methods to form the same
A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate.
04/17/14
20140103283
new patent Variable resistance memory device and method of fabricating the same
Disclosed herein are a variable resistance memory device and a method of fabricating the same. The variable resistance memory device may include a first electrode; a second electrode; and a variable resistance layer configured to be interposed between the first electrode and the second electrode, wherein the variable resistance layer includes a si-added metal oxide..
04/17/14
20140103125
new patent Apparatus and method for thermal management of a memory device
A system and method for thermal management of a memory device is described. In an embodiment, one or more thermal sensors sends a signal to a thermal control module indicating that a pre-determined temperature threshold for a memory device or devices has been reached.
04/10/14
20140101748
Adaptive system behavior change on malware trigger
A hardware secured flag mechanism which is activated by trusted anti-malware (am) software. Upon being activated, the information handling system takes action to reduce user exposure even if the am software is subsequently subverted.
04/10/14
20140101519
Non-volatile memory device having adjustable read voltage, memory system comprising same, and method of operating same
A nonvolatile memory device comprises a memory cell array comprising a selected page comprising multiple error correction code (ecc) units, and a voltage generation unit configured to generate a read voltage to read data from the selected page. Read voltage levels are set individually for the respective ecc units according to data detection results for each of the ecc units.
04/10/14
20140101518
Dynamic graduated memory device protection in redundant array of independent memory (raim) systems
Dynamic graduated memory device protection in redundant array of independent memory (raim) systems that include a plurality of memory devices is provided. A first severity level of a first failing memory device in the plurality of memory devices is determined.
04/10/14
20140101514
Method of performing write operation or read operation in memory system and system thereof
A method of performing a write operation or a read operation in a memory system includes compressing data of a first size unit, generating a plurality of types of error checking and correction (ecc) information based on the compressed data, combining the compressed data and the plurality of types of ecc information in units of a second size, and writing the information combined in units of the second size into a memory device.. .
04/10/14
20140101513
Method of operating cyclic redundancy check in memory system and memory controller using the same
A method of performing a cyclic redundancy check (crc) operation in a memory system, and a memory controller that uses the same. The method includes initializing a linear feed-back shift register (lfsr) circuit in a crc polynomial, generating crc parity information with respect to input data to be stored in a memory device by using the lfsr circuit, and generating a crc code with respect to the input data based on the crc parity information, such that the initialization of the lfsr circuit is set such that a register initial value of the lfsr circuit is determined to satisfy a condition that, when data input to the lfsr circuit is first state information, the crc parity information generated from the lfsr circuit is second state information..
04/10/14
20140101490
Apparatus and methods for providing data integrity
The present disclosure includes apparatus (e.g., computing systems, memory systems, controllers, etc.) and methods for providing data integrity. One or more methods can include, for example: receiving a number of sectors of data to be written to a number of memory devices; appending first metadata corresponding to the number of sectors and including first integrity data to the number of sectors, the first metadata has a particular format; generating second integrity data to be provided in second metadata, the second integrity data corresponding to at least one of the number of sectors (wherein the second metadata has a second format); and generating third integrity data to be provided in the second metadata, the third integrity data including error data corresponding to the second integrity data and the at least one of the number of sectors..
04/10/14
20140101481
Per-rank channel marking in a memory system
Channel marking is provided in a memory system that includes a memory channel with a plurality of memory devices. The memory devices are arranged into a first group of memory devices and a second group of memory devices.
04/10/14
20140101395
Semiconductor memory devices including a discharge circuit
Semiconductor memory devices are provided. Each of the semiconductor memory devices may include first and second memory cells.
04/10/14
20140101381
Managing banks in a memory system
Systems and methods are provided that facilitate memory storage in a multi-bank memory device. The system contains a memory controller and a memory array communicatively coupled to the memory controller.
04/10/14
20140101380
Managing banks in a memory system
Systems and methods are provided that facilitate memory storage in a memory device. The system contains a memory controller and a memory array communicatively coupled to the memory controller.
04/10/14
20140101373
Method of managing data storage device and data storage device
A method of managing a data storage device including a memory controller and a memory device includes: calculating a first sequential and consecutive write cost (scwc) according to a garbage collection (gc) write operation policy, a second scwc according to a slack space recycling (ssr) write operation policy and a third scwc according to an in-place updating (ipu) write operation policy respectively, in response to a write request in the memory controller; determining a write operation policy which has a minimum cost of the first through third scwcs; and writing data in a selected segment in the memory device according to the determined write operation policy.. .
04/10/14
20140101372
Memory system and read reclaim method thereof
A memory system includes a nonvolatile memory device including a first memory area formed of memory blocks which store n-bit data per cell and a second memory area formed of memory blocks which store m-bit data per cell, where n and m are different integers, and a memory controller configured to control the nonvolatile memory device. The memory controller is configured to execute a read operation, and to execute a read reclaim operation in which valid data of a target memory block of the second memory area is transferred to one or more memory blocks of the first memory area, the target memory block selected during the read operation.
04/10/14
20140101369
Methods, devices and systems for physical-to-logical mapping in solid state drives
A data storage device comprises a plurality of non-volatile memory devices storing physical pages, each stored at a predetermined physical location. A controller may be coupled to the memory devices and configured to access data stored in a plurality of logical pages (l-pages), each associated with an l-page number that enables the controller to logically reference data stored in the physical pages.
04/10/14
20140101368
Binding microprocessor to memory chips to prevent re-use of microprocessor
A processor is provided that binds itself to a circuit such that the processor cannot be subsequently reused in other circuits. On a first startup of the processor, a memory segment of an external volatile memory device is read to obtain information prior to initialization of the memory segment.
04/10/14
20140100905
Home tour and open house scheduler
A computer-implemented method includes providing to a user access, via an electronic network, to a memory device on which are stored listings of parcels of real property. A selection of a set of the stored listings is received from the user via the electronic network.
04/10/14
20140100838
System, method and apparatus for handling power limit restrictions in flash memory devices
A system, method and apparatus for dynamic power management including creating a model for each task of multiple tasks performed by a circuit, the model including a corresponding power requirement value for each task, selecting each task for execution, executing the selected task when the corresponding power requirement value does not exceed an average power consumption cap of an execution window, determining an actual power consumption of the selected task during execution of the selected task and storing the actual power consumption corresponding to the selected task as the corresponding power requirement value for the selected task. A memory system can include a memory die, a data bus coupled to the memory die, a power supply coupled to the memory die, a power monitor coupled to the memory die and the power supply and a controller coupled to the data bus and the memory die..
04/10/14
20140100757
System and method for controlling labor in a model vehicle
A system and method is provided for using load data to control a feature in a model vehicle. In one embodiment of the present invention, a model vehicle includes a controller in communication with a remote control, a motor module, a smoke module, a sound module, and a memory device.
04/10/14
20140100740
Vehicle user interface systems and methods
A control system for mounting in a vehicle and for providing information to a portable electronic device for processing by the portable electronic device is shown and described. The control system includes a first interface for communicating with the portable electronic device and a memory device.
04/10/14
20140100700
Air conditioning control system, air conditioning control method and recording medium
An air conditioning control system comprises an air conditioning controller, air conditioning outdoor equipment and air conditioning indoor equipment. The air conditioning controller acquires the age of a user and causes this age to be stored in an auxiliary memory device.
04/10/14
20140099761
Three dimensional semiconductor memory devices and methods of forming the same
Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate.


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