Images List Premium Download Classic

Memory Device

Memory Device-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


loading
Superlattice memory and crosspoint memory device
Kabushiki Kaisha Toshiba
August 10, 2017 - N°20170229645

According to one embodiment, a memory device includes a superlattice structure portion containing first chalcogen-compound layers and second chalcogen-compound layers differing in composition from the first chalcogen-compound layers are alternately deposited, a first layer provided on one of main surfaces of the superlattice structure portion in a deposition direction thereof, which has a larger energy gap than that of the ...
Methods, apparatuses, and circuits for programming a memory device
Micron Technology, Inc.
August 10, 2017 - N°20170229644

Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.
Low magnetic moment materials for spin transfer torque magnetoresistive random access memory devices
International Business Machines Corporation
August 10, 2017 - N°20170229642

A magnetoresistive random access memory device (mram) device is described. The mram device has a stack arrangement in which a tunnel barrier layer is formed over a magnetizable reference layer, a metal layer is formed over the tunnel barrier layer, a free layer of a magnetizable material is formed over the metal layer, and an oxide layer is formed over ...
Memory Device Patent Pack
Download 2989+ patent application PDFs
Memory Device Patent Applications
Download 2989+ Memory Device-related PDFs
For professional research & prior art discovery
inventor
  • 2989+ full patent PDF documents of Memory Device-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Magnetic memory device
Kabushiki Kaisha Toshiba
August 10, 2017 - N°20170229640

According to one embodiment, a magnetic memory device includes a first magnetic body and a second magnetic body. The first magnetic body extends in a first direction. The second magnetic body extends in the first direction. A distance between the second magnetic body and the first magnetic body changes periodically along the first direction.
Semiconductor memory device
Kabushiki Kaisha Toshiba
August 10, 2017 - N°20170229577

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a pillar structure, at least one charge storage film, and a first electrode. The stacked body includes electrode films stacked separately from each other. The pillar structure is provided in the stacked body and includes a semiconductor layer extending in stacking direction of the stacked body. ...
Non-volatile memory device having reduced drain and read disturbances
Semiconductor Manufacturing International (shanghai) Corporation
August 10, 2017 - N°20170229540

A source-drain structure is disclosed. The source-drain structure includes a substrate containing a drain region and a source region. The drain region includes a lightly-doped ultra-shallow junction and a heavily-doped region, and a drain-substrate junction disposed in the vicinity of a junction between a side portion and a bottom portion of the lightly-doped ultra-shallow junction and the substrate, a plurality ...
Memory Device Patent Pack
Download 2989+ patent application PDFs
Memory Device Patent Applications
Download 2989+ Memory Device-related PDFs
For professional research & prior art discovery
inventor
  • 2989+ full patent PDF documents of Memory Device-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Non-volatile memory device and structure thereof
Taiwan Semiconductor Manufacturing Company Ltd.
August 10, 2017 - N°20170229515

In the present disclosure, a non-volatile memory cell comprises a data storage unit, a selection unit and a switching unit. The data storage unit is configured to store an information bit and has a first end and a second end. The first end is coupled to a bit line. The selection unit is configured to access the data storage unit, ...
Memory device
Kabushiki Kaisha Toshiba
August 10, 2017 - N°20170229514

According to one embodiment, a memory device includes a first interconnect group, a second interconnect group, and a memory cell. In the first interconnect group, first interconnects are stacked. The first interconnect group includes first regions in which the first interconnects are formed along a first direction, and a second region in which first contact plugs are formed on the ...
Superlattice memory and crosspoint memory device
Kabushiki Kaisha Toshiba
August 10, 2017 - N°20170229513

According to one embodiment, a memory includes a resistance change layer includes a first chalcogenide layer, and a second chalcogenide layer having a composition different from that of the first chalcogenide layer which are stacked alternately, and the resistance change layer having a superlattice structure, and a semiconductor layer of a first conductivity type provided on a one of main ...
Non-volatile memory device
Kabushiki Kaisha Toshiba
August 10, 2017 - N°20170229476

A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a ...
Semiconductor memory device
Kabushiki Kaisha Toshiba
August 10, 2017 - N°20170229475

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, and a charge storage film. The stacked body is provided on the substrate. The stacked body includes a plurality of first insulating films and a plurality of electrode films alternately stacked one layer by one layer. The semiconductor pillar is provided inside the ...
Semiconductor memory device and method for manufacturing same
Kabushiki Kaisha Toshiba
August 10, 2017 - N°20170229474

A semiconductor memory device according to one embodiment includes a stacked body, a semiconductor pillar and a plurality of charge storage films. The stacked body includes a plurality of electrode films and air gaps. The plurality of electrode films are disposed to be separated from each other along a first direction. Each of the air gaps is made between the ...
Semiconductor memory device having voids between word lines and a source line
Kabushiki Kaisha Toshiba
August 10, 2017 - N°20170229473

According to an embodiment, a semiconductor memory device includes first and second stacked bodies, first and second memory parts, and an insulating part. The first stacked body includes first conductive layers and first insulating layers alternately arranged in a first direction. The second stacked body includes second conductive layers and second insulating layers alternately arranged in the first direction. The ...
Memory Device Patent Pack
Download 2989+ patent application PDFs
Memory Device Patent Applications
Download 2989+ Memory Device-related PDFs
For professional research & prior art discovery
inventor
  • 2989+ full patent PDF documents of Memory Device-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Semiconductor memory device and operating method thereof
Sk Hynix Inc.
August 10, 2017 - N°20170229189

There are provided a semiconductor memory device and an operating method thereof. A semiconductor memory device may include a memory cell array, a peripheral circuit, a control logic, and one or more programs. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a program operation on the memory cell array. The control logic ...
Calibrating optimal read levels
Western Digital Technologies, Inc.
August 10, 2017 - N°20170229186

After a predetermined period of time in a life cycle of a flash memory device, a plurality of reliability values corresponding to a plurality of reads of one or more of the plurality of memory cells are generated; each of the reads using a variation of a predetermined read level voltage. An offset voltage is then identified, offset from the ...
Semiconductor memory device and operating method thereof
Sk Hynix Inc.
August 10, 2017 - N°20170229185

A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation or erase operation of the memory cell array, and a control logic controlling the peripheral circuit. The control logic controls the peripheral circuit such that a first program allowable voltage applied to bit lines of the memory cell ...
Semiconductor memory device, erasing method and programing method thereof
Winbond Electronics Corp.
August 10, 2017 - N°20170229184

A semiconductor memory device, an erasing method and a programming method thereof which can improve yields and utilization efficiency of a memory array are provided. The semiconductor memory device includes a memory array, which includes a plurality of nand strings; a page buffer/sensing circuit (170), which is connected to the nand strings of the memory array through bit lines and ...
Fast programming memory device
Micron Technology, Inc.
August 10, 2017 - N°20170229183

In an embodiment of a memory device including a matrix of memory cells wherein the memory cells are arranged in a plurality of memory cells strings each one including at least two serially-connected memory cells, groups of at least two memory cells strings being connected to a respective bit line, and wherein said memory cells are adapted to be programmed ...
Nonvolatile semiconductor memory device
Kabushiki Kaisha Toshiba
August 10, 2017 - N°20170229181

A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has ...
Memory devices with a transistor that selectively connects a data line to another data line ...
Micron Technology, Inc.
August 10, 2017 - N°20170229180

In an example, a memory device has a first string of memory cells selectively connected to a first data line, a second string of memory cells selectively connected to a second data line, and a transistor that selectively connects the first data line to the second data line.
Non-volatile memory device and operating method thereof
Nuvoton Technology Corporation
August 10, 2017 - N°20170229177

A non-volatile memory (nvm) device includes a logic memory circuit, a nvm element, a writing circuit and a reading circuit. The input terminal of the writing circuit and the output terminal of the reading circuit are coupled to the output terminal of the logic memory circuit. The first output terminal of the writing circuit and the first input terminal of ...
Loading