|| List of recent Memory Device-related patents
| Nonvolatile memory device having authentication, and methods of operation and manufacture thereof|
A memory device package encloses two separate die, one being a standard nonvolatile memory integrated circuit (“ic”) die, and the other being any suitable authentication ic die. Either die may be stacked upon the other, or the die may be placed side-by-side.
| Memory system and wear-leveling method thereof|
Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller.
| Semiconductor memory devices including error correction circuits and methods of operating the semiconductor memory devices|
A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit.
| Semiconductor memory device|
A crc code is generated from an original data, a bch code is generated with respect to the original data and the crc code, and the original data, the crc code, and the bch code are recorded in pages selected from different planes of a plurality of memory chips. An rs code is generated from the original data across pages, a crc code is generated with respect to the rs code, a bch code is generated with respect to the rs code and the crc code, and the rs code, the crc code, the bch code are recorded in a memory chip different from a memory chip including the original data.
| Semiconductor memory device|
According to one embodiment, a semiconductor memory device includes memory cells each given one of threshold voltages to store data, and a controller configured to use read voltages to determine threshold voltages of the memory cells. The controller is configured to use voltages over a window to read data from the memory cells to determine distribution of the threshold voltages of the memory cells to estimate a read voltage.
| Systems and methods for managing data in a system for hibernation states|
The present application is directed to systems and methods for managing data in a system for hibernation states. In one implementation, a memory device comprises a controller memory, a main memory, a buffer to the main memory and a controller comprising a processor.
| Mitigate flash write latency and bandwidth limitation|
A method of operating a memory system is provided. The method includes a controller that regulates read and write access to one or more flash memory devices that are employed for random access memory applications.
| Semiconductor memory device|
According to one embodiment, a semiconductor memory device includes: string units including a plurality of memory cells stacked above a semiconductor substrate; and a control circuit configured to perform an erase operation per a block, the block including the string units, the control circuit being configured to perform an erase verify operation per string unit.. .
| Memory device|
According to an embodiment of the invention, a memory device includes an interface unit, a determining unit, a second command generating unit, and a processor. The interface unit receives a first command from the outside of the memory device.
| Linear programming based decoding for memory devices|
Technologies are generally described herein for linear programming based decoding for memory devices. In some examples, a cell threshold voltage level of a memory cell is detected.
| Memory device and computer system|
A memory device according to an embodiment includes a non-volatile storage device from which data is read and to which data is written, an interface that is connected to the host device by a multiple upstream lanes and/or a multiple downstream lanes and performs data communication in both directions with the host device, and a memory controller. The memory controller changes a connection state of each lane on the basis of lane settings which are determined on the basis of at least one of an amount of data transmitted and the sequentiality of data when the data is transmitted between the memory device and the host device..
| Non-volatile memory based system ram|
A memory module includes an input/output (i/o) interface adapted to fit into a system random access memory (ram) socket. The module also includes at least one controller coupled to the i/o interface, the controller comprising a plurality of registers, and a plurality of non-volatile memory devices coupled to the controller.
| Storage control system with data management mechanism and method of operation thereof|
A method of operation of a storage control system includes: calculating a throttle threshold; identifying a detection point based on the throttle threshold; and calculating a number of write/erase cycles based on the detection point and the throttle threshold for writing a memory device.. .
| Data processing apparatus and control method|
A connected access request is generated by connecting access requests that are issued within a period of carrying out connections from when a initially received leading access request is issued. At this time the period of carrying out connections is set so that access to data corresponding to the connected access request is completed within a time from when the leading access request is issued until other access to a memory device is performed..
| Semiconductor memory device capable of testing signal integrity|
According to one embodiment, a semiconductor memory device includes a memory cell array, a first buffer, a second buffer, an interface unit and a controller. Data is transferred between the interface unit and the first buffer.
| System for accessing and browsing a plc provided within a network|
Certain exemplary embodiments can comprise a method, comprising: recognizing, by a plc, that a memory device has been connected to the plc; and configuring the plc via a plc executable software program resident on the memory device. Certain exemplary embodiments can comprise a method, comprising: via a plc network interface: presenting a plc network as a namespace shell extension of an operating system of a non-plc information device; and rendering, to a user of the non-plc information device, the plc network as a node of a network.
| Systems, methods and devices for configuring wagering game devices based on shared data|
Gaming devices, gaming systems, methods of configuring gaming devices, and computer programs for configuring gaming devices are featured. A gaming machine is disclosed for communicatively coupling to peer gaming machines via a peer-to-peer network.
| Method of manufacturing nonvolatile semiconductor memory device|
According to one embodiment, a method includes forming first and second gate patterns each including a structure stacked in order of a first insulating layer, a floating gate layer, a charge trap layer, a second insulating layer and a dummy layer on a semiconductor layer, implanting impurities in the semiconductor layer by an ion implantation using the first and second gate patterns as a mask, forming a third insulating layer on the semiconductor layer, the third insulating layer covering side surfaces of the first and second gate patterns, and forming first and second concave portions, the first concave portion formed by removing the dummy layer of the first gate pattern, the second concave portion formed by removing the dummy layer, the second insulating layer, the charge trap layer and the floating gate layer of the second gate pattern.. .
| Phase change memory device having self-aligned bottom electrode and fabrication method thereof|
A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer..
| 3-dimensional non-volatile memory device including a selection gate having an l shape|
A 3-dimensional (3-d) non-volatile memory device includes a first channel protruding from a substrate, a selection gate formed on sidewalls of the first channel and in an l shape, and a gate insulating layer interposed between the first channel and the selection gate and surrounding the first channel. A method of manufacturing a 3-d non-volatile memory device includes forming first channels protruding from a substrate, forming a first gate insulating layer surrounding the first channels, and forming first selection gates having an l shape on sidewalls of the first channels on which the first gate insulating layers are formed..
| Optical closed loop microresonator and thyristor memory device|
A monolithic semiconductor device that includes a waveguide structure optically coupled to an optical resonator. The optical resonator is adapted to process light at a predetermined wavelength.
| Image processing apparatus, image processing method, and memory device in which image processing program is stored|
Provided is an image processing apparatus including an edge identifying portion that generates an edge image in which an edge is identified at each pixel in an input image; a mask-image generating portion that distinguishes an edge direction at a pixel of interest in the input image, that calculates a difference between pixel values of pixels that are positioned perpendicular to the edge direction and that are positioned symmetrically to each other, with the pixel of interest located at a center thereof, and that generates a mask image in which a pixel value of the pixel of interest is increased as that difference decreases; an enhancement-filter image generating portion that generates an enhancement-filter image by multiplying pixel values of pixels of the edge image by pixel values of the mask image; and a combining portion that generates an output image by combining the input image and the enhancement-filter image.. .
| Memory device and memory system including the same|
A memory device may be provided which includes a memory cell array including a plurality of sub arrays each sub array having a plurality of memory cells connected to bit lines; an address buffer configured to receive a row address and a column address; and a column decoder configured to receive the column address from the address buffer and, for each of the sub arrays, to select a column selection line corresponding to the column address, from among a plurality of column selection lines, based on different offset values applied to the sub arrays, respectively. The selected column selection lines correspond to bit lines having different physical locations, respectively, according to the different offset values..
| Memory device refresh commands on the fly|
On the fly switching from one memory device refresh rate to another is provided. Control logic associated with the memory device detects a condition to switch from a currently-applied refresh rate to a different refresh rate.
| Semiconductor memory device for performing disable operation using anti-fuse and method thereof|
A semiconductor memory device for performing a disable operation using an anti-fuse, and method thereof are provided. The semiconductor memory device according to an example embodiment includes a fuse circuit including at least one anti-fuse configured to store fuse data, a memory circuit configured to at least one of read data stored in a memory cell and write data to the memory cell and a fuse controller configured to disable a read/write operation of the memory circuit based on the fuse data..
| Nonvolatile memory device, read method for nonvolatile memory device, and memory system incorporating nonvolatile memory device|
A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read data after the strobe signal is toggled a predetermined number of times.. .
| Bridge device architecture for connecting discrete memory devices to a system|
A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices in response to global memory control signals having a format or protocol that is incompatible with the memory devices. The discrete memory devices can be commercial off-the-shelf memory devices or custom memory devices which respond to native, or local memory control signals.
| Chip die and semiconductor memory device including the same|
A chip die including a first input/output (i/o) pad configured to transmit/receive an i/o signal of a memory cell array included in the chip die; a second i/o pad configured to, if a stacked chip die exists on the chip die, transmit/receive a via i/o signal of the stacked chip die, and configured to, if the stacked chip die does not exist on the chip die, transmit/receive a differential i/o signal of the chip die; and an i/o driver configured to receive an operation mode signal including information as to whether the stacked chip die exists on the chip die in such a manner that the second i/o pad is configured to transmit/receive the via i/o signal or the differential i/o signal.. .
| Semiconductor memory device|
A sense amplifier circuit is divided into a plurality of sense amplifier groups. The plurality of sense amplifier groups are each further divided into a plurality of sense units.
| Semiconductor memory device, method of testing the same and method of operating the same|
A method of testing a semiconductor memory device is provided. Data is written to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device.
| Semiconductor memory device|
A semiconductor memory device includes a memory cell array including memory cells arranged therein. A first latch circuit temporarily holds data to perform a read operation and a write operation on the memory cell array.
| Memory system and memory access method|
Systems and methods of sequentially accessing memory cells in a nonvolatile memory device (nvm) are provided. The nvm has a plurality of strings and a common signal line coupled to the plurality of strings.
| Vertically-integrated nonvolatile memory devices having laterally-integrated ground select transistors|
Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., nand-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines..
| Semiconductor memory device|
A semiconductor memory device comprises a memory string including first and second selection transistors, and first and second groups of memory cell transistors connected in series between the first and second selection transistors; a bit line and a source line respectively connected to the first and second selection transistors; first word lines respectively connected to gates of the memory cell transistors in the first group; second word lines respectively connected to gates of the memory cell transistors in the second group; first transfer transistors respectively connected to the first word lines; second transfer transistors respectively connected to the second word lines; and a control unit configured to apply a first control voltage to gates of the first transfer transistors and a second control voltage lower than the first control voltage to gates of the second transfer transistors when data is being written to memory cell transistors in the first group.. .
| Fast access with low leakage and low power technique for read only memory devices|
A read only memory (rom) and method for providing a high operational speed with reduced leakage, no core cell standby leakage, and low power consumption. The source of the rom cell (nmos) is connected to a virtual ground line (vngd) instead of vss.
| Nonvolatile semiconductor memory device and method of controlling same|
According to an embodiment, a semiconductor memory device includes a memory cell array and a control circuit. The memory cell array comprises a plurality of memory cells that each include a control gate and a charge accumulation layer and that each are configured to have a threshold set to be included in any of a plurality of threshold distributions, the memory cell being connected between a bit line and a source line.
| Nonvolatile semiconductor memory device|
A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array having a plurality of memory cell transistors connected in series therein; a plurality of bit lines; and a control circuit for executing a read operation. The control circuit is configured capable of executing the read operation, the read operation charging the bit line and applying a read voltage to the control gate electrode of the memory cell transistor to determine whether the memory cell transistor is conductive and the bit line discharges or not.
| Reduced complexity reliability computations for flash memories|
Methods and apparatus are provided for computing reliability values, such as log likelihood ratios (llrs), with reduced complexity for flash memory devices. Data from a flash memory device that stores m bits per cell using 2̂m possible states is processed by obtaining at least two soft read voltage values corresponding to two reference voltages v0 and v1, wherein the two reference voltages v0 and v1 are between two adjacent states of the 2̂m possible states; and converting the at least two soft read voltage values to a log likelihood ratio for a region between the two reference voltages v0 and v1 using probability density functions only for the two adjacent states.
| Method and system for reducing the complexity of electronically programmable nonvolatile memory|
Embodiments relate to memory devices and methods for firmly programming at least a portion of a plurality of electronically programmable and erasable nonvolatile memory cells in a processing of the nonvolatile memory devices.. .
| Trench isolation implantation|
Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth of the dielectric material. Embodiments further include methods of fabricating the trench structures with the implant of energetic species to the predetermined depth.
| Carbon nanotube memory cell with enhanced current control|
A desired current through a carbon nano tube (cnt) element of a cnt memory device can be controlled by a wordline voltage, and a voltage on the cnt common node can be held constant. The common node can be constant at a source voltage if a p-channel metal-oxide-semiconductor field-effect transistor (mosfet) is used in the cnt memory device, or the common node can be constant at a supply voltage if an n-channel mosfet is used in the cnt memory device.
| Nonvolatile semiconductor memory device|
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell which stores data with two or more levels. The memory cell includes a structure includes a first electrode layer, a first semiconductor layer, a phase change film, an electrical insulating layer, a second semiconductor layer, and a second electrode layer arranged in order thereof, and the first semiconductor layer and the second semiconductor layer have carrier polarities different from each other..
| Semiconductor memory devices with a power supply|
A semiconductor device includes a virtual power supplier, a driving signal generator and a load driver. The virtual power supplier boosts a driving voltage to generate a virtual voltage.
| Semiconductor memory device|
A memory cell array includes first wiring lines, and second wiring lines, the first and second wiring lines intersecting, and memory cells disposed in the intersections of the first and second wiring lines, the memory cells including a variable resistance element. A control circuit controls voltages of selected first and second wiring lines.
| Semiconductor memory device|
A memory cell array comprises first wiring lines, second wiring lines, and memory cells disposed at intersections thereof. A control circuit comprises a first power-supply line supplying a first voltage to selected ones of the first or second wiring lines, and first selection circuits connected between the first or second wiring lines and the first power-supply line, each first selection circuit comprising first and second transistors connected in series.
| Multi channel semiconductor memory device and semiconductor device including the same|
Disclosed is a semiconductor memory device that includes a plurality of channel memories mounted within a package and is capable of minimizing or reducing the number of through-silicon vias. With the semiconductor memory device, a row command or a row address on two or more channels is applied through a shared bus.
| Memory dies, stacked memories, memory devices and methods|
Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack.
| Method for rotating an original image using self-learning and apparatuses performing the method|
A method of rotating an original image includes performing a self-learning using addresses related to at least one page miss and generating address generation rules using a result of the self-learning. The method includes pre-fetching the original image from a memory device based on the address generation rules to obtain a pre-fetched image and generating a rotated image using the pre-fetched image..
| Connections for memory electrode lines|
Subject matter disclosed herein may relate to word line electrodes and/or digit line electrodes in a cross-point array memory device. One or more word line electrodes may be configured to form a socket area to provide connection points to drivers and/or other circuitry that may be located within a footprint of an array of memory cells..
| Nonvolatile semiconductor memory device provided with charge storage layer in memory cell|
A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, and a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film formed above the charge storage layer, a silicon nitride film formed on the first silicon oxide film, a metal oxide film formed on the silicon nitride film, and a nitride film formed on the metal oxide film.
| Vertical memory devices and methods of manufacturing the same|
A memory device includes a plurality of channels, a plurality of first charge storage sites coupled to first sides of respective ones of the channels, and a plurality of second charge storage sites coupled to second sides of respective ones of the channels. The first charge storage sites correspond to first memory cells and the second charge storage sites coupled to second memory cells.
| Memory devices and methods of manufacturing the same|
A vertical memory device includes a channel array, a charge storage layer structure, multiple gate electrodes and a dummy pattern array. The channel array includes multiple channels, each of which is formed on a first region of a substrate and is formed to extend in a first direction substantially perpendicular to a top surface of the substrate.
| Embedded sonos based memory cells|
Memory cells including embedded sonos based non-volatile memory (nvm) and mos transistors and methods of forming the same are described. Generally, the method includes: forming a dielectric stack on a substrate, the dielectric stack including a tunneling dielectric on the substrate and a charge-trapping layer on the tunneling dielectric; patterning the dielectric stack to form a gate stack of a nvm transistor of a memory device in a first region of the substrate while concurrently removing the dielectric stack from a second region of the substrate; and performing a gate oxidation process of a baseline cmos process flow to thermally grow a gate oxide of a mos transistor overlying the substrate in the second region while concurrently growing a blocking oxide overlying the charge-trapping layer.
| Semiconductor memory device and method for manufacturing same|
According to one embodiment, a semiconductor memory device includes a semiconductor member, a first insulating layer provided on the semiconductor member, a tan layer provided on the first insulating layer and containing tantalum and nitrogen, a tasin layer provided on the tan layer in contact with the tan layer and containing tantalum, silicon, and nitrogen, a second insulating layer provided on the tasin layer in contact with the tasin layer and containing oxygen, and a control electrode provided on the second insulating layer.. .
| Memory device and method of forming the same|
Provided is a memory device including a first dielectric layer, a t-shaped gate, two charge storage layers and two second dielectric layers. The first dielectric layer is disposed on a substrate.
| Transistor, resistance variable memory device including the same, and manufacturing method thereof|
A resistance variable memory device including a vertical transistor includes an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (ldd) region and a drain formed in the other end of the channel region, a first gate electrode formed to surround a periphery of the ldd region and having a first work function, and a second gate electrode formed to be connected to the first gate electrode and to surround the channel region and having a second work function that is higher than the first to work function.. .
| Semiconductor memory device and method for manufacturing same|
According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction, a plurality of stacked films respectively provided between the first interconnects and the second interconnects, each of the plurality of stacked films including a variable resistance film, a first inter-layer insulating film provided in a first region between the stacked films, and a second inter-layer insulating film provided in a second region having a wider width than the first region. The second inter-layer insulating film includes a plurality of protrusions configured to support one portion of the plurality of second interconnects on the second region.
| Vertical mosfet transistor, in particular operating as a selector in nonvolatile memory devices|
A vertical mosfet transistor is formed in a body of semiconductor material having a surface. The transistor includes a buried conductive region of a first conductivity type; a channel region of a second conductivity type, arranged on top of the buried conductive region; a surface conductive region of the first conductivity type, arranged on top of the channel region and the buried conductive region; a gate insulation region, extending at the sides of and contiguous to the channel region; and a gate region extending at the sides of and contiguous to the gate insulation region..
|Capture of stylized tv table data via ocr|
In certain implementations consistent with the present invention, a method of detecting text in a television video display table involves saving a frame of video to a memory device; determining that the frame of video contains a table having cells containing text; storing a working copy of the frame of video to a memory; isolating text in the table by: removing any table boundaries from the image; removing any cell boundaries from the image; determining if the image has three dimensional or shadow attributes and removing any three dimensional or shadow attributes identified; thereby producing text isolated against a contrasting color background; and processing the isolated text using an optical character recognition (ocr) engine to extract the text as data. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract..
|Apparatus and method for handling a message|
A system for handling automated messages from a travel supplier includes a messaging client configured to receive an automated message generated by a remote travel supplier. The message comprises a link to a web address for completing a travel action associated with the link.
|Method and apparatus for reading data from non-volatile memory|
Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array.
|Nonvolatile memory device and method of operating the same|
A nonvolatile memory device includes a nonvolatile memory, a buffer memory configured to store a plurality of read data transmitted from the nonvolatile memory, an error detection and correction circuit configured to detect an error in partial data of each of the plurality of read data and judging whether the partial data is correctable or not on the basis of the detected error, and a controller configured to analyze the uncorrectable partial data with respect to the plurality of read data to determine a representative value, and to transmit the representative value to the error detection and correction circuit. The plurality of read data is read through a read operation with respect to a same page..
|Generic address scrambler for memory circuit test engine|
A generic address scrambler for a memory circuit test engine. An embodiment of a memory device includes a memory stack having one or more of coupled memory elements, a built-in self-test circuit including a generic programmable address scrambler for the mapping of logical addresses to physical addresses for the memory elements, and one or more registers to hold pro-gramming values for the generic programmable address scrambler..
|Nonvolatile semiconductor memory device and memory system using the same|
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and an encryption arithmetic module. The memory cell array includes a first storage area and a second storage area.
|Compression status bit cache and backing store|
One embodiment of the present invention sets forth a technique for increasing available storage space within compressed blocks of memory attached to data processing chips, without requiring a proportional increase in on-chip compression status bits. A compression status bit cache provides on-chip availability of compression status bits used to determine how many bits are needed to access a potentially compressed block of memory.
|Memory module and memory system having the same|
A memory module includes a master memory device and at least one slave memory device. The master memory device may generate a refresh clock signal, and perform a refresh operation in synchronization with the refresh clock signal.
|System and method for unlocking additional functions of a module|
A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system performs a maze unlock sequence by operating a memory device in a maze unlock mode.
|Memory controller, method of operating the same and memory system including the same|
A memory controller controlling a nonvolatile memory device having a plurality of memory blocks as a data storage space includes an error detection and correction circuit and a reclaim control unit. The error detection and correction circuit receives data from a memory block and calculates a comparison result by comparing a bit error rate of the received data and a predetermined value.
|Non-volatile memory channel control using a general purpose programmable processor in combination with a low level programmable sequencer|
A system includes a control processor, a non-volatile memory device interface, and a micro-sequencer. The control processor may be configured to receive commands and send responses via a command interface.
|Load reduction based on percentage change in energy price|
A thermostatic controller generally includes a transceiver configured to receive a signal that includes an energy price rate for a given time period, and an electronic memory device in which one or more energy price rates received by the transceiver are stored. A microprocessor is configured to select the lowest energy price rate received within a given time period for establishing a base energy price rate; determine if the energy price rate for a present time period exceeds the base energy price rate by more than a first percentage or multiplier factor of the base energy price rate; and respond to an energy price rate that exceeds the base energy price rate by more than the first percentage or multiplier factor by transmitting a signal via the transceiver to an energy consuming appliance indicating that the energy consuming appliance should be in an off state and/or to one or more ceiling fans to activate, deactivate and/or change speed of the one or more ceiling fans..
|Cement data telemetry via drill string|
A method can include acquiring data via a receiver mounted in a drill string during tripping of the drill string downward into a wellbore (e.g., including a casing and a cement annulus about the casing) where the acquired data can be for evaluation of at least one characteristic of cement; buffering at least a portion of the acquired data to a memory device mounted in the drill string; and while pumping drilling fluid through a passage in the drill string, as disposed in the wellbore, transmitting at least a portion of the buffered data via mud-pulse telemetry. Various other apparatuses, systems, methods, etc., are also disclosed..