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Memory Device

Memory Device-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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Universal subscriber identity recognition and data classification
At&t Mobility Ii Llc
June 15, 2017 - N°20170171217

An aspect includes storing data elements in a storage space of a memory device. The storage space is allocated for an account of a subscriber of a universal subscriber identification system. An aspect also includes assigning subscriber-inputted security levels to the data elements. The security levels define varying degrees of access protections associated with the data elements. An aspect further ...
Storage device and operating method of storage device
At&t Mobility Ii Llc
June 15, 2017 - N°20170170845

A storage device includes a nonvolatile memory device and a controller configured to read data from the nonvolatile memory device, to divide the read data into a plurality of segments, and to sequentially perform error correction decoding with respect to the plurality of segments. When the error correction decoding of each segment is completed, the controller adds error correction parity ...
Resistive switching memory device using brownmillerite-structured material
Hankuk University Of Foreign Studies Research Business Foundation
June 15, 2017 - N°20170170395

A resistive switching memory device using a brownmillerite-structured material, the resistive switching memory device comprises a first electrode comprising an oxide electrode; a resistive switching unit that is disposed on the first electrode and comprises a thin-film of a brownmillerite structured oxide; and a second electrode that is disposed on the resistive switching unit. Furthermore, the resistive switching unit has ...
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Memory Device Patent Applications
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Magnetic memory device and method of fabricating the same
Imec Vzw
June 15, 2017 - N°20170170387

A magnetic memory device and a method of fabricating the same are provided. The method includes forming a first magnetic layer on a substrate, forming a tunnel barrier layer on the first magnetic layer, and forming a second magnetic layer on the tunnel barrier layer. The forming of the tunnel barrier layer includes forming a first metal oxide layer on ...
Variable resistive memory device and method of manufacturing the same
Imec Vzw
June 15, 2017 - N°20170170237

A variable resistive memory device includes a first electrode layer, a variable resistive pattern structure located on the first electrode layer and including a variable resistive layer, a capping layer formed on opposite side walls of the variable resistive pattern structure and including regions having different impurity concentrations, and a second electrode layer formed on the capping layer.
Magnetoresistive random access memory device and method of manufacturing the same
Imec Vzw
June 15, 2017 - N°20170170234

A magnetoresistive random access memory (mram) device including a substrate including a plurality of active patterns arranged along a first direction, each of the active patterns extending in a diagonal direction with respect to the first direction; a plurality of gate structures on the substrate, the gate structures extending in a second direction substantially perpendicular to the first direction; a ...
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Memory Device Patent Applications
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  • 2989+ full patent PDF documents of Memory Device-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Memory devices and systems having reduced bit line to drain select gate shorting and associated ...
Intel Corporation
June 15, 2017 - N°20170170190

3d nand memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.
Gate fringing effect based channel formation for semiconductor device
Cypress Semiconductor Corporation
June 15, 2017 - N°20170170187

A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and ...
Rom segmented bitline circuit
Easic Corporation
June 15, 2017 - N°20170170186

A bitline structure for use in a memory device may be connected to a plurality of bit memory cells. The bitline may be segmented into segments connected to one-third of the plurality of bit memory cells and two-thirds of the bit memory cells, respectively. The segments may be electrically coupled to each other to provide an overall bitline output.
Memory devices with controllers under memory packages and associated systems and methods
Micron Technology, Inc.
June 15, 2017 - N°20170170149

Semiconductor devices with controllers under stacks of semiconductor packages and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate, a controller attached to the package substrate, and at least two semiconductor packages disposed over the controller. Each semiconductor package includes a plurality of semiconductor dies. The semiconductor device further includes an encapsulant ...
Semiconductor memory device and method for manufacturing the same
Kabushiki Kaisha Toshiba
June 15, 2017 - N°20170170125

A semiconductor memory device according to one embodiment includes a plurality of lower electrode films stacked separated from each other, an upper electrode film provided above the plurality of lower electrode films, a semiconductor pillar extending in an arrangement direction of the plurality of lower electrode films and the upper electrode film, a memory film provided between the semiconductor pillar ...
Boundary scan chain for stacked memory
Intel Corporation
June 15, 2017 - N°20170169900

A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (i/o) cells and a boundary scan chain for the i/o cells. A boundary scan chain of a memory die layer includes a scan chain ...
Piezoelectric and logic integrated delay line memory
Cornell University
June 15, 2017 - N°20170169899

Delay line memory device, systems and methods are disclosed. In one aspect, a delay line memory device includes a substrate; an electronic unit disposed on the substrate and operable to receive, amplify, and/or synchronize data signals into a bit stream to be transmitted as acoustic pulses carrying data stored in the delay line memory device; a first and a ...
Memory Device Patent Pack
Download 2989+ patent application PDFs
Memory Device Patent Applications
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For professional research & prior art discovery
inventor
  • 2989+ full patent PDF documents of Memory Device-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Reducing verification checks when programming a memory device
Intel Corporation
June 15, 2017 - N°20170169896

Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to initiate a program verify sequence to verify data written to a non-volatile memory (nvm). The program verify sequence can have one or more program verify levels that each correspond to memory cells in the nvm for which written data is being verified. The ...
Semiconductor memory device that determines a deterioration level of memory cells and an operation method ...
Kabushiki Kaisha Toshiba
June 15, 2017 - N°20170169895

A semiconductor memory device includes a memory cell unit including a plurality of blocks, each of the blocks including a plurality of pages, and a circuit configured to count a number of activated or non-activated memory cells in one or more pages when a first voltage is applied to gates of memory cells of said one or more pages to ...
Dynamically adjusting read voltage in a nand flash memory
International Business Machines Corporation
June 15, 2017 - N°20170169894

A nand flash memory device detects the occurrence of cell voltage distribution disruption events (cvddes), such as a partial block program (pbp) and program-read-immediate (pm), and provides a way to dynamically adjust read voltage to account for cvddes. A read command includes extended addressing bits that are used when a cvdde has occurred to access registers that indicate an adjustment ...
Dynamically adjusting read voltage in a nand flash memory
International Business Machines Corporation
June 15, 2017 - N°20170169893

A nand flash memory device detects the occurrence of cell voltage distribution disruption events (cvddes), such as a partial block program (pbp) and program-read-immediate (pri), and provides a way to dynamically adjust read voltage to account for cvddes. A read command includes extended addressing bits that are used when a cvdde has occurred to access registers that indicate an adjustment ...
Nonvolatile memory device and method of operating the nonvolatile memory device
International Business Machines Corporation
June 15, 2017 - N°20170169892

A nonvolatile memory device includes a memory cell array, a row decoder, and page buffer, and control logic. The memory cell array includes cell strings connected to select lines. Each select line is connected to two or more cell strings, each cell string includes memory cells connected to a plurality of word lines, and a select transistor is connected to ...
Dynamically adjusting read voltage in a nand flash memory
International Business Machines Corporation
June 15, 2017 - N°20170169891

A nand flash memory device detects the occurrence of cell voltage distribution disruption events (cvddes), such as a partial block program (pbp) and program-read-immediate (pri), and provides a way to dynamically adjust read voltage to account for cvddes. A read command includes extended addressing bits that are used when a cvdde has occurred to access registers that indicate an adjustment ...
Dynamically adjusting read voltage in a nand flash memory
International Business Machines Corporation
June 15, 2017 - N°20170169890

A nand flash memory device detects the occurrence of cell voltage distribution disruption events (cvddes), such as a partial block program (pbp) and program-read-immediate (pm), and provides a way to dynamically adjust read voltage to account for cvddes. A read command includes extended addressing bits that are used when a cvdde has occurred to access registers that indicate an adjustment ...
Semiconductor memory device
Kabushiki Kaisha Toshiba
June 15, 2017 - N°20170169889

A semiconductor memory device has a memory block including memory strings with first and second selection transistors at opposite ends of the memory strings. A bit line is connected to the first selection transistor of each memory string and a sense amplifier is connected to the bit line. The memory block includes word lines connected to each memory cell transistor ...
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