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Memory Device patents

      

This page is updated frequently with new Memory Device-related patent applications.




 Wireless server access control system and method patent thumbnailWireless server access control system and method
A wireless server access control system comprising a wireless server generating a local wireless communications network, the wireless server having a processor and a plurality of redundant data memory devices. A first wireless device coupled to the wireless server through the local wireless communications network.
Myth Innovations, Inc.


 Image formation system,  controlling the same, image formation apparatus, and program patent thumbnailImage formation system, controlling the same, image formation apparatus, and program
An image formation system includes an image formation apparatus that outputs a test chart; and external equipment that generates data for correction of performance of the image formation apparatus based on the test chart output by the image formation apparatus. The image formation apparatus also outputs save location information associated with the test chart.
Konica Minolta, Inc.


 Semiconductor memory device and  manufacturing same patent thumbnailSemiconductor memory device and manufacturing same
According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction, a plurality of stacked films respectively provided between the first interconnects and the second interconnects, each of the plurality of stacked films including a variable resistance film, a first inter-layer insulating film provided in a first region between the stacked films, and a second inter-layer insulating film provided in a second region having a wider width than the first region. The second inter-layer insulating film includes a plurality of protrusions configured to support one portion of the plurality of second interconnects on the second region.
Kabushiki Kaisha Toshiba


 Method and processing  fabricating a magnetic resistive random access memory device patent thumbnailMethod and processing fabricating a magnetic resistive random access memory device
Methods of fabricating mram devices are provided along with a processing apparatus for fabricating the mram devices. The methods may include forming a ferromagnetic layer, cooling the ferromagnetic layer to a temperature within a range of between about 50° k to about 300° k, forming and oxidizing one or more mg layers on the cooled ferromagnetic layer to form an mgo structure, forming a free layer on the mgo structure, and forming a capping layer on the free layer..

 Methods of forming an interconnection line and methods of fabricating a magnetic memory device using the same patent thumbnailMethods of forming an interconnection line and methods of fabricating a magnetic memory device using the same
Provided herein are methods of fabricating a magnetic memory device including forming magnetic tunnel junction patterns on a substrate, forming an interlayered insulating layer on the substrate to cover the magnetic tunnel junction patterns, forming a conductive layer on the interlayered insulating layer, patterning the conductive layer to form interconnection patterns electrically connected to the magnetic tunnel junction patterns, and performing a cleaning process on the interconnection patterns. The cleaning process is performed using a gas mixture of a first gas and a second gas.
Samsung Electronics Co., Ltd.


 Spin torque mram based on co, ir synthetic antiferromagnetic multilayer patent thumbnailSpin torque mram based on co, ir synthetic antiferromagnetic multilayer
Magnetic memory devices having an antiferromagnetic reference layer based on co and ir are provided. In one aspect, a magnetic memory device includes a reference magnetic layer having multiple co-containing layers oriented in a stack, wherein adjacent co-containing layers in the stack are separated by an ir-containing layer such that the adjacent co-containing layers in the stack are anti-parallel coupled by the ir-containing layer therebetween; and a free magnetic layer separated from the reference magnetic layer by a barrier layer.
International Business Machines Corporation


 Magnetic memory devices patent thumbnailMagnetic memory devices
A magnetic memory device includes a substrate, a landing pad on the substrate, first and second magnetic tunnel junction patterns disposed on the interlayer insulating layer and spaced apart from the landing pad when viewed from a plan view, and an interconnection structure electrically connecting a top surface of the second magnetic tunnel junction pattern to the landing pad. A distance between the landing pad and the first magnetic tunnel junction pattern is greater than a distance between the first and second magnetic tunnel junction patterns, and a distance between the landing pad and the second magnetic tunnel junction pattern is greater than the distance between the first and second magnetic tunnel junction patterns, when viewed from a plan view..

 Semiconductor memory device patent thumbnailSemiconductor memory device
A semiconductor memory device includes free magnetic pattern on a substrate, a reference magnetic pattern on the free magnetic pattern, the reference magnetic pattern including a first pinned pattern, a second pinned pattern, and an exchange coupling pattern between the first and second pinned patterns, a tunnel barrier pattern between the reference magnetic pattern and the free magnetic pattern, a polarization enhancement magnetic pattern between the tunnel barrier pattern and the first pinned pattern, and an intervening pattern between the polarization enhancement magnetic pattern and the first pinned pattern, wherein the first pinned pattern includes first ferromagnetic patterns and anti-ferromagnetic exchange coupling patterns which are alternately stacked.. .

 Semiconductor memory device patent thumbnailSemiconductor memory device
A semiconductor memory device includes a selection transistor on a semiconductor substrate, a lower contact plug connected to a drain region of the selection transistor, and a magnetic tunnel junction pattern on the lower contact plug, the magnetic tunnel junction pattern including a bottom electrode in contact with the lower contact plug, the bottom electrode being an amorphous tantalum nitride layer, a top electrode on the bottom electrode, first and second magnetic layers between the top and bottom electrodes, and a tunnel barrier layer between the first and second magnetic layers.. .

 Mtj structures and magnetoresistive random access memory devices including the same patent thumbnailMtj structures and magnetoresistive random access memory devices including the same
A magnetic tunnel junction (mtj) structure includes a fixed layer pattern structure having a perpendicular magnetization direction, a tunnel barrier pattern on the fixed layer pattern structure, a free layer pattern on the tunnel barrier pattern, the free layer pattern having a perpendicular magnetization direction, a first surface magnetism induction pattern on the free layer pattern, the first surface magnetism induction pattern inducing a perpendicular magnetism in a surface of the free layer pattern, a conductive pattern on the first surface magnetism induction pattern, and a ferromagnetic pattern on the conductive pattern.. .

Magnetoresistive random access memory device and manufacturing the same

A magnetoresistive random access memory device includes a free layer, a tunnel barrier layer, an insulation barrier layer, a pinned layer, and a vertical polarizer structure. The tunnel barrier layer and the insulation barrier layer directly contacts different surfaces of the free layer.

In-situ annealing and etch back steps to improve exchange stiffness in cobalt iron boride based perpendicular magnetic anisotropy free layers

A method for forming a memory device that includes providing a free layer of an alloy of cobalt (co), iron (fe) and boron (b) overlying a reference layer; and forming metal layer comprising a boron (b) sink composition atop the free layer. Boron (b) may be diffused from the free layer to the metal layer comprising the boron sink composition.
International Business Machines Corporation

High aspect ratio 3-d flash memory device

Methods of selectively etching tungsten from the surface of a patterned substrate are described. The etch electrically separates vertically arranged tungsten slabs from one another as needed, for example, in the manufacture of vertical flash memory devices.
Applied Materials, Inc.

Methods for manufacturing ultrathin semiconductor channel three-dimensional memory devices

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack to the substrate.
Sandisk Technologies Inc.

Single-poly nonvolatile memory device

A single-poly nvm cell includes a select transistor and a floating gate transistor serially connected to the select transistor. The select transistor includes a select gate, a select gate oxide layer, a source doping region, a first ldd region merged with the source doping region, a commonly-shared doping region, and a second ldd region merged with the commonly-shared doping region.
Ememory Technology Inc.

Ultrathin semiconductor channel three-dimensional memory devices

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack to the substrate.
Sandisk Technologies Inc.

Semiconductor memory device and manufacturing the same

In general, according to one embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first sub-conductive layer, a first insulating film. One portion of the first conductive layer overlaps at least one portion of the first sub-conductive layer in the first direction.
Kabushiki Kaisha Toshiba

Memory device and fabrication the same

A device is disclosed that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is disposed in a first metal layer and is electrically coupled to the memory bit cell.
Taiwan Semiconductor Manufacturing Co., Ltd.

Nonvolatile memory device and fabricating the same

A nonvolatile memory device may include a stair-shaped structure including a first interlayer dielectric layer and a memory cell repeatedly stacked. The nonvolatile memory device may include an etch stop layer and a second interlayer dielectric layer formed over the stair-shaped structure.
Sk Hynix Inc.

Sputtering apparatuses and methods of manufacturing a magnetic memory device using the same

A sputtering apparatus includes a process chamber in which a sputtering process is performed, a substrate holder provided in the process chamber and fixing a horizontal position of a substrate during the sputtering process, and a first sputter gun provided to be vertically spaced apart from the substrate in the process chamber. The first sputter gun is spaced apart from the substrate by a first horizontal distance during the sputtering process.

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application, and accessing data storage memory through the first and second memory devices.. .
Sk Hynix Inc.

Semiconductor memory devices and methods of operating the same

A method of operating a semiconductor memory device is provided. In a method of operating a semiconductor memory device including a memory cell array which includes a plurality of bank arrays, memory cells in a first region of the memory cell array are tested to detect one or more failed cells in the first region, a fail address corresponding to the detected one or more failed cells is determined and the determined fail address is stored in a second region different from the first region, in the memory cell array..
Samsung Electronics Co., Ltd.

Semiconductor memory device, testing the same and operating the same

A method of testing a semiconductor memory device is provided. Data is written to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device.
Samsung Electronics Co., Ltd.

Memory device and operating method thereof

A memory device includes a plurality of memory cells for storing data; a plurality of memory cells for storing data; a non-volatile memory unit; a test control unit suitable for detecting weak memory cells among the plurality of memory cells; a program control unit suitable for controlling addresses of the detected weak memory cells to be programmed in the non-volatile memory unit; and a refresh control unit suitable for refreshing the addresses stored in the non-volatile memory unit more frequently than other memory cells.. .
Sk Hynix Inc.

Error characterization and mitigation for 16nm mlc nand flash memory under total ionizing dose effect

A data device includes a memory having a plurality of memory cells configured to store data values in accordance with a predetermined rank modulation scheme that is optional and a memory controller that receives a current error count from an error decoder of the data device for one or more data operations of the flash memory device and selects an operating mode for data scrubbing in accordance with the received error count and a program cycles count.. .
California Institute Of Technology

Power driven optimization for flash memory

A memory device, and method of operation, includes an array of non-volatile memory cells and a controller. The controller is configured to perform an operation (e.g.
Silicon Storage Technology, Inc.

Nonvolatile semiconductor memory device

A semiconductor memory device includes a memory cell array, a sense amplifier, a register, a controller. The memory cell array includes a memory cell.
Kabushiki Kaisha Toshiba

Method for fabricating semiconductor memory device having integrated dosram and nosram

A method for fabricating a semiconductor memory device is disclosed. A semiconductor substrate having a main surface is prepared.
United Microelectronics Corp.

Method, system and device for non-volatile memory device operation

Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a non-volatile memory device may be placed in any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device.
Arm Ltd.

Fast read speed memory device

A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations.. .
Rambus Inc.

Semiconductor memory device configured to sense memory cell threshold voltages in ascending order

According to one embodiment, a semiconductor memory device includes first and second memory cells, a word line, first and second bit lines, a sense amplifier and a driver. The first and second memory cells have first and second threshold voltages, respectively.
Kabushiki Kaisha Toshiba

Programming non volatile memory device

Provided is a programming method of a nonvolatile memory device including a plurality of memory cells. The programming method of the nonvolatile memory device includes: programming a first set of memory cells of the plurality of memory cells to a target state based on a primary program voltage such that a threshold voltage distribution of the first set of memory cells is formed; grouping the first set of memory cells into a plurality of cell groups at least one cell group having a different threshold voltage distribution width from others, based on program speeds of the first set of memory cells; and reprogramming remaining cell groups other than a first cell group that is programmed to the target state among the plurality of cell groups, to the target state based on a plurality of secondary program voltages determined based on threshold voltage distribution widths of the plurality of cell groups..

Hybrid refresh with hidden refreshes and external refreshes

A memory subsystem enables satisfying refresh needs for a memory device with hidden refreshes performed by the memory device in response to activate commands, and external refreshes to make up a difference between the number of hidden refreshes and a minimum number of total refreshes needed during a refresh window. With a hidden refresh the memory device executes the activate command in one memory portion as indicated by the identified memory location of the command, and executes a refresh in a different portion, such as a different sub-bank.
Intel Corporation

Memory device for refresh and memory system including the same

A memory device includes a memory bank including a plurality of memory blocks, a row selection circuit and a refresh controller. The row selection circuit is configured to perform an access operation and a refresh operation with respect to the memory bank.
Samsung Electronics Co., Ltd.

Memory device and system including the same

A memory device may include: an active controller configured to output a row active signal in response to a refresh control signal and a row enable signal when an active signal is activated; a refresh controller configured to generate and store a flag bit for controlling a refresh operation in response to a refresh signal, a precharge signal, and a precharge stop signal, and output the row enable signal corresponding to the stored flag bit to the active controller; and a cell array circuit configured to perform a refresh operation in memory cell array areas in response to the row active signal.. .
Sk Hynix Inc.

Memory device and system supporting command bus training, and operating method thereof

A memory device and system supporting command bus training are provided. An operating method of the memory device includes entering into a command bus training mode, receiving a clock signal, a chip selection signal and a first command/address signal, generating an internal clock signal by dividing the clock signal, generating a second command/address signal by latching the first command/address signal at a rising edge or a falling edge of the internal clock signal when a chip selection signal is activated, and outputting the second command/address signal..
Samsung Electronics Co., Ltd.

Memory device, related method, and related electronic device

A memory device may include the following elements: a first memory cell; a first word line for transmitting a first control signal to control an electrical connection in the first memory cell; a first bit line connected to the first memory cell; a first transistor, wherein a first terminal of the first transistor is connected to the first bit line; a second memory cell; a second word line for transmitting a second control signal to control an electrical connection in the second memory cell; a second bit line connected to the second memory cell; a second transistor, wherein a first terminal of the second transistor is connected to the second bit line; and a sense amplifier having a first input terminal connected to a second terminal of the first transistor and having a second input terminal connected to a second terminal of the second transistor.. .
Semiconductor Manufacturing International (shanghai) Corporation

Memory device and system supporting command bus training, and operating method thereof

An operating method of a memory device includes entering into a command bus training mode, generating a plurality of internal clock signals by dividing a received clock signal, generating a plurality of internal chip selection signals by latching a received chip selection signal according to the plurality of internal clock signals, generating a second command/address signal by encoding a received first command/address signal based on the plurality of internal chip selection signals, and outputting the second command/address signal.. .
Samsung Electronics Co., Ltd.

Systems and methods for object detection

A computing device for detecting an object of interest in an image is provided. The computing device includes a memory device and a processor to process image data by evaluating pixel contrast to facilitate detecting an edge transition in an image, by identifying neighboring pixels that are above a predetermined contrast value, which represent a potential object of interest, filtering the pixels based on color information to identify areas where there is a color edge transition, applying a convolution filter mask to yield regions of pixels having a localized concentration of contrast and color changes, applying a threshold filter for identifying those pixel regions having values that are greater than a predetermined threshold value and grouping the identified pixel regions into one or more groups representing an object of interest, and generating an alert to notify an operator that the object of interest in the image has been detected..
The Boeing Company

Method and system for managing payment transactions

A method for managing payment transactions between a merchant and a payment-service-provider (psp) using a payment management device in communication with a memory device. Each payment transaction is initiated by a consumer using a payment card.
Mastercard Asia/pacific Pte Ltd

Mechanical locking device for computer ports and portable storage devices

The present invention is directed to a mechanical locking device for securing computer input/output (i/o) ports that are in use and for securing unused computer i/o ports of an electronic device. The invention is also directed to a mechanical locking device which can be used to secure a portable locking flash memory device in a computer i/o port.
Foxrun Development Co., Llc

Nonvolatile memory devices and solid state drives including the same

A nonvolatile memory device includes a memory cell array, a voltage generator, and a control circuit. The voltage generator generates word-line voltages to be applied to the memory cell array.
Samsung Electronics Co., Ltd.

Memory device

A memory device includes: a plurality of bank groups each comprising one or more banks; a first bus coupled to the plurality of bank groups; a second bus coupled to the plurality of bank groups; a toggle signal generation unit suitable for generating a first signal which toggles in response to a column command signal and a second signal having the opposite logic value of the first signal; a column command transmission unit suitable for transmitting a read command signal or write command signal to the first bus when the first signal is activated, and transmitting the read command signal or write command signal to the second bus when the second signal is activated; and a column address transmission unit suitable for transmitting one or more column address signals corresponding to the read command signal or write command signal to a bus to which the read command signal or write command signal is transmitted, between the first and second buses.. .
Sk Hynix Inc.

I/o bus shared memory system

A memory system has a plurality of memory devices coupled with a hub in discrete and shared port arrangements. A plurality of bus lines connect the plurality of memory devices to the hub, including a first subset of bus lines connected in a point-to-point configuration between the hub and a particular memory device, and a second subset of bus lines connected to all the memory devices in the plurality of memory devices including the particular memory device.
Macronix International Co., Ltd.

Memory system and operating the memory system

In a memory system including a memory device including a plurality of storage regions, and a controller suitable for selecting storage regions indicated by logical addresses from among the plurality of storage regions using a mapping table storing a plurality of pieces of mapping information for mapping a plurality of logical addresses to a plurality of physical addresses corresponding to the plurality of storage regions. The controller may narrow a search range in which a second requested logical address of n logical addresses (n is an integer greater than 2) is to be searched for in the mapping table based on a position in which the mapping information corresponding to a first requested logical address of the n logical addresses has been stored in the mapping table when the n logical addresses are sequentially searched for in the mapping table..
Sk Hynix Inc.

Memory system and operation method thereof

A memory system includes a memory device comprising a plurality of blocks, and a controller suitable for erasing at least one victim block selected from among the plurality of blocks in a first garbage collection operation, and preparing a second garbage collection operation for one or more other blocks, except for the victim block among the plurality of blocks during a period in which the victim block is erased.. .
Sk Hynix Inc.

Memory system

A memory system includes: a first memory device including a plurality of first memories and a first memory controller suitable for controlling the plurality of first memories to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. .
Sk Hynix Inc.

Memory system and operation method thereof

A memory system may include a nonvolatile memory device including a plurality of blocks each including a plurality of pages, and a controller that selects a mapping block from the plurality of blocks, stores address information corresponding to each of other blocks, except for the mapping block and a free block among the plurality of blocks, in each of the plurality of pages, searches for a block including no valid page among the other blocks, and invalidates a page of the mapping block storing the address information corresponding to the searched block.. .
Sk Hynix Inc.

Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination

An arbitration system and method is disclosed. The apparatus includes first and second memory devices, and a resistor coupled in common to the first and second memory devices, the first memory device including a first calibration circuit configured to perform, when activated, a first calibration operation based on the resistor and a first arbiter configured to activate the first calibration circuit responsive, at least in part, to an assertion of a first command or keep the first calibration circuit inactive irrespective of the assertion of the first command..
Micron Technology, Inc.

Methods operating semiconductor memory devices with selective write-back of data for error scrubbing and related devices

A method of scrubbing errors from a semiconductor memory device including a memory cell array and an error correction circuit, can be provided by accessing a page of the memory cell array to provide a data that includes sub units that are separately writable to the page of memory and to provide parity data configured to detect and correct a bit error in the data and selectively enabling write-back of a selected sub unit of the data responsive to determining that the selected sub unit of data includes a correctable error upon access as part of an error scrubbing operation.. .
Samsung Electronics Co., Ltd.

Semiconductor memory devices and memory systems including the same

A semiconductor memory device includes a memory cell array, an error correction circuit and a control logic circuit. The error correction circuit performs an error correction code (ecc) encoding on write data to be stored in the memory cell array, and performs an ecc decoding on read data from the memory cell array.
Samsung Electronics Co., Ltd.

Apparatus and generating common locator bits to locate a device or column error during error correction operations

Provided are an apparatus and method for generating common locator bits to locate a device or column error during error correction operation for a memory subsystem having memory modules, each including a plurality of memory devices. Error detection logic generates common locator bits from device bits in a plurality of memory devices in one of the memory modules.
Intel Corporation

Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination

An arbitration system and method is disclosed. The apparatus includes a fiat and a second memory devices, and a resistor coupled in common to the first and second memory devices, the first memory device includes a first calibration circuit configured to perform a first calibration operation responsive, at least in part, to an external calibration command, the first calibration operation being performed based on the resistor, and the second memory device includes a second calibration circuit configured to perform a second calibration operation responsive, at least in part, to the external calibration command, the second calibration operation being performed based on the resistor after the first calibration operation has finished..
Micron Technology, Inc.

System and page-by-page memory channel interleaving

Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method comprises configuring a memory address map for two or more memory devices accessed via two or more respective memory channels.
Qualcomm Incorporated

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. .
Sk Hynix Inc.

Memory device that writes data into a block based on time passage since erasure of data from the block

A memory device includes a non-volatile semiconductor memory including a plurality of first areas, each corresponding to an erasing unit, each of the first areas including a plurality of second areas, each corresponding to a writing unit and a controller configured to erase data stored in a first area of the non-volatile semiconductor memory, track amount of time elapsed since the erasure of data from the first area, and write data into one or more unwritten second areas of the first area in accordance with the elapsed time, independent of a command to write data into the unwritten second areas.. .
Kabushiki Kaisha Toshiba

Logical address history management in memory device

Some embodiments include apparatuses and methods including memory cells and a control unit to store information in a portion of the memory cells and to generate an entry associated with the information. The information is associated with a logical address recognized by a host.
Micron Technology, Inc.

Partitioned memory having pipeline writes

A memory device includes a non-volatile memory (nvm) array and a memory controller. The nvm array has four partitions in which each partition has as plurality of groups of nvm cells.
Freescale Semiconductor, Inc.

Memory system

A memory system includes: a memory module including: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data and a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. .
Sk Hynix Inc.

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access data storage memory through the first and second memory devices.. .
Sk Hynix Inc.

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. .
Sk Hynix Inc.

Memory system

A memory system includes: a system main memory including a first memory device and a second memory device, wherein each of the first and second memory devices maintains latency information thereof; a processor suitable for executing an operating system (os) and an application to access a data storage memory through the system main memory, wherein the system main memory is separated from the processor and the processor and the first and second memory devices are electrically coupled to one another through a common bus; and a memory controller suitable for transferring data between the system main memory and the processor.. .
Sk Hynix Inc.

Memory system

A memory system includes: a plurality of first memory devices directly or indirectly coupled to one another, each first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a multi-processor including a plurality of processors, each processor executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. .
Sk Hynix Inc.

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. .
Sk Hynix Inc.

Memory system

A memory system includes: a plurality of first memory devices directly or indirectly coupled to one another, each first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device commonly coupled to the plurality of the plurality of first memory devices, and including a second memory and a second memory controller suitable for controlling the second memory to store data; and a multi-processor including a plurality of processors, each processor executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. .
Sk Hynix Inc.

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. .
Sk Hynix Inc.

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. .
Sk Hynix Inc.

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. .
Sk Hynix Inc.

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. .
Sk Hynix Inc.

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. .
Sk Hynix Inc.

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. .
Sk Hynix Inc.

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application, and accessing data storage memory through the first and second memory devices.. .
Sk Hynix Inc.

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application, and accessing data storage memory through the first and second memory devices.. .
Sk Hynix Inc.

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. .
Sk Hynix Inc.

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access a data storage memory through the first and second memory devices.. .
Sk Hynix Inc.

Method and system for accessing a flash memory device

An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed.
Conversant Intellectual Property Management Inc.

Data storage device and operating method thereof

A data storage device includes a controller; and a nonvolatile memory device including a plurality of memory blocks, and suitable for erasing a memory block selected from among the plurality of memory blocks, wherein the controller is suitable for managing the memory block through an erase prohibition list so that at least one predetermined erase cycle is ensured for the memory block.. .
Sk Hynix Inc.

Memory system

A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (os) and an application to access data from a data storage memory through the first and second memory devices.. .
Sk Hynix Inc.





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