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Memory Device patents



      
           
This page is updated frequently with new Memory Device-related patent applications. Subscribe to the Memory Device RSS feed to automatically get the update: related Memory RSS feeds. RSS updates for this page: Memory Device RSS RSS


Nonvolatile semiconductor memory device

Updating a set of memory devices in a dispersed storage network

Apparatus and method for controlling access to a memory device

Date/App# patent app List of recent Memory Device-related patents
08/14/14
20140230079
 Response to tamper detection in a memory device patent thumbnailnew patent Response to tamper detection in a memory device
In response to a tamper-attempt indication, a memory device selectively disables one or more memory operations. Disabling can be accomplished by different techniques, including altering bias voltages associated with performing the memory operation, gating off a current needed for performing the memory operation, and limiting the needed current to a magnitude below the threshold magnitude required for the operation.
08/14/14
20140229798
 Efficient data storage in multi-plane memory devices patent thumbnailnew patent Efficient data storage in multi-plane memory devices
A method for data storage includes initially storing a sequence of data pages in a memory that includes multiple memory arrays, such that successive data pages in the sequence are stored in alternation in a first number of the memory arrays. The initially-stored data pages are rearranged in the memory so as to store the successive data pages in the sequence in a second number of the memory arrays, which is less than the first number.
08/14/14
20140229797
 Error correcting code scheme utilizing reserved space patent thumbnailnew patent Error correcting code scheme utilizing reserved space
Methods, techniques, systems and apparatuses for utilizing reserved space for error correcting functionality. A cache line (“reserved line”) in a plurality of cache lines to store error correcting code (ecc) data is utilized for storing ecc data corresponding to other cache lines within the plurality of cache lines when a memory device has failed..
08/14/14
20140229795
 Configurable coding system and method of multiple eccs patent thumbnailnew patent Configurable coding system and method of multiple eccs
A configurable coding system and method of multiple error correcting codes (eccs) for a memory device or devices are disclosed. The system includes a first ecc codec that selectively performs different error corrections with different parameters; means for providing a selected parameter to the ecc codec for initializing the ecc codec; and a second ecc codec that corrects the selected error-prone parameter in order to provide an error-free parameter to the first ecc codec..
08/14/14
20140229793
 Apparatus and method for controlling access to a memory device patent thumbnailnew patent Apparatus and method for controlling access to a memory device
An apparatus includes encoding circuitry to generate code words for storage in a memory device. Decoding circuitry is responsive to a read transaction to decode one or more code words read from the memory device in order to generate read data for outputting in response to the read transaction.
08/14/14
20140229777
 Autorecovery after manufacturing/system integration patent thumbnailnew patent Autorecovery after manufacturing/system integration
Testing methods in a pre-programmed memory device after it has been assembled into a final customer platform include issuing a self-test command to the memory device, the memory device reporting results of a self-test of pre-programmed data executed responsive to receiving the self-test command, and issuing a self-repair command responsive to the results indicating repair of the pre-programmed data is needed.. .
08/14/14
20140229775
 Updating a set of memory devices in a dispersed storage network patent thumbnailnew patent Updating a set of memory devices in a dispersed storage network
A method begins by tracking age related failure levels of memory devices within the storage unit. The method continues by maintaining a data location table that maps a range of dsn addresses allocated to the storage unit to the memory devices and further records storing of encoded data slices having specific dsn addresses within the memory devices.
08/14/14
20140229766
 Apparatus and method for performing data scrubbing on a memory device patent thumbnailnew patent Apparatus and method for performing data scrubbing on a memory device
An apparatus and method are provided for opportunistically performing scrubbing operations on a memory device. The apparatus is used for accessing the memory device in response to access requests issued by at least one requesting device and comprises interface circuitry that is configured to access the memory device in response to the access requests.
08/14/14
20140229762
 Failure recovery memory devices and methods patent thumbnailnew patent Failure recovery memory devices and methods
Memory devices and methods are described that include serially chained memory devices. In one or more of the configurations shown, a serial chain of memory devices includes a number of memory devices, and an error recovery device at an end of the chain.
08/14/14
20140229745
 System and method for updating read-only memory in smart card memory modules patent thumbnailnew patent System and method for updating read-only memory in smart card memory modules
A storage device contains a smart-card device and a memory device, both connected to a controller. The storage device may be used in the same manner as a conventional smart-card device, or it may he used to store a relatively large amount of data in various partitions.
08/14/14
20140229666
new patent Memory subsystem i/o performance based on in-system empirical testing
A memory subsystem empirically tests performance parameters of i/o with a memory device. Based on the empirical testing, the memory subsystem can set the performance parameters specific to the system in which the memory subsystem is included.
08/14/14
20140229664
new patent Preloading data into a flash storage device
Programmer's data that is transferred from a programming device to a storage device is initially stored in a memory device of the storage device by using a durable data-retention storage setup. After the storage device is embedded in a host device, the programmer's data is internally (i.e., in the storage device) read from the memory device and rewritten into the memory device by using a conventional storage setup.
08/14/14
20140229661
new patent Operating system based dram and flash management
A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more flash memory devices that are employed for random access memory applications.
08/14/14
20140229042
new patent Brake control device for a brake system of a rail vehicle, brake system, rail vehicle and method for operating a brake control device
A brake control device for a brake system of a rail vehicle, wherein the brake control device detects strain during a braking process on at least one friction brake device actuated during the braking process, the brake control device further stores wear data based on the detected strain in a memory device. Also disclosed is a brake system for a rail vehicle having such a brake control device, a rail vehicle having such a brake system and/or such a brake control device, and a method for operating a brake control device for a brake system of a rail vehicle..
08/14/14
20140228692
new patent Respiratory rate measurement using a combination of respiration signals
A method and system for measuring respiratory rate are disclosed. In a first aspect, the method comprises measuring at least one respiration signal and filtering the respiration signal using a lowpass filter.
08/14/14
20140228096
new patent Gaming system with remote controller having location-based variable functionality
A gaming system includes a handheld device coupled to a fixed structure. The handheld device includes a sensor configured to detect inputs.
08/14/14
20140228086
new patent Systems, methods, and devices for playing wagering games with skill-based and non-skill-based game features
Gaming devices, gaming systems, methods of conducting wagering games, and computer programs for executing wagering games are disclosed. A gaming system for playing a wagering game is disclosed which includes one or more processors and one or more memory devices storing instructions that, when executed by at least one of the processors, cause the gaming system to: receive a wager to play the wagering game; direct a display device to display a randomly determined outcome of a base game of the wagering game; in response to a triggering event, initiate play of a non-skill-based game feature and, further in response to receiving a player selection of a skill-based game feature, initiate play of the skill-based game feature; determine an award value for the skill-based game feature; determine an award value for the non-skill-based game feature; and, award to the player only the higher of the two award values..
08/14/14
20140227888
new patent Remote plasma radical treatment of silicon oxide
Embodiments described herein generally relate to methods for manufacturing flash memory devices. In one embodiment, the method includes generating a plasma comprising nitrogen-containing radicals in a remote plasma applicator, flowing the plasma comprising nitrogen-containing radicals into a processing region of the processing chamber where a semiconductor device is disposed, wherein the semiconductor device has a substrate comprising an oxide layer formed thereon, exposing an exposed surface of the oxide layer to the nitrogen-containing radicals, and incorporating nitrogen in the exposed surface of the oxide layer of the substrate..
08/14/14
20140227842
new patent 3d structured memory devices and methods for manufacturing thereof
A 3d structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region.
08/14/14
20140227841
new patent Three-dimensional semiconductor memory devices and methods of fabricating the same
Example embodiments relate to a three-dimensional semiconductor memory device including an electrode structure on a substrate, the electrode structure including at least one conductive pattern on a lower electrode, and a semiconductor pattern extending through the electrode structure to the substrate. A vertical insulating layer may be between the semiconductor pattern and the electrode structure, and a lower insulating layer may be between the lower electrode and the substrate.
08/14/14
20140227840
new patent 3d non-volatile memory device and method for fabricating the same
A non-volatile memory device having a string of a plurality of memory cells that are serially coupled, wherein the string of memory cells includes a plurality of second channels of a pillar type, a first channel coupling lower end portions of the plurality of the second channels with each other, and a plurality of control gate electrodes surrounding the plurality of the second channels.. .
08/14/14
20140226427
new patent Memory device word line drivers and methods
Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors.
08/14/14
20140226424
new patent Memory device and corresponding reading method
An electrically erasable and programmable non-volatile memory device includes memory cells arranged in rows and columns, and each column of memory cells is associated with a respective local bit line. The local bit lines are divided into packets of local bit lines, each packet of local bit lines associated with a respective main bit line.
08/14/14
20140226422
new patent Semiconductor memory device and method of testing the same
A semiconductor memory device including an open bit line structure is disclosed. The semiconductor memory device including an open bit line structure includes a first mat, a second mat contiguous to the first mat, a first sense amplifier coupled to a first bit line of the first mat, a second sense amplifier coupled to a second bit line of the first mat and a third bit line of the second mat, a third sense amplifier coupled to a fourth bit line of the second mat, and a plurality of bit line precharge voltage providers for varying a level of a bit line precharge voltage provided to the first, second, and third sense amplifiers, selectively providing the resultant bit line precharge voltage level, and providing the same voltage as that of data of a selected cell to a non-selected sense amplifier during a read operation..
08/14/14
20140226421
new patent Clock signal generation apparatus for use in semiconductor memory device and its method
A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, including: a clock signal generation unit for receiving an internal clock signal to generate the reference clock signal according to a control signal; and a control unit for generating the control signal based on a read command, a write command and an external address.. .
08/14/14
20140226418
new patent Weak keeper circuit for memory device
A memory circuit is provided comprising a plurality of bit cells coupled to a bit line that permits accessing information from each of the plurality of bit cells. A sense inverter is coupled to an output of the bit line.
08/14/14
20140226416
new patent Erase operation with controlled select gate voltage for 3d non-volatile memory
An erase process for a 3d stacked memory device controls a drain-side select gate (sgd) and a source-side select gate (sgs) of a nand string. In one approach, sgd and sgs are driven to provide a predictable drain-to-gate voltage across the select gates while an erase voltage is applied to a bit line or source line.
08/14/14
20140226414
new patent Group word line erase and erase-verify methods for 3d non-volatile memory
An erase operation for a 3d stacked memory device assigned storage elements to groups according to an expected erase speed. The storage elements are then erased according to their group to provide a more uniform erase depth and a tighter erase distribution.
08/14/14
20140226408
new patent Nonvolatile memory device
According to one embodiment, a nonvolatile memory device includes a core unit and a peripheral circuit unit. The core unit is configured to be capable of storing data.
08/14/14
20140226407
new patent Nonvolatile semiconductor memory device
An erase verify operation is executed divided into at least a first erase verify operation and a second erase verify operation. The first erase verify operation is an operation that applies a verify read voltage only to a first group of memory cells among the plurality of memory cells included in the nand cell unit, and applies a first read pass voltage to memory cells other than the first group of memory cells.
08/14/14
20140226406
new patent Efficient smart verify method for programming 3d non-volatile memory
In a programming operation of a 3d stacked non-volatile memory device, an initial set of memory cells on a selected word line layer, involving fewer than all memory cells on a selected word line layer, are programmed first as a test case to determine optimal conditions for programming the remaining memory cells on the selected word line layer. For example, a number of program-verify iterations or loops which are needed to program the initial set of memory cells an initial amount is determined.
08/14/14
20140226403
new patent Memory system and method of driving memory system using zone voltages
A method is provided for driving a nonvolatile memory device, including multiple strings, where each string is formed by penetrating plate-shaped word lines stacked on a substrate. The method includes configuring the word lines of a string in multiple zones based on zone configuration information, and applying zone voltages to the zones, respectively.
08/14/14
20140226401
new patent Memory device and semiconductor device
A memory device in which data can be retained for a long time is provided. The memory device includes a memory element and a transistor which functions as a switching element for controlling supply, storage, and release of electrical charge in the memory element.
08/14/14
20140226397
new patent Nonvolatile memory device and control method thereof
A vertical nonvolatile memory device which includes a plurality of cell strings formed in a direction intersecting with a substrate is provided. The vertical nonvolatile memory device is configured to apply a non-selection read voltage to at least one selection line connected to a cell string from among the plurality of cell strings.
08/14/14
20140226396
new patent Tamper detection and response in a memory device
A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements.
08/14/14
20140226278
new patent Printed circuit board and printed wiring board
A memory system is provided with a motherboard, and a memory controller and a plurality memory devices mounted on the motherboard. The motherboard comprises a unicursal-shape main wiring, and branch wirings branched from the main wiring to the respective memory devices.
08/14/14
20140225280
new patent Semiconductor device having stacked memory elements and method of stacking memory elements on a semiconductor device
A semiconductor device includes a die coupled to a substrate, a first memory device coupled to a surface of the die opposite the substrate and a coupling device coupled between the surface of the die opposite the substrate and a second memory device such that the second memory device at least partially overlaps the first memory device. Also disclosed is method of mounting first and second memory devices on a die in an at least partially overlapping manner..
08/14/14
20140225183
new patent Three-dimensional semiconductor memory device
A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.. .
08/14/14
20140225179
new patent Nonvolatile semiconductor memory device
According to one embodiment, a memory cell includes a gate insulating layer on the active area, a floating gate electrode on the gate insulating layer, the floating gate electrode having a lower portion with a first width and a higher portion with a second width narrower than the first width, an intermediate insulating layer covering an end of the higher portion of the floating gate electrode, a charge storage layer being adjacent to the intermediate layer, an inter-electrode insulating layer covering the floating gate electrode and the charge storage layer, and a control gate electrode on the inter-electrode insulating layer.. .
08/14/14
20140225171
new patent Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device
Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device are disclosed. The techniques may be realized as a semiconductor memory device.
08/14/14
20140225116
new patent Deuterated film encapsulation of nonvolatile charge trap memory device
Nonvolatile charge trap memory devices with deuterium passivation of charge traps and methods of forming the same are described. In one embodiment, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device.
08/14/14
20140225055
new patent Resistive switching device for a non-volatile memory device
A method for forming a non-volatile memory device configured with a resistive switching element includes providing a substrate having a surface region, depositing a first dielectric material overlying the surface region, forming a first wiring structure overlying the first dielectric material, forming a contact layer of doped polycrystalline silicon containing material overlying the first wiring structure, forming a switching layer of resistive switching material over the contact layer, removing native oxide formed on a top surface of the switching layer, if any, depositing a metal layer of an active metal directly upon the top surface of the switching layer, and depositing a second wiring structure overlying the metal layer, wherein the top surface of the switching layer is cleaned of the native oxide, if any, to reduce agglomeration of the active metal.. .
08/14/14
20140225054
new patent Manufacturing method of non-volatile memory element, non-volatile memory element, and non-volatile memory device
A method of manufacturing a non-volatile memory element includes forming a first electrode; forming a variable resistance layer; and forming a second electrode. Forming the variable resistance layer includes forming a third metal oxide layer having a third metal oxide, forming a second metal oxide layer having a second metal oxide, and forming a first metal oxide layer e having a first metal oxide; wherein the variable resistance layer reversibly changes its resistance value in response to an electric signal applied between the first electrode and the second electrode; the first metal oxide is lower in degree of oxygen deficiency than the third metal oxide; the second metal oxide is lower in degree of oxygen deficiency than the third metal oxide; the third metal oxide is an oxygen-deficient metal oxide; and the first metal oxide layer is different in density from the second metal oxide layer..
08/14/14
20140225053
new patent Nonvolatile memory device and method for manufacturing the same
A variable resistance layer includes a first variable resistance layer comprising a first metal oxide that is oxygen deficient and a second variable resistance layer comprising a second metal oxide having a degree of oxygen deficiency that is different from that of the first metal oxide, wherein the second variable resistance layer includes a non-metal element a that is different from oxygen, x<(y+z) is satisfied where a composition of the first variable resistance layer is represented by mox and a composition of the second variable resistance layer is represented by noyaz, the second variable resistance layer has a higher resistivity than a resistivity of the first variable resistance layer, and a film density of the second variable resistance layer is lower than a theoretical film density of the second metal oxide which has a stoichiometric composition.. .
08/14/14
20140223715
new patent Product indication for filter status update
A water filter communication system and method of using the system. A method of periodically reading water filter data associated with a water filter and retained by the water filter that has been positioned in an appliance includes the steps of: installing a water filter into an engaged position in a filter head assembly within an interior of a cabinet of an appliance that includes a water inlet and a water outlet and periodically, based upon and after a user's interaction with the appliance or the water filter, supplying power from the appliance to the filter read-write memory device engaged to the filter housing; transmitting water filter data to the appliance from the filter read-write memory device, which retains filter information..
08/07/14
20140223399
Circuit analysis device and circuit analysis method
A circuit analysis device includes: a processor configured to execute a procedure by: calculating, for power supply noise included in a power supply voltage supplied to a semiconductor memory device, variation characteristics of an electric potential relative to the power supply voltage in a specific memory cell included in a memory cell array; calculating power supply noise of a power supply system that occurs when a current is supplied to an equivalent circuit of the power supply system under a predetermined condition, the power supply system including a power supply line and an element for supplying a power supply voltage from a voltage source to a semiconductor device; calculating, from the variation characteristics, the electric potential obtained when the power supply noise is equal to a specific magnitude; and determining, by comparing the calculated electric potential with a threshold, whether memory latch-up will occur in the specific memory cell.. .
08/07/14
20140223313
System for organizing and displaying information on a display device
A system for organizing, displaying, and interacting with information on a display device includes a computer processor and a memory device. The memory device stores at least one piece of computer code executable by the computers processor and data used by the computer code.
08/07/14
20140223260
Memory channel detector systems and methods
A method for determining decision metrics in a detector for a memory device. The method includes receiving a plurality of signal samples and extracting a set of statistics from the signal samples, wherein at least one of the statistics is non-linear or complex, is derived from a plurality of the signal samples, and is not a function of at least one real linear statistic that is derived from a plurality of the signal samples.
08/07/14
20140223257
Semiconducotr memory device including non-volatile memory cell array
A semiconductor memory device that may correct error data using an error correction circuit is disclosed. The semiconductor memory device may include a dram cell array, a parity generator, a nonvolatile memory cell array and an error correction circuit.
08/07/14
20140223245
Volatile memory device and methods of operating and testing volatile memory device
A method is provided for operating a volatile memory device. The method includes performing a first initialization operation for the volatile memory device based on a boot code received from an external memory controller, storing the boot code in an internal register, reading the boot code stored in the internal register based on a first signal received from the external memory controller when the first initialization operation is not normally performed, and performing a second initialization operation for the volatile memory device based on the boot code read from the internal register..
08/07/14
20140223239
Memory error management system
A memory error management system connected to memory channels for managing errors detected in corresponding memory devices includes a reporting table including a list of historically reported errors, a binary value representing the current error status of the memory channels, a uniqueness check module for checking whether a historically reported error is reappearing as a current error, an error mask register for generating a masked binary value representing unique current errors in the memory channels, and a channel arbitration module for decoding the channel identifiers of corrupted memory channels from the masked binary value and storing the decoded channel identifiers into the reporting table.. .
08/07/14
20140223198
Secure replay protected storage
Embodiments of the invention enable secure standard storage flash memory devices such as spi flash memory devices to achieve replay protection for securely stored data. Embodiments of the invention utilize flash memory controllers, flash memory devices, unique device keys and hmac key logic to create secure execution environments for various components..
08/07/14
20140223136
Lookup tables utilizing read only memory and combinational logic
The disclosure is directed to a system and method for accessing one or more values of a lookup table. In some embodiments, one or more read only memory devices are configured for storing a first plurality of values of the lookup table, and one or more combinational logic circuits are configured for accessing a second plurality of values of the lookup table.
08/07/14
20140223128
Memory device and method for organizing a homogeneous memory
A memory device comprising a memory controller and a homogeneous memory accessible by the memory controller, wherein the homogeneous memory is divided by the memory controller in a first memory partition and a second memory partition, wherein the first memory partition is allocated to a first type of information comprising user data and ecc data that are arranged interleaved with the user data, and wherein the second memory partition is allocated to a second type of information comprising further user data.. .
08/07/14
20140223120
Securing the contents of a memory device
A memory device may be equipped with quick erase capability to secure the contents of the memory device. The quick erase capability may effectively permanently disable access to data stored in the memory device instantaneously upon a command being issued, making all previous data written to the memory device unreadable.
08/07/14
20140223117
Securing the contents of a memory drive
A memory device may be equipped with quick erase capability to secure the contents of the memory device. The quick erase capability may effectively permanently disable access to data stored in the memory device instantaneously upon a command being issued, making all previous data written to the memory device unreadable.
08/07/14
20140223116
Methods for sequencing memory access requests
Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate requests that would occur if the memory access requests were to be executed in the received order are detected, and the received order of the memory access requests is rearranged to avoid or minimize the conflicts or delays and to optimize the flow of data to and from the memory data bus.
08/07/14
20140223087
Multi-partitioning of memories
Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller.
08/07/14
20140223086
Rapid reading from memory devices
The invention generally relates to rapid reading of data from multi-level cell (mlc) memory devices. Information is stored in a way that allows all of the bit-space to be used but that also allows single-read-per-cell retrieval.
08/07/14
20140223084
Memory system and related method of operation
A method of operating a memory system comprises determining whether a write request from a host is a random write request, and as a consequence of determining that the write request is a random write request, programming a lower page of a selected word line of a nonvolatile memory device with restorable data of the nonvolatile memory device, and programming an upper page of the selected word line with write data corresponding to the write request after programming the lower page.. .
08/07/14
20140223080
Non-volatile memory device, electronic control system, and method of operating the non-volatile memory device
Provided are a non-volatile memory device, an electronic control system, and a method of operating the non-volatile memory device. A non-volatile memory device according to an embodiment of the present invention includes a first nand cell array including a first group of pages, and a second nand cell array including a second group of pages.
08/07/14
20140223068
Memory system topologies including a buffer device and an integrated circuit memory device
Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path.
08/07/14
20140223035
Memory method and apparatus with button release
A flash memory device apparatus and method is provided such that data or programming information is uploaded or downloaded between the flash memory device and a host, in response to a single-press of a button associated with the flash memory device. The system can facilitate a number of operations including saving an active window application or associated data, transferring media files to or from media players, providing device-specific and/or data-specific transfer of applications or data and/or providing protection of transferred data or applications..
08/07/14
20140222597
Intelligent mobile payment system and method
An intelligent wallet (iw) computer device is provided for recommending a payment card from a plurality of payment cards to a cardholder for use in a payment transaction with a merchant. The iw computer device includes a memory device for storing data and a processor in communication with the memory device.
08/07/14
20140222458
Method and appratus for collecting and analyzing surface wound data
A computer-implemented method of analyzing damage to personal protective equipment (ppe) uses a processor connected to a memory device. A plurality of location informations are stored in the memory device.
08/07/14
20140222364
Magnetic field sensor and associated method that can establish a measured threshold value and that can store the measured threshold value in a memory device
A magnetic field sensor includes a true power on state (tpos) detector for which a measured threshold value is stored prior to power down and recalled upon power up. A corresponding method is associated with the magnetic field sensor..
08/07/14
20140222197
System and method for monitoring operation of an autonomous robot
A system and method for monitoring operation of an autonomous robot. In one aspect, the invention can be a method comprising: defining, with a central processing unit of the autonomous robot, a perimeter of an area of confinement; storing the perimeter of the area of confinement within a memory device of the autonomous robot as map data; transmitting the map data from a transceiver of the autonomous robot to a server; overlaying, by the server, the area of confinement onto a satellite image corresponding to a geographic location that includes the area of confinement to create a visual representation of the area of confinement overlaid onto the satellite image; transmitting, from the server to an external device, the visual representation of the area of confinement overlaid onto the satellite image; and displaying, on a display, the visual representation of the area of confinement overlaid onto the satellite image..
08/07/14
20140220771
Worm memory device and process of manufacturing the same
A process of manufacturing a write-once-read-many-times memory, at least includes the following steps: (a) providing a substrate as a lower electrode; (b) depositing a first oxide layer on the substrate; (c) depositing at least one or more silicon/germanium (si/ge) layers on the first oxide layer; (d) depositing a second oxide layer on the at least one or more si/ge layers; (e) carrying out a rapid thermal annealing to form sige nanocrystals embedded in the first dioxide layer and the second oxide layer; and (f) depositing a conductive layer on the second oxide layer as an upper electrode. The sige nanocrystals embedded in the al2o3 bilayer as the active layer of the worm memory offers high thermal stability, so that low operating voltage, fast writing, ideal reading durability, persistence at high temperature, and the highly reliable memory performance for effectively reading data at high temperature can be achieved..
08/07/14
20140220763
Memory devices and formation methods
A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types.
08/07/14
20140220750
Semiconductor memory device and method of fabricating the same
Provided are a semiconductor device and a method of fabricating the same. The method may include forming an electrode structure including insulating layers and electrode layers alternatingly stacked on a substrate, forming a channel hole to penetrate the electrode structure, forming a data storage layer on a sidewall of the channel hole, and forming a semiconductor pattern on a sidewall of the data storage layer to be electrically connected to the substrate.
08/07/14
20140220733
Antimony and germanium complexes useful for cvd/ald of metal thin films
Antimony, germanium and tellurium precursors useful for cvd/ald of corresponding metal-containing thin films are described, along with compositions including such precursors, methods of making such precursors, and films and microelectronic device products manufactured using such precursors, as well as corresponding manufacturing methods. The precursors of the invention are useful for forming germanium-antimony-tellurium (gst) films and microelectronic device products, such as phase change memory devices, including such films..


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