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Memory Device

Memory Device-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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Method and apparatus for remote prefetches of variable size
Intel Corporation
December 07, 2017 - N°20170353576

In one embodiment, an apparatus comprises a processor to generate, in anticipation of receipt of a read request for data of a data set, a prefetch request to retrieve the data set from a memory device, the prefetch request to comprise at least one parameter indicating a size of the data set. The processor is further to cause transmission of ...
Packet descriptor storage in packet memory with cache
Marvell Israel (m.i.s.l) Ltd.
December 07, 2017 - N°20170353403

A first memory device stores (i) a head part of a fifo queue structured as a linked list (ll) of ll elements arranged in an order in which the ll elements were added to the fifo queue and (ii) a tail part of the fifo queue. A second memory device stores a middle part of the fifo queue, the middle ...
On-die termination
Rambus Inc.
December 07, 2017 - N°20170353184

Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of ...
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Double spin filter tunnel junction
International Business Machines Corporation
December 07, 2017 - N°20170352803

A memory device that includes a first magnetic insulating tunnel barrier reference layer present on a first non-magnetic metal electrode, and a free magnetic metal layer present on the first magnetic insulating tunnel barrier reference layer. A second magnetic insulating tunnel barrier reference layer may be present on the free magnetic metal layer, and a second non-magnetic metal electrode may ...
Semiconductor memory device
International Business Machines Corporation
December 07, 2017 - N°20170352801

A semiconductor memory device that includes at least a lower contact plug on a semiconductor substrate, a magnetic tunnel junction of the lower contact plug, and a barrier pattern on a sidewall of the lower contact plug may further include an insulation pattern on the sidewall of the lower contact plug. The insulation pattern may be between the barrier pattern ...
Electronic memory devices
Lancaster University Business Enterprises Limited
December 07, 2017 - N°20170352767

A memory cell for storing one or more bits of information has a control gate, a source terminal and a drain terminal. A semiconductor substrate is located between the source and drain terminals, and a floating gate is disposed between the control gate and the semiconductor substrate. The floating gate is electrically isolated from the control gate by a charge ...
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Memory Device Patent Applications
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  • 2989+ full patent PDF documents of Memory Device-related inventions.
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Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region
Cypress Semiconductor Corporation
December 07, 2017 - N°20170352732

A memory is described. Generally, the memory includes a number of non-planar multigate transistors, each including a channel of semiconducting material overlying a surface of a substrate and electrically connecting a source and a drain, a tunnel dielectric layer overlying the channel on at least three sides thereof, and a multi-layer charge-trapping region overlying the tunnel dielectric layer. In one ...
Memory device and method for manufacturing the same
Toshiba Memory Corporation
December 07, 2017 - N°20170352705

A memory device according to one embodiment includes a resistance change film, an insulating film provided on the resistance change film, a first wiring provided on the insulating film and being not in contact with the resistance change film, and a high resistance film having a higher resistivity than the first wiring. The high resistance film is provided on a ...
Memory device
Toshiba Memory Corporation
December 07, 2017 - N°20170352680

In one embodiment, the semiconductor device includes a substrate having an impurity region, and the substrate and the impurity region have a different impurity characteristic. The semiconductor device further includes a stack of alternating first interlayer insulating layers and gate electrode layers on the substrate; at least one second interlayer insulating layer formed on the stack; a plurality of bit ...
Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making ...
Sandisk Technologies Llc
December 07, 2017 - N°20170352678

Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a ...
Semiconductor memory device
Toshiba Memory Corporation
December 07, 2017 - N°20170352672

A semiconductor memory device according to an embodiment includes first and second semiconductor pillars extending in a first direction and being arranged along a second direction, first and second interconnects extending in a third direction and being provided between the first semiconductor pillar and the second semiconductor pillar, a first electrode provided between the first semiconductor pillar and the first ...
Semiconductor memory device and method for manufacturing same
Toshiba Memory Corporation
December 07, 2017 - N°20170352671

A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the first electrode and the second electrode and on two first-direction sides of ...
Three-dimensional memory device having multilayer word lines containing selectively grown cobalt or ruthenium and method ...
Sandisk Technologies Llc
December 07, 2017 - N°20170352669

A memory stack structure including a memory film and a vertical semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulating layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulating layers, a backside blocking dielectric layer may be ...
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Memory Device Patent Applications
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  • 2989+ full patent PDF documents of Memory Device-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
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Semiconductor device using a parallel bit operation and method of operating the same
Samsung Electronics Co., Ltd.
December 07, 2017 - N°20170352434

A memory device may include a memory cell array including a plurality of memory cells, and an internal operation circuit configured to perform a test operation in a test mode using a parallel bit operation of simultaneously comparing a plurality of bits and also perform an internal operation including a comparison operation with respect to external data in a normal ...
Memory device including extra capacity and stacked memory device including the same
Samsung Electronics Co., Ltd.
December 07, 2017 - N°20170352433

A memory device includes a memory cell array, a multiplexing circuit, and a control logic circuit. The memory cell array includes a first sub memory cell array, a second sub memory cell array, and a third sub memory cell array. The multiplexing circuit selects the first sub memory cell array, the second sub memory cell array, and the third sub ...
Memory devices configured to perform leak checks
Micron Technology, Inc.
December 07, 2017 - N°20170352431

Memory devices include an array of memory cells and circuitry for control and/or access of the array of memory cells, wherein the circuitry is configured to perform a method including applying a particular voltage to an unselected access line of a program operation, sensing a current of a selected access line of the program operation while applying the particular ...
Memory refresh methods and apparatuses
Micron Technology, Inc.
December 07, 2017 - N°20170352429

Apparatuses and memory refresh methods are disclosed, such as those involving checking a portion of a memory device for errors in response to the memory device being powered on, and reprogramming corrected data to the memory device if errors are found in checking the portion of the nonvolatile memory for errors. Other apparatuses and memory refresh methods are disclosed.
Non-volatile memory devices comprising high voltage generation circuits and operating methods thereof
Samsung Electronics Co., Ltd.
December 07, 2017 - N°20170352428

A non-volatile memory device includes a memory cell array including a plurality of memory cells, wherein at least one selected memory cell that is selected from among the plurality of memory cells is programmed based on a high voltage, a high voltage generator configured to generate the high voltage by boosting an input voltage based on a pumping clock, a ...
Nonvolatile semiconductor storage device
Floadia Corporation
December 07, 2017 - N°20170352425

A non-volatile semiconductor memory device in which, while voltage from a first control line is applied, as a memory gate voltage, to a sub control line through a switching transistor, another switching transistor can block voltage application to a corresponding sub control line. Thus, while a plurality of memory cells are arranged in one direction along the first control line, ...
Data retention flags in solid-state drives
Western Digital Technologies, Inc.
December 07, 2017 - N°20170352423

Systems and methods for managing data retention in a solid-state storage system utilizing data retention flag bytes are disclosed. A data storage device includes a non-volatile memory comprising a plurality of non-volatile memory devices and a controller configured to write data to a memory unit of the non-volatile memory array and write a data retention flag value indicating a number ...
Solid state drive with improved power efficiency
Toshiba Corporation
December 07, 2017 - N°20170352422

A solid state drive (ssd) with improved power efficiency includes one or more non-volatile memory devices configured to operate according to a programming voltage for a program function or an erase function and to a supply voltage for a read function. The ssd also includes a voltage regulator, external of the one or more non-volatile memory devices, having an output ...
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