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Memory Device patents

      

This page is updated frequently with new Memory Device-related patent applications.




 Methods and  detecting space-shifted media associated with a digital recording/playback device patent thumbnailMethods and detecting space-shifted media associated with a digital recording/playback device
Methods and apparatus for detecting space-shifted media content associated with a digital recording/playback device are disclosed. An example apparatus includes a meter to detect presentation of media by a media playback device; a network analyzer to detect a data packet transmitted from a network database to the media playback device; and determine that the data packet includes the media; and a memory device to, in response to determining that the data packet includes the media, store an indication that the media was space-shifted..
The Nielsen Company (us), Llc


 On-die termination control without a dedicated pin in a multi-rank system patent thumbnailOn-die termination control without a dedicated pin in a multi-rank system
A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (odt) settings.
Intel Corporation


 Semiconductor memory device and  manufacturing the same patent thumbnailSemiconductor memory device and manufacturing the same
According to one embodiment, a semiconductor memory device includes first and second interconnect parts, and a second interconnect connection part. The first interconnect part includes a first core part, and a first interconnect layer.
Kabushiki Kaisha Toshiba


 Magnetic element and memory device patent thumbnailMagnetic element and memory device
According to one embodiment, a magnetic element includes a first stacked unit and a third ferromagnetic layer. The first stacked unit includes first and second ferromagnetic layers, and a first non-magnetic layer.
Kabushiki Kaisha Toshiba


 Embedded memory in interconnect stack on silicon die patent thumbnailEmbedded memory in interconnect stack on silicon die
A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein forming ones of the plurality of first interconnects and a plurality of second interconnects includes embedding memory devices therein. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein ones of the plurality of first interconnects and a plurality of second interconnects includes memory devices embedded therein..
Intel Corporation


 Magnetic memory device and  manufacturing the same patent thumbnailMagnetic memory device and manufacturing the same
According to one embodiment, a magnetic memory device includes a stacked structure including a magnetic layer, and an upper structure provided on the stacked structure, and including a first portion and a second portion surrounding the first portion and formed of material different from that of the first portion.. .
Kabushiki Kaisha Toshiba


 Semiconductor memory device and  manufacturing the same patent thumbnailSemiconductor memory device and manufacturing the same
Provided is a semiconductor device, which prevents unnecessary voltage drop in a mos transistor that is connected in series in a location between a booster circuit and a memory main body portion, to thereby operate on a low voltage and improve the on/off ratio so that chip size shrinking and memory performance improvement are accomplished simultaneously. In a semiconductor memory device including a memory transistor portion and a select transistor portion, at least the select transistor portion is formed of a fin-shaped single-crystal semiconductor thin film..
Sii Semiconductor Corporation


 Semiconductor memory device and  manufacturing the same patent thumbnailSemiconductor memory device and manufacturing the same
The embodiments provide a semiconductor memory device including: a plurality of first wiring lines extending in a first direction, the first wiring lines being provided in a second direction intersecting the first direction; a plurality of second wiring lines extending in the second direction, the second wiring lines being provided in the first direction; a plurality of memory cells provided in the intersections between the first wiring lines and the second wiring lines, each memory cell having a first stack structure comprising at least a variable resistor film; a contact extending in a third direction intersecting the first and second directions, the contact having a first end connected to one of the first wiring lines or one of the second wiring lines, the contact having a second stack structure having a stack of a plurality of films; and a wiring layer connected to a second end of the contact. At least some of the films of the second stack structure have generally the same third direction position and film thickness as at least some of layers of the first stack structure.
Kabushiki Kaisha Toshiba


 Nonvolatile semiconductor memory device patent thumbnailNonvolatile semiconductor memory device
A nonvolatile semiconductor memory device includes a memory cell array. The memory cell array includes conducting layers, semiconductor layers, variable resistance films, and first wirings.
Kabushiki Kaisha Toshiba


 Magnetic memory device patent thumbnailMagnetic memory device
According to one embodiment, a magnetic memory device includes a stack structure including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, wherein the second magnetic layer includes a first layer containing iron (fe) and boron (b), a second layer containing iron (fe) and boron (b), and a third layer provided between the first layer and the second layer and containing a semiconductor.. .
Kabushiki Kaisha Toshiba


Semiconductor memory device and manufacturing same

According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on the insulating layer; a stacked body provided on the conductive layer and including a plurality of electrode layers and a plurality of insulating layers respectively provided among the plurality of electrode layers; a columnar section piercing through the stacked body to reach the conductive layer and extending in a first direction in which the stacked body is stacked; and a source layer. The columnar section includes a channel body and a charge storage film provided between the channel body and the respective electrode layers.
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing method thereof

A semiconductor memory device according to an embodiment includes a memory cell array that includes memory cells and a plurality of first conducting layers. The memory cells are arrayed in a three-dimensional manner.
Kabushiki Kaisha Toshiba

Method for manufacturing semiconductor device

Embodiments of the inventive concepts provide a method for manufacturing a three-dimensional semiconductor memory device. The method includes forming a stack structure including insulating layers and sacrificial layers which are alternately and repeatedly stacked on a substrate.
Samsung Electronics Co., Ltd.

Memory device and manufacturing the same

A memory device includes a plurality of gate electrode layers, an interlayer insulating layer, a plurality of contact plugs, and at least one contact insulating layer. The gate electrode layers extend in a first direction and have different lengths to form a step structure.

Semiconductor memory device and manufacturing method thereof

A semiconductor memory device according to an embodiment includes a laminated body. The laminated body is disposed above a semiconductor substrate.
Kabushiki Kaisha Toshiba

Non-volatile memory device and manufacturing same

A non-volatile memory device comprises a first electrode, a second electrode stacked on the first electrode, a semiconductor layer extending in a first direction through the first electrode and the second electrode, charge storage parts respectively provided between the first electrode and the semiconductor layer and between the second electrode and the semiconductor layer, and a barrier body arranged with the first electrode and the second electrode in a second direction orthogonal to the first direction and extending in the first direction. A distance between the second electrode and the barrier body is wider in the second direction than a distance between the first electrode and the barrier body..
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing the same

According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a memory film and a conductive member. The stacked body includes a plurality of electrode layers arranged in a first direction.
Kabushiki Kaisha Toshiba

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a stacked body; a semiconductor body; a charge storage layer; a first conductor; a second conductor; and a third conductor. The stacked body includes a plurality of electrode layers stacked with an insulator interposed.
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing the same

According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a memory film and a first contact portion. The stacked body includes a first electrode film, a second electrode film and an inter-electrode insulating film.
Kabushiki Kaisha Toshiba

Semiconductor memory device

According to one embodiment, a semiconductor memory device comprises a first semiconductor region of n-type conductivity, a second semiconductor region of p-type conductivity, a third semiconductor region of n-type conductivity, a stacked body, a semiconductor pillar, a first insulating layer, a charge storage layer, a second insulating layer, a first conductive portion, and a second conductive portion. The semiconductor pillar extends in the stacked body in a direction in which the conductive layers and the insulating layers are stacked.
Kabushiki Kaisha Toshiba

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and at least one columnar member. The stacked body is provided on the substrate.
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing same

According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of insulating layers and including a first insulating layer and a plurality of conductive layers including a first conductive layer; a first semiconductor film extending in a stacking direction of the stacked body; a second semiconductor film, the second semiconductor film having a maximum thickness thicker than a maximum thickness of the first semiconductor film in a first direction crossing the stacking direction; and a first insulating film. The second semiconductor film has an upper face, and a height of the upper face is lower than a height of the first conductive layer.
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing the same

According to one embodiment, a semiconductor memory device includes a structural body, first to fourth pillars, a first interconnection, a second interconnection, a third interconnection, and a fourth interconnection. The first to fourth pillars provides within the structural body extending along the first direction.
Kabushiki Kaisha Toshiba

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a plurality of memory cells arranged on a substrate. The semiconductor memory device includes an interconnect layer including a first interconnect and a second interconnect, the first interconnect extending in a first direction, the second interconnect extending in a second direction, the first direction being tilted with respect to an arrangement direction of the memory cells, the second direction being different from the first direction and tilted with respect to the arrangement direction of the memory cells..
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing the same

A semiconductor memory device according to an embodiment includes a first semiconductor layer containing an acceptor and a memory cell array including an interlayer insulating layer and a conductive layer arranged in a first direction above the first semiconductor layer and a memory columnar body extending in the first direction and having a lower end positioned lower than a position of a top surface of the first semiconductor layer, the memory columnar body containing a second semiconductor layer in a columnar shape having a side face opposite to a side face of the conductive layer, wherein a first portion of the first semiconductor layer in contact with the side face of the memory columnar body contains a donor in a higher concentration than a second portion different from the first portion of the first semiconductor substrate.. .
Kabushiki Kaisha Toshiba

Semiconductor memory device and production method thereof

A semiconductor memory device according to an embodiment includes a memory cell array which has: a first conductive layer which is arranged in a first direction on a first semiconductor layer; a second conductive layer which is arranged in the first direction above the first conductive layer; a columnar second semiconductor layer which extends in the first direction; and a contact unit which electrically connects the first semiconductor layer and the second conductive layer. The contact unit has a first film which contains silicide as a first metal, and is in contact with the first semiconductor layer; and a second film which contains the first metal, is in contact with the first film, and is in contact with the first semiconductor layer with the first film interposed therebetween..
Kabushiki Kaisha Toshiba

Semiconductor memory device

A semiconductor memory device according to an embodiment includes: an insulating layer; a conductive layer stacked above the insulating layer in a first direction, the conductive layer having a second direction as a longitudinal direction and a third direction as a short direction; and a channel semiconductor layer extending in the first direction, and the conductive layer including a recessed portion narrowed in the third direction.. .
Kabushiki Kaisha Toshiba

Three dimensional memory device having isolated periphery contacts through an active layer exhume process

A three dimensional memory device is described having an array region and a periphery region. The array region has a three dimensional stack of storage cells.

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device according to an embodiment comprises a memory cell, the memory cell comprising: a semiconductor layer; a control gate electrode; a charge accumulation layer disposed between the semiconductor layer and the control gate electrode; a first insulating layer disposed between the semiconductor layer and the charge accumulation layer; and a second insulating layer disposed between the charge accumulation layer and the control gate electrode, the charge accumulation layer including an insulator that includes silicon and nitrogen, and the insulator further including: a first element or a second element, the second element being different from the first element; and a third element different from the first element and the second element.. .
Kabushiki Kaisha Toshiba

Semiconductor memory device

A semiconductor memory device includes a first word line that is provided above a semiconductor substrate, a second word line that is provided above the first word line, a plurality of semiconductor pillars that are provided on the semiconductor substrate, and pass through the first and second word lines, and first and second plugs that are provided so that the plurality of semiconductor pillars are interposed therebetween. The semiconductor substrate includes an insulating region that is provided deeper than a bottom of the first plug relative to a surface of the semiconductor substrate, between the first plug and one of the semiconductor pillars..
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing the same

An embodiment includes: a semiconductor substrate, a memory cell array region including a plurality of conductive layers connected to memory cells arranged in a stacking direction on the semiconductor substrate; a peripheral region including a transistor on the substrate ; a plurality of first layers and second layers stacked alternately in the stacking direction, above the transistor; and a plurality of first contacts penetrating the plurality of first and second layers and connected to the transistor. The plurality of first layers and second layers are stacked alternately in the stacking direction, above the transistor disposed in the peripheral region.
Kabushiki Kaisha Toshiba

Nonvolatile semiconductor memory device and manufacturing the same

A semiconductor memory device according to an embodiment includes a plurality of channel layers, a gate-insulating film disposed on the channel layer, a floating gate electrode disposed on the gate-insulating film, a block insulating film disposed over the floating gate electrode, the block insulating film including at least a first insulating film and a second insulating film, the second insulating film including lanthanum and aluminum, and a control gate electrode disposed on the block insulating film. The second insulating film includes an upwardly convex curved portion in a region between the channel layers..
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing the same

According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction on the substrate. The semiconductor memory device also includes a memory hole that extends in the stacked body in the first direction and a semiconductor member that is disposed to extend in the memory hole in the first direction.
Kabushiki Kaisha Toshiba

Semiconductor device, non-volatile semiconductor memory device and manufacturing semiconductor device

According to one embodiment, it includes a stacked body including n-number of layers (n is an integer of 2 or more) stacked on a semiconductor substrate, opening portions penetrating the stacked body in a stacking direction, columnar bodies respectively disposed in the opening portions, and a slit dividing m-number of layers (m is an integer of 1 or more and (n−2) or less) of the stacked body in a horizontal direction from above, wherein the slit is formed with lateral surfaces respectively having a spatial periodicity in a horizontal plane.. .
Kabushiki Kaisha Toshiba

Method for manufacturing semiconductor memory device, semiconductor wafer and semiconductor memory device

A method for manufacturing includes forming a first insulating film on a substrate, forming first to third portions in the first insulating film, forming a second insulating film on the first insulating film, removing a part of the second portion, a portion including a region directly above the part of the second portion of the second insulating film, and at least a part of a portion including a region directly above the other part of the second portion of the second insulating film, and forming a first stacked body, forming a stacked film by alternately stacking third and fourth insulating films, and forming a stacked structure by processing a remaining part of the stacked film into a stepped pattern forming steps at each of the third insulating films. A depression is formed on the region directly above the third portion in an upper surface of the second insulating film..
Kabushiki Kaisha Toshiba

Finfet memory device

A finfet system comprises a first inverter comprising a first p-type pull-up transistor (pu) and a first n-type pull-down transistor (pd connected in series with the first pd, a second inverter cross-coupled to the first inverter comprising a second pu and a second pd connected in series with the second pd, a first pass-gate transistor, wherein the first pass-gate transistor is coupled between the first inverter and a first bit line, a second pass-gate transistor, wherein the second pass-gate transistor is coupled between the second inverter and a second bit line, a first dummy transistor coupled to a first common node of the first pu and the first pd and a second dummy transistor coupled to a second common node of the second pu and the second pd.. .
Taiwan Semiconductor Manufacturing Company, Ltd.

Nonvolatile memory device manufacturing method

A method of manufacturing a nonvolatile memory device includes sequentially forming, on a first wiring layer extending in a first direction, a first layer containing a first metal and a second layer containing a second metal into which the first metal can diffuse. The method further includes oxidizing the first layer and the second layer, removing oxygen from the oxidized first layer by annealing, forming a conductive third layer on the oxidized second layer after removing oxygen from the oxidized first layer, and forming a second wiring layer on the third layer.
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing method thereof

According to an embodiment, a semiconductor memory device includes a plurality of first conductive layers disposed above a substrate in a laminating direction. A stepped wiring area includes a second conductive layer electrically connected to the first conductive layer.
Kabushiki Kaisha Toshiba

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, and a first interconnect. When an imaginary first straight line extending in a second direction crossing a first direction is set, the plurality of columnar portions are divided into first sets of n (n is an integer number not less than 3 and not more than 32) columnar portions with center axes alternately disposed on both sides of the first straight line along the second direction and second sets of n columnar portions having position relationships of inversion of the first sets with respect to the first straight line, and the first sets and the second sets are alternately arranged..
Kabushiki Kaisha Toshiba

Stair step formation using at least two masks

Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area.
Micron Technology, Inc.

Casimir effect memory cell

A digital memory device includes a moveable element that is configured to move between a first stable position and a second stable position, where the moveable element comprises a first conducting area. The digital memory device further includes a second conducting area on the surface of a substrate.
Elwha Llc

Programming of non-volatile memory subjected to high temperature exposure

A memory device having features of the present invention comprises a reprogrammable memory portion including therein a first plurality of magnetic tunnel junctions (mtjs) whose resistance is switchable; and a one-time-programmable (otp) memory portion including therein a second plurality of mtjs whose resistance is switchable and a third plurality of mtjs whose resistance is fixed. Each mtj of the first, second, and third plurality of mtjs includes a magnetic free layer having a magnetization direction substantially perpendicular to a layer plane thereof and a magnetic reference layer having a fixed magnetization direction substantially perpendicular to a layer plane thereof.
Avalanche Technology, Inc.

Semiconductor memory device

A semiconductor memory device includes a memory cell includes a charge storage layer, a word line that is connected to a gate of the memory cell, and a controller that performs a write operation on the memory cell by applying a write voltage to the word line, and a verify operation to verify a threshold voltage of the memory cell after the write operation. The verify operation includes a first verify operation using a first verify voltage, and a second verify operation using a second verify voltage higher than the first verify voltage..
Kabushiki Kaisha Toshiba

Semiconductor pillars charged in read operation

A memory device includes a word line above a semiconductor substrate, a semiconductor pillar extending through the word line in a direction crossing a surface of the semiconductor substrate, a memory cell at an intersection of the word line and the semiconductor pillar and having a gate electrically connected to the word line, a bit line electrically connected to a first end of the memory cell, a source line electrically connected to a second end of the memory cell, and a controller that controls a write operation on the memory cell, the write operation including a program operation followed by a verify operation. During the verify operation on the memory cell, the semiconductor pillar is charged after performing a read operation on the memory cell..
Kabushiki Kaisha Toshiba

Memory device

According to one embodiment, a memory device includes a string unit including a plurality of memory cell transistors which are connected in series, a first select transistor connected to a first end of the plurality of memory cell transistors, and a second select transistor connected to a second end of the plurality of memory cell transistors; and a bit line connected to the first select transistor.. .
Kabushiki Kaisha Toshiba

Verify operations using different sense node voltages in a memory device

Sense circuits in a memory device can be pre-charged to different levels in a sensing process to reduce the amount of time used for sensing. For example, in a program operation, a memory cell is in a fast programming mode until its threshold voltage exceeds an offset verify voltage (vo) of a data state.
Sandisk Technologies Inc.

Flash memory system using complementary voltage supplies

A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns.
Silicon Storage Technology, Inc.

Access line management in a memory device

Memory devices are configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device.
Micron Technology, Inc.

Multiple blocks per string in 3d nand memory

Embodiments describe techniques and configurations for an apparatus including a three-dimensional (3d) memory array having a plurality of strings of memory cells, where individual strings may have memory cells that correspond to different memory blocks (e.g., multiple memory blocks per string). For example, a first set of memory cells of a string may be included in a first memory block, and a second set of memory cells of the string may be included in a second memory block.
Intel Corporation

Non-volatile semiconductor memory device and memory system

A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level.
Kabushiki Kaisha Toshiba

Semiconductor memory device and operating method thereof

A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation or erase operation of the memory cell array; and a control logic controlling the peripheral circuit. The control logic controls the peripheral circuit such that a first program allowable voltage applied to bit lines of the memory cell array during a first program operation of the program operation and a second program allowable voltage applied during a second program operation of the program operation are different from each other..
Sk Hynix Inc.

Memory system

A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset..
Kabushiki Kaisha Toshiba

Voltage generating circuit and semiconductor memory device

A voltage generating circuit includes a first booster circuit that generates a first boosted voltage from a voltage supplied to an input thereof, a first transistor having a first terminal electrically connected to the input of the first booster circuit, a second booster circuit that generates a second boosted voltage from a voltage supplied to an input thereof, a second transistor having a first terminal electrically connected to the input of the second booster circuit and a second terminal electrically connected to a voltage source, and a control circuit electrically connected between the voltage source and a second terminal of the first transistor, the control circuit configured to cut off the voltage source from the second terminal of the first transistor in accordance with a voltage level of the voltage source.. .
Kabushiki Kaisha Toshiba

Semiconductor memory device

A semiconductor memory device includes a first block having a first memory cell and a second block having a second memory cell, first and second word lines respectively connected to the first and second memory cells, first and second select transistors having first ends respectively connected to the first and second word lines, a first circuit configured to apply a voltage to the first word line, and to control a gate voltage of the second select transistor, a second circuit configured to apply a voltage to the second word line, and to control a gate voltage of the first select transistor, first and second wirings respectively connected to second ends of the first and second select transistors, a third circuit configured to apply a voltage to the first wiring, and a fourth circuit configured to apply a voltage to the second wiring.. .
Kabushiki Kaisha Toshiba

Semiconductor memory device and operation method thereof

A semiconductor memory device according to an embodiment includes a control circuit configured to apply a first voltage to a selected first line, apply a second voltage to a selected second line, and apply a third voltage and a fourth voltage to a non-selected first line and a non-selected second line in a setting operation, respectively. The control circuit includes a detection circuit configured to detect a transition of a resistance state of a selected memory cell using a reference voltage.
Kabushiki Kaisha Toshiba

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes: first and second memory cells each including a variable resistance element; a first sense amplifier having a first input terminal coupled to the first memory cell; a second sense amplifier having a first input terminal coupled to the second memory cell; and a first current generator including a first resistance element coupled to a second input terminal of the first sense amplifier and a second input terminal of the second sense amplifier, and generating a first current supplied to the first sense amplifier or the second sense amplifier. The first sense amplifier is set to an active state and the second sense amplifier is set to an inactive state in a read operation of the first memory cell..
Kabushiki Kaisha Toshiba

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes first and second memory cells, a word line, first and second bit lines, a sense amplifier and a driver. The first and second memory cells have first and second threshold voltages, respectively.
Toshiba America Electronic Components, Inc.

Memory with output control

An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device.
Conversant Intellectual Property Management Inc.

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a first memory cell, a second memory cell, and a third memory cell, a first word line coupled to the first memory cell, the second memory cell, and the third memory cell, a first bit line coupled to the first memory cell, a second bit line coupled to the second memory cell, and a third bit line coupled to the third memory cell. A first voltage, a second voltage, and a third voltage are sequentially applied to the first word line, and a fourth voltage is applied to the first bit line when the first voltage is applied to the first word line, applied to the second bit line when the second voltage is applied to the first word line, and applied to the third bit line when the third voltage is applied to the first word line..
Kabushiki Kaisha Toshiba

Systems and methods for reducing standby power in floating body memory devices

Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0.
Zeno Semiconductor, Inc.

Memory device and storing method

It is required to store data to be stored for a holding period required for this data and then erase the data while suppressing power consumption. A memory device 10 to solve such a problem has the following configuration.
Renesas Electronics Corporation

Memory device refresh commands on the fly

On the fly switching from one memory device refresh rate to another is provided. Control logic associated with the memory device detects a condition to switch from a currently-applied refresh rate to a different refresh rate.

Row hammer refresh command

A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses.
Intel Corporation

Semiconductor integrated circuit capable of precisely adjusting delay amount of strobe signal

An interface circuit provided in a semiconductor device supplies an operation clock to an external memory device based on a clock signal (ck) and receives a data signal (dq) and a strobe signal (dqs) from the external memory device. The interface circuit includes a delay circuit delaying the received strobe signal (dqs).
Renesas Electronics Corporation

Logical operation circuit and memory device

According to one embodiment, a logical operation circuit includes a magnetic tunnel junction (mtj) element and driver. The mtj element includes a first magnetic layer, a second magnetic layer, and an intermediate layer between the first and second magnetic layers.

Multi-bit mram cell and writing and reading to such mram cell

A multi-bit magnetic random access memory (mram) cell including a magnetic tunnel junction including: a first magnetic storage layer, a second magnetic storage layer, a magnetic sense layer, a first spacer layer between the first magnetic storage layer and the magnetic sense layer, and a second spacer layer between the second magnetic storage layer and the sense layer. The first and second storage magnetization are switchable between m directions to store data corresponding to one of m2 logic states, with m>2.
Crocus Technology Sa

Memory device, memory module, and memory system

A memory device includes a memory cell array, a data pattern providing unit, and a write circuit. The memory cell array includes a plurality of memory regions.
Samsung Electronics Co., Ltd.

Multiprocessor system with independent direct access to bulk solid state memory resources

A system includes a plurality of processors, each being coupled to each of remaining processors via a cluster of processor interconnects. The cluster of processor interconnects form a data distribution network.
Emc Corporation

Memory device and electronic apparatus including the same

A memory device includes a plurality of channels that respectively include memory cell arrays and local input/output lines electrically coupled to the memory cell arrays and are independently operable, shared global input/output lines electrically coupled to the local input/output lines included in the plurality of channels and having a connection relation controlled through one or more path switch circuits arranged among the plurality of channels, and the path switch circuits that control the connection relation of the shared global input/output lines according to a path control signal.. .
Sk Hynix Inc.

Memory device

A memory device according to one embodiment includes a memory cell which transitions to a first state or a second state by a first current through the memory cell; and a first circuit configured to stop supplying the first current when a first number of cycles of a clock signal lapses from reception of write data.. .
Kabushiki Kaisha Toshiba

Memory device

According to one embodiment, a memory device includes: a first storage area configured to store data; a first sense amplifier; a first data latch; a first selector configured to select either connection between the first data latch and the first sense amplifier or connection between the first data latch and another sense amplifier; and a second selector configured to select either connection between the first storage area and the first sense amplifier or connection between another storage area and the first sense amplifier.. .
Kabushiki Kaisha Toshiba

Storage device, memory device and semiconductor device

According to one embodiment, a storage device includes a memory device including a memory cell configured to hold data, an output buffer configured to output the data, and a circuit configured to generate a reference voltage; and a controller device including an input buffer. The data from the output buffer is input into one input terminal of the input buffer and the reference voltage from the circuit is input into the other input terminal of the input buffer..
Kabushiki Kaisha Toshiba

Memory devices with strap cells

A device includes a memory array, a first data line, and a second data line. The memory array includes a first strap cell, a first sub-bank, and a second sub-bank, in which the first strap cell is disposed between the first sub-bank and the second sub-bank.
Taiwan Semiconductor Manufacturing Co., Ltd.





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