|| List of recent Memory Device-related patents
| Software update methodology|
Software update information is communicated to a network appliance either across a network or from a local memory device. The software update information includes kernel data, application data, or indicator data.
| Multi-element memory device with power control for individual elements|
A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value.
| Selective precharge for power savings|
Embodiments of a memory device are disclosed that may allow for detecting the opportunity for energy savings and implementing the energy savings for each access to the memory device. The memory device may include a plurality of columns, an address comparator, and a timing and control circuit.
| System, method, and apparatus for data, data structure, or encryption key cognition incorporating autonomous security protection|
A system, method, and apparatus for securing a date file or a cognitive encryption key data file stored in a storage medium or memory device. The date file or encryption key file having stored instructions for an embedded autonomous executable program which is executed each time there is an attempt to access, control, or manipulate the encryption key file includes querying a user of the date file or encryption key file, the user environment of the date file or encryption key file, or both, for information required for analyzing a computational environment in relation to required security parameters for the cognitive date file or encryption key file.
| Page miss handler including wear leveling logic|
Embodiments of the invention describe an apparatus, system and method for utilizing a page miss handler having wear leveling logic/modules for memory devices. Embodiments of the invention may track an amount of writes directed towards cells of a memory device, and determine whether a linear address specified by a system write transaction is included in a translation-lookaside buffer (tlb).
| Host controlled enablement of automatic background operations in a memory device|
A host that is coupled to a memory device is configured to read a status register of the memory device to determine if the memory device supports host controlled enablement of automatic background operations. The memory device responds to the host regarding whether the memory device supports host controlled enablement of automatic background operations.
| Dram memory interface|
It is proposed a dram memory interface (40) for transmitting signals between a memory controller device (50) and a dram memory device (52). The dram memory interface comprises: data lines (44) for transmitting data signals; one or more control line(s) for transmitting control signals; one or more address line(s) for transmitting address signals; for each line, a transmitter device (41) connected to a first end of the line and a receiver device (42) connected to a second end of the line; wherein: each line is a single ended line wherein a signal transmitted on the line is referenced to a first reference voltage line (46); and —each line has an termination (z1, z2) on both the first and second ends of the line by connecting a first impedance (z1) to the first end of the line and a second impedance (z2) to the second end of the line..
| Method and system for vicarious downloading or uploading of information|
Methods and systems for vicarious downloading or uploading of information are disclosed herein. In one embodiment, such a system involves a mobile device that includes a memory device capable of storing information or content, and at least one wireless communication component.
| Time controlled switch|
A time controlled electrical switch operable in a sabbath state and in a working day state, comprising a switching component for selectively directing the supply of electrical power, or for selectively transmitting a logical input, to a device; a memory device in which is stored local sunset information, calendar information, and predetermined rules for initiating a state changing event relating to a sabbath state and a working day state; a logical circuit in data communication with the switching component, and a time supplying device. The logical circuit is operable to transmit a signal to the switching component for initiating the state changing event in response to an instantaneous time indicated by the time supplying device and the stored local sunset information, calendar information, and predetermined rules..
| Detection of sleep apnea using respiratory signals|
A method and system for sleep apnea detection are disclosed. The method comprises detecting at least one respiratory signal and utilizing a detection algorithm to automatically detect at least one sleep apnea event from the at least one respiratory signal.
| Methods of manufacturing a semiconductor device|
A method of manufacturing a vertical type memory device includes stacking a first lower insulating layer, one layer of a lower sacrificial layer and a second lower insulating layer on a substrate, forming a stacking structure by stacking sacrificial layers and insulating layers, and etching an edge portion of the stacking structure to form a preliminary stepped shape pattern structure. The preliminary stepped shape pattern structure has a stepped shape edge portion.
| Low symmetry molecules and phosphonium salts, methods of making and devices formed there from|
Synthesis of molecules and salts is disclosed having low average symmetry and their use in many applications, including but not limited to: as electrolytes in electronic devices such as memory devices including static, permanent and dynamic random access memory, as electrolytes in energy storage devices such as batteries, electrochemical double layer capacitors (edlcs) or supercapacitors or ultracapacitors, electrolytic capacitors, as electrolytes in dye-sensitized solar cells (dsscs), as electrolytes in fuel cells, as a heat transfer medium, high temperature reaction and/or extraction media, among other applications. In particular, synthesis methods and processes to form molecules and salts having low average symmetry using mixed grignard reagents are disclosed..
| Methods and systems for chip-to-chip communication with reduced simultaneous switching noise|
Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated simultaneous switching output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency.
| System and method of performing power on reset for memory array circuits|
The disclosure relates to an apparatus for deactivating one or more predecoded address lines of a memory circuit in response to one or more of the predecoded address lines being activated upon powering on of at least a portion of the apparatus. In particular, the apparatus includes a memory device; an address predecoder configured to activate one or more of a plurality of predecoded address lines based on an input address, wherein the plurality of predecoded address lines are coupled to the memory device for accessing one or more memory cells associated with the one or more activated predecoded address lines; and a power-on-reset circuit configured to deactivate one or more of the predecoded address lines in response to the one or more of the predecoded address lines being activated upon powering on the at least portion of the apparatus..
| Circuit for controlling sense amplifier source node in semiconductor memory device and controlling method thereof|
Provided is a bit line sense amplifier source node control circuit of a semiconductor memory device. The sense amplifier source node control circuit may include a source driver connected between a source node of a sense amplifier and a sense amplifier driving signal line, for driving the source node of the sense amplifier to a set voltage level.
| Variable pre-charge levels for improved cell stability|
Embodiments of a memory device are disclosed that may allow for multiple pre-charge voltages. The memory device may include a plurality of data lines, and a plurality of pre-charge circuits.
| Redundancy circuit and semiconductor memory device including the same|
A redundancy circuit includes a redundancy decoder, a fuse array, and a decoder. The redundancy decoder decodes a redundancy enable signal generated when an address of a defective cell matches an input address.
| Memory core and semiconductor memory device including the same|
A semiconductor device may include a first memory cell connected to a bit-line and a first word-line, a second memory cell connected to a complementary bit-line and a second word-line, and an equalizer. The equalizer may be configured to transition a voltage of the bit-line and the complementary bit-line from a first voltage to a second voltage different from the first voltage at a first time period when the bit-line and complementary bit line are floating, and to transition the voltage of at least one of the bit-line and the complementary bit-line from the second voltage to a third voltage at a second time period after the first time period when the bit-line and complementary bit line are floating, the third voltage being different from the first and second voltages..
| Capacitor structures having improved area efficiency|
Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric material spacing apart the conductive structures may be adjusted to provide optimization of capacitance and voltage threshold.
| Method of storing data in nonvolatile memory device and method of testing nonvolatile memory device|
A method of storing data in a nonvolatile memory device comprises performing a program operation on target memory cells among multiple memory cells, performing a first verify operation to determine whether the target memory cells are in a program pass state or a program fail state, and as a consequence of determining that the target memory cells are in the program pass state, performing a second verify operation to determine whether the target memory cells exhibit a program error symptom.. .
| Data path integrity verification|
Methods and memories for verifying data path integrity are provided. In one such method, a first set of data are read from a first register of a memory device while a second set of data are written to an array of the memory device.
| Memory system and method of operation thereof|
A method of operating a memory system including a non-volatile memory device and a memory controller controlling the non-volatile memory device, includes reading data from a memory cell array in a unit of a page which includes a plurality of sectors; performing error correction decoding on the read data in a unit of a sector of the page; selecting at least one target sector which includes at least one uncorrectable error and selecting at least one pass sector wherein all errors of the pass sector are correctable by the error correction decoding; inhibiting precharging of bit-lines connected to the at least one pass sector while precharging target bit lines connected to the at least one target sector; and performing a read retry operation for data in the at least one target sector.. .
| Selecting memory cells|
A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section.
| Memory cell and memory device having the same|
A memory cell includes a metal oxide semiconductor (mos) capacitor including a gate coupled to a storage node and an electrode coupled to a synchronization control line. The mos capacitor adds a coupling voltage to the gate based on a change in voltage on the synchronization control line.
| Nonvolatile memory device using variable resistive element and memory system having the same|
A nonvolatile memory device, which has an improved read reliability through a refresh operation, and a memory system, are provided. The nonvolatile memory device includes a resistive memory cell, a reference resistor corresponding to the resistive memory cell, a reference sense amplifier electrically connected to the reference resistor and configured to change a transition time of an output value of the reference resistor, and a refresh request signal generator configured to output the refresh request signal for the resistive memory cell when the transition time of an output value of the reference resistor is in a preset refresh requiring period..
| Integrated circuit 3d phase change memory array and manufacturing method|
A 3d phase change memory device can store multiple bits per cell represented by a plurality of non-overlapping ranges of resistance all of which are established by different resistance ranges corresponding to respective amorphous phase thickness of the phase change memory material. An array of access devices can underlie a plurality of conductive layers, separated from each other and from the array of access devices by insulating layers.
| Content addressable memory device having electrically floating body transistor|
A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node.
| Pad structures and wiring structures in a vertical type semiconductor device|
Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper surface of an edge portion, and a second conductive line having s second line shape and being spaced apart from the first conductive line and provided on the first conductive line. An end portion of the first conductive line is extended to a first position.
| Vertical type semiconductor devices|
A vertical type semiconductor device includes first and second word line structures that include first and second word lines. The word lines surround a plurality of pillar structures, which are provided to connect the word lines to corresponding string select lines.
| Non-volatile memory devices having reduced susceptibility to leakage of stored charges and methods of forming same|
Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode.
| Nonvolatile memory devices with aligned trench isolation regions|
A nonvolatile memory device includes a substrate, an elongate isolation region including a field insulation film disposed in a trench in the substrate, and a word line crossing the insulation region and including a tunneling insulation layer on an active region of the substrate adjacent the isolation region, a charge storage layer on the tunneling insulation layer and a blocking insulation layer on the charge storage layer. A first plane index of a bottom surface of the trench has a first interface trap density and a second plane index of a sidewall of the trench has a second interface trap density equal to or less than the first interface trap density.
| Nonvolatile memory element, nonvolatile memory device, nonvolatile memory element manufacturing method, and nonvolatile memory device manufacturing method|
A nonvolatile memory element including: a first electrode; a second electrode; a variable resistance layer that is between the first electrode and the second electrode and includes, as stacked layers, a first variable resistance layer connected to the first electrode and a second variable resistance layer connected to the second electrode; and a side wall protecting layer that has oxygen barrier properties and covers a side surface of the variable resistance layer. The first variable resistance layer includes a first metal oxide and a third metal oxide formed around the first metal oxide and having an oxygen deficiency lower than that of the first metal oxide, and the second variable resistance layer includes a second metal oxide having an oxygen deficiency lower than that of the first metal oxide..
According to one embodiment, a memory device includes a memory unit including a first subunit and a second subunit, a code encoding unit configured to calculate first redundant data based on first write data and second redundant data based on second write data, and a control unit configured to cause the first write data and the first redundant data to be written in the first subunit and the second write data and the second redundant data to be written in the second subunit. The control unit is configured to control the code encoding unit to start calculation of the second redundant data after all of the writing steps for writing the first write data and the first redundant data have been carried out..
|Memory testing with selective use of an error correction code decoder|
A method includes directing an access of a memory location of a memory device to an error correction code (ecc) decoder in response to receiving a test activation request indicating the memory location. The method also includes writing a test pattern to the memory location and reading a value from the memory location.
|Enhanced dynamic memory management with intelligent current/power consumption minimization|
A low-power state current/power consumption for each volatile memory device in a plurality of volatile memory devices is obtained. Data is copied from a first set of the volatile memory devices to a second set of the volatile memory devices, where the second set of volatile memory devices has a lower current/power consumption than the first set of volatile memory devices.
|Line termination methods and apparatus|
Methods and apparatus for termination of signal lines coupled to a number of memory devices are disclosed. One such method includes adjusting an input impedance of one or more terminals of an interface of a memory device in response to the memory device receiving a particular address.
|Memory device having an adaptable number of open rows|
A memory device comprises a memory array, at least one row address buffer, a set of row data buffers, a row decoder, an array of sense amplifiers, and a demultiplexer. The memory array comprises data elements organized into rows and columns.
|Block or page lock features in serial interface memory|
Embodiments are provided for protecting boot block space in a memory device. Such a memory device may include a memory array having a protected portion and a serial interface controller.
|On-chip traffic prioritization in memory|
According to one embodiment, a memory device is provided. The memory device includes a processing element coupled to a crossbar interconnect.
|On-chip traffic prioritization in memory|
According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to a memory controller in the memory device associated with the memory access request.
|System on chip including memory management unit and memory address translation method thereof|
A system on chip (soc) including a memory management unit (mmu) and a memory address translation method thereof are provided. The soc includes a master intellectual property (ip) configured to output a request corresponding to each of a plurality of working sets; an mmu module comprising a plurality of mmus, each of which is allocated for one of the working sets and translates virtual addresses corresponding to the request into physical addresses; a first bus interconnect configured to connect the mmu module with a memory device and to transmit the request, on which address translation has been performed in at least one of the mmus, to the memory device; and a second bus interconnect configured to connect the master ip with the mmu module and to allocate one of the mmus for each of the working sets..
|Robust and secure memory subsystem|
The present disclosure is generally directed to a more robust memory subsystem having a an improved architecture for managing a memory space. In one embodiment, a method is provided that includes receiving a memory access request from a memory controller and attempting to access the requested data from a first level of memory maintained on the memory device that contains the map cache.
|Non-volatile configuration for serial non-volatile memory|
Example embodiments for configuring a serial non-volatile memory device may comprise a non-volatile configuration register to store a configuration value received from the processor, the configuration value to specify one or more attributes of a memory access operation. The configuration value may be read at least in part in response to power being applied to the memory device..
|Scalable memory system|
A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign.
|Maintaining i/o priority and i/o sorting|
Multiple variants of a data processing system, which maintains i/o priority from the time a process makes an i/o request until the hardware services that request, will be described. In one embodiment, a data processing system has one or more processors having one or more processor cores, which execute an operating system and one or more applications of the data processing system.
|System and method for customized prompting|
A method for providing an audible prompt to a user within a vehicle. The method includes retrieving one or more data files from a memory device.
|Translation quality quantifying apparatus and method|
A system for automating the quality evaluation of a translation. The system may include a computer having a processor and memory device operably connected to one another.
|Passive interface for an electronic memory device|
A passive interface for connecting an electronic memory device to an exterior circuit is provided. The passive interface includes a signal connection point, a power connection point and a ground connection point on an electronic memory device.
|Portable biometric lighter|
A portable biometric lighter device (100) generally involving a control unit (210), a biometric sensor, such as a fingerprint sensor (140), wherein the biometric sensor is configured to scan a biometric data of a user and is operably coupled to the control unit (210), and an ignition element, wherein the ignition element is activated by the control unit (210) upon a match of the scanned biometric data of the user and a biometric data of an authorized user that is stored in a memory device.. .
|Adaptive voltage input to a charge pump|
A memory subsystem includes an adaptive output voltage to provide a voltage based on a power profile of a memory device of the memory subsystem. A charge pump increases the voltage to a level needed to write data to the memory device.
|Stacked memory device, memory system including the same and method for operating the same|
A stacked memory device includes a plurality of interconnected memory chips and a controller to control the plurality of memory chips to perform refresh operations during non-overlapping time periods. Each memory chip includes a plurality of ranks, and each rank includes at least one memory bank.
|Multi-port memory device with serial input/output interface|
A multi-port memory device includes a plurality of serial i/o data pads for providing a serial input/output (i/o) data communication; a plurality of ports for performing the serial i/o data communication with external devices through the serial i/o data pads; a plurality of banks for performing a parallel i/o data communication with the ports; a plurality of first data buses for transferring first signals from the ports to the banks; a plurality of second data buses for transferring second signals from the banks to the ports; and a switching unit for connecting the first data buses with the second data buses in response to a control signal.. .
|Semiconductor memory device|
According to one embodiment, a semiconductor memory device includes first hookup transistors connected to word lines, a first dummy hookup transistor connected to first dummy word line, and a second dummy hookup transistor connected to second dummy word line. A group of hookup transistors formed by the first hookup transistors, the first dummy hookup transistor, and the second dummy hookup transistor is aligned on either of one row and rows.
|Nonvolatile memory with split substrate select gates and heirarchical bitline configuration|
Generally, the present disclosure provides a non-volatile memory device having a hierarchical bitline structure for preventing erase voltages applied to one group of memory cells of the memory array from leaking to other groups in which erasure is not required. Local bitlines are coupled to the memory cells of each group of memory cells.
|P-channel 3d memory array|
A p-channel flash memory device including a 3d nand array has excellent performance characteristics. Techniques for operating 3d, p-channel nand arrays include selective programming, selective (bit) erase, and block erase.
|Nonvolatile memory device and read method thereof|
A nonvolatile memory device is provided which includes a main area including main cells connected to word lines and main bit lines; a reference area including reference cells connected to the word lines and reference bit lines and programmed using the same write condition as that of the main area; a reference sense amplifier circuit configured to read data written at the reference area through the reference bit lines at a read operation; and control logic configured to control the reference sense amplifier circuit such that data written at the reference area is shifted with a weight scheme and then read, the data written at the reference area being used as a read reference value of the main area at a read operation.. .
|Programmable and flexible reference cell selection method for memory devices|
Systems, methods, and computer program products for programmable reference cell selection for flash memory are disclosed. An exemplary system includes an array of interconnected cells and a flexible decoder.
|Circuit for and method of receiving data to control the operation of a configurable light timer|
A circuit in a configurable light timer for receiving data to control the operation of the configurable light timer is described. The circuit comprises an input portion coupled to receive first data from a portable memory device by way of a connector on the configurable light timer; and a data transceiver coupled to receive wireless communication signals according to a wireless communication protocol, the wireless communication signals comprising second data for implementing the configurable light timer; wherein the second data coupled to the configurable light timer by way of the wireless communication link comprises timing characterization data.
|Magnetic memory devices including magnetic layers separated by tunnel barriers|
A magnetic memory device may include a first vertical magnetic layer, a non-magnetic layer on the first vertical magnetic layer, and a first junction magnetic layer on the non-magnetic layer, with the non-magnetic layer being between the first vertical magnetic layer and the first junction magnetic layer. A tunnel barrier may be on the first junction magnetic layer, with the first junction magnetic layer being between the non-magnetic layer and the tunnel barrier.
|Magnetic memory device and method of manufacturing the same|
A magnetic memory with a memory layer having magnetization, the direction of magnetization of which changes according to information recorded therein; a reference layer having a fixed magnetization against which magnetization of the memory layer can be compared; a nonmagnetization layer between the memory layer and the reference layer; and an electrode on one side of the memory layer facing away from the reference layer, wherein, the memory device memorizes the information by reversal of the magnetization of the memory layer by a spin torque generated when a current flows between the memory layer, the nonmagnetization layer and the reference layer, and a heat conductivity of a center portion of the electrode is lower than a heat conductivity of surroundings thereof. The memory and reference preferably have vertical magnetizations..
|Semiconductor memory device|
A semiconductor memory device has a memory cell array having memory cells, each including first and second conduction type transistors, a peripheral circuit having the first and second conduction type transistors, a first conduction type memory cell array well region within the memory cell array region, a second conduction type memory cell array well region within the first conduction type memory cell array well region, a first conduction type peripheral circuit well region within the peripheral circuit region, a second conduction type peripheral circuit well region within the first conduction type peripheral circuit well region, and a second conduction type isolation region between the first conduction type memory cell array well region and the first conduction type peripheral circuit well region. At least a portion of first conduction type transistors of first conduction type transistors of the peripheral circuit is formed in the second conduction type isolation region..
|Semiconductor memory device|
A semiconductor memory device has a memory cell array with memory cells, each including first and second conduction type transistors, column-side peripheral circuits disposed with the same row-direction interval as the memory cells, a first conduction type well region formed within the memory cell array, a second conduction type well region formed within the first conduction type well region and is disposed separately in the row direction, a second conduction type well contact region disposed extending in the row direction among the memory cells, a first conduction type well contact region disposed extending in the column direction among the memory cells, a column-side peripheral contact region, a first conduction type back gate voltage line connecting to the first conduction type well region; and a second conduction type back gate voltage line connecting to the second conduction type well.. .
|Memory device and method of fabricating thereof|
Subject matter disclosed herein relates to a process flow to form a gate structure of a memory device.. .
|Low temperature p+ polycrystalline silicon material for non-volatile memory device|
A method of forming a non-volatile memory device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region of the substrate.
|Personalized vehicle climate control|
A climate control system includes a blower, a memory device, a user interface device, and a processor. The memory device stores a default value associated with a speed of the blower.
|Error detection and correction scheme for a memory device|
An embodiment of a method of operating a memory device includes reading data from a memory array into a data buffer, checking the data using a first checker, checking the data using a second checker, and when an error is detected by the first checker and the error is not detected by the second checker returning the data to the memory array from the data buffer.. .
|Nonvolatile memory devices with age-based variability of read operations and methods of operating same|
Integrated circuit memory systems and methods include comparing a number of erase cycles of a memory block corresponding to a read request to a first value and reading data stored in the memory block according to a first read condition corresponding to a first reliability improvement operation when the number of erase cycles of the memory block is less than the first value. An error of the data read according to the first read condition may be corrected using an error correction code (ecc) when the error of the data read according to the first read condition is correctable..
|Memory devices and systems configured to adjust a size of an ecc coverage area|
Memory devices and systems having an array of memory cells arranged in a plurality of sectors and a plurality of ecc coverage areas, and control circuitry configured to adjust a size of one or more of the ecc coverage areas.. .
|Memory error detection|
Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller.
|Method of detecting an error of a multi-time programmable operation, and organic light emitting display device employing the same|
A method of detecting an error of a multi-time programmable (mtp) operation in which each gamma-offset and each header-bit at predetermined reference gray-levels are written in a mtp memory device while the mtp operation is performed on a pixel circuit, the each header-bit indicating whether or not the each gamma-offset is written in the mtp memory device, and it is detected whether or not the mtp operation is performed on the pixel circuit based on a logical operation between the header-bits at the predetermined reference gray-levels read from the mtp memory device when the mtp operation is finished on the pixel circuit.. .
|Memory subsystem performance based on in-system weak bit detection|
A memory subsystem can test a memory device in situ, testing the performance of parameters of operation the device in the system it is built into during production. Thus, the system can detect the specific values that will work for one or more operating parameters for the memory device in actual runtime.
|Memory devices, and systems and methods for verifying secure data storage|
A memory device includes an input/output (i/o) interface, a secure logic for receiving a storage verifying command including an expected value of secure data via the i/o interface, an i/o logic for receiving an input request for inputting user data into the memory device and/or an output request for outputting user data therefrom and perform one of the input request and/or the output request, and a memory unit including a secure area, accessible by the secure logic, for storing the secure data and a normal area, accessible by the i/o logic, for storing the user data. The secure logic reads the secure data from the secure area in response to the input of the storage verifying command and outputs a storage verifying result to the external device, without outputting the secure data to the external device, according to whether the secure data expected value is identical with the secure data..
|Sub-block based wear leveling|
Embodiments of the invention describe an apparatus, system and method for sub-block based wear leveling for memory devices. Embodiments of the invention may receive a write request to a physical memory address including a physical block address and a physical sub-block address.
|Semiconductor memory device and operating method for the same|
Provided is a semiconductor memory device that may efficiently map an internal address used inside the semiconductor memory device in response to an external address that is applied from the outside of the semiconductor memory device. The semiconductor memory device may include a memory cell array configured to include a first main cell array, a first spare cell array, a second main cell array, and a second spare cell array each of which has internal cells that are selected in response to an internal address, and an address mapping unit configured to map external address as the internal address when the external address designates the first main and spare cell arrays, and to operate calculation with a given value and the external address and to map the calculation result value as the internal address when the external address designates the second main and spare cell arrays..
|Methods and apparatus for compressed and compacted virtual memory|
A method and an apparatus for a memory device including a dynamically updated portion of compressed memory for a virtual memory are described. The memory device can include an uncompressed portion of memory separate from the compressed portion of memory.
|High read block clustering at deduplication layer|
Methods, systems, and computer program products are provided for deduplicating data mapping a plurality of file blocks of selected data to a plurality of logical blocks, deduplicating the plurality of logical blocks to thereby associate each logical block with a corresponding physical block of a plurality of physical blocks located on a physical memory device, two or more of the corresponding physical blocks being non-contiguous with each other, determining whether one or more of the corresponding physical blocks are one or more frequently accessed physical blocks being accessed at a frequency above a threshold frequency and being referred to by a common set of applications, and relocating data stored at the one or more frequently accessed physical blocks to different ones of the plurality of physical blocks, the different ones of the plurality of physical blocks being physically contiguous.. .
|Semiconductor memory device|
A semiconductor memory device includes a memory array including memory blocks stacked in a plurality of layers over a substrate, first lines coupling word lines of memory blocks arranged in even-numbered layers, and second lines coupling word lines of memory blocks arranged in odd-numbered layers.. .
|Semiconductor memory device|
A semiconductor memory device includes stacked memory strings in which at least some adjacent memory strings share a common source line. During a read operation for a selected memory string, a first current path is formed from a bit line of the selected memory string to the common source line through the selected memory string.
|Refresh rate performance based on in-system weak bit detection|
A memory subsystem can test a memory device in situ, testing the performance of the device in the system it is built into during production. Thus, the refresh rate can be adjusted specific to the memory device(s) of a specific system, rather than defaulting to a refresh frequency specified by a standard for the memory device(s).
|Throttling support for row-hammer counters|
Throttling of memory access commands. Accesses to rows of a memory device are monitored for a timeframe.
|Memory device and a memory module having the same|
A memory device is provided. The memory device includes a plurality of memory chips, and a buffer chip connected to the plurality of memory chips.
|Memory device and memory system having the same|
A memory device includes a memory cell array, a multi-purpose register (mpr) and a control unit. The memory cell array includes a plurality of memory blocks.
|Training for mapping swizzled data to command/address signals|
Data pin mapping and delay training techniques. Valid values are detected on a command/address (ca) bus at a memory device.
|Method for performing data shaping, and associated memory device and controller thereof|
A method for performing data shaping is applied to a controller of a flash memory, where the flash memory includes a plurality of blocks. The method includes: performing a program optimization operation according to original data and a plurality of shaping codes, in order to generate trace back information corresponding to a trellis diagram and utilize the trace back information as side information; and dynamically selecting at least one shaping code from the shaping codes according to the side information to perform data shaping on the original data..
|Execute-in-place mode configuration for serial non-volatile memory|
Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store an execute-in-place mode value that may be read at least in part in response to power being applied to the memory device.. .
|Solid state storage element and method|
A method and system for storing and retrieving data using flash memory devices. One example system includes an apparatus within a flash memory configuration.
|Memory modules and memory systems|
A memory module includes a plurality of memory devices and a buffer chip. The buffer chip manages the memory devices.
|Flash memory using virtual physical addresses|
A system and method for using virtual physical addresses in a non-volatile memory device are disclosed. The physical layout of the non-volatile memory device may have physical die that are not a power-of-2 in number.
|Memory system and driving method thereof|
A memory system includes first and second memory devices, a memory controller configured to control the second memory device, to store a request signal to access the first memory device, and to generate an interrupt signal, and a host configured to receive the request signal in response to the interrupt signal.. .
|Method and system for changing bus direction in memory systems|
A method including sorting read/write commands initiated by a memory controller based upon a destination page within a memory device. The read/write commands having a highest priority level are determined.