Images List Premium Download Classic

Memory Chip

Memory Chip-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


loading
Dimm dram memory chips quick optical data erasure after power cycling
June 14, 2018 - N°20180166116

Quick optical dram reset and data erasure can be performed during power down (power cycling) or chip cooling and removal from the socket. In this way cold boot attacks on dram secret information are prevented using simple and cheap embodiment.
3d spinram
Integrated Magnetoelectronics Corp.
June 14, 2018 - N°20180166113

Techniques are described that enable a high-capacity memory chip based on three-dimensional spinram cells and modules, and support electronics, at least some of which, are implemented with all-metal solid-state components.. .
Memory module including memory group
Samsung Electronics Co., Ltd.
June 14, 2018 - N°20180166105

A memory module may include a first memory group and a second memory group; and a first clock signal line and a second clock signal line via which the first clock signal and the second clock signal propagate from the buffer chip to the first memory group and the second memory group, respectively, wherein distances that the first clock signals ...
Memory Chip Patent Pack
Download + patent application PDFs
Memory Chip Patent Applications
Download + Memory Chip-related PDFs
For professional research & prior art discovery
inventor
  • + full patent PDF documents of Memory Chip-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Memory system and error correcting method of the same
Sk Hynix Inc.
June 14, 2018 - N°20180165151

An error correcting method of a memory system includes: reading data and an error correction code from a plurality of memory chips; correcting an error of the data based on the error correction code; determining whether or not a miscorrection occurs in the correcting of the error of the data; designating one memory chip among the plurality of the memory ...
Memory arrangement
Axis Ab
June 07, 2018 - N°20180158490

A memory arrangement and method to arrange memories are disclosed. The memory arrangement comprises at least two memory chips (m1, m2) arranged on a printed circuit board, pcb.
Semiconductor device and semiconductor integrated system
May 31, 2018 - N°20180151247

The semiconductor device that mounts a plurality of chips in a common package includes a logic chip having a predetermined function and a memory chip that is coupled with the logic chip and stores data. The memory chip includes a memory chip testing circuit that performs an operation test of the memory chip and a serial bus interface circuit for ...
Memory Chip Patent Pack
Download + patent application PDFs
Memory Chip Patent Applications
Download + Memory Chip-related PDFs
For professional research & prior art discovery
inventor
  • + full patent PDF documents of Memory Chip-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Storage system
Hitachi, Ltd.
May 31, 2018 - N°20180150233

A storage system according to an embodiment of the present invention includes a storage device and a storage controller having a memory chip with a magneto-resistant element as a memory element, a memory device having a memory controller for controlling the memory chip, and a processor. The processor may be configured to manage a storage are of the memory chip ...
Image sensor package
Samsung Electronics Co., Ltd.
May 24, 2018 - N°20180145104

An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip.
Multi protocol communication switch apparatus
Psimast,inc
May 24, 2018 - N°20180143930

A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit ethernet interface provided by protocol processor integrated as part of the chip.
Image sensor package
Samsung Electronics Co., Ltd.
May 17, 2018 - N°20180138225

An image sensor package includes an image sensor chip, a logic chip, and a memory chip structure that are vertically stacked. The image sensor chip includes a pixel array and an interconnection structure that receives a power voltage, ground voltage, or signals.
Image processing device and control method therefor
Canon Kabushiki Kaisha
May 17, 2018 - N°20180138153

An image processing device includes: an integrated circuit chip arranged on a substrate to perform processing on image data; a first memory chip arranged adjacent to the integrated circuit chip on the substrate and connected to the integrated circuit chip; and a second memory chip stacked on the integrated circuit chip and connected to the integrated circuit chip, wherein the ...
Increased redundancy in multi-device memory package to improve reliability
Intel Corporation
May 17, 2018 - N°20180137005

In a memory system a multichip memory provides data redundancy for error recovery. The multichip memory can be an integrated circuit package with multiple memory dies or memory devices integrated with a common package.
Memory system with selective access to first and second memories
Toshiba Memory Corporation
May 10, 2018 - N°20180129420

A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an mpu that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus ...
Memory Chip Patent Pack
Download + patent application PDFs
Memory Chip Patent Applications
Download + Memory Chip-related PDFs
For professional research & prior art discovery
inventor
  • + full patent PDF documents of Memory Chip-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Memory package, memory module including the same, and operation method of memory package
April 19, 2018 - N°20180108383

Disclosed is a memory package. The memory package includes a nonvolatile memory chip, a volatile memory chip of which an access speed is faster than an access speed of the nonvolatile memory chip, and a logic chip for performing a refresh operation about the volatile memory chip in response to a refresh command from an external device, and migrating at ...
Fan-out semiconductor package
Samsung Electro-mechanics Co., Ltd.
April 12, 2018 - N°20180102332

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a processor chip disposed in the through-hole; a memory chip disposed in the through-hole and including a plurality of dies stacked on each other; an encapsulant encapsulating at least portions of the first interconnection member, the memory chip, and the processor chip; and a second interconnection member disposed ...
Memory module, memory controller and systems responsive to memory chip read fail information and related ...
April 12, 2018 - N°20180101424

A memory module for reporting information about a fail in chip units, an operation of a memory module, and an operation of a memory controller are provided. The memory module includes: first to mth memory chips (where m is an integer that is equal to or greater than 2) mounted on a module board and storing data, and an (m+1)th ...
Memory system that carries out temperature-based access to a memory chip
Toshiba Memory Corporation
March 29, 2018 - N°20180090218

A memory system is connectable to a host and comprises a memory chip including a nonvolatile semiconductor memory cell array, a memory controller, a first temperature sensor positioned to measure a first temperature, which is representative of a temperature of the memory controller, and a second temperature sensor positioned to measure a second temperature, which is representative of a temperature ...
Securely binding between memory chip and host
Winbond Electronics Corporation
March 22, 2018 - N°20180081827

A memory system includes an interface, a non-volatile memory and a controller. The interface is configured to communicate over an unsecured communication link with an external host.
Fan-out semiconductor package
Samsung Electro-mechanics Co., Ltd.
March 15, 2018 - N°20180076156

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a processor chip disposed in the through-hole; a memory chip disposed in the through-hole and including a plurality of dies stacked on each other; an encapsulant encapsulating at least portions of the first interconnection member, the memory chip, and the processor chip; and a second interconnection member disposed ...
Providing memory bandwidth compression in chipkill-correct memory architectures
Qualcomm Incorporated
March 15, 2018 - N°20180074893

Providing memory bandwidth compression in chipkill-correct memory architectures is disclosed. In this regard, a compressed memory controller (cmc) introduces a specified error pattern into chipkill-correct error correcting code (ecc) bits to indicate compressed data.
Memory system
Sk Hynix Inc.
March 08, 2018 - N°20180067686

A memory system includes a memory controller, a first memory module including first and second groups of first memory chips, a second memory module including first and second groups of second memory chips, and a channel including a first group of signal lines suitable for coupling the memory controller with the first memory module, and a second group of signal ...
Loading