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Memory Chip patents

      

This page is updated frequently with new Memory Chip-related patent applications.




 Optical sensors for monitoring biopharmaceutical solutions in single-use containers patent thumbnailOptical sensors for monitoring biopharmaceutical solutions in single-use containers
Disposable, pre-sterilized, and pre-calibrated, pre-validated sensor components are provided. The sensor components interact with a sensor system having disposable fluid conduit or bioreactor bag and a reusable sensor assembly.
Parker-hannifin Corporation


 Semiconductor memory device patent thumbnailSemiconductor memory device
A semiconductor memory device includes a thin-film capacitor disposed at a position facing a circuit surface of a memory chip except for a center pad region. The thin-film capacitor includes a first plane electrode, a thin-film dielectric layer, and a second plane electrode.
Noda Screen Co., Ltd.


 Memory  error correction of memory patent thumbnailMemory error correction of memory
A memory system and a method for the error correction of memory are disclosed herein. The method for the error correction of memory is performed by a memory system including a plurality of memory chips.
Wisconsin Alumni Research Foundation


 Device for the additive manufacturing of three-dimensional objects from powdery construction material patent thumbnailDevice for the additive manufacturing of three-dimensional objects from powdery construction material
A device for the additive manufacturing of three-dimensional objects from powdery construction material by introducing radiation energy, in particular a laser sintering and/or laser melting device, comprising at least one housing having a process chamber, in which process chamber a construction space or an exchangeable container having a vertically movable construction platform is arranged, to which construction platform the powdery construction material provided for solidification by radiation energy can be applied, characterized by a memory chip, which can be removed from the process chamber of the device with the exchangeable container and/or the constructed object and which can be read out by an electronic reading device and on which production data, which belong to the additive manufacturing process, and/or subsequent processing steps and/or processing stations for automatically controlling processing apparatuses and/or transport paths and/or storage positions and/or data from controlling active elements of the exchangeable container itself are stored.. .
Cl Schutzrechtsverwaltungs Gmbh


 Camera case with removable carrier, filter receiver, external battery and supplemental memory storage patent thumbnailCamera case with removable carrier, filter receiver, external battery and supplemental memory storage
The present invention is a supplemental waterproof housing that completely surrounds a camera device, and it encloses an integrated and removable supplemental external battery and supplemental memory storage inside the external housing, and provides for a mounting point for lenses, filters or adaptors and handles attached to outside to the external housing. The internal compartment of the housing encloses an inner housing that holds the camera, and allows easy connections to the removable memory chips and removable battery packs through coupling adapters, connectors and bridges, which is all integrated into and enclosed by the external housing.
Avant Technology, Inc.


 Semiconductor device with a magnetic shield patent thumbnailSemiconductor device with a magnetic shield
A semiconductor device includes a substrate, a magnetoresistive memory chip disposed on the substrate, and a sealing resin layer that seals the magnetoresistive memory chip. The magnetoresistive memory chip includes a magnetoresistive memory element layer and an organic resin layer that covers at least a portion of the magnetoresistive memory element layer and contains magnetic particles..
Kabushiki Kaisha Toshiba


 Memory card with communication function patent thumbnailMemory card with communication function
A memory card provided with a communication function has a substrate having a first mounting surface and a second mounting surface on a side opposite to the first mounting surface, a memory chip mounted on the first mounting surface or the second mounting surface, a proximity wireless communication circuit on the first mounting surface or the second mounting surface, a circuit pattern which is disposed on at least one of a first area of the first mounting surface and a second area of the second mounting surface located opposite to the first area, the substrate being between the first area and the second area, and which is connected with the memory chip and the proximity wireless communication circuit, and a chip antenna mounted on a third area of the first mounting surface or a fourth area of the second mounting surface.. .
Kabushiki Kaisha Toshiba


 Implementing magnetic memory integration with cmos driving circuits patent thumbnailImplementing magnetic memory integration with cmos driving circuits
A magnetic memory integrated with complementary metal oxide semiconductor (cmos) driving circuits and a method for implementing magnetic memory integrated with complementary metal oxide semiconductor (cmos) driving circuits for use in solid-state drives (ssds) are provided. A complementary metal oxide semiconductor (cmos) wafer is provided, and a magnetic memory is formed on top of the cmos wafer providing a functioning magnetic memory chip..
Hgst Netherlands B.v.


 Rendering system and method patent thumbnailRendering system and method
A rendering system includes: a ray generator configured to generate a ray; a memory chip configured to store information about objects in three-dimensional (3d) space; an intersection tester embedded in the memory chip and configured to perform an intersection test between the ray and the objects by using the information about the objects and information about the ray; and a shader configured to perform pixel shading based on a result of the intersection test.. .
Samsung Electronics Co., Ltd.


 Semiconductor system and controlling method thereof patent thumbnailSemiconductor system and controlling method thereof
A semiconductor system may include a controller, a buffer chip electrically coupled to the controller, and a plurality of memory chips electrically coupled to the buffer chip, each memory chip including at least one chip data terminal. The buffer chip may be configured to perform logic operations on data output from at least one pair of chip data terminals among the plurality of memory chips, and to output the logic operation results to the controller or provide the logic operation results to other chip data terminals among the plurality of memory chips other than the at least one pair of chip data terminals which output the data..
Sk Hynix Inc.


Memory system and operating method thereof

A memory system may include: a memory device including: a plurality of pages each including a plurality of memory cells coupled to a plurality of word lines and suitable for storing read data and write data requested from a host; a plurality of memory blocks each including the pages; a plurality of planes each including the memory blocks; and a plurality of memory chips each including the planes; and a controller suitable for checking the write data corresponding to a command received from the host, programming the write data to pages of memory blocks included in planes of a first memory chip, and programming first data for the write data to pages of memory blocks included in planes of a second memory chip.. .
Sk Hynix Inc.

Solid state drive apparatus

A solid state drive apparatus includes a housing having a first accommodation space and a second accommodation space; a substrate mounted in the first accommodation space, wherein at least one non-volatile memory chip is mounted on the substrate; and a heat dissipation member mounted in the second accommodation space and including an isolation barrier that defines a boundary between the second accommodation space and the first accommodation space and a plurality of fin portions that extend from the isolation barrier away from the first accommodation space, wherein a plurality of through air holes are provided in a side of the housing adjacent the second accommodation space.. .
Samsung Electronics Co., Ltd.

Flash memory controller and memory device for accessing flash memory module, and associated method

A method for accessing a flash memory module includes: sequentially writing nth-(n+k)th data to a plurality of flash memory chips of the flash memory module, and encoding the nth-(n+k)th data to generate nth-(n+k)th eccs, respectively, where the nth-(n+k) th eccs are used to correct errors of the nth-(n+k)th data, respectively, and n and k are positive integers; and writing the (n+k+1)th data to the plurality of flash memory chips of the flash memory module, and encoding the (n+k+1)th data with at least one of the nth-(n+k)th eccs to generate the (n+k+1)th ecc.. .
Silicon Motion Inc.

Read distribution in a three-dimensional stacked memory based on thermal profiles

A memory controller may receive a plurality of thermal profiles from a plurality of three-dimensional (3d)-stacked memory chips, where the plurality of thermal profiles include thermal profile data for the memory chips, where the thermal profile data includes a memory chip usage data and a location data for each of the memory chips, and where the memory chips include a first memory chip and a second memory chip. The memory controller may generate a first predicted memory chip usage data and location data by analyzing the usage data and location data of the thermal profile data.
International Business Machines Corporation

Memory chips and data protection methods

A memory chip coupled to a host includes a memory and a controller. The memory is pre-loaded with a plurality of boot images, wherein the boot images have the same content.
Via Technologies, Inc.

3d mram with through silicon vias or through silicon trenches magnetic shielding

Emerging memory chips and methods for forming an emerging memory chip are presented. For example, magnetoresistive random access memory (mram) chip magnetic shielding and vertical stacking capabilities processed at the wafer-level are disclosed.
Globalfoundries Singapore Pte. Ltd.

Mram chip magnetic shielding

Emerging memory chips and methods for forming an emerging memory chip are presented. For example, magnetic random access memory (mram) chip magnetic shielding and methods of forming a magnetic shield processed at the wafer-level are disclosed.
Globalfoundries Singapore Pte. Ltd.

Memory system and operating memory system

A memory system may include: a memory device including a plurality of pages having a plurality of memory cells coupled to a plurality of word lines and suitable for storing read data and write data requested from a host, a plurality of memory blocks each including the pages, a plurality of planes each including the memory blocks, and a plurality of memory chips each including the planes; and a controller suitable for searching map data of the read data corresponding to a read command received from the host on a basis of a plurality of segments, triggering memory chips corresponding to the map data searched through the searches of the respective segments, reading data stored in the triggered memory chips, and transferring the read data to the host.. .
Sk Hynix Inc.

Medical data card system

A system for maintaining and updating patient data that includes: a magnetic card reader; a magnetic card; a memory chip on the magnetic card, where the memory chip stores patient data; and a biometric reader attached to the magnetic card reader. Preferably, the card reader updates patient data stored in the memory chip when the magnetic card is swiped through the magnetic card reader.

Storage apparatus

A storage apparatus includes: a plurality of flash memory devices each including: a plurality of flash memory chips each including a plurality of physical blocks being data erasure units; and a flash controller configured to provide logical storage areas by associating at least one of the plurality of physical blocks with the logical storage areas; and a raid controller configured to: manage a plurality of virtual drives each including a part of the logical storage areas provided by each of the plurality of flash memory devices; and control the plurality of virtual drives as a raid group.. .
Hitachi, Ltd.

Method for manufacturing semiconductor device

When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy..

Memory module

A memory module that includes: a printed circuit board having a connecting terminal; memory chips arranged on the printed circuit board; data buffers disposed on a first surface of the printed circuit board and corresponding to the memory chips; and resistance units disposed on a second surface of the printed circuit board and corresponding to the data buffers.. .
Samsung Electronics Co., Ltd.

Method for preventing an unauthorized use of disposable biprocess components

This invention provides a system and apparatus that is able to authenticate and prevent illegal manufacturing and unauthorized operation of disposable bioprocess components. This invention utilizes a ferro-electric random access memory chip (fram) chip to store error-correctable information on a rfid tag attached to the disposable bioprocess components, where the error-correctable information is written in sequence into the memory chip, so that the redundant information can remain in the chip when the rfid tag and disposable bioprocess component is gamma-sterilized.
Ge Healthcare Biosciences Corp.

High performance persistent memory

Embodiments are generally directed to high capacity energy backed memory with off device storage. A memory device includes a circuit board; multiple memory chips that are installed on the circuit board; a controller to provide for backing up contents of the memory chips when a power loss condition is detected; a connection to a backup energy source; and a connection to a backup data storage that is separate from the memory device..
Intel Corporation

Resource management for terminal system

The present document relates to a system resource management method and device for a terminal. The method includes: partitioning a memory chip of the terminal into a customized data partition and at least one operating system partition, the customized data partition being used for storing system characteristic resource data, and the operating system partition being used for storing system general function resource data; and respectively managing the resource data of the customized data partition and the at least one operating system partition, and sharing the resource data of the customized data partition in the at least one operating system partition.
Zte Corporation

Arithmetic control device, memory system including the same, information processing device, and arithmetic control method

An arithmetic control device according to an embodiment controls arithmetic operations using a memory chip. The memory chip includes a memory cell array and a controller.
Kabushiki Kaisha Toshiba

Memory chip and stack type semiconductor apparatus including the same

A memory chip may include a plurality of channels including a plurality of memory banks and having a separate input/output interface, and each of the plurality of channels may be configured to simultaneously latch compression data groups obtained by compressing respective unit data groups outputted from the plurality of memory banks, sequentially output latched data as test read data according to a read start signal or a read end signal, and generate the read end signal which defines that final data output has ended.. .
Sk Hynix Inc.

Memory system and assembling memory system

According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores therein second information for determining an effective bit of the n-bit first information, and a control unit that determines an effective bit of the n-bit first information and an effective bit of the chip address based on the second information.. .
Kabushiki Kaisha Toshiba

Lighted door knob with lighted keyhole and lighted door frame and including motion detector and music or sounds

An illuminated doorknob and keyhole brightens when in motion. The illumination level is dependent both on the ambient light level and on the motion of the doorknob.

Magnetic shielding for mtj device or bit

Emerging memory chips and methods for forming an emerging memory chip are presented. For example, magnetic random access memory (mram) chip magnetic shielding and methods of forming a magnetic shield processed at the device-level are disclosed.
Globalfoundries Singapore Pte. Ltd.

Micro heat pipe cooling system

At least one hollow metal body with a plurality of micro heat pipes embedded in the hollow metal body is used as a heat sink to remove heat from memory chips in a memory device.. .
Corsair Memory, Inc.

Apparatus having dice to perorm refresh operations

Some embodiments include an apparatus that comprise an interface chip having an oscillator to produce an original clock signal, a first memory chip having first memory cells, and a second memory chip having second memory cells. The first memory cells may be refreshed in response to a first clock signal based on the original clock signal.
Micron Technology, Inc.

Systems and methods for data alignment in a memory system

A method may include link training a plurality of back-side lanes coupling a plurality of memory chips of a memory module to a plurality of data buffers of the memory module. The method may also include link training a plurality of front-side lanes coupling the plurality of data buffers to a memory controller.
Dell Products L.p.

Memory system having a plurality of types of memory chips and a memory controller for controlling the memory chips

A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller.
Socionext Inc.

Method and flexible raid in ssd

A solid state drive (ssd) employing a redundant array of independent disks (raid) scheme includes a flash memory chip, erasable blocks in the flash memory chip, and a flash controller. The erasable blocks are configured to store flash memory pages.
Futurewei Technologies, Inc.

Memory system and operating method thereof

A memory system includes a memory device including a plurality of memory chips, each of which includes a plurality of planes suitable for storing data and a plurality of page buffers respectively corresponding to the planes; and a controller suitable for transferring write data stored in a write buffer thereof to a first page buffer of a first chip, releasing the write buffer and a first plane corresponding to the first page buffer in the first chip after the transfer to the first page buffer, and programming the write data in the first planes after the release from the first plane.. .
Sk Hynix Inc.

Pressure scanner assemblies having replaceable sensor plates

A pressure scanner assembly having at least one replaceable sensor plate, wherein each of the replaceable sensor plates has at least one pressure sensor adapted to transmit a signal substantially indicative of a sensed pressure condition. A memory chip, which stores correction coefficients for each of the pressure sensor to compensate for thermal errors, may be installed on each of the replaceable sensor plates.
Kulite Semiconductor Products, Inc.

Waypoint generation for adaptive flash tuning

The present invention includes embodiments of systems and methods for increasing the operational efficiency and extending the estimated operational lifetime of a flash memory storage device (and its component flash memory chips, luns and blocks of flash memory) by monitoring the health of the device and its components and, in response, adaptively tuning the operating parameters of flash memory chips during their operational lifetime, as well as employing other less extreme preventive measures in the interim, via an interface that avoids the need for direct access to the test modes of the flash memory chips. In an offline characterization phase, “test chips” from a batch of recently manufactured flash memory chips are used to simulate various usage scenarios and measure the performance effects of writing and attempting to recover (read) test patterns written with different sets of operating parameters over time (simulating desired retention periods)..

Candidate generation for adaptive flash tuning

The present invention includes embodiments of systems and methods for increasing the operational efficiency and extending the estimated operational lifetime of a flash memory storage device (and its component flash memory chips, luns and blocks of flash memory) by monitoring the health of the device and its components and, in response, adaptively tuning the operating parameters of flash memory chips during their operational lifetime, as well as employing other less extreme preventive measures in the interim, via an interface that avoids the need for direct access to the test modes of the flash memory chips. In an offline characterization phase, “test chips” from a batch of recently manufactured flash memory chips are used to simulate various usage scenarios and measure the performance effects of writing and attempting to recover (read) test patterns written with different sets of operating parameters over time (simulating desired retention periods)..

Offline characterization for adaptive flash tuning

The present invention includes embodiments of systems and methods for increasing the operational efficiency and extending the estimated operational lifetime of a flash memory storage device (and its component flash memory chips, luns and blocks of flash memory) by monitoring the health of the device and its components and, in response, adaptively tuning the operating parameters of flash memory chips during their operational lifetime, as well as employing other less extreme preventive measures in the interim, via an interface that avoids the need for direct access to the test modes of the flash memory chips. In an offline characterization phase, “test chips” from a batch of recently manufactured flash memory chips are used to simulate various usage scenarios and measure the performance effects of writing and attempting to recover (read) test patterns written with different sets of operating parameters over time (simulating desired retention periods)..

Semiconductor memory apparatus, repair system therefor, and managing apparatus quality

A semiconductor memory apparatus may include a chip area configured to include one or more semiconductor memory chips. The semiconductor memory apparatus may include a repair system configured to perform a test for the chip area while the chip area is in a test mode, to determine whether the chip area has been repaired, and to generate the determination of whether the chip area has been repaired as quality information in response to a failure detection signal enabled while the chip area is in the test mode..
Sk Hynix Inc.

Gun mounted camera

A system for recording gun activity that includes: a mounting bracket; a camera, where camera is attached the mounting bracket and the mounting bracket enables attachment to a gun barrel; a camera lens directed inline with the gun barrel; a lighting mechanism within the camera directed in the line of sight of the camera lens; a microprocessor incorporated into the camera; a battery, where the battery supplies power to the camera; a memory chip, where the memory chip stores images captured by the camera; and a proximity sensor, where the proximity sensor activates the camera lens and lighting mechanism and places the camera in a record mode. The camera may further include a usb port for transmitting data to and from the camera.

Device including magnetoresistive element and memory chip

According to one embodiment, a device including a magnetoresistive element is disclosed. The device includes a substrate, a second layer provided on the substrate and including a magnetic material, and a third layer provided on a top or bottom of the second layer and including a material having a negative coefficient of thermal expansion..
Kabushiki Kaisha Toshiba

Memory system and operating method thereof

A memory system includes a memory device including a plurality of memory chips each including a plurality of memory blocks grouped as one or more super blocks, wherein the memory blocks each include a plurality of pages suitable for storing write data requested from a host, and a controller suitable for checking a size of the write data and free pages of the super blocks, determining a first super block corresponding to the checked size of the write data based on the checked free pages among the super blocks, and programming the write data in memory blocks of the first super block.. .
Sk Hynix Inc.

Reduced load memory module

An apparatus relates generally to a reduced load memory module. In such an apparatus, there is a circuit platform with a plurality of memory chips coupled to the circuit platform.
Invensas Corporation

Stack memory device and operating same

The present invention provides a stack memory device and a method for operating same. The stack memory device, according to the present invention, is provided with: a first memory chip in which first type memory cells are repeatedly arranged in row direction and column direction, and which comprises one or more cell arrays, in which a dump line is connected to the each first type memory cell; and a second memory chip in which second type memory cells are repeatedly arranged in row direction and column direction, and which comprises one or more cell arrays, in which a dump line is connected to the each second type memory cell, wherein first pads are connected to the dump lines of the first type memory cells and second pads are connected to the dump lines of the second type memory cells, the first pads and the second pads having one-to-one correspondence..
Siliconfile Technologies Inc.

Memory system

A memory system includes a memory and a controller. The memory includes a first memory chip and a second memory chip.
Kabushiki Kaisha Toshiba

System and distributed computing in non-volatile memory

A system and method are disclosed for incorporating mathematical and/or logical functionality within a memory system (such as a solid state drive (ssd)). The mathematical and/or logical functionality may comprise an arithmetic logic unit (alu).
Sandisk Technologies Llc

Multichip dual write

Identical data is written to multiple nonvolatile memory chips connected to a memory bus by sending address information to a first nonvolatile memory chip and a second nonvolatile memory chip, selecting the first and second nonvolatile memory chips, while the first nonvolatile and second nonvolatile memory chips are both selected, sending user data over the memory bus to the first and second nonvolatile memory chips in parallel, and programming the user data in the first nonvolatile memory chip and the second nonvolatile memory chip in parallel.. .
Sandisk Technologies Inc.

Dynamic approximate storage for custom applications

A memory chip for dynamic approximate storage includes an array of memory cells associated with at least two regions. The chip further includes at least one threshold register for storing values for thresholds for memory cells corresponding to each of the at least two regions; and control logic to programmatically adjust the values for the thresholds for the memory cells.
Microsoft Technology Licensing, Llc

Front/back control of integrated circuits for flash dual inline memory modules

In one implementation, flash memory chips are provided with an operating power supply voltage to substantially match a power supply voltage expected at an edge connector of a dual inline memory module. The one or more of the flash memory chips and a memory support application integrated circuit (asic) may be mounted together into a multi-chip package for integrated circuits.
Virident Systems, Inc.



Memory Chip topics:
  • Memory Chip
  • Semiconductor
  • Storage Device
  • Semiconductor Memory
  • Memory Cell
  • Volatile Memory
  • Host Computer
  • Form Factor
  • Memory Cells
  • Data Storage
  • Aspect Ratio
  • Error Correction
  • Semiconductor Device
  • Control Unit
  • Crystallin


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    This listing is a sample listing of patent applications related to Memory Chip for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Memory Chip with additional patents listed. Browse our RSS directory or Search for other possible listings.


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