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Memory Chip patents

      

This page is updated frequently with new Memory Chip-related patent applications.




 Lighted door knob with lighted keyhole and lighted door frame and including motion detector and music or sounds patent thumbnailnew patent Lighted door knob with lighted keyhole and lighted door frame and including motion detector and music or sounds
An illuminated doorknob and keyhole brightens when in motion. The illumination level is dependent both on the ambient light level and on the motion of the doorknob.

 Magnetic shielding for mtj device or bit patent thumbnailnew patent Magnetic shielding for mtj device or bit
Emerging memory chips and methods for forming an emerging memory chip are presented. For example, magnetic random access memory (mram) chip magnetic shielding and methods of forming a magnetic shield processed at the device-level are disclosed.
Globalfoundries Singapore Pte. Ltd.


 Micro heat pipe cooling system patent thumbnailnew patent Micro heat pipe cooling system
At least one hollow metal body with a plurality of micro heat pipes embedded in the hollow metal body is used as a heat sink to remove heat from memory chips in a memory device.. .
Corsair Memory, Inc.


 Apparatus having dice to perorm refresh operations patent thumbnailApparatus having dice to perorm refresh operations
Some embodiments include an apparatus that comprise an interface chip having an oscillator to produce an original clock signal, a first memory chip having first memory cells, and a second memory chip having second memory cells. The first memory cells may be refreshed in response to a first clock signal based on the original clock signal.
Micron Technology, Inc.


 Systems and methods for data alignment in a memory system patent thumbnailSystems and methods for data alignment in a memory system
A method may include link training a plurality of back-side lanes coupling a plurality of memory chips of a memory module to a plurality of data buffers of the memory module. The method may also include link training a plurality of front-side lanes coupling the plurality of data buffers to a memory controller.
Dell Products L.p.


 Memory system having a plurality of types of memory chips and a memory controller for controlling the memory chips patent thumbnailMemory system having a plurality of types of memory chips and a memory controller for controlling the memory chips
A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller.
Socionext Inc.


 Method and  flexible raid in ssd patent thumbnailMethod and flexible raid in ssd
A solid state drive (ssd) employing a redundant array of independent disks (raid) scheme includes a flash memory chip, erasable blocks in the flash memory chip, and a flash controller. The erasable blocks are configured to store flash memory pages.
Futurewei Technologies, Inc.


 Memory system and operating method thereof patent thumbnailMemory system and operating method thereof
A memory system includes a memory device including a plurality of memory chips, each of which includes a plurality of planes suitable for storing data and a plurality of page buffers respectively corresponding to the planes; and a controller suitable for transferring write data stored in a write buffer thereof to a first page buffer of a first chip, releasing the write buffer and a first plane corresponding to the first page buffer in the first chip after the transfer to the first page buffer, and programming the write data in the first planes after the release from the first plane.. .
Sk Hynix Inc.


 Pressure scanner assemblies having replaceable sensor plates patent thumbnailPressure scanner assemblies having replaceable sensor plates
A pressure scanner assembly having at least one replaceable sensor plate, wherein each of the replaceable sensor plates has at least one pressure sensor adapted to transmit a signal substantially indicative of a sensed pressure condition. A memory chip, which stores correction coefficients for each of the pressure sensor to compensate for thermal errors, may be installed on each of the replaceable sensor plates.
Kulite Semiconductor Products, Inc.


 Waypoint generation for adaptive flash tuning patent thumbnailWaypoint generation for adaptive flash tuning
The present invention includes embodiments of systems and methods for increasing the operational efficiency and extending the estimated operational lifetime of a flash memory storage device (and its component flash memory chips, luns and blocks of flash memory) by monitoring the health of the device and its components and, in response, adaptively tuning the operating parameters of flash memory chips during their operational lifetime, as well as employing other less extreme preventive measures in the interim, via an interface that avoids the need for direct access to the test modes of the flash memory chips. In an offline characterization phase, “test chips” from a batch of recently manufactured flash memory chips are used to simulate various usage scenarios and measure the performance effects of writing and attempting to recover (read) test patterns written with different sets of operating parameters over time (simulating desired retention periods)..

Candidate generation for adaptive flash tuning

The present invention includes embodiments of systems and methods for increasing the operational efficiency and extending the estimated operational lifetime of a flash memory storage device (and its component flash memory chips, luns and blocks of flash memory) by monitoring the health of the device and its components and, in response, adaptively tuning the operating parameters of flash memory chips during their operational lifetime, as well as employing other less extreme preventive measures in the interim, via an interface that avoids the need for direct access to the test modes of the flash memory chips. In an offline characterization phase, “test chips” from a batch of recently manufactured flash memory chips are used to simulate various usage scenarios and measure the performance effects of writing and attempting to recover (read) test patterns written with different sets of operating parameters over time (simulating desired retention periods)..

Offline characterization for adaptive flash tuning

The present invention includes embodiments of systems and methods for increasing the operational efficiency and extending the estimated operational lifetime of a flash memory storage device (and its component flash memory chips, luns and blocks of flash memory) by monitoring the health of the device and its components and, in response, adaptively tuning the operating parameters of flash memory chips during their operational lifetime, as well as employing other less extreme preventive measures in the interim, via an interface that avoids the need for direct access to the test modes of the flash memory chips. In an offline characterization phase, “test chips” from a batch of recently manufactured flash memory chips are used to simulate various usage scenarios and measure the performance effects of writing and attempting to recover (read) test patterns written with different sets of operating parameters over time (simulating desired retention periods)..

Semiconductor memory apparatus, repair system therefor, and managing apparatus quality

A semiconductor memory apparatus may include a chip area configured to include one or more semiconductor memory chips. The semiconductor memory apparatus may include a repair system configured to perform a test for the chip area while the chip area is in a test mode, to determine whether the chip area has been repaired, and to generate the determination of whether the chip area has been repaired as quality information in response to a failure detection signal enabled while the chip area is in the test mode..
Sk Hynix Inc.

Gun mounted camera

A system for recording gun activity that includes: a mounting bracket; a camera, where camera is attached the mounting bracket and the mounting bracket enables attachment to a gun barrel; a camera lens directed inline with the gun barrel; a lighting mechanism within the camera directed in the line of sight of the camera lens; a microprocessor incorporated into the camera; a battery, where the battery supplies power to the camera; a memory chip, where the memory chip stores images captured by the camera; and a proximity sensor, where the proximity sensor activates the camera lens and lighting mechanism and places the camera in a record mode. The camera may further include a usb port for transmitting data to and from the camera.

Device including magnetoresistive element and memory chip

According to one embodiment, a device including a magnetoresistive element is disclosed. The device includes a substrate, a second layer provided on the substrate and including a magnetic material, and a third layer provided on a top or bottom of the second layer and including a material having a negative coefficient of thermal expansion..
Kabushiki Kaisha Toshiba

Memory system and operating method thereof

A memory system includes a memory device including a plurality of memory chips each including a plurality of memory blocks grouped as one or more super blocks, wherein the memory blocks each include a plurality of pages suitable for storing write data requested from a host, and a controller suitable for checking a size of the write data and free pages of the super blocks, determining a first super block corresponding to the checked size of the write data based on the checked free pages among the super blocks, and programming the write data in memory blocks of the first super block.. .
Sk Hynix Inc.

Reduced load memory module

An apparatus relates generally to a reduced load memory module. In such an apparatus, there is a circuit platform with a plurality of memory chips coupled to the circuit platform.
Invensas Corporation

Stack memory device and operating same

The present invention provides a stack memory device and a method for operating same. The stack memory device, according to the present invention, is provided with: a first memory chip in which first type memory cells are repeatedly arranged in row direction and column direction, and which comprises one or more cell arrays, in which a dump line is connected to the each first type memory cell; and a second memory chip in which second type memory cells are repeatedly arranged in row direction and column direction, and which comprises one or more cell arrays, in which a dump line is connected to the each second type memory cell, wherein first pads are connected to the dump lines of the first type memory cells and second pads are connected to the dump lines of the second type memory cells, the first pads and the second pads having one-to-one correspondence..
Siliconfile Technologies Inc.

Memory system

A memory system includes a memory and a controller. The memory includes a first memory chip and a second memory chip.
Kabushiki Kaisha Toshiba

System and distributed computing in non-volatile memory

A system and method are disclosed for incorporating mathematical and/or logical functionality within a memory system (such as a solid state drive (ssd)). The mathematical and/or logical functionality may comprise an arithmetic logic unit (alu).
Sandisk Technologies Llc

Multichip dual write

Identical data is written to multiple nonvolatile memory chips connected to a memory bus by sending address information to a first nonvolatile memory chip and a second nonvolatile memory chip, selecting the first and second nonvolatile memory chips, while the first nonvolatile and second nonvolatile memory chips are both selected, sending user data over the memory bus to the first and second nonvolatile memory chips in parallel, and programming the user data in the first nonvolatile memory chip and the second nonvolatile memory chip in parallel.. .
Sandisk Technologies Inc.

Dynamic approximate storage for custom applications

A memory chip for dynamic approximate storage includes an array of memory cells associated with at least two regions. The chip further includes at least one threshold register for storing values for thresholds for memory cells corresponding to each of the at least two regions; and control logic to programmatically adjust the values for the thresholds for the memory cells.
Microsoft Technology Licensing, Llc

Front/back control of integrated circuits for flash dual inline memory modules

In one implementation, flash memory chips are provided with an operating power supply voltage to substantially match a power supply voltage expected at an edge connector of a dual inline memory module. The one or more of the flash memory chips and a memory support application integrated circuit (asic) may be mounted together into a multi-chip package for integrated circuits.
Virident Systems, Inc.

Extended capacity memory module with dynamic data buffers

A memory module uses dynamic data buffers for providing extended capacity for computing systems. The memory module comprises an external interface having a first set of data pins and a second set of data pins.
Rambus Inc.

Memory module with packages of stacked memory chips

An apparatus is provided that includes a plurality of array dies and at least two die interconnects. The first die interconnect is in electrical communication with a data port of a first array die and a data port of a second array die and not in electrical communication with data ports of a third array die.
Netlist, Inc.

Method for managing storage system using flash memory, and computer

To facilitate the management of a storage system that uses a flash memory as a storage area. A controller of the storage system provided with a flash memory chip manages a surplus capacity value of the flash memory chip, and transmits a value based on the surplus capacity value to a management server, on the basis of at least one of a definition of a parity group, a definition of an internal lu, and a definition of a logical unit.
Hitachi, Ltd.

Solid state memory thermal regulation

A chassis for a storage system contains a digital chamber that houses conventional electronic components and a thermal chamber that houses non-volatile solid state memory such as flash memory. A temperature regulating system monitors temperature within the digital chamber to keep the components therein below their maximum junction temperature.
Skyera, Inc.

Stack semiconductor package

A stack semiconductor package includes a first semiconductor package having a first package substrate and a first semiconductor chip mounted on the first package substrate. The first semiconductor chip includes first chip pads arranged along a side portion thereof.

Stacked memory chip having reduced input-output load, memory module and memory system including the same

A stacked memory chip includes a chip input-output pad unit, a first semiconductor die and a second semiconductor die. The chip input-output pad unit includes a chip command-address pad unit, a lower chip data pad unit and an upper chip data pad unit that are to be connected to an external device.

Memory system and operating method thereof

A memory system includes a plurality of memory chips each including memory regions and page buffers; an address table suitable for storing mapping information for mapping physical addresses and logical addresses; a target table suitable for storing sequential physical addresses and sequential logical addresses; a selective output block suitable for selecting the memory regions as pages under selection by units of a page according to a preset order, based on the sequential physical addresses, and outputting data stored in page buffers of memory chips under selection corresponding to the pages under selection; and an expected read block suitable for reading data stored in selection-expected pages, which is to be selected following the pages under selection according to the preset order, to store in page buffers of selection-expected memory chips corresponding to the selection-expected pages, while the data stored in the page buffers under selection are outputted.. .

Individual identification device, storage device, individual identification system, individual identification, and program product

An individual identification device (1) according to embodiments may identify a storage device (100) including one or more memory chips (40). The device comprises a first storage (40), a region allocator (15), and a hardware fingerprint generator (12).

Medication management health and health related facilities

A system and method for control of prescription drug packaging and dispensing machines located in an in-patient health care facility including centralized control and enhanced communication between system components. Delay and errors in processing item data in the prescription dispensing system are reduced by using concise id data incorporated into each canister memory chip and storing canister contents data elsewhere.
Cerx Pharmacy Partners, Lp

Implementing enhanced performance flash memory devices

A method and apparatus for implementing enhanced performance in a flash memory system in a computer system. A flash memory chip includes a function engine performing garbage collection and scrub operations using an internal bus for data movement, preserving i/o bandwidth.
International Business Machines Corporation

Implementing enhanced performance flash memory devices

A method and apparatus for implementing enhanced performance in a flash memory system in a computer system. A flash memory chip includes a function engine performing garbage collection and scrub operations using an internal bus for data movement, preserving i/o bandwidth.
International Business Machines Corporation

Semiconductor device having plural memory chip

A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip.
Ps4 Luxco S.a.r.l.

Address-remapped memory chip, memory module and memory system including the same

A memory chip includes a chip input-output pad unit, a plurality of semiconductor dies. The chip input-output pad unit includes a plurality of input-output pins connected to an external device and the plurality of semiconductor dies are connected commonly to the chip input-output pad unit and having a full memory capacity respectively.
Samsung Electronics Co., Ltd.

Processor apparatus with programmable multi port serial communication interconnections

A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit ethernet interface provided by protocol processor integrated as part of the chip.
Psimast, Inc

Memory system with selective access to first and second memories

A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an mpu that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.. .
Kabushiki Kaisha Toshiba

Memory system and assembling memory system

According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores therein second information for determining an effective bit of the n-bit first information, and a control unit that determines an effective bit of the n-bit first information and an effective bit of the chip address based on the second information.. .
Kabushiki Kaisha Toshiba

Semiconductor integrated circuit and driving the same

Provided is a semiconductor integrated circuit including a plurality of memory chips stacked therein, each of the memory chips may include: a pumping enable signal control unit suitable for generating a pumping enable signal in response to a power-up signal or a trigger signal received from a first adjacent memory chip, delaying the pumping enable signal by a given time, and outputting the delayed pumping enable signal to a second adjacent memory chip; and a pumping unit suitable for generating a pumping voltage by performing a pumping operation in response to the pumping enable signal.. .
Sk Hynix Inc.

A communicating with an electronic device and an electronic device locatable on or in an animal

An electronic monitoring device (20) for attaching to an animal (21) for determining a plurality of states of an animal (21). The monitoring device (20) comprises an nfc module (31) which facilitates wireless communication between a smart phone (32) and the monitoring device (20).
Dairymaster

Mirroring in three-dimensional stacked memory

A method for mirroring in three-dimensional-stacked memory includes receiving a plurality of thermal profiles from a plurality of memory chips. The method also includes ranking the plurality of memory chips in a first ranked list of memory chips as a function of the plurality of thermal profiles and forming a first group of memory chips from the plurality of memory chips based on the first ranked list of memory chips.
International Business Machines Corporation

Mirroring in three-dimensional stacked memory

A method for mirroring in three-dimensional-stacked memory includes receiving a plurality of thermal profiles from a plurality of memory chips. The method also includes ranking the plurality of memory chips in a first ranked list of memory chips as a function of the plurality of thermal profiles and forming a first group of memory chips from the plurality of memory chips based on the first ranked list of memory chips.
International Business Machines Corporation

Method and calibrating write timing in a memory system

A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation.
Rambus Inc.

Memory system and soc including linear remapper and access window

A system on chip which is connected with a plurality of memory chips includes first and second processors, a first access window, a first linear remapper, and a memory controller. The first and second processors are configured to provide an address for using the plurality of memory chips.

Multi-chip device and storing data

A multi-chip device and method for storing input data. The multi-chip device includes: a plurality of memory chips being adapted to store encoded input data, wherein each of the plurality of memory chips includes a detection unit that outputs detection information; an evaluation unit being adapted to perform an evaluation of the detection information from each of the plurality of memory chips, and to adapt the detection algorithm of any of the detection units depending on the performed evaluation; a combination unit being adapted to receive the detected bits and to combine the detected bits; and a decoding unit being adapted to output decoded data by decoding the combined detected bits.
International Business Machines Corporation

System and distributed computing in non-volatile memory

A system and method are disclosed for incorporating mathematical and/or logical functionality within a memory system (such as a solid state drive (ssd)). The mathematical and/or logical functionality may comprise an arithmetic logic unit (alu).
Sandisk Technologies Inc.

Bipolar logic gates on mos-based memory chips

A system uses both mos-based and bipolar-based decoding circuitry in an address decoder for mos-based memory. The system includes a mos-based memory, which includes an array of a plurality of memory cells configured to store data, and an address decoder including mos-based circuitry and bipolar logic circuitry.
Elwha Llc

Storage device including a plurality of nonvolatile memory chips

A storage device includes first and second nonvolatile memory groups that respectively include first and second nonvolatile memory chips, a memory controller connected to the first and second nonvolatile memory groups in common through input/output lines and at least one control line, and a group select circuit connected to the memory controller through the at least one control line and chip enable lines. The group select circuit is connected to the first and second nonvolatile memory groups through a plurality of first and second chip enable lines, respectively.
Samsung Electronics Co., Ltd.



Memory Chip topics:
  • Memory Chip
  • Semiconductor
  • Storage Device
  • Semiconductor Memory
  • Memory Cell
  • Volatile Memory
  • Host Computer
  • Form Factor
  • Memory Cells
  • Data Storage
  • Aspect Ratio
  • Error Correction
  • Semiconductor Device
  • Control Unit
  • Crystallin


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    This listing is a sample listing of patent applications related to Memory Chip for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Memory Chip with additional patents listed. Browse our RSS directory or Search for other possible listings.


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