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Memory Chip patents

      

This page is updated frequently with new Memory Chip-related patent applications.




Date/App# patent app List of recent Memory Chip-related patents
08/18/16
20160239208 
 Extended capacity memory module with dynamic data buffers patent thumbnailExtended capacity memory module with dynamic data buffers
A memory module uses dynamic data buffers for providing extended capacity for computing systems. The memory module comprises an external interface having a first set of data pins and a second set of data pins.
Rambus Inc.


08/04/16
20160225414 
 Memory module with packages of stacked memory chips patent thumbnailMemory module with packages of stacked memory chips
An apparatus is provided that includes a plurality of array dies and at least two die interconnects. The first die interconnect is in electrical communication with a data port of a first array die and a data port of a second array die and not in electrical communication with data ports of a third array die.
Netlist, Inc.


08/04/16
20160224257 
 Method for managing storage system using flash memory, and computer patent thumbnailMethod for managing storage system using flash memory, and computer
To facilitate the management of a storage system that uses a flash memory as a storage area. A controller of the storage system provided with a flash memory chip manages a surplus capacity value of the flash memory chip, and transmits a value based on the surplus capacity value to a management server, on the basis of at least one of a definition of a parity group, a definition of an internal lu, and a definition of a logical unit.
Hitachi, Ltd.


07/28/16
20160216749 
 Solid state memory thermal regulation patent thumbnailSolid state memory thermal regulation
A chassis for a storage system contains a digital chamber that houses conventional electronic components and a thermal chamber that houses non-volatile solid state memory such as flash memory. A temperature regulating system monitors temperature within the digital chamber to keep the components therein below their maximum junction temperature.
Skyera, Inc.


06/30/16
20160190109 
 Stack semiconductor package patent thumbnailStack semiconductor package
A stack semiconductor package includes a first semiconductor package having a first package substrate and a first semiconductor chip mounted on the first package substrate. The first semiconductor chip includes first chip pads arranged along a side portion thereof.

06/23/16
20160181214 
 Stacked memory chip having reduced input-output load, memory module and memory system including the same patent thumbnailStacked memory chip having reduced input-output load, memory module and memory system including the same
A stacked memory chip includes a chip input-output pad unit, a first semiconductor die and a second semiconductor die. The chip input-output pad unit includes a chip command-address pad unit, a lower chip data pad unit and an upper chip data pad unit that are to be connected to an external device.

06/23/16
20160179697 
 Memory system and operating method thereof patent thumbnailMemory system and operating method thereof
A memory system includes a plurality of memory chips each including memory regions and page buffers; an address table suitable for storing mapping information for mapping physical addresses and logical addresses; a target table suitable for storing sequential physical addresses and sequential logical addresses; a selective output block suitable for selecting the memory regions as pages under selection by units of a page according to a preset order, based on the sequential physical addresses, and outputting data stored in page buffers of memory chips under selection corresponding to the pages under selection; and an expected read block suitable for reading data stored in selection-expected pages, which is to be selected following the pages under selection according to the preset order, to store in page buffers of selection-expected memory chips corresponding to the selection-expected pages, while the data stored in the page buffers under selection are outputted.. .

06/23/16
20160179431 
 Individual identification device, storage device, individual identification system,  individual identification, and program product patent thumbnailIndividual identification device, storage device, individual identification system, individual identification, and program product
An individual identification device (1) according to embodiments may identify a storage device (100) including one or more memory chips (40). The device comprises a first storage (40), a region allocator (15), and a hardware fingerprint generator (12).

06/16/16
20160171176 
 Medication management  health and health related facilities patent thumbnailMedication management health and health related facilities
A system and method for control of prescription drug packaging and dispensing machines located in an in-patient health care facility including centralized control and enhanced communication between system components. Delay and errors in processing item data in the prescription dispensing system are reduced by using concise id data incorporated into each canister memory chip and storing canister contents data elsewhere.
Cerx Pharmacy Partners, Lp


06/16/16
20160170656 
 Implementing enhanced performance flash memory devices patent thumbnailImplementing enhanced performance flash memory devices
A method and apparatus for implementing enhanced performance in a flash memory system in a computer system. A flash memory chip includes a function engine performing garbage collection and scrub operations using an internal bus for data movement, preserving i/o bandwidth.
International Business Machines Corporation


06/16/16
20160170646 

Implementing enhanced performance flash memory devices


A method and apparatus for implementing enhanced performance in a flash memory system in a computer system. A flash memory chip includes a function engine performing garbage collection and scrub operations using an internal bus for data movement, preserving i/o bandwidth.
International Business Machines Corporation


05/26/16
20160148910 

Semiconductor device having plural memory chip


A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip.
Ps4 Luxco S.a.r.l.


05/26/16
20160148656 

Address-remapped memory chip, memory module and memory system including the same


A memory chip includes a chip input-output pad unit, a plurality of semiconductor dies. The chip input-output pad unit includes a plurality of input-output pins connected to an external device and the plurality of semiconductor dies are connected commonly to the chip input-output pad unit and having a full memory capacity respectively.
Samsung Electronics Co., Ltd.


05/26/16
20160147689 

Processor apparatus with programmable multi port serial communication interconnections


A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit ethernet interface provided by protocol processor integrated as part of the chip.
Psimast, Inc


05/26/16
20160147455 

Memory system with selective access to first and second memories


A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an mpu that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.. .
Kabushiki Kaisha Toshiba


05/19/16
20160141033 

Memory system and assembling memory system


According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores therein second information for determining an effective bit of the n-bit first information, and a control unit that determines an effective bit of the n-bit first information and an effective bit of the chip address based on the second information.. .
Kabushiki Kaisha Toshiba


05/19/16
20160141005 

Semiconductor integrated circuit and driving the same


Provided is a semiconductor integrated circuit including a plurality of memory chips stacked therein, each of the memory chips may include: a pumping enable signal control unit suitable for generating a pumping enable signal in response to a power-up signal or a trigger signal received from a first adjacent memory chip, delaying the pumping enable signal by a given time, and outputting the delayed pumping enable signal to a second adjacent memory chip; and a pumping unit suitable for generating a pumping voltage by performing a pumping operation in response to the pumping enable signal.. .
Sk Hynix Inc.


05/19/16
20160135426 

A communicating with an electronic device and an electronic device locatable on or in an animal


An electronic monitoring device (20) for attaching to an animal (21) for determining a plurality of states of an animal (21). The monitoring device (20) comprises an nfc module (31) which facilitates wireless communication between a smart phone (32) and the monitoring device (20).
Dairymaster


05/12/16
20160132409 

Mirroring in three-dimensional stacked memory


A method for mirroring in three-dimensional-stacked memory includes receiving a plurality of thermal profiles from a plurality of memory chips. The method also includes ranking the plurality of memory chips in a first ranked list of memory chips as a function of the plurality of thermal profiles and forming a first group of memory chips from the plurality of memory chips based on the first ranked list of memory chips.
International Business Machines Corporation


05/12/16
20160132408 

Mirroring in three-dimensional stacked memory


A method for mirroring in three-dimensional-stacked memory includes receiving a plurality of thermal profiles from a plurality of memory chips. The method also includes ranking the plurality of memory chips in a first ranked list of memory chips as a function of the plurality of thermal profiles and forming a first group of memory chips from the plurality of memory chips based on the first ranked list of memory chips.
International Business Machines Corporation


05/05/16
20160125930 

Method and calibrating write timing in a memory system


A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation.
Rambus Inc.


05/05/16
20160124851 

Memory system and soc including linear remapper and access window


A system on chip which is connected with a plurality of memory chips includes first and second processors, a first access window, a first linear remapper, and a memory controller. The first and second processors are configured to provide an address for using the plurality of memory chips.

05/05/16
20160124807 

Multi-chip device and storing data


A multi-chip device and method for storing input data. The multi-chip device includes: a plurality of memory chips being adapted to store encoded input data, wherein each of the plurality of memory chips includes a detection unit that outputs detection information; an evaluation unit being adapted to perform an evaluation of the detection information from each of the plurality of memory chips, and to adapt the detection algorithm of any of the detection units depending on the performed evaluation; a combination unit being adapted to receive the detected bits and to combine the detected bits; and a decoding unit being adapted to output decoded data by decoding the combined detected bits.
International Business Machines Corporation


05/05/16
20160124654 

System and distributed computing in non-volatile memory


A system and method are disclosed for incorporating mathematical and/or logical functionality within a memory system (such as a solid state drive (ssd)). The mathematical and/or logical functionality may comprise an arithmetic logic unit (alu).
Sandisk Technologies Inc.


04/28/16
20160118097 

Bipolar logic gates on mos-based memory chips


A system uses both mos-based and bipolar-based decoding circuitry in an address decoder for mos-based memory. The system includes a mos-based memory, which includes an array of a plurality of memory cells configured to store data, and an address decoder including mos-based circuitry and bipolar logic circuitry.
Elwha Llc


04/28/16
20160118088 

Storage device including a plurality of nonvolatile memory chips


A storage device includes first and second nonvolatile memory groups that respectively include first and second nonvolatile memory chips, a memory controller connected to the first and second nonvolatile memory groups in common through input/output lines and at least one control line, and a group select circuit connected to the memory controller through the at least one control line and chip enable lines. The group select circuit is connected to the first and second nonvolatile memory groups through a plurality of first and second chip enable lines, respectively.
Samsung Electronics Co., Ltd.


04/28/16
20160117264 

Systems and methods for preventing data remanence in memory


A system for preventing data remanence in memory is provided. The system includes a computing device, a memory chip coupled to the computing device and including memory, and a heater, the heater configured to prevent data remanence in a memory by providing heat to at least a portion of the memory.
Elwha Llc


04/14/16
20160103152 

Testing apparatus


A test apparatus for testing a first flash memory chip is provided. The testing apparatus includes: an interface printed circuit board (pcb), a separate pcb, and a socket device.

04/07/16
20160099077 

Test system simultaneously testing semiconductor devices


Individual memory chips are simultaneously tested by a tester using selectively enabled stress modules that apply a corresponding stress test to memory cells, wherein each stress test is associated with a corresponding failure attribute for the memory cells. Built-in self-test (bist)/built-in self-stress (biss) circuitry is provided in each stress module and may configured to selectively apply one or more stress test(s) during the simultaneous testing of a plurality of memory chips..

03/31/16
20160093378 

Semiconductor memory device


A semiconductor memory device may include a plurality of memory chips stacked upon one another, and electrically coupled to one another through a plurality of first tsvs. The semiconductor memory device may include a plurality of second memory chips stacked separately from the first memory chips, and the plurality of second memory chips electrically coupled to one another through a plurality of second tsvs.
Sk Hynix Inc.


03/24/16
20160085670 

Memory access method, buffer scheduler and memory module


The present invention discloses a memory access method, a buffer scheduler, and a memory module, which can support multiple application scenarios without changing the memory module or a memory chip. The method includes: receiving an operation request message for memory access data, where the operation request message includes tag information of the memory access data, operation information of the memory access data, and a memory address of the memory access data; and performing, according to at least one of the tag information of the memory access data, a memory address of the memory access data, and the operation information of the memory access data, an operation on the tag of the memory access data and/or the memory access data stored in the memory module.
Huawei Technologies Co., Ltd.


03/17/16
20160079219 

Semiconductor device


According to one embodiment, there is provided a semiconductor device including an interposer, a logic chip, a memory chip, and a package substrate. In the interposer, first via is configured to electrically connect a signal terminal of the logic chip and a signal terminal of the memory chip to each other through a substrate.
Kabushiki Kaisha Toshiba


03/10/16
20160070506 

Device and storing data in a plurality of multi-level cell memory chips


A device for storing data in a plurality of multi-level cell memory chips. The device includes a scrambling unit to generate a plurality of candidate scrambled sequences of data by performing a plurality of scrambling operations on a sequence of data to be stored, a calculation unit to calculate a cost function for each of the plurality of candidate scrambled sequences of data, the result of each cost function being indicative of a balancing degree of subsequences of a candidate scrambled sequence, when the subsequences of the candidate scrambled sequence are written to the plurality of multi-level cell memory chips, a selection unit to select one of the candidate scrambled sequences of data based on the results of the cost functions, and a storing unit to store the selected candidate scrambled sequence of data in the multi-level cell memory chips by storing the subsequences across the multi-level memory chips..
International Business Machines Corporation


03/10/16
20160070313 

Data storage and transfer device


A data storage/transfer device includes at least a data storage component, such as a integrated memory chip or a card reader for data storage, at least a connector on one end, e.g., a usb type a or usb type c connector, and at least one connector on the other end, preferably, a different type of connector, e.g., a micro-b usb or a lightning connector. Users may use embodiments of the present invention as a data storage device and/or data transferring cable and/or charging cable.

03/03/16
20160064063 

Semiconductor device


A semiconductor device capable of controlling a memory while preventing the functional deterioration of the memory and reducing the power consumption of the semiconductor device is provided. The semiconductor device includes a first semiconductor chip (logic chip) and a second semiconductor chip (memory chip).
Renesas Electronics Corporation


02/25/16
20160055898 

Memory access method and memory system


A first level buffer chip gates a target second level buffer chip according to a preset mapping relationship, a first chip select signal, and a first higher-order address signal, and forwards a memory access instruction and a lower-order address signal received from a memory controller to the target second level buffer chip. The target second level buffer chip determines a target memory module according to a second chip select signal and a delayed address signal obtained by delays a second higher-order address signal, determines a target memory chip according to the lower-order address signal, acquires target data from the target memory chip according to the memory access instruction, and returns the target data to the memory controller.
Huawei Technologies Co., Ltd.


02/18/16
20160049206 

High voltage step down regulator with breakdown protection


A high voltage step regulator, such as would be used to provide a regulated low voltage (on the order of a few volts) from a high voltage external supply (e.g. 12v), is presented.
Sandisk Technologies Inc.


02/04/16
20160035711 

Stacked package-on-package memory devices


3d stacked memory devices with copper pillars electrically connecting the package units are disclosed. A stacked package-on-package memory device includes a base chip package unit having a logic processing chip disposed on a base substrate; and a memory chip stack overlying the base chip unit.

02/04/16
20160034206 

Adaptive flash tuning


The present invention includes embodiments of systems and methods for increasing the operational efficiency and extending the estimated operational lifetime of a flash memory storage device (and its component flash memory chips, luns and blocks of flash memory) by monitoring the health of the device and its components and, in response, adaptively tuning the operating parameters of flash memory chips during their operational lifetime, as well as employing other less extreme preventive measures in the interim, via an interface that avoids the need for direct access to the test modes of the flash memory chips. In an offline characterization phase, “test chips” from a batch of recently manufactured flash memory chips are used to simulate various usage scenarios and measure the performance effects of writing and attempting to recover (read) test patterns written with different sets of operating parameters over time (simulating desired retention periods)..

01/14/16
20160012865 

Semiconductor device having interconnection in package and manufacturing the same


A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip..

01/14/16
20160011781 

Memory chip, memory system, and accessing the memory chip


A memory chip, a memory system, and a method of accessing the memory chip. The memory chip includes a substrate, a first storage unit, and a second storage unit.
Samsung Electronics Co., Ltd.


12/31/15
20150380078 

Memory chip and layout design for manufacturing same


A static random access memory (sram) chip including a plurality of sram cells and a plurality of cell current tracking cells. Each of the sram cells include a source voltage reference conductor, a first ground reference conductor, two cross-coupled inverters, and two pass-gate devices.
Taiwan Semiconductor Manufacturing Company, Ltd.


12/31/15
20150379184 

Layout printed circuit board


A printed circuit board (pcb) is provided. The pcb has a specific routing module, having a first chip, a memory chip, and a plurality of traces designed for interconnection between the first chip and the memory chip according to a routing configuration between the first chip and the memory chip.
Mediatek Inc


12/31/15
20150379180 

Layout printed circuit board


A layout method for a printed circuit board (pcb) is provided. The method obtains a memory type of a dynamic random access memory (dram) to be mounted on the pcb, obtains a module group from a database according to the memory type of the dram, wherein the module group comprises a plurality of routing modules, obtains a plurality of pcb parameters, selects a specific routing module from the module group according to the pcb parameters, and implements the specific routing module into a layout design for pcb fabrication.
Mediatek Inc


12/31/15
20150378818 

Memory chip with error detection and retry modes of operation


A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter.
Rambus Inc.


12/31/15
20150378613 

Storage device


A storage device comprises plural memory units and a storage controller that controls the memory units as a raid group. Each memory unit is provided with a nonvolatile semiconductor memory (e.g.
Hitachi, Ltd.


12/24/15
20150371701 

Memory chip and layout design for manufacturing same


An embedded synchronous random access memory (sram) chip, includes a first single-port (sp) sram macro and a second sp macro. The first macro includes a first periphery circuit, and a plurality of first sram cells.
Taiwan Semiconductor Manufacturing Company, Ltd.


12/24/15
20150370669 

Implementing enhanced wear leveling in 3d flash memories


A method, system and computer program product are provided for implementing enhanced wear leveling in a stack of flash memory chips. A flash memory includes plurality of flash memory chips including a number n data chips and one or more spare chips.
International Business Machines Corporation


12/24/15
20150370635 

Implementing enhanced wear leveling in 3d flash memories


A method, system and computer program product are provided for implementing enhanced wear leveling in a stack of flash memory chips. A flash memory includes plurality of flash memory chips including a number n data chips and one or more spare chips.
International Business Machines Corporation


12/17/15
20150365108 

System and module comprising an electrically erasable programmable memory chip


A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data.
Rambus Inc.


12/17/15
20150364206 

Memory system and control method


A memory system according to embodiments comprises a memory chip that includes a memory cell array having a plurality of memory cells, a first writing unit that writes first data in a first memory cell in the memory cell array, and a second writing unit that writes second data in a second memory cell which is adjacent to the first memory cell. The second data is used in adjusting a threshold value of the first memory cell..
Kabushiki Kaisha Toshiba


12/10/15
20150357002 

Stacked memory with redundancy


A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations.
Rambus Inc.


12/10/15
20150355964 

Controller device for use with electrically erasable programmable memory chip with error detection and retry modes of operation


A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter.
Rambus Inc.


12/03/15
20150347058 

System and distributed computing in non-volatile memory


A system and method are disclosed for incorporating mathematical and/or logical functionality within a memory system (such as a solid state drive (ssd)). The mathematical and/or logical functionality may comprise an arithmetic logic unit (alu).
Sandisk Technologies Inc.


11/26/15
20150340342 

Semiconductor device


A semiconductor device in which a plurality of semiconductor chips having different planar sizes are stacked with a degree of freedom in design of each of the semiconductor chips is provided. A logic chip, a redistribution chip, and a memory chip having a larger planar size than the logic chip are mounted over a wiring board.
Renesas Electronics Corporation


11/26/15
20150340074 

Memory module having address mirroring function


A memory module having an address minoring function is provided. The memory module includes a register that allows mode registers of first memory chips of a first rank and mode registers of second memory chips of a second rank to be identically programmed in response to a mode register set (mrs) command during a rank-merged test mode.
Samsung Electronics Co., Ltd.


11/19/15
20150332736 

Stacked memory device control


A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects.
International Business Machines Corporation


11/19/15
20150331768 

Data retrieval from stacked computer memory


Data is retrieved from a stacked memory device having a plurality of slave memory chips in response to recognizing a problem in the stacked memory device. The problem is determined to be associated with a primary driver module in the stacked memory device.
International Business Machines Corporation


11/19/15
20150331767 

Stacked memory device control


A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects.
International Business Machines Corporation


11/19/15
20150331764 

Data retrieval from stacked computer memory


Data is retrieved from a stacked memory device having a plurality of slave memory chips in response to recognizing a problem in the stacked memory device. The problem is determined to be associated with a primary driver module in the stacked memory device.
International Business Machines Corporation


11/12/15
20150325276 

Bipolar logic gates on mos-based memory chips


A system for using selectable-delay bipolar logic circuitry within the address decoder of a mos-based memory includes a mos-based memory, which includes an array of a plurality of memory cells configured to store data; an address decoder including bipolar logic circuitry, where the address decoder is configured to accept a word including a plurality of bits and access the array of memory cells using the word; where the bipolar logic circuitry includes a plurality of bipolar transistor devices, where at least one bipolar transistor device has an adjustable gate bias and is configured to accept an input, wherein the gate bias is adjusted based on the input, where the gate bias determines a selectable gate delay.. .
Elwha Llc


11/12/15
20150324668 

Method, system and memory chip for generating checkout value


A method, a system and a memory chip for generating a check value, which can eliminate the defect of time consuming and high power consumption of the existing memory chip for generating check value, are provided according to the present disclosure. The method comprises the following steps: a frequently changing data relating to an imaging cartridge is acquired; an intermediate check data pre-generated based on infrequently changing data is acquired; the frequently changing data and the intermediate check data are calculated through a predetermined algorithm, and thus a check value is obtained.
Apex Microelectronics Co., Ltd.


11/05/15
20150317276 

Reconfigurable high speed memory chip module and electronic device with a reconfigurable high speed memory chip module


A reconfigurable high speed memory chip module includes a type of memory cell array group, a first transmission bus, and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ics).
Etron Technology, Inc.


11/05/15
20150317097 

De-duplication in flash memory module


Data capacity efficiency is improved by de-duplicating data assigned with a code that is different for each data. A storage apparatus comprising a flash memory control device equipped with one or more flash memory modules, wherein the flash memory module comprises at least one flash memory chip for providing a storage area, and a controller for controlling writing/reading of data including user data and a guarantee code accompanying the user data to and from the storage area provided by the flash memory chip, wherein the controller respectively divides a plurality of the data having the common user data into the user data and the guarantee code, stores one of the user data in an area of a predetermined unit of the storage area, and links and stores each of the guarantee codes accompanying the plurality of user data in an area of a predetermined unit of the storage area..
Hitachi, Ltd.


10/29/15
20150310910 

Multi-level memory array having resistive elements for multi-bit data storage


A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device.
Sandisk 3d Llc


10/22/15
20150302904 

Accessing memory


A disclosed example method involves performing simultaneous data accesses on at least first and second independently selectable logical sub-ranks to access first data via a wide internal data bus in a memory device. The memory device includes a translation buffer chip, memory chips in independently selectable logical sub-ranks, a narrow external data bus to connect the translation buffer chip to a memory controller, and the wide internal data bus between the translation buffer chip and the memory chips.

10/22/15
20150301748 

Storage operating system


A storage system includes a plurality of unit storages each including at least one flash memory chip. Performance of at least a first storage of the unit storages is monitored.
Samsung Electronics Co., Ltd.


10/15/15
20150293859 

Memory access processing method, memory chip, and system based on memory chip interconnection


A memory access processing method is based on memory chip interconnection, a memory chip, and a system, which relate to the field of electronic devices, and can shorten a time delay in processing a memory access request and improve a utilization rate of system bandwidth. The method of the present invention includes: receiving, by a first memory chip, a memory access request; and if the first memory chip is not a target memory chip corresponding to the memory access request, sending, according to a preconfigured routing rule, the memory access request to a next memory chip connected with the first memory chip, until the target memory chip corresponding to the memory access request is determined.

10/01/15
20150279444 

Apparatus, providing termination for multiple chips of an integrated circuit package


Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (ic) package which includes a command and address bus and a plurality of memory chips each coupled thereto.
Intel Corporation


10/01/15
20150278054 

Method for managing storage system using flash memory, and computer


To facilitate the management of a storage system that uses a flash memory as a storage area. A controller of the storage system provided with a flash memory chip manages a surplus capacity value of the flash memory chip, and transmits a value based on the surplus capacity value to a management server, on the basis of at least one of a definition of a parity group, a definition of an internal lu, and a definition of a logical unit.
Hitachi, Ltd.


09/17/15
20150262900 

Dam for three-dimensional integrated circuit


An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (ic) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members.
Taiwan Semiconductor Manufacturing Company, Ltd.


09/17/15
20150261448 

Memory system, memory controller and control non-volatile memory


According to one embodiment, a controller executes a first process such that writing is performed in an order of page numbers in the memory chip. The first process includes a second process to be executed in an order of group units.
Kabushiki Kaisha Toshiba


09/10/15
20150255144 

Method and calibrating write timing in a memory system


A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation.
Rambus Inc.


09/10/15
20150255131 

Stacked semiconductor apparatus and semiconductor system capable of inputting signals through various paths


A semiconductor apparatus includes a control signal reception portion. The control signal reception portion may set information related to operation of a memory chip by receiving a command signal and an address signal from one among a stack chip test portion, a control signal interface portion and a test setting portion..
Sk Hynix Inc.


09/10/15
20150254011 

Memory system, memory controller and control non-volatile memory


According to an embodiment, a controller executes chip interleaving for a host write partway through one cycle, and executes chip interleaving for writes of garbage collection to n memory chips from a memory chip next in turn to a memory chip to which the host write was executed last, to the memory chip to which the host write was executed last.. .
Kabushiki Kaisha Toshiba


09/03/15
20150248935 

Apparatus, systems, and methods for operating flash backed dram module


A device includes volatile memory; one or more non-volatile memory chips, each of which is for storing data moved from the volatile-memory; an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from a primary power source; a controller in communication with the volatile memory and the non-volatile memory, wherein: the controller is programmed to move data from the volatile memory to the non-volatile memory chips upon a loss of power of the primary power source of the volatile memory; and the at least one parameter describing the volatile memory are stored in at least one of the non-volatile memory chips that store the data moved from the volatile memory. In some aspects the at least one parameter includes serial presence detect information..
Hgst Netherlands B.v.


09/03/15
20150248926 

Method and calibrating write timing in a memory system


A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation.
Rambus Inc.


09/03/15
20150248322 

Memory controller and memory system


According to one embodiment, a memory controller includes a controller that is configured to, when notified of an error by one of memory chips at a time of power supply startup, transmit a first command including an address to the memory chip by which the error was notified, when notified of a normal end by the memory chip in which the first command was received, transmit a second command including an address to the memory chip by which the normal end was notified.. .
Kabushiki Kaisha Toshiba


09/03/15
20150246941 

Cobalt precursors for low temperature ald or cvd of cobalt-based thin films


Cobalt silylamide and cobalt carbonyl precursors are described, which are usefully employed in vapor deposition processes, such as chemical vapor deposition and atomic layer deposition, to deposit cobalt and to form high purity cobalt-containing films at temperatures below 400° c. These precursors and processes can be utilized in the manufacture of integrated circuitry and production of devices such as microprocessors, and logic and memory chips..
Entegris, Inc.


08/27/15
20150243605 

Method for manufacturing semiconductor device


To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip.
Renesas Electronics Corporation


08/27/15
20150243347 

Semiconductor device preventing multiword state


To prevent a multiword state in which a plurality of word lines are active in a same memory bank, the semiconductor device includes a plurality of memory chips commonly receiving an access command, in which each of the plurality of memory chips are provided with a control circuit ignoring an new access command when the bank address information in the new access command is the same as the bank address information for the specified memory bank even if the new access command received before reading/writing data from/to the specified memory bank of the selected memory chip is completed contains chip selection information selecting another memory chip.. .
Ps5 Luxco S.a.r.l.


08/27/15
20150243343 

Method and calibrating write timing in a memory system


A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation.
Rambus Inc.


08/20/15
20150236002 

Multi-chip module with stacked face-down connected dies


A microelectronic assembly can include a substrate having first and second surfaces, at least two logic chips overlying the first surface, and a memory chip having a front surface with contacts thereon, the front surface of the memory chip confronting a rear surface of each logic chip. The substrate can have conductive structure thereon and terminals exposed at the second surface for connection with a component.
Tessera, Inc.


08/20/15
20150235715 

Stacked semiconductor memory apparatus and test circuit therefor


A stacked semiconductor memory apparatus includes a memory module including a plurality of memory chips; and a logic circuit block with the memory module stacked thereon, configured to be electrically coupled with an interface substrate through a first terminal group and a second terminal group and to communicate with a controller, and to include a test circuit that receives a first test signal through the first terminal group from the controller and outputs the first test signal through the second terminal group in a test mode.. .
Sk Hynix Inc.


08/20/15
20150235714 

Semiconductor device for parallel bit test and test method thereof


A semiconductor device includes a plurality of memory chips and a plurality of signal selection units respectively corresponding to the plurality of memory chips, and suitable for commonly transferring test data signals from an external to a corresponding one of the plurality of memory chips during a common test mode, wherein one or more of the plurality of signal selection units may transfer the test data signals from the external to corresponding ones of the plurality of memory chips during an individual test mode, and wherein the semiconductor device may be set to the common test mode when a common test signal is enabled, and set to the individual test mode when both the common test signal and a test control signal are enabled.. .
Sk Hynix Inc.


08/20/15
20150234752 

Memory chip


According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.. .
Kabushiki Kaisha Toshiba


08/20/15
20150234705 

Semiconductor memory device


A crc code is generated from an original data, a bch code is generated with respect to the original data and the crc code, and the original data, the crc code, and the bch code are recorded in pages selected from different planes of a plurality of memory chips. An rs code is generated from the original data across pages, a crc code is generated with respect to the rs code, a bch code is generated with respect to the rs code and the crc code, and the rs code, the crc code, the bch code are recorded in a memory chip different from a memory chip including the original data.
Kabushiki Kaisha Toshiba


07/30/15
20150213841 

Memory chip and memory storage device


A memory chip is disclosed. The memory comprises a substrate and a plurality of memory pads.
Eorex Corporation


07/23/15
20150208510 

Thin low profile strip dual in-line memory module


A low profile strip dual in-line memory module (200) includes a passive interposer support structure (90) with patterned openings (91-97) formed between opposing top and bottom surfaces, a plurality of memory chips (d1-d8) attached to the top and bottom surfaces, and vertical solder ball conductors (98) extending through the patterned openings to electrically connect the plurality of memory chips, where each memory chip has an attachment surface facing the passive interposer structure and a patterned array of horizontal conductors (e.g., 82-86) formed on the attachment surface with contact pads electrically connected to the plurality of vertical conductors to define at least one bus conductor that is electrically connected to each memory die in the first and second plurality of memory die.. .
Freescale Semiconductor, Inc.


07/23/15
20150208124 

Smart television system and turn-on and turn-off method thereof


A smart television, and a turn-off method and a turn-on method for the smart television system are provided. The smart television system includes a remote controller and a smart television.
Mstar Semiconductor, Inc.


07/23/15
20150207565 

Interface circuit for transmitting and receiving signals between electronic devices, and semiconductor memory chip and operation processing device including the same


An interface circuit configured to transmit and receive signals between electronic devices is provided. The interface circuit includes an optical connection protocol manager configured to serialize a parallel transmission packet electrical signal generated based on output data to generate a serialized transmission packet electrical signal, parallelize a serial reception packet electrical signal to generate a parallelized reception packet electrical signal, and parse the parallelized reception packet electrical signal according to whether there is an error in the parallelized reception packet electrical signal to generate input data; and an electro-optical converter configured to convert the serialized transmission packet electrical signal into a transmission packet optical signal to output the transmission packet optical signal, receive a reception packet optical signal, and convert the reception packet optical signal into the serial reception packet electrical signal to provide the serial reception packet electrical signal to the optical connection protocol manager..
Electronics And Telecommunications Research Institute


07/23/15
20150206866 

Semiconductor package and methods of forming same


An embodiment package-on-package (pop) device includes a fan-out structure, one or more memory chips, and a plurality of connectors bonding the one or more memory chips to the fan-out structure. The fan-out structure includes a logic chip, a molding compound encircling the logic chip, and a plurality of conductive pillars extending through the molding compound..
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206865 

Integrated circuit package and methods of forming same


An embodiment package-on-package (pop) device includes a package structure, a package substrate, and a plurality of connectors bonding the package structure to the package substrate. The package structure includes a logic chip bonded to a memory chip, a molding compound encircling the memory chip, and a plurality of conductive studs extending through the molding compound.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206849 

System-in-package module and manufacture a system-in-package module


A system-in-package module includes a non-memory chip, a bundled memory, and an encapsulation package material. The non-memory chip has a plurality of pads.
Etron Technology, Inc.


07/23/15
20150201880 

Integrated injection system and communication device


An integrated system for injection including an injection device (10) in electronic connection with a communication device (a) is provided. The external communication device may be a handheld electronic device such as a smartphone or a dedicated reader such as a reader capable of reading information contained on an rfid tag.
Becton Dickinson France S.a.s.


07/16/15
20150200008 

Semiconductor package and electronic apparatus


According to one embodiment, a semiconductor package includes a package substrate, a controller chip, a semiconductor memory chip, a temperature sensor, a seal portion, and a plurality of solder balls. The controller chip and the semiconductor memory chip are provided on a first surface of the package substrate.
Kabushiki Kaisha Toshiba


07/16/15
20150199266 

3dic memory chips including computational logic-in-memory for performing accelerated data processing


This disclosure relates to a three-dimensional (3d) integrated circuit (3dic) memory chip including computational logic-in-memory (lim) for performing accelerated data processing. Related memory systems and methods are also disclosed.
Carnegie Mellon University


07/09/15
20150193308 

Memory chips and data protection methods


A memory chip coupled to a host includes a memory and a controller. Multiple boot images having the same content are pre-loaded in the memory.
Via Technologies, Inc.


07/02/15
20150187682 

Semiconductor device


A semiconductor device is reduced in size. The semiconductor device includes a die pad, a plurality of leads arranged around the die pad, a memory chip and a power source ic chip mounted over the die pad, a logic chip mounted over the memory chip, a plurality of down bonding wires for connecting the semiconductor chip to the die pad, a plurality of lead wires for connecting the semiconductor chip to leads, and a plurality of inter-chip wires.
Renesas Electronics Corporation


07/02/15
20150187399 

Pulse mechanism for memory circuit interruption


In a memory system where multiple memory chips communicate their ready/busy status on a shared bus line, a pulse mechanism is used for the individual memory chips to indicate their ready/busy status to the controller. In one example, the controller assigns pulse durations of differing lengths to the memory dies to allow the controller to distinguish between them.
Sandisk Technologies Inc.




Memory Chip topics: Memory Chip, Semiconductor, Storage Device, Semiconductor Memory, Memory Cell, Volatile Memory, Host Computer, Form Factor, Memory Cells, Data Storage, Aspect Ratio, Error Correction, Semiconductor Device, Control Unit, Crystallin

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