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Memory Chip patents



      
           
This page is updated frequently with new Memory Chip-related patent applications. Subscribe to the Memory Chip RSS feed to automatically get the update: related Memory RSS feeds. RSS updates for this page: Memory Chip RSS RSS


Memory chip

Memory chip

Memory with refresh logic to accomodate low-retention storage rows

Memory with refresh logic to accomodate low-retention storage rows

Memory with refresh logic to accomodate low-retention storage rows

Ink cartridge and method of producing the same

Date/App# patent app List of recent Memory Chip-related patents
10/09/14
20140304461
 Storage subsystem patent thumbnailStorage subsystem
The storage system includes a plurality of flash memory devices, each of the flash memory devices including a flash memory controller and flash memory chips, which are configured as a raid group and a storage controller, coupled to the plurality of flash memory devices, configured to receive data from a computer and send the data to a first flash memory device of the plurality of flash memory devices. The flash memory controller of the flash memory device is configured to receive the data from the storage controller and execute a parity operation using the data..
10/02/14
20140298043
 Memory chip patent thumbnailMemory chip
According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.. .
10/02/14
20140293725
 Memory with refresh logic to accomodate low-retention storage rows patent thumbnailMemory with refresh logic to accomodate low-retention storage rows
An apparatus is disclosed that includes a memory controller chip and memory chips packaged with the memory controller chip. Each memory chip includes normal-retention storage rows that exhibit retention times greater or equal to a first time interval, and having been tested to generate information identifying low-retention storage rows that exhibit retention times less than the first time interval.
10/02/14
20140292957
 Ink cartridge and method of producing the same patent thumbnailInk cartridge and method of producing the same
An ink cartridge includes a cartridge body defining an ink chamber, an ink supply portion provided at the cartridge body, an air flow path provided in the cartridge body, a cover, and a memory chip disposed on the cover. The cartridge body has an outer surface oriented in a first direction and an air communication port opened on the outer surface.
09/25/14
20140289453
 Memory system and constructing method of virtual block patent thumbnailMemory system and constructing method of virtual block
According to one embodiment, a virtual block is constructed according to configuration conditions that, when a plurality of physical blocks included in the virtual block are selected, the sum of the number of physical block pairs and the number of single blocks allocated from the same memory chip to one virtual block is less than or equal to a first value.. .
09/25/14
20140287541
 Semiconductor chip and semiconductor device patent thumbnailSemiconductor chip and semiconductor device
When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy..
09/25/14
20140286074
 System and memory module patent thumbnailSystem and memory module
A system includes: a controller, a first memory module connected to the controller through a first data bus, and a second memory module connected to the controller through a second data bus, wherein the first memory module includes: first and second memory chips; a first data terminal connected to the first data bus, and a first switch unit that electrical connects the first data terminal with either the first memory chip and the second memory chip, and the second module includes: third and fourth memory chips; a second data terminal connected to the second data bus, and a second switch unit that switches over electrical connection of the second data terminal with either the third memory chip or the fourth memory chip.. .
09/18/14
20140281168
 Storage system and method of control for storage system patent thumbnailStorage system and method of control for storage system
The storage system includes a plurality of storage devices and a storage controller. The storage controller stores a data request quantity indicating the data quantity of write data written to the target area in a specific period, and estimates, based on the quantity of request data and relationship information received from storage devices, the estimated data quantity written to the nonvolatile semiconductor memory chips based on the write data written to the target area in the specific period.
09/18/14
20140281160
 Non-volatile semiconductor storage apparatus patent thumbnailNon-volatile semiconductor storage apparatus
According to one embodiment, apparatus includes non-volatile memory chips, and a first controller which executes processing for reading first valid data stored in a first storage region of a first non-volatile memory chip in the non-volatile memory chips, processing for storing the first valid data in a buffer memory, processing for writing the first valid data stored in the buffer memory in a second storage region of the first non-volatile memory chip, and processing for erasing data stored in the first storage region. Each of the non-volatile memory chips comprises erase blocks.
09/18/14
20140281157
 Memory system, memory controller and method patent thumbnailMemory system, memory controller and method
According to one embodiment, a memory system includes a plurality of non-volatile memory chips and a memory controller. The memory controller controls a read operation of the memory chips, and manages correspondence relation information between a logical address included in a read command and a physical address of the memory chip.
09/18/14
20140273300
Method for forming reram chips operating at low operating temperatures
Forming a resistive memory structure at a temperature well above the operating temperature can reduce the forming voltage and create a defect distribution with higher stability and lower programming voltages. The forming temperature can be up to 200 c above the operating temperature.
09/18/14
20140269004
Method for improving data retention of reram chips operating at low operating temperatures
Programming a resistive memory structure at a temperature well above the operating temperature can create a defect distribution with higher stability, leading to a potential improvement of the retention time. The programming temperature can be up to 100 c above the operating temperature.
09/18/14
20140268980
Memory chip package, memory system having the same and driving method thereof
A memory chip package includes memory chips stacked, electrically connected one another, and configured to input and output an optical signal through an optical line formed by a via penetrating the memory chips. The memory chips input and output optical signals with different wavelengths, and each of the memory chips has an optical-electrical converter configured to convert an optical signal with a corresponding wavelength into an electrical signal and to convert an electrical signal into an optical signal with the corresponding wavelength..
09/11/14
20140258558
Transcoding on virtual machines using memory cards
The present embodiments disclose techniques for transcoding media data using a virtualized network environment. This virtual environment may be hosted on one or more memory cards which each contain one or more memory chips.
09/11/14
20140253167
Memory chip testing system and connector thereof
A memory chip testing system includes a computer, a rheostat, a voltmeter, and a connector. The computer includes a main board, a number of memory chip interfaces mounted on the main board.
09/11/14
20140252357
Semiconductor device
Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (pop) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length.
09/04/14
20140250525
Systems and methods for preventing data remanence in memory
A system for preventing data remanence in memory is provided. The system includes a computing device, a memory chip coupled to the computing device and including memory, and a heater, the heater configured to prevent data remanence in a memory by providing heat to at least a portion of the memory.
09/04/14
20140248743
Semiconductor memory modules and methods of fabricating the same
The inventive concept provides semiconductor memory modules and methods of fabricating the same. The semiconductor memory module may include a module board having a first surface and a second surface opposite to the first surface, and memory chips mounted directly on the module board by a flip-chip bonding method.
09/04/14
20140247681
Wiring configuration of a bus system and power wires in a memory chip
Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. The effective resistance on the power supply wires may be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires.
09/04/14
20140246788
Stack-type semiconductor package
Provided is a stack-type semiconductor package comprising a first semiconductor package with a first package substrate and a logic chip mounted thereon, a second semiconductor package including a second package substrate disposed on the first semiconductor package and first and second memory chips stacked on the second package substrate, and connection pads disposed between the first and second package substrates to connect the first and second semiconductor packages electrically to each other. The first package substrate has first and second edges that are substantially perpendicular to each other.
08/28/14
20140245100
Semiconductor memory device
A crc code is generated from an original data, a bch code is generated with respect to the original data and the crc code, and the original data, the crc code, and the bch code are recorded in pages selected from different planes of a plurality of memory chips. An rs code is generated from the original data across pages, a crc code is generated with respect to the rs code, a bch code is generated with respect to the rs code and the crc code, and the rs code, the crc code, the bch code are recorded in a memory chip different from a memory chip including the original data.
08/28/14
20140240913
Thermal regulation for solid state memory
A chassis for a storage system contains a digital chamber that houses conventional electronic components and a thermal chamber that houses non-volatile solid state memory such as flash memory. A temperature regulating system monitors temperature within the digital chamber to keep the components therein below their maximum junction temperature.
08/21/14
20140233335
Semiconductor devices
A plurality of memory chips each have an alert terminal that notifies the outside that the memory chip has detected a predetermined error. The plurality of memory chips are mounted on memory module 100.
08/07/14
20140217586
Package-on-package device
A package-on-package device includes memory chips side-by-side on a package substrate. Accordingly, it is possible to reduce a thickness of a semiconductor package.
07/24/14
20140204673
Flash memory module for realizing high reliability
A flash memory module may include a plurality of flash memory chips. The memory chips may include one or more blocks.
07/24/14
20140204105
Dram compression scheme to reduce power consumption in motion compensation and display refresh
Systems and methods of operating a memory controller may provide for receiving a write request from a motion compensation module, wherein the write request includes video data. A compression of the video data may be conducted to obtain compressed data, wherein the compression of the video data is transparent to the motion compensation module.
07/17/14
20140197505
Shields for magnetic memory chip packages
Chip packages are described with soft-magnetic shields that are included inside or attached externally to the package containing a mram chip. In one group of embodiments a single shield with vias for bonding wires is affixed to the surface of the mram chip having the contact pads.
07/10/14
20140195722
Storage system which realizes asynchronous remote copy using cache memory composed of flash memory, and control method thereof
The first storage apparatus provides a primary logical volume, and the second storage apparatus has a secondary logical volume. When the first storage apparatus receives a write command to the primary logical volume, a package processor in a flash package allocates first physical area in the flash memory chip to first cache logical area for write data and stores the write data to the allocated first physical area.
07/10/14
20140192606
Stacked memory device, memory system including the same and method for operating the same
A stacked memory device includes a plurality of interconnected memory chips and a controller to control the plurality of memory chips to perform refresh operations during non-overlapping time periods. Each memory chip includes a plurality of ranks, and each rank includes at least one memory bank.
07/03/14
20140189407
Data storage device and method for operating the same
A data storage device and a method for operating the same are provided. In the data storage device and the method for operating the same, a predetermined number of memory chips are operated based on a usable power limitation when a power supply is supplied from a finite power supply source such as a battery, and as many memory chips as possible are operated in parallel.
07/03/14
20140189227
Memory device and a memory module having the same
A memory device is provided. The memory device includes a plurality of memory chips, and a buffer chip connected to the plurality of memory chips.
07/03/14
20140189201
Flash memory interface using split bus configuration
A system having a split bus flash memory and a method for operating the split bus flash memory is disclosed. The system may include a controller, a non-volatile memory (including first and second non-volatile memory chips) and the system bus.
07/03/14
20140185352
Configurable-width memory channels for stacked memory structures
The disclosed embodiments provide a chip package that facilitates configurable-width memory channels. In this chip package, a semiconductor die is electrically connected to two or more memory chips.
07/03/14
20140185226
Multi-channel memory module
Embodiments of the invention further describe a memory module having a memory card housing, first and second pluralities of memory chips/devices included in the housing, and first and second pluralities of memory module electrical i/o terminals for coupling the first and second pluralities of memory chips/devices to pcb, respectively. In embodiments of the invention, the above described first and second pluralities electrical i/o connectors are disposed on different sides of the housing..
06/26/14
20140181415
Prefetching functionality on a logic die stacked with memory
Prefetching functionality on a logic die stacked with memory is described herein. A device includes a logic chip stacked with a memory chip.
06/26/14
20140177315
Multi-level memory array having resistive elements for multi-bit data storage
A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device.
06/19/14
20140173170
Multiple subarray memory access
A multiple subarray-access memory system is disclosed. The system includes a plurality of memory chips, each including a plurality of subarrays and a memory controller in communication.
06/19/14
20140167134
Self-aligned vertical nonvolatile semiconductor memory device
The present invention belongs to the technical field of semiconductor memory devices and specifically relates to a self-aligned vertical nonvolatile semiconductor memory device, including: a semiconductor substrate, a drain region of a first doping type, two source regions of a second doping type, a stacked gate used to capture electrons; wherein the drain region, the two source regions and the stacked gate form two tunneling field effect transistors (tfets) sharing one gate and one drain, the drain region current of each of the tfet is affected by the quantity and distribution of the charges in the stacked gate used to capture electrons, the drain is buried in the semiconductor substrate, the source regions above the drain region are separated from the drain through a channel and separated form each other through a region of the first doping type. The semiconductor memory device of the present invention features small unit area and simple manufacturing process.
06/12/14
20140160595
Emergency power off (epo) island for saving critical data to non-volatile memory
Approaches for an emergency power off (epo) power island, for saving critical data to non-volatile memory in the event of an epo condition, for use in a hard-disk drive (hdd) storage device. The epo power island includes a controller for detecting an epo condition.
06/12/14
20140159247
3d semiconductor interposer for heterogeneous integration of standard memory and split-architecture processor
A standard memory chip (150) is vertically assembled with two processor chips (130, 140) of split architecture by means of a small silicon interposer (120) stacked onto a large silicon interposer (110); both interposers include through-silicon vias (tsvs), while the chips are free of tsvs. The tsvs of small interposer (120) connect to the memory chip (150) and to the bottom interposer (110).
06/05/14
20140157065
Method and system for providing a smart memory architecture
A smart memory system preferably includes a memory including one or more memory chips, and a processor including one or more memory processor chips. The system may include a smart memory controller capable of performing a bit error rate built-in self test.
06/05/14
20140156915
Partitioning a flash memory data storage device
A method of partitioning a data storage device that has a plurality of memory chips includes determining a number memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips, defining a second partition of the data storage device via the host where the second partition includes a second subset of the plurality of memory chips, such that the first subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the first subset.. .
06/05/14
20140153336
Semiconductor memory device having a plurality of chips and capability of outputting a busy signal
One package contains a plurality of memory chips. Each memory chip has an i/o terminal which generates a busy signal.
05/22/14
20140141543
Semiconductor device having optical fuse and electrical fuse
A method for manufacturing a stacked semiconductor memory device includes testing a plurality of memory chips to detect first defective addresses, programming optical fuses with first defective address information on each of the plurality of memory chips that have the first defective addresses, stacking the plurality of memory chips, testing the stacked memory chips to detect second defective addresses, and programming electrical fuses with second defective address information.. .
05/22/14
20140138851
Semiconductor memory chips and stack-type semiconductor packages including the same
Provided are semiconductor memory chips and semiconductor packages with the same. The semiconductor package may include a memory chip including first data pads and first command/address pads arranged adjacent to a first side region thereof and second data pads and second command/address pads arranged adjacent to a second side region thereof arranged opposite to the first side region, and a package substrate including first ca connection pads and second ca connection pads.
05/08/14
20140129906
Data and error correction code mixing device and method
Memory devices and methods are described such as those that mix data and associated error correction code blocks between multiple memory device locations. Examples include mixing between multiple memory blocks, mixing between memory pages, mixing between memory chips and mixing between memory modules.
05/08/14
20140126304
Memory system and operating method thereof
A memory system includes one or more memory chips, and a repair information storage chip including a nonvolatile memory configured to store a repair information of the one or more memory chips, wherein during an initial operation of the memory system, the repair information stored in the repair information storage chip is transmitted to the one or more memory chips.. .
05/08/14
20140124959
Memory device, laminated semiconductor substrate and method of manufacturing the same
A memory device has a laminated chip package and a controller chip. In the laminated chip package, a plurality of memory chips are laminated.
05/08/14
20140124921
Semiconductor package
A semiconductor package includes a substrate; a driving chip having first bumps on a first surface and bump pads on a second surface facing away from the first surface, and mounted to the substrate by the medium of the first bumps; a support member disposed on the substrate substantially horizontally with respect to the driving chip; and a plurality of memory chips substantially horizontally disposed on the driving chip and the support member such that one corner portions of the memory chips are positioned on the driving chip while being centered about the driving chip, wherein the respective memory chips have second bumps which are electrically connected with the respective bump pads of the driving chip, on one surfaces of the one corner portions of the memory chips which face the driving chip.. .
05/01/14
20140119150
Bipolar logic gates on mos-based memory chips
A system for using selectable-delay bipolar logic circuitry within the address decoder of a mos-based memory includes a mos-based memory, which includes an array of a plurality of memory cells configured to store data; an address decoder including bipolar logic circuitry, where the address decoder is configured to accept a word including a plurality of bits and access the array of memory cells using the word; where the bipolar logic circuitry includes a plurality of bipolar transistor devices, where at least one bipolar transistor device has an adjustable gate bias and is configured to accept an input, wherein the gate bias is adjusted based on the input, where the gate bias determines a selectable gate delay.. .
05/01/14
20140118382
Method for programming extended display identification data and display device
A method for programming extended display identification data (edid) adapted to a display device is provided. The display device has at least one edid chip, a microcontroller unit chip, and a flash memory chip.
05/01/14
20140117430
Semiconductor package
A semiconductor package includes a first substrate, a plurality of memory chips horizontally disposed on the first substrate, and having one surfaces which face the first substrate, other surfaces which face away from the one surfaces, and first bumps formed on the other surfaces, a second substrate disposed on the plurality of memory chips and electrically connected, a sub-substrate horizontally disposed on the first substrate together with the plurality of memory chips and electrically connecting the first substrate and the second substrate, and a driving chip having second bumps on one surface thereof and mounted to the second substrate such that the second bumps are electrically connected with the second substrate.. .
04/24/14
20140115230
Flash memory with data retention partition
A nand flash memory chip includes a first partition that has smaller memory cells, with smaller charge storage elements, and a second partition that has larger memory cells, with larger charge storage elements, in the same memory array. Data is selected for storage in the first or second partition according to characteristics, or expected characteristics, of the data..
04/17/14
20140109035
Layout method for printed circuit board
A layout method for a printed circuit board (pcb) is provided. A memory type of a dynamic random access memory (dram) to be mounted on the pcb is obtained.
04/17/14
20140108708
Raid configuration in a flash memory data storage device
A method of storing data in a flash memory data storage device that includes a plurality of memory chips is disclosed. The method includes determining a number of memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips and defining a second partition of the data storage device via a host coupled to the data storage device, where the second partition includes a second subset of the plurality of memory chips.
04/17/14
20140108683
Memory system that utilizes a wide input/output (i/o) interface to interface memory storage with an interposer
A memory system is provided in which at least one memory chip and a memory controller chip are mounted in a side-by-side relationship on an interposer. The memory chip is connected to the interposer via a wide i/o interface to enable the memory chip and the memory controller chip to communicate with each other via the wide i/o interface.
04/17/14
20140104946
On-chip hv and lv capacitors acting as the second back-up supplies for nvsram auto-store operation
Two on-chip capacitors including one hv capacitor vppcap and one lv vcc capacitor vcccap are built over a nvsram memory chip as a back-up second power supplies for each nvsram cell, regardless of 1-poly, 2-poly, pmos or nmos flash cell structures therein. The on-chip hv and lv capacitors are preferably made from one or more mim or mip layers for achieving required capacitance.
04/17/14
20140104920
Semiconductor device
According to one embodiment, a semiconductor device includes a processor chip, and a memory chip stacked on the processor chip with bumps and including a memory cell unit and a memory logic unit. The bumps are arranged on the memory logic unit.
04/17/14
20140104917
Semiconductor memory device including plurality of memory chips
A semiconductor memory device includes a plurality of memory chips each including a chip identification (id) generation circuit. The chip id generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip id generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip id numbers of the plurality of device chips.
04/10/14
20140101368
Binding microprocessor to memory chips to prevent re-use of microprocessor
A processor is provided that binds itself to a circuit such that the processor cannot be subsequently reused in other circuits. On a first startup of the processor, a memory segment of an external volatile memory device is read to obtain information prior to initialization of the memory segment.
04/10/14
20140099815
Memory module connector with auxiliary power
An apparatus includes a socket that receives a memory module that includes a card having card edge voltage pads along the lower card edge, auxiliary voltage pads along at least one of the vertical card edges, and one or more persistent, solid-state memory chips on one or both card faces. A latch pivotally coupled to the socket is movable between a latched position and an unlatched position.
04/10/14
20140098480
Memory module connector with auxiliary power cable
A memory module includes persistent-storage memory chips and an auxiliary voltage connector for powering the persistent-storage memory chips. An auxiliary power cable has a first end coupled to an electronic power source on the system board and has a second end having connector that plugs in to the auxiliary voltage connector on the memory module to provide power to the persistent-storage memory chips.
04/10/14
20140097482
Full metal gate replacement process for nand flash memory
A nand flash memory chip is made by forming sacrificial control gate structures and sacrificial select structures, and subsequently replacing these sacrificial structures with metal. Filler structures are formed between sacrificial control gate structures and are subsequently removed to form air gaps between neighboring control gate lines and between floating gates..
03/27/14
20140089729
Storage system and storage control method
A storage system includes a plurality of nonvolatile memory devices that each includes a plurality of nonvolatile memory chips, and a storage controller configured to perform input and output of data to and from a raid group comprised by storage areas of the plurality of nonvolatile memory devices. A nonvolatile memory device identifies a failure occurrence area that is a storage area in which a failure occurred in the plurality of nonvolatile memory chips, excludes the failure occurrence area from a storage area allocated to the raid group, and transmits failure occurrence information that is information relating to the failure that has occurred in the nonvolatile memory device to the storage controller.
03/27/14
20140089548
Systems, methods, and articles of manufacture to stream data
Systems and methods for streaming data. Systems allow read/write across multiple or n device modules.
03/27/14
20140084434
Semiconductor device
A semiconductor device is reduced in size. The semiconductor device includes a die pad, a plurality of leads arranged around the die pad, a memory chip and a power source ic chip mounted over the die pad, a logic chip mounted over the memory chip, a plurality of down bonding wires for connecting the semiconductor chip to the die pad, a plurality of lead wires for connecting the semiconductor chip to leads, and a plurality of inter-chip wires.
03/20/14
20140078826
Methods of making word lines and select lines in nand flash memory
A nand flash memory chip includes word lines formed by etching through concentric conductive loops and, in the same etch step, etching through a conductive strip to form select lines. A conductive loop forms two word lines which are in different erase blocks and are separately controlled by peripheral circuits..
03/20/14
20140077391
Semiconductor device
A semiconductor device in which a plurality of semiconductor chips having different planar sizes are stacked with a degree of freedom in design of each of the semiconductor chips is provided. A logic chip, a redistribution chip, and a memory chip having a larger planar size than the logic chip are mounted over a wiring board.


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Memory Chip topics: Memory Chip, Semiconductor, Storage Device, Semiconductor Memory, Memory Cell, Volatile Memory, Host Computer, Form Factor, Memory Cells, Data Storage, Aspect Ratio, Error Correction, Semiconductor Device, Control Unit, Crystallin

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