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Memory Chip patents



      
           
This page is updated frequently with new Memory Chip-related patent applications. Subscribe to the Memory Chip RSS feed to automatically get the update: related Memory RSS feeds. RSS updates for this page: Memory Chip RSS RSS


Date/App# patent app List of recent Memory Chip-related patents
02/26/15
20150058664
 Dynamic memory cell replacement using column redundancy patent thumbnailnew patent Dynamic memory cell replacement using column redundancy
A memory chip comprises a main memory array having a plurality of memory columns, a redundancy memory column associated with the main memory array, and a hit logic circuitry configured to generate a plurality of hit logic signals by a plurality of hit logic units in the hit logic circuitry to enable dynamic replacement of a defective memory cell in one of the memory columns for dynamic replacement by the redundancy memory column when the memory array is in operation.. .
Taiwan Semiconductor Manufacturing Co., Ltd.
02/26/15
20150055419
 Controller, memory system, and method patent thumbnailnew patent Controller, memory system, and method
According to one embodiment, a memory system includes a memory chip and a controller. The controller is configured to count a first elapsed time from a start of an erase process when causing the memory chip to execute the erase process.
Kabushiki Kaisha Toshiba
02/19/15
20150048521
 Semiconductor package patent thumbnailSemiconductor package
According to example embodiments, a semiconductor package includes a first and a second semiconductor package. The first semiconductor package includes a first package substrate, first and second memory chips spaced apart from each other on the first package substrate in a first direction, third and fourth memory chips on the first and second memory chips, respectively, and first and second jumper chips on the first and second memory chips, respectively.
02/12/15
20150046612
 Memory device formed with a semiconductor interposer patent thumbnailMemory device formed with a semiconductor interposer
A packaged memory device includes a semiconductor interposer, a first memory stack, a second memory stack, and a buffer chip that are all coupled to the semiconductor interposer. The first memory stack and the second memory stack each include multiple memory chips that are configured as a single stack.
Nvidia Corporation
02/05/15
20150039921
 Memory system and memory chip patent thumbnailMemory system and memory chip
A memory system includes a memory which asserts a high-power-consumption operation output when an amount of the power consumption is high in internal operations in respective operations, and a controller which has an interface function between a host and the memory and receives the high-power-consumption operation output. The controller switches an operation mode thereof to a low power consumption mode when the high-power-consumption operation output is asserted..
Kabushiki Kaisha Toshiba
02/05/15
20150039820
 Flash memory storage system and controller and data writing method thereof patent thumbnailFlash memory storage system and controller and data writing method thereof
A flash memory storage system having a flash memory controller and a flash memory chip is provided. The flash memory controller configures a second physical unit of the flash memory chip as a midway cache physical unit corresponding to a first physical unit and temporarily stores first data corresponding to a first host write command and second data corresponding to a second host write command in the midway cache physical unit, wherein the first and second data corresponding to slow physical addresses of the first physical unit.
Phison Electronics Corp.
01/29/15
20150028517
 Identification device for a pneumatic spring patent thumbnailIdentification device for a pneumatic spring
An identification device (1) for a pneumatic spring (2) includes an rfid transponder (8), which is completely embedded into the elastomer matrix (13) of the flexible member (4). An electromagnetic field is generated by a read device (9), wherein the energy necessary for supplying the rfid transponder (8) is taken from the electromagnetic field generated by the read device (9).
Contitech Luftfedersysteme Gmbh
01/15/15
20150016047
 Memory module patent thumbnailMemory module
A memory module that includes: a printed circuit board having a connecting terminal; memory chips arranged on the printed circuit board; data buffers disposed on a first surface of the printed circuit board and corresponding to the memory chips; and resistance units disposed on a second surface of the printed circuit board and corresponding to the data buffers.. .
Samsung Electronics Co., Ltd.
01/15/15
20150016046
 Ina cabled memory appliance patent thumbnailIna cabled memory appliance
According to one general aspect, an apparatus may include an expansion memory device, a connection printed circuit board, and a connection cable. The expansion memory device may include a plurality of memory chips.
Samsung Electronics Co., Ltd.
01/08/15
20150009769
 Dram sub-array level refresh patent thumbnailDram sub-array level refresh
A memory controller coupled to a memory chip having a number of sub-arrays of memory cells is configured to determine a configuration of the memory chip. The memory controller is configured to read the sub-array configuration of the memory chip and to detect sub-array level conflicts between external commands and refresh operations.
Qualcomm Incorporated
01/01/15
20150006806

Double data rate synchronous dynamic random access memory module and configuring method thereof


Disclosed are a double data rate synchronous dynamic random access memory module and a configuring method thereof. The ddr sdram module in accordance with an embodiment of the present invention includes: a plurality of memory chips; and a serial transceiver portion configured to serially receive first serial data including a control signal and data transferred from outside for the plurality of memory chips and to provide the control signal and the data included in the serially received first serial data to the plurality of memory chips..
Electronics And Telecommunications Research Institute
01/01/15
20150003172

Memory module including buffer chip controlling refresh operation of memory devices


Provided is a memory module including a buffer chip controlling refresh operations. The buffer chip issues a hidden refresh command controlling refresh operations for the memory chips, and outputs a wait signal indicating that the memory chips are in refresh..
01/01/15
20150001538

Semiconductor device and a manufacturing the same


A device featuring a substrate configured to include an upper surface and an opposing lower surface and, in parallel, a first and an opposing second peripheral edge, the first peripheral edge being smaller in length than the second peripheral edge, one or more semiconductor chip mounted over the upper surface of the substrate, a control semiconductor chip mounted over the upper surface of the substrate, a sealing resin covering the memory and control chips, and a plurality of external terminals provided over the lower surface of the substrate, the external terminals being arranged in a line along the first peripheral edge. The external terminals are used to fit the device to an electronic apparatus.
Ps4 Luxco S.a.r.l.
12/25/14
20140374900

Semiconductor package and fabricating the same


A semiconductor package includes memory i/o bumps and power/ground voltage bumps which are disposed at different positions from each other. In the semiconductor package, memory chips are disposed side by side, and a passivation layer is interposed between a conductive pad and a bump..
12/18/14
20140371945

Information processing apparatus, controlling the same and program


An information processing apparatus according to an aspect of the present invention generates temperature distribution information (updated temperature information) that indicates the current temperature distribution in a memory chip, based on predetermined temperature information generated by an analysis executed in advance and temperature information obtained by a temperature sensor. The predetermined temperature information includes information related to the temperature distribution in the memory chip that corresponds to the operating states of an soc die and a wide io memory device.
Canon Kabushiki Kaisha
12/11/14
20140364771

Pressure sensitive assemblies for limiting movements adverse to health or surgical recovery


Pressure sensitive devices, systems and methods for alerting a user of movements potentially adverse to health or surgical recovery are disclosed. The pressure sensitive device may include a force sensor placed along the anterior aspect of a hand; and a vibration motor in communication with the force sensor in close proximity to the user, e.g., along the posterior aspect of the wrist.
12/04/14
20140359200

High performance system topology for nand memory systems


A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device.
12/04/14
20140357021

Multi-chip module with stacked face-down connected dies


A microelectronic assembly can include a substrate having first and second surfaces, at least two logic chips overlying the first surface, and a memory chip having a front surface with contacts thereon, the front surface of the memory chip confronting a rear surface of each logic chip. The substrate can have conductive structure thereon and terminals exposed at the second surface for connection with a component.
12/04/14
20140355370

Semiconductor system and semiconductor package


A semiconductor system includes a plurality of memory chips. Each of the memory chips includes an oscillator suitable for generating a periodic wave in a self refresh mode, and a delay unit suitable for delaying the periodic wave to generate a refresh pulse and for setting a delay value based on a corresponding chip identification..
12/04/14
20140355363

Memory chip and semiconductor package including the same


A memory chip includes a data processing block suitable for serial-parallel converting data inputted and for parallel-serial converting data to be outputted, a write data transmitting unit suitable for transmitting the data serial-parallel converted by the data processing block to a write data interlayer channel, a write data receiving unit suitable for receiving data from the write data interlayer channel, the data to be written to a core area, a read data receiving unit suitable for receiving data from a read data interlayer channel, the data to be parallel-serial converted by the data processing block, and a read data transmitting unit suitable for transmitting data read from the core area to the read data interlayer channel.. .
12/04/14
20140355325

Packaging of high performance system topology for nand memory systems


A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device.
12/04/14
20140353516

Optical sensors for monitoring biopharmaceutical solutions in single-use containers


Disposable, pre-sterilized, and pre-calibrated, pre-validated sensors are provided. The sensor comprises a disposable fluid conduit or bioreactor bag and a reusable sensor assembly.
11/27/14
20140351525

Efficient memory accesses in a multi-core processor


A method of providing memory accesses for a multi-core processor includes reserving a group of pins of a multi-core processor to transmit either data or address information in communication with one or more memory chips, receiving memory access requests from the plurality of processor cores, determining granularity of the memory access requests by a memory controller, and dynamically adjusting the number of pins in the group of pins to be used to transmit address information based with the granularity of the memory access requests.. .
11/27/14
20140350415

Method and circuit for storing and providing historical physiological data


Embodiments of the present invention include systems and methods that relate to pulse oximetry. Specifically, one embodiment includes an oximeter sensor comprising a light emitting element configured to emit light, a light detector configured to detect the light, and a memory chip having a built-in trimmed resistor, the trimmed resistor having a resistance value that is detectable by a monitor..
11/27/14
20140349708

Computing device with removable processing unit


A handheld tablet computing device with a removable central processor module has a first plurality of user interface elements comprising at least a screen, a keyboard, and a pointing device, a first communications link software module resident in a read-only firmware memory chip; a first docking port located on an interior surface of a void extending inward from one of the exterior surfaces of the handheld computing device; and a user-removable processing unit comprising at least a central processor module, a data storage module, a second communications link software module, a second docking port, and a second plurality of user interface elements, the user-removable processing unit being removably coupled to the handheld computing device via connection between the first docking port and the second docking port and adapted to be removable while running.. .
11/27/14
20140347809

Semiconductor device


A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board.
11/20/14
20140343375

Method and circuit for storing and providing historical physiological data


Embodiments of the present invention include systems and methods that relate to pulse oximetry. Specifically, one embodiment includes an oximeter sensor comprising a light emitting element configured to emit light, a light detector configured to detect the light, and a memory chip having a built-in trimmed resistor, the trimmed resistor having a resistance value that is detectable by a monitor..
11/13/14
20140337681

Data writing method, memory storage device, and memory controller


A data writing method, a memory storage device, and a memory controller for controlling a rewritable non-volatile memory module are provided. The rewritable non-volatile memory module includes at least one memory chip, and each memory chip includes a plurality of physical erasing units.
11/13/14
20140337579

Entertainment memory device


A digital memory device comprising: stick shaped memory chip; and read only memory. The digital memory device provides a means to store digital audio and video files for playback..
11/06/14
20140331005

Memory system and bus switch


A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an mpu that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.. .
11/06/14
20140328104

Semiconductor device


A logic chip and memory chip stacked over the logic chip, the logic chip having a first surface facing the memory chip and a second surface opposite to the first surface and including: first and second internal input/output circuit units for exchanging signals; first external input/output circuit unit for exchanging signals through first external input/output pads formed according to an external interface standard of a first memory over the second surface; and second external input/output circuit unit for exchanging signals through second external input/output pads formed according to an external interface standard of a second memory over the second surface, wherein semiconductor device operates in one of a first mode in which the first internal input/output circuit unit and the first external input/output circuit unit are enabled and a second mode in which the first and second internal input/output circuit units and the second external input/output circuit unit are enabled.. .
11/06/14
20140327138

Semiconductor device


The long sides of a rectangular control chip and the long sides of a rectangular memory chip are arranged parallel with first sides of the upper surface of a wiring substrate in a bga. A lid includes a pair of first brims and a pair of second brims, the widths of the second brims are formed wider than those of the first brims, and a mounting area for mounting chip parts and a junction base area for joining the lid are secured outside the short sides of the control chip mounted on the upper surface of the wiring substrate and outside the short sides of the memory chip mounted on the upper surface of the wiring substrate, which enables the wide-width second brims of the lid to be disposed on the junction base area.
10/30/14
20140325148

Data storage devices which supply host with data processing latency information, and related data processing methods


A method is for operating a data storage device including a plurality of memory chips. The method includes generating state information regarding the plurality of memory chips, storing the generated state information in a memory, receiving an access command from a host, analyzing the state information in response to the access command, and transmitting a response to the host indicative of whether the access command is performed based on the analyzed state information..
10/30/14
20140325127

Storage system comprising flash memory modules subject to two wear-leveling processes


A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip.
10/30/14
20140325124

Memory operating a memory system


A memory system for storing data in a plurality n of memory chips. The memory system includes a number k of sets of memory chips, wherein each set of the k sets includes a number m of the memory chips, with n=k·m; and one signal processing unit having a number l of signal processing engines for signal processing data of the n memory chips and having a data link interface for interfacing each of the k sets..
10/30/14
20140321208

De-duplication in flash memory module


Data capacity efficiency is improved by de-duplicating data assigned with a code that is different for each data. A storage apparatus comprising a flash memory control device equipped with one or more flash memory modules, wherein the flash memory module comprises at least one flash memory chip for providing a storage area, and a controller for controlling writing/reading of data including user data and a guarantee code accompanying the user data to and from the storage area provided by the flash memory chip, wherein the controller respectively divides a plurality of the data having the common user data into the user data and the guarantee code, stores one of the user data in an area of a predetermined unit of the storage area, and links and stores each of the guarantee codes accompanying the plurality of user data in an area of a predetermined unit of the storage area..
10/30/14
20140321186

Stacked memory with redundancy


A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations.
10/23/14
20140313808

Content addressable memory chip


A content addressable memory chip which can perform a high speed search with less error is provided. A match amplifier zone determines coincidence or non-coincidence of search data with data stored in the content addressable memory cells in an entry of a cam cell array, according to the voltage of a match line.
10/23/14
20140312488

Method of manufacturing wiring board unit, manufacturing insertion base, wiring board unit, and insertion base


A method of manufacturing a wiring board unit, the wiring board unit including a semiconductor package that includes a memory chip, a wiring board on which the semiconductor package is mounted, and an insertion base inserted between the wiring board and the semiconductor package, the method includes: forming a plurality of connection portion groups in a base material, the connection portion groups each including a plurality of connection portions that each electrically connect a board-side pad of the wiring board and an external terminal of the semiconductor package to each other; forming the insertion base such that resistances of the connection portions included in the connection portion groups are adjusted in accordance with types of target memory chips; and connecting the external terminals and the board-side pads to one another by using the connection portion group selected in accordance with the type of the memory chip.. .
10/23/14
20140312403

Memory cell floating gate replacement


A nand flash memory chip is formed by depositing two n-type polysilicon layers. The upper n-type polysilicon layer is then replaced with p-type polysilicon and barrier layer in the array area only, while maintaining the upper n-type polysilicon layer in the periphery.
10/16/14
20140310576

Semiconductor memory device


According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit.
10/16/14
20140310575

Semiconductor memory device


According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit.
10/09/14
20140304461

Storage subsystem


The storage system includes a plurality of flash memory devices, each of the flash memory devices including a flash memory controller and flash memory chips, which are configured as a raid group and a storage controller, coupled to the plurality of flash memory devices, configured to receive data from a computer and send the data to a first flash memory device of the plurality of flash memory devices. The flash memory controller of the flash memory device is configured to receive the data from the storage controller and execute a parity operation using the data..
10/02/14
20140298043

Memory chip


According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.. .
10/02/14
20140293725

Memory with refresh logic to accomodate low-retention storage rows


An apparatus is disclosed that includes a memory controller chip and memory chips packaged with the memory controller chip. Each memory chip includes normal-retention storage rows that exhibit retention times greater or equal to a first time interval, and having been tested to generate information identifying low-retention storage rows that exhibit retention times less than the first time interval.
10/02/14
20140292957

Ink cartridge and producing the same


An ink cartridge includes a cartridge body defining an ink chamber, an ink supply portion provided at the cartridge body, an air flow path provided in the cartridge body, a cover, and a memory chip disposed on the cover. The cartridge body has an outer surface oriented in a first direction and an air communication port opened on the outer surface.
09/25/14
20140289453

Memory system and constructing virtual block


According to one embodiment, a virtual block is constructed according to configuration conditions that, when a plurality of physical blocks included in the virtual block are selected, the sum of the number of physical block pairs and the number of single blocks allocated from the same memory chip to one virtual block is less than or equal to a first value.. .
09/25/14
20140287541

Semiconductor chip and semiconductor device


When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy..
09/25/14
20140286074

System and memory module


A system includes: a controller, a first memory module connected to the controller through a first data bus, and a second memory module connected to the controller through a second data bus, wherein the first memory module includes: first and second memory chips; a first data terminal connected to the first data bus, and a first switch unit that electrical connects the first data terminal with either the first memory chip and the second memory chip, and the second module includes: third and fourth memory chips; a second data terminal connected to the second data bus, and a second switch unit that switches over electrical connection of the second data terminal with either the third memory chip or the fourth memory chip.. .
09/18/14
20140281168

Storage system and control for storage system


The storage system includes a plurality of storage devices and a storage controller. The storage controller stores a data request quantity indicating the data quantity of write data written to the target area in a specific period, and estimates, based on the quantity of request data and relationship information received from storage devices, the estimated data quantity written to the nonvolatile semiconductor memory chips based on the write data written to the target area in the specific period.
09/18/14
20140281160

Non-volatile semiconductor storage apparatus


According to one embodiment, apparatus includes non-volatile memory chips, and a first controller which executes processing for reading first valid data stored in a first storage region of a first non-volatile memory chip in the non-volatile memory chips, processing for storing the first valid data in a buffer memory, processing for writing the first valid data stored in the buffer memory in a second storage region of the first non-volatile memory chip, and processing for erasing data stored in the first storage region. Each of the non-volatile memory chips comprises erase blocks.
09/18/14
20140281157

Memory system, memory controller and method


According to one embodiment, a memory system includes a plurality of non-volatile memory chips and a memory controller. The memory controller controls a read operation of the memory chips, and manages correspondence relation information between a logical address included in a read command and a physical address of the memory chip.
09/18/14
20140273300

Method for forming reram chips operating at low operating temperatures


Forming a resistive memory structure at a temperature well above the operating temperature can reduce the forming voltage and create a defect distribution with higher stability and lower programming voltages. The forming temperature can be up to 200 c above the operating temperature.
09/18/14
20140269004

Method for improving data retention of reram chips operating at low operating temperatures


Programming a resistive memory structure at a temperature well above the operating temperature can create a defect distribution with higher stability, leading to a potential improvement of the retention time. The programming temperature can be up to 100 c above the operating temperature.
09/18/14
20140268980

Memory chip package, memory system having the same and driving method thereof


A memory chip package includes memory chips stacked, electrically connected one another, and configured to input and output an optical signal through an optical line formed by a via penetrating the memory chips. The memory chips input and output optical signals with different wavelengths, and each of the memory chips has an optical-electrical converter configured to convert an optical signal with a corresponding wavelength into an electrical signal and to convert an electrical signal into an optical signal with the corresponding wavelength..
09/11/14
20140258558

Transcoding on virtual machines using memory cards


The present embodiments disclose techniques for transcoding media data using a virtualized network environment. This virtual environment may be hosted on one or more memory cards which each contain one or more memory chips.
09/11/14
20140253167

Memory chip testing system and connector thereof


A memory chip testing system includes a computer, a rheostat, a voltmeter, and a connector. The computer includes a main board, a number of memory chip interfaces mounted on the main board.
09/11/14
20140252357

Semiconductor device


Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (pop) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length.
09/04/14
20140250525

Systems and methods for preventing data remanence in memory


A system for preventing data remanence in memory is provided. The system includes a computing device, a memory chip coupled to the computing device and including memory, and a heater, the heater configured to prevent data remanence in a memory by providing heat to at least a portion of the memory.
09/04/14
20140248743

Semiconductor memory modules and methods of fabricating the same


The inventive concept provides semiconductor memory modules and methods of fabricating the same. The semiconductor memory module may include a module board having a first surface and a second surface opposite to the first surface, and memory chips mounted directly on the module board by a flip-chip bonding method.
09/04/14
20140247681

Wiring configuration of a bus system and power wires in a memory chip


Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. The effective resistance on the power supply wires may be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires.
09/04/14
20140246788

Stack-type semiconductor package


Provided is a stack-type semiconductor package comprising a first semiconductor package with a first package substrate and a logic chip mounted thereon, a second semiconductor package including a second package substrate disposed on the first semiconductor package and first and second memory chips stacked on the second package substrate, and connection pads disposed between the first and second package substrates to connect the first and second semiconductor packages electrically to each other. The first package substrate has first and second edges that are substantially perpendicular to each other.
08/28/14
20140245100

Semiconductor memory device


A crc code is generated from an original data, a bch code is generated with respect to the original data and the crc code, and the original data, the crc code, and the bch code are recorded in pages selected from different planes of a plurality of memory chips. An rs code is generated from the original data across pages, a crc code is generated with respect to the rs code, a bch code is generated with respect to the rs code and the crc code, and the rs code, the crc code, the bch code are recorded in a memory chip different from a memory chip including the original data.
08/28/14
20140240913

Thermal regulation for solid state memory


A chassis for a storage system contains a digital chamber that houses conventional electronic components and a thermal chamber that houses non-volatile solid state memory such as flash memory. A temperature regulating system monitors temperature within the digital chamber to keep the components therein below their maximum junction temperature.
08/21/14
20140233335

Semiconductor devices


A plurality of memory chips each have an alert terminal that notifies the outside that the memory chip has detected a predetermined error. The plurality of memory chips are mounted on memory module 100.
08/07/14
20140217586

Package-on-package device


A package-on-package device includes memory chips side-by-side on a package substrate. Accordingly, it is possible to reduce a thickness of a semiconductor package.
07/24/14
20140204673

Flash memory module for realizing high reliability


A flash memory module may include a plurality of flash memory chips. The memory chips may include one or more blocks.
07/24/14
20140204105

Dram compression scheme to reduce power consumption in motion compensation and display refresh


Systems and methods of operating a memory controller may provide for receiving a write request from a motion compensation module, wherein the write request includes video data. A compression of the video data may be conducted to obtain compressed data, wherein the compression of the video data is transparent to the motion compensation module.


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Memory Chip topics: Memory Chip, Semiconductor, Storage Device, Semiconductor Memory, Memory Cell, Volatile Memory, Host Computer, Form Factor, Memory Cells, Data Storage, Aspect Ratio, Error Correction, Semiconductor Device, Control Unit, Crystallin

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