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Memory Chip

Memory Chip-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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Memory management system and method thereof
Korea University Research And Business Foundation
January 11, 2018 - N°20180011770

Disclosed are a memory management system and a method thereof. Restricted spare cells are optimally distributed (or allocated) into a physical region and a virtual region in a system for repairing a fault of a memory, thereby increasing a yield of a memory chip.
Solid state drive devices and storage systems having the same
Samsung Electronics Co., Ltd.
January 11, 2018 - N°20180011633

A solid state drive (ssd) device includes a first nonvolatile memory package, a second nonvolatile memory package, and a controller. The first nonvolatile memory package includes a first buffer chip and a plurality of first nonvolatile memory chips. The second nonvolatile memory package includes a plurality of second nonvolatile memory chips. The controller controls the first nonvolatile memory package and ...
Magnetic memory device
Toshiba Memory Corporation
January 04, 2018 - N°20180006212

According to one embodiment, a magnetic memory device includes a magnetic memory chip having a magnetoresistive element, a magnetic layer having first and second portions spacing out each other, the first portion covering a first main surface of the magnetic memory chip, the second portion covering a second main surface facing the first main surface of the magnetic memory chip, ...
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Ots for nvm array select lines
Hgst Netherlands B.v.
December 28, 2017 - N°20170372779

The present disclosure generally relates to non-volatile memory arrays and memory devices in which a leakage current through an ots is utilized to pre-charge a circuit of a memory chip. By running an additional wire on each side of a tile which is orthogonal to, above, or below the x and y select wires, a high value resistance material, such ...
Method and apparatus for memory access
Mediatek Inc.
December 28, 2017 - N°20170371815

Aspects of the disclosure provide an integrated circuit (ic) chip that includes interface circuits and a control circuit. The interface circuits is configured to interface the ic chip to buses that couple the ic chip with a memory chip, to drive signals onto the buses for transmission to the memory chip and to receive signals that are transmitted on the ...
Shared error detection and correction memory
Micron Technology, Inc.
December 21, 2017 - N°20170365356

Apparatuses and methods of sharing error correction memory on an interface chip are described. An example apparatus includes: at least one memory chip having a plurality of first memory cells and an interface chip coupled to the at least one memory chip and having a control circuit and a storage area. The control circuit detects one or more defective memory ...
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Packaging of high performance system topology for nand memory systems
Sandisk Technologies Llc
November 09, 2017 - N°20170323876

A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual ...
Packaging of high performance system topology for nand memory systems
Sandisk Technologies Llc
November 09, 2017 - N°20170323875

A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual ...
System-in-package module with memory
Etron Technology, Inc.
November 09, 2017 - N°20170323687

A system-in-package module with memory includes a non-memory chip, a substrate, and a memory chip. The non-memory chip has a first portion and a second portion. The substrate has a window and the substrate is electrically connected to the second portion of the non-memory chip. The memory chip is placed into the window of the substrate to electrically connect the ...
Generalized write operations verification method
Hgst Netherlands B.v.
November 09, 2017 - N°20170322927

A verification architecture described according to embodiments of the present invention validates changes made to metadata and may comprise one or more subsystems and phases. According to some embodiments, the “mkfs” volume creation utility works in cooperation with the device driver to create a file system volume by means of reservation and initialization space for metadata ...
Semiconductor apparatus, production method, and electronic apparatus
Hgst Netherlands B.v.
November 02, 2017 - N°20170317061

The present technology relates to a semiconductor apparatus, a production method, and an electronic apparatus that enable semiconductor apparatuses to be laminated and the laminated semiconductor apparatuses to be identified. A semiconductor apparatus that is laminated and integrated with a plurality of semiconductor apparatuses, includes a first penetrating electrode for connecting with the other semiconductor apparatuses and a second penetrating ...
Draining a write queue based on information from a read queue
Hgst Netherlands B.v.
November 02, 2017 - N°20170315914

A method to access a memory chip having memory banks includes processing read requests in a read queue, and when a write queue is filled beyond a high watermark, stopping the processing of the read requests in the read queue and draining the write queue until the write queue is under a low watermark. Draining the write queue include issuing ...
Method, flash memory controller, memory device for accessing flash memory
Hgst Netherlands B.v.
November 02, 2017 - N°20170315909

A method for accessing a flash memory module is provide. The flash memory module is a 3d flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least one super block of ...
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Method for accessing flash memory module and associated flash memory controller and memory device
Hgst Netherlands B.v.
November 02, 2017 - N°20170315867

A method for accessing a flash memory module is provided. The flash memory module is a 3d flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block ...
Semiconductor device having interconnection in package and method for manufacturing the same
Hgst Netherlands B.v.
October 19, 2017 - N°20170301388

A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being ...
Substrate for camera module and camera module having the same
Samsung Electro-mechanics Co., Ltd.
October 12, 2017 - N°20170294469

A substrate for a camera module includes: a first substrate; an image sensor installed on the first substrate and a memory chip installed to be embedded in the first substrate. The first substrate includes a soft substrate portion disposed at a central portion of the first substrate, and a hard substrate portion formed on upper and lower portions of the ...
Single command, multiple column-operation memory device
Rambus Inc.
October 12, 2017 - N°20170293552

A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first ...
Method and circuit for self-training of a reference voltage and memory system including the same
Samsung Electronics Co., Ltd.
October 05, 2017 - N°20170287535

A semiconductor device, includes at least a first memory chip, which includes at least a first buffer connected to receive an input signal and a reference voltage; at least a first reference voltage generator configured to output a reference voltage based on a first control code; and at least a first self-training circuit for determining an operational reference voltage to ...
Storage device
Kabushiki Kaisha Toshiba
October 05, 2017 - N°20170286000

According to one embodiment, there is provided a storage device including a control chip and a plurality of memory chips. The control chip has an input buffer common to the control chip and the plurality of memory chips and electrically connected to an external terminal. A first transmission path going through the input buffer and a second transmission path not ...
Semiconductor package
Sk Hynix Inc.
September 28, 2017 - N°20170278833

A semiconductor package may include a dram chip mounted on a substrate; an interposer stacked over the dram chip and including redistribution structures; a nonvolatile memory chip stacked over the interposer; a memory controller chip mounted on the substrate, and including a control circuit for controlling the nonvolatile memory chip and first pads and second pads electrically coupled to the ...
Storage apparatus and data access method
Huawei Technologies Co., Ltd.
September 14, 2017 - N°20170262397

A storage apparatus includes a printed circuit board (pcb) and multiple memory chips symmetrically arranged on two sides of the pcb, where multiple memory chips on one side of the pcb form a rank, and multiple memory chips on the other side of the pcb form a rank; a memory chip includes multiple pins; multiple cables are disposed in the ...
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