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Memory Chip patents



      
           
This page is updated frequently with new Memory Chip-related patent applications. Subscribe to the Memory Chip RSS feed to automatically get the update: related Memory RSS feeds. RSS updates for this page: Memory Chip RSS RSS


Stacked semiconductor memory apparatus and test circuit therefor

Sk Hynix

Stacked semiconductor memory apparatus and test circuit therefor

Semiconductor device for parallel bit test and test method thereof

Sk Hynix

Semiconductor device for parallel bit test and test method thereof

Semiconductor device for parallel bit test and test method thereof

Toshiba

Memory chip


Date/App# patent app List of recent Memory Chip-related patents
08/20/15
20150236002 
 Multi-chip module with stacked face-down connected dies patent thumbnailMulti-chip module with stacked face-down connected dies
A microelectronic assembly can include a substrate having first and second surfaces, at least two logic chips overlying the first surface, and a memory chip having a front surface with contacts thereon, the front surface of the memory chip confronting a rear surface of each logic chip. The substrate can have conductive structure thereon and terminals exposed at the second surface for connection with a component.
Tessera, Inc.


08/20/15
20150235715 
 Stacked semiconductor memory apparatus and test circuit therefor patent thumbnailStacked semiconductor memory apparatus and test circuit therefor
A stacked semiconductor memory apparatus includes a memory module including a plurality of memory chips; and a logic circuit block with the memory module stacked thereon, configured to be electrically coupled with an interface substrate through a first terminal group and a second terminal group and to communicate with a controller, and to include a test circuit that receives a first test signal through the first terminal group from the controller and outputs the first test signal through the second terminal group in a test mode.. .
Sk Hynix Inc.


08/20/15
20150235714 
 Semiconductor device for parallel bit test and test method thereof patent thumbnailSemiconductor device for parallel bit test and test method thereof
A semiconductor device includes a plurality of memory chips and a plurality of signal selection units respectively corresponding to the plurality of memory chips, and suitable for commonly transferring test data signals from an external to a corresponding one of the plurality of memory chips during a common test mode, wherein one or more of the plurality of signal selection units may transfer the test data signals from the external to corresponding ones of the plurality of memory chips during an individual test mode, and wherein the semiconductor device may be set to the common test mode when a common test signal is enabled, and set to the individual test mode when both the common test signal and a test control signal are enabled.. .
Sk Hynix Inc.


08/20/15
20150234752 
 Memory chip patent thumbnailMemory chip
According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.. .
Kabushiki Kaisha Toshiba


08/20/15
20150234705 
 Semiconductor memory device patent thumbnailSemiconductor memory device
A crc code is generated from an original data, a bch code is generated with respect to the original data and the crc code, and the original data, the crc code, and the bch code are recorded in pages selected from different planes of a plurality of memory chips. An rs code is generated from the original data across pages, a crc code is generated with respect to the rs code, a bch code is generated with respect to the rs code and the crc code, and the rs code, the crc code, the bch code are recorded in a memory chip different from a memory chip including the original data.
Kabushiki Kaisha Toshiba


07/30/15
20150213841 
 Memory chip and memory storage device patent thumbnailMemory chip and memory storage device
A memory chip is disclosed. The memory comprises a substrate and a plurality of memory pads.
Eorex Corporation


07/23/15
20150208510 
 Thin low profile strip dual in-line memory module patent thumbnailThin low profile strip dual in-line memory module
A low profile strip dual in-line memory module (200) includes a passive interposer support structure (90) with patterned openings (91-97) formed between opposing top and bottom surfaces, a plurality of memory chips (d1-d8) attached to the top and bottom surfaces, and vertical solder ball conductors (98) extending through the patterned openings to electrically connect the plurality of memory chips, where each memory chip has an attachment surface facing the passive interposer structure and a patterned array of horizontal conductors (e.g., 82-86) formed on the attachment surface with contact pads electrically connected to the plurality of vertical conductors to define at least one bus conductor that is electrically connected to each memory die in the first and second plurality of memory die.. .
Freescale Semiconductor, Inc.


07/23/15
20150208124 
 Smart television system and turn-on and turn-off method thereof patent thumbnailSmart television system and turn-on and turn-off method thereof
A smart television, and a turn-off method and a turn-on method for the smart television system are provided. The smart television system includes a remote controller and a smart television.
Mstar Semiconductor, Inc.


07/23/15
20150207565 
 Interface circuit for transmitting and receiving signals between electronic devices, and semiconductor memory chip and operation processing device including the same patent thumbnailInterface circuit for transmitting and receiving signals between electronic devices, and semiconductor memory chip and operation processing device including the same
An interface circuit configured to transmit and receive signals between electronic devices is provided. The interface circuit includes an optical connection protocol manager configured to serialize a parallel transmission packet electrical signal generated based on output data to generate a serialized transmission packet electrical signal, parallelize a serial reception packet electrical signal to generate a parallelized reception packet electrical signal, and parse the parallelized reception packet electrical signal according to whether there is an error in the parallelized reception packet electrical signal to generate input data; and an electro-optical converter configured to convert the serialized transmission packet electrical signal into a transmission packet optical signal to output the transmission packet optical signal, receive a reception packet optical signal, and convert the reception packet optical signal into the serial reception packet electrical signal to provide the serial reception packet electrical signal to the optical connection protocol manager..
Electronics And Telecommunications Research Institute


07/23/15
20150206866 
 Semiconductor package and methods of forming same patent thumbnailSemiconductor package and methods of forming same
An embodiment package-on-package (pop) device includes a fan-out structure, one or more memory chips, and a plurality of connectors bonding the one or more memory chips to the fan-out structure. The fan-out structure includes a logic chip, a molding compound encircling the logic chip, and a plurality of conductive pillars extending through the molding compound..
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206865 

Integrated circuit package and methods of forming same


An embodiment package-on-package (pop) device includes a package structure, a package substrate, and a plurality of connectors bonding the package structure to the package substrate. The package structure includes a logic chip bonded to a memory chip, a molding compound encircling the memory chip, and a plurality of conductive studs extending through the molding compound.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206849 

System-in-package module and manufacture a system-in-package module


A system-in-package module includes a non-memory chip, a bundled memory, and an encapsulation package material. The non-memory chip has a plurality of pads.
Etron Technology, Inc.


07/23/15
20150201880 

Integrated injection system and communication device


An integrated system for injection including an injection device (10) in electronic connection with a communication device (a) is provided. The external communication device may be a handheld electronic device such as a smartphone or a dedicated reader such as a reader capable of reading information contained on an rfid tag.
Becton Dickinson France S.a.s.


07/16/15
20150200008 

Semiconductor package and electronic apparatus


According to one embodiment, a semiconductor package includes a package substrate, a controller chip, a semiconductor memory chip, a temperature sensor, a seal portion, and a plurality of solder balls. The controller chip and the semiconductor memory chip are provided on a first surface of the package substrate.
Kabushiki Kaisha Toshiba


07/16/15
20150199266 

3dic memory chips including computational logic-in-memory for performing accelerated data processing


This disclosure relates to a three-dimensional (3d) integrated circuit (3dic) memory chip including computational logic-in-memory (lim) for performing accelerated data processing. Related memory systems and methods are also disclosed.
Carnegie Mellon University


07/09/15
20150193308 

Memory chips and data protection methods


A memory chip coupled to a host includes a memory and a controller. Multiple boot images having the same content are pre-loaded in the memory.
Via Technologies, Inc.


07/02/15
20150187682 

Semiconductor device


A semiconductor device is reduced in size. The semiconductor device includes a die pad, a plurality of leads arranged around the die pad, a memory chip and a power source ic chip mounted over the die pad, a logic chip mounted over the memory chip, a plurality of down bonding wires for connecting the semiconductor chip to the die pad, a plurality of lead wires for connecting the semiconductor chip to leads, and a plurality of inter-chip wires.
Renesas Electronics Corporation


07/02/15
20150187399 

Pulse mechanism for memory circuit interruption


In a memory system where multiple memory chips communicate their ready/busy status on a shared bus line, a pulse mechanism is used for the individual memory chips to indicate their ready/busy status to the controller. In one example, the controller assigns pulse durations of differing lengths to the memory dies to allow the controller to distinguish between them.
Sandisk Technologies Inc.


06/25/15
20150179285 

Detecting defective connections in stacked memory devices


A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error.
International Business Machines Corporation


06/25/15
20150179280 

Detecting defective connections in stacked memory devices


A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error.
International Business Machines Corporation


06/25/15
20150178197 

Addressing auto address assignment and auto-routing in nand memory network


A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device.
Sandisk Technologies Inc.


06/25/15
20150178187 

Single command, multiple column-operation memory device


A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values..
Rambus Inc.


06/25/15
20150177993 

Memory system and bank interleaving method


According to embodiments, a memory system includes a plurality of memory chips configuring banks, an instruction generator, and a memory controller. The instruction generator generates a plurality of instructions.
Kabushiki Kaisha Toshiba


06/04/15
20150155042 

Semiconductor memory device


A nand dc-dc converter includes two output terminals. Each output terminal is connected to several multi-chip packages in each of which a plurality of nand flash memory chips are provided.
Kabushiki Kaisha Toshiba


06/04/15
20150155020 

Semiconductor apparatus


A semiconductor apparatus includes a logic memory chip including a transmission block which outputs input signals and a strobe signal; and a plurality of memory chips stacked with the logic memory chip. At least one of the plurality of memory chips includes a plurality of reception blocks.
Sk Hynix Inc.


06/04/15
20150154129 

Memory system having a plurality of types of memory chips and a memory controller for controlling the memory chips


A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller.
Fujitsu Semiconductor Limited


06/04/15
20150150495 

System and facilitating sensor and monitor communication


Embodiments disclosed herein may include an adapter which is capable of converting signals from an oximeter sensor such that the signals are readable by an oximeter monitor. In an embodiment, the adapter is capable of converting signals relating to calibration information from the oximeter sensor.
Covidien Lp


05/21/15
20150143155 

Data storage apparatus


A data storage apparatus includes a controller including a controller input/output unit suitable for receiving a ready/busy delay signal and generating a ready/busy output signal in response to a first control signal, and a memory chip including a memory input/output unit suitable for receiving a chip enable delay signal and generating a chip enable output signal in response to a second control signal. The ready/busy delay signal and the chip enable delay signal are transmitted through a substantially same transmission line..
Sk Hynix Inc.


05/14/15
20150131397 

Memory system and assembling memory system


According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores therein second information for determining an effective bit of the n-bit first information, and a control unit that determines an effective bit of the n-bit first information and an effective bit of the chip address based on the second information.. .

05/07/15
20150127914 

Semiconductor memory device, memory system and operating the same


A memory system including a plurality of memory chips is provided. The memory system includes a first memory chip and a second memory chip that share a data bus and become active by a chip enable signal, and a controller transmitting multi chip select commands to the first and second memory chips.
Sk Hynix Inc.


04/30/15
20150121030 

High density memory structure


A semiconductor memory comprises a plurality of sub banks each including one or more rows of memory bit cells connected to a set of local bit lines, wherein the sub banks share a same set of global bit lines for reading/writing data from/to the memory bit cells of the sub banks. The semiconductor memory chip further comprises a plurality of switch elements for each of the sub banks, wherein each of the switch elements connects the local bit line and the global bit line of a corresponding one of the memory bit cells in the sub bank for data transmission between the local bit line and the global bit line.
Taiwan Semiconductor Manufacturing Co., Ltd.


04/30/15
20150117080 

Multi-chip package and memory system


A multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal, a second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal. The first memory chip and the second memory chip each include a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation..
Kabushiki Kaisha Toshiba


04/30/15
20150113851 

Realtime memorialization firearm attachment


A firearm accessory that includes a body that is demountably attached to a firearm, the body containing: a camera; a microphone; a memory chip; a micro-controller operable to record a user's firearm activity into the memory chip as captured by the camera and the microphone; and, a trigger-switch mechanism demountably attached to a firearm-handle operable by a user's finger to turn the contents of the body on but not off. The body disposed on a firearm further includes a plurality of electronic components operable to: record audio, video, location, time, and date, at the time of usage of a firearm; and transmit the recorded a record audio, video, location, time, and date, outside of the body through a wire, a portable memory card, or wirelessly in realtime..

04/23/15
20150113665 

Systems and methods for preventing data remanence in memory


A system for preventing data remanence in memory is provided. The system includes a computing device, a memory chip coupled to the computing device and including memory, and a heater, the heater configured to prevent data remanence in a memory by providing heat to at least a portion of the memory.
Elwha Llc


04/23/15
20150113356 

System-in-package module with memory


A system-in-package module with memory includes a non-memory chip, a substrate, and a memory chip. The non-memory chip has a first portion and a second portion.
Etron Technology, Inc.


04/23/15
20150108657 

Electronic device


A semiconductor device and electronic device comprising the same includes at least one dummy chip having at least one through silicon via (tsv), and at least one active chip connected to the at least one dummy chip. The at least one active chip exchanges an electrical signal through the at least one tsv.
Samsung Electronics Co., Ltd.


04/09/15
20150100721 

Storage system and control for storage system


The storage system includes a plurality of storage devices and a storage controller. The storage controller stores a data request quantity indicating the data quantity of write data written to the target area in a specific period, and estimates, based on the quantity of request data and relationship information received from storage devices, the estimated data quantity written to the nonvolatile semiconductor memory chips based on the write data written to the target area in the specific period.
Hitachi, Ltd.


04/02/15
20150095556 

Memory system


A memory system includes a first memory chip, a second memory chip, and a memory controller. The first memory chip and the second memory chip are connected to the memory controller via a plurality of data lines including a first data line and a second data line.
Kabushiki Kaisha Toshiba


04/02/15
20150092509 

Semiconductor apparatus and chip id generation method thereof


Provided is a semiconductor apparatus including a plurality of memory chips which are sequentially stacked. Each of the memory chips includes: a temperature sensor configured to sense the temperature of the memory chip; and a chip id output unit configured to generate a chip id for the memory chip based on an output of the temperature sensor..
Sk Hynix Inc.


03/26/15
20150085577 

Flash memory module for realizing high reliability


A flash memory module may include a plurality of flash memory chips. The memory chips may include one or more blocks.
Hitachi, Ltd.


03/26/15
20150084166 

Semiconductor device having plural memory chip


A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip.
Ps4 Luxco S.a.r.l.


03/19/15
20150078094 

Memory chip, memory device, and reading method


A memory chip includes a memory cell array having a plurality of memory cells connected to word lines and bit lines, and a sense amplifier configured to detect data stored in a memory cell that is connected to a selected one of the word lines and a selected one of the bit lines, and a control circuit configured to read data from the memory cell in a first read mode when a first command is received and in a second read mode when a second command is received. A peak or an average value of an operation current that is flowing between power supply and ground terminals of the memory chip during a read operation in the first read mode is less than a peak or an average value of the operation current during a read operation in the second read mode..
Kabushiki Kaisha Toshiba


03/19/15
20150078055 

Memory module and manufacturing method thereof


A memory module includes a printed circuit board; first memory chips disposed in parallel with a long axis of the printed circuit board along a first column; second memory chips disposed in parallel with the long axis of the printed circuit board along a second column; and passive elements disposed between the first memory chips and the second memory chips, wherein the passive elements are connected between input/output pins of each of the first and second memory chips and tap pins.. .
Samsung Electronics Co., Ltd.


03/19/15
20150076640 

Optical module


The present optical module includes a sensor configured to pick up an image of an image pickup object, and a memory chip configured to store pixel data read out from the sensor and having the sensor joined thereto. The memory chip is connected to a substrate by a connection portion by flip-chip connection.

03/12/15
20150074346 

Memory controller, memory module and memory system


A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.. .
Mediatek Inc.


03/12/15
20150074342 

Method for managing storage system using flash memory, and computer


To facilitate the management of a storage system that uses a flash memory as a storage area. A controller of the storage system provided with a flash memory chip manages a surplus capacity value of the flash memory chip, and transmits a value based on the surplus capacity value to a management server, on the basis of at least one of a definition of a parity group, a definition of an internal lu, and a definition of a logical unit.
Hitachi, Ltd.


03/12/15
20150074331 

Nonvolatile memory package and nonvolatile memory chip


A nonvolatile memory package of an embodiment includes: a data terminal configured to receive a write command for a data; a first ce terminal; a second ce terminal; a ce selection terminal; and a selector coupled to the first ce terminal and the second ce terminal. The selector outputs one of a first chip-enable signal and a second chip-enable signal based on a ce selection signal.
Kabushiki Kaisha Toshiba


03/12/15
20150071021 

Accessing independently addressable memory chips


A method of accessing rows and columns stored in a memory system that include memory chips that can be individually addressed and accessed is described. In order to leverage this capability, prior to performing a row-write request on the memory system, a computer system may transform the rows and the columns in a matrix.
Oracle International Corporation


03/12/15
20150069633 

Semiconductor device and memory device


A semiconductor device includes a substrate, a controller chip, and memory chips. Wiring is formed on the substrate.
Kabushiki Kaisha Toshiba


03/05/15
20150067291 

Controller, memory system, and method


According to the embodiments, a controller includes an arbiter, a command fetch unit, and a processing unit. The arbiter executes a retrieval process.
Kabushiki Kaisha Toshiba


03/05/15
20150067236 

Memory system


According to one embodiment, the memory controller outputs a first command, then outputs n pieces of second commands to first and second memory chips, and reads out the read data from the first and second memory chips. First time is for reading out the read data from a memory cell array to a buffer, and second time is for transferring data of the one-nth of the read data from the buffer to the memory controller.
Kabushiki Kaisha Toshiba


02/26/15
20150058664 

Dynamic memory cell replacement using column redundancy


A memory chip comprises a main memory array having a plurality of memory columns, a redundancy memory column associated with the main memory array, and a hit logic circuitry configured to generate a plurality of hit logic signals by a plurality of hit logic units in the hit logic circuitry to enable dynamic replacement of a defective memory cell in one of the memory columns for dynamic replacement by the redundancy memory column when the memory array is in operation.. .
Taiwan Semiconductor Manufacturing Co., Ltd.


02/26/15
20150055419 

Controller, memory system, and method


According to one embodiment, a memory system includes a memory chip and a controller. The controller is configured to count a first elapsed time from a start of an erase process when causing the memory chip to execute the erase process.
Kabushiki Kaisha Toshiba


02/19/15
20150048521 

Semiconductor package


According to example embodiments, a semiconductor package includes a first and a second semiconductor package. The first semiconductor package includes a first package substrate, first and second memory chips spaced apart from each other on the first package substrate in a first direction, third and fourth memory chips on the first and second memory chips, respectively, and first and second jumper chips on the first and second memory chips, respectively.

02/12/15
20150046612 

Memory device formed with a semiconductor interposer


A packaged memory device includes a semiconductor interposer, a first memory stack, a second memory stack, and a buffer chip that are all coupled to the semiconductor interposer. The first memory stack and the second memory stack each include multiple memory chips that are configured as a single stack.
Nvidia Corporation


02/05/15
20150039921 

Memory system and memory chip


A memory system includes a memory which asserts a high-power-consumption operation output when an amount of the power consumption is high in internal operations in respective operations, and a controller which has an interface function between a host and the memory and receives the high-power-consumption operation output. The controller switches an operation mode thereof to a low power consumption mode when the high-power-consumption operation output is asserted..
Kabushiki Kaisha Toshiba


02/05/15
20150039820 

Flash memory storage system and controller and data writing method thereof


A flash memory storage system having a flash memory controller and a flash memory chip is provided. The flash memory controller configures a second physical unit of the flash memory chip as a midway cache physical unit corresponding to a first physical unit and temporarily stores first data corresponding to a first host write command and second data corresponding to a second host write command in the midway cache physical unit, wherein the first and second data corresponding to slow physical addresses of the first physical unit.
Phison Electronics Corp.


01/29/15
20150028517 

Identification device for a pneumatic spring


An identification device (1) for a pneumatic spring (2) includes an rfid transponder (8), which is completely embedded into the elastomer matrix (13) of the flexible member (4). An electromagnetic field is generated by a read device (9), wherein the energy necessary for supplying the rfid transponder (8) is taken from the electromagnetic field generated by the read device (9).
Contitech Luftfedersysteme Gmbh


01/15/15
20150016047 

Memory module


A memory module that includes: a printed circuit board having a connecting terminal; memory chips arranged on the printed circuit board; data buffers disposed on a first surface of the printed circuit board and corresponding to the memory chips; and resistance units disposed on a second surface of the printed circuit board and corresponding to the data buffers.. .
Samsung Electronics Co., Ltd.


01/15/15
20150016046 

Ina cabled memory appliance


According to one general aspect, an apparatus may include an expansion memory device, a connection printed circuit board, and a connection cable. The expansion memory device may include a plurality of memory chips.
Samsung Electronics Co., Ltd.


01/08/15
20150009769 

Dram sub-array level refresh


A memory controller coupled to a memory chip having a number of sub-arrays of memory cells is configured to determine a configuration of the memory chip. The memory controller is configured to read the sub-array configuration of the memory chip and to detect sub-array level conflicts between external commands and refresh operations.
Qualcomm Incorporated


01/01/15
20150006806 

Double data rate synchronous dynamic random access memory module and configuring method thereof


Disclosed are a double data rate synchronous dynamic random access memory module and a configuring method thereof. The ddr sdram module in accordance with an embodiment of the present invention includes: a plurality of memory chips; and a serial transceiver portion configured to serially receive first serial data including a control signal and data transferred from outside for the plurality of memory chips and to provide the control signal and the data included in the serially received first serial data to the plurality of memory chips..
Electronics And Telecommunications Research Institute


01/01/15
20150003172 

Memory module including buffer chip controlling refresh operation of memory devices


Provided is a memory module including a buffer chip controlling refresh operations. The buffer chip issues a hidden refresh command controlling refresh operations for the memory chips, and outputs a wait signal indicating that the memory chips are in refresh..

01/01/15
20150001538 

Semiconductor device and a manufacturing the same


A device featuring a substrate configured to include an upper surface and an opposing lower surface and, in parallel, a first and an opposing second peripheral edge, the first peripheral edge being smaller in length than the second peripheral edge, one or more semiconductor chip mounted over the upper surface of the substrate, a control semiconductor chip mounted over the upper surface of the substrate, a sealing resin covering the memory and control chips, and a plurality of external terminals provided over the lower surface of the substrate, the external terminals being arranged in a line along the first peripheral edge. The external terminals are used to fit the device to an electronic apparatus.
Ps4 Luxco S.a.r.l.


12/25/14
20140374900 

Semiconductor package and fabricating the same


A semiconductor package includes memory i/o bumps and power/ground voltage bumps which are disposed at different positions from each other. In the semiconductor package, memory chips are disposed side by side, and a passivation layer is interposed between a conductive pad and a bump..

12/18/14
20140371945 

Information processing apparatus, controlling the same and program


An information processing apparatus according to an aspect of the present invention generates temperature distribution information (updated temperature information) that indicates the current temperature distribution in a memory chip, based on predetermined temperature information generated by an analysis executed in advance and temperature information obtained by a temperature sensor. The predetermined temperature information includes information related to the temperature distribution in the memory chip that corresponds to the operating states of an soc die and a wide io memory device.
Canon Kabushiki Kaisha


12/11/14
20140364771 

Pressure sensitive assemblies for limiting movements adverse to health or surgical recovery


Pressure sensitive devices, systems and methods for alerting a user of movements potentially adverse to health or surgical recovery are disclosed. The pressure sensitive device may include a force sensor placed along the anterior aspect of a hand; and a vibration motor in communication with the force sensor in close proximity to the user, e.g., along the posterior aspect of the wrist.

12/04/14
20140359200 

High performance system topology for nand memory systems


A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device.

12/04/14
20140357021 

Multi-chip module with stacked face-down connected dies


A microelectronic assembly can include a substrate having first and second surfaces, at least two logic chips overlying the first surface, and a memory chip having a front surface with contacts thereon, the front surface of the memory chip confronting a rear surface of each logic chip. The substrate can have conductive structure thereon and terminals exposed at the second surface for connection with a component.

12/04/14
20140355370 

Semiconductor system and semiconductor package


A semiconductor system includes a plurality of memory chips. Each of the memory chips includes an oscillator suitable for generating a periodic wave in a self refresh mode, and a delay unit suitable for delaying the periodic wave to generate a refresh pulse and for setting a delay value based on a corresponding chip identification..

12/04/14
20140355363 

Memory chip and semiconductor package including the same


A memory chip includes a data processing block suitable for serial-parallel converting data inputted and for parallel-serial converting data to be outputted, a write data transmitting unit suitable for transmitting the data serial-parallel converted by the data processing block to a write data interlayer channel, a write data receiving unit suitable for receiving data from the write data interlayer channel, the data to be written to a core area, a read data receiving unit suitable for receiving data from a read data interlayer channel, the data to be parallel-serial converted by the data processing block, and a read data transmitting unit suitable for transmitting data read from the core area to the read data interlayer channel.. .

12/04/14
20140355325 

Packaging of high performance system topology for nand memory systems


A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device.

12/04/14
20140353516 

Optical sensors for monitoring biopharmaceutical solutions in single-use containers


Disposable, pre-sterilized, and pre-calibrated, pre-validated sensors are provided. The sensor comprises a disposable fluid conduit or bioreactor bag and a reusable sensor assembly.

11/27/14
20140351525 

Efficient memory accesses in a multi-core processor


A method of providing memory accesses for a multi-core processor includes reserving a group of pins of a multi-core processor to transmit either data or address information in communication with one or more memory chips, receiving memory access requests from the plurality of processor cores, determining granularity of the memory access requests by a memory controller, and dynamically adjusting the number of pins in the group of pins to be used to transmit address information based with the granularity of the memory access requests.. .

11/27/14
20140350415 

Method and circuit for storing and providing historical physiological data


Embodiments of the present invention include systems and methods that relate to pulse oximetry. Specifically, one embodiment includes an oximeter sensor comprising a light emitting element configured to emit light, a light detector configured to detect the light, and a memory chip having a built-in trimmed resistor, the trimmed resistor having a resistance value that is detectable by a monitor..

11/27/14
20140349708 

Computing device with removable processing unit


A handheld tablet computing device with a removable central processor module has a first plurality of user interface elements comprising at least a screen, a keyboard, and a pointing device, a first communications link software module resident in a read-only firmware memory chip; a first docking port located on an interior surface of a void extending inward from one of the exterior surfaces of the handheld computing device; and a user-removable processing unit comprising at least a central processor module, a data storage module, a second communications link software module, a second docking port, and a second plurality of user interface elements, the user-removable processing unit being removably coupled to the handheld computing device via connection between the first docking port and the second docking port and adapted to be removable while running.. .

11/27/14
20140347809 

Semiconductor device


A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board.

11/20/14
20140343375 

Method and circuit for storing and providing historical physiological data


Embodiments of the present invention include systems and methods that relate to pulse oximetry. Specifically, one embodiment includes an oximeter sensor comprising a light emitting element configured to emit light, a light detector configured to detect the light, and a memory chip having a built-in trimmed resistor, the trimmed resistor having a resistance value that is detectable by a monitor..

11/13/14
20140337681 

Data writing method, memory storage device, and memory controller


A data writing method, a memory storage device, and a memory controller for controlling a rewritable non-volatile memory module are provided. The rewritable non-volatile memory module includes at least one memory chip, and each memory chip includes a plurality of physical erasing units.

11/13/14
20140337579 

Entertainment memory device


A digital memory device comprising: stick shaped memory chip; and read only memory. The digital memory device provides a means to store digital audio and video files for playback..

11/06/14
20140331005 

Memory system and bus switch


A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an mpu that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.. .

11/06/14
20140328104 

Semiconductor device


A logic chip and memory chip stacked over the logic chip, the logic chip having a first surface facing the memory chip and a second surface opposite to the first surface and including: first and second internal input/output circuit units for exchanging signals; first external input/output circuit unit for exchanging signals through first external input/output pads formed according to an external interface standard of a first memory over the second surface; and second external input/output circuit unit for exchanging signals through second external input/output pads formed according to an external interface standard of a second memory over the second surface, wherein semiconductor device operates in one of a first mode in which the first internal input/output circuit unit and the first external input/output circuit unit are enabled and a second mode in which the first and second internal input/output circuit units and the second external input/output circuit unit are enabled.. .

11/06/14
20140327138 

Semiconductor device


The long sides of a rectangular control chip and the long sides of a rectangular memory chip are arranged parallel with first sides of the upper surface of a wiring substrate in a bga. A lid includes a pair of first brims and a pair of second brims, the widths of the second brims are formed wider than those of the first brims, and a mounting area for mounting chip parts and a junction base area for joining the lid are secured outside the short sides of the control chip mounted on the upper surface of the wiring substrate and outside the short sides of the memory chip mounted on the upper surface of the wiring substrate, which enables the wide-width second brims of the lid to be disposed on the junction base area.

10/30/14
20140325148 

Data storage devices which supply host with data processing latency information, and related data processing methods


A method is for operating a data storage device including a plurality of memory chips. The method includes generating state information regarding the plurality of memory chips, storing the generated state information in a memory, receiving an access command from a host, analyzing the state information in response to the access command, and transmitting a response to the host indicative of whether the access command is performed based on the analyzed state information..

10/30/14
20140325127 

Storage system comprising flash memory modules subject to two wear-leveling processes


A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip.

10/30/14
20140325124 

Memory operating a memory system


A memory system for storing data in a plurality n of memory chips. The memory system includes a number k of sets of memory chips, wherein each set of the k sets includes a number m of the memory chips, with n=k·m; and one signal processing unit having a number l of signal processing engines for signal processing data of the n memory chips and having a data link interface for interfacing each of the k sets..

10/30/14
20140321208 

De-duplication in flash memory module


Data capacity efficiency is improved by de-duplicating data assigned with a code that is different for each data. A storage apparatus comprising a flash memory control device equipped with one or more flash memory modules, wherein the flash memory module comprises at least one flash memory chip for providing a storage area, and a controller for controlling writing/reading of data including user data and a guarantee code accompanying the user data to and from the storage area provided by the flash memory chip, wherein the controller respectively divides a plurality of the data having the common user data into the user data and the guarantee code, stores one of the user data in an area of a predetermined unit of the storage area, and links and stores each of the guarantee codes accompanying the plurality of user data in an area of a predetermined unit of the storage area..

10/30/14
20140321186 

Stacked memory with redundancy


A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations.

10/23/14
20140313808 

Content addressable memory chip


A content addressable memory chip which can perform a high speed search with less error is provided. A match amplifier zone determines coincidence or non-coincidence of search data with data stored in the content addressable memory cells in an entry of a cam cell array, according to the voltage of a match line.

10/23/14
20140312488 

Method of manufacturing wiring board unit, manufacturing insertion base, wiring board unit, and insertion base


A method of manufacturing a wiring board unit, the wiring board unit including a semiconductor package that includes a memory chip, a wiring board on which the semiconductor package is mounted, and an insertion base inserted between the wiring board and the semiconductor package, the method includes: forming a plurality of connection portion groups in a base material, the connection portion groups each including a plurality of connection portions that each electrically connect a board-side pad of the wiring board and an external terminal of the semiconductor package to each other; forming the insertion base such that resistances of the connection portions included in the connection portion groups are adjusted in accordance with types of target memory chips; and connecting the external terminals and the board-side pads to one another by using the connection portion group selected in accordance with the type of the memory chip.. .

10/23/14
20140312403 

Memory cell floating gate replacement


A nand flash memory chip is formed by depositing two n-type polysilicon layers. The upper n-type polysilicon layer is then replaced with p-type polysilicon and barrier layer in the array area only, while maintaining the upper n-type polysilicon layer in the periphery.

10/16/14
20140310576 

Semiconductor memory device


According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit.

10/16/14
20140310575 

Semiconductor memory device


According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit.

10/09/14
20140304461 

Storage subsystem


The storage system includes a plurality of flash memory devices, each of the flash memory devices including a flash memory controller and flash memory chips, which are configured as a raid group and a storage controller, coupled to the plurality of flash memory devices, configured to receive data from a computer and send the data to a first flash memory device of the plurality of flash memory devices. The flash memory controller of the flash memory device is configured to receive the data from the storage controller and execute a parity operation using the data..

10/02/14
20140298043 

Memory chip


According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.. .

10/02/14
20140293725 

Memory with refresh logic to accomodate low-retention storage rows


An apparatus is disclosed that includes a memory controller chip and memory chips packaged with the memory controller chip. Each memory chip includes normal-retention storage rows that exhibit retention times greater or equal to a first time interval, and having been tested to generate information identifying low-retention storage rows that exhibit retention times less than the first time interval.

10/02/14
20140292957 

Ink cartridge and producing the same


An ink cartridge includes a cartridge body defining an ink chamber, an ink supply portion provided at the cartridge body, an air flow path provided in the cartridge body, a cover, and a memory chip disposed on the cover. The cartridge body has an outer surface oriented in a first direction and an air communication port opened on the outer surface.



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Memory Chip topics: Memory Chip, Semiconductor, Storage Device, Semiconductor Memory, Memory Cell, Volatile Memory, Host Computer, Form Factor, Memory Cells, Data Storage, Aspect Ratio, Error Correction, Semiconductor Device, Control Unit, Crystallin

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