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Memory Chip

Memory Chip-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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Storage apparatus and data access method
Huawei Technologies Co., Ltd.
September 14, 2017 - N°20170262397

A storage apparatus includes a printed circuit board (pcb) and multiple memory chips symmetrically arranged on two sides of the pcb, where multiple memory chips on one side of the pcb form a rank, and multiple memory chips on the other side of the pcb form a rank; a memory chip includes multiple pins; multiple cables are disposed in the ...
Memory module repair system with failing component detection and method of operation thereof
Smart Modular Technologies, Inc.
September 14, 2017 - N°20170262337

A memory module repair system, and a method of operation thereof, including: a memory controller; a volatile memory having memory chips coupled to the memory controller, the memory controller for testing the volatile memory; an ecc controller, coupled to the memory controller, for determining a failing bit location information of a failing bit within the volatile memory; and an error ...
Memory module with packages of stacked memory chips
Netlist, Inc.
September 07, 2017 - N°20170256291

A memory module is operable in a computer system to communicate with a system memory controller via a command/address bus and a data bus. The memory module comprises a register device coupled to the command/address bus, and a plurality of dram packages coupled to the data bus and to the register device via a set of module control ...
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Information processing device, semiconductor device, and memory inspection method
Fujitsu Limited
August 24, 2017 - N°20170242750

An information processing device includes: a processor that executes processing of data; and a memory module that includes a first memory in which a plurality of memory chips each storing the data are mounted in layers, and a memory controller that controls the first memory, wherein the memory controller: inspects the data; executes correction processing of the data when a ...
Memory chip and operating method thereof
Sk Hynix Inc.
August 17, 2017 - N°20170236588

There are provided a memory chip and an operating method thereof. A memory chip includes a main memory block including a plurality of sub-memory blocks, a peripheral circuit for programming memory cells included in the sub-memory blocks in units of pages, and a control circuit for controlling the peripheral circuit such that, after a program operation of a sub-memory block ...
Adaptable gun safety system
Sk Hynix Inc.
August 17, 2017 - N°20170234637

A firearm with identification, safety system, preventing use by an unauthorized user. The firearm includes a scanner capable of scanning a middle and ring finger on the grip of the gun; a memory chip means for means for storing data representative of at least one fingerprint; a microprocessor connected to said scanner and said memory chip for receiving and transmitting ...
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Memory system
Sk Hynix Inc.
August 03, 2017 - N°20170220294

A memory system includes a memory controller, a first memory module including first and second groups of first memory chips, a second memory module including first and second groups of second memory chips, and a channel including a first group of signal lines suitable for coupling the memory controller with the first memory module, and a second group of signal ...
Memory package, memory module including the same, and operation method of memory package
Sk Hynix Inc.
August 03, 2017 - N°20170220293

Disclosed is a memory package. The memory package includes a nonvolatile memory chip, a volatile memory chip of which an access speed is faster than an access speed of the nonvolatile memory chip, and a logic chip for performing a refresh operation about the volatile memory chip in response to a refresh command from an external device, and migrating at ...
Memory system and method of operating the same
Sk Hynix Inc.
August 03, 2017 - N°20170220251

A memory system in accordance with an embodiment may include a memory chip and a controller. The memory chip may store data in a plurality of logical pages by performing a sensing operation on a selected page in response to commands and performing an output operation of the data. The controller may transmit the commands to the memory chip so ...
Short circuit detecting device of stacked memory chips and method thereof
Samsung Electronics Co., Ltd.
August 03, 2017 - N°20170219647

Disclosed are a method and a device for detecting a short circuit between adjacent micro-bumps. The method includes setting outputs of a pull-up driver and a pull-down driver of a data output circuit connected with a micro-bump to be suitable for a test type and determining whether a short circuit is generated.
Pulse mechanism for memory circuit interruption
Sandisk Technologies Llc
July 27, 2017 - N°20170212849

In a memory system where multiple memory chips communicate their ready/busy status on a shared bus line, a pulse mechanism is used for the individual memory chips to indicate their ready/busy status to the controller. In one example, the controller assigns pulse durations of differing lengths to the memory dies to allow the controller to distinguish between them. ...
Method for reduced load memory module
Invensas Corporation
July 27, 2017 - N°20170212848

A method for reducing load in a memory module. In such a method, a plurality of memory chips are coupled to a circuit platform. Each memory chip of the plurality of memory chips each has a plurality of memory dies. At least one controller is coupled to the circuit platform and further coupled to the plurality of memory chips for ...
Memory device and method of operating the same
Sk Hynix Inc.
July 20, 2017 - N°20170206037

Disclosed herein is a memory system including: a plurality of memory chips coupled to a plurality of input/output lines included in a channel and output ready/busy signals to the input/output lines in response to a status check command; and a memory controller configured to transmit the status check command to the memory chips through the channel and ...
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Method and apparatus for calibrating write timing in a memory system
Rambus Inc.
July 13, 2017 - N°20170200489

A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory ...
Semiconductor memory device
Renesas Electronics Corporation
July 06, 2017 - N°20170194039

A stack memory includes a base chip, a memory chip stacked over the base chip, and a via 42 provided between the base chip and the memory chip. The base chip has an external interface circuit and a late write control circuit. The external interface circuit externally receives/transmits write data and read data. The late write control circuit has at ...
Device and method for storing data in a plurality of multi-level cell memory chips
International Business Machines Corporation
July 06, 2017 - N°20170192908

A device for storing data in a plurality of multi-level cell memory chips. The device includes a scrambling unit to generate a plurality of candidate scrambled sequences of data by performing a plurality of scrambling operations on a sequence of data to be stored, a calculation unit to calculate a cost function for each of the plurality of candidate scrambled ...
Memory systems and electronic devices including nonvolatile memory modules
Samsung Electronics Co .. Ltd.
July 06, 2017 - N°20170192704

A memory system includes a nonvolatile memory module and a memory controller. The nonvolatile memory module includes a plurality of memory chips and a module controller disposed on a printed circuit board. The module controller controls operations of the plurality of memory chips. Each of the plurality of memory chips includes a plurality of nonvolatile memory cells and operates in ...
Memory module and memory system including the memory module
Sk Hynix Inc.
June 29, 2017 - N°20170185349

A memory system may include a controller and a plurality of memory modules. Each of the plurality of memory modules may include a buffer chip and a plurality of memory chips coupled to the buffer chip through independent input and output (i/o) lines. The buffer chips in the plurality of memory modules may be coupled to the controller through ...
Apparatus and method to support a storage mode over a cache-line memory interface to a ...
Intel Corporation
June 22, 2017 - N°20170177496

Provided are an apparatus and method for using block windows configured in a memory module to provide block level access to memory chips in the memory module. A plurality of block windows are configured that map to addresses corresponding to the addressable locations in the memory chips. A read/write request is received indicating a requested read or write operation ...
Video server device and writing/reading data method
Kabushiki Kaisha Toshiba
June 15, 2017 - N°20170170848

According to one embodiment, a video server device includes: a memory; and a memory controller. The memory controller includes: a first ecc encoding unit configured to add a first ecc code to each of first data units of the data block, each of the first data units written to memory chips in parallel; a second ecc encoding unit configured to ...
Semiconductor package
Samsung Electronics Co., Ltd.
June 15, 2017 - N°20170170156

A semiconductor package is provided. The semiconductor package may include a plurality of memory chips, which are mounted on a top surface of a package substrate, and a plurality of controller chips, which are vertically stacked on at least one of top and bottom surfaces of the package substrate.
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