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Memory Chip patents



      
           
This page is updated frequently with new Memory Chip-related patent applications. Subscribe to the Memory Chip RSS feed to automatically get the update: related Memory RSS feeds. RSS updates for this page: Memory Chip RSS RSS


Storage system which realizes asynchronous remote copy using cache memory composed of flash memory, and control method…

Stacked memory device, memory system including the same and method for operating the same

Data storage device and method for operating the same

Date/App# patent app List of recent Memory Chip-related patents
07/17/14
20140197505
 Shields for magnetic memory chip packages patent thumbnailnew patent Shields for magnetic memory chip packages
Chip packages are described with soft-magnetic shields that are included inside or attached externally to the package containing a mram chip. In one group of embodiments a single shield with vias for bonding wires is affixed to the surface of the mram chip having the contact pads.
07/10/14
20140195722
 Storage system which realizes asynchronous remote copy using cache memory composed of flash memory, and control method thereof patent thumbnailStorage system which realizes asynchronous remote copy using cache memory composed of flash memory, and control method thereof
The first storage apparatus provides a primary logical volume, and the second storage apparatus has a secondary logical volume. When the first storage apparatus receives a write command to the primary logical volume, a package processor in a flash package allocates first physical area in the flash memory chip to first cache logical area for write data and stores the write data to the allocated first physical area.
07/10/14
20140192606
 Stacked memory device, memory system including the same and method for operating the same patent thumbnailStacked memory device, memory system including the same and method for operating the same
A stacked memory device includes a plurality of interconnected memory chips and a controller to control the plurality of memory chips to perform refresh operations during non-overlapping time periods. Each memory chip includes a plurality of ranks, and each rank includes at least one memory bank.
07/03/14
20140189407
 Data storage device and method for operating the same patent thumbnailData storage device and method for operating the same
A data storage device and a method for operating the same are provided. In the data storage device and the method for operating the same, a predetermined number of memory chips are operated based on a usable power limitation when a power supply is supplied from a finite power supply source such as a battery, and as many memory chips as possible are operated in parallel.
07/03/14
20140189227
 Memory device and a memory module having the same patent thumbnailMemory device and a memory module having the same
A memory device is provided. The memory device includes a plurality of memory chips, and a buffer chip connected to the plurality of memory chips.
07/03/14
20140189201
 Flash memory interface using split bus configuration patent thumbnailFlash memory interface using split bus configuration
A system having a split bus flash memory and a method for operating the split bus flash memory is disclosed. The system may include a controller, a non-volatile memory (including first and second non-volatile memory chips) and the system bus.
07/03/14
20140185352
 Configurable-width memory channels for stacked memory structures patent thumbnailConfigurable-width memory channels for stacked memory structures
The disclosed embodiments provide a chip package that facilitates configurable-width memory channels. In this chip package, a semiconductor die is electrically connected to two or more memory chips.
07/03/14
20140185226
 Multi-channel memory module patent thumbnailMulti-channel memory module
Embodiments of the invention further describe a memory module having a memory card housing, first and second pluralities of memory chips/devices included in the housing, and first and second pluralities of memory module electrical i/o terminals for coupling the first and second pluralities of memory chips/devices to pcb, respectively. In embodiments of the invention, the above described first and second pluralities electrical i/o connectors are disposed on different sides of the housing..
06/26/14
20140181415
 Prefetching functionality on a logic die stacked with memory patent thumbnailPrefetching functionality on a logic die stacked with memory
Prefetching functionality on a logic die stacked with memory is described herein. A device includes a logic chip stacked with a memory chip.
06/26/14
20140177315
 Multi-level memory array having resistive elements for multi-bit data storage patent thumbnailMulti-level memory array having resistive elements for multi-bit data storage
A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device.
06/19/14
20140173170
Multiple subarray memory access
A multiple subarray-access memory system is disclosed. The system includes a plurality of memory chips, each including a plurality of subarrays and a memory controller in communication.
06/19/14
20140167134
Self-aligned vertical nonvolatile semiconductor memory device
The present invention belongs to the technical field of semiconductor memory devices and specifically relates to a self-aligned vertical nonvolatile semiconductor memory device, including: a semiconductor substrate, a drain region of a first doping type, two source regions of a second doping type, a stacked gate used to capture electrons; wherein the drain region, the two source regions and the stacked gate form two tunneling field effect transistors (tfets) sharing one gate and one drain, the drain region current of each of the tfet is affected by the quantity and distribution of the charges in the stacked gate used to capture electrons, the drain is buried in the semiconductor substrate, the source regions above the drain region are separated from the drain through a channel and separated form each other through a region of the first doping type. The semiconductor memory device of the present invention features small unit area and simple manufacturing process.
06/12/14
20140160595
Emergency power off (epo) island for saving critical data to non-volatile memory
Approaches for an emergency power off (epo) power island, for saving critical data to non-volatile memory in the event of an epo condition, for use in a hard-disk drive (hdd) storage device. The epo power island includes a controller for detecting an epo condition.
06/12/14
20140159247
3d semiconductor interposer for heterogeneous integration of standard memory and split-architecture processor
A standard memory chip (150) is vertically assembled with two processor chips (130, 140) of split architecture by means of a small silicon interposer (120) stacked onto a large silicon interposer (110); both interposers include through-silicon vias (tsvs), while the chips are free of tsvs. The tsvs of small interposer (120) connect to the memory chip (150) and to the bottom interposer (110).
06/05/14
20140157065
Method and system for providing a smart memory architecture
A smart memory system preferably includes a memory including one or more memory chips, and a processor including one or more memory processor chips. The system may include a smart memory controller capable of performing a bit error rate built-in self test.
06/05/14
20140156915
Partitioning a flash memory data storage device
A method of partitioning a data storage device that has a plurality of memory chips includes determining a number memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips, defining a second partition of the data storage device via the host where the second partition includes a second subset of the plurality of memory chips, such that the first subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the first subset.. .
06/05/14
20140153336
Semiconductor memory device having a plurality of chips and capability of outputting a busy signal
One package contains a plurality of memory chips. Each memory chip has an i/o terminal which generates a busy signal.
05/22/14
20140141543
Semiconductor device having optical fuse and electrical fuse
A method for manufacturing a stacked semiconductor memory device includes testing a plurality of memory chips to detect first defective addresses, programming optical fuses with first defective address information on each of the plurality of memory chips that have the first defective addresses, stacking the plurality of memory chips, testing the stacked memory chips to detect second defective addresses, and programming electrical fuses with second defective address information.. .
05/22/14
20140138851
Semiconductor memory chips and stack-type semiconductor packages including the same
Provided are semiconductor memory chips and semiconductor packages with the same. The semiconductor package may include a memory chip including first data pads and first command/address pads arranged adjacent to a first side region thereof and second data pads and second command/address pads arranged adjacent to a second side region thereof arranged opposite to the first side region, and a package substrate including first ca connection pads and second ca connection pads.
05/08/14
20140129906
Data and error correction code mixing device and method
Memory devices and methods are described such as those that mix data and associated error correction code blocks between multiple memory device locations. Examples include mixing between multiple memory blocks, mixing between memory pages, mixing between memory chips and mixing between memory modules.
05/08/14
20140126304
Memory system and operating method thereof
A memory system includes one or more memory chips, and a repair information storage chip including a nonvolatile memory configured to store a repair information of the one or more memory chips, wherein during an initial operation of the memory system, the repair information stored in the repair information storage chip is transmitted to the one or more memory chips.. .
05/08/14
20140124959
Memory device, laminated semiconductor substrate and method of manufacturing the same
A memory device has a laminated chip package and a controller chip. In the laminated chip package, a plurality of memory chips are laminated.
05/08/14
20140124921
Semiconductor package
A semiconductor package includes a substrate; a driving chip having first bumps on a first surface and bump pads on a second surface facing away from the first surface, and mounted to the substrate by the medium of the first bumps; a support member disposed on the substrate substantially horizontally with respect to the driving chip; and a plurality of memory chips substantially horizontally disposed on the driving chip and the support member such that one corner portions of the memory chips are positioned on the driving chip while being centered about the driving chip, wherein the respective memory chips have second bumps which are electrically connected with the respective bump pads of the driving chip, on one surfaces of the one corner portions of the memory chips which face the driving chip.. .
05/01/14
20140119150
Bipolar logic gates on mos-based memory chips
A system for using selectable-delay bipolar logic circuitry within the address decoder of a mos-based memory includes a mos-based memory, which includes an array of a plurality of memory cells configured to store data; an address decoder including bipolar logic circuitry, where the address decoder is configured to accept a word including a plurality of bits and access the array of memory cells using the word; where the bipolar logic circuitry includes a plurality of bipolar transistor devices, where at least one bipolar transistor device has an adjustable gate bias and is configured to accept an input, wherein the gate bias is adjusted based on the input, where the gate bias determines a selectable gate delay.. .
05/01/14
20140118382
Method for programming extended display identification data and display device
A method for programming extended display identification data (edid) adapted to a display device is provided. The display device has at least one edid chip, a microcontroller unit chip, and a flash memory chip.
05/01/14
20140117430
Semiconductor package
A semiconductor package includes a first substrate, a plurality of memory chips horizontally disposed on the first substrate, and having one surfaces which face the first substrate, other surfaces which face away from the one surfaces, and first bumps formed on the other surfaces, a second substrate disposed on the plurality of memory chips and electrically connected, a sub-substrate horizontally disposed on the first substrate together with the plurality of memory chips and electrically connecting the first substrate and the second substrate, and a driving chip having second bumps on one surface thereof and mounted to the second substrate such that the second bumps are electrically connected with the second substrate.. .
04/24/14
20140115230
Flash memory with data retention partition
A nand flash memory chip includes a first partition that has smaller memory cells, with smaller charge storage elements, and a second partition that has larger memory cells, with larger charge storage elements, in the same memory array. Data is selected for storage in the first or second partition according to characteristics, or expected characteristics, of the data..
04/17/14
20140109035
Layout method for printed circuit board
A layout method for a printed circuit board (pcb) is provided. A memory type of a dynamic random access memory (dram) to be mounted on the pcb is obtained.
04/17/14
20140108708
Raid configuration in a flash memory data storage device
A method of storing data in a flash memory data storage device that includes a plurality of memory chips is disclosed. The method includes determining a number of memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips and defining a second partition of the data storage device via a host coupled to the data storage device, where the second partition includes a second subset of the plurality of memory chips.
04/17/14
20140108683
Memory system that utilizes a wide input/output (i/o) interface to interface memory storage with an interposer
A memory system is provided in which at least one memory chip and a memory controller chip are mounted in a side-by-side relationship on an interposer. The memory chip is connected to the interposer via a wide i/o interface to enable the memory chip and the memory controller chip to communicate with each other via the wide i/o interface.
04/17/14
20140104946
On-chip hv and lv capacitors acting as the second back-up supplies for nvsram auto-store operation
Two on-chip capacitors including one hv capacitor vppcap and one lv vcc capacitor vcccap are built over a nvsram memory chip as a back-up second power supplies for each nvsram cell, regardless of 1-poly, 2-poly, pmos or nmos flash cell structures therein. The on-chip hv and lv capacitors are preferably made from one or more mim or mip layers for achieving required capacitance.
04/17/14
20140104920
Semiconductor device
According to one embodiment, a semiconductor device includes a processor chip, and a memory chip stacked on the processor chip with bumps and including a memory cell unit and a memory logic unit. The bumps are arranged on the memory logic unit.
04/17/14
20140104917
Semiconductor memory device including plurality of memory chips
A semiconductor memory device includes a plurality of memory chips each including a chip identification (id) generation circuit. The chip id generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip id generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip id numbers of the plurality of device chips.
04/10/14
20140101368
Binding microprocessor to memory chips to prevent re-use of microprocessor
A processor is provided that binds itself to a circuit such that the processor cannot be subsequently reused in other circuits. On a first startup of the processor, a memory segment of an external volatile memory device is read to obtain information prior to initialization of the memory segment.
04/10/14
20140099815
Memory module connector with auxiliary power
An apparatus includes a socket that receives a memory module that includes a card having card edge voltage pads along the lower card edge, auxiliary voltage pads along at least one of the vertical card edges, and one or more persistent, solid-state memory chips on one or both card faces. A latch pivotally coupled to the socket is movable between a latched position and an unlatched position.
04/10/14
20140098480
Memory module connector with auxiliary power cable
A memory module includes persistent-storage memory chips and an auxiliary voltage connector for powering the persistent-storage memory chips. An auxiliary power cable has a first end coupled to an electronic power source on the system board and has a second end having connector that plugs in to the auxiliary voltage connector on the memory module to provide power to the persistent-storage memory chips.
04/10/14
20140097482
Full metal gate replacement process for nand flash memory
A nand flash memory chip is made by forming sacrificial control gate structures and sacrificial select structures, and subsequently replacing these sacrificial structures with metal. Filler structures are formed between sacrificial control gate structures and are subsequently removed to form air gaps between neighboring control gate lines and between floating gates..
03/27/14
20140089729
Storage system and storage control method
A storage system includes a plurality of nonvolatile memory devices that each includes a plurality of nonvolatile memory chips, and a storage controller configured to perform input and output of data to and from a raid group comprised by storage areas of the plurality of nonvolatile memory devices. A nonvolatile memory device identifies a failure occurrence area that is a storage area in which a failure occurred in the plurality of nonvolatile memory chips, excludes the failure occurrence area from a storage area allocated to the raid group, and transmits failure occurrence information that is information relating to the failure that has occurred in the nonvolatile memory device to the storage controller.
03/27/14
20140089548
Systems, methods, and articles of manufacture to stream data
Systems and methods for streaming data. Systems allow read/write across multiple or n device modules.
03/27/14
20140084434
Semiconductor device
A semiconductor device is reduced in size. The semiconductor device includes a die pad, a plurality of leads arranged around the die pad, a memory chip and a power source ic chip mounted over the die pad, a logic chip mounted over the memory chip, a plurality of down bonding wires for connecting the semiconductor chip to the die pad, a plurality of lead wires for connecting the semiconductor chip to leads, and a plurality of inter-chip wires.
03/20/14
20140078826
Methods of making word lines and select lines in nand flash memory
A nand flash memory chip includes word lines formed by etching through concentric conductive loops and, in the same etch step, etching through a conductive strip to form select lines. A conductive loop forms two word lines which are in different erase blocks and are separately controlled by peripheral circuits..
03/20/14
20140077391
Semiconductor device
A semiconductor device in which a plurality of semiconductor chips having different planar sizes are stacked with a degree of freedom in design of each of the semiconductor chips is provided. A logic chip, a redistribution chip, and a memory chip having a larger planar size than the logic chip are mounted over a wiring board.
03/20/14
20140076973
Method for preventing an unauthorized use of disposable bioprocess components
This invention provides a system and apparatus that is able to authenticate and prevent illegal manufacturing and unauthorized operation of disposable bioprocess components. This invention utilizes a ferro-electric random access memory chip (fram) chip to store error-correctable information on a rfid tag attached to the disposable bioprocess components, where the error-correctable information is written in sequence into the memory chip, so that the redundant information can remain in the chip when the rfid tag and disposable bioprocess component is gamma-sterilized.
03/13/14
20140071757
Flash dual inline memory modules with multiplexing support circuits
In one implementation, flash memory chips are provided with an operating power supply voltage to substantially match a power supply voltage expected at an edge connector of a dual inline memory module. The one or more of the flash memory chips and a memory support application integrated circuit (asic) may be mounted together into a multi-chip package for integrated circuits.
03/13/14
20140071610
Multi-chip packaged flash memory/support application specific integrated circuit for flash dual inline memory modules
In one implementation, flash memory chips are provided with an operating power supply voltage to substantially match a power supply voltage expected at an edge connector of a dual inline memory module. The one or more of the flash memory chips and a memory support application integrated circuit (asic) may be mounted together into a multi-chip package for integrated circuits.
03/13/14
20140070381
Semiconductor memory card
A semiconductor memory card includes a lead frame having external connection terminals, a controller chip mounted on the lead frame and a memory chip mounted on the lead frame. The lead frame, the controller chip, and the memory chip are sealed with a sealing resin layer that has a surface at which the external connection terminals are exposed and a recess surrounding the external connection terminals..
03/13/14
20140070214
Semiconductor device
Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (pop) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length.
03/06/14
20140068146
Memory system
According to one embodiment, a memory system according to one embodiment is equipped with several nonvolatile memory chips and a memory controller that controls the nonvolatile memory chips based on a firmware. The firmware is written in a nonvolatile memory chip positioned the farthest distance from the memory controller..
03/06/14
20140063942
Memory device interface methods, apparatus, and systems
Apparatus and systems for memory system are provided. In an example, an interface chip can include a memory controller configured to couple to a processor and to couple to a plurality of stacked memory arrays using a data bus and a maintenance bus, wherein the data bus is separate from the maintenance bus, the plurality of stacked memory arrays forming two or more memory chips, the memory controller configured to control access to memory locations within the plurality of stacked memory arrays..
03/06/14
20140062528
Semiconductor memory device, memory controller and memory system having on die termination and on die termination controlling method
A semiconductor memory device includes a first memory chip including a first on die termination (odt) unit electrically connected to a first pad, the first pad being connected to a first terminal to receive a first signal, and a second memory chip including a second odt unit electrically connected to a second pad, the second pad being connected to the first terminal to receive the first signal, the first odt unit being configured to turn on/off according to a memory operation, the second odt unit being configured to turn off regardless of the memory operation, and the first and second odt units are switchable.. .
03/06/14
20140060161
Risk-managed, single-use, pre-calibrated, pre-sterilized sensors for use in bio-processing applications
Single-use, pre-sterilized, and pre-calibrated, pre-validated sensors are provided. These sensors are designed to store sensor-specific information, such as calibration and production information, in a non-volatile memory chip on the sensor or in a barcode printed on the sensor.
02/27/14
20140056052
Resistive memory device performing selective refresh and method of refreshing resistive memory device
A method of operating a resistive memory device, includes; performing a data retention time test on a resistive memory cell array of a memory chip, determining a number of bad memory blocks of the resistive memory cell array on the basis of the data retention time test, determining on the basis of the number of bad memory blocks whether the memory chip is a refresh memory chip or a good memory chip, and upon determining that the memory chip is a refresh memory chip, performing at least one refresh operation on at least one bad memory block of the refresh memory chip.. .
02/27/14
20140054669
Structures and methods for making nand flash memory
A nand flash memory chip includes wide openings in an inter-poly dielectric layer through which gaps are later etched to define structures such as select gates. Such select gates are asymmetric, with inter-poly dielectric on a side adjacent to a memory cell and no inter-poly dielectric on a side away from a memory cell.
02/20/14
20140052903
Memory system and bus switch
A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an mpu that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.. .
02/13/14
20140047172
Data storage device
A data storage device may include a first memory board having multiple memory chips and a controller board that is arranged and configured to operably connect to the first memory board. The controller board may include an interface to a host and a controller that is arranged and configured to control command processing for multiple different types of memory chips, automatically recognize a type of the memory chips on the first memory board, receive commands from the host using the interface, and execute the commands using the memory chips..
02/13/14
20140043884
Semiconductor apparatus
A semiconductor apparatus includes a memory chip which includes: a memory area; a data input/output block configured to communicate with the memory area; and a data transmission/reception block configured to connect one of a plurality of channels and a pad to the data input/output block, wherein the plurality of channels are configured to input and output normal data to and from another chip, and the pad is configured to input and output test data.. .
02/06/14
20140034891
Semiconductor memory structure and its manufacturing method thereof
The present invention belongs to the technical field of microelectronic devices, specifically relates to a semiconductor memory structure and its manufacturing method thereof. The semiconductor memory structure which carries out erasing, writing and reading operation on the phase change memory or the resistance change memory through a tunneling field-effect transistor is formed, for one hand, the high current passed through the tunneling field-effect transistor when the p-n junction the biased positively, meeting the high current requirements for erasing of and writing of the phase change memory and the resistance change memory, and on the other hand, vertical structure of the field-effect transistor can greatly improve the density of memory devices arrays.
01/23/14
20140022842
Data storage device comprising nonvolatile memory chips and control method thereof
A storage device is provided which includes a plurality of memory chips each nonvolatile memory cells divided into a first memory region and a second memory region; and a memory controller configured to buffer data provided from the exterior and to control the plurality of memory chips to perform a buffer-program operation and a main-program operation. The buffered data is stored at the first memory region at the buffer-program operation and data stored at the first memory region is written at the second memory region at the main-program operation.
01/23/14
20140021596
Wafer-level device packaging
The present invention relates to a semiconductor device packaged at the wafer level such that an entire packaged device is formed prior to separation of individual devices. The semiconductor device package includes a semiconductor chip having one or more bonding pads associated with the chip and a protective layer bonded over the semiconductor chip.
01/16/14
20140016426
Systems and methods for preventing data remanence in memory
A system for preventing data remanence in memory is provided. The system includes a computing device, a memory chip coupled to the computing device and including memory, and a heater, the heater configured to prevent data remanence in a memory by providing heat to at least a portion of the memory.
01/16/14
20140016425
Voltage regulator, voltage regulating system, memory chip, and memory device
A voltage regulator comprises a power source terminal configured to supply a power source voltage; an output terminal configured to output a load current; a first transistor which is connected between the power source terminal and the output terminal, is enabled by a signal applied from an amplifier in a first mode to generate a first current, and outputs the first current to the output terminal; and a second transistor which is connected between the power source terminal and the output terminal, is enabled by a signal applied from the amplifier in a second mode to generate a second current different from the first current, and outputs the second current to the output terminal, wherein the first transistor is enabled in the second mode, and the second transistor is disabled in the first mode.. .
01/09/14
20140011386
Electronics module for insertion into a carrier unit
An electronics module configured for insertion into a carrier unit and having, arranged on a rear side, a coding pair including a first coding part and a second coding part, wherein the first and second coding parts are configured in accordance with the lock-and-key principle, the first coding part being snapped into place in the rear side, while the second coding part is removably arranged on the first coding part, wherein a plug-and-socket connector is arranged on the second coding part such that a mating plug-and-socket connector arranged in the interior of the electronics module is insertable into the plug and-socket connector to establish an electrical connection, and wherein a memory chip which is connected to the plug and socket connector is also arranged on the second coding part.. .
01/02/14
20140006906
Memory device
A memory device includes a memory chip that stores data, and an external controller that controls the memory chip. The memory chip includes multiple memory cells configured to store data of two or more bits; and an internal controller that executes a program operation for page data including a lower and an upper page program operation, and executes a read operation for page data including a lower and an upper page read operation.
01/02/14
20140003122
Semiconductor memory structure and control method thereof
The present invention belongs to the technical field of non-volatile semiconductor memories, and relates to a semiconductor memory structure and a control method thereof. The semiconductor memory structure in the present invention comprises a memory unit for storing information and a tunneling field-effect transistor connected with the memory unit.
12/26/13
20130340998
Method and apparatus for inspecting and tallying pipe
A method and apparatus for inspecting and tallying pipe in a well completion system. In one embodiment, at least one sensor determines the length of a pipe and/or at least one thread protector sensor determines whether the thread protectors are removed from both ends of the pipe.
12/19/13
20130340068
Memory device comprising a plurality of memory chips, authentication system and authentication method thereof
A memory device includes a plurality of memory chips, including one or more memory chips that store authentication information, and a controller including a first register that stores information indicating a representative memory chip, from among the one or more memory chips that store the authentication information, that stores valid authentication information.. .
12/19/13
20130339594
Host bus adapters with shared memory and battery backup
The present disclosure includes methods and systems that share memory located on one pcie based hba across other pcie based hbas in the system. In addition, the backup battery is effectively shared across multiple pcie based hbas in the system.
12/19/13
20130336058
Nonvolatile memory device and related method of operation
A nonvolatile memory device comprises a nonvolatile memory chip comprising a static latch, first and second dynamic latches that receive the data stored in the static latch through a floating node, and a memory cell configured to store multi-bit data. The nonvolatile memory device performs a refresh operation on the first dynamic latch where externally supplied first single bit data is stored in the first dynamic latch, performs a refresh operation on the second dynamic latch where externally supplied second single bit data is stored in the second dynamic latch, and programs the memory cell using the data stored in the first and second dynamic latches after the first and second single bit data are stored in the respective first and second dynamic latches..
12/19/13
20130335909
Memory apparatus and electronic apparatus
A memory apparatus comprising a circuit board, a memory portion having a plurality of memory chips arranged on the circuit board, a terminal to provide an interface between an electronic apparatus and the plurality of memory chips being arranged on a first side of the circuit board, and a connecting portion connected to a fixing unit of the electronic apparatus to fix the memory apparatus to the electronic apparatus, the connecting portion being arranged on a second side of the circuit board so as to face the terminal.. .
12/12/13
20130332797
Memory controller
A memory controller is provided. The memory controller includes a memory interface and an encoding module.
12/12/13
20130328046
Semiconductor device and a method of manufacturing the same
A device featuring a substrate configured to include an upper surface and an opposing lower surface and, in parallel, a first and an opposing second peripheral edge, the first peripheral edge being smaller in length than the second peripheral edge, one or more semiconductor chip mounted over the upper surface of the substrate, a control semiconductor chip mounted over the upper surface of the substrate, a sealing resin covering the memory and control chips, and a plurality of external terminals provided over the lower surface of the substrate, the external terminals being arranged in a line along the first peripheral edge. The external terminals are used to fit the device to an electronic apparatus.


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Memory Chip topics: Memory Chip, Semiconductor, Storage Device, Semiconductor Memory, Memory Cell, Volatile Memory, Host Computer, Form Factor, Memory Cells, Data Storage, Aspect Ratio, Error Correction, Semiconductor Device, Control Unit, Crystallin

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