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Memory Chip patents



      

This page is updated frequently with new Memory Chip-related patent applications.




Date/App# patent app List of recent Memory Chip-related patents
02/04/16
20160035711 
 Stacked package-on-package memory devices patent thumbnailStacked package-on-package memory devices
3d stacked memory devices with copper pillars electrically connecting the package units are disclosed. A stacked package-on-package memory device includes a base chip package unit having a logic processing chip disposed on a base substrate; and a memory chip stack overlying the base chip unit.

02/04/16
20160034206 
 Adaptive flash tuning patent thumbnailAdaptive flash tuning
The present invention includes embodiments of systems and methods for increasing the operational efficiency and extending the estimated operational lifetime of a flash memory storage device (and its component flash memory chips, luns and blocks of flash memory) by monitoring the health of the device and its components and, in response, adaptively tuning the operating parameters of flash memory chips during their operational lifetime, as well as employing other less extreme preventive measures in the interim, via an interface that avoids the need for direct access to the test modes of the flash memory chips. In an offline characterization phase, “test chips” from a batch of recently manufactured flash memory chips are used to simulate various usage scenarios and measure the performance effects of writing and attempting to recover (read) test patterns written with different sets of operating parameters over time (simulating desired retention periods)..

01/14/16
20160012865 
 Semiconductor device having interconnection in package and  manufacturing the same patent thumbnailSemiconductor device having interconnection in package and manufacturing the same
A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip..

01/14/16
20160011781 
 Memory chip, memory system, and  accessing the memory chip patent thumbnailMemory chip, memory system, and accessing the memory chip
A memory chip, a memory system, and a method of accessing the memory chip. The memory chip includes a substrate, a first storage unit, and a second storage unit.
Samsung Electronics Co., Ltd.


12/31/15
20150380078 
 Memory chip and layout design for manufacturing same patent thumbnailMemory chip and layout design for manufacturing same
A static random access memory (sram) chip including a plurality of sram cells and a plurality of cell current tracking cells. Each of the sram cells include a source voltage reference conductor, a first ground reference conductor, two cross-coupled inverters, and two pass-gate devices.
Taiwan Semiconductor Manufacturing Company, Ltd.


12/31/15
20150379184 
 Layout  printed circuit board patent thumbnailLayout printed circuit board
A printed circuit board (pcb) is provided. The pcb has a specific routing module, having a first chip, a memory chip, and a plurality of traces designed for interconnection between the first chip and the memory chip according to a routing configuration between the first chip and the memory chip.
Mediatek Inc


12/31/15
20150379180 
 Layout  printed circuit board patent thumbnailLayout printed circuit board
A layout method for a printed circuit board (pcb) is provided. The method obtains a memory type of a dynamic random access memory (dram) to be mounted on the pcb, obtains a module group from a database according to the memory type of the dram, wherein the module group comprises a plurality of routing modules, obtains a plurality of pcb parameters, selects a specific routing module from the module group according to the pcb parameters, and implements the specific routing module into a layout design for pcb fabrication.
Mediatek Inc


12/31/15
20150378818 
 Memory chip with error detection and retry modes of operation patent thumbnailMemory chip with error detection and retry modes of operation
A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter.
Rambus Inc.


12/31/15
20150378613 
 Storage device patent thumbnailStorage device
A storage device comprises plural memory units and a storage controller that controls the memory units as a raid group. Each memory unit is provided with a nonvolatile semiconductor memory (e.g.
Hitachi, Ltd.


12/24/15
20150371701 
 Memory chip and layout design for manufacturing same patent thumbnailMemory chip and layout design for manufacturing same
An embedded synchronous random access memory (sram) chip, includes a first single-port (sp) sram macro and a second sp macro. The first macro includes a first periphery circuit, and a plurality of first sram cells.
Taiwan Semiconductor Manufacturing Company, Ltd.


12/24/15
20150370669 

Implementing enhanced wear leveling in 3d flash memories


A method, system and computer program product are provided for implementing enhanced wear leveling in a stack of flash memory chips. A flash memory includes plurality of flash memory chips including a number n data chips and one or more spare chips.
International Business Machines Corporation


12/24/15
20150370635 

Implementing enhanced wear leveling in 3d flash memories


A method, system and computer program product are provided for implementing enhanced wear leveling in a stack of flash memory chips. A flash memory includes plurality of flash memory chips including a number n data chips and one or more spare chips.
International Business Machines Corporation


12/17/15
20150365108 

System and module comprising an electrically erasable programmable memory chip


A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data.
Rambus Inc.


12/17/15
20150364206 

Memory system and control method


A memory system according to embodiments comprises a memory chip that includes a memory cell array having a plurality of memory cells, a first writing unit that writes first data in a first memory cell in the memory cell array, and a second writing unit that writes second data in a second memory cell which is adjacent to the first memory cell. The second data is used in adjusting a threshold value of the first memory cell..
Kabushiki Kaisha Toshiba


12/10/15
20150357002 

Stacked memory with redundancy


A stacked memory is disclosed including a first integrated circuit memory chip having first storage locations and a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip. The second integrated circuit memory chip has second storage locations.
Rambus Inc.


12/10/15
20150355964 

Controller device for use with electrically erasable programmable memory chip with error detection and retry modes of operation


A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter.
Rambus Inc.


12/03/15
20150347058 

System and distributed computing in non-volatile memory


A system and method are disclosed for incorporating mathematical and/or logical functionality within a memory system (such as a solid state drive (ssd)). The mathematical and/or logical functionality may comprise an arithmetic logic unit (alu).
Sandisk Technologies Inc.


11/26/15
20150340342 

Semiconductor device


A semiconductor device in which a plurality of semiconductor chips having different planar sizes are stacked with a degree of freedom in design of each of the semiconductor chips is provided. A logic chip, a redistribution chip, and a memory chip having a larger planar size than the logic chip are mounted over a wiring board.
Renesas Electronics Corporation


11/26/15
20150340074 

Memory module having address mirroring function


A memory module having an address minoring function is provided. The memory module includes a register that allows mode registers of first memory chips of a first rank and mode registers of second memory chips of a second rank to be identically programmed in response to a mode register set (mrs) command during a rank-merged test mode.
Samsung Electronics Co., Ltd.


11/19/15
20150332736 

Stacked memory device control


A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects.
International Business Machines Corporation


11/19/15
20150331768 

Data retrieval from stacked computer memory


Data is retrieved from a stacked memory device having a plurality of slave memory chips in response to recognizing a problem in the stacked memory device. The problem is determined to be associated with a primary driver module in the stacked memory device.
International Business Machines Corporation


11/19/15
20150331767 

Stacked memory device control


A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects.
International Business Machines Corporation


11/19/15
20150331764 

Data retrieval from stacked computer memory


Data is retrieved from a stacked memory device having a plurality of slave memory chips in response to recognizing a problem in the stacked memory device. The problem is determined to be associated with a primary driver module in the stacked memory device.
International Business Machines Corporation


11/12/15
20150325276 

Bipolar logic gates on mos-based memory chips


A system for using selectable-delay bipolar logic circuitry within the address decoder of a mos-based memory includes a mos-based memory, which includes an array of a plurality of memory cells configured to store data; an address decoder including bipolar logic circuitry, where the address decoder is configured to accept a word including a plurality of bits and access the array of memory cells using the word; where the bipolar logic circuitry includes a plurality of bipolar transistor devices, where at least one bipolar transistor device has an adjustable gate bias and is configured to accept an input, wherein the gate bias is adjusted based on the input, where the gate bias determines a selectable gate delay.. .
Elwha Llc


11/12/15
20150324668 

Method, system and memory chip for generating checkout value


A method, a system and a memory chip for generating a check value, which can eliminate the defect of time consuming and high power consumption of the existing memory chip for generating check value, are provided according to the present disclosure. The method comprises the following steps: a frequently changing data relating to an imaging cartridge is acquired; an intermediate check data pre-generated based on infrequently changing data is acquired; the frequently changing data and the intermediate check data are calculated through a predetermined algorithm, and thus a check value is obtained.
Apex Microelectronics Co., Ltd.


11/05/15
20150317276 

Reconfigurable high speed memory chip module and electronic device with a reconfigurable high speed memory chip module


A reconfigurable high speed memory chip module includes a type of memory cell array group, a first transmission bus, and a logic unit. The type memory cell array group includes multiple memory cell array integrated circuits (ics).
Etron Technology, Inc.


11/05/15
20150317097 

De-duplication in flash memory module


Data capacity efficiency is improved by de-duplicating data assigned with a code that is different for each data. A storage apparatus comprising a flash memory control device equipped with one or more flash memory modules, wherein the flash memory module comprises at least one flash memory chip for providing a storage area, and a controller for controlling writing/reading of data including user data and a guarantee code accompanying the user data to and from the storage area provided by the flash memory chip, wherein the controller respectively divides a plurality of the data having the common user data into the user data and the guarantee code, stores one of the user data in an area of a predetermined unit of the storage area, and links and stores each of the guarantee codes accompanying the plurality of user data in an area of a predetermined unit of the storage area..
Hitachi, Ltd.


10/29/15
20150310910 

Multi-level memory array having resistive elements for multi-bit data storage


A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device.
Sandisk 3d Llc


10/22/15
20150302904 

Accessing memory


A disclosed example method involves performing simultaneous data accesses on at least first and second independently selectable logical sub-ranks to access first data via a wide internal data bus in a memory device. The memory device includes a translation buffer chip, memory chips in independently selectable logical sub-ranks, a narrow external data bus to connect the translation buffer chip to a memory controller, and the wide internal data bus between the translation buffer chip and the memory chips.

10/22/15
20150301748 

Storage operating system


A storage system includes a plurality of unit storages each including at least one flash memory chip. Performance of at least a first storage of the unit storages is monitored.
Samsung Electronics Co., Ltd.


10/15/15
20150293859 

Memory access processing method, memory chip, and system based on memory chip interconnection


A memory access processing method is based on memory chip interconnection, a memory chip, and a system, which relate to the field of electronic devices, and can shorten a time delay in processing a memory access request and improve a utilization rate of system bandwidth. The method of the present invention includes: receiving, by a first memory chip, a memory access request; and if the first memory chip is not a target memory chip corresponding to the memory access request, sending, according to a preconfigured routing rule, the memory access request to a next memory chip connected with the first memory chip, until the target memory chip corresponding to the memory access request is determined.

10/01/15
20150279444 

Apparatus, providing termination for multiple chips of an integrated circuit package


Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (ic) package which includes a command and address bus and a plurality of memory chips each coupled thereto.
Intel Corporation


10/01/15
20150278054 

Method for managing storage system using flash memory, and computer


To facilitate the management of a storage system that uses a flash memory as a storage area. A controller of the storage system provided with a flash memory chip manages a surplus capacity value of the flash memory chip, and transmits a value based on the surplus capacity value to a management server, on the basis of at least one of a definition of a parity group, a definition of an internal lu, and a definition of a logical unit.
Hitachi, Ltd.


09/17/15
20150262900 

Dam for three-dimensional integrated circuit


An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (ic) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members.
Taiwan Semiconductor Manufacturing Company, Ltd.


09/17/15
20150261448 

Memory system, memory controller and control non-volatile memory


According to one embodiment, a controller executes a first process such that writing is performed in an order of page numbers in the memory chip. The first process includes a second process to be executed in an order of group units.
Kabushiki Kaisha Toshiba


09/10/15
20150255144 

Method and calibrating write timing in a memory system


A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation.
Rambus Inc.


09/10/15
20150255131 

Stacked semiconductor apparatus and semiconductor system capable of inputting signals through various paths


A semiconductor apparatus includes a control signal reception portion. The control signal reception portion may set information related to operation of a memory chip by receiving a command signal and an address signal from one among a stack chip test portion, a control signal interface portion and a test setting portion..
Sk Hynix Inc.


09/10/15
20150254011 

Memory system, memory controller and control non-volatile memory


According to an embodiment, a controller executes chip interleaving for a host write partway through one cycle, and executes chip interleaving for writes of garbage collection to n memory chips from a memory chip next in turn to a memory chip to which the host write was executed last, to the memory chip to which the host write was executed last.. .
Kabushiki Kaisha Toshiba


09/03/15
20150248935 

Apparatus, systems, and methods for operating flash backed dram module


A device includes volatile memory; one or more non-volatile memory chips, each of which is for storing data moved from the volatile-memory; an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from a primary power source; a controller in communication with the volatile memory and the non-volatile memory, wherein: the controller is programmed to move data from the volatile memory to the non-volatile memory chips upon a loss of power of the primary power source of the volatile memory; and the at least one parameter describing the volatile memory are stored in at least one of the non-volatile memory chips that store the data moved from the volatile memory. In some aspects the at least one parameter includes serial presence detect information..
Hgst Netherlands B.v.


09/03/15
20150248926 

Method and calibrating write timing in a memory system


A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation.
Rambus Inc.


09/03/15
20150248322 

Memory controller and memory system


According to one embodiment, a memory controller includes a controller that is configured to, when notified of an error by one of memory chips at a time of power supply startup, transmit a first command including an address to the memory chip by which the error was notified, when notified of a normal end by the memory chip in which the first command was received, transmit a second command including an address to the memory chip by which the normal end was notified.. .
Kabushiki Kaisha Toshiba


09/03/15
20150246941 

Cobalt precursors for low temperature ald or cvd of cobalt-based thin films


Cobalt silylamide and cobalt carbonyl precursors are described, which are usefully employed in vapor deposition processes, such as chemical vapor deposition and atomic layer deposition, to deposit cobalt and to form high purity cobalt-containing films at temperatures below 400° c. These precursors and processes can be utilized in the manufacture of integrated circuitry and production of devices such as microprocessors, and logic and memory chips..
Entegris, Inc.


08/27/15
20150243605 

Method for manufacturing semiconductor device


To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip.
Renesas Electronics Corporation


08/27/15
20150243347 

Semiconductor device preventing multiword state


To prevent a multiword state in which a plurality of word lines are active in a same memory bank, the semiconductor device includes a plurality of memory chips commonly receiving an access command, in which each of the plurality of memory chips are provided with a control circuit ignoring an new access command when the bank address information in the new access command is the same as the bank address information for the specified memory bank even if the new access command received before reading/writing data from/to the specified memory bank of the selected memory chip is completed contains chip selection information selecting another memory chip.. .
Ps5 Luxco S.a.r.l.


08/27/15
20150243343 

Method and calibrating write timing in a memory system


A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation.
Rambus Inc.


08/20/15
20150236002 

Multi-chip module with stacked face-down connected dies


A microelectronic assembly can include a substrate having first and second surfaces, at least two logic chips overlying the first surface, and a memory chip having a front surface with contacts thereon, the front surface of the memory chip confronting a rear surface of each logic chip. The substrate can have conductive structure thereon and terminals exposed at the second surface for connection with a component.
Tessera, Inc.


08/20/15
20150235715 

Stacked semiconductor memory apparatus and test circuit therefor


A stacked semiconductor memory apparatus includes a memory module including a plurality of memory chips; and a logic circuit block with the memory module stacked thereon, configured to be electrically coupled with an interface substrate through a first terminal group and a second terminal group and to communicate with a controller, and to include a test circuit that receives a first test signal through the first terminal group from the controller and outputs the first test signal through the second terminal group in a test mode.. .
Sk Hynix Inc.


08/20/15
20150235714 

Semiconductor device for parallel bit test and test method thereof


A semiconductor device includes a plurality of memory chips and a plurality of signal selection units respectively corresponding to the plurality of memory chips, and suitable for commonly transferring test data signals from an external to a corresponding one of the plurality of memory chips during a common test mode, wherein one or more of the plurality of signal selection units may transfer the test data signals from the external to corresponding ones of the plurality of memory chips during an individual test mode, and wherein the semiconductor device may be set to the common test mode when a common test signal is enabled, and set to the individual test mode when both the common test signal and a test control signal are enabled.. .
Sk Hynix Inc.


08/20/15
20150234752 

Memory chip


According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.. .
Kabushiki Kaisha Toshiba


08/20/15
20150234705 

Semiconductor memory device


A crc code is generated from an original data, a bch code is generated with respect to the original data and the crc code, and the original data, the crc code, and the bch code are recorded in pages selected from different planes of a plurality of memory chips. An rs code is generated from the original data across pages, a crc code is generated with respect to the rs code, a bch code is generated with respect to the rs code and the crc code, and the rs code, the crc code, the bch code are recorded in a memory chip different from a memory chip including the original data.
Kabushiki Kaisha Toshiba


07/30/15
20150213841 

Memory chip and memory storage device


A memory chip is disclosed. The memory comprises a substrate and a plurality of memory pads.
Eorex Corporation


07/23/15
20150208510 

Thin low profile strip dual in-line memory module


A low profile strip dual in-line memory module (200) includes a passive interposer support structure (90) with patterned openings (91-97) formed between opposing top and bottom surfaces, a plurality of memory chips (d1-d8) attached to the top and bottom surfaces, and vertical solder ball conductors (98) extending through the patterned openings to electrically connect the plurality of memory chips, where each memory chip has an attachment surface facing the passive interposer structure and a patterned array of horizontal conductors (e.g., 82-86) formed on the attachment surface with contact pads electrically connected to the plurality of vertical conductors to define at least one bus conductor that is electrically connected to each memory die in the first and second plurality of memory die.. .
Freescale Semiconductor, Inc.


07/23/15
20150208124 

Smart television system and turn-on and turn-off method thereof


A smart television, and a turn-off method and a turn-on method for the smart television system are provided. The smart television system includes a remote controller and a smart television.
Mstar Semiconductor, Inc.


07/23/15
20150207565 

Interface circuit for transmitting and receiving signals between electronic devices, and semiconductor memory chip and operation processing device including the same


An interface circuit configured to transmit and receive signals between electronic devices is provided. The interface circuit includes an optical connection protocol manager configured to serialize a parallel transmission packet electrical signal generated based on output data to generate a serialized transmission packet electrical signal, parallelize a serial reception packet electrical signal to generate a parallelized reception packet electrical signal, and parse the parallelized reception packet electrical signal according to whether there is an error in the parallelized reception packet electrical signal to generate input data; and an electro-optical converter configured to convert the serialized transmission packet electrical signal into a transmission packet optical signal to output the transmission packet optical signal, receive a reception packet optical signal, and convert the reception packet optical signal into the serial reception packet electrical signal to provide the serial reception packet electrical signal to the optical connection protocol manager..
Electronics And Telecommunications Research Institute


07/23/15
20150206866 

Semiconductor package and methods of forming same


An embodiment package-on-package (pop) device includes a fan-out structure, one or more memory chips, and a plurality of connectors bonding the one or more memory chips to the fan-out structure. The fan-out structure includes a logic chip, a molding compound encircling the logic chip, and a plurality of conductive pillars extending through the molding compound..
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206865 

Integrated circuit package and methods of forming same


An embodiment package-on-package (pop) device includes a package structure, a package substrate, and a plurality of connectors bonding the package structure to the package substrate. The package structure includes a logic chip bonded to a memory chip, a molding compound encircling the memory chip, and a plurality of conductive studs extending through the molding compound.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206849 

System-in-package module and manufacture a system-in-package module


A system-in-package module includes a non-memory chip, a bundled memory, and an encapsulation package material. The non-memory chip has a plurality of pads.
Etron Technology, Inc.


07/23/15
20150201880 

Integrated injection system and communication device


An integrated system for injection including an injection device (10) in electronic connection with a communication device (a) is provided. The external communication device may be a handheld electronic device such as a smartphone or a dedicated reader such as a reader capable of reading information contained on an rfid tag.
Becton Dickinson France S.a.s.


07/16/15
20150200008 

Semiconductor package and electronic apparatus


According to one embodiment, a semiconductor package includes a package substrate, a controller chip, a semiconductor memory chip, a temperature sensor, a seal portion, and a plurality of solder balls. The controller chip and the semiconductor memory chip are provided on a first surface of the package substrate.
Kabushiki Kaisha Toshiba


07/16/15
20150199266 

3dic memory chips including computational logic-in-memory for performing accelerated data processing


This disclosure relates to a three-dimensional (3d) integrated circuit (3dic) memory chip including computational logic-in-memory (lim) for performing accelerated data processing. Related memory systems and methods are also disclosed.
Carnegie Mellon University


07/09/15
20150193308 

Memory chips and data protection methods


A memory chip coupled to a host includes a memory and a controller. Multiple boot images having the same content are pre-loaded in the memory.
Via Technologies, Inc.


07/02/15
20150187682 

Semiconductor device


A semiconductor device is reduced in size. The semiconductor device includes a die pad, a plurality of leads arranged around the die pad, a memory chip and a power source ic chip mounted over the die pad, a logic chip mounted over the memory chip, a plurality of down bonding wires for connecting the semiconductor chip to the die pad, a plurality of lead wires for connecting the semiconductor chip to leads, and a plurality of inter-chip wires.
Renesas Electronics Corporation


07/02/15
20150187399 

Pulse mechanism for memory circuit interruption


In a memory system where multiple memory chips communicate their ready/busy status on a shared bus line, a pulse mechanism is used for the individual memory chips to indicate their ready/busy status to the controller. In one example, the controller assigns pulse durations of differing lengths to the memory dies to allow the controller to distinguish between them.
Sandisk Technologies Inc.


06/25/15
20150179285 

Detecting defective connections in stacked memory devices


A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error.
International Business Machines Corporation


06/25/15
20150179280 

Detecting defective connections in stacked memory devices


A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error.
International Business Machines Corporation


06/25/15
20150178197 

Addressing auto address assignment and auto-routing in nand memory network


A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device.
Sandisk Technologies Inc.


06/25/15
20150178187 

Single command, multiple column-operation memory device


A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values..
Rambus Inc.


06/25/15
20150177993 

Memory system and bank interleaving method


According to embodiments, a memory system includes a plurality of memory chips configuring banks, an instruction generator, and a memory controller. The instruction generator generates a plurality of instructions.
Kabushiki Kaisha Toshiba


06/04/15
20150155042 

Semiconductor memory device


A nand dc-dc converter includes two output terminals. Each output terminal is connected to several multi-chip packages in each of which a plurality of nand flash memory chips are provided.
Kabushiki Kaisha Toshiba


06/04/15
20150155020 

Semiconductor apparatus


A semiconductor apparatus includes a logic memory chip including a transmission block which outputs input signals and a strobe signal; and a plurality of memory chips stacked with the logic memory chip. At least one of the plurality of memory chips includes a plurality of reception blocks.
Sk Hynix Inc.


06/04/15
20150154129 

Memory system having a plurality of types of memory chips and a memory controller for controlling the memory chips


A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller.
Fujitsu Semiconductor Limited


06/04/15
20150150495 

System and facilitating sensor and monitor communication


Embodiments disclosed herein may include an adapter which is capable of converting signals from an oximeter sensor such that the signals are readable by an oximeter monitor. In an embodiment, the adapter is capable of converting signals relating to calibration information from the oximeter sensor.
Covidien Lp


05/21/15
20150143155 

Data storage apparatus


A data storage apparatus includes a controller including a controller input/output unit suitable for receiving a ready/busy delay signal and generating a ready/busy output signal in response to a first control signal, and a memory chip including a memory input/output unit suitable for receiving a chip enable delay signal and generating a chip enable output signal in response to a second control signal. The ready/busy delay signal and the chip enable delay signal are transmitted through a substantially same transmission line..
Sk Hynix Inc.


05/14/15
20150131397 

Memory system and assembling memory system


According to one embodiment, each memory chip included in a memory package includes a first storage unit that stores therein first information that is n-bit information and is a comparison target of a chip address, and is used for identifying its own memory chip, a second storage unit that stores therein second information for determining an effective bit of the n-bit first information, and a control unit that determines an effective bit of the n-bit first information and an effective bit of the chip address based on the second information.. .

05/07/15
20150127914 

Semiconductor memory device, memory system and operating the same


A memory system including a plurality of memory chips is provided. The memory system includes a first memory chip and a second memory chip that share a data bus and become active by a chip enable signal, and a controller transmitting multi chip select commands to the first and second memory chips.
Sk Hynix Inc.


04/30/15
20150121030 

High density memory structure


A semiconductor memory comprises a plurality of sub banks each including one or more rows of memory bit cells connected to a set of local bit lines, wherein the sub banks share a same set of global bit lines for reading/writing data from/to the memory bit cells of the sub banks. The semiconductor memory chip further comprises a plurality of switch elements for each of the sub banks, wherein each of the switch elements connects the local bit line and the global bit line of a corresponding one of the memory bit cells in the sub bank for data transmission between the local bit line and the global bit line.
Taiwan Semiconductor Manufacturing Co., Ltd.


04/30/15
20150117080 

Multi-chip package and memory system


A multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal, a second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal. The first memory chip and the second memory chip each include a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation..
Kabushiki Kaisha Toshiba


04/30/15
20150113851 

Realtime memorialization firearm attachment


A firearm accessory that includes a body that is demountably attached to a firearm, the body containing: a camera; a microphone; a memory chip; a micro-controller operable to record a user's firearm activity into the memory chip as captured by the camera and the microphone; and, a trigger-switch mechanism demountably attached to a firearm-handle operable by a user's finger to turn the contents of the body on but not off. The body disposed on a firearm further includes a plurality of electronic components operable to: record audio, video, location, time, and date, at the time of usage of a firearm; and transmit the recorded a record audio, video, location, time, and date, outside of the body through a wire, a portable memory card, or wirelessly in realtime..

04/23/15
20150113665 

Systems and methods for preventing data remanence in memory


A system for preventing data remanence in memory is provided. The system includes a computing device, a memory chip coupled to the computing device and including memory, and a heater, the heater configured to prevent data remanence in a memory by providing heat to at least a portion of the memory.
Elwha Llc


04/23/15
20150113356 

System-in-package module with memory


A system-in-package module with memory includes a non-memory chip, a substrate, and a memory chip. The non-memory chip has a first portion and a second portion.
Etron Technology, Inc.


04/23/15
20150108657 

Electronic device


A semiconductor device and electronic device comprising the same includes at least one dummy chip having at least one through silicon via (tsv), and at least one active chip connected to the at least one dummy chip. The at least one active chip exchanges an electrical signal through the at least one tsv.
Samsung Electronics Co., Ltd.


04/09/15
20150100721 

Storage system and control for storage system


The storage system includes a plurality of storage devices and a storage controller. The storage controller stores a data request quantity indicating the data quantity of write data written to the target area in a specific period, and estimates, based on the quantity of request data and relationship information received from storage devices, the estimated data quantity written to the nonvolatile semiconductor memory chips based on the write data written to the target area in the specific period.
Hitachi, Ltd.


04/02/15
20150095556 

Memory system


A memory system includes a first memory chip, a second memory chip, and a memory controller. The first memory chip and the second memory chip are connected to the memory controller via a plurality of data lines including a first data line and a second data line.
Kabushiki Kaisha Toshiba


04/02/15
20150092509 

Semiconductor apparatus and chip id generation method thereof


Provided is a semiconductor apparatus including a plurality of memory chips which are sequentially stacked. Each of the memory chips includes: a temperature sensor configured to sense the temperature of the memory chip; and a chip id output unit configured to generate a chip id for the memory chip based on an output of the temperature sensor..
Sk Hynix Inc.


03/26/15
20150085577 

Flash memory module for realizing high reliability


A flash memory module may include a plurality of flash memory chips. The memory chips may include one or more blocks.
Hitachi, Ltd.


03/26/15
20150084166 

Semiconductor device having plural memory chip


A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip.
Ps4 Luxco S.a.r.l.


03/19/15
20150078094 

Memory chip, memory device, and reading method


A memory chip includes a memory cell array having a plurality of memory cells connected to word lines and bit lines, and a sense amplifier configured to detect data stored in a memory cell that is connected to a selected one of the word lines and a selected one of the bit lines, and a control circuit configured to read data from the memory cell in a first read mode when a first command is received and in a second read mode when a second command is received. A peak or an average value of an operation current that is flowing between power supply and ground terminals of the memory chip during a read operation in the first read mode is less than a peak or an average value of the operation current during a read operation in the second read mode..
Kabushiki Kaisha Toshiba


03/19/15
20150078055 

Memory module and manufacturing method thereof


A memory module includes a printed circuit board; first memory chips disposed in parallel with a long axis of the printed circuit board along a first column; second memory chips disposed in parallel with the long axis of the printed circuit board along a second column; and passive elements disposed between the first memory chips and the second memory chips, wherein the passive elements are connected between input/output pins of each of the first and second memory chips and tap pins.. .
Samsung Electronics Co., Ltd.


03/19/15
20150076640 

Optical module


The present optical module includes a sensor configured to pick up an image of an image pickup object, and a memory chip configured to store pixel data read out from the sensor and having the sensor joined thereto. The memory chip is connected to a substrate by a connection portion by flip-chip connection.

03/12/15
20150074346 

Memory controller, memory module and memory system


A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.. .
Mediatek Inc.


03/12/15
20150074342 

Method for managing storage system using flash memory, and computer


To facilitate the management of a storage system that uses a flash memory as a storage area. A controller of the storage system provided with a flash memory chip manages a surplus capacity value of the flash memory chip, and transmits a value based on the surplus capacity value to a management server, on the basis of at least one of a definition of a parity group, a definition of an internal lu, and a definition of a logical unit.
Hitachi, Ltd.


03/12/15
20150074331 

Nonvolatile memory package and nonvolatile memory chip


A nonvolatile memory package of an embodiment includes: a data terminal configured to receive a write command for a data; a first ce terminal; a second ce terminal; a ce selection terminal; and a selector coupled to the first ce terminal and the second ce terminal. The selector outputs one of a first chip-enable signal and a second chip-enable signal based on a ce selection signal.
Kabushiki Kaisha Toshiba


03/12/15
20150071021 

Accessing independently addressable memory chips


A method of accessing rows and columns stored in a memory system that include memory chips that can be individually addressed and accessed is described. In order to leverage this capability, prior to performing a row-write request on the memory system, a computer system may transform the rows and the columns in a matrix.
Oracle International Corporation


03/12/15
20150069633 

Semiconductor device and memory device


A semiconductor device includes a substrate, a controller chip, and memory chips. Wiring is formed on the substrate.
Kabushiki Kaisha Toshiba


03/05/15
20150067291 

Controller, memory system, and method


According to the embodiments, a controller includes an arbiter, a command fetch unit, and a processing unit. The arbiter executes a retrieval process.
Kabushiki Kaisha Toshiba


03/05/15
20150067236 

Memory system


According to one embodiment, the memory controller outputs a first command, then outputs n pieces of second commands to first and second memory chips, and reads out the read data from the first and second memory chips. First time is for reading out the read data from a memory cell array to a buffer, and second time is for transferring data of the one-nth of the read data from the buffer to the memory controller.
Kabushiki Kaisha Toshiba


02/26/15
20150058664 

Dynamic memory cell replacement using column redundancy


A memory chip comprises a main memory array having a plurality of memory columns, a redundancy memory column associated with the main memory array, and a hit logic circuitry configured to generate a plurality of hit logic signals by a plurality of hit logic units in the hit logic circuitry to enable dynamic replacement of a defective memory cell in one of the memory columns for dynamic replacement by the redundancy memory column when the memory array is in operation.. .
Taiwan Semiconductor Manufacturing Co., Ltd.


02/26/15
20150055419 

Controller, memory system, and method


According to one embodiment, a memory system includes a memory chip and a controller. The controller is configured to count a first elapsed time from a start of an erase process when causing the memory chip to execute the erase process.
Kabushiki Kaisha Toshiba




Memory Chip topics: Memory Chip, Semiconductor, Storage Device, Semiconductor Memory, Memory Cell, Volatile Memory, Host Computer, Form Factor, Memory Cells, Data Storage, Aspect Ratio, Error Correction, Semiconductor Device, Control Unit, Crystallin

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