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Memory Cells patents



      
           
This page is updated frequently with new Memory Cells-related patents. Subscribe to the Memory Cells RSS feed to automatically get the update: related Memory RSS feeds.

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Date/App# patent app List of recent Memory Cells-related patents
04/17/14
20140106533
 Memory cells and methods of forming memory cells patent thumbnailnew patent Memory cells and methods of forming memory cells
Some embodiments include memory cells having programmable material between a pair of electrodes. The programmable material includes a material selected from the group consisting of a metal silicate with a ratio of metal to silicon within a range of from about 2 to about 6, and metal aluminate with a ratio of metal to aluminum within a range of from about 2 to about 6.
04/17/14
20140104965
 Non-volatile memory array and method of using same for fractional word programming patent thumbnailnew patent Non-volatile memory array and method of using same for fractional word programming
A non-volatile memory device that includes n planes of non-volatile memory cells (where n is an integer greater than 1). Each plane of non-volatile memory cells includes a plurality of memory cells configured in rows and columns.
04/17/14
20140104961
 Non-volatile memory device with plural reference cells, and method of setting the reference cells patent thumbnailnew patent Non-volatile memory device with plural reference cells, and method of setting the reference cells
A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells..
04/17/14
20140104959
 Memory apparatus and methods patent thumbnailnew patent Memory apparatus and methods
Embodiments of apparatus and methods having a memory device can include a line to exchange information with a string of memory cells and a transistor coupled between the string of memory cells and the line. Such a memory device can also include a module configured to couple a gate of the transistor to a node during a first time interval of a memory operation and decouple the gate from the node during a second time interval of the memory operation.
04/17/14
20140104957
 Partial local self boosting for nand patent thumbnailnew patent Partial local self boosting for nand
A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines.
04/17/14
20140104956
 Sensing operations in a memory device patent thumbnailnew patent Sensing operations in a memory device
Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output.
04/17/14
20140104955
 Programming nonvolatile memory device using program voltage with variable offset patent thumbnailnew patent Programming nonvolatile memory device using program voltage with variable offset
A method of programming a nonvolatile memory device comprises applying at least one test program pulse to selected memory cells located in a scan read area, performing a scan read operation on the selected memory cells following application of the at least one test program pulse to detect at least one one-shot upper cell, calculating an offset voltage corresponding to a scan read region at which the scan read operation is performed, setting a program start bias using the offset voltage, and executing at least one program loop using the program start bias.. .
04/17/14
20140104951
 Sensing data stored in memory patent thumbnailnew patent Sensing data stored in memory
The present disclosure includes apparatuses and methods for sensing data stored in memory. A number of embodiments include an array of memory cells, and a controller coupled to the array and configured to sense a page of memory cells coupled to an activated access line by pre-charging only a single subset of a number of data lines coupled to the page, wherein more than two subsets of data lines are coupled to the page and the single subset is coupled to those memory cells storing at least a portion of a single sector of data of the page, and sensing the single subset of the number of data lines to determine the at least a portion of the single sector of data..
04/17/14
20140104948
 Split block decoder for a nonvolatile memory device patent thumbnailnew patent Split block decoder for a nonvolatile memory device
A non-volatile memory device having a memory array organized into a plurality of memory blocks, having either planar memory cells or stacks of cells. Row decoding circuitry of the memory device is configured to select a group of the plurality of memory blocks in response to a first row address, and to select a memory block of the group for receiving row signals in response to a second row address.
04/17/14
20140104944
 Programming based on controller performance requirements patent thumbnailnew patent Programming based on controller performance requirements
Methods and solid state drives are disclosed, for example a solid state drive that is adapted to receive and transmit analog data signals representative of bit patterns of three or more levels (such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits). Programming of the solid state drive, comprising an array of non-volatile memory cells, might include adjusting the level of each memory cell being programmed in response to a desired performance level of a controller circuit..
04/17/14
20140104943
new patent Accelerated soft read for multi-level cell nonvolatile memories
A memory device includes a memory array comprising multi-level memory cells, and control circuitry coupled to the memory array. The control circuitry is configured to perform accelerated soft read operations on at least a portion of the memory array.
04/17/14
20140104936
new patent Latch-based memory array
The invention concerns a memory array having memory cells arranged in columns and rows, the memory cells of each column being coupled to at least one common write line of their column, the memory cells of each row being coupled to a common selection line of their row, wherein each of the memory cells includes a latch formed of a pair of inverters cross-coupled between first and second storage nodes; a first transistor coupled between the first storage node and a first test data input; and a second transistor coupled between the second storage node and a second test data input.. .
04/17/14
20140104932
new patent Memory cells, non-volatile memory arrays, methods of operating memory cells, methods of writing to and writing from a memory cell, and methods of programming a memory cell
In one aspect, a method of operating a memory cell includes using different electrodes to change a programmed state of the memory cell than are used to read the programmed state of the memory cell. In one aspect, a memory cell includes first and second opposing electrodes having material received there-between.
04/17/14
20140104931
new patent Nonvolatile memory device and method of performing forming the same
A nonvolatile memory device including a control unit configured to read resistance value information for each of memory cells as initial resistance value information and store it temporarily before a voltage pulse for forming is applied, to set resistance value information as a threshold value serving as a target for completion of the forming, the resistance value information being obtained by multiplying the initial resistance value information by a predetermined coefficient, and to repeat application of the voltage pulse for forming and reading of the resistance value information until a resistance value indicated by the resistance value information on the memory cell becomes lower than a resistance value indicated by the threshold value.. .
04/17/14
20140104930
new patent Semiconductor memory device
A semiconductor memory device comprises a memory cell array including plural memory cells provided at the intersections of plural first lines and plural second lines; and a write circuit. The write circuit, on execution of a write operation, executes a first step of applying a voltage across the first and second lines connected to a data-write-targeted, selected memory cell, and a different voltage across the first and second lines connected to a data-write-untargeted, unselected memory cell of the plural memory cells and, after execution of the first step, executes a second step of applying a voltage, required for data write, across the first and second lines connected to the selected memory cell, and bringing at least one of the first and second lines connected to the unselected memory cell into the floating state..
04/17/14
20140104929
new patent Method and apparatus managing worn cells in resistive memories
A method and apparatus for management worn resistive memory cells are presented. A normal read mode or worn memory cell detecting mode are used depending on the wear state of a resistive memory cell.
04/17/14
20140104922
new patent Apparatuses, circuits, and methods for biasing signal lines
Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line.
04/17/14
20140104919
new patent Semiconductor device having hierarchically structured bit lines and system including the same
A method for sensing data in an open bit line dynamic random access memory includes activating a word line in a first memory block of a first memory mat to transfer charge from memory cells to first sub-bit lines, the first memory mat being between a second memory mat and a third memory mat, activating first hierarchy switches corresponding to the first memory block to transfer charge from first sub-bit lines to global bit lines of the first memory mat, and activating second hierarchy switches corresponding to a second memory block in a second memory mat, to connect sub-bit lines to global bit lines of the second memory mat, the first memory block and the second memory block being equidistant from a first sense amplifier array located between the first memory mat and the second memory mat.. .
04/17/14
20140103471
new patent Low cost high density nonvolatile memory array device employing thin film transistors and back to back schottky diodes
An improved crosspoint memory array device comprising a plurality of memory cells, each memory cell being disposed at an intersection region of bit and word conductive lines, electrically coupled to one of the first conductive lines at a first terminal and to one of the second conductive lines at a second terminal, and comprising a controllable electrical resistance, wherein a back to back schottky diode is located between each memory cell and one of the said conductive lines, and wherein each conductive line is electrically coupled to at least two thin film transistors (tfts). The device is substantially produced in beol facilities without need of front end semiconductor production facilities, yet can be made with ultra high density and low cost..
04/17/14
20140103285
new patent Integrated circuitry, methods of forming memory cells, and methods of patterning platinum-containing material
Some embodiments include methods of patterning platinum-containing material. An opening may be formed to extend into an oxide.
04/17/14
20140103282
new patent Diffusion barrier layer for resistive random access memory cells
Provided are resistive random access memory (reram) cells having diffusion barrier layers formed from various materials, such as beryllium oxide or titanium silicon nitrides. Resistive switching layers used in reram cells often need to have at least one inert interface such that substantially no materials pass through this interface.
04/10/14
20140101517
Encoding and decoding redundant bits to accommodate memory cells having stuck-at faults
A data storage system has a memory circuit that comprises memory cells and a control circuit that receives data bits provided for storage in the memory cells. The control circuit encodes the data bits to generate a first set of redundant bits and encoded data bits, such that the encoded data bits selected for storage in a first subset of the memory cells with first stuck-at faults have digital values of corresponding ones of the first stuck-at faults.
04/10/14
20140101516
Encoding and decoding data to accommodate memory cells having stuck-at faults
A data storage system includes a memory circuit that has memory cells and a control circuit that is operable to receive data bits provided for storage in the memory cells. The control circuit is operable to receive a first matrix.
04/10/14
20140101395
Semiconductor memory devices including a discharge circuit
Semiconductor memory devices are provided. Each of the semiconductor memory devices may include first and second memory cells.
04/10/14
20140099341
Modulated immunodominance therapy
The invention involves generating a t cell response to subdominant antigens and using the cells to therapeutically change the cellular homeostasis and nature of the immune response. In a preferred embodiment, the cells are generated outside of the patient avoiding the influence of the patient's immunologic milieu.
04/10/14
20140098619
Non-volatile memory with overwrite capability and low write amplification
Providing for a non-volatile memory architecture having write and overwrite capabilities providing low write amplification to a storage system is described herein. By way of example, a memory array is disclosed comprising blocks and sub-blocks of two-terminal memory cells.
04/10/14
20140098616
Method and apparatus for reducing read disturb in memory
Various aspects of a nand memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution..
04/10/14
20140098614
Methods, devices, and systems for dealing with threshold voltage change in memory devices
The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array.
04/10/14
20140098613
Multi-port semiconductor memory device with multi-interface
A semiconductor memory device is provided which includes a first port configured to connect to a first processor and including a first interface circuit; a second port configured to connect to a second processor and including a second interface circuit; and a memory cell array including a first memory area connected to the first and second ports in common. The first memory area includes a plurality of magneto-resistive random access memory cells.
04/10/14
20140098612
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device comprises multiple memory strings each including a plurality of first and second groups of serially connected memory cells, and a back gate transistor serially connected between the first and second groups of memory cells, a plurality of word lines, each word line being connected to a control gate of a different memory cell in each of the memory strings, a voltage generating circuit configured to generate control voltages of different voltage levels, and a control circuit configured to control application of control voltages to the word lines and the back gate line. A control voltage applied to the back gate line may be varied depending on how far a selected word line is from the back gate line, and a control voltage applied to unselected word lines may be varied depending on how far the unselected word line is from the selected word line..
04/10/14
20140098610
Erased state reading
Memory cells that are indicated as being erased but are suspected of being partially programmed may be subject to a verification scheme that first performs a conventional read and then, if the conventional read does not indicate partial programming, performs a second read using lower read-pass voltage on at least one neighboring word line.. .
04/10/14
20140098609
Nonvolatile semiconductor memory apparatus
According to one embodiment, a nonvolatile semiconductor memory apparatus includes a memory cell array, a row decoder, a controller. The memory cell array includes a plurality of memory strings.
04/10/14
20140098607
Sensing memory cells
The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (adc).
04/10/14
20140098606
Reducing programming disturbance in memory devices
Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation.
04/10/14
20140098600
Semiconductor memory device having discriminary read and write operations according to temperature
A semiconductor memory device is provided which includes a memory cell array including magnetic memory cells arranged in a matrix form of rows and columns and connected with bit lines and a source line; and a temperature sensing unit configured to generate a temperature sensing signal by sensing a temperature of the memory cell array. A memory controller, constituting a memory system together with the semiconductor memory device, may control read and write operations of the semiconductor memory device differently according to the temperature sensing signal of the temperature sensing unit..
04/10/14
20140098597
Single-ended volatile memory access
A memory includes an array of memory cells that form rows and columns. The rows include memory cell pairs.
04/10/14
20140098595
Non-volatile memory device
A non-volatile memory device includes: a memory cell array including a plurality of memory cells each including a first variable resistance element and a first current steering element and a parameter generation circuit including a reference cell including a second variable resistance element and a second current steering element having the same current density-voltage characteristic as that of the first current steering element, wherein a conductive shorting layer for causing short-circuiting between the electrodes is formed on the side surfaces of the second variable resistance element.. .
04/10/14
20140098592
Resistive memory device including compensation resistive device and method of compensating resistance distribution
A resistive memory device includes a memory cell array, an input/output (i/o) sense amplifier unit, an address input buffer, a row decoder, and a column decoder. The memory cell array includes unit memory cells, and operates in response to a word line driving signal and a column selecting signal, each unit memory cell includes a resistive device and a compensation resistive device.
04/10/14
20140098590
Volatile memory access via shared bitlines
A memory includes an array of memory cells that form rows and columns. The rows of the array include memory cell pairs.
04/10/14
20140098228
Memory management in event recording systems
A vehicle event recorder is provided that includes a camera for capturing a video as discrete image frames, and that further includes a managed loop memory and a management system for generating a virtual ‘timeline dilation’ effect. To overcome size limits in the buffer memory of the video event recorder, the maximum time extension of a video series is increased by enabling a reduction in temporal resolution in exchange for an increase in the temporal extension.
04/10/14
20140097503
Memory cell array with semiconductor selection device for multiple memory cells
A memory array that includes access devices that are each electrically coupled to more than one memory cell. The memory cells are coupled to the access devices via diode devices.
04/10/14
20140097481
Non-volatile memory with vertical selection transistors
The present disclosure relates to a method for manufacturing a non-volatile memory on a semiconductive substrate, comprising the steps of implanting in the depth of the substrate a first doped region forming a source region of selection transistors, forming in the substrate a buried gate comprising deep parts extending between an upper face of the substrate and the first doped region, implanting between two adjacent deep parts of the buried gate, a second doped region forming a common drain region of common selection transistors of a pair of memory cells, the selection transistors of the pair of memory cells thus having channel regions extending between the first doped region and the second doped region, along faces opposite the two buried gate adjacent deep parts, and implanting along opposite upper edges of the buried gate, third doped regions forming source regions of charge accumulation transistors.. .
04/03/14
20140095962
Semiconductor device and operating method thereof
An operating method of a semiconductor device may comprise monitoring error handling information for a data read from a semiconductor memory device; and generating a refresh request for one or more memory cells of the semiconductor memory device according to the error handling information.. .
04/03/14
20140095770
Selective protection of lower page data during upper page write
Lower page data that may be endangered by programming upper page data in the same memory cells is protected during upper programming using protective upper page programming schemes. High overall programming speeds are maintained by selectively using protective upper programming schemes only where endangered data is committed and may not be recoverable from another location..
04/03/14
20140094011
Self-aligned method of forming a semiconductor memory array of floating gate memory cells with single poly layer
A method of forming a semiconductor memory cell that includes forming the floating and control gates from the same poly layer. Layers of insulation, conductive and second insulation material are formed over a substrate.
04/03/14
20140092696
Power management domino sram bit line discharge circuit
A domino static random access memory (sram) having one or more sram memory cells connected with a local bit line is disclosed. The sram may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected between the voltage supply and the global bit line.
04/03/14
20140092691
Semiconductor storage device
A semiconductor includes a memory cell array including a plurality of memory cells. A first amplifier produces, when activated, a first data signal related to data stored in a selected first one of the memory cells.
04/03/14
20140092686
Vertically-integrated nonvolatile memory devices having laterally-integrated ground select transistors
Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., nand-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines..
04/03/14
20140092685
Nonvolatile memory device, operating method thereof and memory system including the same
A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (ssls), the memory cells associated with the plurality of ssls constituting a memory block, and verifying the erasing operation to second memory cells associated with a second ssl after verifying the erasing operation to first memory cells associated with a first ssl.. .
04/03/14
20140092675
Two-port sram write tracking scheme
A write tracking control circuit includes an input node, and a first transistor configured to pre-charge a word bit line connected to at least two memory cells. The write tracking control circuit further includes a second transistor configured to pre-charge a read bit line connected to the at least two memory cells.
04/03/14
20140092672
Power management domino sram bit line discharge circuit
A domino static random access memory (sram) having one or more sram memory cells connected with a local bit line is disclosed. The sram may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected between the voltage supply and the global bit line.
04/03/14
20140092671
Cross-point variable resistance nonvolatile memory device
A cross-point memory device including memory cells each includes: a variable resistance element that reversibly changes at least between a low resistance state and a high resistance state; and a current steering element that has nonlinear current-voltage characteristics, and the cross-point memory device comprises a read circuit which includes: a reference voltage generation circuit which comprises at least the current steering element; a differential amplifier circuit which performs current amplification on an output voltage in the reference voltage generation circuit; a feedback controlled bit line voltage clamp circuit which sets the low voltage side reference voltage to increase with an output of the differential amplifier circuit; and a sense amplifier circuit which determines a resistance state of a selected memory cell according to an amount of current flowing through the selected memory cell.. .
04/03/14
20140092670
Non-volatile resistive memory devices and methods for biasing resistive memory structures thereof
The disclosed technology relates to a non-volatile resistive memory device and a method of using the same. In one aspect, the memory device comprises a plurality of memory cells interconnected by a plurality of bit lines, a plurality of word lines, a plurality of source lines and a plurality of form lines.
04/03/14
20140092665
Semiconductor memory device
A memory cell array includes a plurality of word lines each connected to gates of cell transistors in corresponding ones of a plurality of memory cells, a plurality of first control lines, a plurality of second control lines, a first ground circuit configured to ground the first control lines together in accordance with a first signal, and the first ground circuit includes a plurality of first transistors provided in a one-to-one correspondence with the first control lines, and each including a drain connected to a corresponding one of the first control lines, a first ground line configured to ground sources of the first transistors together, and a first signal line connected to gates of the first transistors to feed the first signal to the gates.. .
04/03/14
20140091218
Infrared detector system and method
An infrared detector system is described which includes a detector diode array 3 and a non volatile memory 1. The non volatile memory 1 can use cmos silicon fuse technology which can be polysilicon devices that are programmed using voltage-current-time profiles suitable for the silicon process technology, such that when applied will cause the polysilicon element to heat up rapidly and melt.
03/27/14
20140089763
Flash memory and accessing method thereof
A flash memory and an accessing method thereof are provided. The accessing method includes steps of receiving a plurality of contiguous accessing commands, sequentially selecting a plurality of word lines corresponding to the accessing commands, and accessing a plurality of memory cells on each of the word lines according to the accessing commands sequentially.
03/27/14
20140089762
Techniques associated with a read and write window budget for a two level memory system
Examples are disclosed for techniques associated with a read and write window budget for a two level memory (2lm) system. In some examples, a read and write window budget may be established for the 2lm system that includes a first level memory and a second level memory.
03/27/14
20140089612
Electronic counter in non-volatile limited endurance memory
The erasing increment logic is configured to erase a next cell of the sequence of non-volatile memory cells from a one state to a zero state, the erase phase terminating when all memory cells of the sequence of memory cells are in the zero state.. .
03/27/14
20140089570
Semiconductor memory
A memory block area in a semiconductor memory includes program segments. Each program segment includes a group of memory cells arranged at positions where word lines and bit lines intersect and connected to a common source line.
03/27/14
20140087558
Methods of forming memory cells; and methods of forming vertical structures
Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series.
03/27/14
20140086001
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors.
03/27/14
20140085994
Integrated circuitry, chip, method for testing a memory device, method for manufacturing an integrated circuit and method for manufacturing a chip
In various embodiments an integrated circuit or chip is provided, the integrated circuit including a memory device including a plurality of memory cells, and with the memory cells being configured to store a data content, and a controller being configured to write a predefined data pattern in the memory cells of the memory device, reading the data content of the memory cells, mapping each read data content which corresponds to an expected data content depending on the predefined data pattern to a predefined instruction for the controller, with the predefined instruction causing the controller to carry out a predefined action which is representative for the accurate operation of the memory cells, determining that the memory device operates accurately, if the controller carries out the predefined action, and determining that the memory device does not operate accurately, if the controller does not carry out the predefined action.. .
03/27/14
20140085989
Semiconductor memory device
According to one embodiment, a semiconductor memory device includes memory units each of which includes first and second select transistors and memory cells connected in series between the first and second select transistors. A control circuit applies a first potential difference between a source and a drain of either the first or second select transistor in a first memory unit, thereby programming either the first or second select transistor.
03/27/14
20140085983
Nonvolatile semiconductor memory device and control method thereof
A nonvolatile semiconductor memory device includes a memory cell array having first and second groups of memory strings, each memory string including first and second memory cells connected between select transistors. The nonvolatile semiconductor memory device further includes a first word line connected to the first memory cells of the memory strings, a second word line connected to the second memory cells of the memory strings, and a control unit configured to control application of control voltages to the select transistors and the word lines, such that a select line voltage is applied to the first word line and a non-select line voltage is applied to the second word line and not discharged while select transistors of the first group of memory strings are turned off and select transistors of the second group of memory strings are turned on..
03/27/14
20140085980
Memory devices and their operation with different sets of logical erase blocks
Systems comprising an array of memory cells organized into a plurality of erasable physical blocks, the address of physical block associated with an array of memory cells having a predetermined logical erase block size, wherein at least of the logical erase block size is smaller than another logical erase block size and a processor that selects the storage of data among different logical erase blocks in the array of memory cells based upon programmable and predetermined criteria.. .
03/27/14
20140085979
Nonvolatile semiconductor memory device
A memory cell array according to an embodiment includes a plurality of nand strings with a plurality of memory cells stacked, and a bit line is connected to the nand string. A word line is connected to a gate of the memory cell.
03/27/14
20140085977
Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate
A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to n-th memory cells.
03/27/14
20140085972
Semiconductor memory device, memory system and access method to semiconductor memory device
A semiconductor memory device includes a block array having an m number of memory blocks in a row direction and an n number of memory blocks in a column direction (m being an integer of 2 or more and n being an integer of 1 or more), a page selection circuit configured to select a row in the block array as a page to be selected, and a page buffer configured to store data to be written in a page selected by the page selection circuit or data read from the page. Each of the memory blocks includes a memory cell array having a plurality of memory cells, a row selection circuit configured to select a row of the memory cell array, and a column selection circuit configured to select a column of the memory cell array..
03/27/14
20140085963
Systems and methods for writing and non-destructively reading ferroelectric memories
Ferroelectric memory cell configurations, a system for controlling writing and reading to those configurations and a method for employing those configurations for writing and reading ferroelectric memories are provided. Ferroelectric memory cells according to the disclosed configurations are read without disturbing the stored data, i.e., not requiring any modification of the stored polarization state of the ferroelectric memory cell to read the stored data, thus providing a “non-destructive” reading process.
03/27/14
20140084948
Test vehicles for evaluating resistance of thin layers
Provided are test vehicles for evaluating various semiconductor materials. These materials may be used for various integrated circuit components, such as embedded resistors of resistive random access memory cells.
03/27/14
20140084353
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device with a first region including a memory cell array of a plurality of memory cells arrayed in three dimensions and a second region with a peripheral circuit for controlling the memory cell array is described. The peripheral circuit includes an insulating film and a template region.


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