FreshPatents.com Logo
Enter keywords:  

Track companies' patents here: Public Companies RSS Feeds | RSS Feed Home Page
Popular terms

[SEARCH]

Memory Cell topics
Memory Cell
Memory Cells
Phase Change Memory
Phase Change Material
Integrated Circuit
Semiconductor
Magnetic Material
Random Access
Volatile Memory
Memory Device
Conductive Layer
Mim Capacitor
Buffer Layer
Led Driving Circuit
Led Module

Follow us on Twitter
twitter icon@FreshPatents

Web & Computing
Cloud Computing
Ecommerce
Search patents
Smartphone patents
Social Media patents
Video patents
Website patents
Web Server
Android patents
Copyright patents
Database patents
Programming patents
Wearable Computing
Webcam patents

Web Companies
Apple patents
Google patents
Adobe patents
Ebay patents
Oracle patents
Yahoo patents

[SEARCH]

Memory Cell patents



      
           
This page is updated frequently with new Memory Cell-related patent applications. Subscribe to the Memory Cell RSS feed to automatically get the update: related Memory RSS feeds. RSS updates for this page: Memory Cell RSS RSS


Semiconductor device and method of operating the same

Multilevel cell nonvolatile memory system

Date/App# patent app List of recent Memory Cell-related patents
07/24/14
20140208060
 Systems and methods for accessing memory patent thumbnailnew patent Systems and methods for accessing memory
Methods of mapping memory cells to applications, methods of accessing memory cells, systems, and memory controllers are described. In some embodiments, a memory system including multiple physical channels is mapped into regions, such that any region spans each physical channel of the memory system.
07/24/14
20140208054
 Determining soft data for fractional digit memory cells patent thumbnailnew patent Determining soft data for fractional digit memory cells
Apparatuses and methods for determining soft data for fractional digit memory cells are provided. One example apparatus can include a controller to determine states of memory cells of a group of memory cells operated as fractional digit memory cells, and determine soft data based, at least partially, on dimensions to which particular memory cells correspond with respect to the group of memory cells, determined states of the memory cells with respect to a state adjacent a state corresponding to a swapping shell, and whether a particular memory cell is a candidate for swapping..
07/24/14
20140208044
 Semiconductor device and method of operating the same patent thumbnailnew patent Semiconductor device and method of operating the same
A method of operating a semiconductor device may comprise storing data in memory cells coupled to first word lines of memory blocks including the first word lines and second word lines located respectively between the first word lines, detecting a memory block, where data stored in the memory cells of the first word lines is invalidated, from the memory blocks, and storing data in memory cells coupled to the second word lines of the detected memory block.. .
07/24/14
20140208002
 Multilevel cell nonvolatile memory system patent thumbnailnew patent Multilevel cell nonvolatile memory system
A multilevel cell (mlc) nonvolatile memory system including a plurality of memory cells each cell storing first bit data and second bit data, and a controller programming the plurality of memory cells on a page-by-page basis, the controller programming original data to an original block and programming copy data that is the same as the original data to a mirroring block, wherein first bit page data and second bit page data of the original data are programmed to memory cells connected to the same word line, but the first bit page data and second bit page data of the copy data are programmed to memory cells connected to different word lines.. .
07/24/14
20140206171
 Memory cells, integrated devices, and methods of forming memory cells patent thumbnailnew patent Memory cells, integrated devices, and methods of forming memory cells
Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the chalcogenide material, and a thermal sink between the electrically conductive material and the chalcogenide material.
07/24/14
20140206106
 Magnetic memory and method of manufacturing the same patent thumbnailnew patent Magnetic memory and method of manufacturing the same
A magnetic memory according to an embodiment includes: at least one memory cell comprising a magnetoresistive element as a memory element, and first and second electrodes that energize the magnetoresistive element. The magnetoresistive element includes: a first magnetic layer having a variable magnetization direction perpendicular to a film plane; a tunnel barrier layer on the first magnetic layer; and a second magnetic layer on the tunnel barrier layer, and having a fixed magnetization direction perpendicular to the film plane.
07/24/14
20140206104
 Strain induced reduction of switching current in spin-transfer torque switching devices patent thumbnailnew patent Strain induced reduction of switching current in spin-transfer torque switching devices
Partial perpendicular magnetic anisotropy (ppma) type magnetic random access memory cells are constructed using processes and structural configurations that induce a directed static strain/stress on an mtj to increase the perpendicular magnetic anisotropy. Consequently, reduced switching current of the mtj results.
07/24/14
20140204692
 Semiconductor memory device and method with auxiliary i/o  line assist circuit and functionality patent thumbnailnew patent Semiconductor memory device and method with auxiliary i/o line assist circuit and functionality
A semiconductor memory device includes an i/o line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the i/o line on the basis of the read data, a read circuit for receiving the read data transmitted through the i/o line, and an assist circuit for amplifying the read data transmitted through the i/o line. The assist circuit is disposed farther away from a prescribed drive circuit included in the plurality of drive circuits as viewed from the read circuit.
07/24/14
20140204683
 Margin free pvt tolerant fast self-timed sense amplifier reset circuit patent thumbnailnew patent Margin free pvt tolerant fast self-timed sense amplifier reset circuit
In described embodiments, a circuit for providing a margin free pvt tolerant fast self-timed sense amplifier reset includes a sense amplifier coupled between a complementary pair of first and second bitlines in a memory cell, a first and second pmos drivers connected to internal nodes of the sense amplifier, respectively, and outputting a first and second output signals, wherein the second output signal is inverted by an inverter to form an inverted output signal, a read detect block receiving the first and inverted output signals and generating a transition detect signal that is latched by a cross-coupled inverters and employed to generate a sense amplifier enable signal with a global sense amplifier enable signal, and a push-pull logic formed by a nmos and a pmos in series to generate an output of the circuit.. .
07/24/14
20140204682
 Method and apparatus for simultaneously accessing a plurality of memory cells in a memory array to perform a read operation and/or a write operation patent thumbnailnew patent Method and apparatus for simultaneously accessing a plurality of memory cells in a memory array to perform a read operation and/or a write operation
A memory system includes a memory array and a read/write module. The memory array includes bit lines, word lines, and memory cells.
07/24/14
20140204681
new patent Semiconductor memory device and method of operating the same
A semiconductor memory device includes strings each configured to include a drain select transistor, memory cells, and a source select transistor coupled in series between a bit line and a common source line and peripheral circuits configured to perform an operation of precharging a bit line so that the precharge level of the bit line varies depending on whether an adjacent unselected memory cell, which is adjacent to a selected memory cell, is in the program state or the erase state, by supplying a first voltage to the adjacent unselected memory cell arranged toward the drain select transistor, a second voltage to the remaining memory cells in order to turn on the remaining memory cells, and a third voltage higher than a bit line precharge voltage to the common source line and perform a read operation of supplying a read voltage lower than the second voltage to the selected memory cell, the second voltage to the remaining memory cells including the adjacent unselected memory cell, and a ground voltage to the common source line.. .
07/24/14
20140204679
new patent Programming and/or erasing a memory device in response to its program and/or erase history
For one embodiment, a programming method includes programming one or more memory cells of a memory device during a programming operation, determining, internal to the memory device, a number of program pulses required to program a sample of the one or more memory cells of the memory device during the programming operation, and adjusting a program starting voltage level of one or more program pulses applied to the one or more memory cells during a subsequent programming operation in response, at least in part, to the number of program pulses required to program the sample of the one or more memory cells programed during the prior programming operation.. .
07/24/14
20140204677
new patent Apparatuses and methods including memory write operation
Some embodiments include apparatuses and methods having memory cells and access lines coupled to the memory cells. In one such apparatus, the access lines include a first access line and a second access line.
07/24/14
20140204670
new patent Semiconductor memory device using only single-channel transistor to apply voltage to selected word line
A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines.
07/24/14
20140204668
new patent Robust initialization with phase change memory cells in both configuration and array
The present application discloses phase-change memory architectures and methods, in which an additional test is performed, after the normal power-valid signal, to assure that the phase-change memory components which are used for storing configuration data are able to operate correctly. Surprisingly, the inventor has discovered that this additional test is highly desirable when using phase-change memory for configuration data..
07/24/14
20140204667
new patent Robust initialization with phase change memory cells in both configuration and array
The present application discloses phase-change memory architectures and methods, in which an additional test is performed, after the normal power-valid signal, to assure that the phase-change memory components which are used for storing configuration data are able to operate correctly. Surprisingly, the inventor has discovered that this additional test is highly desirable when using phase-change memory for configuration data..
07/24/14
20140204666
new patent Robust initialization with phase change memory cells in both configuration and array
The present application discloses phase-change memory architectures and methods, in which an additional test is performed, after the normal power-valid signal, to assure that the phase-change memory components which are used for storing configuration data are able to operate correctly. Surprisingly, the inventor has discovered that this additional test is highly desirable when using phase-change memory for configuration data..
07/24/14
20140204664
new patent Method of driving phase change memory device capable of reducing heat disturbance
A method of driving phase change memory device includes initializing all memory cells and programming individually at least two selected memory cells disposed at random positions, wherein the selected memory cells are selected among the initialized memory cells.. .
07/24/14
20140204660
new patent Memory having sense amplifier for output tracking by controlled feedback latch
In described embodiments, a memory circuit includes a static random access memory (sram) including n banks of memory cells, rows of m sense amplifiers, a controlled feedback latch storing a previous state of input data in a read cycle, a pull down select block coupled to the controlled feedback latch and the dummy sense amplifier, a dummy output latch coupled to the pull-down select block to store the read data, and a sram reset generation circuit coupled to the sense amplifier control circuits and the controlled feedback latch. The dummy output latch is a latch that is the same as a sense amplifier latch used in the local input/output circuit, thereby, no margin is involved between a reset of the sense amplifiers and the read data latched at the dummy output latch in the read cycle..
07/24/14
20140204658
new patent Memory cell flipping for mitigating sram bti
An apparatus may comprise a memory cell configured to operate according to a voltage mode, a voltage controller coupled with the memory cell, wherein the voltage controller is configured to change the voltage mode of the memory cell between a low voltage mode and a high voltage mode, and a memory controller module coupled with the memory cell, wherein the memory controller is configured to invert a logic state stored in the memory cell based on the voltage mode.. .
07/24/14
20140204656
new patent Low voltage dual supply memory cell with two word lines and activation circuitry
A memory cell includes a latch having a true data node and a complement data node, a true bitline, a complement bitline, a first access transistor coupled between the true bitline and the true data node, and a second access transistor coupled between the complement bitline and the complement data node. A wordline driver circuit includes a true wordline coupled to control the first access transistor and a complement wordline coupled to control the second access transistor.
07/24/14
20140204655
new patent Memory device, semiconductor device, and detecting method
To provide a memory device which can perform verification operation for detecting a memory cell whose data holding time is shorter than a predetermined length, accurately in a short time. Each memory cell includes at least a first capacitor, a second capacitor, and a transistor which functions as a switching element for controlling supply, storage, and release of charge in the first capacitor and the second capacitor.
07/24/14
20140204652
new patent Resistive memory device
A resistive memory device includes memory cell array blocks, a reference cell array block, two first and second sink transistors, and a word line. Each of the memory cell array blocks includes a row line, and the reference cell array block includes a reference row line.
07/24/14
20140204650
new patent Nonvolatile resistive memory device and writing method
A writing method for a resistive nonvolatile memory device includes writing data to a resistive nonvolatile memory cell using an up/down write pulse signal when the data is first data type, and writing data to the resistive nonvolatile memory cell using only one of an up write pulse signal and a down write pulse signal when the data is second data type.. .
07/24/14
20140204648
new patent Racetrack memory cells with a vertical nanowire storage element
A racetrack memory cell device include a dielectric, an electrode disposed in the dielectric, a metal strap disposed in the dielectric, a nanowire disposed in the dielectric between the electrode and the metal strap and a magnetic tunnel junction disposed in the dielectric on the metal strap, and axially with the nanowire.. .
07/24/14
20140204647
new patent Racetrack memory cells with a vertical nanowire storage element
A racetrack memory cell device include a dielectric, an electrode disposed in the dielectric, a metal strap disposed in the dielectric, a nanowire disposed in the dielectric between the electrode and the metal strap and a magnetic tunnel junction disposed in the dielectric on the metal strap, and axially with the nanowire.. .
07/24/14
20140204646
new patent High current capable access device for three-dimensional solid-state memory
The present invention generally relates to three-dimensional arrangement of memory cells and methods of addressing those cells. The memory cells can be arranged in a 3d orientation such that macro cells that are in the middle of the 3d arrangement can be addressed without the need for overhead wiring or by utilizing a minimal amount of overhead wiring.
07/24/14
20140203345
new patent Non-volatile semiconductor memory device
A non-volatile semiconductor memory device is proposed whereby voltage can be more flexibly set in accumulating electric charges into a selected memory cell transistor in comparison with a conventional device. In a non-volatile semiconductor memory device (1), when a selected memory cell transistor (115) is caused to accumulate electric charges, high voltage as writing prevention voltage is applied from a pmos transistor (9b) while low voltage as writing voltage is applied from an nmos transistor (15a).
07/24/14
20140203344
new patent 3d memory
Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack.
07/24/14
20140203343
new patent Non-volatile memory cell having a floating gate and a coupling gate with improved coupling ratio therebetween
A non-volatile memory cell having a split gate, wherein the floating gate and the coupling/control gate have complimentary non-planar shapes. The shape may be a step shape.
07/24/14
20140203342
new patent Ferroelectric random access memory with optimized hardmask
Device structures, fabrication methods, and design structures for a capacitor of a memory cell of ferroelectric random access memory device. The capacitor may include a first electrode comprised of a first conductor, a ferroelectric layer on the first electrode, a second electrode on the ferroelectric layer, and a cap layer on an upper surface of the second electrode.
07/24/14
20140203263
new patent Switchable memory diodes based on ferroelectric/conuugated polymer heterostructures and/or their composites
An embodiment of the present memory cell a first layer of a chosen conductivity type, and a second layer which includes ferroelectric semiconductor material of the opposite conductivity type, the layers forming a pn junction. The first layer may be a conjugated semiconductor polymer, or may also be of ferroelectric semiconductor material.
07/17/14
20140201692
Pre-colored methodology of multiple patterning
Some embodiments relate to a system that pre-colors word lines and control lines within a memory cell to avoid timing delays that result from processing variations introduced through multiple patterning lithography processes. The system has a memory element that stores a graphical ic layout with a memory circuit having layout features including a plurality of word lines and a plurality of y-control lines.
07/17/14
20140201600
Apparatus and method for encoding data for storage in multi-level nonvolatile memory
A controller for a nonvolatile memory includes an encoder and a decoder. The memory includes memory cells that each store data using more than two levels.
07/17/14
20140201596
Adaptation of analog memory cell read thresholds using partial ecc syndromes
A method includes storing data that is encoded with an error correction code (ecc) in a group of analog memory cells. The memory cells in the group are read using multiple sets of read thresholds.
07/17/14
20140201593
Efficient memory architecture for low density parity check decoding
A low density parity check (ldpc) decoder integrated on a single semiconductor substrate may comprise one or more arrays of first-type memory cells and one or more arrays of second-type memory cells. The ldpc decoder may be configured to store intrinsic messages in the array of first-type cells and to store extrinsic messages in the array of second-type cells.
07/17/14
20140201433
Selective activation of programming schemes in analog memory cell arrays
A method for data storage includes defining a first programming scheme that programs a group of analog memory cells while reducing interference caused by at least one memory cell that neighbors the group, and a second programming scheme that programs the group of the analog memory cells and does not reduce all of the interference reduced by the first programming scheme. One of the first and second programming schemes is selected based on a criterion defined with respect to the analog memory cells.
07/17/14
20140199821
Variable-resistance material memories and methods
Variable-resistance memory material cells are contacted by vertical bottom spacer electrodes. Variable-resistance material memory spacer cells are contacted along the edge by electrodes.
07/17/14
20140198598
System and method of performing power on reset for memory array circuits
The disclosure relates to an apparatus for deactivating one or more predecoded address lines of a memory circuit in response to one or more of the predecoded address lines being activated upon powering on of at least a portion of the apparatus. In particular, the apparatus includes a memory device; an address predecoder configured to activate one or more of a plurality of predecoded address lines based on an input address, wherein the plurality of predecoded address lines are coupled to the memory device for accessing one or more memory cells associated with the one or more activated predecoded address lines; and a power-on-reset circuit configured to deactivate one or more of the predecoded address lines in response to the one or more of the predecoded address lines being activated upon powering on the at least portion of the apparatus..
07/17/14
20140198595
Multiple read port memory system with a single port memory cell
An improved multi-port register file system and method of operating. The multi-port register file memory system comprises: n single memory bit cells each storing a data value and having a single bit cell write port and a single read port connecting a respective local bit line, wherein corresponding parallel activated single bit cells output a stored data value in parallel at n read port outputs to a respective local bit line of n local bit lines, each single bit cell accessed in parallel according to a decoded read address signal.
07/17/14
20140198589
Memory core and semiconductor memory device including the same
A semiconductor device may include a first memory cell connected to a bit-line and a first word-line, a second memory cell connected to a complementary bit-line and a second word-line, and an equalizer. The equalizer may be configured to transition a voltage of the bit-line and the complementary bit-line from a first voltage to a second voltage different from the first voltage at a first time period when the bit-line and complementary bit line are floating, and to transition the voltage of at least one of the bit-line and the complementary bit-line from the second voltage to a third voltage at a second time period after the first time period when the bit-line and complementary bit line are floating, the third voltage being different from the first and second voltages..
07/17/14
20140198584
Buffering systems for accessing multiple layers of memory in integrated circuits
Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory.
07/17/14
20140198581
Method of storing data in nonvolatile memory device and method of testing nonvolatile memory device
A method of storing data in a nonvolatile memory device comprises performing a program operation on target memory cells among multiple memory cells, performing a first verify operation to determine whether the target memory cells are in a program pass state or a program fail state, and as a consequence of determining that the target memory cells are in the program pass state, performing a second verify operation to determine whether the target memory cells exhibit a program error symptom.. .
07/17/14
20140198579
Disturb verify for programming memory cells
Apparatuses and methods for disturb verify for programming operations are described. Programming memory cells can include applying a number of programming pulses to a first memory cell, performing a disturb verify operation on a second memory cell adjacent to the first memory cell, and inhibiting the first memory cell from further programming in response to the second memory cell failing the disturb verify operation.
07/17/14
20140198578
Method of operating a split gate flash memory cell with coupling gate
A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the first region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate.
07/17/14
20140198577
Semiconductor device
A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a mos type first transistor section (3) used for information storage, and a mos type second transistor section (4) which selects the first transistor section.
07/17/14
20140198576
Programming technique for reducing program disturb in stacked memory structures
A programming bias technique is described for programming a stacked memory structure with a plurality of layers of memory cells. The technique includes the controller circuitry responsive to a program instruction to program data in target cells in a stack of cells at a particular multibit address.
07/17/14
20140198575
Method and apparatus for program and erase of select gate transistors
Techniques are provided for programming and erasing of select gate transistors in connection with the programming or erasing of a set of memory cells. In response to a program command to program memory cells, the select gate transistors are read to determine whether their vth is below an acceptable range, in which case the select gate transistors are programmed before the memory cells.
07/17/14
20140198574
Nonvolatile memory and manipulating method thereof
A manipulating method of a nonvolatile memory is provided and comprises following steps. The nonvolatile memory having a plurality of memory cell is provided.
07/17/14
20140198573
Memory system and method of operation thereof
A method of operating a memory system including a non-volatile memory device and a memory controller controlling the non-volatile memory device, includes reading data from a memory cell array in a unit of a page which includes a plurality of sectors; performing error correction decoding on the read data in a unit of a sector of the page; selecting at least one target sector which includes at least one uncorrectable error and selecting at least one pass sector wherein all errors of the pass sector are correctable by the error correction decoding; inhibiting precharging of bit-lines connected to the at least one pass sector while precharging target bit lines connected to the at least one target sector; and performing a read retry operation for data in the at least one target sector.. .
07/17/14
20140198571
Selecting memory cells
A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section.
07/17/14
20140198570
Programming multibit memory cells
A multiple bits per cell memory is operated by applying a one-pass, multiple-level programming, using a single pulse sequence one time (or in one-pass), such as an incremental pulse program sequence, with program verify steps for multiple target program levels, to program multiple bits per cell in a plurality of memory cells. Using these techniques, the number of program pulses required, and the time required for programming the data can be reduced.
07/17/14
20140198569
Flash memory, flash memory system and operating method of the same
A flash memory, a flash memory system, and an operating method thereof. The method of operating a flash memory includes counting the number of memory cells having threshold voltages included in a first adjacent threshold voltage range (defined by a first reference read voltage for distinguishing between initially separated adjacently located threshold voltage distributions and a first search read voltage having a first voltage difference from the first reference read voltage), and a second adjacent threshold voltage range (defined by the first reference read voltage and a second search read voltage having a second voltage difference from the first reference read voltage), and setting a first optimal read voltage based on the difference between the first and second counted numbers of the memory cells..
07/17/14
20140198567
Dynamic adjustment of read voltage levels based on memory cell threshold voltage distribution
A system and methods to find the threshold voltage distribution across a set of nonvolatile memory cells, such that embodiments may incorporate this distribution information into calculations that may change the read compare voltages used to read the memory cells, while ensuring adequate separation in read voltage between different data states at which the memory cells may be read.. .
07/17/14
20140198562
Ten-transistor dual-port sram with shared bit-line architecture
A 10-transistor dual-port sram with shared bit-line architecture includes a first memory cell and a second memory cell. The first memory cell has a first storage unit, a first switch set, and a second switch set.
07/17/14
20140198560
Memory cell and memory device having the same
A memory cell includes a metal oxide semiconductor (mos) capacitor including a gate coupled to a storage node and an electrode coupled to a synchronization control line. The mos capacitor adds a coupling voltage to the gate based on a change in voltage on the synchronization control line.
07/17/14
20140198558
Non-volatile storage system using opposite polarity programming signals for mim memory cell
A reversible resistance-switching metal-insulator-metal (mim) stack is provided which can be set to a low resistance state with a first polarity signal and reset to a higher resistance state with a second polarity signal. The first polarity signal is opposite in polarity than the second polarity signal.
07/17/14
20140198556
Nonvolatile memory device using variable resistive element and memory system having the same
A nonvolatile memory device, which has an improved read reliability through a refresh operation, and a memory system, are provided. The nonvolatile memory device includes a resistive memory cell, a reference resistor corresponding to the resistive memory cell, a reference sense amplifier electrically connected to the reference resistor and configured to change a transition time of an output value of the reference resistor, and a refresh request signal generator configured to output the refresh request signal for the resistive memory cell when the transition time of an output value of the reference resistor is in a preset refresh requiring period..
07/17/14
20140198553
Integrated circuit 3d phase change memory array and manufacturing method
A 3d phase change memory device can store multiple bits per cell represented by a plurality of non-overlapping ranges of resistance all of which are established by different resistance ranges corresponding to respective amorphous phase thickness of the phase change memory material. An array of access devices can underlie a plurality of conductive layers, separated from each other and from the array of access devices by insulating layers.
07/17/14
20140198552
Three-dimensional semiconductor devices and methods of fabricating the same
According to example embodiments of inventive concepts, a three-dimensional semiconductor device may include: a memory cell array including memory cells that may be arranged three-dimensionally, the memory cell array including a left side opposite a right side, and a top side opposite a bottom side in a plan view; at least one word line decoder adjacent to at least one of the left and right sides of the memory cell array; a page buffer adjacent to the bottom side of the memory cell array; and a string selection line decoder adjacent to one of the top and bottom sides of the memory cell array.. .
07/17/14
20140198551
Content addressable memory device having electrically floating body transistor
A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node.
07/17/14
20140198110
Reducing the number of sequential operations in an application to be performed on a shared memory cell
Methods and apparatuses to reduce the number of sequential operations such as atomic operations in an application to be performed on a shared memory cell may be provided. A translation unit can detect in the application multiple atomic operations to be performed on the same memory and replaces the multiple atomic operations with an equivalent single atomic operation.


Popular terms: [SEARCH]

Memory Cell topics: Memory Cell, Memory Cells, Phase Change Memory, Phase Change Material, Integrated Circuit, Semiconductor, Magnetic Material, Random Access, Volatile Memory, Memory Device, Conductive Layer, Mim Capacitor, Buffer Layer, Led Driving Circuit, Led Module

Follow us on Twitter
twitter icon@FreshPatents

###

This listing is a sample listing of patent applications related to Memory Cell for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Memory Cell with additional patents listed. Browse our RSS directory or Search for other possible listings.
     SHARE
  
         


FreshNews promo



0.2454

4119

3 - 0 - 100