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Memory Cell patents



      
           
This page is updated frequently with new Memory Cell-related patents. Subscribe to the Memory Cell RSS feed to automatically get the update: related Memory RSS feeds.

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Date/App# patent app List of recent Memory Cell-related patents
04/10/14
20140101519
 Non-volatile memory device having adjustable read voltage, memory system comprising same, and method of operating same patent thumbnailNon-volatile memory device having adjustable read voltage, memory system comprising same, and method of operating same
A nonvolatile memory device comprises a memory cell array comprising a selected page comprising multiple error correction code (ecc) units, and a voltage generation unit configured to generate a read voltage to read data from the selected page. Read voltage levels are set individually for the respective ecc units according to data detection results for each of the ecc units.
04/10/14
20140101517
 Encoding and decoding redundant bits to accommodate memory cells having stuck-at faults patent thumbnailEncoding and decoding redundant bits to accommodate memory cells having stuck-at faults
A data storage system has a memory circuit that comprises memory cells and a control circuit that receives data bits provided for storage in the memory cells. The control circuit encodes the data bits to generate a first set of redundant bits and encoded data bits, such that the encoded data bits selected for storage in a first subset of the memory cells with first stuck-at faults have digital values of corresponding ones of the first stuck-at faults.
04/10/14
20140101516
 Encoding and decoding data to accommodate memory cells having stuck-at faults patent thumbnailEncoding and decoding data to accommodate memory cells having stuck-at faults
A data storage system includes a memory circuit that has memory cells and a control circuit that is operable to receive data bits provided for storage in the memory cells. The control circuit is operable to receive a first matrix.
04/10/14
20140101395
 Semiconductor memory devices including a discharge circuit patent thumbnailSemiconductor memory devices including a discharge circuit
Semiconductor memory devices are provided. Each of the semiconductor memory devices may include first and second memory cells.
04/10/14
20140099758
 Sram devices utilizing strained-channel transistors and methods of manufacture patent thumbnailSram devices utilizing strained-channel transistors and methods of manufacture
A novel sram memory cell structure and method of making the same are provided. The sram memory cell structure comprises strained pmos transistors formed in a semiconductor substrate.
04/10/14
20140099341
 Modulated immunodominance therapy patent thumbnailModulated immunodominance therapy
The invention involves generating a t cell response to subdominant antigens and using the cells to therapeutically change the cellular homeostasis and nature of the immune response. In a preferred embodiment, the cells are generated outside of the patient avoiding the influence of the patient's immunologic milieu.
04/10/14
20140098619
 Non-volatile memory with overwrite capability and low write amplification patent thumbnailNon-volatile memory with overwrite capability and low write amplification
Providing for a non-volatile memory architecture having write and overwrite capabilities providing low write amplification to a storage system is described herein. By way of example, a memory array is disclosed comprising blocks and sub-blocks of two-terminal memory cells.
04/10/14
20140098616
 Method and apparatus for reducing read disturb in memory patent thumbnailMethod and apparatus for reducing read disturb in memory
Various aspects of a nand memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution..
04/10/14
20140098614
 Methods, devices, and systems for dealing with threshold voltage change in memory devices patent thumbnailMethods, devices, and systems for dealing with threshold voltage change in memory devices
The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array.
04/10/14
20140098613
 Multi-port semiconductor memory device with multi-interface patent thumbnailMulti-port semiconductor memory device with multi-interface
A semiconductor memory device is provided which includes a first port configured to connect to a first processor and including a first interface circuit; a second port configured to connect to a second processor and including a second interface circuit; and a memory cell array including a first memory area connected to the first and second ports in common. The first memory area includes a plurality of magneto-resistive random access memory cells.
04/10/14
20140098612
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device comprises multiple memory strings each including a plurality of first and second groups of serially connected memory cells, and a back gate transistor serially connected between the first and second groups of memory cells, a plurality of word lines, each word line being connected to a control gate of a different memory cell in each of the memory strings, a voltage generating circuit configured to generate control voltages of different voltage levels, and a control circuit configured to control application of control voltages to the word lines and the back gate line. A control voltage applied to the back gate line may be varied depending on how far a selected word line is from the back gate line, and a control voltage applied to unselected word lines may be varied depending on how far the unselected word line is from the selected word line..
04/10/14
20140098610
Erased state reading
Memory cells that are indicated as being erased but are suspected of being partially programmed may be subject to a verification scheme that first performs a conventional read and then, if the conventional read does not indicate partial programming, performs a second read using lower read-pass voltage on at least one neighboring word line.. .
04/10/14
20140098609
Nonvolatile semiconductor memory apparatus
According to one embodiment, a nonvolatile semiconductor memory apparatus includes a memory cell array, a row decoder, a controller. The memory cell array includes a plurality of memory strings.
04/10/14
20140098608
Apparatus and methods to perform read-while write (rww) operations
Subject matter disclosed herein relates to methods and apparatus, such as memory devices and systems including such memory devices. In one apparatus example, a plurality of block configurations may be employed.
04/10/14
20140098607
Sensing memory cells
The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (adc).
04/10/14
20140098606
Reducing programming disturbance in memory devices
Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation.
04/10/14
20140098603
Reliable set operation for phase-change memory cell
A phase-change memory (pcm) device and a method of writing data to the pcm device are described. The pcm device includes a multi-phase data storage cell having at least a set state and a reset state that may be established using a heater configured to heat the data storage cell.
04/10/14
20140098600
Semiconductor memory device having discriminary read and write operations according to temperature
A semiconductor memory device is provided which includes a memory cell array including magnetic memory cells arranged in a matrix form of rows and columns and connected with bit lines and a source line; and a temperature sensing unit configured to generate a temperature sensing signal by sensing a temperature of the memory cell array. A memory controller, constituting a memory system together with the semiconductor memory device, may control read and write operations of the semiconductor memory device differently according to the temperature sensing signal of the temperature sensing unit..
04/10/14
20140098599
Semiconductor memory device with data path option function
A semiconductor memory device may include a memory cell, a bit line connected to the memory cell, a bit line data latch circuit configured to sense-amplify data stored in the memory cell connected to the bit line and to store write data in the memory cell via the bit line; an input/output driver configured to output read data on the bit line to an external device or to drive the write data provided from the external device; and a selection unit configured to select whether the read data and the write data are communicated between the input/output driver and the memory cell with or without use of the bit line data latch circuit.. .
04/10/14
20140098598
Memory cell array latchup prevention
A current-limiting device may be configured to be placed along a power-supply bus to limit current through a first complimentary-metal-oxide semiconductor (cmos) circuit coupled to the power-supply bus so that current does not exceed a trigger current level of a pnpn diode in a second cmos circuit coupled to the power bus.. .
04/10/14
20140098597
Single-ended volatile memory access
A memory includes an array of memory cells that form rows and columns. The rows include memory cell pairs.
04/10/14
20140098595
Non-volatile memory device
A non-volatile memory device includes: a memory cell array including a plurality of memory cells each including a first variable resistance element and a first current steering element and a parameter generation circuit including a reference cell including a second variable resistance element and a second current steering element having the same current density-voltage characteristic as that of the first current steering element, wherein a conductive shorting layer for causing short-circuiting between the electrodes is formed on the side surfaces of the second variable resistance element.. .
04/10/14
20140098594
Cross point variable resistance nonvolatile memory device
Each memory cell is formed at a different one of cross points of bit lines extending in an x direction and formed in a plurality of layers and word lines extending in a y direction. In a multilayer cross point structure in which a plurality of vertical array planes sharing the word lines are aligned in the y direction each for a group of bit lines aligned in a z direction, even and odd layer bit line selection switch elements switch connection and disconnection between a global bit line and the commonly-connected even layer bit line and the commonly-connected odd layer bit line, respectively.
04/10/14
20140098593
Drift acceleration in resistance variable memory
The present disclosure includes apparatuses and methods including drift acceleration in resistance variable memory. A number of embodiments include applying a programming signal to the resistance variable memory cell to program the cell to a target state, subsequently applying a pre-read signal to the resistance variable memory cell to accelerate a drift of a resistance of the programmed cell, and subsequently applying a read signal to the resistance variable memory cell..
04/10/14
20140098592
Resistive memory device including compensation resistive device and method of compensating resistance distribution
A resistive memory device includes a memory cell array, an input/output (i/o) sense amplifier unit, an address input buffer, a row decoder, and a column decoder. The memory cell array includes unit memory cells, and operates in response to a word line driving signal and a column selecting signal, each unit memory cell includes a resistive device and a compensation resistive device.
04/10/14
20140098591
Antifuse otp memory cell with performance improvement prevention and operating method of memory
Provided is an otp memory cell including a first antifuse unit, a second antifuse unit, a select transistor, and a well region. The first and the second antifuse unit respectively include an antifuse layer and an antifuse gate disposed on a substrate in sequence.
04/10/14
20140098590
Volatile memory access via shared bitlines
A memory includes an array of memory cells that form rows and columns. The rows of the array include memory cell pairs.
04/10/14
20140098589
Replacement of a faulty memory cell with a spare cell for a memory circuit
A memory interface circuit device comprising a data structure configured to match and substitute an address in a run-time.. .
04/10/14
20140098228
Memory management in event recording systems
A vehicle event recorder is provided that includes a camera for capturing a video as discrete image frames, and that further includes a managed loop memory and a management system for generating a virtual ‘timeline dilation’ effect. To overcome size limits in the buffer memory of the video event recorder, the maximum time extension of a video series is increased by enabling a reduction in temporal resolution in exchange for an increase in the temporal extension.
04/10/14
20140097503
Memory cell array with semiconductor selection device for multiple memory cells
A memory array that includes access devices that are each electrically coupled to more than one memory cell. The memory cells are coupled to the access devices via diode devices.
04/10/14
20140097484
Vertical type memory device
A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections.
04/10/14
20140097481
Non-volatile memory with vertical selection transistors
The present disclosure relates to a method for manufacturing a non-volatile memory on a semiconductive substrate, comprising the steps of implanting in the depth of the substrate a first doped region forming a source region of selection transistors, forming in the substrate a buried gate comprising deep parts extending between an upper face of the substrate and the first doped region, implanting between two adjacent deep parts of the buried gate, a second doped region forming a common drain region of common selection transistors of a pair of memory cells, the selection transistors of the pair of memory cells thus having channel regions extending between the first doped region and the second doped region, along faces opposite the two buried gate adjacent deep parts, and implanting along opposite upper edges of the buried gate, third doped regions forming source regions of charge accumulation transistors.. .
04/10/14
20140097480
Method for manufacturing a memory cell, a method for manufacturing a memory cell arrangement, and a memory cell
A method for manufacturing a memory cell in accordance with various embodiments may include: forming at least one charge storing memory cell structure over a substrate, the charge storing memory cell structure having a first sidewall and a second sidewall opposite the first sidewall; forming an electrically conductive layer over the substrate and the charge storing memory cell structure; patterning the electrically conductive layer to form a spacer at the first sidewall and a blocking structure at the second sidewall of the charge storing memory cell structure; implanting first dopant atoms to form a first doped region in the substrate proximate the spacer, wherein the first dopant atoms are blocked by the blocking structure; removing the blocking structure after implanting the first dopant atoms; implanting second dopant atoms to form a second doped region in the substrate proximate the second sidewall of the charge storing memory cell structure.. .
04/10/14
20140097399
Phase change memory structures and methods
Methods, devices, and systems associated with phase change material memory are described herein. In one or more embodiments, a method of forming a phase change material memory cell includes forming a number of memory structure regions, wherein the memory structure regions include a bottom electrode material and a sacrificial material, forming a number of insulator regions between the number of memory structure regions, forming a number of openings between the number of insulator regions and forming a contoured surface on the number of insulator regions by removing the sacrificial material and a portion of the number of insulator regions, forming a number of dielectric spacers on the number of insulator regions, forming a contoured opening between the number of insulator regions and exposing the bottom electrode material by removing a portion of the number of dielectric spacers, and forming a phase change material in the opening between the number of insulator regions..
04/03/14
20140095962
Semiconductor device and operating method thereof
An operating method of a semiconductor device may comprise monitoring error handling information for a data read from a semiconductor memory device; and generating a refresh request for one or more memory cells of the semiconductor memory device according to the error handling information.. .
04/03/14
20140095770
Selective protection of lower page data during upper page write
Lower page data that may be endangered by programming upper page data in the same memory cells is protected during upper programming using protective upper page programming schemes. High overall programming speeds are maintained by selectively using protective upper programming schemes only where endangered data is committed and may not be recoverable from another location..
04/03/14
20140094011
Self-aligned method of forming a semiconductor memory array of floating gate memory cells with single poly layer
A method of forming a semiconductor memory cell that includes forming the floating and control gates from the same poly layer. Layers of insulation, conductive and second insulation material are formed over a substrate.
04/03/14
20140092696
Power management domino sram bit line discharge circuit
A domino static random access memory (sram) having one or more sram memory cells connected with a local bit line is disclosed. The sram may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected between the voltage supply and the global bit line.
04/03/14
20140092694
Multi-bit resistance measurement
An example embodiment is a circuit for determining a binary value of a memory cell. The circuit includes shunt capacitors having different capacitances to selectively couple with the memory cell, and a controller configured to iteratively charge the shunt capacitors to a first voltage until a selected shunt capacitor causes the first voltage to decay through the memory cell to a first reference voltage within a predetermined time range, determine a binary value of the most significant bits of the memory cell based on the selected shunt capacitor, charge the selected shunt capacitor to a second voltage after determining the binary value of the most significant bits of the memory cell, and determine a binary value of the least significant bits of the memory cell based on a decay of the second voltage at the selected shunt capacitor through the memory cell..
04/03/14
20140092691
Semiconductor storage device
A semiconductor includes a memory cell array including a plurality of memory cells. A first amplifier produces, when activated, a first data signal related to data stored in a selected first one of the memory cells.
04/03/14
20140092689
Method for programming non-volatile memory cell, non-volatile memory array and non-volatile memory apparatus
A method for programming a non-volatile memory cell is described. The memory cell includes a substrate, a gate over the substrate, a charge-trapping structure at least between the substrate and the gate, and first and second s/d regions in the substrate beside the gate.
04/03/14
20140092688
Non-volatile semiconductor storage device
In a split gate monos memory which carries out rewrite by hot carrier injection, retention characteristics are improved. A select gate electrode of a memory cell is connected to a select gate line, and a memory gate electrode is connected to a memory gate line.
04/03/14
20140092686
Vertically-integrated nonvolatile memory devices having laterally-integrated ground select transistors
Nonvolatile memory devices utilize vertically-stacked strings of nonvolatile memory cells (e.g., nand-type strings) that can be selectively coupled to common source lines within a substrate. This selective coupling may be provided by lateral ground select transistors having different threshold voltages that account for different lateral spacings between the vertically-stacked strings of nonvolatile memory cells and the common source lines..
04/03/14
20140092685
Nonvolatile memory device, operating method thereof and memory system including the same
A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (ssls), the memory cells associated with the plurality of ssls constituting a memory block, and verifying the erasing operation to second memory cells associated with a second ssl after verifying the erasing operation to first memory cells associated with a first ssl.. .
04/03/14
20140092681
Semiconductor device and driving method thereof
A semiconductor device includes: a source line; a bit line; a word line; a memory cell connected to the bit line and the word line; a driver circuit which drives a plurality of second signal lines and a plurality of word lines so as to select the memory cell specified by an address signal; a potential generating circuit which generates a writing potential and a plurality of reading potentials to supply to a writing circuit and a reading circuit; and a control circuit which selects one of a plurality of voltages for correction on a basis of results of the reading circuit comparing a potential of the bit line with the plurality of reading potentials.. .
04/03/14
20140092680
Multiple well bias memory
A multiple well bias memory device that includes a semiconductor substrate; a first well of a first conductivity type formed in the semiconductor substrate and having a memory cell formed therein; and a second well of the first conductivity type formed in the semiconductor substrate and having formed therein a sense amplifier configured to sense and amplify data from the memory cell. The first and second wells have different doping concentrations and are biased to first and second voltages, respectively.
04/03/14
20140092679
Memory device and writing method thereof
A write amplifier for driving a bit line connected to a selected phase change memory cell drives the bit line with a first current driving capability and then drives the bit line with a second current driving capability lower than the first current driving capability.. .
04/03/14
20140092677
Decreased switching current in spin-transfer torque memory
Switching current in spin-transfer torque memory (sttm) can be decreased. A magnetic memory cell is driven with a first pulse on a write line of the memory cell to heat the cell.
04/03/14
20140092676
Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage
In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use.
04/03/14
20140092675
Two-port sram write tracking scheme
A write tracking control circuit includes an input node, and a first transistor configured to pre-charge a word bit line connected to at least two memory cells. The write tracking control circuit further includes a second transistor configured to pre-charge a read bit line connected to the at least two memory cells.
04/03/14
20140092673
Memory cell
This invention relates generally to a memory cell. The embodiments of the present invention provide a sram cell and a sram cell array comprising such sram cell.
04/03/14
20140092672
Power management domino sram bit line discharge circuit
A domino static random access memory (sram) having one or more sram memory cells connected with a local bit line is disclosed. The sram may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected between the voltage supply and the global bit line.
04/03/14
20140092671
Cross-point variable resistance nonvolatile memory device
A cross-point memory device including memory cells each includes: a variable resistance element that reversibly changes at least between a low resistance state and a high resistance state; and a current steering element that has nonlinear current-voltage characteristics, and the cross-point memory device comprises a read circuit which includes: a reference voltage generation circuit which comprises at least the current steering element; a differential amplifier circuit which performs current amplification on an output voltage in the reference voltage generation circuit; a feedback controlled bit line voltage clamp circuit which sets the low voltage side reference voltage to increase with an output of the differential amplifier circuit; and a sense amplifier circuit which determines a resistance state of a selected memory cell according to an amount of current flowing through the selected memory cell.. .
04/03/14
20140092670
Non-volatile resistive memory devices and methods for biasing resistive memory structures thereof
The disclosed technology relates to a non-volatile resistive memory device and a method of using the same. In one aspect, the memory device comprises a plurality of memory cells interconnected by a plurality of bit lines, a plurality of word lines, a plurality of source lines and a plurality of form lines.
04/03/14
20140092665
Semiconductor memory device
A memory cell array includes a plurality of word lines each connected to gates of cell transistors in corresponding ones of a plurality of memory cells, a plurality of first control lines, a plurality of second control lines, a first ground circuit configured to ground the first control lines together in accordance with a first signal, and the first ground circuit includes a plurality of first transistors provided in a one-to-one correspondence with the first control lines, and each including a drain connected to a corresponding one of the first control lines, a first ground line configured to ground sources of the first transistors together, and a first signal line connected to gates of the first transistors to feed the first signal to the gates.. .


Popular terms: [SEARCH]

Memory Cell topics: Memory Cell, Memory Cells, Phase Change Memory, Phase Change Material, Integrated Circuit, Semiconductor, Magnetic Material, Random Access, Volatile Memory, Memory Device, Conductive Layer, Mim Capacitor, Buffer Layer, Led Driving Circuit, Led Module

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This listing is a sample listing of patents related to Memory Cell for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Memory Cell with additional patents listed. Browse our RSS directory or Search for other possible listings.
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