|| List of recent Memory Cell-related patents
| Semiconductor memory device|
A semiconductor memory device includes a memory cell array configured to include sub memory blocks and a redundancy memory block, data line groups configured to deliver data to be programmed into the sub memory blocks and data read from the sub memory blocks, a redundancy data line group configured to deliver data to be programmed into the redundancy memory block and data read from the redundancy memory block, and switching circuits configured to couple selectively the data line groups to the redundancy data line group.. .
| Dynamic random access memory for storing randomized data and method of operating the same|
A dynamic random access memory (dram) includes a memory cell array, a data input/output circuit, and a data randomizer configured to randomize data to be stored in the memory cell array. The data randomizer includes an encoder configured to generate write data by encoding input data received from the data input/output circuit using a randomization code and to output the write data to the memory cell array.
| Methods of forming a programmable region that comprises a multivalent metal oxide portion and an oxygen containing dielectric portion|
A method of forming a memory cell includes forming one of multivalent metal oxide material or oxygen-containing dielectric material over a first conductive structure. An outer surface of the multivalent metal oxide material or the oxygen-containing dielectric material is treated with an organic base.
| Memory cells and methods of forming memory cells|
Some embodiments include memory cells having programmable material between a pair of electrodes. The programmable material includes a material selected from the group consisting of a metal silicate with a ratio of metal to silicon within a range of from about 2 to about 6, and metal aluminate with a ratio of metal to aluminum within a range of from about 2 to about 6.
| Semiconductor device and method of manufacturing the same|
In a power feeding region of a memory cell (mc) in which a sidewall-shaped memory gate electrode (mg) of a memory nmis (qnm) is provided by self alignment on a side surface of a selection gate electrode (cg) of a selection nmis (qnc) via an insulating film, a plug (pm) which supplies a voltage to the memory gate electrode (mg) is embedded in a contact hole (cm) formed in an interlayer insulating film (9) formed on the memory gate electrode (mg) and is electrically connected to the memory gate electrode (mg). Since a cap insulating film (cap) is formed on an upper surface of the selection gate electrode (cg), the electrical conduction between the plug (pm) and the selection gate electrode (cg) can be prevented..
| Method of manufacturing flash memory cell|
A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ono) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ono spacer, and forming a floating gate at outer sides of the ono spacer on the second dielectric layer, respectively.. .
| Nonvolatile memory devices|
A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors.
| Non-volatile memory array and method of using same for fractional word programming|
A non-volatile memory device that includes n planes of non-volatile memory cells (where n is an integer greater than 1). Each plane of non-volatile memory cells includes a plurality of memory cells configured in rows and columns.
| Non-volatile memory device with plural reference cells, and method of setting the reference cells|
A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells..
| Methods and apparatus for designing and constructing high-speed memory circuits|
Static random access memory (sram) circuits are used in most digital integrated circuits to store digital data bits. Sram memory circuits are generally read by decoding an address, reading from an addressed memory cell using a set of bit lines, outputting data from the read memory cell, and precharging the bit lines for a subsequent memory cycle.
| Memory apparatus and methods|
Embodiments of apparatus and methods having a memory device can include a line to exchange information with a string of memory cells and a transistor coupled between the string of memory cells and the line. Such a memory device can also include a module configured to couple a gate of the transistor to a node during a first time interval of a memory operation and decouple the gate from the node during a second time interval of the memory operation.
| Partial local self boosting for nand|
A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines.
| Sensing operations in a memory device|
Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output.
| Programming nonvolatile memory device using program voltage with variable offset|
A method of programming a nonvolatile memory device comprises applying at least one test program pulse to selected memory cells located in a scan read area, performing a scan read operation on the selected memory cells following application of the at least one test program pulse to detect at least one one-shot upper cell, calculating an offset voltage corresponding to a scan read region at which the scan read operation is performed, setting a program start bias using the offset voltage, and executing at least one program loop using the program start bias.. .
| Sensing data stored in memory|
The present disclosure includes apparatuses and methods for sensing data stored in memory. A number of embodiments include an array of memory cells, and a controller coupled to the array and configured to sense a page of memory cells coupled to an activated access line by pre-charging only a single subset of a number of data lines coupled to the page, wherein more than two subsets of data lines are coupled to the page and the single subset is coupled to those memory cells storing at least a portion of a single sector of data of the page, and sensing the single subset of the number of data lines to determine the at least a portion of the single sector of data..
| Split block decoder for a nonvolatile memory device|
A non-volatile memory device having a memory array organized into a plurality of memory blocks, having either planar memory cells or stacks of cells. Row decoding circuitry of the memory device is configured to select a group of the plurality of memory blocks in response to a first row address, and to select a memory block of the group for receiving row signals in response to a second row address.
| Programming based on controller performance requirements|
Methods and solid state drives are disclosed, for example a solid state drive that is adapted to receive and transmit analog data signals representative of bit patterns of three or more levels (such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits). Programming of the solid state drive, comprising an array of non-volatile memory cells, might include adjusting the level of each memory cell being programmed in response to a desired performance level of a controller circuit..
| Accelerated soft read for multi-level cell nonvolatile memories|
A memory device includes a memory array comprising multi-level memory cells, and control circuitry coupled to the memory array. The control circuitry is configured to perform accelerated soft read operations on at least a portion of the memory array.
| Memory device architecture|
Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.. .
| Latch-based memory array|
The invention concerns a memory array having memory cells arranged in columns and rows, the memory cells of each column being coupled to at least one common write line of their column, the memory cells of each row being coupled to a common selection line of their row, wherein each of the memory cells includes a latch formed of a pair of inverters cross-coupled between first and second storage nodes; a first transistor coupled between the first storage node and a first test data input; and a second transistor coupled between the second storage node and a second test data input.. .
| Semiconductor memory|
Provided is a semiconductor memory in which it is easier to read a read margin when an ambient temperature changes. The semiconductor memory includes: a memory cell including a first variable resistance element having variable electric resistance; a first reference cell including a second variable resistance element having variable electric resistance, and serving as a point of reference for a magnitude of electric resistance of the memory cell; and a second reference cell serving as a point of reference for a magnitude of electric resistance of the first reference cell, in which a first temperature coefficient of the first variable resistance element and a second temperature coefficient of the second variable resistance element have the same polarity..
| Memory cells, non-volatile memory arrays, methods of operating memory cells, methods of writing to and writing from a memory cell, and methods of programming a memory cell|
In one aspect, a method of operating a memory cell includes using different electrodes to change a programmed state of the memory cell than are used to read the programmed state of the memory cell. In one aspect, a memory cell includes first and second opposing electrodes having material received there-between.
| Nonvolatile memory device and method of performing forming the same|
A nonvolatile memory device including a control unit configured to read resistance value information for each of memory cells as initial resistance value information and store it temporarily before a voltage pulse for forming is applied, to set resistance value information as a threshold value serving as a target for completion of the forming, the resistance value information being obtained by multiplying the initial resistance value information by a predetermined coefficient, and to repeat application of the voltage pulse for forming and reading of the resistance value information until a resistance value indicated by the resistance value information on the memory cell becomes lower than a resistance value indicated by the threshold value.. .
| Semiconductor memory device|
A semiconductor memory device comprises a memory cell array including plural memory cells provided at the intersections of plural first lines and plural second lines; and a write circuit. The write circuit, on execution of a write operation, executes a first step of applying a voltage across the first and second lines connected to a data-write-targeted, selected memory cell, and a different voltage across the first and second lines connected to a data-write-untargeted, unselected memory cell of the plural memory cells and, after execution of the first step, executes a second step of applying a voltage, required for data write, across the first and second lines connected to the selected memory cell, and bringing at least one of the first and second lines connected to the unselected memory cell into the floating state..
| Method and apparatus managing worn cells in resistive memories|
A method and apparatus for management worn resistive memory cells are presented. A normal read mode or worn memory cell detecting mode are used depending on the wear state of a resistive memory cell.
| Configuring resistive random access memory (rram) array for write operations|
A system includes a resistive random access memory cell and a driver circuit. The resistive random access memory cell includes a resistive element and a switching element, and has a first terminal connected to a bit line and a second terminal connected to a word line.
| Systems and methods for reading resistive random access memory (rram) cells|
A system including a resistive random access memory cell connected to a word line and a bit line and a pre-charge circuit configured to pre-charge the bit line to a first voltage with the word line being unselected. A driver circuit selects the word line at a first time subsequent to the bit line being charged to the first voltage.
| Cross-point variable resistance nonvolatile memory device and reading method for cross-point variable resistance nonvolatile memory device|
A cross-point variable resistance nonvolatile memory device comprises: a memory cell array; a column decoder and pre-charge circuit which pre-charges a selected word line to a first voltage in a period p1 among the period p1, a period p2, and a period s that are included in this order in a read operation of a memory cell; a low decoder driver which pre-charges a selected word line to the first voltage in the periods p1 and p2 and sets the selected word line to a third voltage different from the first voltage in the period s; a feedback controlled bit line voltage clamp circuit which sets the selected bit line to a second voltage in the periods p2 and s; and a sense amplifier which determines the resistance state in a memory cell at a cross-point of the selected word line and the selected bit line in the period s.. .
| Apparatuses, circuits, and methods for biasing signal lines|
Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line.
| Semiconductor device|
According to one embodiment, a semiconductor device includes a processor chip, and a memory chip stacked on the processor chip with bumps and including a memory cell unit and a memory logic unit. The bumps are arranged on the memory logic unit.
| Semiconductor device having hierarchically structured bit lines and system including the same|
A method for sensing data in an open bit line dynamic random access memory includes activating a word line in a first memory block of a first memory mat to transfer charge from memory cells to first sub-bit lines, the first memory mat being between a second memory mat and a third memory mat, activating first hierarchy switches corresponding to the first memory block to transfer charge from first sub-bit lines to global bit lines of the first memory mat, and activating second hierarchy switches corresponding to a second memory block in a second memory mat, to connect sub-bit lines to global bit lines of the second memory mat, the first memory block and the second memory block being equidistant from a first sense amplifier array located between the first memory mat and the second memory mat.. .
| Semiconductor device having memory cell array divided into plural memory mats|
A semiconductor device includes a plurality of memory mats arranged in an x direction and a mat selecting circuit that activates a part of the memory mats based on a row address and maintains the rest of the memory mats inactivated. The memory mats are divided into a plurality of memory mat groups each including the same number of memory mats arranged in the x direction.
| Semiconductor memory device|
A semiconductor memory device includes a memory cell, a pair of local bit lines connected to the memory cell, first and second transistors, one end of the current channel of each connected to a power supply and the other end of the current channel of each connected to one of the local bit lines, third and fourth transistors, one end of the current channel of each connected to one of the local bit lines, the other end of the current channel of each connected to one of the global bit lines, fifth and sixth transistors, one end of the current channel of each connected to one of the global bit lines and the other end of the current channel of which connected to the power supply. The device further includes a control unit configured to control the transistors..
| Reactive material for integrated circuit tamper detection and response|
The present disclosure relates to integrated circuits having tamper detection and response devices and methods for manufacturing such integrated circuits. One integrated circuit having a tamper detection and response device includes at least one reactive material and at least one memory cell coupled to the at least one reactive material.
| Low cost high density nonvolatile memory array device employing thin film transistors and back to back schottky diodes|
An improved crosspoint memory array device comprising a plurality of memory cells, each memory cell being disposed at an intersection region of bit and word conductive lines, electrically coupled to one of the first conductive lines at a first terminal and to one of the second conductive lines at a second terminal, and comprising a controllable electrical resistance, wherein a back to back schottky diode is located between each memory cell and one of the said conductive lines, and wherein each conductive line is electrically coupled to at least two thin film transistors (tfts). The device is substantially produced in beol facilities without need of front end semiconductor production facilities, yet can be made with ultra high density and low cost..
| Semiconductor sram structures and fabrication methods|
Various embodiments provide semiconductor structures and their fabrication methods. An sram memory cell can include at least one semiconductor structure, and an sram memory can include at least one sram memory cell.
| Memory arrays and associated methods of manufacturing|
Memory arrays and associated methods of manufacturing are disclosed herein. In one embodiment, a memory array includes an access line extending along a first direction and a first contact line and a second contact line extending along a second direction different from the first direction.
| Integrated circuit tamper detection and response|
The present disclosure relates to integrated circuits having tamper detection and response devices and methods for manufacturing such integrated circuits. One integrated circuit having a tamper detection and response device includes at least one photovoltaic cell and at least one memory cell coupled to the at least one photovoltaic cell.
| Integrated circuitry, methods of forming memory cells, and methods of patterning platinum-containing material|
Some embodiments include methods of patterning platinum-containing material. An opening may be formed to extend into an oxide.
| Diffusion barrier layer for resistive random access memory cells|
Provided are resistive random access memory (reram) cells having diffusion barrier layers formed from various materials, such as beryllium oxide or titanium silicon nitrides. Resistive switching layers used in reram cells often need to have at least one inert interface such that substantially no materials pass through this interface.
|Non-volatile memory device having adjustable read voltage, memory system comprising same, and method of operating same|
A nonvolatile memory device comprises a memory cell array comprising a selected page comprising multiple error correction code (ecc) units, and a voltage generation unit configured to generate a read voltage to read data from the selected page. Read voltage levels are set individually for the respective ecc units according to data detection results for each of the ecc units.
|Encoding and decoding redundant bits to accommodate memory cells having stuck-at faults|
A data storage system has a memory circuit that comprises memory cells and a control circuit that receives data bits provided for storage in the memory cells. The control circuit encodes the data bits to generate a first set of redundant bits and encoded data bits, such that the encoded data bits selected for storage in a first subset of the memory cells with first stuck-at faults have digital values of corresponding ones of the first stuck-at faults.
|Encoding and decoding data to accommodate memory cells having stuck-at faults|
A data storage system includes a memory circuit that has memory cells and a control circuit that is operable to receive data bits provided for storage in the memory cells. The control circuit is operable to receive a first matrix.
|Semiconductor memory devices including a discharge circuit|
Semiconductor memory devices are provided. Each of the semiconductor memory devices may include first and second memory cells.
|Sram devices utilizing strained-channel transistors and methods of manufacture|
A novel sram memory cell structure and method of making the same are provided. The sram memory cell structure comprises strained pmos transistors formed in a semiconductor substrate.
|Modulated immunodominance therapy|
The invention involves generating a t cell response to subdominant antigens and using the cells to therapeutically change the cellular homeostasis and nature of the immune response. In a preferred embodiment, the cells are generated outside of the patient avoiding the influence of the patient's immunologic milieu.