|| List of recent Memory Cell-related patents
|Apparatus and method for determining an operating condition of a memory cell based on cycle information|
A method populates a parameter set for dynamically adjusting an operating condition in a memory block of a non-volatile memory circuit. A desired condition limit is identified, and a first parameter is computed as a function of a first memory operation to be performed on the memory block.
|Scheduling of reactive i/o operations in a storage environment|
A system and method for effectively scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network.
|Preloading data into a flash storage device|
Programmer's data that is transferred from a programming device to a storage device is initially stored in a memory device of the storage device by using a durable data-retention storage setup. After the storage device is embedded in a host device, the programmer's data is internally (i.e., in the storage device) read from the memory device and rewritten into the memory device by using a conventional storage setup.
|Garbage collection with demotion of valid data to a lower memory tier|
Method and apparatus for managing data in a memory. In accordance with some embodiments, a first tier of a multi-tier memory structure is arranged into a plurality of garbage collection units (gcus).
|Method for forming resistance-switching memory cell with multiple electrodes using nano-particle hard mask|
In a fabrication process for reversible resistance-switching memory cells, a bottom electrode layer is coated with nano-particles. The nano-particles are used to etch the bottom electrode layer, forming multiple narrow, spaced apart bottom electrode structures for each memory cell.
|Method of manufacturing a semiconductor device|
A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n+-type semiconductor regions for a source or a drain of misfet are formed in the peripheral circuit region.
|3d non-volatile memory device and method for fabricating the same|
A non-volatile memory device having a string of a plurality of memory cells that are serially coupled, wherein the string of memory cells includes a plurality of second channels of a pillar type, a first channel coupling lower end portions of the plurality of the second channels with each other, and a plurality of control gate electrodes surrounding the plurality of the second channels.. .
|Method of manufacturing semiconductor device|
Provided is a semiconductor device having improved performance. In a semiconductor substrate located in a memory cell region, a memory cell of a nonvolatile memory is formed while, in the semiconductor substrate located in a peripheral circuit region, a misfet is formed.
|Memory device word line drivers and methods|
Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors.
|Memory device and corresponding reading method|
An electrically erasable and programmable non-volatile memory device includes memory cells arranged in rows and columns, and each column of memory cells is associated with a respective local bit line. The local bit lines are divided into packets of local bit lines, each packet of local bit lines associated with a respective main bit line.
A semiconductor apparatus includes: a memory cell block configured to store data; a fuse block including a plurality of fuses configured to store fuse information; an i/o driver configured to output the data transmitted through a global line to a pad; and a fuse driver configured to output the fuse information transmitted through a test global line to the pad during a test mode.. .
|Load and short current measurement by current summation technique|
Methods for monitoring one or more load currents corresponding with one or more voltage regulators used during operation of a semiconductor memory are described. The one or more load currents may be due to the biasing of memory cells within a memory array or due to the presence of shorts between lines in the memory array.
|Data writing method, and memory control circuit unit and memory storage apparatus using the same|
A data writing method for writing data into a memory cell of a rewritable non-volatile memory module, and a memory control circuit unit and a memory storage apparatus using the same area provided. The method includes recording a wear degree of the memory cell and detecting an operating temperature of the memory storage apparatus.
|Method of programming flash memory|
A method of programming a nand flash memory cell string. The method includes a pre-boost stage configured to elevate channel voltage of a selected memory cell, and a boost stage is introduced after the pre-boost stage.
|Nonvolatile semiconductor memory device|
An erase verify operation is executed divided into at least a first erase verify operation and a second erase verify operation. The first erase verify operation is an operation that applies a verify read voltage only to a first group of memory cells among the plurality of memory cells included in the nand cell unit, and applies a first read pass voltage to memory cells other than the first group of memory cells.
|Efficient smart verify method for programming 3d non-volatile memory|
In a programming operation of a 3d stacked non-volatile memory device, an initial set of memory cells on a selected word line layer, involving fewer than all memory cells on a selected word line layer, are programmed first as a test case to determine optimal conditions for programming the remaining memory cells on the selected word line layer. For example, a number of program-verify iterations or loops which are needed to program the initial set of memory cells an initial amount is determined.
|Bit line resistance compensation|
Methods for compensating for variations in bit line resistance during sensing of memory cells are described. The variations in bit line resistance may occur die-to-die or plane-to-plane on the same die.
|System and method for reading memory cells by accounting for inter-cell interference|
A system including a read module and a detector module. The read module is configured to generate a plurality of read signals by reading a plurality of memory cells located along a bit line or a word line.
|Tamper detection and response in a memory device|
A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements.
|Temperature compensation of conductive bridge memory arrays|
Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array.
|Arrays of vertically stacked tiers of non-volatile cross point memory cells and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells|
An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers.
|Optimization of variable resistance memory cells|
A data storage device may generally be constructed and operated with at least one variable resistance memory cell configured with non-factory operational parameters by a controller. The non-factory operational parameters are assigned in response to an identified variance from a predetermined threshold in at least one variable resistance memory cell..
|Nonvolatile semiconductor memory device|
According to one embodiment, a memory cell includes a gate insulating layer on the active area, a floating gate electrode on the gate insulating layer, the floating gate electrode having a lower portion with a first width and a higher portion with a second width narrower than the first width, an intermediate insulating layer covering an end of the higher portion of the floating gate electrode, a charge storage layer being adjacent to the intermediate layer, an inter-electrode insulating layer covering the floating gate electrode and the charge storage layer, and a control gate electrode on the inter-electrode insulating layer.. .
|Electronic device including a nonvolatile memory structure having an antifuse component|
An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include a substrate, an access transistor, a read transistor, and an antifuse component. Each of the access and read transistors can include source/drain regions at least partly within the substrate, a gate dielectric layer overlying the substrate, and a gate electrode overlying the gate dielectric layer.
|Flash memory cells having trenched storage elements|
An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench.
|Resistance-switching memory cell with multiple electrodes|
A reversible resistance-switching memory cell has multiple narrow, spaced apart bottom electrode structures. The raised structures can be formed by coating a bottom electrode layer with nano-particles and etching the bottom electrode layer.
|Circuit analysis device and circuit analysis method|
A circuit analysis device includes: a processor configured to execute a procedure by: calculating, for power supply noise included in a power supply voltage supplied to a semiconductor memory device, variation characteristics of an electric potential relative to the power supply voltage in a specific memory cell included in a memory cell array; calculating power supply noise of a power supply system that occurs when a current is supplied to an equivalent circuit of the power supply system under a predetermined condition, the power supply system including a power supply line and an element for supplying a power supply voltage from a voltage source to a semiconductor device; calculating, from the variation characteristics, the electric potential obtained when the power supply noise is equal to a specific magnitude; and determining, by comparing the calculated electric potential with a threshold, whether memory latch-up will occur in the specific memory cell.. .
|Semiconducotr memory device including non-volatile memory cell array|
A semiconductor memory device that may correct error data using an error correction circuit is disclosed. The semiconductor memory device may include a dram cell array, a parity generator, a nonvolatile memory cell array and an error correction circuit.
|Memory, memory controller, memory system, method of memory, memory controller and memory system|
In one embodiment, the method includes performing a read operation on a memory, and determining, by a memory controller, whether to perform a reliability verification read operation based on a count value and a reference value. The count value is based on a number of read commands issued by the memory controller to the memory, and the reliability verification read operation is for reading data from at least one memory cell associated with at least one unselected word line in the memory.
|Memory devices and formation methods|
A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types.
|Memory module and memory system comprising same|
A memory module comprises a plurality of semiconductor memory devices each comprising a mode register set (mrs) circuit configured to generate an enable signal corresponding to an error mode of the semiconductor memory device in response to an mrs command received from a command decoder, and an address buffer configured to store a predetermined address signal, to receive an address signal and corresponding data from an external device, and to compare the address signal received with the predetermined address signal in response to the enable signal. As a consequence of determining that the address signal received from the external device is the same as the predetermined address signal stored in the address buffer, data different from the corresponding data received from the external device is written to a memory cell corresponding to the predetermined address signal..
|Write driver for write assistance in memory device|
A write assist driver circuit is provided that assists a memory cell (e.g., volatile memory bit cell) in write operations to keep the voltage at the memory core sufficiently high for correct write operations, even when the supply voltage is lowered. The write assist driver circuit may be configured to provide a memory supply voltage vddm to a bit cell core during a standby mode of operation.
|Methods for programming a memory device and memory devices|
Methods for programming memory cells and memory devices are disclosed. One such method for programming includes performing a program verify operation of a group of memory cells.
|Smart bridge for memory core|
An apparatus includes a first semiconductor device including a three-dimensional (3d) memory. The 3d memory includes multiple memory cells arranged in multiple physical levels above a substrate.
|Programming method for nonvolatile semiconductor memory device|
A method for programming a plurality of memory cells of a nonvolatile semiconductor memory device comprises the steps of: dividing the plurality of memory cells into m number of groups (m is an integer); successively selecting each of the m number of groups; generating m number of successive overlapping pulse signals; and programming the memory cells of the m number of groups in response to the respective m number of successive overlapping pulse signals.. .
|Programming select gate transistors and memory cells using dynamic verify level|
Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage which increases from an initial level to a final level during a programming operation. Faster-programming transistors are locked out from programming before slower-programming transistors, but experience program disturb which increases their threshold voltage to a common level with the slower-programming transistors at the conclusion of the programming operation.
|Method and apparatus for leakage suppression in flash memory in response to external commands|
Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells.
|Program and read methods of memory devices using bit line sharing|
A program method of a nonvolatile memory device includes loading first word line data to be stored in first memory cells connected to a first word line and second word line data to be stored in second memory cells connected to a second word line; setting up upper bit lines according to the first word line data; turning off bit line sharing transistors after the upper bit lines are set up; setting up lower bit lines according to the second word line data; performing a first program operation on the first memory cells using the upper bit lines; turning on the bit line sharing transistors; and performing a second program operation on the second memory cells using the lower bit lines. The bit line sharing transistors electrically connect the upper bit lines and the lower bit lines in response to a bit line sharing signal..
|Nonvolatile semiconductor memory device|
Word lines extend in a first direction and are commonly connected to memory cells in a plurality of nand cell units. Bit lines extend in a second direction crossing to the first direction and connected to one ends of the nand cell units.
|Smart bridge for memory core|
An apparatus includes a semiconductor device that includes a multi-ported three-dimensional (3d) memory. The multi-ported 3d memory includes multiple memory cells arranged in multiple physical levels above a substrate.
|Memory system comprising nonvolatile memory device and program method thereof|
A memory system includes a nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device such that memory cells connected with a selected row of the nonvolatile memory device are programmed by one of a first program mode and a second program mode. At the first program mode, a plurality of logical pages corresponding in number to a maximum page number is stored at the memory cells, and at the second program mode, one or more logical pages the number of which is less than the maximum page number are stored at the memory cells using a bias condition that is different from that used in the first program mode..
|Non-volatile memory device|
A non-volatile memory device comprising a memory cell array including memory cells distributed among a plurality of sectors; a controller operable to program, read, and erase memory cells in said memory array, said controller further operable to generate and store epli values for programming a number of epli bits in one of said plurality of sectors with said stored epli values; and a comparator to compare said stored epli values with epli values programmed in said epli bits.. .
|Capacitor-less memory cell, device, system and method of making same|
A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell include forming the capacitor-less memory cell in an active area of a substantially physically isolated portion of a bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line.
|System and method of programming a memory cell|
A method includes selectively creating a first breakdown condition and a second breakdown condition at a semiconductor transistor structure. The first breakdown condition is between a source overlap region of the semiconductor transistor structure and a gate of the semiconductor transistor structure.
|System and method of programming a memory cell|
A method includes creating a breakdown condition at a semiconductor transistor structure that includes an overlap region and a channel region. The breakdown condition is created by causing a first voltage difference between a gate of the semiconductor transistor structure and the overlap region to exceed a breakdown voltage of the semiconductor transistor structure while maintaining a second voltage difference between the gate and the channel region at less than the breakdown voltage..
|Nonvolatile memory device and writing method thereof|
A writing method of a nonvolatile memory device is provided which receiving data, a target time, and a target resistance value; writing the data at a memory cell; calculating a resistance drift coefficient based on resistance values of the memory cell read on at least two times; calculating a resistance value of the memory cell on the target time using the resistance drift coefficient; and determining whether the resistance value calculated satisfies the target resistance value.. .
|Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features|
A sectioned bit line of an sram memory device, an sram memory device having a sectioned bit line, and associated systems and methods are described, including embodiments having sectioned bit lines with hierarchical aspects. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line.
|Semiconductor memory device with hierarchical bitlines|
A dynamic random access memory (dram) device has a hierarchical bitline structure with local bitlines and global bitlines formed on different metal layers. The local bitlines are separated into a plurality of local bitline sections, and bitline isolation switches are configured to connect or disconnect the local bitline sections to or from the global bitlines.
|Access signal adjustment circuits and methods for memory cells in a cross-point array|
Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed beol directly on top of a feol substrate that includes data access circuitry. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements disposed among word lines and subsets of bit lines, and an access signal generator.
|Nonvolatile semiconductor memory device|
A length of a wiring line between the set operation-dedicated first driver circuit and the memory cell array is longer compared to a length of a wiring line between the reset operation-dedicated first driver circuit and the memory cell array.. .
|Temperature based logic profile for variable resistance memory cells|
A data storage device may generally be constructed and operated with at least one variable resistance memory cell having a first logic state threshold that is replaced with a second logic state threshold by a controller. The first and second logic states respectively corresponding to a predicted resistance shift that is based upon an operating temperature profile..
|Method and apparatus for adaptive timing write control in a memory|
A bit line, which is coupled to a resistive element of a memory cell is set to a first voltage level. The memory cell may be an mram cell or an rram cell.
|Applying a bias signal to memory cells to reverse a resistance shift of the memory cells|
Data is written to cells of a resistance-based, non-volatile memory. An activity metric is tracked since the writing of the data to the cells.