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Logical Address patents



      
           
This page is updated frequently with new Logical Address-related patent applications. Subscribe to the Logical Address RSS feed to automatically get the update: related Logical RSS feeds. RSS updates for this page: Logical Address RSS RSS


Memory system and method for controlling a nonvolatile semiconductor memory

Logical address offset

Date/App# patent app List of recent Logical Address-related patents
08/14/14
20140229790
 Using ecc data for write deduplication processing patent thumbnailUsing ecc data for write deduplication processing
Method and apparatus for managing data in a memory. In accordance with some embodiments, a first data object and an associated first ecc data set are generated and stored in a non-volatile (nv) main memory responsive to a first set of data blocks having a selected logical address.
08/14/14
20140229662
 Memory system and method for controlling a nonvolatile semiconductor memory patent thumbnailMemory system and method for controlling a nonvolatile semiconductor memory
A memory system includes a nonvolatile semiconductor memory having blocks, the block being data erasing unit; and a controller configured to execute; an update processing for; writing superseding data in a block, the superseding data being treated as valid data; and invalidating superseded data having the same logical address as the superseding data, the superseded data being treated as invalid data; and a compaction processing for; retrieving blocks having invalid data using a management table, the management table managing blocks in a linked list format for each number of valid data included in the block; selecting a compaction source block having at least one valid data from the retrieved blocks; copying a plurality of valid data included in the compaction source blocks into a compaction target block; invalidating the plurality of valid data in the compaction source blocks; and releasing the compaction source blocks in which all data are invalidated.. .
08/14/14
20140229660
 Logical address offset patent thumbnailLogical address offset
The present disclosure includes methods, devices, and systems for a logical address offset. One method embodiment includes detecting a memory unit formatting operation.
08/14/14
20140229546
  patent thumbnail
The present invention relates to a main electronic device for communicating within a network comprising an interface for enabling communication within the network and a controller for sending polling messages via the network to logical addresses via said interface in order to request information from at least one further electronic device. The present invention further relates to a method for operating a main electronic device for communicating within a network..
08/14/14
20140226413
 Non-volatile buffering to enable sloppy writes and fast write verification patent thumbnailNon-volatile buffering to enable sloppy writes and fast write verification
Method and apparatus for managing data in a memory. In accordance with some embodiments, input write data having a selected logical address are stored in a rewriteable non-volatile (nv) buffer.
08/07/14
20140223089
 Method and device for storing data in a flash memory using address mapping for supporting various block sizes patent thumbnailMethod and device for storing data in a flash memory using address mapping for supporting various block sizes
The present invention relates to a method and device for storing data in a flash memory using address mapping for supporting various block sizes. A storage device determines the size of a block that a host system uses on the basis of the size of data that the host system requests and uses the determined block size as a mapping unit.
08/07/14
20140223083
 Zone-based defragmentation methods and user devices using the same patent thumbnailZone-based defragmentation methods and user devices using the same
A defragmentation method of a user device which includes a host and a nonvolatile storage device includes: determining whether fragments of a first file stored at the nonvolatile storage device are in a same logical address zone; and executing defragmentation on the fragments of the first file if the fragments of the first file are in different logical address zones by moving the fragments of the first file to a logical address space corresponding to at least one of the different logical address zones.. .
08/07/14
20140223079
 Non-volatile memory apparatus and operating method thereof patent thumbnailNon-volatile memory apparatus and operating method thereof
A non-volatile memory (nvm) apparatus and an operation method thereof are provided. A mapping table in a main memory is divided into a plurality of sub-mapping tables according to logical address groups.
08/07/14
20140223075
 Physical-to-logical address map to speed up a recycle operation in a solid state drive patent thumbnailPhysical-to-logical address map to speed up a recycle operation in a solid state drive
A method for increasing performance of a recycle operation in a solid state drive, comprising the steps of (a) creating an empty physical-to-logical address map in a memory having a plurality of entry locations, (b) filling one of the plurality of entry locations with a physical page address associated with each data write operation to a block, where the block has a plurality of pages, (c) writing the physical-to-logical address map to a last of the plurality of pages during a write to a second to last page of the block and (d) initiating a recycle operation of the block by reading the address map to determine whether the pages contain valid data.. .
08/07/14
20140219034
 Non-volatile write buffer data retention pending scheduled verification patent thumbnailNon-volatile write buffer data retention pending scheduled verification
Method and apparatus for managing data in a memory. In accordance with some embodiments, a non-volatile (nv) buffer is adapted to store input write data having a selected logical address.
07/31/14
20140215132
Data writing method, memory controller and memory storage device
A data writing method, a memory controller, and a memory storage device are provided. The method is applied to control a rewritable non-volatile memory module that includes two memory units.
07/24/14
20140208059
Highly configurable memory architecture for partitioned global address space memory systems
A system and method for identifying from an address an appropriate target node and a location in that node that holds desired data related to that address is provided. The system and method includes a logical address generator that generates a logical address.
07/24/14
20140207998
System and method of wear leveling for a non-volatile memory
In an architecture of wear leveling for a non-volatile memory composed of plural storage units, a translation layer is configured to translate a logical address provided by a host to a physical address of the non-volatile memory. A cold-block table is configured to assign a cold block or blocks in at least one storage unit, the cold block in a given storage unit having an erase count being less than erase counts of non-cold blocks in the given storage unit.
07/17/14
20140201437
Modifying logical addressing at a requestor level
Method and apparatus for managing data in a memory. In accordance with some embodiments, a control circuit monitors access operations upon a set of data blocks in a memory of a data storage device.
07/10/14
20140195761
Logical volume space sharing
Space sharing between logical volumes is achieved through a technique that enables available storage space to be flexibly consumed and released by the logical volumes. Each logical volume is associated with an address tree that defines how available storage space is consumed by the logical volume.
07/03/14
20140189286
Wear leveling with marching strategy
A method for managing utilization of a memory including a physical address space comprises mapping logical addresses of data objects to locations within the physical address space, and defining a plurality of address segments in the space as an active window. The method comprises allowing writes of data objects having logical addresses mapped to locations within the plurality of address segments in the active window.
07/03/14
20140189275
Providing versioning in a storage device
Provided are a computer program product, system and method for managing input/output (i/o) requests to a storage device. A write request is received having write data for a logical address, wherein data for the logical address is at a first physical location in the storage device and has an indicated version number.
07/03/14
20140189264
Reads and writes between a contiguous data block and noncontiguous sets of logical address blocks in a persistent storage device
In the present disclosure, a persistent storage device includes both persistent storage, which includes a set of persistent storage blocks, and a storage controller. The persistent storage device stores and retrieves data in response to commands received from an external host device.
07/03/14
20140189217
Semiconductor storage device
According to an embodiment, a semiconductor storage device includes a first storage unit, a read control unit, a second storage unit, and a write control unit. The first storage unit is configured to store data supplied from a host device.
07/03/14
20140189210
Memory system having an unequal number of memory die
A flash memory system having unequal number of memory die and method for operation is disclosed. The memory includes a plurality of flash memory die distributed unevenly among different control lines, such that there are an unequal number of die between control lines.
07/03/14
20140189203
Storage apparatus and storage control method
A cache memory (cm) in which data, which is accessed with respect to a storage device, is temporarily stored is coupled to a controller for accessing the storage device in accordance with an access command from a higher-level apparatus. The cm comprises a nonvolatile semi-conductor memory (nvm), and provides a logical space to the controller.
07/03/14
20140189078
Locating and addressing communication devices
A system is provided that includes first- and second-network subsystems. The first-network subsystem includes a first-network device with knowledge of its physical location and assigned logical address within the first-network subsystem.
06/26/14
20140181375
Memory controller
According to one embodiment, a memory controller includes a first interface, a second interface, a cache unit, a translation unit, an access unit and a lock unit. The first interface receives a lock request and an access request which includes a logical address.
06/26/14
20140181372
Data reading method, memory controller, and memory storage device
A data reading method, a memory controller, and a memory storage device are provided. The data reading method is adapted to a rewritable non-volatile memory module having a plurality of physical erasing units.
06/26/14
20140177085
Disk storage apparatus and method for shingled magnetic recording
According to one embodiment, a disk storage apparatus includes a storage device, a writing controller, and a controller. The storage device includes a nonvolatile cache area in which a part of consecutive data is temporarily stored.
06/19/14
20140173234
Semiconductor memory device and memory system
A semiconductor memory system or device includes a memory cell array and an address converter. The memory cell array includes a plurality of memory blocks, and there is at least one block that serves as a buffer.
06/19/14
20140173191
Semiconductor memory system having a snapshot function
In a semiconductor memory computer equipped with a flash memory, use of backed-up data is enabled. The semiconductor memory computer includes an address conversion table for detecting physical addresses of at least two pages storing data by designating a logical address from one of logical addresses to be designated by a reading request.
06/19/14
20140173178
Joint logical and physical address remapping in non-volatile memory
A method includes, for data items that are to be stored in a non-volatile memory in accordance with respective logical addresses, associating the logical addresses with respective physical storage locations in the non-volatile memory, and storing the data items in the respective associated physical storage locations. A remapping command, which specifies a group of source logical addresses that are associated with respective source physical storage locations, is received.
06/12/14
20140164730
System and methods for managing storage space allocation
A request for obtaining a space allocation descriptor is received by a block control layer of a storage system. The space allocation descriptor is indicative of one or more logical blocks free for allocation within a range of logical addresses.
06/12/14
20140164677
Using a logical to physical map for direct user space communication with a data storage device
A data storage device includes multiple flash memory devices, where each of the flash memory devices is arranged into multiple blocks having multiple pages for storing data. The data storage device includes a memory controller operationally coupled with the flash memory devices.
06/05/14
20140156967
Hinting of deleted data from host to storage device
A storage device includes a memory and a processor. The processor is configured to store data items for a host in respective logical addresses, to identify a first subset of the logical addresses as frequently-accessed logical addresses and a second subset of the logical addresses as rarely-accessed logical addresses, to manage the frequently-accessed logical addresses separately from the rarely-accessed logical addresses, to receive from the host an indication of one or more logical addresses, which are used for storing data that is identified by the host as having been deleted by a user, and to add the logical addresses indicated by the host to the rarely-accessed logical addresses..
05/29/14
20140149670
Storage system and method of operating thereof
There is provided a storage system capable to maintain a snapshot family comprising a plurality of members having hierarchical relations therebetween, and a method of operating thereof. The method comprises generating a mapping data structure with mapping entries each comprising mappings for mapping a logical address range associated with the mapping entry into physical address ranges respectively correlated to representative members of the snapshot family; omitting mappings corresponding to omitted member(s) different from any of the one or more representative members sharing a respective range of physical addresses; responsive to an access request directed to a certain logical address range and a certain omitted member, determining, using a predefined rule related to the hierarchical and sequential relations between members of the snapshot family, a representative member from the one or more representative members; and responding to the access request by using a physical address range correlated to the representative member..
05/29/14
20140149640
Adaptive power control of memory map storage devices
An apparatus includes a storage resource to store data. The data can be accessible by a host computer system.
05/22/14
20140143483
Memory management schemes for non-volatile memory devices
A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory.
05/22/14
20140143482
Memory management schemes for non-volatile memory devices
A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory.
05/15/14
20140136769
Solid-state storage management
Solid-state storage management for a system, the management including establishing, externally to a solid-state storage board, a correspondence between a first logical address and a first physical address on solid-state storage devices located on the solid-state storage board. The solid-state storage devices include a plurality of physical memory locations identified by physical addresses.
05/01/14
20140122671
Method for assigning logical addresses to the connection ports of devices of a server cluster, and corresponding computer program and server cluster
A method and system for assigning logical addresses to connection ports of devices of a server cluster. The method includes defining a logical addressing policy in respect of said connection ports of devices of the cluster; based on a logical distribution of the devices of the cluster in the data transmission network, a geographic distribution, and a hardware definition of the devices of the cluster, initialising a server cluster administration database; according to the logical addressing policy, assigning logical addresses to the connection ports of devices of the server cluster; and saving the logical addresses assigned in the server cluster administration database.
04/24/14
20140115423
Non-volatile memory error correction
Improving the performance, life and amount of data storage in write limited non-volatile memory may be achieved by: a) utilizing a serial content-addressable memory (cam) to perform logical address translation, b) a minimum cam function to perform erase error count wear leveling, c) increasingly refining a two dimensional error-correction coding (ecc) method as needed to correct for degrading storage, and/or d) serially generating ecc and using an ecc serial decoder to correct the data.. .
04/24/14
20140115422
Non-volatile memory error correction
Improving the performance, life and amount of data storage in write limited non-volatile memory may be achieved by: a) utilizing a serial content-addressable memory (cam) to perform logical address translation, b) a minimum cam function to perform erase error count wear leveling, c) increasingly refining a two dimensional error-correction coding (ecc) method as needed to correct for degrading storage, and/or d) serially generating ecc and using an ecc serial decoder to correct the data.. .
04/24/14
20140115416
Non-volatile memory error correction
Improving the performance, life and amount of data storage in write limited non-volatile memory may be achieved by: a) utilizing a serial content-addressable memory (cam) to perform logical address translation, b) a minimum cam function to perform erase error count wear leveling, c) increasingly refining a two dimensional error-correction coding (ecc) method as needed to correct for degrading storage, and/or d) serially generating ecc and using an ecc serial decoder to correct the data.. .
04/24/14
20140115296
Remapping memory cells based on future endurance measurements
A method of operating a memory device that includes groups of memory cells is presented. The groups include a first group of memory cells.
04/24/14
20140115252
Block storage-based data processing methods, apparatus, and systems
The present disclosure relates to the field of information technology, and in particular, to a block storage-based data processing method, apparatus, and system. The block storage-based data processing method provided in embodiments of the present disclosure is applied in a system including at least two storage nodes, each storage node including a cpu, a cache medium, and a non-volatile storage medium, and the cache medium in all the storage nodes forming a cache pool.
04/17/14
20140108757
Processing a copy command directed to a first storage architecture for data that is stored in a second storage architecture
Provided are a computer program product, system, and method for processing a copy command indicating a source set comprising a subset of source logical addresses to copy to an indicated target set comprising a subset of target logical addresses. Complete is expected to be returned to the copy command in response to completing the copying of the source set to the target set.
04/17/14
20140108752
Managing updates and copying data in a point-in-time copy relationship expressed as source logical addresses and target logical addresses
Provided are a computer program product, system, and method for managing updates and copying data in a point-in-time copy relationship expressed as source logical addresses and target logical addresses. A copy relationship indicates a source set of a subset of source logical addresses to copy to a target set comprising a subset of target logical addresses.
04/17/14
20140108751
Processing a copy command directed to a first storage architecture for data that is stored in a second storage architecture
Provided are a computer program product, system, and method for processing a copy command indicating a source set comprising a subset of source logical addresses to copy to an indicated target set comprising a subset of target logical addresses. Complete is expected to be returned to the copy command in response to completing the copying of the source set to the target set.
04/17/14
20140108750
Establishing a point-in-time copy relationship between source logical addresses and target logical addresses
Provided are a computer program product, system, and method for establishing a point-in-time copy relationship between source logical addresses and target logical addresses. A point-in-time (pit) copy establish command specifies a source set comprising a subset of source logical addresses in at least one storage and a target set comprising a subset of target logical addresses in the at least one storage.
04/17/14
20140108705
Use of high endurance non-volatile memory for read acceleration
A high endurance, short retention nand memory is used as a read cache for a memory of a higher level of non-volatility, such as standard nand flash memory or a hard drive. The combined memory system identifies frequently read logical addresses of the main non-volatile memory or specific read sequences and stores the corresponding data in cache nand to accelerate host reads.
04/17/14
20140108680
Quiescing input/output (i/o) requests to subsets of logical addresses in a storage for a requested operation
Provided are a computer program product, system, and method for quiescing input/output (i/o) requests to subsets of logical addresses in a storage for a requested operation. A requested operation is received to a subset of addresses in the storage that requires that input/output (i/o) requests to the subset of addresses received following the requested operation be quiesced.
04/10/14
20140101378
Metadata rebuild in a flash memory controller following a loss of power
A method of rebuilding metadata in a flash memory controller following a loss of power is provided. The method includes reading logical address information associated with an area of flash memory, and using time stamp information to determine if data stored in the flash memory area are valid..
04/10/14
20140101375
Apparatus, system, and method for allocating storage
An apparatus, system, and method are disclosed for allocating non-volatile storage. The storage device may present a logical address, which may exceed a physical storage capacity of the device.
03/20/14
20140082323
Address mapping
The present disclosure includes methods, memory units, and apparatuses for address mapping. One method includes providing a mapping unit having logical to physical mapping data corresponding to a number of logical addresses.
03/20/14
20140082265
Data storage device and flash memory control method thereof
A mapping table h2f update technique for a flash memory is disclosed. In a disclosed data storage device, the controller updates a logical-to-physical address mapping table between a host and the flash memory in accordance with a group count of a buffer block of the flash memory.
03/20/14
20140082263
Memory system
According to one embodiment, a memory system includes a plurality of nonvolatile memories, an address converter, a plurality of channel controllers, and a controller. The plurality of nonvolatile memories is connected to respective channels.
03/20/14
20140082252
Combined two-level cache directory
Responsive to receiving a logical address for a cache access, a mechanism looks up a first portion of the logical address in a local cache directory for a local cache. The local cache directory returns a set identifier for each set in the local cache directory.
03/20/14
20140079065
Lan emulation over infiniband fabric apparatus, systems, and methods
A method and device for local area network (lan) emulation over an infiniband (ib) fabric. An ib lan driver at a first node on an ib fabric receives the port and associated local identifier (lid) of one or more remote peer nodes on the ib fabric.
03/13/14
20140075096
Storage device and method for controlling the same
A storage device according to an embodiment includes: a host interface connected to a host; a memory including a first buffer that stores a logical address range designated by an invalidation instruction received from the host via the host interface and a second buffer that stores an internal logical address range which is an area combination with the logical address range; a nonvolatile memory; and a controller. The controller includes: an invalidation instruction processor that stores the logical address range designated by the invalidation instruction in the first buffer; an area combination executor that generates the internal logical address range by the area combination with the logical address range and stores the internal logical address range in the second buffer; and an invalidation executor that executes invalidation processing on the nonvolatile memory based on the internal logical address range..
03/06/14
20140068211
Converting a first address mapping function for mapping addresses to storage locations to a second address mapping function
Provided are a computer program product, system, and method for converting a first address mapping function for mapping addresses to storage locations to a second address mapping function. For each of a plurality of addresses allocated in the storage using the first address mapping function, a node is generated in the second address mapping function.
03/06/14
20140068182
Storage virtualization in a block-level storage system
A data storage system that stores data has a logical address space divided into ordered areas and unordered areas. Retrieval of storage system metadata for a logical address is based on whether the address is located in an ordered area or an unordered area.
03/06/14
20140068158
Flash storage device and control method for flash memory
A flash memory is used in data storage and is further stored with a logical-to-physical address mapping table and a write protection mapping table. The write protection mapping table shows the write protection statuses of the different logical addresses.
03/06/14
20140068152
Method and system for storage address re-mapping for a multi-bank memory device
A method and system for storage address re-mapping in a multi-bank memory is disclosed. The method includes allocating logical addresses in blocks of clusters and re-mapping logical addresses into storage address space, where short runs of host data dispersed in logical address space are mapped in a contiguous manner into megablocks in storage address space.
02/27/14
20140059619
Video and digital multimedia aggregator content coding and formatting
A video and digital multimedia aggregator includes a content decoder, coder (codec) and formatter. The codec formatter receives coding and formatting requests that characterize input source content and desired output target content.
02/27/14
20140059273
Host apparatus and memory device
According to one embodiment, a host apparatus is capable of accessing memory device. The host apparatus includes application software, a dedicated file system, and an interface circuit.
02/27/14
20140059018
Data de-duplication in a distributed network
A computer-implemented method for efficient data storage is provided. A first storage medium associates data stored on one or more data storage media with a unique identification value (id) for the purpose of determining de-duplication status of the data.
02/20/14
20140052904
Systems and methods for recovering addressing data
A memory includes first memory configured to store first data indicating relationships between logical addresses and respective physical addresses, wherein the physical addresses are arranged in a plurality of different groups, respective statuses of each of the plurality of different groups, and an activity log indicating when any of the respective statuses has changed. A second memory is configured to store second data in memory locations corresponding to the physical addresses and, in response to a respective status of one of the plurality of groups changing, store a portion of the first data corresponding to the one of the plurality of groups.
02/20/14
20140052893
File deletion for non-volatile memory
A device includes non-volatile memory and a controller. The controller receives a write request including data and a logical address associated with a file.
02/20/14
20140050121
Double-ring network system, method for determining transmission priority in double-ring network and transmission station device
According to one embodiment, in a double-ring network, a master station includes a transmitting and receiving permission switch portion, a communication port a at an a-system side, a communication port b at a b-system side, a first receiving control circuit portion, a transmitting and receiving control circuit portion, a frame detection determining circuit portion, a frame data generating circuit portion, a logical address determining circuit portion, a live list setting circuit portion and an address list setting circuit portion. The master station determines a token order (a transmission priority, also called a logical address) using a shortest path function by the logical address determining circuit portion and the address list setting circuit portion such that the token order does not depend on physical addresses of transmission stations and is matched to a connection order of transmission stations to realize path optimization.
02/13/14
20140047210
Trim mechanism using multi-level mapping in a solid-state media
Described embodiments provide a media controller that receives requests that include a logical address and address range. In response to the request, the media controller determines whether the received request is an invalidating request.
02/13/14
20140047170
Maintaining ordering via a multi-level map of a solid-state media
Described embodiments provide a media controller that processes requests including a logical address and address range. A map of the media controller determines physical addresses of a media associated with the logical address and address range of the request.
02/06/14
20140040533
Data management method, memory controller and memory storage device
A data management method for a rewritable non-volatile memory module including a first memory unit and a second memory unit is provided. The method includes: grouping erasing units of the first memory unit into a data area and a spare area; and grouping the physical erasing units of the second memory unit into a data backup area and a command recording area; configuring multiple logical addresses to map to the physical erasing units associated with the data area; receiving a write command which instructs writing data; writing the data to a physical erasing unit associated with the spare area, and writing the data to a physical erasing unit associated with the data backup area; recording at least a portion of the write command in a physical erasing unit associated with the command recording area.
01/23/14
20140025921
Memory control method utilizing main memory for address mapping and related memory control circuit
A memory control method, including: writing a write-in data which has a logical address into a write-in cache buffer; generating a write-in address mapping table which maps the logical address of the data to a physical address of a main memory, and writing the write-in address mapping table into a cached data mapping table write buffer; writing the write-in data into the main memory according to the write-in address mapping table; and when an available storage space of the cached data mapping table write buffer is reduced to reach a predetermined threshold, writing the address mapping table in the cached data mapping table write buffer into the main memory, and storing a corresponding main memory write-in address mapping table into a global mapping table buffer.. .
01/23/14
20140025872
Systems and methods for contextual storage
A storage layer presents logical address space of a non-volatile storage device. The storage layer maintains logical interfaces to the non-volatile storage device, which may include arbitrary, any-to-any mappings between logical identifiers and storage resources.


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Logical Address topics: Logical Address, Address Space, Storage Device, Volatile Memory, Control Unit, Memory Device, Data Storage, Interleave, Distributed, Redundancy, Physical Map, Backing Store, Forward Index, Data Structure, Contiguous

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