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Date/App# patent app List of recent Logical Address-related patents
04/17/14
20140108757
 Processing a copy command directed to a first storage architecture for data that is stored in a second storage architecture patent thumbnailnew patent Processing a copy command directed to a first storage architecture for data that is stored in a second storage architecture
Provided are a computer program product, system, and method for processing a copy command indicating a source set comprising a subset of source logical addresses to copy to an indicated target set comprising a subset of target logical addresses. Complete is expected to be returned to the copy command in response to completing the copying of the source set to the target set.
04/17/14
20140108752
 Managing updates and copying data in a point-in-time copy relationship expressed as source logical addresses and target logical addresses patent thumbnailnew patent Managing updates and copying data in a point-in-time copy relationship expressed as source logical addresses and target logical addresses
Provided are a computer program product, system, and method for managing updates and copying data in a point-in-time copy relationship expressed as source logical addresses and target logical addresses. A copy relationship indicates a source set of a subset of source logical addresses to copy to a target set comprising a subset of target logical addresses.
04/17/14
20140108751
 Processing a copy command directed to a first storage architecture for data that is stored in a second storage architecture patent thumbnailnew patent Processing a copy command directed to a first storage architecture for data that is stored in a second storage architecture
Provided are a computer program product, system, and method for processing a copy command indicating a source set comprising a subset of source logical addresses to copy to an indicated target set comprising a subset of target logical addresses. Complete is expected to be returned to the copy command in response to completing the copying of the source set to the target set.
04/17/14
20140108750
 Establishing a point-in-time copy relationship between source logical addresses and target logical addresses patent thumbnailnew patent Establishing a point-in-time copy relationship between source logical addresses and target logical addresses
Provided are a computer program product, system, and method for establishing a point-in-time copy relationship between source logical addresses and target logical addresses. A point-in-time (pit) copy establish command specifies a source set comprising a subset of source logical addresses in at least one storage and a target set comprising a subset of target logical addresses in the at least one storage.
04/17/14
20140108705
 Use of high endurance non-volatile memory for read acceleration patent thumbnailnew patent Use of high endurance non-volatile memory for read acceleration
A high endurance, short retention nand memory is used as a read cache for a memory of a higher level of non-volatility, such as standard nand flash memory or a hard drive. The combined memory system identifies frequently read logical addresses of the main non-volatile memory or specific read sequences and stores the corresponding data in cache nand to accelerate host reads.
04/17/14
20140108680
 Quiescing input/output (i/o) requests to subsets of logical addresses in a storage for a requested operation patent thumbnailnew patent Quiescing input/output (i/o) requests to subsets of logical addresses in a storage for a requested operation
Provided are a computer program product, system, and method for quiescing input/output (i/o) requests to subsets of logical addresses in a storage for a requested operation. A requested operation is received to a subset of addresses in the storage that requires that input/output (i/o) requests to the subset of addresses received following the requested operation be quiesced.
04/10/14
20140101378
 Metadata rebuild in a flash memory controller following a loss of power patent thumbnailMetadata rebuild in a flash memory controller following a loss of power
A method of rebuilding metadata in a flash memory controller following a loss of power is provided. The method includes reading logical address information associated with an area of flash memory, and using time stamp information to determine if data stored in the flash memory area are valid..
04/10/14
20140101375
 Apparatus, system, and method for allocating storage patent thumbnailApparatus, system, and method for allocating storage
An apparatus, system, and method are disclosed for allocating non-volatile storage. The storage device may present a logical address, which may exceed a physical storage capacity of the device.
03/20/14
20140082323
 Address mapping patent thumbnailAddress mapping
The present disclosure includes methods, memory units, and apparatuses for address mapping. One method includes providing a mapping unit having logical to physical mapping data corresponding to a number of logical addresses.
03/20/14
20140082265
 Data storage device and flash memory control method thereof patent thumbnailData storage device and flash memory control method thereof
A mapping table h2f update technique for a flash memory is disclosed. In a disclosed data storage device, the controller updates a logical-to-physical address mapping table between a host and the flash memory in accordance with a group count of a buffer block of the flash memory.
03/20/14
20140082263
Memory system
According to one embodiment, a memory system includes a plurality of nonvolatile memories, an address converter, a plurality of channel controllers, and a controller. The plurality of nonvolatile memories is connected to respective channels.
03/20/14
20140082252
Combined two-level cache directory
Responsive to receiving a logical address for a cache access, a mechanism looks up a first portion of the logical address in a local cache directory for a local cache. The local cache directory returns a set identifier for each set in the local cache directory.
03/20/14
20140079065
Lan emulation over infiniband fabric apparatus, systems, and methods
A method and device for local area network (lan) emulation over an infiniband (ib) fabric. An ib lan driver at a first node on an ib fabric receives the port and associated local identifier (lid) of one or more remote peer nodes on the ib fabric.
03/13/14
20140075096
Storage device and method for controlling the same
A storage device according to an embodiment includes: a host interface connected to a host; a memory including a first buffer that stores a logical address range designated by an invalidation instruction received from the host via the host interface and a second buffer that stores an internal logical address range which is an area combination with the logical address range; a nonvolatile memory; and a controller. The controller includes: an invalidation instruction processor that stores the logical address range designated by the invalidation instruction in the first buffer; an area combination executor that generates the internal logical address range by the area combination with the logical address range and stores the internal logical address range in the second buffer; and an invalidation executor that executes invalidation processing on the nonvolatile memory based on the internal logical address range..
03/06/14
20140068211
Converting a first address mapping function for mapping addresses to storage locations to a second address mapping function
Provided are a computer program product, system, and method for converting a first address mapping function for mapping addresses to storage locations to a second address mapping function. For each of a plurality of addresses allocated in the storage using the first address mapping function, a node is generated in the second address mapping function.
03/06/14
20140068182
Storage virtualization in a block-level storage system
A data storage system that stores data has a logical address space divided into ordered areas and unordered areas. Retrieval of storage system metadata for a logical address is based on whether the address is located in an ordered area or an unordered area.
03/06/14
20140068158
Flash storage device and control method for flash memory
A flash memory is used in data storage and is further stored with a logical-to-physical address mapping table and a write protection mapping table. The write protection mapping table shows the write protection statuses of the different logical addresses.
03/06/14
20140068152
Method and system for storage address re-mapping for a multi-bank memory device
A method and system for storage address re-mapping in a multi-bank memory is disclosed. The method includes allocating logical addresses in blocks of clusters and re-mapping logical addresses into storage address space, where short runs of host data dispersed in logical address space are mapped in a contiguous manner into megablocks in storage address space.
02/27/14
20140059619
Video and digital multimedia aggregator content coding and formatting
A video and digital multimedia aggregator includes a content decoder, coder (codec) and formatter. The codec formatter receives coding and formatting requests that characterize input source content and desired output target content.
02/27/14
20140059273
Host apparatus and memory device
According to one embodiment, a host apparatus is capable of accessing memory device. The host apparatus includes application software, a dedicated file system, and an interface circuit.
02/27/14
20140059018
Data de-duplication in a distributed network
A computer-implemented method for efficient data storage is provided. A first storage medium associates data stored on one or more data storage media with a unique identification value (id) for the purpose of determining de-duplication status of the data.
02/20/14
20140052904
Systems and methods for recovering addressing data
A memory includes first memory configured to store first data indicating relationships between logical addresses and respective physical addresses, wherein the physical addresses are arranged in a plurality of different groups, respective statuses of each of the plurality of different groups, and an activity log indicating when any of the respective statuses has changed. A second memory is configured to store second data in memory locations corresponding to the physical addresses and, in response to a respective status of one of the plurality of groups changing, store a portion of the first data corresponding to the one of the plurality of groups.
02/20/14
20140052893
File deletion for non-volatile memory
A device includes non-volatile memory and a controller. The controller receives a write request including data and a logical address associated with a file.
02/20/14
20140050121
Double-ring network system, method for determining transmission priority in double-ring network and transmission station device
According to one embodiment, in a double-ring network, a master station includes a transmitting and receiving permission switch portion, a communication port a at an a-system side, a communication port b at a b-system side, a first receiving control circuit portion, a transmitting and receiving control circuit portion, a frame detection determining circuit portion, a frame data generating circuit portion, a logical address determining circuit portion, a live list setting circuit portion and an address list setting circuit portion. The master station determines a token order (a transmission priority, also called a logical address) using a shortest path function by the logical address determining circuit portion and the address list setting circuit portion such that the token order does not depend on physical addresses of transmission stations and is matched to a connection order of transmission stations to realize path optimization.
02/13/14
20140047210
Trim mechanism using multi-level mapping in a solid-state media
Described embodiments provide a media controller that receives requests that include a logical address and address range. In response to the request, the media controller determines whether the received request is an invalidating request.
02/13/14
20140047170
Maintaining ordering via a multi-level map of a solid-state media
Described embodiments provide a media controller that processes requests including a logical address and address range. A map of the media controller determines physical addresses of a media associated with the logical address and address range of the request.
02/06/14
20140040533
Data management method, memory controller and memory storage device
A data management method for a rewritable non-volatile memory module including a first memory unit and a second memory unit is provided. The method includes: grouping erasing units of the first memory unit into a data area and a spare area; and grouping the physical erasing units of the second memory unit into a data backup area and a command recording area; configuring multiple logical addresses to map to the physical erasing units associated with the data area; receiving a write command which instructs writing data; writing the data to a physical erasing unit associated with the spare area, and writing the data to a physical erasing unit associated with the data backup area; recording at least a portion of the write command in a physical erasing unit associated with the command recording area.
01/23/14
20140025921
Memory control method utilizing main memory for address mapping and related memory control circuit
A memory control method, including: writing a write-in data which has a logical address into a write-in cache buffer; generating a write-in address mapping table which maps the logical address of the data to a physical address of a main memory, and writing the write-in address mapping table into a cached data mapping table write buffer; writing the write-in data into the main memory according to the write-in address mapping table; and when an available storage space of the cached data mapping table write buffer is reduced to reach a predetermined threshold, writing the address mapping table in the cached data mapping table write buffer into the main memory, and storing a corresponding main memory write-in address mapping table into a global mapping table buffer.. .
01/23/14
20140025872
Systems and methods for contextual storage
A storage layer presents logical address space of a non-volatile storage device. The storage layer maintains logical interfaces to the non-volatile storage device, which may include arbitrary, any-to-any mappings between logical identifiers and storage resources.
01/16/14
20140019670
Data writing method, memory controller, and memory storage device
A data writing method for controlling a rewritable non-volatile memory module having physical erasing units is provided. The physical erasing units are grouped into a first buffer area and a second buffer area.
01/16/14
20140019579
Transferring data of a dispersed storage network
A method begins by a dispersed storage (ds) processing detecting unavailability of a storage device of a site of dispersed storage network (dsn) memory to produce an unavailable storage device. The method continues with the ds processing module reassigning a fraction of a logical address sub-range of the unavailable storage device to one or more other storage devices, rebuilding one or more logically addressable data objects to produce one or more rebuilt data objects and storing the one or more rebuilt data objects in the one or more other storage devices.
01/09/14
20140013043
Memory system
A memory system according to an embodiment of the present invention comprises: speed of processing for searching through management tables is increased by providing a forward lookup table for searching for, respectively in track and cluster units, from a logical address, a storage device position where data corresponding to the logical address and a reverse lookup table for searching for, from a position of the storage device, a logical address stored in the position and linking these tables.. .
01/02/14
20140006851
Semiconductor memory controlling device
According to one embodiment, a semiconductor memory controlling device includes a write control unit that writes a predetermined number of pieces of first data and redundant information calculated by using the predetermined number of pieces of the first data and used for correcting an error in the first data into different semiconductor storage drives, respectively; a constructing unit that constructs a storage area for storing therein a table by using driver information, the table showing an association between a logical address and a physical address of the first data and identification information for associating the predetermined number of pieces of first data with the redundant information; and a table controlling unit that stores, into the storage area, the table associated with the identification information, the physical address and the logical address of the predetermined number of pieces of the first data, and a physical address of the redundant information.. .
01/02/14
20140006689
Non-volatile memory device, control method for information processing device, and information processing device
A storage device for a host device includes a non-volatile semiconductor memory and a control section configured to execute a delete process in response to a command from the host device to delete data stored at locations in the non-volatile semiconductor memory corresponding to a selected logical address included in the command. The delete process includes determining a selected mapping and at least one prior mapping of the selected logical address to physical addresses of the non-volatile semiconductor memory, and erasing or overwriting the data stored at the physical addresses..
01/02/14
20140002701
Pixel and method for feedback based resetting of a pixel
A storage system, a non-transitory computer readable medium and a method for pre-fetching. The method may include presenting, by a storage system and to at least one host computer, a logical address space; determining, by a fetch module, to fetch a certain data portion from a data storage device to a cache memory of the storage system; determining, by a pre-fetch module, whether to pre-fetch at least one additional data portion from at least one data storage device to the cache memory based upon at least one characteristic of a mapping tree that maps one or more contiguous ranges of addresses related to the logical address space and one or more contiguous ranges of addresses related to the physical address space; and pre-fetching the at least one additional data portions if it is determined to pre-fetch the at least one additional data portions..
12/26/13
20130346675
Data storing method, and memory controller and memory storage apparatus using the same
A data storing method for a rewritable non-volatile memory module is provided. The method includes dividing logical addresses into a plurality of logical zones, and respectively establishing a plurality of logical address mapping tables for the logical zones.
12/26/13
20130346674
Data writing method, memory controller and memory storage device
A data writing method for controlling a rewritable non-volatile memory module having a plurality of physical erase units is provided. The method includes: receiving a write command which instructs writing data to a first logical address, wherein the first logical address is mapped to a second physical erase unit; determining whether the second physical erase unit is in a sequential writing state which represents that the physical programming units over a predetermined ratio in the second physical erasing unit have been successively written sequentially within a predetermined time; if yes, writing the data into a third physical erasing unit in a first programming mode, wherein the first programming mode represents that a plurality of upper physical programming units are non-programmable.
12/26/13
20130346673
Method for improving flash memory storage device access
A method for improving flash memory storage device access is disclosed. The steps of the method comprises requesting to read/write data of logical address by a host; setting up an engine by a cpu; looking up physical address and updating at least one table stored in at least one flash memory by the engine; and reading/writing data from/to the at least one flash memory.
12/19/13
20130339667
Special case register update without execution
A method of changing a value of associated with a logical address in a computing device. The method includes: receiving an instruction at an instruction decoder, the instruction including a target register expressed as a logical value; determining at an instruction decoder that a result of the instruction is to set the target register to a constant value, the target register being in a physical register file associated with an execution unit; and mapping, in a register mapper, the logical address to a location represented by a special register tag..
12/19/13
20130339666
Special case register update without execution
A method of changing a value of associated with a logical address in a computing device. The method includes: receiving an instruction at an instruction decoder, the instruction including a target register expressed as a logical value; determining at an instruction decoder that a result of the instruction is to set the target register to a constant value, the target register being in a physical register file associated with an execution unit; and mapping, in a register mapper, the logical address to a location represented by a special register tag..
12/19/13
20130339628
Determining the logical address of a transaction abort
Embodiments relate to determining the logical address of a transaction abort. In an embodiment, one or more instructions are received are received from an application.
12/12/13
20130332700
Cloud storage arrangement and method of operating thereof
There is provided a storage arrangement and a method of operating thereof. The storage arrangement comprises a first storage system and one or more second storage systems operatively coupled to the first storage system.
12/12/13
20130329508
Methods and devices for determining logical to physical mapping on an integrated circuit
Methods and devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment of the method includes fabricating a die, where the die has a plurality of bits that are electrically accessible by way of logical addresses.
12/05/13
20130326030
Discovery of electronic devices in a combined network
Embodiments of the invention are generally directed to discovery of electronic devices in a combined network. An embodiment of a method includes determining an identifier for a first device in a combined network according to a first network protocol, the combined network including a first network using the first network protocol and a second network using a second network protocol, where the identifier is determined based on a unique designation for the first device, and determining addressing information for the first device according to the second network protocol, where determining the addressing information includes establishing a physical address and a logical address for the first device.
11/28/13
20130318316
Storage device and method for controlling storage device
A storage device includes a memory and a control device. The control device allocates a first storage region out of a plurality of storage regions to a first logical address specified by an external device.
11/21/13
20130311750
Transaction log recovery
The present disclosure includes methods for transaction log recovery in memory. One such method includes examining a number of entries saved in a transaction log to determine a write pattern, reading the memory based on the write pattern, updating the transaction log with information associated with data read from the memory based on the write pattern, and updating a logical address (la) table using the transaction log..
11/21/13
20130311747
Memory mapping and translation for arbitrary number of memory units
A method for address translation in a memory comprising a plurality of memory streaming units (msus), wherein n represents the number of msus and n is not a power of two, and wherein the memory further comprises a striped region, the method comprising determining an msu from among the plurality of msus having a physical address (pa) in the striped region corresponding to a logical address (la) comprising performing a modulo n operation on less than all the bits representing the la; and transmitting the la to the msu.. .
11/21/13
20130311746
Shared memory access using independent memory maps
A method includes defining a first mapping, which translates between logical addresses and physical storage locations in a memory with a first mapping unit size, for accessing the memory by a first processing unit. A second mapping is defined, which translates between the logical addresses and the physical storage locations with a second mapping unit size that is different from the first mapping unit size, for accessing the memory by a second processing unit.
11/21/13
20130311712
Control apparatus, storage device, and storage control method
A control apparatus includes a control unit configured to perform control in such a manner that in a case where data is to be written into a physical area, which is the unit in which an erasing operation is performed, subjected to processing in a first non-volatile memory in response to a write request and in a case where the end of the data does not match a boundary between physical regions, which are the smallest units in which a writing operation is performed, in the first non-volatile memory, first data having a size smaller than the smallest units is stored in a predetermined temporary storage area, and thereafter in a case where second data specified by the same logical address as the first data is requested to be written, the first data and the second data are combined and written into the physical area subjected to processing.. .
11/21/13
20130311711
Nonvolatile memory device and program method thereof
Disclosed is a nonvolatile memory device which includes a nonvolatile memory having multi-level cell (mlc) storage; and a controller configured to control the nonvolatile memory, wherein if a logical address of write-requested data coincides with a logical address of data stored in the nonvolatile memory, the controller controls the nonvolatile memory to program the write-requested data prior to programming of a page sharing the same word line as a page including the data stored in the nonvolatile memory.. .
11/21/13
20130311707
Storage control apparatus and storage control method
A storage control apparatus comprises a storage unit, an association unit, and an execution unit. The storage unit stores association information showing multiple physical chunks which are configured in a physical address space of a nonvolatile semiconductor memory, multiple logical storage areas which are configured in a logical address space of the nonvolatile semiconductor memory, multiple logical chunks which are respectively associated with the multiple physical chunks, and an association between a logical storage area and a logical chunk.
11/14/13
20130304998
Write command overlap detection
The present disclosure includes methods and apparatuses that include write command overlap detection. A number of embodiments include receiving an incoming write command and comparing a logical address of the incoming write command to logical addresses of a number of write commands in a queue using a tree data structure, wherein a starting logical address and/or an ending logical address of the incoming write command and a starting logical address and/or an ending logical address of each of the number of write commands are associated with nodes in the tree data structure..
11/14/13
20130304975
Apparatuses for managing and accessing flash memory module
A method for maintaining address mapping for a flash memory module is disclosed including: recording a first set of addresses corresponding to a first set of sequential logical addresses in a first section of a first addressing block; recording a second set of addresses corresponding to a second set of sequential logical addresses in a second section of the first addressing block; recording a third set of addresses corresponding to a third set of sequential logical addresses in a first section of a second addressing block; and recording a fourth set of addresses corresponding to a fourth set of sequential logical addresses in a second section of the second addressing block; wherein the second set of logical addresses is successive to the first set of logical addresses, and the third set of logical addresses is successive to the second set of logical addresses.. .
11/14/13
20130304973
Control device, storage device, and storage control method
A control device includes a control unit that performs control of writing of data with respect to a memory unit, in which a size of a physical block that is a deletion unit is larger than a size of a physical page that is a minimum writing unit, and generates logical and physical address management information that indicates a correspondence relation between a physical page address and a logical address in a writing target physical block, in which data is written through the control of writing, so as to perform control so that the logical and physical address management information is written in the writing target physical block.. .
11/14/13
20130304972
Control device, storage device, and storage control method
A control device includes a control unit that performs control of writing of data with respect to a first non-volatile memory, in which a size of a physical block that is a deletion unit is larger than a size of a physical page that is a minimum writing unit, and generates logical and physical address management information that indicates a correspondence relation between a physical page address and a logical address in a writing target physical block, in which data is written through the control of writing, so as to perform control so that the logical and physical address management information is stored in a second non-volatile memory every time data is written in the first non-volatile memory.. .
11/07/13
20130297880
Non-volatile cache
Apparatuses, systems, and methods are disclosed for caching data. A method includes directly mapping a logical address of a backing store to a logical address of a non-volatile cache.
11/07/13
20130294162
Column redundancy circuitry for non-volatile memory
In a non-volatile memory circuit, techniques are presented so that bad columns can be ignored and/or replaced during memory data input and output operations. A column redundant circuit for this purpose reduces circuit size and improves performance.
10/24/13
20130282953
Systems and methods for referencing data on a storage medium
A storage layer is configured to store data at respective offsets within storage units of a storage device. Physical addresses of the data may be segmented into a first portion identifying the storage unit in which the data is stored, and a second portion that indicates the offset of the data within the identified storage unit.
10/17/13
20130275716
Program execution device and compiler system
A program execution device includes a program loader reading a machine language program including a machine language code and access frequency information; an address conversion table creator creating an address conversion table including entries, each of which indicates a relation between a logical address range and a physical address range; and a tlb register registering, in a tlb, an entry of the address conversion table storing a logical address range accessed according to the machine language code. When determining that the frequency of access to a logical address range is high based on the access frequency information, the address conversion table creator adjusts the size of an entry storing this logical address range to an appropriate size..
10/17/13
20130275657
Data storage device and operating method thereof
An operating method of a data storage device including a plurality of nonvolatile memory devices includes the steps of: mapping physical addresses of the nonvolatile memory devices into logical addresses; reflecting environmental factors to remap a physical address into a logical address requested to be accessed; and performing an interleaving operation for the nonvolatile memory devices using the remapped physical address.. .
10/17/13
20130275656
Apparatus, system, and method for key-value pool identifier encoding
Apparatuses, systems, and methods are disclosed for a key-value store. A method includes encoding a key of a key-value pair into a logical address of a sparse logical address space for a non-volatile medium.
10/17/13
20130275447
Method of migrating stored data and system thereof
There is provided a storage system and a method of moving a source data portion from a source logical volume to a destination logical volume. The method comprises: configuring a source mapping data structure to comprise an entry indicative of mapping between logical addresses corresponding to source data portion and addresses corresponding to source data portion and related to a physical address space; and, responsive to a move command, providing an atomic operation comprising configuring a destination mapping data structure to comprise an entry associated with said at least one destination range and comprising a reference to said entry in the source mapping data structure; and configuring said at least one entry in the source mapping data structure dssrc to bear an indication that said one or more contiguous ranges of addresses corresponding to said source data portion in the source logical volume vsrc are unavailable to a client..
10/03/13
20130262739
Memory module virtualization
A memory system having a plurality of modules operated so that a group of memory modules may operation in a raid configuration having an erase hiding property. The raid groups are mapped to areas of memory in each of the memory modules of the raid group.
10/03/13
20130258829
Recording apparatus, and recording method
Provided is a recording apparatus including a light radiating unit that radiates light to an optical recording medium, a recording unit that performs light emission control of the light radiating unit, and performs recording on the optical recording medium, and a control unit that controls the recording unit in a manner that recording of remaining data starts from a position over a defect occurrence area, according to occurrence of a defect, in a state in which a logical address space and a physical address space are defined with respect to a recording area of the optical recording medium, and controls the recording unit in a manner that, when the buffer area is consumed and data is not completely recorded, a recording area of the remaining data that is not completely recorded is replaced with the spare area and the remaining data is recorded on the spare area.. .
10/03/13
20130258828
Recording apparatus, recording method, reproducing apparatus, and reproducing method
There is provided a recording apparatus including a light radiating unit that radiates light to an optical recording medium, a recording unit that performs light emission control of the light radiating unit, and performs recording on the optical recording medium, and a control unit that performs control in a manner that, in a state in which a logical address space, a virtual address space obtained by adding at least a spare area to the logical address space, and a physical address space obtained by adding a buffer area to the virtual address space are defined, a process for replacing a recording area of the optical recording medium with the spare area is executed using a virtual address.. .
09/26/13
20130254514
Wear-leveling method, storage device, and information system
Embodiments of the present invention provide a wear-leveling method, a storage device, and an information system, where a storage region is divided into a plurality of storage sub-regions of the same size. The method includes: recording the accumulated number of write operations of each storage sub-region; and when the accumulated number of write operations of any one storage sub-region of the plurality of storage sub-regions reaches a predetermined remapping rate, mapping a logical address of the storage sub-region to a remapping physical address.
09/26/13
20130254471
Device and memory system for memory management using access frequency information
An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.. .
09/26/13
20130250710
Non-volatile memory device, circuit board, printing material container and printer
A non-volatile memory device includes first and second memory regions to store data and a memory control unit. Each of the first and second memory regions is configured by a plurality of physical pages.
09/19/13
20130246721
Controller, data storage device, and computer program product
According to an embodiment, a controller includes a write control unit configured to make a control that converts data requested to be written by an external device into pieces of cluster data with a size of a cluster of a storage medium, compresses each piece of cluster data, determines a corresponding physical address of a write destination in the storage medium according to a predetermined rule, and writes the compressed pieces of cluster data to the storage medium using the physical address of the write destination. The write control unit also makes a control that writes a correspondence between the physical address and a corresponding logical address to a storage unit.
09/19/13
20130243004
Communication control method, relay device, and information processing device
A communication control method of a communication system including a first communication device, a first relay device coupled to the first communication device via a first network which is a network domain where a message broadcast from the first communication device reaches and where communication based on physical addresses is performed, and a second communication device belonging to the same logical network to which the first communication device belongs, the communication control method including: broadcasting, by the first communication device, a first request including a logical address assigned to the second communication device and requesting a physical address assigned to the second communication device, transmitting, by the first relay device, in the event that the second communication device is not coupled to the first network, a first response which is a response to the first request and includes a predetermined physical address, to the first communication device.. .
09/12/13
20130238870
Disposition instructions for extended access commands
A computer system that generates a disposition instruction and an associated access command directed to a block of data at a logical address is described. The disposition instruction and the access command are communicated to a memory system in the computer system via a communication link.
09/12/13
20130238869
Enhanced copy-on-write operation for solid state drives
A method for increasing the efficiency of a “copy-on-write” operation performed on an ssd to extend the life of the ssd is disclosed herein. In one embodiment, such a method includes receiving a first logical address specifying a logical location where new data should be written to an ssd.
09/12/13
20130238855
Management of cache memory in a storage system
According to the teaching disclosed herein there is provided at least a method, system and device for managing a cache memory of a storage system. The storage system is associated with at least one physical storage device and, responsive to a read request, comprising information indicative of a logical address of at least one requested data unit, to obtain a storage physical address associated with the logical address, search the cache memory for a data unit associated with the storage physical address and service the request from the cache in case the data unit to is found in the cache memory..


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Logical Address topics: Logical Address, Address Space, Storage Device, Volatile Memory, Control Unit, Memory Device, Data Storage, Interleave, Distributed, Redundancy, Physical Map, Backing Store, Forward Index, Data Structure, Contiguous

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