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Logical Address patents



      
           
This page is updated frequently with new Logical Address-related patent applications. Subscribe to the Logical Address RSS feed to automatically get the update: related Logical RSS feeds. RSS updates for this page: Logical Address RSS RSS


Logical volume space sharing

Wear leveling with marching strategy

Providing versioning in a storage device

Date/App# patent app List of recent Logical Address-related patents
07/17/14
20140201437
 Modifying logical addressing at a requestor level patent thumbnailnew patent Modifying logical addressing at a requestor level
Method and apparatus for managing data in a memory. In accordance with some embodiments, a control circuit monitors access operations upon a set of data blocks in a memory of a data storage device.
07/10/14
20140195761
 Logical volume space sharing patent thumbnailLogical volume space sharing
Space sharing between logical volumes is achieved through a technique that enables available storage space to be flexibly consumed and released by the logical volumes. Each logical volume is associated with an address tree that defines how available storage space is consumed by the logical volume.
07/03/14
20140189286
 Wear leveling with marching strategy patent thumbnailWear leveling with marching strategy
A method for managing utilization of a memory including a physical address space comprises mapping logical addresses of data objects to locations within the physical address space, and defining a plurality of address segments in the space as an active window. The method comprises allowing writes of data objects having logical addresses mapped to locations within the plurality of address segments in the active window.
07/03/14
20140189275
 Providing versioning in a storage device patent thumbnailProviding versioning in a storage device
Provided are a computer program product, system and method for managing input/output (i/o) requests to a storage device. A write request is received having write data for a logical address, wherein data for the logical address is at a first physical location in the storage device and has an indicated version number.
07/03/14
20140189264
 Reads and writes between a contiguous data block and noncontiguous sets of logical address blocks in a persistent storage device patent thumbnailReads and writes between a contiguous data block and noncontiguous sets of logical address blocks in a persistent storage device
In the present disclosure, a persistent storage device includes both persistent storage, which includes a set of persistent storage blocks, and a storage controller. The persistent storage device stores and retrieves data in response to commands received from an external host device.
07/03/14
20140189217
 Semiconductor storage device patent thumbnailSemiconductor storage device
According to an embodiment, a semiconductor storage device includes a first storage unit, a read control unit, a second storage unit, and a write control unit. The first storage unit is configured to store data supplied from a host device.
07/03/14
20140189210
 Memory system having an unequal number of memory die patent thumbnailMemory system having an unequal number of memory die
A flash memory system having unequal number of memory die and method for operation is disclosed. The memory includes a plurality of flash memory die distributed unevenly among different control lines, such that there are an unequal number of die between control lines.
07/03/14
20140189203
 Storage apparatus and storage control method patent thumbnailStorage apparatus and storage control method
A cache memory (cm) in which data, which is accessed with respect to a storage device, is temporarily stored is coupled to a controller for accessing the storage device in accordance with an access command from a higher-level apparatus. The cm comprises a nonvolatile semi-conductor memory (nvm), and provides a logical space to the controller.
07/03/14
20140189078
 Locating and addressing communication devices patent thumbnailLocating and addressing communication devices
A system is provided that includes first- and second-network subsystems. The first-network subsystem includes a first-network device with knowledge of its physical location and assigned logical address within the first-network subsystem.
06/26/14
20140181375
 Memory controller patent thumbnailMemory controller
According to one embodiment, a memory controller includes a first interface, a second interface, a cache unit, a translation unit, an access unit and a lock unit. The first interface receives a lock request and an access request which includes a logical address.
06/26/14
20140181372
Data reading method, memory controller, and memory storage device
A data reading method, a memory controller, and a memory storage device are provided. The data reading method is adapted to a rewritable non-volatile memory module having a plurality of physical erasing units.
06/26/14
20140177085
Disk storage apparatus and method for shingled magnetic recording
According to one embodiment, a disk storage apparatus includes a storage device, a writing controller, and a controller. The storage device includes a nonvolatile cache area in which a part of consecutive data is temporarily stored.
06/19/14
20140173234
Semiconductor memory device and memory system
A semiconductor memory system or device includes a memory cell array and an address converter. The memory cell array includes a plurality of memory blocks, and there is at least one block that serves as a buffer.
06/19/14
20140173191
Semiconductor memory system having a snapshot function
In a semiconductor memory computer equipped with a flash memory, use of backed-up data is enabled. The semiconductor memory computer includes an address conversion table for detecting physical addresses of at least two pages storing data by designating a logical address from one of logical addresses to be designated by a reading request.
06/19/14
20140173178
Joint logical and physical address remapping in non-volatile memory
A method includes, for data items that are to be stored in a non-volatile memory in accordance with respective logical addresses, associating the logical addresses with respective physical storage locations in the non-volatile memory, and storing the data items in the respective associated physical storage locations. A remapping command, which specifies a group of source logical addresses that are associated with respective source physical storage locations, is received.
06/12/14
20140164730
System and methods for managing storage space allocation
A request for obtaining a space allocation descriptor is received by a block control layer of a storage system. The space allocation descriptor is indicative of one or more logical blocks free for allocation within a range of logical addresses.
06/12/14
20140164677
Using a logical to physical map for direct user space communication with a data storage device
A data storage device includes multiple flash memory devices, where each of the flash memory devices is arranged into multiple blocks having multiple pages for storing data. The data storage device includes a memory controller operationally coupled with the flash memory devices.
06/05/14
20140156967
Hinting of deleted data from host to storage device
A storage device includes a memory and a processor. The processor is configured to store data items for a host in respective logical addresses, to identify a first subset of the logical addresses as frequently-accessed logical addresses and a second subset of the logical addresses as rarely-accessed logical addresses, to manage the frequently-accessed logical addresses separately from the rarely-accessed logical addresses, to receive from the host an indication of one or more logical addresses, which are used for storing data that is identified by the host as having been deleted by a user, and to add the logical addresses indicated by the host to the rarely-accessed logical addresses..
05/29/14
20140149670
Storage system and method of operating thereof
There is provided a storage system capable to maintain a snapshot family comprising a plurality of members having hierarchical relations therebetween, and a method of operating thereof. The method comprises generating a mapping data structure with mapping entries each comprising mappings for mapping a logical address range associated with the mapping entry into physical address ranges respectively correlated to representative members of the snapshot family; omitting mappings corresponding to omitted member(s) different from any of the one or more representative members sharing a respective range of physical addresses; responsive to an access request directed to a certain logical address range and a certain omitted member, determining, using a predefined rule related to the hierarchical and sequential relations between members of the snapshot family, a representative member from the one or more representative members; and responding to the access request by using a physical address range correlated to the representative member..
05/29/14
20140149640
Adaptive power control of memory map storage devices
An apparatus includes a storage resource to store data. The data can be accessible by a host computer system.
05/22/14
20140143483
Memory management schemes for non-volatile memory devices
A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory.
05/22/14
20140143482
Memory management schemes for non-volatile memory devices
A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory.
05/15/14
20140136769
Solid-state storage management
Solid-state storage management for a system, the management including establishing, externally to a solid-state storage board, a correspondence between a first logical address and a first physical address on solid-state storage devices located on the solid-state storage board. The solid-state storage devices include a plurality of physical memory locations identified by physical addresses.
05/01/14
20140122671
Method for assigning logical addresses to the connection ports of devices of a server cluster, and corresponding computer program and server cluster
A method and system for assigning logical addresses to connection ports of devices of a server cluster. The method includes defining a logical addressing policy in respect of said connection ports of devices of the cluster; based on a logical distribution of the devices of the cluster in the data transmission network, a geographic distribution, and a hardware definition of the devices of the cluster, initialising a server cluster administration database; according to the logical addressing policy, assigning logical addresses to the connection ports of devices of the server cluster; and saving the logical addresses assigned in the server cluster administration database.
04/24/14
20140115423
Non-volatile memory error correction
Improving the performance, life and amount of data storage in write limited non-volatile memory may be achieved by: a) utilizing a serial content-addressable memory (cam) to perform logical address translation, b) a minimum cam function to perform erase error count wear leveling, c) increasingly refining a two dimensional error-correction coding (ecc) method as needed to correct for degrading storage, and/or d) serially generating ecc and using an ecc serial decoder to correct the data.. .
04/24/14
20140115422
Non-volatile memory error correction
Improving the performance, life and amount of data storage in write limited non-volatile memory may be achieved by: a) utilizing a serial content-addressable memory (cam) to perform logical address translation, b) a minimum cam function to perform erase error count wear leveling, c) increasingly refining a two dimensional error-correction coding (ecc) method as needed to correct for degrading storage, and/or d) serially generating ecc and using an ecc serial decoder to correct the data.. .
04/24/14
20140115416
Non-volatile memory error correction
Improving the performance, life and amount of data storage in write limited non-volatile memory may be achieved by: a) utilizing a serial content-addressable memory (cam) to perform logical address translation, b) a minimum cam function to perform erase error count wear leveling, c) increasingly refining a two dimensional error-correction coding (ecc) method as needed to correct for degrading storage, and/or d) serially generating ecc and using an ecc serial decoder to correct the data.. .
04/24/14
20140115296
Remapping memory cells based on future endurance measurements
A method of operating a memory device that includes groups of memory cells is presented. The groups include a first group of memory cells.
04/24/14
20140115252
Block storage-based data processing methods, apparatus, and systems
The present disclosure relates to the field of information technology, and in particular, to a block storage-based data processing method, apparatus, and system. The block storage-based data processing method provided in embodiments of the present disclosure is applied in a system including at least two storage nodes, each storage node including a cpu, a cache medium, and a non-volatile storage medium, and the cache medium in all the storage nodes forming a cache pool.
04/17/14
20140108757
Processing a copy command directed to a first storage architecture for data that is stored in a second storage architecture
Provided are a computer program product, system, and method for processing a copy command indicating a source set comprising a subset of source logical addresses to copy to an indicated target set comprising a subset of target logical addresses. Complete is expected to be returned to the copy command in response to completing the copying of the source set to the target set.
04/17/14
20140108752
Managing updates and copying data in a point-in-time copy relationship expressed as source logical addresses and target logical addresses
Provided are a computer program product, system, and method for managing updates and copying data in a point-in-time copy relationship expressed as source logical addresses and target logical addresses. A copy relationship indicates a source set of a subset of source logical addresses to copy to a target set comprising a subset of target logical addresses.
04/17/14
20140108751
Processing a copy command directed to a first storage architecture for data that is stored in a second storage architecture
Provided are a computer program product, system, and method for processing a copy command indicating a source set comprising a subset of source logical addresses to copy to an indicated target set comprising a subset of target logical addresses. Complete is expected to be returned to the copy command in response to completing the copying of the source set to the target set.
04/17/14
20140108750
Establishing a point-in-time copy relationship between source logical addresses and target logical addresses
Provided are a computer program product, system, and method for establishing a point-in-time copy relationship between source logical addresses and target logical addresses. A point-in-time (pit) copy establish command specifies a source set comprising a subset of source logical addresses in at least one storage and a target set comprising a subset of target logical addresses in the at least one storage.
04/17/14
20140108705
Use of high endurance non-volatile memory for read acceleration
A high endurance, short retention nand memory is used as a read cache for a memory of a higher level of non-volatility, such as standard nand flash memory or a hard drive. The combined memory system identifies frequently read logical addresses of the main non-volatile memory or specific read sequences and stores the corresponding data in cache nand to accelerate host reads.
04/17/14
20140108680
Quiescing input/output (i/o) requests to subsets of logical addresses in a storage for a requested operation
Provided are a computer program product, system, and method for quiescing input/output (i/o) requests to subsets of logical addresses in a storage for a requested operation. A requested operation is received to a subset of addresses in the storage that requires that input/output (i/o) requests to the subset of addresses received following the requested operation be quiesced.
04/10/14
20140101378
Metadata rebuild in a flash memory controller following a loss of power
A method of rebuilding metadata in a flash memory controller following a loss of power is provided. The method includes reading logical address information associated with an area of flash memory, and using time stamp information to determine if data stored in the flash memory area are valid..
04/10/14
20140101375
Apparatus, system, and method for allocating storage
An apparatus, system, and method are disclosed for allocating non-volatile storage. The storage device may present a logical address, which may exceed a physical storage capacity of the device.
03/20/14
20140082323
Address mapping
The present disclosure includes methods, memory units, and apparatuses for address mapping. One method includes providing a mapping unit having logical to physical mapping data corresponding to a number of logical addresses.
03/20/14
20140082265
Data storage device and flash memory control method thereof
A mapping table h2f update technique for a flash memory is disclosed. In a disclosed data storage device, the controller updates a logical-to-physical address mapping table between a host and the flash memory in accordance with a group count of a buffer block of the flash memory.
03/20/14
20140082263
Memory system
According to one embodiment, a memory system includes a plurality of nonvolatile memories, an address converter, a plurality of channel controllers, and a controller. The plurality of nonvolatile memories is connected to respective channels.
03/20/14
20140082252
Combined two-level cache directory
Responsive to receiving a logical address for a cache access, a mechanism looks up a first portion of the logical address in a local cache directory for a local cache. The local cache directory returns a set identifier for each set in the local cache directory.
03/20/14
20140079065
Lan emulation over infiniband fabric apparatus, systems, and methods
A method and device for local area network (lan) emulation over an infiniband (ib) fabric. An ib lan driver at a first node on an ib fabric receives the port and associated local identifier (lid) of one or more remote peer nodes on the ib fabric.
03/13/14
20140075096
Storage device and method for controlling the same
A storage device according to an embodiment includes: a host interface connected to a host; a memory including a first buffer that stores a logical address range designated by an invalidation instruction received from the host via the host interface and a second buffer that stores an internal logical address range which is an area combination with the logical address range; a nonvolatile memory; and a controller. The controller includes: an invalidation instruction processor that stores the logical address range designated by the invalidation instruction in the first buffer; an area combination executor that generates the internal logical address range by the area combination with the logical address range and stores the internal logical address range in the second buffer; and an invalidation executor that executes invalidation processing on the nonvolatile memory based on the internal logical address range..
03/06/14
20140068211
Converting a first address mapping function for mapping addresses to storage locations to a second address mapping function
Provided are a computer program product, system, and method for converting a first address mapping function for mapping addresses to storage locations to a second address mapping function. For each of a plurality of addresses allocated in the storage using the first address mapping function, a node is generated in the second address mapping function.
03/06/14
20140068182
Storage virtualization in a block-level storage system
A data storage system that stores data has a logical address space divided into ordered areas and unordered areas. Retrieval of storage system metadata for a logical address is based on whether the address is located in an ordered area or an unordered area.
03/06/14
20140068158
Flash storage device and control method for flash memory
A flash memory is used in data storage and is further stored with a logical-to-physical address mapping table and a write protection mapping table. The write protection mapping table shows the write protection statuses of the different logical addresses.
03/06/14
20140068152
Method and system for storage address re-mapping for a multi-bank memory device
A method and system for storage address re-mapping in a multi-bank memory is disclosed. The method includes allocating logical addresses in blocks of clusters and re-mapping logical addresses into storage address space, where short runs of host data dispersed in logical address space are mapped in a contiguous manner into megablocks in storage address space.
02/27/14
20140059619
Video and digital multimedia aggregator content coding and formatting
A video and digital multimedia aggregator includes a content decoder, coder (codec) and formatter. The codec formatter receives coding and formatting requests that characterize input source content and desired output target content.
02/27/14
20140059273
Host apparatus and memory device
According to one embodiment, a host apparatus is capable of accessing memory device. The host apparatus includes application software, a dedicated file system, and an interface circuit.
02/27/14
20140059018
Data de-duplication in a distributed network
A computer-implemented method for efficient data storage is provided. A first storage medium associates data stored on one or more data storage media with a unique identification value (id) for the purpose of determining de-duplication status of the data.
02/20/14
20140052904
Systems and methods for recovering addressing data
A memory includes first memory configured to store first data indicating relationships between logical addresses and respective physical addresses, wherein the physical addresses are arranged in a plurality of different groups, respective statuses of each of the plurality of different groups, and an activity log indicating when any of the respective statuses has changed. A second memory is configured to store second data in memory locations corresponding to the physical addresses and, in response to a respective status of one of the plurality of groups changing, store a portion of the first data corresponding to the one of the plurality of groups.
02/20/14
20140052893
File deletion for non-volatile memory
A device includes non-volatile memory and a controller. The controller receives a write request including data and a logical address associated with a file.
02/20/14
20140050121
Double-ring network system, method for determining transmission priority in double-ring network and transmission station device
According to one embodiment, in a double-ring network, a master station includes a transmitting and receiving permission switch portion, a communication port a at an a-system side, a communication port b at a b-system side, a first receiving control circuit portion, a transmitting and receiving control circuit portion, a frame detection determining circuit portion, a frame data generating circuit portion, a logical address determining circuit portion, a live list setting circuit portion and an address list setting circuit portion. The master station determines a token order (a transmission priority, also called a logical address) using a shortest path function by the logical address determining circuit portion and the address list setting circuit portion such that the token order does not depend on physical addresses of transmission stations and is matched to a connection order of transmission stations to realize path optimization.
02/13/14
20140047210
Trim mechanism using multi-level mapping in a solid-state media
Described embodiments provide a media controller that receives requests that include a logical address and address range. In response to the request, the media controller determines whether the received request is an invalidating request.
02/13/14
20140047170
Maintaining ordering via a multi-level map of a solid-state media
Described embodiments provide a media controller that processes requests including a logical address and address range. A map of the media controller determines physical addresses of a media associated with the logical address and address range of the request.
02/06/14
20140040533
Data management method, memory controller and memory storage device
A data management method for a rewritable non-volatile memory module including a first memory unit and a second memory unit is provided. The method includes: grouping erasing units of the first memory unit into a data area and a spare area; and grouping the physical erasing units of the second memory unit into a data backup area and a command recording area; configuring multiple logical addresses to map to the physical erasing units associated with the data area; receiving a write command which instructs writing data; writing the data to a physical erasing unit associated with the spare area, and writing the data to a physical erasing unit associated with the data backup area; recording at least a portion of the write command in a physical erasing unit associated with the command recording area.
01/23/14
20140025921
Memory control method utilizing main memory for address mapping and related memory control circuit
A memory control method, including: writing a write-in data which has a logical address into a write-in cache buffer; generating a write-in address mapping table which maps the logical address of the data to a physical address of a main memory, and writing the write-in address mapping table into a cached data mapping table write buffer; writing the write-in data into the main memory according to the write-in address mapping table; and when an available storage space of the cached data mapping table write buffer is reduced to reach a predetermined threshold, writing the address mapping table in the cached data mapping table write buffer into the main memory, and storing a corresponding main memory write-in address mapping table into a global mapping table buffer.. .
01/23/14
20140025872
Systems and methods for contextual storage
A storage layer presents logical address space of a non-volatile storage device. The storage layer maintains logical interfaces to the non-volatile storage device, which may include arbitrary, any-to-any mappings between logical identifiers and storage resources.
01/16/14
20140019670
Data writing method, memory controller, and memory storage device
A data writing method for controlling a rewritable non-volatile memory module having physical erasing units is provided. The physical erasing units are grouped into a first buffer area and a second buffer area.
01/16/14
20140019579
Transferring data of a dispersed storage network
A method begins by a dispersed storage (ds) processing detecting unavailability of a storage device of a site of dispersed storage network (dsn) memory to produce an unavailable storage device. The method continues with the ds processing module reassigning a fraction of a logical address sub-range of the unavailable storage device to one or more other storage devices, rebuilding one or more logically addressable data objects to produce one or more rebuilt data objects and storing the one or more rebuilt data objects in the one or more other storage devices.
01/09/14
20140013043
Memory system
A memory system according to an embodiment of the present invention comprises: speed of processing for searching through management tables is increased by providing a forward lookup table for searching for, respectively in track and cluster units, from a logical address, a storage device position where data corresponding to the logical address and a reverse lookup table for searching for, from a position of the storage device, a logical address stored in the position and linking these tables.. .
01/02/14
20140006851
Semiconductor memory controlling device
According to one embodiment, a semiconductor memory controlling device includes a write control unit that writes a predetermined number of pieces of first data and redundant information calculated by using the predetermined number of pieces of the first data and used for correcting an error in the first data into different semiconductor storage drives, respectively; a constructing unit that constructs a storage area for storing therein a table by using driver information, the table showing an association between a logical address and a physical address of the first data and identification information for associating the predetermined number of pieces of first data with the redundant information; and a table controlling unit that stores, into the storage area, the table associated with the identification information, the physical address and the logical address of the predetermined number of pieces of the first data, and a physical address of the redundant information.. .
01/02/14
20140006689
Non-volatile memory device, control method for information processing device, and information processing device
A storage device for a host device includes a non-volatile semiconductor memory and a control section configured to execute a delete process in response to a command from the host device to delete data stored at locations in the non-volatile semiconductor memory corresponding to a selected logical address included in the command. The delete process includes determining a selected mapping and at least one prior mapping of the selected logical address to physical addresses of the non-volatile semiconductor memory, and erasing or overwriting the data stored at the physical addresses..
01/02/14
20140002701
Pixel and method for feedback based resetting of a pixel
A storage system, a non-transitory computer readable medium and a method for pre-fetching. The method may include presenting, by a storage system and to at least one host computer, a logical address space; determining, by a fetch module, to fetch a certain data portion from a data storage device to a cache memory of the storage system; determining, by a pre-fetch module, whether to pre-fetch at least one additional data portion from at least one data storage device to the cache memory based upon at least one characteristic of a mapping tree that maps one or more contiguous ranges of addresses related to the logical address space and one or more contiguous ranges of addresses related to the physical address space; and pre-fetching the at least one additional data portions if it is determined to pre-fetch the at least one additional data portions..
12/26/13
20130346675
Data storing method, and memory controller and memory storage apparatus using the same
A data storing method for a rewritable non-volatile memory module is provided. The method includes dividing logical addresses into a plurality of logical zones, and respectively establishing a plurality of logical address mapping tables for the logical zones.
12/26/13
20130346674
Data writing method, memory controller and memory storage device
A data writing method for controlling a rewritable non-volatile memory module having a plurality of physical erase units is provided. The method includes: receiving a write command which instructs writing data to a first logical address, wherein the first logical address is mapped to a second physical erase unit; determining whether the second physical erase unit is in a sequential writing state which represents that the physical programming units over a predetermined ratio in the second physical erasing unit have been successively written sequentially within a predetermined time; if yes, writing the data into a third physical erasing unit in a first programming mode, wherein the first programming mode represents that a plurality of upper physical programming units are non-programmable.
12/26/13
20130346673
Method for improving flash memory storage device access
A method for improving flash memory storage device access is disclosed. The steps of the method comprises requesting to read/write data of logical address by a host; setting up an engine by a cpu; looking up physical address and updating at least one table stored in at least one flash memory by the engine; and reading/writing data from/to the at least one flash memory.
12/19/13
20130339667
Special case register update without execution
A method of changing a value of associated with a logical address in a computing device. The method includes: receiving an instruction at an instruction decoder, the instruction including a target register expressed as a logical value; determining at an instruction decoder that a result of the instruction is to set the target register to a constant value, the target register being in a physical register file associated with an execution unit; and mapping, in a register mapper, the logical address to a location represented by a special register tag..
12/19/13
20130339666
Special case register update without execution
A method of changing a value of associated with a logical address in a computing device. The method includes: receiving an instruction at an instruction decoder, the instruction including a target register expressed as a logical value; determining at an instruction decoder that a result of the instruction is to set the target register to a constant value, the target register being in a physical register file associated with an execution unit; and mapping, in a register mapper, the logical address to a location represented by a special register tag..
12/19/13
20130339628
Determining the logical address of a transaction abort
Embodiments relate to determining the logical address of a transaction abort. In an embodiment, one or more instructions are received are received from an application.
12/12/13
20130332700
Cloud storage arrangement and method of operating thereof
There is provided a storage arrangement and a method of operating thereof. The storage arrangement comprises a first storage system and one or more second storage systems operatively coupled to the first storage system.


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Logical Address topics: Logical Address, Address Space, Storage Device, Volatile Memory, Control Unit, Memory Device, Data Storage, Interleave, Distributed, Redundancy, Physical Map, Backing Store, Forward Index, Data Structure, Contiguous

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