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Line Driver

Line Driver-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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Method and apparatus for edge equalization for high speed drivers
Mediatek Inc.
October 05, 2017 - N°20170288665

A line driver for signal equalization is described. The line driver may comprise an equalization driver and a gating circuit. The gating circuit may be configured to gate the equalization driver between a first transition and a second transition, such as between a rising edge and a falling edge. The gating circuit may comprise one or more delay elements, such ...
Three dimensional storage cell array with highly dense and scalable word line design approach
Intel Corporation
October 05, 2017 - N°20170287833

An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word ...
Semiconductor device
Renesas Electronics Corporation
October 05, 2017 - N°20170287553

An assist driver is coupled to an end of a word line to which a word line driver is not coupled, and couples the other end of the word line to a first power source, in accordance with a voltage of the other end of the word line.
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Semiconductor memory device
Rohm Co., Ltd.
September 28, 2017 - N°20170278558

Proposed as a configuration, a controlling method, and a testing method for a ferroelectric shadow memory are (1) a bit line non-precharge method, in which no precharging of a bit line is performed during a read/write operation; (2) a plate line charge share method, in which electric charge is shared between plate lines that are driven sequentially during store/recall operation; (3) ...
Semiconductor storage device and test method thereof using a common bit line
Renesas Electronics Corporation
September 14, 2017 - N°20170263334

Provided is a semiconductor storage device including: first memory cells; first word lines; first bit lines; a first common bit line; second memory cells; second word lines; second bit lines; a second common bit line; a first selection circuit that connects the first common bit line to a first bit line selected from the first bit lines; a second selection ...
Semiconductor memory device
Kabushiki Kaisha Toshiba
September 14, 2017 - N°20170263326

A memory device capable of narrowing the threshold voltage distribution thereof includes word lines, bit lines, memory cells, a word line driver configured to apply voltage to a selected word line, a sense amplifier circuit configured to detect data of the memory cell, and a controller configured to control the word line driver and the sense amplifier. A write sequence ...
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Word line decoder circuitry under a three-dimensional memory array
Sandisk Technologies Inc.
August 24, 2017 - N°20170243650

The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact ...
Method and apparatus for controlling access to a common bus by multiple components
Micron Technology, Inc.
August 24, 2017 - N°20170243631

Apparatuses and methods for controlling access to a common bus including a plurality of memory devices coupled to a common bus, wherein individual ones of the plurality of memory devices are configured to access the common bus responsive to a strobe signal, and a strobe line driver programmed with a first delay associated with a combination of a first command ...
Dual rail memory, memory macro and associated hybrid power supply method
Taiwan Semiconductor Manufacturing Company Ltd.
August 24, 2017 - N°20170243620

A dual rail memory operable at a first voltage and a second voltage, the dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal; ...
Flash memory
Renesas Electronics Corporation
August 17, 2017 - N°20170236587

In order to reduce the manufacturing cost, a flash memory includes a memory cell array formed by a plurality of memory cells arranged in a matrix shape; a plurality of word lines provided in each column of the memory cell array; a first word line driver that outputs a first voltage group to each of the word lines; and a ...
Semiconductor memory device for stably reading and writing data
Renesas Electronics Corporation
August 17, 2017 - N°20170236579

In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply ...
Bit-cell voltage distribution system
Apple Inc.
August 17, 2017 - N°20170236577

In some embodiments, a method includes receiving, at a voltage distribution circuit, a power enable signal. In response to the power enable signal, the voltage distribution circuit may connect a word line driver circuit to a bit-cell voltage circuit such that an operating voltage is received at a bit-cell circuit before a word line signal form the word line driver ...
Display device
Japan Display Inc.
August 10, 2017 - N°20170228077

To enable size reduction of a display device having a touch sensor function in which a display area has a non-rectangular shape. In a display area, video lines extend in the first direction, and scan lines and common electrodes extend in the second direction. A video signal transmission circuit is arranged along a first edge of the display area, with ...
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Line Driver Patent Applications
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Apparatuses, circuits, and methods for biasing signal lines
Micron Technology, Inc.
July 20, 2017 - N°20170206942

Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal ...
Display device
Samsung Display Co., Ltd.
July 06, 2017 - N°20170193918

A display device includes: a pixel unit including pixels, each including an oled; a scan driver configured to supply scan signals to scan lines connected to the pixels; a data driver configured to supply data signals to data lines connected to the pixels; a control line driver configured to supply control signals to control lines connected to the pixels; a ...
Memory tile access and selection patterns
Micron Technology, Inc.
July 06, 2017 - N°20170192911

In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory ...
Through-memory-level via structures for a three-dimensional memory device
Sandisk Technologies Llc
June 22, 2017 - N°20170179154

A three dimensional nand memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via ...
Through-memory-level via structures for a three-dimensional memory device
Sandisk Technologies Llc
June 22, 2017 - N°20170179153

A three dimensional nand memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via ...
Through-memory-level via structures for a three-dimensional memory device
Sandisk Technologies Llc
June 22, 2017 - N°20170179152

A three dimensional nand memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via ...
Through-memory-level via structures for a three-dimensional memory device
Sandisk Technologies Llc
June 22, 2017 - N°20170179151

A three dimensional nand memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via ...
Through-memory-level via structures for a three-dimensional memory device
Sandisk Technologies Llc
June 22, 2017 - N°20170179026

A three dimensional nand memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via ...
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