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Line Driver

Line Driver-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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Through-memory-level via structures for a three-dimensional memory device
Sandisk Technologies Llc
June 22, 2017 - N°20170179154

A three dimensional nand memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via ...
Through-memory-level via structures for a three-dimensional memory device
Sandisk Technologies Llc
June 22, 2017 - N°20170179153

A three dimensional nand memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via ...
Through-memory-level via structures for a three-dimensional memory device
Sandisk Technologies Llc
June 22, 2017 - N°20170179152

A three dimensional nand memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via ...
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Through-memory-level via structures for a three-dimensional memory device
Sandisk Technologies Llc
June 22, 2017 - N°20170179026

A three dimensional nand memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via ...
High voltage tolerant word-line driver
Intel Corporation
June 15, 2017 - N°20170169874

Described is a word-line driver which is operable to switch a voltage level of a word-line to one of: first power supply, second power supply, or third power supply wherein the voltage level of the second power supply is higher than the voltage level of the first power supply, and wherein transistors of the word-line driver have same gate oxide ...
Dynamic random access memory circuit and voltage controlling method thereof
Intel Corporation
May 25, 2017 - N°20170148503

A dynamic random access memory circuit includes several memory cells, several word line drivers and a first voltage generator. The first voltage generator electrically coupled with the word line drivers, and the first voltage generator is configured to generate a first voltage signal to the word line drivers, in which during a self refresh period of the memory cells, the ...
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Line Driver Patent Applications
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  • + full patent PDF documents of Line Driver-related inventions.
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Semiconductor device
Semiconductor Energy Laboratory Co., Ltd.
May 11, 2017 - N°20170132985

It is an object to provide a semiconductor device which can supply a signal with sufficient amplitude to a scan line while power consumption is kept small. Further, it is an object to provide a semiconductor device which can suppress distortion of a signal supplied to the scan line and shorten a rising time and a falling time while power ...
Enumeration of cameras in an array
Gopro, Inc.
May 04, 2017 - N°20170126985

Disclosed is an apparatus and method for an enumeration circuit that enumerates a plurality of devices in an array. The apparatus includes an input line to receive an input signal. A comparator compares the voltage of the input signal to a voltage of a ground reference. Based on the comparison, a first device detector module determines if the current device ...
Multilevel driver for high speed chip-to-chip communications
Kandou Labs, S.a.
April 27, 2017 - N°20170118048

Transmission line driver systems are described which are comprised of multiple paralleled driver elements. The paralleled structure allows efficient generation of multiple output signal levels with adjustable output amplitude, optionally including finite impulse response signal shaping and skew pre-compensation.
Semiconductor devices including resistive memory cells
Samsung Electronics Co., Ltd.
April 27, 2017 - N°20170117042

A resistive memory device resistive memory device includes a bit line configured to be driven by a bit line driver, a source line configured to be driven by a source line driver adjacent to the bit line driver, and a plurality of memory cells connected between the bit line and the source line. An electrical path of the bit line ...
Source line driver for three dimensional non-volatile memory
Sandisk Technologies Llc
April 27, 2017 - N°20170117036

A non-volatile storage system includes a plurality of non-volatile memory cells configured to form a monolithic three dimensional memory structure, a plurality of bit lines connected to the memory cells, a plurality of source lines connected to the memory cells, a plurality of bit line drivers connected to the bit lines and a plurality of source line drivers connected to ...
Data line driving circuit, data line driver and display device including the same
National Chiao Tung University
April 27, 2017 - N°20170116906

A data line driving circuit for a display device having a plurality of data lines is provided to include a plurality of data line drivers respectively coupled to the data lines. Each data line driver includes a register unit to store video data having a pixel value, a pulse width modulation unit generating a pwm signal having a pulse width ...
Dual rail memory, memory macro and associated hybrid power supply method
Taiwan Semiconductor Manufacturing Company Ltd.
April 20, 2017 - N°20170110164

A dual rail memory operable at a first voltage and a second voltage is disclosed. The dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output ...
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Line Driver Patent Applications
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  • + full patent PDF documents of Line Driver-related inventions.
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  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Dual rail memory, memory macro and associated hybrid power supply method
Taiwan Semiconductor Manufacturing Company Ltd.
March 23, 2017 - N°20170084317

A dual rail memory operable at a first voltage and a second voltage, the dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal; ...
Semiconductor device
Renesas Electronics Corporation
March 16, 2017 - N°20170076785

An assist driver is coupled to an end of a word line to which a word line driver is not coupled, and couples the other end of the word line to a first power source, in accordance with a voltage of the other end of the word line.
Semiconductor device with hierarchical word line scheme
Sk Hynix Inc.
March 02, 2017 - N°20170062022

A semiconductor device includes: first and second memory cell regions disposed adjacent to each other in a first direction, and suitable for sharing a sub-word line driving signal, and a first sub-word line driving unit disposed in a crossing area that is disposed between the first and second memory cell regions in a diagonal direction. The first sub-word line driving ...
Semiconductor storage device and test method thereof using a common bit line
Renesas Electronics Corporation
February 16, 2017 - N°20170047129

Provided is a semiconductor storage device including: first memory cells; first word lines; first bit lines; a first common bit line; second memory cells; second word lines; second bit lines; a second common bit line; a first selection circuit that connects the first common bit line to a first bit line selected from the first bit lines; a second selection ...
Memory device with reduced neighbor memory cell disturbance
Micron Technology, Inc.
February 16, 2017 - N°20170047117

In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping element, and control circuit. The memory cell and clamping element can be both coupled to a digit line. The control circuit can be configured to cause the clamping element to clamp the voltage of the ...
Displays with gate driver circuitry for discharging display pixels
Apple Inc.
February 02, 2017 - N°20170031477

A touch screen display may include gate line driver circuitry coupled to a display pixel array. The gate driver circuitry may include gate drivers connected in a chain. A given one of the gate drivers may include a set-reset latch. The set-reset latch may have a set input and a reset input. A logic gating circuit such as a logic ...
Display device
Semiconductor Energy Laboratory Co., Ltd.
January 12, 2017 - N°20170013720

The display device includes: a flexible display panel including a display portion in which scanning lines and signal lines cross each other; a supporting portion for supporting an end portion of the flexible display panel; a signal line driver circuit for outputting a signal to the signal line, which is provided for the supporting portion; and a scanning line driver ...
Address decoding circuitry
Arm Limited
January 12, 2017 - N°20170011788

Various implementations described herein are directed to an integrated circuit for address decoding. The integrated circuit may include an input circuit configured to provide an encoded address via multiple address lines. The integrated circuit may include an address decoding circuit configured to directly translate the encoded address provided via the multiple address lines. The address decoding circuit may include multiple ...
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