|| List of recent Lexer-related patents
|Multithreaded event handling using partitioned event de-multiplexers|
Techniques for handling events are provided. In one embodiment, a computer system can create a plurality of i/o handles for receiving events.
|Dual-domain dynamic multiplexer and method of transitioning between asynchronous voltage and frequency domains|
A dual-domain dynamic multiplexer and a method of transitioning between asynchronous voltage and frequency domains. One embodiment of the dual-domain dynamic multiplexer includes: (1) a first domain having a first voltage and a first clock, and a second domain having a second voltage and a second clock, (2) a plurality of data and data select input pairs wherein a data input of an input pair is in the first domain and a data select input of an input pair is in the second domain, and (3) a pre-charge stage in the second domain that is energized upon an edge of the second clock, whereby one data and data input pair is enabled and data latched in the second domain upon another edge of the second clock..
|Broadband distributed antenna system with non-duplexer isolator sub-system|
Certain aspects and aspects of the present invention are directed to a distributed antenna system having a downlink communication path, an uplink communication path, and a non-duplexer isolator sub-system. The downlink communication path can communicatively couple a transmit antenna to a base station.
|Wavelength multiplexing optical communication device|
A wavelength multiplexing optical communication device includes: a pluggable ld module that generates a check optical signal having a specific wavelength; a multiplexer that multiplexes the check optical signal onto the transmitting-side optical fiber which links the transmitting-side connector with a corresponding output port of the optical demultiplexer, the transmitting-side connector being connected to the in-device optical fiber; a demultiplexer that demultiplexer the check optical signal from a receiving-side optical fiber which links the receiving-side connector with a corresponding input port of the optical multiplexer, the receiving-side connector being connected to the in-device optical fiber; a level detector that detects a level of the check optical signal obtained by the demultiplexer; and an erroneous connection detector that detects an erroneous connection of the in-device optical fiber in accordance with the detected level.. .
|Coding concept allowing parallel processing, transport demultiplexer and video bitstream|
A raw byte sequence payload describing a picture in slices, wpp substreams or tiles and coded using context-adaptive binary arithmetic coding is subdivided into tranches with continuing the context-adaptive binary arithmetic coding probability adaptation across tranche boundaries. Thereby, tranche boundaries additionally introduced within slices, wpp substreams or tiles do not lead to a reduction in the entropy coding efficiency of these entities.
|Methods and apparatuses including a statistical multiplexer with bitrate smoothing|
Examples methods and apparatuses including a statistical multiplexer with the bitrate smoother are described herein. An example apparatus may include a statistical multiplexing (statmux) system for use with a communication link.
A tunable diplexer includes a high band port, a low band port, an antenna port, a high pass filter, and a low pass filter. The high pass filter is coupled between the high band port and the antenna port, and is configured to pass signals within a high pass band between the high band port and the antenna port.
|Apparatus for communication using simplex antennas|
An apparatus comprises a duplexer having a transmit port, a receive port, and an antenna port. A transmitter is coupled to the antenna port of the duplexer.
|Method and transceiver for cancelling multi-carrier transmission interference|
A method, an apparatus, and a transceiver for cancelling multi-carrier transmission interference are provided. The method includes: collecting a high order intermodulation signal in radio frequency signals output by a transmitter; processing the high order intermodulation signal so as to generate a first digital signal; establishing a high order intermodulation model by using the first digital signal and a first baseband signal output by the transmitter; generating a second digital signal by using a coefficient of the high order intermodulation model and a second baseband signal output by the transmitter; and counteracting interference in a digital signal output by a receiver with the second digital signal.
|Dc-based uninterruptible power system and method for detecting abnormal voltage|
A direct current (dc) uninterruptible power system is disclosed. The dc-based uninterruptible power system includes a multiplexer, a battery unit, a linear regulator, a switch-transistor, a voltage comparator and micro controller.
|Method and system for control of apparatus|
The present invention relates generally to manually controlling an apparatus and/or a multiplexer. More particularly, the present invention relates to controlling an apparatus and/or a multiplexer by signals that preferably include both proportional-output signals and rate-of-change signals.
|Front-end circuit for band aggregation modes|
A front-end circuit for a wireless communication unit includes at least two antenna feeds. At least one of the antennas is coupled to an antenna switch.
A smart antenna apparatus includes a casing, which supports an omnidirectional antenna array; a plurality of transceivers electrically connected with the antenna array; and a format converter and booster device electrically connected between the plurality of transceivers and a network port, said format converter and booster device comprising a multiplexer/de-multiplexer circuit for encoding plural usb signals from the plurality of transceivers to the network port and for decoding plural usb signals from the network port to the plurality of transceivers. .
|Channel monitoring with plural frequency agile receivers|
A system and method to efficiently use a plurality of ‘receivers’ to monitor a larger plurality of ‘sources’ for audio content. Upon identifying that a source is active, one of the plural receivers is assigned to convey the content to a destination.
|Methods and apparatuses including a statistical multiplexer with global rate control|
Examples methods and apparatuses including a statistical multiplexer with global rate control are described herein. An example apparatus may include a statistical multiplexing (statmux) system coupled to a communication link.
|Carrier aggregation arrangements for mobile devices|
Front end circuitry for a wireless communication system includes a first antenna node, a second antenna node, a first triplexer, a second triplexer, and front end switching circuitry coupled between the first triplexer, the second triplexer, the first antenna node, and the second antenna node. The front end switching circuitry is configured to selectively couple the first triplexer to one of the first antenna node and the second antenna node and couple the second triplexer to a different one of the first antenna node and the second antenna node.
|Positive edge preset reset flip-flop with dual-port slave latch|
In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals se and sen of the multiplexer determine whether data or scan data is input to the master latch.
|Tunable diplexers in three-dimensional (3d) integrated circuits (ic) (3dic) and related components and methods|
Tunable diplexers in three-dimensional (3d) integrated circuits (ic) (3dic) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer.
|Code coverage circuitry|
A method with a circuit that includes a memory (130) coupled to an analog line coverage circuit (104). The analog line coverage circuit includes a plurality of buffers (151-154) in which each buffer is coupled to one memory location of the memory, a plurality of bin cells (161-164) in which each bin cell is coupled to a buffer, a multiplexer (170), each input terminal of which is coupled to a bin cell, and an analog-to-digital converter (180) coupled to the multiplexer and to an output terminal of the analog line coverage circuit.
|Timing control circuit|
A timing control circuit includes: a first variable delay circuit configured to receive first data having a first communication speed, and to give a variable delay to the first data; a first multiplexer configured to receive output of the first variable delay circuit, and to convert into second data having a second communication speed different from the first communication speed in accordance with first control signal; a second variable delay circuit configured to receive third data having the first communication speed, and to give a delay corresponding to the delay of the first variable delay circuit to the third data; a decision circuit configured to compare timings of output of the second variable delay circuit and the first control signal; and a control circuit configured to control the delays of the first variable delay circuit and the second variable delay circuit in accordance with output of the decision circuit.. .
|Monolithic device combining cmos with magnetoresistive sensors|
A monolithic device comprises a substrate. An array of sensing elements is coupled to the substrate, and each sensing element includes a magnetoresistive sensor.
|Full channel-swap crossbar|
A programmable channel-swap crossbar switch for swapping signal flow from one channel to another within an ethernet physical layer device (phy) is presented. The crossbar switch includes two or more programmed multiplexers, each multiplexer configured to receive two or more input signals and to select which one of the input signals to pass to a programmed corresponding channel, such that a first, input signal associated with a first channel can be swapped to a second channel as operating conditions necessitate.
|Duplexer architectures and methods for enabling additional signal path|
Disclosed are architectures and methods for enabling additional signal path. In some embodiments, a frequency division duplexing (fdd) system can include a transmit (tx) path configured for passage of a tx signal in a first frequency band during operation in a first mode; a receive (rx) path configured for passage of an rx signal in a second frequency band during operation in a second mode, with the second mode being different than the first mode, and the second frequency band having at least some overlap with the first frequency band; and a bandpass filter disposed along the tx path and along the rx path, with the bandpass filter being configured to filter the tx signal when in the first mode and to filter the rx signal when in the second mode.
|Front-end circuit and impedance adjustment method|
Provided is a front-end circuit which can prevent a signal from leaking into another circuit even when signals are sent and received simultaneously in multiple frequency bands in carrier aggregation. The circuit includes a transmission and reception antenna 91, a double-pole n-throw switch 92 with its common contact connected to the transmission and reception antenna 91, n variable impedance adjustment circuits 17-1 to 17-n each having a terminal on the antenna side, the terminals being respectively connected to n changeover contacts of the switch 92, n duplexers 93-1 to 93-n each having a common terminal, for receiving transmission and reception signals in first to n-th frequency bands, the common terminals being respectively connected to terminals on the rfic side of the variable impedance adjustment circuits 17-1 to 17-n, a control unit 18 connected to the variable impedance adjustment circuits 17-1 to 17-n and the switch 92 by control lines, for controlling switching operations of the variable impedance adjustment circuits 17-1 to 17-n and the switch 92, and an rfic 16 for sending a control signal to the control unit 18..
|Apparatus and method for reading data from multi-bank memory circuits|
The disclosure relates to an apparatus for reading data from a memory circuit that includes at least two memory banks. The apparatus includes a first multiplexer configured to generate data at a first output from a first selected one of a first set of bit lines of a first memory bank based on a select signal.
|Touch display having in-plane-switching liquid crystal structure|
A touch display having in-plane-switching liquid crystal structure, comprising a pixel cell and a multiplexer circuit, wherein the multiplexer circuit is used to couple a source driver unit with the pixel cell to provide an in-plane switching display function during a display period, and couple a touch control unit with the pixel cell to provide a touch detection function during a touch detection period.. .
|Distributed feeding device for antenna beamforming|
A distributed feeding device for antenna beamforming comprises a first distributed feeding circuit comprising p inputs and n outputs, for producing a signal on each of its outputs with a phase shift which is substantially constant between two adjacent outputs, at least one frequency multiplexer connected to at least one input of the said first circuit, a number n of frequency demultiplexers each connected, by their input, to an output of the first circuit and a second distributed feeding means comprising a plurality of inputs, each connected to an output of one of the frequency demultiplexers, and a plurality of outputs, the second distributed feeding means comprising at least one second distributed feeding circuit comprising q inputs and m outputs, for producing a signal on each output with a phase shift which is substantially constant between two adjacent outputs, the integers p, n, q and m being equal or distinct.. .
|Coupled line system with controllable transmission behaviour|
The invention relates two lines each with two terminals. A first line provides a first terminal and a second terminal.
|Glitch free clock multiplexer|
Apparatus for glitch-free switching between two clock sources on an integrated circuit. Clock gaters provide a clock from a single source that can be turned on and off without causing partial pulses to be created.
|Configurable multi-gate switch circuitry|
Integrated circuits with configurable multi-gate switch circuitry are provided. The switch circuitry may include switch control circuitry and an array of multi-gate switches.
|Data access system, data accessing device, and data accessing controller|
A data access system, device and controller are provided. The data access system includes a plurality of storage units and first controllers, a second controller, and a host.
|Allocating internet protocol (ip) addresses to nodes in communications networks which use integrated is-is|
Previously it has only been possible to allocate unique internet protocol (ip) addresses to nodes in open systems interconnection (osi) communications networks such as those using integrated is-is, by manual configuration. This is time consuming and expensive because an operator must travel to the site of the node.
|Wireless communication unit, radio frequency module and method therefor|
A wireless communication unit includes at least one antenna port; a transmitter and a receiver operably coupled to the at least one antenna port via a duplexer; wherein the duplexer includes a dynamically reconfigurable phase shift network that includes: at least one tunable radio frequency (rf) component; and at least one switch operably coupled to the tunable rf component and controllable to reconfigure the dynamically reconfigurable phase shift network to selectively support both normal and reverse duplexer modes of operation for rf signals passing there through.. .
|Reconfigurable 1xn few-mode fiber optical switch based on a spatial light modulator|
An optical switch includes an array of parallel few-mode fibers stacked vertically; beam stretchers that modifies an aspect ratio between a height and a width of beams associated with each few-mode fiber; a spatial light modulator with a 2d array of independently programmed tunable pixels, wherein the spatial light modulator manipulates phase and/or amplitude at each position of an incident optical beam; a wavelength demultiplexer which can separate the spectral components of an incident beam in angle; and lenses for imaging the modes of the input array of fiber to the spatial light modulator.. .
|Common mode voltage multiplexer|
A circuit and a system that uses the circuit for connecting a plurality of input channels to a receiving device. The circuit includes a plurality of dmos switches, each of which connects a respective one of the input channels to the receiving device in response to a respective control signal.
|Inspection system for oled display panels|
A system for inspecting at least a portion of a display panel having thin film transistors (tfts) and light emitting devicxes (oleds), during or immediately following fabrication, so that adjustments can be made to the fabrication procedures to avoid defects and non-uniformities. The system provides bonding pads connected to signal lines on at least portions of the display panel, and probe pads along selected edges of the display panel.
|Memory interleaving on memory channels|
A memory interleaver includes a channel selection unit to receive a system memory address for a memory request. The interleaver also includes a local memory address computation unit and a de-multiplexer.
A multi-standards transceiver includes: a first synthesizer arranged to generate a first oscillating signal; a second synthesizer arranged to generate a second oscillating signal; a first transceiver; a second transceiver; and a multiplexer coupled to the first synthesizer and the second synthesizer; wherein when the multi-standards transceiver operates under a first frequency mode, the first transceiver is arranged to use the first oscillating signal to modulate a first analog signal and the multiplexer is arranged to output the second oscillating signal to the second transceiver so that the second transceiver uses the second oscillating signal to modulate a second analog signal.. .
|Digital polar modulator for a switch mode rf power amplifier|
A digital polar modulator (dpm) for transforming a baseband signal into a modulated digital modulator output signal comprises an input unit and two low-pass delta-sigma modulators, a first one being connected downstream from the first input part and configured to provide at its output a first pulse train in dependence on an amplitude- modulating baseband signal component, and a second one being connected downstream from the second input part and configured to provide at its output a multilevel quantized signal in dependence on a phase modulating baseband signal component; a multiphase generator, which is configured to provide a set of square-wave carrier signals having a common carrier frequency and exhibiting discrete phase shifts with respect to each other; a multiplexer, which is configured to provide a multiplexer output signal that is formed by switching, in dependence on a signal received at a select input as a function of time, between selected ones of the carrier signals; and a combiner unit.. .
|Video encoding device, video decoding device, video encoding method, video decoding method, and program|
A video encoding device includes: a transformer for transforming an image block; an entropy encoder for entropy-encoding transformed data of the image block transformed by the transformer; a pcm encoder for pcm-encoding an image block; a multiplexed data selector for selecting output data of the entropy encoder or output data of the pcm encoder, for each block of an externally set block size; and a multiplexer for embedding a pcm header into a bitstream, in a block of the externally set block size, wherein the number of successive pcm-encoded blocks is embedded into the pcm header, and pcm data for the number of successive pcm-encoded blocks is multiplexed into the bitstream.. .
An electrical balance duplexer comprising an electrical balance load having an electrical balance load connection, an antenna connection, a first differential power amplifier output connection, a second differential power amplifier output connection; and a power combiner configured to combine output power signals from the first differential power amplifier output connection with output power signals from the second differential power amplifier output connection into the antenna connection and into the electrical balance load connection.. .
|Time-interleaved multi-modulus frequency divider|
Described are a multi-modulus frequency divider and event counter that are based on time-interleaved signals generated from a received signal. For the frequency divider, each time-interleaved clock signal generated from a received clock signal is provided to a bit counter and the output signal from each bit counter is provided to a multiplexer.
|Circuit for measuring acceleration of three-axis acceleration sensor|
Disclosed herein is a circuit for measuring acceleration of a three-axis acceleration sensor. The circuit for measuring acceleration of a three-axis acceleration sensor includes: three-axis acceleration sensors connected to one another in parallel and sensing the respective accelerations applied to three axes directions of x, y, and z axes to output corresponding signals; a demultiplexer outputting three axes signals each output from the three-axis acceleration sensors through a single path; and an amplifier amplifying the output signal from the demultiplexer, and further includes, at a back-end of the amplifier, a multiplexer distributing a signal output from the amplifier to the respective axes, a sample and hold circuit unit sampling and storing an analog signal of each axis output from the multiplexer, and an analog-to-digital converter converting an analog signal output from the amplifier into a digital signal..
|Position independent testing of circuits|
Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs.
|Method for testing paths to pull-up and pull-down of input/output pads|
A scan chain architecture for each path in a circuit having combinational paths includes a control mechanism to control one or more flip flops and multiplexers to direct operational or test signals. Operational signals are sent along at least one combinational path to a pull-up/pull-down for at least one input/output pad and an operational voltage is recorded.
|Optimizing optical systems using code division multiple access and/or orthogonal frequency-division multiplexing|
An optical receiver comprises an optical port configured to receive an encoded optical signal, and a demodulation block indirectly coupled to the port and comprising a multiplexer, wherein the multiplexer is configured to receive an encoded electrical signal, wherein the encoded electrical signal is associated with the encoded optical signal, and wherein the encoded electrical signal is encoded using a code division multiple access (cdma) scheme, receive a code associated with the scheme, perform a dot multiplication of the encoded electrical signal and the code, and generate a differential voltage based on the dot multiplication.. .
|Switching architecture with packet encapsulation|
The invention includes, among other things, a system for passing tdm traffic through a packet switch. In one embodiment, the system includes a packet switch that has a plurality of data ports and is capable of routing fsdu packets between the plurality of data ports.
|Analog/digital converter and method for converting analog signals to digital signals|
The objective of the invention is to provide an a/d converter that exhibits fewer malfunctions due to variations in manufacturing. An a/d converter (1) of the invention, which is a cyclic type of analog/digital converter for converting an analog input signal to a digital signal having a predetermined resolution, comprises: a digital approximation unit (10) that includes a comparing unit (13) for comparing the magnitude of an input first analog signal with a threshold value to output a digital value indicating a result of the comparison and that also includes an mdac unit (14) for amplifying the first analog signal to β-fold, where β is greater than one but smaller than two, and for executing a predetermined computation in accordance with the result of the comparison of the comparing unit to output a second analog signal; a multiplexer (20) that, if the msb is to be computed, outputs the analog input signal and, otherwise, outputs the second analog signal as the first analog signal; a β estimating unit (30) that estimates the value of β; and a digital signal outputting unit (40) that sequentially takes in digital values outputted by the comparing unit and that outputs the taken-in digital values as the digital signal..
|Ultra-broadband planar millimeter-wave mixer with multi-octave if bandwidth|
In some embodiments, a system may include a passive uniplanar single-balanced millimeter-wave mixer. In some embodiments, a three-port diode-tee ic forming a mixer core is coupled between an end of a slotline balun and a second coplanar balun.
|Pulse generation circuit and semiconductor device|
Two gate drivers each comprising a shift register and a demultiplexer including single conductivity type transistors are provided on left and right sides of a pixel portion. Gate lines are alternately connected to the left-side and right-side gate drivers in every m rows.
|Method and apparatus for band separation for multiband communication systems|
Aspects of a method and apparatus for band separation for multiband communication systems are provided. One or more circuits for use in a transceiver may comprise a triplexer and a leakage processing module.
|Dual master jtag method, circuit, and system|
A dual-master controller includes a plurality of jtag data registers including a controller-mode register that stores information indicating a standard jtag or a processor-controlled mode of operation. A jtag tap controller receives control signals over a standard test access port and a processor controller receives processor control signals over an external processor bus.
|Circuit and method for testing memory devices|
The present application provides a circuit and method for testing a memory device. The memory device has multiple blocks addressable via a plurality of address lines and capable of inputting and/or outputting data via a plurality of data lines.
|Wireless system for epilepsy monitoring and measurement|
A wireless system for brain monitoring/mapping of neurological-disorder patients includes a plurality of electrodes each configured for surface abutment of brain tissue and main circuitry for placement outside a body of a patient and configured to transmit power at radio frequencies and send and receive data using infrared energy. Remote circuitry is provided for subcutaneous implantation in a head of the patient.
|Laser relay for free space optical communications|
A laser relay module for free space optical communications including an optical telescope for receiving and transmitting optical beams; an optical diplexer for separating transmitting and received optical beams; an optical amplifier; a modulated beacon laser for line of sight control of a plurality of communicating remote network nodes; a beacon beam detector for detecting an incoming beacon optical beam for line of sight control of the optical telescope and receiving data from other network nodes; and means for inserting an output of the modulated beacon laser into the optical telescope for transmission to another network node, and for transporting the incoming beacon optical beam to the beacon detector.. .
|Optical communication apparatus and optical communication method|
An optical communication apparatus and an optical communication method are disclosed. An optical communication apparatus mounted in a first node in a linear network coupled among a plurality nodes through an optical transmission line includes a multiplexer for receiving a plurality of optical signals having different wavelengths to output a first multi-wavelength optical signal obtained by coupling the plurality of optical signals, and a first optical coupler for dividing the first multi-wavelength optical signal into respective multi-wavelength optical signals to be transmitted to at least two different neighboring nodes..
|Signal margin centering for single-ended edram sense amplifier|
Apparatus and methods for signal margin centering for single-ended edram sense amplifier. A plurality of dram cells is connected to an input side of a multiplexer by a first bitline.
|Sampling device with buffer circuit for high-speed adcs|
A sampling and interleaving stage device for use in an analog-digital-converter and for providing a sampling output signal and an analog-to-digital-converter. The sampling and interleaving stage device for use in an analog-digital-converter, including: a receiving unit having a clock unit with a plurality of clock-driven switches for receiving an input signal; for each of the plurality of clock-driven switches, a first demultiplexer, for receiving the input signal via a clock-driven switch and for providing a number of first demultiplexer outputs; for a first demultiplexer output, at least one storage element for a stored input potential depending on the input signal; and an output demultiplexer for receiving an indication about the stored input potential and for outputting a corresponding sampling output signal to a respective sampling output..
One embodiment of the present invention provides a synthesizer. The synthesizer includes one or more tunable oscillators, a frequency-dividing circuit coupled to the tunable oscillators, and a multiplexer coupled to the frequency-dividing circuit.
|Sensor control apparatus and gas detection system|
A sensor control apparatus (2) of a gas detection system (1) includes a first low-pass filter (46), a second low-pass filter (48), and a multiplexer (50) so as to provide different time constants for detection of a sensor output signal vs1 and for detection of a response signal vs2. When the sensor output signal vs1 is detected, a signal whose frequency band is the same as that of vs1 is input to the analog-to-digital conversion section (31) through the first low-pass filter (46).
|Mobile communication method, radio base station, and mobile station|
A duplexer d1 or d2 to be used is appropriately selected from multiple duplexers d1 and d2. A mobile communication method of the invention is a mobile communication method for a mobile communication system 1 operated in a band f1.
|Method and apparatus for sorting elements in hardware structures|
A method for sorting elements in hardware structures is disclosed. The method comprises selecting a plurality of elements to order from an unordered input queue (uiq) within a predetermined range in response to finding a match between at least one most significant bit of the predetermined range and corresponding bits of a respective identifier associated with each of the plurality of elements.
|Method for implementing a reduced size register view data structure in a microprocessor|
A method for implementing a reduced size register view data structure in a microprocessor. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of multiplexers to access ports of a scheduling array to store the instruction blocks as a series of chunks..
|Systems and methods for obtaining substantially simultaneous mult-channel impedance measurements and related applications|
An implantable system includes terminals, a pulse generator, a sensing circuit, separate signal processing channels, and first, second and third multiplexers. The terminals are connected to electrodes via conductors of leads.
|Tunable ila and dila matching for simultaneous high and low band operation|
A method and system configures a wireless communication device to support simultaneous signal propagation using a single narrow band antenna. An antenna tuner controller (atc) configures a tunable low band matching circuit to provide a first antenna matching in order to support propagation of a low band signal with a first signal path.
|Optical signal demodulator, optical signal demodulating method, and optical add-drop multiplexer|
An optical signal demodulator includes: an obtaining unit configured to obtain a spectrum of an optical signal generated by a second signal being superimposed on a first signal using frequency modulation; an identifying unit configured to identify a peak wavelength which is a wavelength corresponding to a peak position of the spectrum; and a demodulating unit configured to demodulate the second signal from the optical signal using a wavelength-variable filter to which a transmitted wavelength band has been set based on the peak wavelength.. .
|Upgradeable passive optical fiber circuit|
Optical equipment for 1g-epon, 10g-epon, and cwdm services are joined together using a novel combination of optical power splitters and multiplexers. This combination of splitters and multiplexers can be disposed in a single housing, which reduces the size of the combination and improves performance, since jumpers between multiple, separately packaged, optical components can be avoided.
|Method and apparatus for multiplexed time aligned analog input sampling|
A sensor system includes a first sensor and a second sensor and a multiplexor having at least two multiplexer inputs connected to the sensors. The output of the multiplexor is connected to a time correlation logic circuit via at least a signal conditioning and anti-aliasing filter, and the output of the time correlation logic is a time correlated sensor reading of the first and second sensor..
|Low-power cml-less transmitter architecture|
Exemplary embodiments of the present invention relate to a low-power current mode logic (cml)-less transmitter architecture. A transmitter comprises a main multiplexer configured to generate a main data signal by multiplexing parallel main data signals retimed from a retimer for time margin between parallel input data signals and a multiphase clock signals from a clock distributor, a secondary multiplexer configured to generate a post data signal by multiplexing parallel post data signals retimed from the retimer, and a plurality of output drivers configured to generate a serial data signal by summing the main data signal and the post data signal..
|Full-duplex wireless transceiver with hybrid circuit and reconfigurable radiation pattern antenna|
A method and circuit are provided that solve the problem of prolonged signal fading in transceivers utilizing dual antenna match in a hybrid transmitter-receiver cancellation circuit, thereby enabling practically implementable full-duplex single channel, or duplexerless frequency division duplex (fdd), wireless communication systems. The method includes controlling dynamic change in signal's amplitude and phase at the receiver port of a hybrid tx-rx circuit by continuously varying radiation pattern parameters of at least one antenna, while maintaining nearly constant impedance at the hybrid's antenna interface ports and equalizing propagation delays between the hybrid circuit and both antennas, using a novel circuit design..
|Device and method for improving reading speed of memory|
A memory device includes a plurality of sense amplifiers coupled with an array of memory cells, a plurality of output data lines receiving outputs of corresponding sense amplifiers, and a plurality of precharge circuits configured to apply a precharge voltage on the output data lines. A controller provides control signals to the sense amplifiers and to the precharge circuits, including to cause the precharge circuits to precharge the output data lines before the sense amplifiers drive output data signals to the output data lines.
|Memory with bit line current injection|
Embodiments of a memory are disclosed that may allow for the detection of weak data storage cells or may allow operation of data storage cells under conditions that may represent the effects of transistor ageing. The memory may include data storage cells, a column multiplexer, a sense amplifier, and a current injector.
|Circuit for memory write data operation|
A pulsed dynamic lcv circuit for improving write operations for sram. The pulsed dynamic lcv circuit includes voltage adjustment circuitry having a plurality of selectable reduced supply voltages and timing adjustment circuitry having a plurality of selectable logical state transition timings for adjustably controlling the voltage and timing of a transition from a selected reduced supply voltage back to a nominal supply voltage.
|Memory with redundant sense amplifier|
Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit.