|| List of recent Level Shift-related patents
| Methods and circuits for dynamically scaling dram power and performance|
A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface.
| Device to avoid attacks from electro-sensitive animals|
A system for protecting user's body from the attacks of electro-sensitive animals is provided. The system includes a frequency generator, a modulator, a controller, a level shifter, plurality of electrodes and a power source to provide power to the controller.
R2z Innovations, Inc.
|Nonvolatile semiconductor memory device|
A nonvolatile semiconductor memory device comprises a memory cell array, a staircase voltage generator, and a decode and level shift circuit. The memory cell array comprises a plurality of memory cells and a plurality of bit lines coupled to the plurality of memory cells.
Elite Semiconductor Memory Technology Inc.
|Semiconductor device and power conversion device using the same|
In a semiconductor device such as a three-phase one-chip gate driver ic, hvnmoss configuring two set and reset level shift circuits are disposed on non-opposed surfaces, and it is thereby possible to reduce the amount of electrons flowing into drains of hvnmoss of another phase due to a negative voltage surge. Also, distances from an opposed surface on the opposite side to the respective drains of the hvnmoss configuring the two set and reset level shift circuits are made equal to or more than 150 μm, and it is thereby possible to prevent a malfunction of a high side driver circuit of another phase to which no negative surge is applied..
Fuji Electric Co., Ltd.
|Driver and driving control power converter|
A driver and a driving control method for a power converter are provided. The driver includes a level shift circuit, a negative voltage generator and a first pmos transistor.
Upi Semiconductor Corp.
|Methods and systems to selectively boost an operating voltage of, and controls to an 8t bit-cell array and/or other logic blocks|
Methods and systems to provide a multi-vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-vcc environment may be implemented to isolate a vmin-limiting logic block from a single-vcc environment, such as to reduce vmin and/or improve energy efficiency in the single-vcc environment.
|Touch detection method and touch detection apparatus having built up linearity|
A touch detection apparatus includes a sensor pad to output a signal based on a touch state in response to an alternating voltage in a floating state after being charged, an operational amplifier including a first input connected to an output of the sensor pad and a second input to receive the alternating voltage, a level shift detection unit to detect a touch signal based on a difference between a voltage variation at an output end of the operational amplifier caused by the alternating voltage and a voltage variation at the output end of the operational amplifier caused by occurrence of a touch, and a switching unit including a first switch to control an electric potential between a first input and the output end of the operational amplifier and a second switch to connect or not the sensor pad and the first input of the operational amplifier.. .
Crucialtec Co., Ltd.
|Voltage level shift circuit for multiple voltage integrated circuits|
A voltage level shift circuit comprises a first pair of transistors and a second pair of transistors. A first transistor of the second pair of transistors is coupled with an input signal terminal.
Taiwan Semiconductor Manufacturing Company, Ltd.
|Semiconductor device having level shift circuit|
Disclosed herein is a device includes; a level conversion circuit coupled to first and third power supply lines, receiving a first signal and an inverted signal of the first signal each having an amplitude between first and second potentials, and output ting a second signal having an amplitude between first and third potentials; a delay circuit coupled to the first and second power supply lines, and output ting a third signal delayed from the first signal; and an output circuit including first and second transistors coupled in series between the first and third power supply lines, the first transistor having a control electrode supplied with the second signal, and the second transistor having a control electrode supplied with the third signal.. .
Micron Technology, Inc.
|Overcurrent protection method, circuit and integrated circuit|
Disclosed is an overcurrent protection method and circuit and an integrated circuit. The overcurrent protection circuit includes an output circuit, an overcurrent sampling circuit and an overcurrent protection loop circuit.
Fairchild Semiconductor Corporation
Apparatus and detecting touch, capable of reducing parasitic capacitance
A touch detection apparatus includes at least one sensor pad outputting a signal according to a touch state in response to an alternating voltage in a floating state after charging with an electric charge, an additional electrostatic capacitive unit electrically connected to an output terminal of the sensor pad and having a capacitance corresponding to a parasitic capacitance of the sensor pad, an electrical charging/discharging unit charging or discharging the additional electrostatic capacitive unit to make the additional electrostatic capacitive unit have an electric charge variation the same as that in the parasitic capacitance caused by the alternation of the alternating voltage but an opposite polarity, and a level shift detection unit detecting a touch signal based on a difference between voltage variations in the sensor pad caused by the alternating voltage during non-touch and caused by the alternating voltage during a touch.. .
Crucialtec Co., Ltd.
Multi power supply type level shifter
There is provided a multi power supply type level shifter. The provided multi power supply type level shifter includes a first level shifter and a second level shifter in a two-stage architecture so as to selectively receive first to third power supplies and change a signal level, even when the first to third power supplies are applied in a different sequence from a normal power-on sequence.
Magnachip Semiconductor, Ltd.
Systems and methods for providing high voltage to memory devices
Apparatus, systems, and methods for providing high voltage to memory devices are provided. One apparatus includes a low voltage input and a two-rail level shifting.
Cypress Semiconductor Corporation
Timing controller for liquid crystal panel and timing control method thereof
A timing controller for a liquid crystal panel and a timing control method thereof are provided. The timing controller includes a timing control unit for analyzing an input signal to generate a system state transition voltage (stv) signal and a base stv signal, and the timing control unit outputs a base trigger signal and a switch trigger signal having asynchronous frame rates to a select unit at the same time.
Chunghwa Picture Tubes, Ltd.
Level conversion circuit and converting voltage level thereof
A level conversion circuit including a first level shifter and a second level shifter is provided. The first level shifter converts a first control voltage into a second control voltage during a voltage conversion period.
Novatek Microelectronics Corp.
Semiconductor integrated circuit and information processing apparatus
According to an embodiment, a semiconductor integrated circuit includes a regulator, a level shifter and a switch circuit. The regulator converts an input voltage that is a difference in potential between a first terminal and a third terminal into an output voltage that is a difference in potential between a second terminal and the third terminal.
Compact level shifter
Embodiments of the present invention provide a device for level shifting an input signal. The device includes an output buffer that has: an output node, a p-fet coupled to a high reference voltage, and an n-fet coupled to a low reference voltage.
Semiconductor integrated circuit device
A semiconductor integrated circuit device comprises i/o cells arranged around a core region. Each of the i/o cells comprises a level shifter circuit, an i/o logic circuit, and an i/o buffer circuit.
Cost effective low pin/ball count level-shifter for lcd bias applications supporting charge sharing of gate lines with perfect waveform matching
A level shifter circuit has a plurality of channels for providing signals to a capacitive load and has circuits for sharing charge stored in the capacitive load between the channels. A first pair of channel clock generating circuits are coupled respectively to a first pair of channels.
A display apparatus is provided which includes a display panel; a gate driver configured to drive a plurality of gate lines, a data driver configured to drive a plurality of data lines, a level shifter configured to generate a gate on voltage corresponding to an atmospheric temperature and to generate a gate clock signal, the gate on voltage becoming higher depending on a decrease in an atmospheric temperature, and a timing controller configured to control the gate driver and the data driver and to generate agate pulse signal having a pulse width corresponding to a voltage level of the gate on voltage.. .
Level shift circuit
A level shift circuit of an embodiment includes first and second mosfets using signals with phases same as and opposite to the phase of an input signal as gate inputs; first and second resistance elements, each having one end connected to a shift level power terminal that supplies high-level output voltage of a level-shifted output signal, and each having the other end connected to a corresponding drain of the first and second mosfets; a comparator having a pair of differential input terminals, individually connected to respective drains of the first and second mosfets; and a current control circuit that controls an amount of first current flowing through the first mosfet via the first resistance element and an amount of second current flowing through the second mosfet via the second resistance element in synchronization with a rising and a falling of a signal level of the input signal.. .
Systems and methods for data receipt from devices of disparate types
Systems and methods are provided for a receiver device for receiving data signals from devices of disparate types. An amplifier is configured to receive a voltage reference signal and a data signal, the data signal being received from a device, the amplifier being configured to output an output signal based on a comparison of the data signal to the voltage reference signal.
Dynamic level shifter circuit
A level shifter does not require any dc (standby) current consumption and has a fast operation with low propagation delay. The level shifting from input to output voltage ranges is performed by a pair of level shifting capacitors.
Voltage level shifter and systems implementing the same
According to the inventive concepts disclosed herein, a level shifter can include an input node in a first voltage domain and an output node in a second voltage domain, higher than the first voltage domain. The input node receives an input signal in the first, lower-voltage domain, and the output node is configured to output a representation of the input signal in the second, higher-voltage domain.
In aspects of the invention, a semiconductor device can include one level shift circuit that outputs a low-side input signal as a high-side signal upon raising a signal level, a pulse modulation circuit that operates in a low-side region, generates a data symbol constituted by or more bits and representing a set signal or a reset signal, where bit is defined as a combination of codes forming a pair. The pulse generation circuit can output the generated data symbol as an input signal of the level shift circuit.
Level shifter circuit and operation method thereof
A level shifter transfers a first voltage signal to a second voltage signal. The level shifter comprises a comparison circuit, a delay circuit, and a selection circuit.
Flexible input/output transceiver
An i/o transceiver includes a driver with a feedback circuit having a mode select signal input, a serial data signal input, and a driver output signal input. The feedback circuit can provide a feedback control signal that is coupled to a pre-driver circuit.
Word line selection circuit and row decoder
A first exemplary aspect of the present invention is a word line selection circuit where address decode signals composed of a power supply voltage and a first voltage lower than a ground voltage are input, and that a word line selection signal composed of the first voltage and a second voltage higher than the power supply voltage is output not via a level shift circuit according to the address decode signals.. .
High-voltage multi-level shifter for ultrasound applications and transmit/receive channel for ultrasound applications using said level shifter
A multi-level shifter includes a first branch having first and second transistors coupled between a higher voltage terminal and a lower voltage terminal. The multi-level shifter comprises a second branch, in parallel with the first branch, having: a third transistor, coupled between said higher voltage reference terminal and an output node, a fourth switching transistor coupled between said output node and said lower voltage terminal.
Boost-type switching regulator and semiconductor device for boost-type switching regulator
A boost-type switching regulator includes an inductor; a rectifying element; a capacitor; a switching element; an output terminal; a detection voltage generating unit; an output voltage controlling unit; and a detection voltage level shifting unit. The detection voltage generating unit generates a detection voltage according to an output voltage.
Charge and discharge signal circuit and dc-dc converter
A charge and discharge signal circuit includes: high side transistors connected in series; low side transistors connected in series; high side drive circuits; low side drive circuits; and a drive signal generation circuit, wherein each drive circuit includes: a high side level shifter; a high side capacitor switch string of a capacitor and a switch element connected in series, being connected in parallel with the high side transistor; and a high side drive part, to which an output of the high side level shifter is supplied, and each of the low side drive circuits includes: a low side level shifter; a low side capacitor switch string of a capacitor and a switch element connected in series, being connected in parallel with the low side transistor; and a low side drive part, to which an output of the low side level shifter is supplied.. .
Shiftable memory employing ring registers
Shiftable memory employs ring registers to shift a contiguous subset of data words stored in the ring registers within the shiftable memory. A shiftable memory includes a memory having built-in word-level shifting capability.
Low side nmos protection circuit for battery pack application
An electric circuit comprising means for communicating with an external device coupled to means for measuring the charge condition of an external battery. In some embodiments, the circuit comprises at least one level shifter for changing the reference voltage of communication signals.
Signal processing device
A level shifter converting a binary signal having a first potential and a second potential into a signal having the first potential and a third potential, and a signal processing circuit using the level shifter are provided. The first potential is higher than the second potential.
Voltage level shifter circuit, system, and high speed applications
A level shifting circuit includes a first inverter including a pair of transistors of opposite conductivity type, the first inverter adapted to receive an input signal in a first voltage domain and further including at least one additional transistor driven by a voltage in a second voltage domain. A second inverter is coupled in series with the first inverter and operable to generate an output signal in the second voltage domain.
Capacitive level shifter devices, methods and systems
Systems and methods of use relate to a circuit that is designed to detect the state of two control signals, wherein one control signal indicates an on state for the gate driver and the other control signal indicates an off state for the gate driver. The circuit responds to each of the control signals by controlling the gate driver so that it drives an output either high or low.