|| List of recent Level Shift-related patents
|High-speed memory write driver circuit with voltage level shifting features|
Various aspects of a fast, energy efficient write driver capable of efficient operation in a dual-voltage domain memory architecture are provided herein. Specifically, various aspects of the write driver described herein combine a high speed driver with voltage level shifting capabilities that may be implemented efficiently in reducing use of silicon area while using lower power.
|Electronic power converter with ground referenced lossless current sensing|
A current sensing circuit for an electronic power converter having an inductor that is not referenced to ground is configured to provide an output signal that is referenced to ground and is proportional to the current flow between the inductor and a load in an electrical power system. The current sensing circuit includes outputs associated with a voltage of the inductor, a current source circuit, a current steering circuit responsive to the voltage outputs and a level shifting circuit..
|Level shifting circuit with adaptive feedback|
An amplifier has a first pull-up path coupled between a voltage supply node and an output node, and a pull-down path coupled between the output node and a ground supply node. A second pull-up path is coupled between the voltage supply node and the output node.
|Low voltage level shifter for low power applications|
A level shifter circuit for low power applications that can shift the level of a digital signal that is below the threshold voltage of output transistors. The level shifter uses core transistors in the input stage and includes an intermediate stage that limits the voltage applied to the drain of the core transistors.
|Voltage level shifter with a low-latency voltage boost circuit|
Certain aspects of the present disclosure provide a voltage level shifting circuit employing a low latency, ac-coupled voltage boost circuit, as well as other circuits and apparatus incorporating such a level shifting circuit. Such level shifting circuits provide significantly lower latency compared to conventional level shifters (e.g., latency reduced by at least a factor of two).
|Apparatuses and method for shifting a voltage level|
Apparatuses and methods, such as those for shifting a voltage level are disclosed. An example apparatus includes a level shifter configured to provide output signals based on a logical value of an input signal, where the level shifter is precharged to a precharge voltage prior to providing the output signals.
An ic generally comprises enable pin, ground pin, input pin, output pin, load switch, control circuitry, and level shifter. Load switch is coupled between input pin and output pin and receives a negative voltage through the input pin.
|Circuit and method for improving noise immunity of a single-end level shifter in a floating gate driver|
A floating gate driver uses a single-end level shifter to translate a set signal and a reset signal induced by a rising edge and a falling edge of a switch signal to a common output terminal to generate an output voltage for a bistable circuit to generate a level shifted switch signal. Under control of a well transient detect signal asserted by detecting noise in the output voltage, a masking circuit between the single-end level shifter and the bistable circuit masks noise in the output voltage.
|Integrated level shifting latch circuit and method of operation of such a latch circuit|
An integrated level shifting latch circuit receives an input signal in a first voltage domain and generates an output signal in a second voltage domain. Data retention circuitry operates in a transparent phase where a data value is subjected to a level shifting function and is written into the data retention circuitry dependent on the input signal.
|Fast voltage level shifter circuit|
A voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a field-effect transistor (fet) switch with a gate attached to the input terminal, a drain attached to the output terminal and a source attached to a current changing mechanism.
|Combinatorial circuit and method of operation of such a combinatorial circuit|
An integrated level shifting combinatorial circuit receives a plurality of input signals in a first voltage domain and performs a combinatorial operation to generate an output signal in a second voltage domain. The circuit includes combinatorial circuitry includes first and second combinatorial circuit portions operating in respective first and second voltage domains.
|Methods and systems for interconnecting host and expansion devices within system-in-package (sip) solutions|
Methods and systems are disclosed for interconnecting die-to-die-port (dtdp) host devices and dtdp expansion devices for combined system-in-package (sip) solutions. Interconnect circuitry having a plurality of ports is configured to provide communication from the host device to the expansion device so that the expansion device appears to be resident on the host device.
|Level shift circuit and driving method thereof|
A level shift circuit includes an input end, a decoding circuit, a control circuit, and a plurality of output circuits. The input end is configured to receive a coded signal string including a starting code, a setting code, a clock standard signal and an ending code.
|Voltage level conversion circuits and display devices including the same|
A voltage level conversion circuit includes a voltage switch circuit and a level shift circuit. The voltage switch circuit is configured to sequentially output an intermediate voltage and a conversion voltage in response to a switch signal.
|Level shift circuit|
There is provided a level shift circuit free from malfunction. The level shift circuit converts a signal of a first power supply voltage of a first supply terminal, which is supplied to an input terminal, into a signal of a second power supply voltage of a second supply terminal and outputs the converted signal to an output terminal.
|Balanced level shifter with wide operation range|
Embodiments of an apparatus are disclosed that may allow for the translation of signals from one power domain to another with well-balanced rise and fall times over a wide operational range. The apparatus may include an input buffer, a voltage shift circuit, and output circuit, and an output driver.
|Integrated circuit testing with power collapsed|
Provided are apparatus and methods for testing an integrated circuit. In an exemplary method for testing an integrated circuit, a test controller and a power manager are integrated into a main power domain of the integrated circuit.
|Dynamic power adjustment of level shift for noise rejection in capacitance touch system|
A dynamic power adjustment circuit for noise rejection in a capacitance touch system includes: a power source configured to generate a fixed power voltage v, a voltage adjustment circuit electrically connected to the power source, and a noise detection circuit electrically connected to the voltage adjustment circuit. The voltage adjustment circuit is configured to generate a plurality of different voltage signals vh(1), vh(2), .
|Charge/discharge control circuit and battery device|
The level shifter circuit includes: a first transistor including a gate connected to an input terminal of the level shifter circuit and a source connected to a first power supply terminal; a first resistor including one terminal connected to the input terminal of the level shifter circuit; a second transistor including a gate connected to another terminal of the first resistor, a drain connected to a drain of the first transistor, and a source connected to a terminal for inputting the voltage subjected to the level conversion; and a third transistor including a gate and a drain connected to the another terminal of the first resistor, and a source connected to the terminal for inputting the voltage subjected to the level conversion. Further, the battery device includes the charge/discharge control circuit..
A display device includes a display panel including gate lines, data lines, and pixels connected to the gate line and the data lines, a gate driver driving the gate lines, a level shifter applying a gate clock signal to the gate driver, a data driver driving the data lines, a timing controller generating control signals to control the level shifter, the gate driver, and the data driver, and a backlight unit providing light to the display panel. The level shifter sets a voltage level of a gate-on voltage of the gate clock signal to a voltage level of a first gate-on voltage or a voltage level of a second gate-on voltage higher than the first gate-on voltage in response to a gate-on control signal..
|Systems and methods of level shifting for voltage drivers|
System and method for controlling one or more switches. The system includes a first converting circuit, a second converting circuit, and a signal processing component.
|Level shifter circuit optimized for metastability resolution and integrated level shifter and metastability resolution circuit|
A level shifter and integrated level shifter and metastability resolution flop circuit are disclosed. A circuit includes a generation circuit, in a first voltage domain, coupled to receive a logic signal via a single-ended input and configured to generate true and complementary values of the logic signal.
|Gate driver and liquid crystal display device|
The present invention provides a gate driver and liquid crystal display device. The gate driver, for driving scan lines of liquid crystal display device, includes: an input buffer, for receiving clock signal, first frame start pulse signal and second frame start pulse signal; shift register, including n+2 triggers, connected serially from the first trigger to the n+1st trigger, a clock signal input terminal of the n+2nd trigger being connected to the clock signal transmission line, wherein n being a natural number, when the first frame start pulse signal starting, the shift register shifting vertical synchronization signal and outputting n+1 outputs of shift registers based on the clock signal; a voltage level shifter, for shifting the output of the shift register to predefined voltage level and outputting shifted result serially; and an output buffer, for applying output of voltage level shifter to scan lines..
An object of one embodiment of the present invention to provide a latch circuit includes a level shifter and a buffer in which transistors each including a channel region formed in an oxide semiconductor film are connected in series. Thus, data can be held in the latch circuit even when power is not supplied..
|Level shifter device|
A level shifter includes a first terminal configured to receive a first supply voltage, a second terminal configured to receive a second supply voltage, an input terminal configured to receive an input signal and an output terminal. The level shifter is configured to shift the input signal from the level of the first supply voltage to the level of the second supply voltage in outputting the output signal.
|Overvoltage protection circuit|
Apparatus and methods for generating an overvoltage signal from a bias winding signal of a power converter transformer are disclosed. In one example, an overvoltage protection circuit may include a current augmentation circuit and a detection circuit.
|High voltage semiconductor device|
An n well region and an n−region surrounding the n well region are provided in the surface layer of a p−silicon substrate. The n−region includes breakdown voltage regions in which high voltage mosfets are disposed.
|Amplifier circuits and methods of amplifying an input signal|
A method of operating an amplifier circuit having a pre-charge phase and a sample/conversion phase includes, during a pre-charge phase, charging first and second capacitors to first and second bias voltages. The first capacitor is coupled to a first input of an amplifier circuit, which has a second input and an output.
|Voltage level shifter|
A circuit includes a first capacitive device and a first latch. The first capacitive device includes a first end configured to receive a first input signal and a second end coupled with the first latch.
|Low power level shifter with output swing control|
A level shifter comprising a first driver transistor for receiving an input signal. A gate-controlled transistor coupled to the first driver transistor.
|Sense amplifier including a level shifter|
An apparatus includes a sense amplifier that has a sense amplifier differential output. The sense amplifier may be in a first power domain.