|| List of recent Level Shift-related patents
| Level shifter utilizing a capacitive isolation barrier|
According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit through a capacitive isolation barrier.
International Rectifier Corporation
| Communication between voltage domains|
An integrated circuit 6 including a first voltage domain 4 incorporates real time clock circuitry 12 that communicates via communication circuitry 18 with processing circuitry 16 contained within a second voltage domain. The communication circuitry 18 includes first parallel-to-serial conversion circuitry 24 located within the first voltage domain 4, level shifting circuitry 32 for passing serial signals between the voltage domains and second parallel-to-serial circuitry 26 located in the second voltage domain..
| Level shifter with static precharge circuit|
A level shifter includes a static precharge circuit. During a precharge phase, two nodes of the level shifter are precharged to a voltage at or near a reference voltage.
Freescale Semiconductor, Inc.
|Level shift circuit with automatic timing control of charging transistors, and driver circuit having the same|
A level shift circuit includes first and second nmos transistors that are coupled between a first supply terminal, and first and second output nodes, respectively, and have respective control terminals receiving input signals of a low amplitude, third and fourth pmos transistors which are coupled between a second supply terminal, and the first and second output nodes outputting signals of high amplitude, respectively, a fifth pmos transistor which is coupled between a gate of the third pmos transistor and the second output node, and has a gate coupled to the first output node, a sixth pmos transistor which is coupled between a gate of the fourth pmos transistor and the first output node, and has a gate coupled to the second output node, and first and second load elements which are coupled between the second supply terminal and the gates of the third and fourth pmos transistors, respectively.. .
Renesas Electronics Corporation
A level shifter includes high breakdown voltage first and second pmos transistors, high breakdown voltage first and second depression nmos transistors having gates respectively supplied with first and second control signals, low breakdown voltage first and second nmos transistors having gates respectively supplied with third and fourth control signals, and a timing control unit that generates the first control signal and the third control signal different from the first control signal corresponding to an inverted signal of an input signal, and generates the second control signal and the fourth control signal different from the second control signal corresponding to a non-inverted signal of the input signal.. .
Renesas Electronics Corporation
|Source driver and method to reduce peak current therein|
A source driver and a method to reduce peak current of the source driver are provided. The source driver includes a latch circuit, a level shifter and a digital-to-analog converter (dac) circuit.
Novatek Microelectronics Corp.
A level shifter includes an input stage circuit, a latch circuit and a transient speed-up circuit. The input stage circuit receives an input signal.
Richtek Technology Corp
|Level shifter circuit, scanning circuit, display device and electronic equipment|
A level shifter circuit, wherein a first and a second transistor circuit are connected serially, a third and a fourth transistor circuit are connected serially; a first input voltage is applied to the second transistor circuit and a second input voltage is applied to the fourth transistor circuit; an input terminal of the first transistor circuit is connected to an output terminal of the third and the fourth transistor circuits, and an input terminal of the third transistor circuit is connected to an output terminal of the first and the second transistor circuits; two transistor circuits of at least one side of two transistor circuits of a first fixed power source side and two transistor circuits of a second fixed power source side are configured of double gate transistors; and the level shifter circuit has a switch element for applying a voltage to a common connection node.. .
|Semiconductor device and electronic appliance|
The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output.
Semiconductor Energy Laboratory Co., Ltd.
|Semiconductor driving device and semiconductor device|
A semiconductor driving device includes a negative surge detection circuit and a level shifter circuit. The negative surge detection circuit detects whether the negative surge occurs at a connection point between a p-side sw element and n-side sw element.
Mitsubishi Electric Corporation
Communication circuit apparatus and transceiver having the same
A communication circuit apparatus includes: multiple level shift circuits, each of which receives an input signal corresponding to a respective communication bus; an activation comparator for generating an activation signal when the input signal is input into one of the level shift circuits, and a level of the input signal exceeds a predetermined threshold; multiple input current voltage conversion circuits, each of which is arranged together with a respective level shift circuit, converts the input signal to a voltage signal, and outputs the voltage signal as an identification signal; and an identification circuit for identifying one of the communication busses based on the identification signal, which is output from one of the input current voltage conversion circuits. The one of the communication busses corresponds to the one of the level shift circuits, in which the input signal is input..
High speed level shifter with amplitude servo loop
A high speed level shifter interfaces a high speed dac to the digital information that the dac processes. The level shifter may convert cmos level digital representations to, for example, cml level digital representations for processing by the dac.
Methods and circuits for dynamically scaling dram power and performance
A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface.
Device to avoid attacks from electro-sensitive animals
A system for protecting user's body from the attacks of electro-sensitive animals is provided. The system includes a frequency generator, a modulator, a controller, a level shifter, plurality of electrodes and a power source to provide power to the controller.
R2z Innovations, Inc.
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device comprises a memory cell array, a staircase voltage generator, and a decode and level shift circuit. The memory cell array comprises a plurality of memory cells and a plurality of bit lines coupled to the plurality of memory cells.
Elite Semiconductor Memory Technology Inc.
Semiconductor device and power conversion device using the same
In a semiconductor device such as a three-phase one-chip gate driver ic, hvnmoss configuring two set and reset level shift circuits are disposed on non-opposed surfaces, and it is thereby possible to reduce the amount of electrons flowing into drains of hvnmoss of another phase due to a negative voltage surge. Also, distances from an opposed surface on the opposite side to the respective drains of the hvnmoss configuring the two set and reset level shift circuits are made equal to or more than 150 μm, and it is thereby possible to prevent a malfunction of a high side driver circuit of another phase to which no negative surge is applied..
Fuji Electric Co., Ltd.
Driver and driving control power converter
A driver and a driving control method for a power converter are provided. The driver includes a level shift circuit, a negative voltage generator and a first pmos transistor.
Upi Semiconductor Corp.
Methods and systems to selectively boost an operating voltage of, and controls to an 8t bit-cell array and/or other logic blocks
Methods and systems to provide a multi-vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-vcc environment may be implemented to isolate a vmin-limiting logic block from a single-vcc environment, such as to reduce vmin and/or improve energy efficiency in the single-vcc environment.
Touch detection method and touch detection apparatus having built up linearity
A touch detection apparatus includes a sensor pad to output a signal based on a touch state in response to an alternating voltage in a floating state after being charged, an operational amplifier including a first input connected to an output of the sensor pad and a second input to receive the alternating voltage, a level shift detection unit to detect a touch signal based on a difference between a voltage variation at an output end of the operational amplifier caused by the alternating voltage and a voltage variation at the output end of the operational amplifier caused by occurrence of a touch, and a switching unit including a first switch to control an electric potential between a first input and the output end of the operational amplifier and a second switch to connect or not the sensor pad and the first input of the operational amplifier.. .
Crucialtec Co., Ltd.
Voltage level shift circuit for multiple voltage integrated circuits
A voltage level shift circuit comprises a first pair of transistors and a second pair of transistors. A first transistor of the second pair of transistors is coupled with an input signal terminal.
Taiwan Semiconductor Manufacturing Company, Ltd.
Semiconductor device having level shift circuit
Disclosed herein is a device includes; a level conversion circuit coupled to first and third power supply lines, receiving a first signal and an inverted signal of the first signal each having an amplitude between first and second potentials, and output ting a second signal having an amplitude between first and third potentials; a delay circuit coupled to the first and second power supply lines, and output ting a third signal delayed from the first signal; and an output circuit including first and second transistors coupled in series between the first and third power supply lines, the first transistor having a control electrode supplied with the second signal, and the second transistor having a control electrode supplied with the third signal.. .
Micron Technology, Inc.
Overcurrent protection method, circuit and integrated circuit
Disclosed is an overcurrent protection method and circuit and an integrated circuit. The overcurrent protection circuit includes an output circuit, an overcurrent sampling circuit and an overcurrent protection loop circuit.
Fairchild Semiconductor Corporation
Apparatus and detecting touch, capable of reducing parasitic capacitance
A touch detection apparatus includes at least one sensor pad outputting a signal according to a touch state in response to an alternating voltage in a floating state after charging with an electric charge, an additional electrostatic capacitive unit electrically connected to an output terminal of the sensor pad and having a capacitance corresponding to a parasitic capacitance of the sensor pad, an electrical charging/discharging unit charging or discharging the additional electrostatic capacitive unit to make the additional electrostatic capacitive unit have an electric charge variation the same as that in the parasitic capacitance caused by the alternation of the alternating voltage but an opposite polarity, and a level shift detection unit detecting a touch signal based on a difference between voltage variations in the sensor pad caused by the alternating voltage during non-touch and caused by the alternating voltage during a touch.. .
Crucialtec Co., Ltd.
Multi power supply type level shifter
There is provided a multi power supply type level shifter. The provided multi power supply type level shifter includes a first level shifter and a second level shifter in a two-stage architecture so as to selectively receive first to third power supplies and change a signal level, even when the first to third power supplies are applied in a different sequence from a normal power-on sequence.
Magnachip Semiconductor, Ltd.
Systems and methods for providing high voltage to memory devices
Apparatus, systems, and methods for providing high voltage to memory devices are provided. One apparatus includes a low voltage input and a two-rail level shifting.
Cypress Semiconductor Corporation
Timing controller for liquid crystal panel and timing control method thereof
A timing controller for a liquid crystal panel and a timing control method thereof are provided. The timing controller includes a timing control unit for analyzing an input signal to generate a system state transition voltage (stv) signal and a base stv signal, and the timing control unit outputs a base trigger signal and a switch trigger signal having asynchronous frame rates to a select unit at the same time.
Chunghwa Picture Tubes, Ltd.
Level conversion circuit and converting voltage level thereof
A level conversion circuit including a first level shifter and a second level shifter is provided. The first level shifter converts a first control voltage into a second control voltage during a voltage conversion period.
Novatek Microelectronics Corp.
Semiconductor integrated circuit and information processing apparatus
According to an embodiment, a semiconductor integrated circuit includes a regulator, a level shifter and a switch circuit. The regulator converts an input voltage that is a difference in potential between a first terminal and a third terminal into an output voltage that is a difference in potential between a second terminal and the third terminal.
Compact level shifter
Embodiments of the present invention provide a device for level shifting an input signal. The device includes an output buffer that has: an output node, a p-fet coupled to a high reference voltage, and an n-fet coupled to a low reference voltage.
Semiconductor integrated circuit device
A semiconductor integrated circuit device comprises i/o cells arranged around a core region. Each of the i/o cells comprises a level shifter circuit, an i/o logic circuit, and an i/o buffer circuit.
Cost effective low pin/ball count level-shifter for lcd bias applications supporting charge sharing of gate lines with perfect waveform matching
A level shifter circuit has a plurality of channels for providing signals to a capacitive load and has circuits for sharing charge stored in the capacitive load between the channels. A first pair of channel clock generating circuits are coupled respectively to a first pair of channels.
A display apparatus is provided which includes a display panel; a gate driver configured to drive a plurality of gate lines, a data driver configured to drive a plurality of data lines, a level shifter configured to generate a gate on voltage corresponding to an atmospheric temperature and to generate a gate clock signal, the gate on voltage becoming higher depending on a decrease in an atmospheric temperature, and a timing controller configured to control the gate driver and the data driver and to generate agate pulse signal having a pulse width corresponding to a voltage level of the gate on voltage.. .
Level shift circuit
A level shift circuit of an embodiment includes first and second mosfets using signals with phases same as and opposite to the phase of an input signal as gate inputs; first and second resistance elements, each having one end connected to a shift level power terminal that supplies high-level output voltage of a level-shifted output signal, and each having the other end connected to a corresponding drain of the first and second mosfets; a comparator having a pair of differential input terminals, individually connected to respective drains of the first and second mosfets; and a current control circuit that controls an amount of first current flowing through the first mosfet via the first resistance element and an amount of second current flowing through the second mosfet via the second resistance element in synchronization with a rising and a falling of a signal level of the input signal.. .
Systems and methods for data receipt from devices of disparate types
Systems and methods are provided for a receiver device for receiving data signals from devices of disparate types. An amplifier is configured to receive a voltage reference signal and a data signal, the data signal being received from a device, the amplifier being configured to output an output signal based on a comparison of the data signal to the voltage reference signal.