This page is updated frequently with new Level Shift-related patent applications.
|Level shifting circuit and the same|
A level shifting circuit includes a transistor output unit that receives a first power supply signal and convert the first power supply signal to a second power supply signal having a different level from the first power supply signal and a current provision unit that provides a current to an output terminal of the transistor output unit when the first power supply signal of the transistor output unit is inputted to shorten a prolonged portion of the second power supply signal. Therefore, the level shifting circuit may provide an additional current to the output terminal of the transistor output unit to shorten a prolonged portion of the output voltage..
Magnachip Semiconductor, Ltd.
|High voltage switching circuitry for a cross-point array|
A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal.
Unity Semiconductor Corporation
|Level shift circuit|
The present invention provides a level-shift circuit that can suppress the malfunction caused by the noise due to the on/off of a level-shift transistor and the dv/dt noise due to external noise. The present invention provides a level-shift circuit for transmitting a signal from a primary potential side to a secondary potential side, comprising: a first serial circuit a first resistance including serially-connected to a first switching element; a second serial circuit including a second resistance serially-connected to a second switching element; a latch malfunction protection circuit for which the respective output terminals of the first and second serial circuits are connected to an input terminal; a latch circuit for receiving a signal outputted from the latch malfunction protection circuit; and a capacitor connected between drain terminals of the first resistance and the first switching element and between drain terminals of the second resistance and the second switching element..
Fuji Electric Co., Ltd.
|Level shift circuit|
An input part is supplied with a low voltage from a low voltage power supply line. A level shift part and an output part are supplied with a high voltage from a high voltage power supply line.
|Voltage level shifter, and embedded nonvolatile memory and system using the same|
A voltage level shifter may include a first input unit, a second input unit, a first mirror unit, a second mirror unit, and a clamping block. The first and second input units may receive a first input signal and a second input signal, respectively, and form current paths of a negative output node and a positive output node.
Sk Hynix Inc.
|Circuits for driving data lines|
A circuit includes: a first data line; a second data line; a write driver including first and second transistors; a first switch connected in series with the first transistor to form a first series-connected pair; a second switch in series with the second transistor to form a second series-connected pair; and a level shifter which includes the first and second transistors. The first series-connected pair is coupled between a first voltage node and the first data line.
Taiwan Semiconductor Manufacturing Company, Ltd.
A data communications receiver including a receiver coil, a first amplification stage coupled to the receiver coil, the first amplification circuitry to differentially amplify at least part of signal received by the receiver coil relative to a threshold, a second amplification stage coupled to receive the differentially amplified signal from the first amplification stage, the second amplification stage comprising a current mirror, and hysteretic level shifting circuitry to shift a level of part of the signal received by the receiver coil, the threshold or part of the signal received by the receiver coil and the threshold such that, in response to the at least part of the signal received by the receiver coil having crossed the threshold, a threshold crossing in the other direction is delayed.. .
Power Integrations Switzerland Gmbh
|Level shifter and approach therefor|
Aspects of the disclosure are directed to communications between respective power domains (circuitry) that may operate in a stacked arrangement in which the each domain operates over a different voltage range. A first circuit provides differential outputs that vary between first and second voltage levels, based on transitions of an input signal received from a first one of the power domains.
|Bipolar gate driver|
According to one aspect, embodiments of the invention provide a gate driver comprising a level shifter circuit configured to be coupled to a controller, to receive control signals from the controller, each control signal having a voltage with respect to a control ground, and to redefine the voltage of each control signal with respect to a chip ground to generate redefined control signals, a gate driver chip coupled to the level shifter circuit and configured to be coupled to at least one semiconductor device, the gate driver chip further configured to provide bipolar control signals to the at least one semiconductor device based on the redefined control signals, and at least one power source configured to provide at least one positive supply voltage to the gate driver chip and at least one negative supply voltage to the gate driver chip and to the chip ground.. .
Schneider Electric It Corporation
|Voltage level shifter|
A voltage level shifter includes: in stages a pull-down driving unit suitable for receiving an input signal swinging between a ground voltage and a first supply voltage, and pull-down driving an output node to the ground voltage according to a voltage level of the input signal, wherein an output signal outputted through the output node swings between the ground voltage level and a second supply voltage level higher than the first supply voltage; a pull-up driving unit suitable for pull-up driving the output node, to the second supply voltage according to the voltage level of the input signal; a bias generation unit suitable for generating a bias voltage fixed to a preset voltage level; and a bias operation unit coupled between the output node and the pull-down driving unit, and suitable for lowering a voltage level of the output node in stages based on the bias voltage to supply the lowered voltage to the pull-down driving unit when a pull-down operation is performed by the pull-down driving unit.. .
Sk Hynix Inc.
System and hierarchical power verification
A hierarchical power verification system and method creates abstract models of power behavior of modules that it successfully verifies. The abstract models simplify the module definition by omitting internal module details but provide sufficient information for power verification of higher level modules that incorporate this abstracted module.
Driver circuit for memory devices
There is described a driver circuit (100) for providing biasing voltages to a flash memory device, the driver circuit comprising (a) a level shifter latch (110) comprising a first latch input terminal (111), a first latch control terminal (112), a latch voltage supply terminal (113), a first latch output terminal (114), and a second latch output terminal (115), wherein the level shifter latch (110) is adapted to provide, in dependency of a voltage at the first latch input terminal (111), one of a first voltage and a second voltage at the first latch output terminal (114) and the other one of the first voltage and the second voltage at the second latch output terminal (115), wherein the first voltage is dependent on a voltage applied to the latch voltage supply terminal (113) and the second voltage is dependent on a voltage applied to the first latch control terminal (112), (b) a first output stage (120) comprising a first switching element (n11, n12), a second switching element (n13), a first voltage supply terminal (122), a second voltage supply terminal (124), and a first biasing voltage output terminal (126), wherein the first switching element (n11, n12) is adapted to connect the first biasing voltage output terminal (126) to the first voltage supply terminal (122) in dependency of the voltage at the first latch output terminal (114), and wherein the second switching element (n13) is adapted to connect the first biasing voltage output terminal (126) to the second voltage supply terminal (124) in dependency of the voltage at the second latch output terminal (115), and (c) a second output stage (130) comprising a third switching element (n21), a fourth switching element (n22), a third voltage supply terminal (132), a fourth voltage supply terminal (134), and a second biasing voltage output terminal (136), wherein the third switching element (n21) is adapted to connect the second biasing voltage output terminal (136) to the third voltage supply terminal (132) in dependency of the voltage at the first latch output terminal (114), and wherein the fourth switching element (n22) is adapted to connect the second biasing voltage output terminal (136) to the fourth voltage supply terminal (134) in dependency of the voltage at the second latch output terminal (115).there is also described a memory system and a method of operating the driver circuit.. .
A system for a feedback transimpedance amplifier with sub-40 khz low-frequency cutoff is disclosed and may include amplifying electrical signals received via coupling capacitors utilizing a transimpedance amplifier (tia) having feedback paths comprising source followers and feedback resistors. The feedback paths may be coupled prior to the coupling capacitors at inputs of the tia.
Liquid crystal display panel and liquid crystal display device
The present invention provides a liquid crystal display panel. The liquid crystal display panel includes drive circuits, data lines for transmitting the data signals, scan lines, and pixel units.
Shenzhen China Star Optoelectronics Technology Co. Ltd
Gate driver circuit, its driving method, array substrate and display device
The present disclosure provides a gate driver circuit including at least one set of clock signal lines and multiple levels of shift registers arranged in a cascaded manner. Each set of the clock signal lines includes two clock signal lines.
Boe Technology Group Co., Ltd.
Level shifter and source driver integrated circuit
The present embodiments relate to an advanced level shifter having a circuit structure which enables miniaturization and high performance, a source driver integrated circuit and a gate driver integrated circuit, and a display device which include the same.. .
Silicon Works Co., Ltd.
Voltage level shifters employing preconditioning circuits, and related systems and methods
Voltage level shifters employing preconditioning circuits are disclosed. Related systems and methods are also disclosed.
Optical reception circuit
An optical reception circuit includes a first photodetector, a first transimpedance amplifier, a level shift circuit, a second photodetector, a second transimpedance amplifier, a peak hold circuit, and a comparator. The first transimpedance amplifier converts a first light current from the first photodetector to a first voltage.
Panasonic Intellectual Property Management Co., Lt
Low power buffer with gain boost
The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal.
Dynamic high voltage driver with adjustable clamped output level
A driver circuit and associated techniques include managing voltage driving an electronic device. An input signal having a first voltage level is received.
International Business Machines Corporation
Circuit and generating clock-signals
The present disclosure provides circuits and methods for generating clock-signals. An exemplary clock-signal generation circuit includes a delay buffer unit; an inverter unit coupled to the delay buffer unit; a first delay unit having a first nand boolean calculation sub unit, a first sub delay unit and a first level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a first delayed clock-signal; and a second delay unit having a second nand boolean calculation sub unit, a second sub delay unit and a second level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a second delayed clock signal..
Semiconductor Manufacturing International (shanghai) Corporation
High voltage level shifter in ultra low power supply memory application
A high voltage level sifter includes a first high-voltage p-channel metal oxide semiconductor (hvpmos) transistor, a second hvpmos transistor, a discharge transistor having a first native high-voltage n-channel metal oxide semiconductor (hvnmos) transistor and a first low-voltage n-channel metal oxide semiconductor (lvnmos) transistor connected in series, and an avalanche transistor having a second hvnmos transistor and a second lvnmos transistor connected in series.. .
Semiconductor Manufacturing International (shanghai) Corporation
Pulsed level shift and inverter circuits for gan devices
Gan-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side gan device communicates through one or more level shift circuits with a high side gan device.
Navitas Semiconductor Inc.