|| List of recent Level Shift-related patents
| Semiconductor integrated circuit and information processing apparatus|
According to an embodiment, a semiconductor integrated circuit includes a regulator, a level shifter and a switch circuit. The regulator converts an input voltage that is a difference in potential between a first terminal and a third terminal into an output voltage that is a difference in potential between a second terminal and the third terminal.
|Compact level shifter|
Embodiments of the present invention provide a device for level shifting an input signal. The device includes an output buffer that has: an output node, a p-fet coupled to a high reference voltage, and an n-fet coupled to a low reference voltage.
|Semiconductor integrated circuit device|
A semiconductor integrated circuit device comprises i/o cells arranged around a core region. Each of the i/o cells comprises a level shifter circuit, an i/o logic circuit, and an i/o buffer circuit.
|Cost effective low pin/ball count level-shifter for lcd bias applications supporting charge sharing of gate lines with perfect waveform matching|
A level shifter circuit has a plurality of channels for providing signals to a capacitive load and has circuits for sharing charge stored in the capacitive load between the channels. A first pair of channel clock generating circuits are coupled respectively to a first pair of channels.
A display apparatus is provided which includes a display panel; a gate driver configured to drive a plurality of gate lines, a data driver configured to drive a plurality of data lines, a level shifter configured to generate a gate on voltage corresponding to an atmospheric temperature and to generate a gate clock signal, the gate on voltage becoming higher depending on a decrease in an atmospheric temperature, and a timing controller configured to control the gate driver and the data driver and to generate agate pulse signal having a pulse width corresponding to a voltage level of the gate on voltage.. .
|Level shift circuit|
A level shift circuit of an embodiment includes first and second mosfets using signals with phases same as and opposite to the phase of an input signal as gate inputs; first and second resistance elements, each having one end connected to a shift level power terminal that supplies high-level output voltage of a level-shifted output signal, and each having the other end connected to a corresponding drain of the first and second mosfets; a comparator having a pair of differential input terminals, individually connected to respective drains of the first and second mosfets; and a current control circuit that controls an amount of first current flowing through the first mosfet via the first resistance element and an amount of second current flowing through the second mosfet via the second resistance element in synchronization with a rising and a falling of a signal level of the input signal.. .
|Systems and methods for data receipt from devices of disparate types|
Systems and methods are provided for a receiver device for receiving data signals from devices of disparate types. An amplifier is configured to receive a voltage reference signal and a data signal, the data signal being received from a device, the amplifier being configured to output an output signal based on a comparison of the data signal to the voltage reference signal.
|Dynamic level shifter circuit|
A level shifter does not require any dc (standby) current consumption and has a fast operation with low propagation delay. The level shifting from input to output voltage ranges is performed by a pair of level shifting capacitors.
|Voltage level shifter and systems implementing the same|
According to the inventive concepts disclosed herein, a level shifter can include an input node in a first voltage domain and an output node in a second voltage domain, higher than the first voltage domain. The input node receives an input signal in the first, lower-voltage domain, and the output node is configured to output a representation of the input signal in the second, higher-voltage domain.
In aspects of the invention, a semiconductor device can include one level shift circuit that outputs a low-side input signal as a high-side signal upon raising a signal level, a pulse modulation circuit that operates in a low-side region, generates a data symbol constituted by or more bits and representing a set signal or a reset signal, where bit is defined as a combination of codes forming a pair. The pulse generation circuit can output the generated data symbol as an input signal of the level shift circuit.
|Level shifter circuit and operation method thereof|
A level shifter transfers a first voltage signal to a second voltage signal. The level shifter comprises a comparison circuit, a delay circuit, and a selection circuit.
|Flexible input/output transceiver|
An i/o transceiver includes a driver with a feedback circuit having a mode select signal input, a serial data signal input, and a driver output signal input. The feedback circuit can provide a feedback control signal that is coupled to a pre-driver circuit.
|Word line selection circuit and row decoder|
A first exemplary aspect of the present invention is a word line selection circuit where address decode signals composed of a power supply voltage and a first voltage lower than a ground voltage are input, and that a word line selection signal composed of the first voltage and a second voltage higher than the power supply voltage is output not via a level shift circuit according to the address decode signals.. .
|High-voltage multi-level shifter for ultrasound applications and transmit/receive channel for ultrasound applications using said level shifter|
A multi-level shifter includes a first branch having first and second transistors coupled between a higher voltage terminal and a lower voltage terminal. The multi-level shifter comprises a second branch, in parallel with the first branch, having: a third transistor, coupled between said higher voltage reference terminal and an output node, a fourth switching transistor coupled between said output node and said lower voltage terminal.
|Boost-type switching regulator and semiconductor device for boost-type switching regulator|
A boost-type switching regulator includes an inductor; a rectifying element; a capacitor; a switching element; an output terminal; a detection voltage generating unit; an output voltage controlling unit; and a detection voltage level shifting unit. The detection voltage generating unit generates a detection voltage according to an output voltage.
|Charge and discharge signal circuit and dc-dc converter|
A charge and discharge signal circuit includes: high side transistors connected in series; low side transistors connected in series; high side drive circuits; low side drive circuits; and a drive signal generation circuit, wherein each drive circuit includes: a high side level shifter; a high side capacitor switch string of a capacitor and a switch element connected in series, being connected in parallel with the high side transistor; and a high side drive part, to which an output of the high side level shifter is supplied, and each of the low side drive circuits includes: a low side level shifter; a low side capacitor switch string of a capacitor and a switch element connected in series, being connected in parallel with the low side transistor; and a low side drive part, to which an output of the low side level shifter is supplied.. .
|Shiftable memory employing ring registers|
Shiftable memory employs ring registers to shift a contiguous subset of data words stored in the ring registers within the shiftable memory. A shiftable memory includes a memory having built-in word-level shifting capability.
|Low side nmos protection circuit for battery pack application|
An electric circuit comprising means for communicating with an external device coupled to means for measuring the charge condition of an external battery. In some embodiments, the circuit comprises at least one level shifter for changing the reference voltage of communication signals.
|Signal processing device|
A level shifter converting a binary signal having a first potential and a second potential into a signal having the first potential and a third potential, and a signal processing circuit using the level shifter are provided. The first potential is higher than the second potential.
|Voltage level shifter circuit, system, and method for high speed applications|
A level shifting circuit includes a first inverter including a pair of transistors of opposite conductivity type, the first inverter adapted to receive an input signal in a first voltage domain and further including at least one additional transistor driven by a voltage in a second voltage domain. A second inverter is coupled in series with the first inverter and operable to generate an output signal in the second voltage domain.
|Capacitive level shifter devices, methods and systems|
Systems and methods of use relate to a circuit that is designed to detect the state of two control signals, wherein one control signal indicates an on state for the gate driver and the other control signal indicates an off state for the gate driver. The circuit responds to each of the control signals by controlling the gate driver so that it drives an output either high or low.
|High-voltage heavy-current drive circuit applied in power factor corrector|
A high-voltage heavy-current drive circuit applied in a power factor corrector, comprising a current mirroring circuit (1), a level shift circuit (3), a high-voltage pre-modulation circuit (2), a dead time control circuit (4) and a heavy-current output stage (5); the heavy-current output stage adopts a darlington output stage structure to increase the maximum operating frequency of the drive circuit. The stabilized breakdown voltage characteristic of a voltage stabilizing diode is utilized to ensure the drive circuit operating within a safe voltage range.
|High performance class ab operational amplifier|
A class ab operational amplifier includes an input stage, an output stage and a level shifter stage to control the quiescent current of the output stage and to transfer the signal from the input stage to the output stage, and a control circuit of the level shifter stage. The control circuit includes a transistor differential pair having a differential input terminals and the differential voltage at the differential terminals of the differential pair controls the level shifter stage..
|Semiconductor switch circuit|
A semiconductor switch circuit includes a switch between an input node and an output node that connects nodes to each other according to a control signal and a level shifter outputting the control signal at a boosted level that is greater than a power supply voltage level. The semiconductor switch circuit also includes a booster circuit to output a boosted voltage at the boosted level higher than a power supply voltage level.
|Method and system for a feedback transimpedance amplifier with sub-40khz low-frequency cutoff|
A system for a feedback amplifier with sub-40khz low-frequency cutoff is disclosed and may include amplifying electrical signals received via coupling capacitors utilizing an amplifier having feedback paths comprising source followers and feedback resistors. Gate terminals of the source followers may be coupled to output terminals of the amplifier circuit.
|Solid-state imaging device and imaging apparatus|
A solid-state imaging device according to the present disclosure includes: a pixel unit in which unit pixels are arranged two-dimensionally, each of the unit pixels including: a photodiode which stores signal charges; a transfer transistor for transferring the signal charges stored in the photodiode; a charge detection unit which temporarily stores the transferred signal charges; and a reset transistor for resetting the signal charges stored in the charge detection unit; and a vertical scanning unit which drives the pixel unit, the vertical scanning unit including: a row selection unit; a level shift circuit for converting a level of an externally inputted power supply voltage; and a buffer circuit for buffering a voltage whose level has been converted by the level shift circuit, the level shift circuit including: a step-down level shift circuit; and a step-up level shift circuit isolated from the step-down level shift circuit by a well.. .
|Power converter with self-driven synchronous rectifier control circuitry|
An ac-dc power converter is provided with two pairs of self-driven synchronous rectifier switches in addition to, or in place of, diode bridge rectifiers for boosting efficiency and reducing cost. An ac sensing circuit is coupled to ac input terminals, and a dc level shifting circuit applies a dc offset to an ac input signal received via the sensing circuit.
|Powerline control interface|
A powerline control interface includes a powerline connection, a level shifter connected to the powerline connection, the level shifter having a zero crossing detector signal output, a capacitor connected to the powerline connection, an inductor connected to the powerline connection, and a receive signal inductively coupled to the inductor.. .
|Voltage level shifter|
The voltage level shifter includes a first voltage shift circuit, a second voltage shift circuit, a first switch circuit, a second switch circuit, a third switch circuit and a fourth switch circuit. The first voltage shift circuit receives a first input voltage, and the second voltage shift circuit receives a second voltage shift circuit.
|Level shifter for high density integrated circuits|
A level shifter for converting between voltages of a core voltage range to voltages within a larger i/o voltage range. The level shifter has interconnected transistors implemented as core devices operable within the core voltage range.
|Dual supply level shifter circuits|
A dual supply level shifter circuit includes a switching circuit and a set of level shifter circuits coupled to the switching circuit. The switching circuit includes a first set of coupled transistors, wherein the supply switching circuit is coupled to a first supply source that is configured to provide a first power supply voltage and is coupled to a second supply source that is configured to provide a second power supply voltage.
|Systems and method for level shifters|
A level shifter system includes an inverting portion, a non-inverting portion and a cross latch output component. The inverting portion is configured to receive an inverting input, a supply voltage and to generate an intermediary inverting output.
|Bias circuit for a switched capacitor level shifter|
A noise resistant switch control circuit is provided. The circuit includes a low pass filter configured to couple to a first terminal of a switch and a first voltage clamp coupled to the low pass filter.
|Cell balancing through a switched capacitor level shifter|
A battery management apparatus is provided. The battery management apparatus includes a switched capacitor level shifter having a first port and a second port.