|| List of recent Level Shift-related patents
| Multi-protocol combined receiver|
A receiver circuit configured to operate in a displayport (dp) mode and a high-definition multimedia interface (hdmi) mode. The receiver circuit includes: termination circuitry configured to receive a dp signal in the dp mode and an hdmi signal in the hdmi mode; and voltage common-mode (vcm) level shifter circuitry configured to operate as a pass-through for the dp signal in the dp mode and generate a converted hdmi signal from the hdmi signal in the hdmi mode..
| High voltage switch, nonvolatile memory device comprising same, and related operation|
A high voltage switch operates in response to a first drive voltage and a second drive voltage higher than the first drive voltage. The high voltage switch comprises a pmos transistor transmitting the second drive voltage to an output terminal according to a voltage applied to its gate, a first depletion mode transistor providing the second drive voltage to the pmos transistor according to an output signal fed back from the output terminal, a second depletion mode transistor receiving the second drive voltage through one end and providing a switching voltage to another end according to a switching control signal, and a level shifter providing the switching voltage to a gate of the pmos transistor according to an enable signal and a reverse enable signal..
Samsung Electronics Co., Ltd.
| Level shift circuit utilizing resistance in semiconductor substrate|
An apparatus such as a level shift circuit includes a first signal output device configured to output a first level shifting signal, a second signal output device configured to output a second level shifting signal, and first and second detector devices. The level shifting signals are to control an output switching element of a high potential side of an output device that includes a power source and a load.
Fuji Electric Co., Ltd.
|Wide range core supply compatible level shifter circuit|
A level shifter circuit is implemented with dual gate fully depleted silicon-on-insulator (fdsoi) technology. By enhancing the performance of the nmos and devices within the level shifting circuit, the vt of the dual gate fdsoi nmos transistors is lowered without a need for additional control circuitry.
|Level shift circuit and dc-dc converter for using the same|
A level shift circuit and a dc-dc buck converter controller for using the same are disclosed. The level shift circuit is capable of detecting a state of a converting circuit, and avoids a current leakage when determining that the converting circuit is operating under a light-load.
|Dual gate fd-soi transistor|
Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (fd-soi) technology. Lowering the threshold voltages of the transistors can be accomplished through dynamic secondary gate control in which a back-biasing technique is used to operate the dual gate fd-soi transistors with enhanced switching performance.
|Charge and discharge signal circuit and dc-dc converter|
A charge and discharge signal circuit includes: high side transistors connected in series; low side transistors connected in series; high side drive circuits; low side drive circuits; and a drive signal generation circuit, wherein each drive circuit includes: a level shifter; a capacitor switch string connected in series, being connected in parallel with the transistor; and a drive part, to which an output of the level shifter is supplied, at least one pair of neighboring ones of the level shifters are commonly formed, and two neighboring ones of the drive parts receive a same output from the common shifters.. .
|Selectable upper voltage range monitoring circuit|
A battery voltage measuring circuit for an implantable cardiac device is presented. Since the usable battery voltage for the device is limited to an upper range of voltages, the need for measuring lower voltages at which the battery is approaching end of life is of no use.
Cameron Health, Inc.
A data driver is disclosed. The data driver includes a first latch unit including a plurality of first latches configured to store data, a selector configured to select and/or output data in two or more first latches, a level shifter unit configured to convert a voltage level of the data in the two or more selected first latches and output the voltage level-converted data, and a second latch unit including a plurality of second latches configured to store the voltage level-converted data..
Dongbu Hitek Co., Ltd.
|Scalable layout architecture for metal-programmable voltage level shifter cells|
A layout architecture for voltage level shifters is provided. The architecture includes features of voltage level shifter cells and arrangements of the voltage level shifter cells within integrated circuits.
Semiconductor device and detecting state of input signal of semiconductor device
A semiconductor device includes a signal detection unit suitable for detecting a state of an input signal and generating a detection signal based on a detected result, and a signal transmission unit suitable for selectively transmitting the input signal in response to the detection signal, wherein the signal detection unit includes a state signal generation unit suitable for detecting a level shifting time of the input signal, and generating a state signal at a detected level shifting time, and a state determination unit suitable for comparing a voltage level of the input signal with a voltage level of a reference voltage in response to the state signal, and outputting the detection signal.. .
Sk Hynix Inc.
Level shifter, dc-dc converter, and level shift method
A level shifter includes: a first cascode portion, including a first transistor of a first conductivity type and a second transistor of a second conductivity type which are cascode-coupled to each other, configured to transmit a first input signal; a second cascode portion, including a third transistor of the first conductivity type and a fourth transistor of the second conductivity type which are cascode-coupled to each other, configured to transmit a second input signal; a latch portion configured to retain a first output signal and a second output signal obtained by changing, based on a first voltage obtained by boosting a power supply voltage, potential levels of the first input signal and the second input signal; and a potential-difference suppression circuit, coupled in parallel to the first cascode portion, configured to control a potential difference between source and drain of each of the first transistor and the second transistor.. .
Level shifter of driving circuit and operating method thereof
A level shifter applied in a driving circuit of a display is disclosed. The level shifter includes a first stage of level shifting unit and a second stage of level shifting unit and used to convert an input voltage signal with low voltage level into an output voltage signal with high voltage level.
Raydium Semiconductor Corporation
Half-bridge circuit including a low-side transistor and a level shifter transistor integrated in a common semiconductor body
A half-bridge circuit includes a low-side transistor and a high-side transistor each having a load path and a control terminal, and a high-side drive circuit having a level shifter with a level shifter transistor. The low-side transistor and the level shifter transistor are integrated in a common semiconductor body..
Infineon Technologies Austria Ag
Self biased dual mode differential cmos tia for 400g fiber optic links
A transimpedance amplifier (tia) device. The device includes a photodiode coupled to a differential tia with a first and second tia, which is followed by a level shifting/differential amplifier (ls/da).
Dual path level shifter
Dual path level shifter methods and devices are described. The described level shifter devices can comprise voltage-to-current and current-to-voltage converters..
Peregrine Semiconductor Corporation
Phase locked loop circuit
A phase locked loop (pll) circuit is provided. The pll includes a voltage controlled oscillator (vco) for outputting an oscillation signal of a frequency corresponding to an inputted voltage, a frequency divider for dividing the oscillation signal and output a frequency-divided signal, a phase comparator for comparing a phase of the frequency-divided signal and the phase of an input signal from the outside and output a first phase comparison signal and a second phase comparison signal which have different polarities, a differential amplifier circuit for outputting a control voltage based on a voltage difference between the first phase comparison signal and the second phase comparison signal to the vco, a level shift circuit for outputting a level-shifted signal which is made by shifting a direct current level of the second phase comparison signal, and an amplifier circuit for outputting an amplified signal which is an amplified level-shifted signal..
Nihon Dempa Kogyo Co., Ltd.
Level shift circuit and semiconductor device
A level shift circuit includes: a latch circuit (q5, q6, q7, q8) including first (q5, q7) and second (q6, q8) inverter circuits; a first input mos transistor (q1) operating in accordance with an input signal; a second input mos transistor (q2) operating in accordance with an inversion signal of the input signal; and a current-voltage control mos transistor (q9). The latch circuit (q5, q6, q7, q8) outputs a voltage having been converted from the input voltage in level.
Renesas Electronics Corporation
Level shifting circuit
A level shifter shifts the level of an input signal from a second voltage domain to a first voltage domain. To accommodate different input signal levels (e.g., including sub-threshold input signal levels) that may arise due to changes in the supply voltage for the second voltage domain, current for a latch circuit of the level shifter is limited based on the supply voltage for the second voltage domain.
Equalization device for assembled battery
In an equalization device for equalizing voltages of battery cells connected in series, each battery cell is provided with an equalization switch and a level shift section. The level shift section includes at least one level shift circuit.
Semiconductor device having level shift circuit
A semiconductor device includes: two level shift circuits having substantially the same circuit configuration; an input circuit that supplies complementary input signals to the level shift circuits, respectively; and an output circuit that converts complementary output signals output from the level shift circuits into in-phase signals and then short-circuits the in-phase signals. According to the present invention, the two level shift circuits having substantially the same circuit configuration are used, and the complementary output signals output from the level shift circuits are converted into in-phase signals before short-circuited.
Ps4 Luxco S.a.r.l.
Multiple voltage input buffer and related method
A device includes a first level shifter, a switch, and a control circuit. The first level shifter is electrically connected to a pad.
Taiwan Semiconductor Manufacturing Company, Ltd.
Level shifter with built-in logic function for reduced delay
A method and circuit for implementing a level shifter with built-in-logic function for reduced delay. The circuit including at least one set of inputs from a first power supply domain.
International Business Machines Corporation
Method and circuit for detecting usb 3.0 lfps signal
A system and method for efficient detection of low frequency periodic signaling (lfps) input signals. A receiver receives two input differential signals that are lfps input signals.
Advanced Micro Devices, Inc.
Output apparatus, output driver, and level shifting system
An output driver for driving a pad includes a pull-up circuit and a pull-down circuit. The pull-up circuit includes first, second and third first-type transistors.
Mstar Semiconductor, Inc.
Level shifter utilizing a capacitive isolation barrier
According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit through a capacitive isolation barrier.
International Rectifier Corporation
Communication between voltage domains
An integrated circuit 6 including a first voltage domain 4 incorporates real time clock circuitry 12 that communicates via communication circuitry 18 with processing circuitry 16 contained within a second voltage domain. The communication circuitry 18 includes first parallel-to-serial conversion circuitry 24 located within the first voltage domain 4, level shifting circuitry 32 for passing serial signals between the voltage domains and second parallel-to-serial circuitry 26 located in the second voltage domain..
Level shifter with static precharge circuit
A level shifter includes a static precharge circuit. During a precharge phase, two nodes of the level shifter are precharged to a voltage at or near a reference voltage.
Freescale Semiconductor, Inc.
Level shift circuit with automatic timing control of charging transistors, and driver circuit having the same
A level shift circuit includes first and second nmos transistors that are coupled between a first supply terminal, and first and second output nodes, respectively, and have respective control terminals receiving input signals of a low amplitude, third and fourth pmos transistors which are coupled between a second supply terminal, and the first and second output nodes outputting signals of high amplitude, respectively, a fifth pmos transistor which is coupled between a gate of the third pmos transistor and the second output node, and has a gate coupled to the first output node, a sixth pmos transistor which is coupled between a gate of the fourth pmos transistor and the first output node, and has a gate coupled to the second output node, and first and second load elements which are coupled between the second supply terminal and the gates of the third and fourth pmos transistors, respectively.. .
Renesas Electronics Corporation
A level shifter includes high breakdown voltage first and second pmos transistors, high breakdown voltage first and second depression nmos transistors having gates respectively supplied with first and second control signals, low breakdown voltage first and second nmos transistors having gates respectively supplied with third and fourth control signals, and a timing control unit that generates the first control signal and the third control signal different from the first control signal corresponding to an inverted signal of an input signal, and generates the second control signal and the fourth control signal different from the second control signal corresponding to a non-inverted signal of the input signal.. .
Renesas Electronics Corporation
Source driver and method to reduce peak current therein
A source driver and a method to reduce peak current of the source driver are provided. The source driver includes a latch circuit, a level shifter and a digital-to-analog converter (dac) circuit.
Novatek Microelectronics Corp.
A level shifter includes an input stage circuit, a latch circuit and a transient speed-up circuit. The input stage circuit receives an input signal.
Richtek Technology Corp
Level shifter circuit, scanning circuit, display device and electronic equipment
A level shifter circuit, wherein a first and a second transistor circuit are connected serially, a third and a fourth transistor circuit are connected serially; a first input voltage is applied to the second transistor circuit and a second input voltage is applied to the fourth transistor circuit; an input terminal of the first transistor circuit is connected to an output terminal of the third and the fourth transistor circuits, and an input terminal of the third transistor circuit is connected to an output terminal of the first and the second transistor circuits; two transistor circuits of at least one side of two transistor circuits of a first fixed power source side and two transistor circuits of a second fixed power source side are configured of double gate transistors; and the level shifter circuit has a switch element for applying a voltage to a common connection node.. .