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Level Shift patents

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 Dead time control patent thumbnailnew patent Dead time control
Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors.
Peregrine Semiconductor Corporation


 Level shifter patent thumbnailnew patent Level shifter
Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors.
Peregrine Semiconductor Corporation


 Gate driving circuit and display module patent thumbnailnew patent Gate driving circuit and display module
A gate driving circuit for providing a scan signal to a lcd panel is disclosed. The gate driving circuit includes at least one positive level shifter, at least one negative level shifter, a pair of p-type transistor and an n-type transistor.
Sitronix Technology Corp.


 Fingerprint information detection circuit patent thumbnailnew patent Fingerprint information detection circuit
The present invention relates to a chip design and discloses a fingerprint information detection circuit. The invention includes a reset unit, a feedback unit, an amplification unit and a source follower unit; the reset unit is connected to the feedback unit and amplification unit, while the feedback unit is connected to the amplification unit, and the amplification unit is connected to the source follower unit; when the reset transistor built-into the reset unit is on, it stores an electric charge, and resets the feedback unit; when the reset transistor is off, the stored electric charge is injected into the feedback unit and amplification unit; the feedback unit receives the electric charge, and outputs the second voltage signal generated when it detects fingerprints to the source follower unit; the amplification unit amplifies the received signal and outputs it to the source follower unit; the source follower unit receives the signal, performs voltage level shifting before outputting the first voltage signal that carries the detected fingerprint information.
Silead Inc.


 Apparatus for improving signal-to-noise performance of projected capacitance touch screens and panels patent thumbnailnew patent Apparatus for improving signal-to-noise performance of projected capacitance touch screens and panels
Improved signal-to-noise performance of projected capacitance touch screens and panels is provided by an integrated circuit regulated high voltage source and high voltage/current drivers coupled to a plurality of projected capacitive touch elements that are controlled by a microcontroller. The single integrated circuit high voltage generator/driver may comprise a voltage boost circuit, a voltage reference, power-on-reset (por), soft start, a plurality of voltage level shifters and a serial interface for coupling to the microcontroller that may control all functions related to using the projected capacitance touch screens and panels..
Microchip Technology Incorporated


 Apparatus for performing level shift control in an electronic device with aid of parallel paths controlled by different control signals for current control purposes patent thumbnailApparatus for performing level shift control in an electronic device with aid of parallel paths controlled by different control signals for current control purposes
An apparatus for performing level shift control in an electronic device includes an input stage positioned in a level shifter of the electronic device, and an output stage positioned in the level shifter and coupled to the input stage through a set of intermediate nodes. The input stage is arranged for receiving at least one input signal of the level shifter through at least one input terminal of the input stage and controlling voltage levels of the set of intermediate nodes according to the at least one input signal.
Mediatek Inc.


 Semiconductor device in a level shifter with electrostatic discharge (esd) protection circuit and semiconductor chip patent thumbnailSemiconductor device in a level shifter with electrostatic discharge (esd) protection circuit and semiconductor chip
The present examples relate to a semiconductor chip having a level shifter with an electrostatic discharge (esd) protection circuit and a device applying to multiple power supply lines with high and low power inputs to protect the level shifter from the static esd stress. More particularly, the present examples relate to using a feature to protect a semiconductor device in a level shifter from the esd stress by using esd stress blocking region adjacent to a gate electrode of the semiconductor device.
Magnachip Semiconductor, Ltd.


 Gate driver control circuit patent thumbnailGate driver control circuit
A method for operating a gate driver that is driving pixel transistors of a display panel, is described. An internal start pulse is produced in response to an external start pulse and in accordance with a system clock, wherein the internal start pulse is input to a first cell of a gate driver shift register whose outputs are coupled to level shifting output stages that are driving the rows of pixel transistors of the display panel.
Apple Inc.


 Level shifter and non-volatile memory device using the same patent thumbnailLevel shifter and non-volatile memory device using the same
The level shifter of an embodiment includes a first level shifter configured to output an intermediate signal wherein a high voltage is a positive supply voltage or a positive voltage by inputting an input signal and a low voltage is a negative supply voltage, to an intermediate signal node and an inverted intermediate signal node and a second level shifter configured to output a low voltage to an output terminal and an inverted output terminal by receiving input of the intermediate signal and altering the low voltage to the negative supply voltage or a negative voltage.. .
Magnachip Semiconductor, Ltd.


 Level shifter and projector patent thumbnailLevel shifter and projector
A level shifter included in a device includes: an external interface power unit configured to supply a power voltage corresponding to electrical input-output characteristics of an interface circuit of an external device; an internal interface power unit configured to supply a power voltage corresponding to electrical input-output characteristics of an internal interface circuit in the device; a power switch unit configured to control power supply to the external interface power unit according to an electrical signal from the external device; and a selector unit configured to control conduction between the interface circuit of the external device and the internal interface circuit, wherein the selector unit is configured to transition to an operable state when the external interface power unit is supplied with power.. .
Casio Computer Co., Ltd.


A/d conversion device


An a/d conversion device includes: a level shifter circuit configured to level-shift an analog voltage of an input voltage signal to generate a conversion signal; an a/d converter configured to a/d-convert a voltage of the conversion signal supplied from the level shifter circuit. The level shifter circuit subtracts an instantaneous voltage value of the input voltage signal from a reference voltage so as to output a signal value as the conversion signal..
Lapis Semiconductor Co., Ltd.


Level shifter circuit


A level shifter circuit a first transistor connected between a power source terminal of the level shifter circuit and an output terminal of the level shifter circuit, the first transistor being configured to transmit, in response to a first signal and a second signal, a power source voltage applied from the power source terminal to the output terminal, the first signal being received from an input terminal of the level shifter circuit through a first gate of the first transistor, the second signal being received through a second gate of the first transistor, and a second transistor connected between a ground terminal of the level shifter circuit and the output terminal, the second transistor being configured to transmit a ground voltage from the ground terminal to the output terminal in response to a gate signal received through a gate of the second transistor.. .
Electronics And Telecommunications Research Institute


Level shifters, memory systems, and level shifting methods


Level shifters, memory systems, and level shifting methods are described. According to one arrangement, a level shifter includes an input configured to receive an input signal in a first voltage domain, an output configured to output an output signal from the level shifter in a second voltage domain different than the first voltage domain, a plurality of pull-down devices, and wherein one of the pull-down devices is coupled with the input and the output, a plurality of cross-coupled devices coupled with the pull-down devices and configured to provide transitions in the output signal as a result of transitions in the input signal, a plurality of current limiting devices coupled with the cross-coupled devices and configured to limit a flow of current from a source to the cross-coupled devices, and a plurality of dynamic devices configured to selectively provide charging current from the source to the cross-coupled devices..
Micron Technology, Inc.


Level shift circuit and driver circuit


According to one embodiment, a level shift circuit includes first through fourth transistors, a control circuit, and first and second generating circuits. The control circuit outputs a first voltage obtained by level-shifting an input voltage to a first terminal.
Kabushiki Kaisha Toshiba


Level shifter circuit and method


A circuit includes a photodiode electrically coupled to a first node, the first node configured to be charged by a first power supply voltage. A second node is configured to be charged by a second power supply voltage lower than the first power supply voltage, a source follower transistor is electrically coupled between the second node and a column line, and a level shifter is electrically coupled between the first node and the second node..
Taiwan Semiconductor Manufacturing Company, Ltd.


High speed level shifter circuit


A r a level shifter circuit includes a first p-channel kick transistor connected directly across a first cross-coupled p-channel transistor, a second p-channel kick transistor connected directly across a second cross-coupled p-channel transistor, a first gate drive circuit coupled to the gate of the first p-channel kick transistor and configured to turn on first p-channel kick transistor to pull up the first output node in response to a rising edge of a signal at the input node, and a second gate drive circuit coupled to the gate of the second p-channel kick transistor and configured to turn on second p-channel kick transistor to pull up the second output node in response to a falling edge of a signal at the input node.. .
Microsemi Soc Corporation


Rf amplification device with power protection during high supply voltage conditions


A radio frequency (rf) amplification device comprises an rf amplification circuit, and a dynamic level shifter (dls) circuit coupled between a supply voltage and the rf amplification circuit. The dls circuit is configured to provide a first shifted voltage to the rf amplification circuit via a first diode when the supply voltage is above a first threshold voltage level.
Rf Micro Devices, Inc.


Level shifter circuit


A level shifter circuit includes an input terminal, a first output terminal, a second output terminal, an output stage, a first control bias unit, a second control bias unit, and an output stage. The input stage includes a first transistor and a second transistor, and their gates are coupled to the input terminal.
Raydium Semiconductor Corporation


Shared interface circuit


The present invention provides a circuit including a multiplexer, a level-shifter circuit, a power-supply circuit, and a switch circuit. The multiplexer has a first input-terminal, a second input-terminal and a third input-terminal, wherein the first and second input-terminals are coupled to a first-interface pin and a second-interface transfer pin of a processor, and the third input-terminal is coupled to a second-interface receive pin or the first-interface pin of the processor.
Wistron Neweb Corp.


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Semiconductor device


The number of level shifters is reduced in a decode circuit of a nonvolatile memory. A semiconductor device is configured with an electrically rewritable nonvolatile memory cell array, and a decode circuit which generates a selection signal to select a driver for a memory gate line (word line).
Renesas Electronics Corporation


Methods and systems to selectively boost an operating voltage of, and controls to an 8t bit-cell array and/or other logic blocks


Methods and systems to provide a multi-vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-vcc environment may be implemented to isolate a vmin-limiting logic block from a single-vcc environment, such as to reduce vmin and/or improve energy efficiency in the single-vcc environment.
Intel Corporation


Voltage level shifter


A method for voltage level shifting comprises several steps. A data signal in a first voltage domain is received by a voltage level shifter.
Invecas, Inc.


Level shifter circuit


Embodiments of the present invention provide a level converter circuit with a resistor and a current adjustment circuit. The resistor is connected between an input and an output of the level converter circuit.
Fraunhofer-gesellschaft Zur Foerderung Der Angewandten Forschung E.v.


Level shifter


Various implementations described herein are directed to a circuit for translating an input signal from a source voltage domain to an output signal for a destination voltage domain that is is different than the source voltage domain. The circuit may include a level shifting portion configured to operate with a supply voltage that exceeds a stressing threshold of one or more components within the circuit.
Arm Limited


Level shifter


An exemplary level shifter includes a clock level shifter configured to generate a level shifted clock signal from an input clock signal; and a switched capacitor logic controller coupled to the clock level shifter. The switched capacitor logic controller is configured to steer the level shifted clock signal based on a data signal and the input clock signal, providing a level shifted version of the data signal..
Analog Devices, Inc.


Level shifter circuit with improved time response and control method thereof


A level shifter circuit with improved time response and a control method thereof are disclosed herein. The level shifter circuit includes the output stage circuit of a level shifter and a booster circuit.
Silicon Works Co., Ltd.


Array substrate, display panel and repairing method thereof


An array substrate, a display panel and a repairing method thereof are provided. In the array substrate, except the last gate line, both ends of each of the remaining gate lines are provided respectively with first leads connected to the gate line; in each group of gate integrated drive circuits, except a first level shift register, an input terminal of every other shift register is provided with a second lead connected to the input terminal; the first lead connected to one of the gate lines and the second lead connected to an input terminal of the shift register at the next level adjacent thereto have an overlapping area (a) therebetween, and are insulated from each other..
Boe Technology Group Co., Ltd.


Organic light-emitting display apparatus


An organic light-emitting display apparatus including a display including pixels arranged in an array, a sensor for detecting respective current characteristics of the pixels, a current sensor for receiving a first current from a first pixel of the pixels, for outputting a first voltage corresponding to the first current, for receiving a second current from a second pixel of the pixels, and for outputting a second voltage corresponding to the second current, a level shifter for receiving the first and second voltages and for generating first and second shift voltages respectively corresponding to the first and second voltages, an intermediate voltage of the first and second voltages being equal to a conversion reference voltage, and an analog-to-digital converter for receiving the first and second shift voltages and for outputting a digital value corresponding to a difference between the first and second shift voltages based on the conversion reference voltage.. .
Samsung Display Co., Ltd.


Cost effective low pin/ball count level-shifter for lcd bias applications supporting charge sharing of gate lines with perfect waveform matching


A level shifter circuit has a plurality of channels for providing signals to a capacitive load and has circuits for sharing charge stored in the capacitive load between the channels. A first pair of channel clock generating circuits are coupled respectively to a first pair of channels.
Texas Instruments Deutschland Gmbh


Decision feedback equalizer


A decision feedback equalizer for n-level amplitude modulated signal, includes: (n-1) level conversion circuits to add (n-1) shifting voltages to the amplitude modulated signal respectively; (n-1)×n determination feedback equalization-correction circuits to perform n types of decision feedback equalization processing, each of which adding each of n-level offset voltages corresponded to any one of n levels of a reception data ahead of one data cycle, on each of the (n-1) level shifted signals to generate (n-1) sets of n equalization correction signals; (n-1)×n comparison circuits; (n-1)×n first latch circuits; (n-1) selection circuits to select a comparison result of the n comparison circuits in each (n-1) sets; (n-1) second latch circuits; and a decoder, wherein each of the (n-1) selection circuits selects an equalization-correction signal among the n equalization-correction signals in each (n-1) set according to outputs latched by the (n-1) second latch circuits.. .

Cross-coupled level shifter with transition tracking circuits


A transition tracking circuit may be configured to receive a first input signal and a second input signal from a level shifter. The transition tracking circuit may be configured to track earlier falling transitions of the first and second signals to generate an output signal..

Voltage level shifter for high voltage applications


A voltage level shifter for high voltage applications has a low voltage domain current mirror having first and second branches. A high voltage switch and a resistor are connected in series with the second branch.

Semiconductor device and battery voltage measuring method


The present disclosure provides a semiconductor device including: a first buffer amplifier into which a voltage of a high potential side of one battery cell selected from plural battery cells that are connected in series is input; a second buffer amplifier into which a voltage of a low potential side of the one battery cell other than a lowermost stage battery cell is input; an analog level shifter into which a voltage output from the first buffer amplifier and a voltage output from, the buffer amplifier are input; a first switch that switches a voltage input to the analog level shifter from the voltage output from the second buffer amplifier to a reference voltage; and a second switch that switches a voltage input to the first buffer amplifier from the voltage of the high potential side of the one battery cell to the reference voltage.. .

Goa circuit applied to liquid crystal display device


A goa (gate on array) circuit applied to a liquid crystal display device is disclosed. The liquid crystal display device has a plurality of scan lines.

Modular light-string system having independently addressable lighting elements


Apparatus and associated methods relate to modular series-connectable led light strings having an input connector and an output connector for electrically communicating power and a control signal, an input control signal being actively level-shifted to a level suitable to a first lighting element of the led light string. In an illustrative embodiment, the led light string may have a plurality of series connected lighting elements that generate a series of intermediate supply voltage levels.

Level shifter and display device including the same


A level shifter may include: a phase controller configured to determine the number of phases of a gate pulse, using an on input signal and an off input signal, and generate a control signal according to the determined number; a switching controller configured to generate one or more switching signals in response to the control signal; and an output buffer configured to generate the level-shifted gate pulse in response to the one or more switching signals.. .

Scanline driver chip and display device including the same


A scanline driver chip includes: a chip selection de-serializer configured to provide an output enable signal based on an enable signal, a clock signal, and serial chip selection data, the serial chip selection data being received in serial order; an address data de-serializer configured to provide parallel address data based on the enable signal, the clock signal, the output enable signal, and serial address data, the serial address data being received in serial order; and a decoder-level shifter configured to provide a scanline enable signal based on the parallel address data. A display device includes: a controller configured to provide an enable signal, a clock signal, serial chip selection data, and serial address data; a plurality of the scanline driver chips each configured to provide a scanline enable signal; and a pixel array configured to be driven based on the scanline enable signal..

Xor phase detector, phase-locked loop, and operating a pll


An xor phase detector for a phase-locked loop pll comprises an xor gate which has an input for a periodic reference signal and another input connected to a frequency divider of the pll. A level shifter has a level shifter input connected to an output of the xor gate and a level shifter output connectable to a voltage-controlled oscillator vco of the pll.
Freescale Semiconductor, Inc.


Semiconductor device and electronic device


To provide a semiconductor device that inhibits unexpected output of a high-level signal immediately after the rise of a power supply voltage. The semiconductor device includes a first buffer circuit, a level shifter circuit, and a second buffer circuit.
Semiconductor Energy Laboratory Co., Ltd.


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Semiconductor device and electronic device


To provide a semiconductor device that inhibits unexpected output of a high-level signal immediately after the rise of a power supply voltage. A semiconductor device includes a first buffer circuit, a level shifter circuit, and a second buffer circuit.
Semiconductor Energy Laboratory Co., Ltd.


Level shifting circuit, apparatus and operating the same


A level shifting circuit includes an input circuit, a leakage divider circuit, a skew inverter circuit and a buffering circuit. The input circuit has an input terminal configured to receive an input voltage.
Taiwan Semiconductor Manufacturing Company, Ltd.


Current steering level shifter


Described is an apparatus which comprises: a first power supply node to provide a first power supply; a second power supply node to provide a second power supply; a driver to operate on the first power supply, the driver to generate an output; and a receiver to operate on the second power supply, the receiver to receive the output from the driver and to generate a level-shifted output such that the receiver is operable to steer current from the second power supply to the first power supply.. .
Intel Corporation


High-speed level shifter


A level shifter includes a latch having first and second branches, first and second outputs, first and second control switches in series between the respective branches and outputs, and a controller receiving first and second output signals and outputting first and second control signals to the first and second control switches for controlling activation thereof. In an initial state, the first output signal is in the first state, the first control switch is activated, the second output signal is in the second state, and the second control switch is deactivated.



Level Shift topics:
  • Level Shift
  • Level Shifter
  • Semiconductor
  • Level Shift Circuit
  • Transistors
  • Semiconductor Substrate
  • Voltage Level Shift
  • Level Shifter Circuit
  • Shifter Circuit
  • Modulation
  • Adverse Effect
  • Protection Circuit
  • Schmitt Trigger
  • Transimpedance Amplifier
  • Optical Fiber


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    This listing is a sample listing of patent applications related to Level Shift for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Level Shift with additional patents listed. Browse our RSS directory or Search for other possible listings.


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