|| List of recent Level Shift-related patents
|Shiftable memory employing ring registers|
Shiftable memory employs ring registers to shift a contiguous subset of data words stored in the ring registers within the shiftable memory. A shiftable memory includes a memory having built-in word-level shifting capability.
|Low side nmos protection circuit for battery pack application|
An electric circuit comprising means for communicating with an external device coupled to means for measuring the charge condition of an external battery. In some embodiments, the circuit comprises at least one level shifter for changing the reference voltage of communication signals.
|Signal processing device|
A level shifter converting a binary signal having a first potential and a second potential into a signal having the first potential and a third potential, and a signal processing circuit using the level shifter are provided. The first potential is higher than the second potential.
|Voltage level shifter circuit, system, and method for high speed applications|
A level shifting circuit includes a first inverter including a pair of transistors of opposite conductivity type, the first inverter adapted to receive an input signal in a first voltage domain and further including at least one additional transistor driven by a voltage in a second voltage domain. A second inverter is coupled in series with the first inverter and operable to generate an output signal in the second voltage domain.
|Capacitive level shifter devices, methods and systems|
Systems and methods of use relate to a circuit that is designed to detect the state of two control signals, wherein one control signal indicates an on state for the gate driver and the other control signal indicates an off state for the gate driver. The circuit responds to each of the control signals by controlling the gate driver so that it drives an output either high or low.
|High-voltage heavy-current drive circuit applied in power factor corrector|
A high-voltage heavy-current drive circuit applied in a power factor corrector, comprising a current mirroring circuit (1), a level shift circuit (3), a high-voltage pre-modulation circuit (2), a dead time control circuit (4) and a heavy-current output stage (5); the heavy-current output stage adopts a darlington output stage structure to increase the maximum operating frequency of the drive circuit. The stabilized breakdown voltage characteristic of a voltage stabilizing diode is utilized to ensure the drive circuit operating within a safe voltage range.
|High performance class ab operational amplifier|
A class ab operational amplifier includes an input stage, an output stage and a level shifter stage to control the quiescent current of the output stage and to transfer the signal from the input stage to the output stage, and a control circuit of the level shifter stage. The control circuit includes a transistor differential pair having a differential input terminals and the differential voltage at the differential terminals of the differential pair controls the level shifter stage..
|Semiconductor switch circuit|
A semiconductor switch circuit includes a switch between an input node and an output node that connects nodes to each other according to a control signal and a level shifter outputting the control signal at a boosted level that is greater than a power supply voltage level. The semiconductor switch circuit also includes a booster circuit to output a boosted voltage at the boosted level higher than a power supply voltage level.
|Method and system for a feedback transimpedance amplifier with sub-40khz low-frequency cutoff|
A system for a feedback amplifier with sub-40khz low-frequency cutoff is disclosed and may include amplifying electrical signals received via coupling capacitors utilizing an amplifier having feedback paths comprising source followers and feedback resistors. Gate terminals of the source followers may be coupled to output terminals of the amplifier circuit.
|Solid-state imaging device and imaging apparatus|
A solid-state imaging device according to the present disclosure includes: a pixel unit in which unit pixels are arranged two-dimensionally, each of the unit pixels including: a photodiode which stores signal charges; a transfer transistor for transferring the signal charges stored in the photodiode; a charge detection unit which temporarily stores the transferred signal charges; and a reset transistor for resetting the signal charges stored in the charge detection unit; and a vertical scanning unit which drives the pixel unit, the vertical scanning unit including: a row selection unit; a level shift circuit for converting a level of an externally inputted power supply voltage; and a buffer circuit for buffering a voltage whose level has been converted by the level shift circuit, the level shift circuit including: a step-down level shift circuit; and a step-up level shift circuit isolated from the step-down level shift circuit by a well.. .
|Power converter with self-driven synchronous rectifier control circuitry|
An ac-dc power converter is provided with two pairs of self-driven synchronous rectifier switches in addition to, or in place of, diode bridge rectifiers for boosting efficiency and reducing cost. An ac sensing circuit is coupled to ac input terminals, and a dc level shifting circuit applies a dc offset to an ac input signal received via the sensing circuit.
|Powerline control interface|
A powerline control interface includes a powerline connection, a level shifter connected to the powerline connection, the level shifter having a zero crossing detector signal output, a capacitor connected to the powerline connection, an inductor connected to the powerline connection, and a receive signal inductively coupled to the inductor.. .
|Voltage level shifter|
The voltage level shifter includes a first voltage shift circuit, a second voltage shift circuit, a first switch circuit, a second switch circuit, a third switch circuit and a fourth switch circuit. The first voltage shift circuit receives a first input voltage, and the second voltage shift circuit receives a second voltage shift circuit.
|Level shifter for high density integrated circuits|
A level shifter for converting between voltages of a core voltage range to voltages within a larger i/o voltage range. The level shifter has interconnected transistors implemented as core devices operable within the core voltage range.
|Dual supply level shifter circuits|
A dual supply level shifter circuit includes a switching circuit and a set of level shifter circuits coupled to the switching circuit. The switching circuit includes a first set of coupled transistors, wherein the supply switching circuit is coupled to a first supply source that is configured to provide a first power supply voltage and is coupled to a second supply source that is configured to provide a second power supply voltage.
|Systems and method for level shifters|
A level shifter system includes an inverting portion, a non-inverting portion and a cross latch output component. The inverting portion is configured to receive an inverting input, a supply voltage and to generate an intermediary inverting output.
|Bias circuit for a switched capacitor level shifter|
A noise resistant switch control circuit is provided. The circuit includes a low pass filter configured to couple to a first terminal of a switch and a first voltage clamp coupled to the low pass filter.
|Cell balancing through a switched capacitor level shifter|
A battery management apparatus is provided. The battery management apparatus includes a switched capacitor level shifter having a first port and a second port.
|Systems and methods for fabricating semiconductor devices having larger die dimensions|
A method of fabricating a semiconductor device is disclosed. A photosensitive material is coated over the device.
|High-voltage semiconductor device|
A withstand voltage region is formed to surround a logic circuit formation region. A high-voltage mosfet for level shifting is formed in part of the withstand voltage region.
|High-speed memory write driver circuit with voltage level shifting features|
Various aspects of a fast, energy efficient write driver capable of efficient operation in a dual-voltage domain memory architecture are provided herein. Specifically, various aspects of the write driver described herein combine a high speed driver with voltage level shifting capabilities that may be implemented efficiently in reducing use of silicon area while using lower power.
|Electronic power converter with ground referenced lossless current sensing|
A current sensing circuit for an electronic power converter having an inductor that is not referenced to ground is configured to provide an output signal that is referenced to ground and is proportional to the current flow between the inductor and a load in an electrical power system. The current sensing circuit includes outputs associated with a voltage of the inductor, a current source circuit, a current steering circuit responsive to the voltage outputs and a level shifting circuit..
|Level shifting circuit with adaptive feedback|
An amplifier has a first pull-up path coupled between a voltage supply node and an output node, and a pull-down path coupled between the output node and a ground supply node. A second pull-up path is coupled between the voltage supply node and the output node.
|Low voltage level shifter for low power applications|
A level shifter circuit for low power applications that can shift the level of a digital signal that is below the threshold voltage of output transistors. The level shifter uses core transistors in the input stage and includes an intermediate stage that limits the voltage applied to the drain of the core transistors.
|Voltage level shifter with a low-latency voltage boost circuit|
Certain aspects of the present disclosure provide a voltage level shifting circuit employing a low latency, ac-coupled voltage boost circuit, as well as other circuits and apparatus incorporating such a level shifting circuit. Such level shifting circuits provide significantly lower latency compared to conventional level shifters (e.g., latency reduced by at least a factor of two).
|Apparatuses and method for shifting a voltage level|
Apparatuses and methods, such as those for shifting a voltage level are disclosed. An example apparatus includes a level shifter configured to provide output signals based on a logical value of an input signal, where the level shifter is precharged to a precharge voltage prior to providing the output signals.
An ic generally comprises enable pin, ground pin, input pin, output pin, load switch, control circuitry, and level shifter. Load switch is coupled between input pin and output pin and receives a negative voltage through the input pin.
|Circuit and method for improving noise immunity of a single-end level shifter in a floating gate driver|
A floating gate driver uses a single-end level shifter to translate a set signal and a reset signal induced by a rising edge and a falling edge of a switch signal to a common output terminal to generate an output voltage for a bistable circuit to generate a level shifted switch signal. Under control of a well transient detect signal asserted by detecting noise in the output voltage, a masking circuit between the single-end level shifter and the bistable circuit masks noise in the output voltage.
|Integrated level shifting latch circuit and method of operation of such a latch circuit|
An integrated level shifting latch circuit receives an input signal in a first voltage domain and generates an output signal in a second voltage domain. Data retention circuitry operates in a transparent phase where a data value is subjected to a level shifting function and is written into the data retention circuitry dependent on the input signal.
|Fast voltage level shifter circuit|
A voltage level shifting circuit with an input terminal and an output terminal. The level shifting circuit has a field-effect transistor (fet) switch with a gate attached to the input terminal, a drain attached to the output terminal and a source attached to a current changing mechanism.
|Combinatorial circuit and method of operation of such a combinatorial circuit|
An integrated level shifting combinatorial circuit receives a plurality of input signals in a first voltage domain and performs a combinatorial operation to generate an output signal in a second voltage domain. The circuit includes combinatorial circuitry includes first and second combinatorial circuit portions operating in respective first and second voltage domains.