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Level Shift patents

      

This page is updated frequently with new Level Shift-related patent applications.




 Optical reception circuit patent thumbnailnew patent Optical reception circuit
An optical reception circuit includes a first photodetector, a first transimpedance amplifier, a level shift circuit, a second photodetector, a second transimpedance amplifier, a peak hold circuit, and a comparator. The first transimpedance amplifier converts a first light current from the first photodetector to a first voltage.
Panasonic Intellectual Property Management Co., Lt


 Low power buffer with gain boost patent thumbnailnew patent Low power buffer with gain boost
The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal.
Inphi Corporation


 Dynamic high voltage driver with adjustable clamped output level patent thumbnailnew patent Dynamic high voltage driver with adjustable clamped output level
A driver circuit and associated techniques include managing voltage driving an electronic device. An input signal having a first voltage level is received.
International Business Machines Corporation


 Circuit and  generating clock-signals patent thumbnailnew patent Circuit and generating clock-signals
The present disclosure provides circuits and methods for generating clock-signals. An exemplary clock-signal generation circuit includes a delay buffer unit; an inverter unit coupled to the delay buffer unit; a first delay unit having a first nand boolean calculation sub unit, a first sub delay unit and a first level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a first delayed clock-signal; and a second delay unit having a second nand boolean calculation sub unit, a second sub delay unit and a second level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a second delayed clock signal..
Semiconductor Manufacturing International (shanghai) Corporation


 High voltage level shifter in ultra low power supply memory application patent thumbnailHigh voltage level shifter in ultra low power supply memory application
A high voltage level sifter includes a first high-voltage p-channel metal oxide semiconductor (hvpmos) transistor, a second hvpmos transistor, a discharge transistor having a first native high-voltage n-channel metal oxide semiconductor (hvnmos) transistor and a first low-voltage n-channel metal oxide semiconductor (lvnmos) transistor connected in series, and an avalanche transistor having a second hvnmos transistor and a second lvnmos transistor connected in series.. .
Semiconductor Manufacturing International (shanghai) Corporation


 Pulsed level shift and inverter circuits for gan devices patent thumbnailPulsed level shift and inverter circuits for gan devices
Gan-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side gan device communicates through one or more level shift circuits with a high side gan device.
Navitas Semiconductor Inc.


 Level shift circuit and level shift  goa structure liquid crystal panel patent thumbnailLevel shift circuit and level shift goa structure liquid crystal panel
The present invention provides a level shift circuit and a level shift method for a goa structure liquid crystal panel. The level shift chip (20) comprises a time delay calculation register module (201) and a start signal line (30) and an inter-integrated circuit bus (40) are employed to communicatively couple the sequence controller (10) and the level shift chip (20).the sequence controller (10) performs initialization assignment (t1-tn) to the time delay calculation register module (201), and sends a start signal (stv) to the level shift chip (20) via the start signal line (30); the level shift chip (20) is triggered to output the at least four sets of sequence signals (ckv1-ckvn) on a basis of the start signal (stv) according to the initialization assignment (t1-tn) of the time delay calculation register module, and raises voltages of the start signal (stv) and the at least four sets of sequence signals (ckv1-ckvn) for driving the goa structure liquid crystal panel (50) and realizing the generation of more sequence signals with lower cost..
Shenzhen China Star Optoelectronics Technology Co. Ltd.


 Amplifying circuit patent thumbnailAmplifying circuit
An amplifying circuit according to an embodiment includes a sample and hold circuit, an operational amplifier, a feedback capacitance, and a level shift circuit. The sample and hold circuit includes a sampling capacitance to sample an analog input signal in a sampling phase.
Tokyo University Of Science Foundation


 Voltage level shifting circuits for signal levels and/or power supply voltage levels using constant voltage circuit elements, lighting apparatuses and methods of operating the same patent thumbnailVoltage level shifting circuits for signal levels and/or power supply voltage levels using constant voltage circuit elements, lighting apparatuses and methods of operating the same
A level shifting circuit can include a level shifting circuit input node that can be coupled to an input signal, where the input signal can be configured to switch between discrete voltage levels in an input voltage domain. A level shifting circuit output node of the level shifting circuit can be configured to provide shifted voltage levels that are shifted relative to the input signal responsive to switching of the input signal.
Cree, Inc.


 Compiler for translating between a virtual image processor instruction set architecture (isa) and target hardware having a two-dimensional shift array structure patent thumbnailCompiler for translating between a virtual image processor instruction set architecture (isa) and target hardware having a two-dimensional shift array structure
A method is described that includes translating higher level program code including higher level instructions having an instruction format that identifies pixels to be accessed from a memory with first and second coordinates from an orthogonal coordinate system into lower level instructions that target a hardware architecture having an array of execution lanes and a shift register array structure that is able to shift data along two different axis. The translating includes replacing the higher level instructions having the instruction format with lower level shift instructions that shift data within the shift register array structure..
Google Inc.


Solid-state image pickup device

Dark current from a transfer transistor is suppressed and power-supply voltage in a second semiconductor substrate is lowered. A solid-state image pickup device includes a pixel array, a plurality of common output lines receiving signals read out from a plurality of pixels, a transfer scanning unit sequentially driving the plurality of transfer transistors, a signal processing unit processing the signals output to the common signal lines, and a level shift unit making amplitude of a pulse supplied to a gate of the transfer transistor larger than amplitude of a pulse supplied to a gate of a transistor constituting the signal processing unit.
Canon Kabushiki Kaisha

Low-cost, capacitive-coupled level shifter scalable for high-voltage applications

A level shifter for level-shifting a digital input signal referenced to an input ground potential to a digital output signal referenced to an output ground potential, comprising: a capacitor; a driver circuit, including an input node coupled to the digital input signal, and an output node coupled to a first terminal of the capacitor; a receiver circuit, including a first input node coupled to a second terminal of the capacitor, and an output node coupled to the digital output signal; and a latching feedback circuit, including a first input node coupled to the output node of the receiver circuit, and an output node coupled to the second terminal of the capacitor to latch a toggled signal. An optional resistor can be inserted to increase the output resistance of the latching feedback circuit to be substantially larger than the output resistance of the driver circuit..
Balanstring Technology, Llc

Voltage level shifter

A level shifter in a primary voltage domain has a control module receiving an input signal from a secondary voltage domain for controlling operation of the level shifter. The control module includes a complementary pair of transistors and a first native transistor connected in a series current conduction path in the primary voltage domain.
Freescale Semiconductor, Inc.

Power control device

A power control is disclosed, which relates to a technology for stably performing a power ramp-up operation during a power-up operation of an integrated circuit (ic) having heterogeneous power. The power control device includes: an amplifier configured to perform level shifting of a second power-supply voltage level to a first power-supply voltage level according to an input signal during an initial power-up operation section, and output the level-shifted output signal; an initialization unit configured to set an output signal level of the amplifier to the first power-supply voltage level according to a control signal during the initial power-up operation section, and output the first power-supply voltage level; and a latch unit configured to latch an output signal of the initialization unit according to the second power-supply voltage level during the initial power-up operation section..
Sk Hynix Inc.

Voltage level shifter circuit

Embodiments include apparatuses, methods, and systems for voltage level shifting a data signal between a low voltage domain and a high voltage domain. In embodiments, a voltage level shifter circuit may include adaptive keeper circuitry, enhanced interruptible supply circuitry, and/or capacitive boosting circuitry to reduce a minimum voltage of the low voltage domain that is supported by the voltage level shifter circuit.
Intel Corporation

Low-power wide-range level shifter

A latch-based level-shifter is provided that includes an edge-triggered pulse generator that drives a switch to switch off and isolate a pair of cross-coupled inverters in the level-shifter from ground for a transition period responsive to rising and falling edges in an input signal.. .
Qualcomm Incorporated

A cmos level shifter with reduced high voltage transistor count

A digital level shifter adapted to shift an input signal from switching in a low voltage range, to an output switching in a high voltage range has a glitch generator configured to generate pulses at rising and falling transitions of the input signal. Glitch generator output triggers a a multiple-level current source to a high current mode, operating in a low current mode at other times.
Theehouse Design, Inc.

Semiconductor device and electronic appliance

The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output.
Semiconductor Energy Laboratory Co., Ltd.

Switching voltage regulator input voltage and current sensing

A voltage regulator includes a power stage configured to produce an output voltage from an input voltage at an input voltage terminal, a shunt resistor connected in series between the input voltage terminal and the power stage, a first level shifting resistor connected in series between a first terminal of the shunt resistor and a first sense pin of the controller, and a second level shifting resistor connected in series between a second terminal of the shunt resistor and a second sense pin of the controller. The input current of the regulator is sensed as a function of the voltage across the shunt resistor, as shifted down by the level shifting resistors and measured across the sense pins.
Infineon Technologies Austria Ag

Multi-level conversion flip-flop circuits for multi-power domain integrated circuits (ics) and related methods

Multi-level conversion flip-flop circuits for multi-power domain integrated circuits (ics) and related methods are disclosed. A flip-flop circuit latches a representation of a received input data signal in a lower voltage domain, in a latch circuit in a higher voltage domain without need for separate voltage level shifters.
Qualcomm Incorporated

Dead time control

Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors.
Peregrine Semiconductor Corporation

Level shifter

Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors.
Peregrine Semiconductor Corporation

Gate driving circuit and display module

A gate driving circuit for providing a scan signal to a lcd panel is disclosed. The gate driving circuit includes at least one positive level shifter, at least one negative level shifter, a pair of p-type transistor and an n-type transistor.
Sitronix Technology Corp.

Fingerprint information detection circuit

The present invention relates to a chip design and discloses a fingerprint information detection circuit. The invention includes a reset unit, a feedback unit, an amplification unit and a source follower unit; the reset unit is connected to the feedback unit and amplification unit, while the feedback unit is connected to the amplification unit, and the amplification unit is connected to the source follower unit; when the reset transistor built-into the reset unit is on, it stores an electric charge, and resets the feedback unit; when the reset transistor is off, the stored electric charge is injected into the feedback unit and amplification unit; the feedback unit receives the electric charge, and outputs the second voltage signal generated when it detects fingerprints to the source follower unit; the amplification unit amplifies the received signal and outputs it to the source follower unit; the source follower unit receives the signal, performs voltage level shifting before outputting the first voltage signal that carries the detected fingerprint information.
Silead Inc.



Level Shift topics:
  • Level Shift
  • Level Shifter
  • Semiconductor
  • Level Shift Circuit
  • Transistors
  • Semiconductor Substrate
  • Voltage Level Shift
  • Level Shifter Circuit
  • Shifter Circuit
  • Modulation
  • Adverse Effect
  • Protection Circuit
  • Schmitt Trigger
  • Transimpedance Amplifier
  • Optical Fiber


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    This listing is a sample listing of patent applications related to Level Shift for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Level Shift with additional patents listed. Browse our RSS directory or Search for other possible listings.


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