|| List of recent Level Shift Circuit-related patents
|Methods and systems for interconnecting host and expansion devices within system-in-package (sip) solutions|
Methods and systems are disclosed for interconnecting die-to-die-port (dtdp) host devices and dtdp expansion devices for combined system-in-package (sip) solutions. Interconnect circuitry having a plurality of ports is configured to provide communication from the host device to the expansion device so that the expansion device appears to be resident on the host device.
|Level shift circuit and driving method thereof|
A level shift circuit includes an input end, a decoding circuit, a control circuit, and a plurality of output circuits. The input end is configured to receive a coded signal string including a starting code, a setting code, a clock standard signal and an ending code.
|Voltage level conversion circuits and display devices including the same|
A voltage level conversion circuit includes a voltage switch circuit and a level shift circuit. The voltage switch circuit is configured to sequentially output an intermediate voltage and a conversion voltage in response to a switch signal.
|Level shift circuit|
There is provided a level shift circuit free from malfunction. The level shift circuit converts a signal of a first power supply voltage of a first supply terminal, which is supplied to an input terminal, into a signal of a second power supply voltage of a second supply terminal and outputs the converted signal to an output terminal.
|High voltage semiconductor device|
An n well region and an n−region surrounding the n well region are provided in the surface layer of a p−silicon substrate. The n−region includes breakdown voltage regions in which high voltage mosfets are disposed.
|Voltage level shift circuit for multiple voltage integrated circuits|
An over-driver, voltage level shift circuit for use with multiple voltage integrated circuits. The voltage level shift circuit includes a first pair of pmos transistors, a second pair pmos transistors and a third pair of pmos transistors using a high supply voltage source vddh and a low supply voltage source to voltage level shift input signals having a first voltage operating range to an output signal having a second voltage operating range higher then the first voltage operating range.
|Driver integrated circuit|
Provided is a configuration of a driver integrated circuit that can output a voltage exceeding the withstand voltage of a process, and that satisfies required apparatus performance (high speed and high voltage). A differential input circuit, a level shift circuit, and an output circuit are manufactured by the same process and divided and disposed on three or more chips with different substrate potentials (sub-potentials).
|Light reception circuit and light reception device|
A light reception circuit includes a direct current (dc) level shift circuit that shifts a dc voltage level of a first signal or a second signal and outputs a third signal or a fourth signal, or outputs both of the third signal and the fourth signal so that a dc voltage level of the first signal output from a cathode of a photodiode that generates a signal by photo conversion and a dc voltage level of the second signal output from an anode of the photodiode agree, and a differential amplifier that amplifies a difference between the third signal and the second signal, between the first signal and the fourth signal, or the third signal and the fourth signal, based on the third signal, the forth signal output from the dc level shift circuit, impedance of the dc level shift circuit being lower than input impedance of the differential amplifier.. .
|Semiconductor integrated circuit with esd protection circuit|
According to an embodiment, a semiconductor integrated circuit includes a first power supply terminal, a second power supply terminal, a regulator circuit, an electrostatic discharge (esd) protection circuit, and a level shift circuit. A first voltage is applied to the first power supply terminal.
|Inverse level shift circuit|
A voltage conversion mask signal generation circuit generates a first main signal and a first mask signal by converting an output signal of the first transistor to a low-side voltage, and generating a second main signal and a second mask signal by converting an output signal of the second transistor to a low-side voltage. A mask signal generation circuit generating a third mask signal with higher sensitivity than the first and second mask signals with respect to a fluctuation in the high-side reference potential.
|Level shift circuit|
According to one embodiment, a first cmos inverter receives an input signal corresponding to a first power supply voltage, and is driven by a second power supply voltage which is smaller than the first power supply voltage; a second cmos inverter is connected to a rear stage of the first cmos inverter, and is driven by the second power supply voltage; a first driving adjustment circuit adjusts a current driving force of a low level output of the first cmos inverter; and a second driving adjustment circuit adjusts a current driving force of a low level output of the second cmos inverter.. .
|Word line selection circuit and row decoder|
A first exemplary aspect of the present invention is a word line selection circuit where address decode signals composed of a power supply voltage and a first voltage lower than a ground voltage are input, and that a word line selection signal composed of the first voltage and a second voltage higher than the power supply voltage is output not via a level shift circuit according to the address decode signals.. .
|Abnormal voltage detecting device|
An abnormal voltage detecting device monitors abnormal decrease in monitoring voltage during a start up period of a voltage generating apparatus. The abnormal voltage detecting device comprises a level shift circuit that generates a reference voltage for a start up period by reducing, in a predetermined amount, voltage from a reference voltage for soft starting, and further comprises a three input comparator that receives a monitoring voltage, a reference voltage vref, and the reference voltage for the start up period, and that reverses a logical output when the monitoring voltage is lower than the reference voltage vref and the reference voltage for the start up period.
|Semiconductor integrated circuit and switching device|
A semiconductor circuit for supplying a signal for controlling a switching circuit includes a control terminal for receiving a control signal. The control signal is sent to a first inverter, which inverts the control signal to generate a first signal.
|Semiconductor device and manufacturing method of the same|
A semiconductor device includes a buffer layer formed with a semiconductor adapted to produce piezoelectric polarization, and a channel layer stacked on the buffer layer, wherein a two-dimensional hole gas, generated in the channel layer by piezoelectric polarization of the buffer layer, is used as a carrier of the channel layer. On a complementary semiconductor device, the semiconductor device described above and an n-type field effect transistor are formed on the same compound semiconductor substrate.
|Level shift circuit using parasitic resistor in semiconductor substrate|
A level shift circuit in which no adverse effect is produced on a delay time, regardless of the resistance values of resistors. The level shift circuit includes an operation detection circuit that outputs a nseten signal and a nresen signal in response to a state of output from first and second series circuits, a latch malfunction protection circuit connected to the operation detection circuit, a latch circuit connected through first to sixth resistors to first and second level shift output terminals of the first and second series circuits, first and second parasitic resistors, and third and fourth switching elements connected in parallel therewith, and fifth and sixth switching elements connected to a power source potential, a connection point of the first and second resistors or a connection point of the third and fourth resistors, and the operation detection circuit..
|Decoder circuit of semiconductor storage device|
The present invention provides a row decoder of a semiconductor storage device that prevents an increase in a circuit area while maintaining a high operation speed. Namely, the row decoder of the semiconductor storage device includes a word line selection circuit that has voltage application mos transistors for each of plural word lines, the voltage application mos transistors applying a normal voltage to the word lines corresponding to memory cells selected among plural memory cells positioned at a portion where the plural word lines intersect plural bit lines in a predetermined normal operation, and applying a high voltage in a predetermined high voltage operation; and a level shift circuit that outputs the normal voltage or a ground voltage lower than the normal voltage in the normal operation, and that outputs the normal voltage or the high voltage in the high voltage operation, to the voltage application mos transistor..
|Level shift circuit utilizing resistance in semiconductor substrate|
A level shift circuit does not affect delay time, regardless of the size of resistor resistance value. The level shift circuit includes first and second series circuits wherein first and second resistors and first and second switching elements are connected in series, rise detector circuits that compare the rise potentials of output signals of the first and second series circuits with a predetermined threshold value, and output first and second output signals, which are pulse outputs of a constant duration, when the threshold value is exceeded, and third and fourth switching elements connected in parallel to the first and second resistors respectively.
|Voltage level shift with interim-voltage-controlled contention interrupt|
Methods and systems to implement voltage level shifting with interim-voltage-controlled contention-interruption. A voltage level shifter (vls) may include voltage level shift circuitry to level shift an input logical state from an input voltage swing to an output voltage swing.
|Level shift circuit|
Provided is a level shift circuit which includes: a first level shift module; a first signal input terminal for providing a first input signal for the first level shift module; a first signal output terminal for providing output from the first level shift module; a second level shift module; a second signal input terminal for providing a second input signal for the second level shift module; a second signal output terminal for providing output from the second level shift module; a drive module connected to the first signal output terminal and the second signal output terminal; and a drive signal output terminal from the drive module. The level shift circuit of the present invention can be applicable for the requirements of bcd process and prevent damages to the high-voltage device due to the excessively high gate voltage..
|Level shift circuit and semiconductor device using level shift circuit|
A level shift circuit, for outputting a data output signal with a second level via an output inverter after a data input signal with a first level is stored in a latch, includes a level set circuit, when the output data signal outputs with a low level, setting the output data signal to a low level in response to a change of the input data signal. The level set circuit is connected to an output terminal of the output inverter, and has an nmos transistor having a drain electrode and a source electrode coupled to a ground, wherein the nmos transistor turns on in response to the input data signal with a high level..
|Level shift circuit|
A level shift circuit includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, a latch-type level shifter, a first current source and a second current source. The first input terminal receives an input signal; the second input terminal receives an inverse signal of the input signal; the first output terminal outputs an output signal; and the second output terminal outputs an inverse signal of the output signal.
|Semiconductor circuit, battery monitoring system, and diagnosis method|
A semiconductor circuit, battery monitoring system, diagnostic program and diagnosis method are provided enabling appropriate self-diagnosis of a measurement unit. An output value (a-b) output through respective power supply lines v (vn, vn−1), a cell selector switch, and a level shift circuit from an ad converter and an output value (b) of a directly input reference voltage b output from the ad converter are summed together.
|Motor drive circuit|
This document discusses, among other things, apparatus and methods for a motor drive, such as a haptic motor drive. In an example, a motor drive can include a low dropout (ldo) regulator configured to receive a supply voltage and to provide a regulated voltage, a power switch circuit configured to receive the supply voltage and to receive the regulated voltage from the ldo regulator, and a level shift circuit configured to receive power from the power switch circuit, to receive an input signal, and to provide an output signal to a a voltage difference generating circuit based on the input signal and the power from the power switch circuit.
|Voltage switching in a memory device|
Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit.
|Electrooptic device, method for driving electrooptic device and electronic apparatus|
An electrooptic device has a data line, a pixel circuit and a driver circuit which drives the pixel circuit. The driver circuit has a first feeder line, a level shift circuit to be electrically coupled with the data line and a driving control circuit which provides the first feeder line with a first voltage or a second voltage and controls operations of the level shift circuit and the pixel circuit.
|Level shift circuit|
A level shift circuit includes a first pair of transistors of the first conductive type (m1, m4) with sources coupled to a pair of input nodes (in, inb) and gates coupled to the first power supply (gnd) in common; a second pair of transistors of the second conductive type (m2, m5) with drains coupled to the drains of the first pair of the transistors and the gates coupled to the first power supply in common; a third pair of transistors of the second conductive type (m3, m6) with cross-coupled gates and drains coupled to the sources of the second pair of transistors and the sources coupled to the second power supply (v2) in common; and a pair of capacitative elements (c1, c2) with one ends coupled to the pair of input nodes and the other ends coupled to the drains of the third pair of transistors.. .
|Level shift circuit|
The invention provides a level shift circuit which uses a low supply voltage level shift circuit as a first level shift element and a high supply voltage level shift circuit as a second level shift element and which is configured to switch these level shift circuits in accordance with supply voltage. The low supply voltage level shift circuit is in an operating state with its power supply turned on when supply voltage is low and in a shut-down state with the power supply turned off to ensure the breakdown voltages of the elements when supply voltage is high.
|Level shift circuit and drive circuit of display device|
In a level shift circuit, input signals are input into gates of a first and a second mos transistors whose sources are coupled to a first supply voltage vss. Gates of a third and a fourth mos transistors whose sources are coupled to a second supply voltage are coupled to drains of the second and the first mos transistors.
|Phase compensation circuit, semiconductor integrated circuit having phase compensation circuit, and power supply circuit having phase compensation circuit|
In a power supply circuit, an error amplifier controls a main transistor based on a detection voltage according to an output voltage and a reference voltage corresponding to a target voltage of the output voltage such that the output voltage coincides with the target value. A phase compensation circuit for the power supply circuit includes a level shift circuit and a phase compensation capacitor.
|Lithium battery protection circuitry|
A lithium battery protection circuit coupled to a lithium battery is provided. The lithium battery protection circuit includes an over-charge protection circuit and a logic circuit coupled to over-charge protection circuit.
|Voltage level shift circuits and methods|
In one embodiment, the present invention includes a charge pump circuit. The charge pump circuit comprises a plurality of terminals, a plurality of switches for selectively coupling the plurality of terminals, and a control circuit.
|Level shift circuit|
In a level shift circuit allows satisfactory operation with short delay time in the case of low-voltage setting of a low-voltage source, for example, when a state of an input signal in transitions from a h (vdd) level to a l level, a node w2 precharged to a h (vdd3) level is discharged to ground (vss) by a discharge circuit n2, and decreases in potential. The decrease in potential propagates to a latch circuit la, and an output of the latch circuit la propagates to an output circuit oc.
|Cylinder inner pressure detector for internal combustion engine|
An cylinder inner pressure detector of an internal combustion engine includes: a reference voltage output circuit for outputting a reference voltage having a level, which is selected among multiple levels according to a switching signal; a level shift circuit for shifting a level of a sensor signal of an inner pressure sensor by a selected level of the reference voltage toward a signal potential side corresponding to a low pressure side of cylinder inner pressure; a first a/d converter circuit for converting the shifted sensor signal from an analog signal to a digital signal; and a controller for outputting the switching signal, which provides the reference voltage such that the reference voltage has the level on the signal potential side corresponding to the low pressure side from an offset voltage, and for detecting the cylinder inner pressure based on the digital signal output from the first a/d converter.. .
|Level shift circuit|
According to one embodiment, a level shift circuit includes a plurality of level shift units which are connected to each other and in which the delay time of the rising edge of an output voltage is different from the delay time of the falling edge of the output voltage. The delay time of the rising edge of the output voltage from the previous level shift unit is compensated by the delay time of the falling edge of the output voltage from the next level shift unit, and the delay time of the falling edge of the output voltage from the previous level shift unit is compensated by the delay time of the rising edge of the output voltage from the next level shift unit..
|Level shift circuit and display device provided with the same|
An object of the present invention is to provide a level shift ic with a reduced number of input signals over the conventional case. A level shift ic includes an amplitude converting unit including four level shifters; and a different-phase signal generating unit at a stage previous to the amplitude converting unit, including delay circuits.