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Level Shift Circuit patents

      

This page is updated frequently with new Level Shift Circuit-related patent applications.




 Level shift circuit and driver circuit patent thumbnailnew patent Level shift circuit and driver circuit
According to one embodiment, a level shift circuit includes first through fourth transistors, a control circuit, and first and second generating circuits. The control circuit outputs a first voltage obtained by level-shifting an input voltage to a first terminal.
Kabushiki Kaisha Toshiba


 Semiconductor device and power conversion device patent thumbnailSemiconductor device and power conversion device
Provided is a semiconductor device which drives a power semiconductor device, in which dead times generated when switch elements of upper and lower arms are turned on and off are minimized, and a loss of a power conversion device is reduced. A semiconductor device used in a power conversion device that includes a first switch element of which the drain is connected to a first power source voltage and a second switch element of which the source is connected to a second power source voltage includes a first drive circuit that drives the first switch element, a second drive circuit that drives the second switch element, a first level shift circuit, and a second level shift circuit.
Hitachi, Ltd.


 Drive circuit for semiconductor element and semiconductor device patent thumbnailDrive circuit for semiconductor element and semiconductor device
A primary circuit produces a first on-pulse and a first off-pulse synchronized with a rising edge and a falling edge of an input signal, respectively. A level shift circuit produces a second on-pulse and a second off-pulse formed by shifting the voltage level of the first on-pulse the first off-pulse, respectively.
Mitsubishi Electric Corporation


 Level shift circuit and semiconductor device patent thumbnailLevel shift circuit and semiconductor device
A level shift circuit includes: a latch circuit (q5, q6, q7, q8) including first (q5, q7) and second (q6, q8) inverter circuits; a first input mos transistor (q1) operating in accordance with an input signal; a second input mos transistor (q2) operating in accordance with an inversion signal of the input signal; and a current-voltage control mos transistor (q9). The latch circuit (q5, q6, q7, q8) outputs a voltage having been converted from the input voltage in level.
Renesas Electronics Corporation


 Pulsed level shift and inverter circuits for gan devices patent thumbnailPulsed level shift and inverter circuits for gan devices
Gan-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side gan device communicates through one or more level shift circuits with a high side gan device.
Navitas Semiconductor Inc.


 Level shift and inverter circuits for gan devices patent thumbnailLevel shift and inverter circuits for gan devices
Gan-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side gan device communicates through one or more level shift circuits with a high side gan device.
Navitas Semiconductor Inc.


 Half bridge driver circuits patent thumbnailHalf bridge driver circuits
Gan-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments, a low side gan device communicates through one or more level shift circuits with a high side gan device.
Navitas Semiconductor Inc.


 Integrated level shifter patent thumbnailIntegrated level shifter
Gan-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side gan device communicates through one or more level shift circuits with a high side gan device.
Navitas Semiconductor, Inc.


 Integrated bias supply, reference and bias current circuits for gan devices patent thumbnailIntegrated bias supply, reference and bias current circuits for gan devices
Gan-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side gan device communicates through one or more level shift circuits with a high side gan device.
Navitas Semiconductor Inc.


 Half bridge power conversion circuits using gan devices patent thumbnailHalf bridge power conversion circuits using gan devices
Gan-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side gan device communicates through one or more level shift circuits with a high side gan device.
Navitas Semiconductor Inc.


Bootstrap capacitor charging circuit for gan devices


Gan-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side gan device communicates through one or more level shift circuits with a high side gan device.
Navitas Semiconductor Inc.


Protection monitoring circuit, battery pack, secondary battery monitoring circuit, and protection circuit


A protection monitoring circuit includes a protection circuit which detects overcharge, overdischarge, and overcurrent of a secondary battery, and a secondary battery monitoring circuit which monitors a state of the secondary battery and detects a residual quantity of the secondary battery. The protection circuit includes a first communication terminal that is connected to the secondary battery monitoring circuit, a second communication terminal that is connected to a mobile device, and a level shift circuit that is connected to the first and second communication terminals.
Mitsumi Electric Co., Ltd.


Gate driving circuit of high-side transistor, switching output circuit, inverter device, and electronic device


A gate driving circuit for turning on a high-side transistor when an input set pulse is asserted and turning off the high-side transistor when an input reset pulse is asserted is provided. The gate driving circuit includes first and second inverters to receive the intermediate set pulse from a level shift circuit to generate first and second set pulses; third and fourth inverters to receive the intermediate reset pulse from the level shift circuit to generate first and second reset pulses; a logic circuit to mask the first set pulse and the first reset pulse by using the second reset pulse and the second set pulse to generate an output set pulse and an output reset pulse, respectively; a flip-flop configured to receive the output set pulse and the output reset pulse to output a driving pulse; and a driver to drive the high-side transistor according to the driving pulse..
Rohm Co., Ltd.


Semiconductor device, power control device and electronic system


In order to reduce the cost and the like of a power control device including a semiconductor device such as a driver ic, as well as an electronic system, the driver ic includes a high side driver, a level shift circuit, first and second transistors, and a comparator circuit. The first transistor is formed in a termination area.
Renesas Electronics Corporation


Level shift circuit with short-circuit detection mechanism and short-circuit detection method thereof


A level shift circuit includes a level shift module and a voltage comparing module. The level shift module includes a plurality of stages of level shift units, each including a front-end circuit and an inverter circuit.
Au Optronics Corp.


Level shift circuit and drive circuit of display device


A display driver includes an input node for receiving display data, a level shift circuit configured to convert voltage level of the display data and output a first voltage and a second voltage based on the display data, an output node for outputting the output display data, a first p-channel mos transistor coupled to the output node, whose gate is configured to input the first voltage, and a first n-channel mos transistor coupled to the output node, whose gate is configured to input the second voltage, wherein a voltage difference between the second voltage and the first voltage varies based on the display data.. .
Renesas Electronics Corporation


Drive circuit and semiconductor device


Malfunction can be reliably avoided even when a signal that drives a high side power device is not normally transmitted in a level shift circuit. In a drive circuit, a pulse generator circuit generates a set signal and reset signal that causes a high side power device to be turned on or off.
Fuji Electric Co., Ltd.


Driver circuit incorporating level shift circuit


A level shift circuit includes first and second nmos transistors that are coupled between a first supply terminal, and first and second output nodes, respectively, and have respective control terminals receiving input signals of a low amplitude, third and fourth pmos transistors which are coupled between a second supply terminal, and the first and second output nodes outputting signals of high amplitude, respectively, a fifth pmos transistor which is coupled between a gate of the third pmos transistor and the second output node, and has a gate coupled to the first output node, a sixth pmos transistor which is coupled between a gate of the fourth pmos transistor and the first output node, and has a gate coupled to the second output node, and first and second load elements which are coupled between the second supply terminal and the gates of the third and fourth pmos transistors, respectively.. .
Renesas Electronics Corporation


Level shift circuit, gate driving circuit and display apparatus


Provided are a level shift circuit, a gate driving circuit and a display apparatus. The level shift circuit comprises a third transistor (m3), a fourth transistor (m4), a fifth transistor (m5), a sixth transistor (m6) and a seventh transistor (m0), the sources of the which transistors are connected to a dc power source (vdd) respectively, and the gates of which transistors are connected to an offset voltage terminal (vbias) respectively, wherein the drains of the third transistor (m3) and the fifth transistor (m5) are connected as a first output terminal (out1), the drains of the fourth transistor (m4) and the sixth transistor (m6) are connected as a second output terminal (out2); and a first transistor (m1) and a second transistor (m2), the gates of which transistors are both connected to an input signal terminal (vin), the sources of which transistors are both connected to the drain of the seventh transistor (m0), wherein the drain of the first transistor (m1) is connected to the first output terminal (out1), the drain of the second transistor (m2) is connected to the second output terminal (out2); a seventh transistor (m0), the source of the seventh transistor (m0) is connected to a reference ground (vss), and the gate of the seventh transistor (m0) is connected to the offset voltage terminal (bbias).
Beijing Boe Display Technology Co., Ltd.


Level shift circuit, electro-optical apparatus, and electronic equipment


To realize a level shift circuit with the small occupation area and capable of performing high-speed operation, a level shift circuit includes an electric potential converting unit that converts a first electric potential of an input signal to a third electric potential and converts a second electric potential of an input signal to a fourth electric potential. A capacitor includes first and second electrodes, the first electrode being electrically connected to the input unit, and the second electrode being electrically connected to an output node of the electric potential converting unit.
Seiko Epson Corporation


Semiconductor device and power converter equipment


A semiconductor device that has a level shift circuit, an anterior stage circuit, and a posterior stage circuit. The level shift circuit transmits an input signal from a primary potential system to a secondary potential system different from the primary potential system.
Fuji Electric Co., Ltd.


Level shift driver circuit capable of reducing gate-induced drain leakage current


A level shift driver circuit comprises a level shift circuit and a driver circuit. The driver circuit comprises a first and a second p-type transistors and a first and a second n-type transistors coupled in series.
Ememory Technology Inc.


Level shift circuit, array substrate and display device


The present invention provides a level shift circuit, an array substrate and a display device. The level shift circuit comprising: a first level non-inverting input terminal, a first level inverting input terminal, a second level non-inverting input terminal, a second level inverting input terminal, a level state transferring unit and a second level driving unit; the level state transferring unit receives a first level input through the first level non-inverting input terminal and the first level inverting input terminal, and transfers a high and low state of the input first level to the second level driving unit; the second level driving unit outputs a second level of a corresponding state to the second level non-inverting input terminal and the second level inverting input terminal according to the input high and low state, wherein the first level is not equal to the second level..
Hefei Boe Optoelectronics Technology Co., Ltd.


Level shift circuit


Provided is a high-reliability level shift circuit not prone to faulty operation due to noise. A level shift circuit 1 is provided with: first and second current control elements 12a and 12b into control terminals of which a reverse-phase input signal and an in-phase input signal are input, respectively; first and second load circuits 13a and 13b which are connected at one end to a high-side power source terminal vb and at the other end to each of first terminals of the first and second current control elements 12a and 12b; a comparator 14 in which a pair of differential input terminals np and nn are connected separately to each of the first terminals of the first and second current control elements 12a and 12b; a current generating circuit 3 in which first and second current output terminals na and nb are connected to second terminals of the first and second current control elements 12a and 12b, and which separately generates a current which flows through the respective first and second current control elements 12a and 12b; and voltage suppressing circuits 15a and 15b which are connected separately or commonly to the first and second current output terminals na and nb, respectively, and suppress voltage from rising in the first and second current output terminals na and nb, respectively..
Sharp Kabushiki Kaisha


Level shift circuit


A level shift circuit includes a first pair of transistors of the first conductive type (m1, m4) with sources coupled to a pair of input nodes (in, inb) and gates coupled to the first power supply (gnd) in common; a second pair of transistors of the second conductive type (m2, m5) with drains coupled to the drains of the first pair of the transistors and the gates coupled to the first power supply in common; a third pair of transistors of the second conductive type (m3, m6) with cross-coupled gates and drains coupled to the sources of the second pair of transistors and the sources coupled to the second power supply (v2) in common; and a pair of capacitative elements (c1, c2) with one ends coupled to the pair of input nodes and the other ends coupled to the drains of the third pair of transistors.. .
Renesas Electronics Corporation


Semiconductor device and manufacturing the same


A semiconductor device includes a buffer layer formed with a semiconductor adapted to produce piezoelectric polarization, and a channel layer stacked on the buffer layer, wherein a two-dimensional hole gas, generated in the channel layer by piezoelectric polarization of the buffer layer, is used as a carrier of the channel layer. On a complementary semiconductor device, the semiconductor device described above and an n-type field effect transistor are formed on the same compound semiconductor substrate.
Sony Corporation


Level shift circuit


A level shift circuit of an embodiment includes: an input circuit configured to receive an input signal and connected to first and second power supply lines; first and second signal paths connected in parallel between the first power supply line and a third power supply line; first and second switching elements configured to control conduction of the first and second signal paths, respectively, based on the input signal; first and second diodes and a cross-coupled circuit arranged towards the third power supply line on the first and second signal paths; and an output circuit connected to the third power supply line and a fourth power supply line, and configured to output an output signal based on at least one of a signal appearing at a first node at one end of the first diode and a signal appearing at a second node at one end of the second diode.. .
Kabushiki Kaisha Toshiba


Semiconductor device


A semiconductor device or the like capable of preventing malfunction of a driver circuit is provided. In a driver circuit for driving a power device used for current supply, a transistor including an oxide semiconductor is used as a transistor in a circuit (specifically, for example, a level shift circuit) requiring a high withstand voltage.
Semiconductor Energy Laboratory Co., Ltd.


Voltage regulator and semiconductor device


Provided is a voltage regulator including a clamp circuit capable of protecting a gate of an output transistor without limiting a drivability of the output transistor. The voltage regulator includes a level shift circuit having an input terminal connected to the gate of the output transistor and an output terminal connected to an input of the clamp circuit.
Seiko Instrument Inc.


Voltage detection device


A first part circuit and an operational amplifier form a level shift circuit, which selects either one of battery cells forming an assembled battery and extracts and holds a voltage representing an inter-terminal voltage of a selected battery cell. A second part circuit and the operational amplifier form a residual voltage generation circuit, which generates a residual voltage by amplifying a differential voltage between a conversion subject voltage and an analog voltage corresponding to a conversion result of an a/d conversion circuit and applies the residual voltage to the a/d conversion circuit as a conversion subject voltage.
Denso Corporation


Level shift circuit utilizing resistance in semiconductor substrate


An apparatus such as a level shift circuit includes a first signal output device configured to output a first level shifting signal, a second signal output device configured to output a second level shifting signal, and first and second detector devices. The level shifting signals are to control an output switching element of a high potential side of an output device that includes a power source and a load.
Fuji Electric Co., Ltd.


Level shift circuit and dc-dc converter for using the same


A level shift circuit and a dc-dc buck converter controller for using the same are disclosed. The level shift circuit is capable of detecting a state of a converting circuit, and avoids a current leakage when determining that the converting circuit is operating under a light-load.

Phase locked loop circuit


A phase locked loop (pll) circuit is provided. The pll includes a voltage controlled oscillator (vco) for outputting an oscillation signal of a frequency corresponding to an inputted voltage, a frequency divider for dividing the oscillation signal and output a frequency-divided signal, a phase comparator for comparing a phase of the frequency-divided signal and the phase of an input signal from the outside and output a first phase comparison signal and a second phase comparison signal which have different polarities, a differential amplifier circuit for outputting a control voltage based on a voltage difference between the first phase comparison signal and the second phase comparison signal to the vco, a level shift circuit for outputting a level-shifted signal which is made by shifting a direct current level of the second phase comparison signal, and an amplifier circuit for outputting an amplified signal which is an amplified level-shifted signal..
Nihon Dempa Kogyo Co., Ltd.


Level shift circuit and semiconductor device


A level shift circuit includes: a latch circuit (q5, q6, q7, q8) including first (q5, q7) and second (q6, q8) inverter circuits; a first input mos transistor (q1) operating in accordance with an input signal; a second input mos transistor (q2) operating in accordance with an inversion signal of the input signal; and a current-voltage control mos transistor (q9). The latch circuit (q5, q6, q7, q8) outputs a voltage having been converted from the input voltage in level.
Renesas Electronics Corporation


Equalization device for assembled battery


In an equalization device for equalizing voltages of battery cells connected in series, each battery cell is provided with an equalization switch and a level shift section. The level shift section includes at least one level shift circuit.
Denso Corporation


Semiconductor device having level shift circuit


A semiconductor device includes: two level shift circuits having substantially the same circuit configuration; an input circuit that supplies complementary input signals to the level shift circuits, respectively; and an output circuit that converts complementary output signals output from the level shift circuits into in-phase signals and then short-circuits the in-phase signals. According to the present invention, the two level shift circuits having substantially the same circuit configuration are used, and the complementary output signals output from the level shift circuits are converted into in-phase signals before short-circuited.
Ps4 Luxco S.a.r.l.


Level shift circuit with automatic timing control of charging transistors, and driver circuit having the same


A level shift circuit includes first and second nmos transistors that are coupled between a first supply terminal, and first and second output nodes, respectively, and have respective control terminals receiving input signals of a low amplitude, third and fourth pmos transistors which are coupled between a second supply terminal, and the first and second output nodes outputting signals of high amplitude, respectively, a fifth pmos transistor which is coupled between a gate of the third pmos transistor and the second output node, and has a gate coupled to the first output node, a sixth pmos transistor which is coupled between a gate of the fourth pmos transistor and the first output node, and has a gate coupled to the second output node, and first and second load elements which are coupled between the second supply terminal and the gates of the third and fourth pmos transistors, respectively.. .
Renesas Electronics Corporation


Communication circuit apparatus and transceiver having the same


A communication circuit apparatus includes: multiple level shift circuits, each of which receives an input signal corresponding to a respective communication bus; an activation comparator for generating an activation signal when the input signal is input into one of the level shift circuits, and a level of the input signal exceeds a predetermined threshold; multiple input current voltage conversion circuits, each of which is arranged together with a respective level shift circuit, converts the input signal to a voltage signal, and outputs the voltage signal as an identification signal; and an identification circuit for identifying one of the communication busses based on the identification signal, which is output from one of the input current voltage conversion circuits. The one of the communication busses corresponds to the one of the level shift circuits, in which the input signal is input..
Denso Corporation


Nonvolatile semiconductor memory device


A nonvolatile semiconductor memory device comprises a memory cell array, a staircase voltage generator, and a decode and level shift circuit. The memory cell array comprises a plurality of memory cells and a plurality of bit lines coupled to the plurality of memory cells.
Elite Semiconductor Memory Technology Inc.


Semiconductor device and power conversion device using the same


In a semiconductor device such as a three-phase one-chip gate driver ic, hvnmoss configuring two set and reset level shift circuits are disposed on non-opposed surfaces, and it is thereby possible to reduce the amount of electrons flowing into drains of hvnmoss of another phase due to a negative voltage surge. Also, distances from an opposed surface on the opposite side to the respective drains of the hvnmoss configuring the two set and reset level shift circuits are made equal to or more than 150 μm, and it is thereby possible to prevent a malfunction of a high side driver circuit of another phase to which no negative surge is applied..
Fuji Electric Co., Ltd.


Driver and driving control power converter


A driver and a driving control method for a power converter are provided. The driver includes a level shift circuit, a negative voltage generator and a first pmos transistor.
Upi Semiconductor Corp.


Voltage level shift circuit for multiple voltage integrated circuits


A voltage level shift circuit comprises a first pair of transistors and a second pair of transistors. A first transistor of the second pair of transistors is coupled with an input signal terminal.
Taiwan Semiconductor Manufacturing Company, Ltd.


Semiconductor device having level shift circuit


Disclosed herein is a device includes; a level conversion circuit coupled to first and third power supply lines, receiving a first signal and an inverted signal of the first signal each having an amplitude between first and second potentials, and output ting a second signal having an amplitude between first and third potentials; a delay circuit coupled to the first and second power supply lines, and output ting a third signal delayed from the first signal; and an output circuit including first and second transistors coupled in series between the first and third power supply lines, the first transistor having a control electrode supplied with the second signal, and the second transistor having a control electrode supplied with the third signal.. .
Micron Technology, Inc.


Timing controller for liquid crystal panel and timing control method thereof


A timing controller for a liquid crystal panel and a timing control method thereof are provided. The timing controller includes a timing control unit for analyzing an input signal to generate a system state transition voltage (stv) signal and a base stv signal, and the timing control unit outputs a base trigger signal and a switch trigger signal having asynchronous frame rates to a select unit at the same time.
Chunghwa Picture Tubes, Ltd.


Level shift circuit


A level shift circuit of an embodiment includes first and second mosfets using signals with phases same as and opposite to the phase of an input signal as gate inputs; first and second resistance elements, each having one end connected to a shift level power terminal that supplies high-level output voltage of a level-shifted output signal, and each having the other end connected to a corresponding drain of the first and second mosfets; a comparator having a pair of differential input terminals, individually connected to respective drains of the first and second mosfets; and a current control circuit that controls an amount of first current flowing through the first mosfet via the first resistance element and an amount of second current flowing through the second mosfet via the second resistance element in synchronization with a rising and a falling of a signal level of the input signal.. .

Semiconductor device


In aspects of the invention, a semiconductor device can include one level shift circuit that outputs a low-side input signal as a high-side signal upon raising a signal level, a pulse modulation circuit that operates in a low-side region, generates a data symbol constituted by or more bits and representing a set signal or a reset signal, where bit is defined as a combination of codes forming a pair. The pulse generation circuit can output the generated data symbol as an input signal of the level shift circuit.

Word line selection circuit and row decoder


A first exemplary aspect of the present invention is a word line selection circuit where address decode signals composed of a power supply voltage and a first voltage lower than a ground voltage are input, and that a word line selection signal composed of the first voltage and a second voltage higher than the power supply voltage is output not via a level shift circuit according to the address decode signals.. .

High-voltage heavy-current drive circuit applied in power factor corrector


A high-voltage heavy-current drive circuit applied in a power factor corrector, comprising a current mirroring circuit (1), a level shift circuit (3), a high-voltage pre-modulation circuit (2), a dead time control circuit (4) and a heavy-current output stage (5); the heavy-current output stage adopts a darlington output stage structure to increase the maximum operating frequency of the drive circuit. The stabilized breakdown voltage characteristic of a voltage stabilizing diode is utilized to ensure the drive circuit operating within a safe voltage range.

Solid-state imaging device and imaging apparatus


A solid-state imaging device according to the present disclosure includes: a pixel unit in which unit pixels are arranged two-dimensionally, each of the unit pixels including: a photodiode which stores signal charges; a transfer transistor for transferring the signal charges stored in the photodiode; a charge detection unit which temporarily stores the transferred signal charges; and a reset transistor for resetting the signal charges stored in the charge detection unit; and a vertical scanning unit which drives the pixel unit, the vertical scanning unit including: a row selection unit; a level shift circuit for converting a level of an externally inputted power supply voltage; and a buffer circuit for buffering a voltage whose level has been converted by the level shift circuit, the level shift circuit including: a step-down level shift circuit; and a step-up level shift circuit isolated from the step-down level shift circuit by a well.. .

Methods and systems for interconnecting host and expansion devices within system-in-package (sip) solutions


Methods and systems are disclosed for interconnecting die-to-die-port (dtdp) host devices and dtdp expansion devices for combined system-in-package (sip) solutions. Interconnect circuitry having a plurality of ports is configured to provide communication from the host device to the expansion device so that the expansion device appears to be resident on the host device.

Level shift circuit and driving method thereof


A level shift circuit includes an input end, a decoding circuit, a control circuit, and a plurality of output circuits. The input end is configured to receive a coded signal string including a starting code, a setting code, a clock standard signal and an ending code.

Voltage level conversion circuits and display devices including the same


A voltage level conversion circuit includes a voltage switch circuit and a level shift circuit. The voltage switch circuit is configured to sequentially output an intermediate voltage and a conversion voltage in response to a switch signal.

Level shift circuit


There is provided a level shift circuit free from malfunction. The level shift circuit converts a signal of a first power supply voltage of a first supply terminal, which is supplied to an input terminal, into a signal of a second power supply voltage of a second supply terminal and outputs the converted signal to an output terminal.

High voltage semiconductor device


An n well region and an n−region surrounding the n well region are provided in the surface layer of a p−silicon substrate. The n−region includes breakdown voltage regions in which high voltage mosfets are disposed.

Voltage level shift circuit for multiple voltage integrated circuits


An over-driver, voltage level shift circuit for use with multiple voltage integrated circuits. The voltage level shift circuit includes a first pair of pmos transistors, a second pair pmos transistors and a third pair of pmos transistors using a high supply voltage source vddh and a low supply voltage source to voltage level shift input signals having a first voltage operating range to an output signal having a second voltage operating range higher then the first voltage operating range.

Driver integrated circuit


Provided is a configuration of a driver integrated circuit that can output a voltage exceeding the withstand voltage of a process, and that satisfies required apparatus performance (high speed and high voltage). A differential input circuit, a level shift circuit, and an output circuit are manufactured by the same process and divided and disposed on three or more chips with different substrate potentials (sub-potentials).

Light reception circuit and light reception device


A light reception circuit includes a direct current (dc) level shift circuit that shifts a dc voltage level of a first signal or a second signal and outputs a third signal or a fourth signal, or outputs both of the third signal and the fourth signal so that a dc voltage level of the first signal output from a cathode of a photodiode that generates a signal by photo conversion and a dc voltage level of the second signal output from an anode of the photodiode agree, and a differential amplifier that amplifies a difference between the third signal and the second signal, between the first signal and the fourth signal, or the third signal and the fourth signal, based on the third signal, the forth signal output from the dc level shift circuit, impedance of the dc level shift circuit being lower than input impedance of the differential amplifier.. .

Semiconductor integrated circuit with esd protection circuit


According to an embodiment, a semiconductor integrated circuit includes a first power supply terminal, a second power supply terminal, a regulator circuit, an electrostatic discharge (esd) protection circuit, and a level shift circuit. A first voltage is applied to the first power supply terminal.

Inverse level shift circuit


A voltage conversion mask signal generation circuit generates a first main signal and a first mask signal by converting an output signal of the first transistor to a low-side voltage, and generating a second main signal and a second mask signal by converting an output signal of the second transistor to a low-side voltage. A mask signal generation circuit generating a third mask signal with higher sensitivity than the first and second mask signals with respect to a fluctuation in the high-side reference potential.

Level shift circuit


According to one embodiment, a first cmos inverter receives an input signal corresponding to a first power supply voltage, and is driven by a second power supply voltage which is smaller than the first power supply voltage; a second cmos inverter is connected to a rear stage of the first cmos inverter, and is driven by the second power supply voltage; a first driving adjustment circuit adjusts a current driving force of a low level output of the first cmos inverter; and a second driving adjustment circuit adjusts a current driving force of a low level output of the second cmos inverter.. .

Word line selection circuit and row decoder


A first exemplary aspect of the present invention is a word line selection circuit where address decode signals composed of a power supply voltage and a first voltage lower than a ground voltage are input, and that a word line selection signal composed of the first voltage and a second voltage higher than the power supply voltage is output not via a level shift circuit according to the address decode signals.. .

Abnormal voltage detecting device


An abnormal voltage detecting device monitors abnormal decrease in monitoring voltage during a start up period of a voltage generating apparatus. The abnormal voltage detecting device comprises a level shift circuit that generates a reference voltage for a start up period by reducing, in a predetermined amount, voltage from a reference voltage for soft starting, and further comprises a three input comparator that receives a monitoring voltage, a reference voltage vref, and the reference voltage for the start up period, and that reverses a logical output when the monitoring voltage is lower than the reference voltage vref and the reference voltage for the start up period.

Semiconductor integrated circuit and switching device


A semiconductor circuit for supplying a signal for controlling a switching circuit includes a control terminal for receiving a control signal. The control signal is sent to a first inverter, which inverts the control signal to generate a first signal.

Semiconductor device and manufacturing the same


A semiconductor device includes a buffer layer formed with a semiconductor adapted to produce piezoelectric polarization, and a channel layer stacked on the buffer layer, wherein a two-dimensional hole gas, generated in the channel layer by piezoelectric polarization of the buffer layer, is used as a carrier of the channel layer. On a complementary semiconductor device, the semiconductor device described above and an n-type field effect transistor are formed on the same compound semiconductor substrate.

Level shift circuit using parasitic resistor in semiconductor substrate


A level shift circuit in which no adverse effect is produced on a delay time, regardless of the resistance values of resistors. The level shift circuit includes an operation detection circuit that outputs a nseten signal and a nresen signal in response to a state of output from first and second series circuits, a latch malfunction protection circuit connected to the operation detection circuit, a latch circuit connected through first to sixth resistors to first and second level shift output terminals of the first and second series circuits, first and second parasitic resistors, and third and fourth switching elements connected in parallel therewith, and fifth and sixth switching elements connected to a power source potential, a connection point of the first and second resistors or a connection point of the third and fourth resistors, and the operation detection circuit..

Decoder circuit of semiconductor storage device


The present invention provides a row decoder of a semiconductor storage device that prevents an increase in a circuit area while maintaining a high operation speed. Namely, the row decoder of the semiconductor storage device includes a word line selection circuit that has voltage application mos transistors for each of plural word lines, the voltage application mos transistors applying a normal voltage to the word lines corresponding to memory cells selected among plural memory cells positioned at a portion where the plural word lines intersect plural bit lines in a predetermined normal operation, and applying a high voltage in a predetermined high voltage operation; and a level shift circuit that outputs the normal voltage or a ground voltage lower than the normal voltage in the normal operation, and that outputs the normal voltage or the high voltage in the high voltage operation, to the voltage application mos transistor..

Level shift circuit utilizing resistance in semiconductor substrate


A level shift circuit does not affect delay time, regardless of the size of resistor resistance value. The level shift circuit includes first and second series circuits wherein first and second resistors and first and second switching elements are connected in series, rise detector circuits that compare the rise potentials of output signals of the first and second series circuits with a predetermined threshold value, and output first and second output signals, which are pulse outputs of a constant duration, when the threshold value is exceeded, and third and fourth switching elements connected in parallel to the first and second resistors respectively.

Voltage level shift with interim-voltage-controlled contention interrupt


Methods and systems to implement voltage level shifting with interim-voltage-controlled contention-interruption. A voltage level shifter (vls) may include voltage level shift circuitry to level shift an input logical state from an input voltage swing to an output voltage swing.

Level shift circuit


Provided is a level shift circuit which includes: a first level shift module; a first signal input terminal for providing a first input signal for the first level shift module; a first signal output terminal for providing output from the first level shift module; a second level shift module; a second signal input terminal for providing a second input signal for the second level shift module; a second signal output terminal for providing output from the second level shift module; a drive module connected to the first signal output terminal and the second signal output terminal; and a drive signal output terminal from the drive module. The level shift circuit of the present invention can be applicable for the requirements of bcd process and prevent damages to the high-voltage device due to the excessively high gate voltage..

Level shift circuit and semiconductor device using level shift circuit


A level shift circuit, for outputting a data output signal with a second level via an output inverter after a data input signal with a first level is stored in a latch, includes a level set circuit, when the output data signal outputs with a low level, setting the output data signal to a low level in response to a change of the input data signal. The level set circuit is connected to an output terminal of the output inverter, and has an nmos transistor having a drain electrode and a source electrode coupled to a ground, wherein the nmos transistor turns on in response to the input data signal with a high level..

Level shift circuit


A level shift circuit includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, a latch-type level shifter, a first current source and a second current source. The first input terminal receives an input signal; the second input terminal receives an inverse signal of the input signal; the first output terminal outputs an output signal; and the second output terminal outputs an inverse signal of the output signal.

Semiconductor circuit, battery monitoring system, and diagnosis method


A semiconductor circuit, battery monitoring system, diagnostic program and diagnosis method are provided enabling appropriate self-diagnosis of a measurement unit. An output value (a-b) output through respective power supply lines v (vn, vn−1), a cell selector switch, and a level shift circuit from an ad converter and an output value (b) of a directly input reference voltage b output from the ad converter are summed together.

Motor drive circuit


This document discusses, among other things, apparatus and methods for a motor drive, such as a haptic motor drive. In an example, a motor drive can include a low dropout (ldo) regulator configured to receive a supply voltage and to provide a regulated voltage, a power switch circuit configured to receive the supply voltage and to receive the regulated voltage from the ldo regulator, and a level shift circuit configured to receive power from the power switch circuit, to receive an input signal, and to provide an output signal to a a voltage difference generating circuit based on the input signal and the power from the power switch circuit.

Voltage switching in a memory device


Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit.

Electrooptic device, driving electrooptic device and electronic apparatus


An electrooptic device has a data line, a pixel circuit and a driver circuit which drives the pixel circuit. The driver circuit has a first feeder line, a level shift circuit to be electrically coupled with the data line and a driving control circuit which provides the first feeder line with a first voltage or a second voltage and controls operations of the level shift circuit and the pixel circuit.

Level shift circuit


A level shift circuit includes a first pair of transistors of the first conductive type (m1, m4) with sources coupled to a pair of input nodes (in, inb) and gates coupled to the first power supply (gnd) in common; a second pair of transistors of the second conductive type (m2, m5) with drains coupled to the drains of the first pair of the transistors and the gates coupled to the first power supply in common; a third pair of transistors of the second conductive type (m3, m6) with cross-coupled gates and drains coupled to the sources of the second pair of transistors and the sources coupled to the second power supply (v2) in common; and a pair of capacitative elements (c1, c2) with one ends coupled to the pair of input nodes and the other ends coupled to the drains of the third pair of transistors.. .

Level shift circuit


The invention provides a level shift circuit which uses a low supply voltage level shift circuit as a first level shift element and a high supply voltage level shift circuit as a second level shift element and which is configured to switch these level shift circuits in accordance with supply voltage. The low supply voltage level shift circuit is in an operating state with its power supply turned on when supply voltage is low and in a shut-down state with the power supply turned off to ensure the breakdown voltages of the elements when supply voltage is high.

Level shift circuit and drive circuit of display device


In a level shift circuit, input signals are input into gates of a first and a second mos transistors whose sources are coupled to a first supply voltage vss. Gates of a third and a fourth mos transistors whose sources are coupled to a second supply voltage are coupled to drains of the second and the first mos transistors.

Phase compensation circuit, semiconductor integrated circuit having phase compensation circuit, and power supply circuit having phase compensation circuit


In a power supply circuit, an error amplifier controls a main transistor based on a detection voltage according to an output voltage and a reference voltage corresponding to a target voltage of the output voltage such that the output voltage coincides with the target value. A phase compensation circuit for the power supply circuit includes a level shift circuit and a phase compensation capacitor.

Lithium battery protection circuitry


A lithium battery protection circuit coupled to a lithium battery is provided. The lithium battery protection circuit includes an over-charge protection circuit and a logic circuit coupled to over-charge protection circuit.

Voltage level shift circuits and methods


In one embodiment, the present invention includes a charge pump circuit. The charge pump circuit comprises a plurality of terminals, a plurality of switches for selectively coupling the plurality of terminals, and a control circuit.

Level shift circuit


In a level shift circuit allows satisfactory operation with short delay time in the case of low-voltage setting of a low-voltage source, for example, when a state of an input signal in transitions from a h (vdd) level to a l level, a node w2 precharged to a h (vdd3) level is discharged to ground (vss) by a discharge circuit n2, and decreases in potential. The decrease in potential propagates to a latch circuit la, and an output of the latch circuit la propagates to an output circuit oc.

Cylinder inner pressure detector for internal combustion engine


An cylinder inner pressure detector of an internal combustion engine includes: a reference voltage output circuit for outputting a reference voltage having a level, which is selected among multiple levels according to a switching signal; a level shift circuit for shifting a level of a sensor signal of an inner pressure sensor by a selected level of the reference voltage toward a signal potential side corresponding to a low pressure side of cylinder inner pressure; a first a/d converter circuit for converting the shifted sensor signal from an analog signal to a digital signal; and a controller for outputting the switching signal, which provides the reference voltage such that the reference voltage has the level on the signal potential side corresponding to the low pressure side from an offset voltage, and for detecting the cylinder inner pressure based on the digital signal output from the first a/d converter.. .

Level shift circuit


According to one embodiment, a level shift circuit includes a plurality of level shift units which are connected to each other and in which the delay time of the rising edge of an output voltage is different from the delay time of the falling edge of the output voltage. The delay time of the rising edge of the output voltage from the previous level shift unit is compensated by the delay time of the falling edge of the output voltage from the next level shift unit, and the delay time of the falling edge of the output voltage from the previous level shift unit is compensated by the delay time of the rising edge of the output voltage from the next level shift unit..

Level shift circuit and display device provided with the same


An object of the present invention is to provide a level shift ic with a reduced number of input signals over the conventional case. A level shift ic includes an amplitude converting unit including four level shifters; and a different-phase signal generating unit at a stage previous to the amplitude converting unit, including delay circuits.



Level Shift Circuit topics:
  • Level Shift
  • Level Shift Circuit
  • Semiconductor
  • Transistors
  • Semiconductor Substrate
  • Level Shifter
  • Voltage Level Shift
  • Reference Voltage
  • Protection Circuit
  • Adverse Effect
  • Memory Cell
  • Storage Device
  • Memory Cells
  • Row Decoder
  • Voltage Level Shifter


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