Popular terms

[SEARCH]

Lattice topics
Semiconductor
Semiconductor Device
Semiconductor Material
Crystallin
Disconnect
Transistors
Replacement Gate
Semiconductor Devices
Dislocations
Dislocation
Image Processing
Coordinates
Surface Plasmon Polariton
Antenna Array

Follow us on Twitter
twitter icon@FreshPatents

Web & Computing
Cloud Computing
Ecommerce
Search patents
Smartphone patents
Social Media patents
Video patents
Website patents
Web Server
Android patents
Copyright patents
Database patents
Programming patents
Wearable Computing
Webcam patents

Web Companies
Apple patents
Google patents
Adobe patents
Ebay patents
Oracle patents
Yahoo patents

[SEARCH]

Lattice patents



      
           
This page is updated frequently with new Lattice-related patent applications. Subscribe to the Lattice RSS feed to automatically get the update: related Lattice RSS feeds. RSS updates for this page: Lattice RSS RSS


Embedded source or drain region of transistor with downward tapered region under facet region

Taiwan Semiconductor Manufacturing

Embedded source or drain region of transistor with downward tapered region under facet region

Nanowire article and processes for making and using same

National Institute Of Standards And Technology

Nanowire article and processes for making and using same


Date/App# patent app List of recent Lattice-related patents
07/30/15
20150214470 
 Piezoelectric element,  manufacturing piezoelectric element, and electronic apparatus patent thumbnailnew patent Piezoelectric element, manufacturing piezoelectric element, and electronic apparatus
A piezoelectric element includes a piezoelectric material portion. The piezoelectric material portion is made of a piezoelectric ceramic that includes a perovskite-type metal oxide including barium titanate and mn and that has residual polarization.
Canon Kabushiki Kaisha


07/30/15
20150214469 
 Piezoelectric ceramic,  manufacturing the same, piezoelectric element, and electronic apparatus patent thumbnailnew patent Piezoelectric ceramic, manufacturing the same, piezoelectric element, and electronic apparatus
A piezoelectric ceramic includes a perovskite-type metal oxide containing barium titanate, and mn. When a surface thereof along the remanent polarization direction is subjected to x-ray diffraction analysis at room temperature, the ratio of the diffraction intensity of the (002) plane to the diffraction intensity of the (200) plane is 1.0 or more, the diffraction peak of the (002) plane has a half width of 1.2° or less, and the lattice constant of the c-axis thereof and the lattice constant of the a-axis thereof satisfy the relationship 1.004≦c/a≦1.010..
Canon Kabushiki Kaisha


07/30/15
20150214412 
 Lattice matchable alloy for solar cells patent thumbnailnew patent Lattice matchable alloy for solar cells
An alloy composition for a subcell of a solar cell is provided that has a bandgap of at least 0.9 ev, namely, ga1-xinxnyas1-y-zsbz with a low antimony (sb) content and with enhanced indium (in) content and enhanced nitrogen (n) content, achieving substantial lattice matching to gaas and ge substrates and providing both high short circuit currents and high open circuit voltages in gainnassb subcells for multijunction solar cells. The composition ranges for ga1-xinxnyas1-y-zsbz are 0.07≦x≦0.18, 0.025≦y≦0.04 and 0.001≦z≦0.03..
Solar Junction Corporation


07/30/15
20150214403 
 Ultrathin group ii-vi semiconductor layers, group ii-vi semiconductor superlattice structures, photovoltaic devices incorporating the same, and related methods patent thumbnailnew patent Ultrathin group ii-vi semiconductor layers, group ii-vi semiconductor superlattice structures, photovoltaic devices incorporating the same, and related methods
Disclosed are ultrathin layers of group ii-vi semiconductors, group ii-vi semiconductor superlattice structures, photovoltaic devices incorporating the layers and superlattice structures and related methods. The superlattice structures comprise an ultrathin layer of a first group ii-vi semiconductor alternating with an ultrathin layer of at least one additional semiconductor, e.g., a second group ii-vi semiconductor, or a group iv semiconductor, or a group iii-v semiconductor..
University Of Kansas


07/30/15
20150214402 
 Light receiving element and solar cell including light receiving element patent thumbnailnew patent Light receiving element and solar cell including light receiving element
A light receiving element includes a p-type semiconductor layer, an n-type semiconductor layer, and a first and a second superlattice semiconductor layers, and the first and the second superlattice semiconductor layers each have a superlattice structure in which a barrier layer and a quantum dot layer are alternately and repeatedly stacked. A band structure of the superlattice structure of the first superlattice semiconductor layer is a type i structure, and that of the second superlattice semiconductor layer is a type ii structure.
Sharp Kabushiki Kaisha


07/30/15
20150214368 
 Embedded source or drain region of transistor with laterally extended portion patent thumbnailnew patent Embedded source or drain region of transistor with laterally extended portion
In some embodiments, in a method, a body structure with a gate structure configured thereon is provided. The gate structure comprises a gate side wall traversing the body structure.
Taiwan Semiconductor Manufacturing Company Ltd.


07/30/15
20150214366 
 Embedded source or drain region of transistor with downward tapered region under facet region patent thumbnailnew patent Embedded source or drain region of transistor with downward tapered region under facet region
In some embodiments, a field effect transistor (fet) structure comprises a body structure, dielectric structures, a gate structure and a source or drain region. The gate structure is formed over the body structure.
Taiwan Semiconductor Manufacturing Company Ltd.


07/30/15
20150214364 
 Fin field effect transistor including a strained epitaxial semiconductor shell patent thumbnailnew patent Fin field effect transistor including a strained epitaxial semiconductor shell
A semiconductor fin including a single crystalline semiconductor material is formed on a dielectric layer. A semiconductor shell including an epitaxial semiconductor material is formed on all physically exposed surfaces of the semiconductor fin by selective epitaxy, which deposits the semiconductor material only on semiconductor surfaces and not on dielectric surfaces.
International Business Machines Corporation


07/30/15
20150214351 
 Semiconductor device including superlattice sige/si fin structure patent thumbnailnew patent Semiconductor device including superlattice sige/si fin structure
A semiconductor device includes a semiconductor-on-insulator substrate having an insulator layer, and at least one silicon germanium (sige) fin having a superlattice structure. The sige fin is formed on an upper surface of the insulator layer.
International Business Machines Corporation


07/30/15
20150214275 
 Magnetic tunnel junction with superlattice barriers patent thumbnailnew patent Magnetic tunnel junction with superlattice barriers
A magnetic tunnel junction is provided. The magnetic tunnel junction can enhance the tunnel magnetoresistance ratio and a device including the magnetic tunnel junction.
National Taiwan University


07/30/15
20150214157 
new patent

Ultrathin superlattice of mno/mn/mnn and other metal oxide/metal/metal nitride liners and caps for copper low dielectric constant interconnects


An electrical device comprising including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure.
International Business Machines Corporation


07/30/15
20150214050 
new patent

Nanowire article and processes for making and using same


A nanowire article includes a substrate; a plurality of nanowires disposed on the substrate, the nanowires comprising a semiconductor nitride, the semiconductor comprising an element selected from group 3 of the periodic table; and a superlattice layer interposed between the substrate and the plurality of gallium nitride nanowires. A process for producing a nanowire article includes disposing a superlattice layer on a substrate; disposing a first buffer layer on the superlattice layer; contacting the first buffer layer with a precursor; and forming a plurality of nanowires from the precursor on the first buffer layer to form the nanowire article, the nanowires comprising a semiconductor nitride, the semiconductor comprising an element selected from group 3 of the periodic table.
National Institute Of Standards And Technology


07/30/15
20150213927 
new patent

Iron-silicon oxide particles having an improved heating rate


D) the core has lattice plane spacings of 0.20 nm, 0.25 nm and 0.29 nm, in each case +/−0.02 nm, determined by means of hr-tem.. .

07/30/15
20150212622 
new patent

Touch panel substrate and display device


A touch panel substrate used for a touch panel with enhanced display quality is realized. A touch panel substrate (2) in accordance with one aspect of the invention includes a first detection electrode (11) including a plurality of first lattice electrodes (13) aligned in a lateral direction.
Sharp Kabushiki Kaisha


07/30/15
20150210581 
new patent

Regenerator for glass melting tanks


A regenerator for glass melting tanks for storing waste heat from combustion cycles and emitting the stored heat to oxidation gases supplied from the outside, having a gas-permeable chamber lattice in which the chamber lining is made of fire-resistant stones held together by lateral wall elements. A cover region is situated over the chamber lattice for the combustion gases entering into the chamber lattice and for the oxidation gases exiting from the chamber lattice, the chamber cover forming a flow duct together with a further cover segment, connected to the cover, limited by a downward-extending terminating wall that is connected to the burner throat and with the wall element.
Beteiligungen Sorg Gmbh & Co. Kg


07/30/15
20150209767 
new patent

Phosphorus-containing ultrastable y-type rare earth molecular sieve and preparation method therefor


Provided is a phosphorus-containing ultrastable y-type rare earth (re) molecular sieve and the preparation method thereof. The method is: based on na y molecular sieve as a raw material, obtaining “one-exchange one-roast” re-na y-type molecular sieve through the steps of exchanging with re, pre-exchanging with dispersing, and the first calcination; and then performing ammonium salt exchange, phosphorus modification, and the second calcination on the “one-exchange one-roast” re-na y-type molecular sieve, wherein the sequence of the re exchange and the pre-exchange with dispersing is unlimited, and the sequence of the ammonium salt exchange and the phosphorus modification is unlimited as well.
Petrochina Company Limited


07/30/15
20150209253 
new patent

Oral care and oral hygiene products having photocatalytic activity comprising inorganic particles superficially functionalised with tio2 nanoparticles


The present invention refers to oral care and oral hygiene products having photocatalytic activity comprising particles of a calcium phosphate compound, superficially functionalised with tio2 nanoparticles in crystalline form, said tio2 nanoparticles having: a) a substantially lamellar morphology; b) an aspect ratio (ar) comprised between 5 and 30; c) a surface structure having face (001) as outermost face of the crystalline lattice; and d) wherein the tio2 is in the form of anatase, optionally mixed with rutile and/or brookite.. .
Coswell S.p.a


07/30/15
20150209140 
new patent

Stented prosthetic heart valve with variable stiffness and methods of use


A prosthetic heart valve including a stent frame and a valve structure. The valve structure is disposed within a lumen of the stent frame.
Medtronic Vascular Galway


07/23/15
20150208261 

Method and analyzing interference in time-space dimensions


Disclosed herein are a method and apparatus for analyzing interference in the time-space dimensions. The apparatus includes an evaluation area partition unit configured to partition an evaluation area into lattices in order for a receiver to determine whether a permitted interference level at which interference needs to be accepted is satisfied or not and an interference analysis unit configured to spatially evaluate the amount of interference in each of the lattices based on a result of temporal evaluation of the amount of interference in each of the lattices..
Electronics And Telecommunications Research Institute


07/23/15
20150207034 

Semiconductor light emitting device


A semiconductor light emitting device may include a base semiconductor layer formed on a substrate and having defect regions therein; cavities disposed in regions corresponding to the defect regions on the base semiconductor layer; a capping layer disposed to cover at least one region of the base semiconductor layer and the cavities; and a light emitting structure disposed on the capping layer and including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer. lattice defects formed in the light emitting structure may be reduced to enhance luminous efficiency..
Samsung Electronics Co., Ltd.


07/23/15
20150207029 

Superlattice structure


A superlattice layer including a plurality of periods, each of which is formed from a plurality of sub-layers is provided. Each sub-layer comprises a different composition than the adjacent sub-layer(s) and comprises a polarization that is opposite a polarization of the adjacent sub-layer(s).
Sensor Electronic Technology, Inc.


07/23/15
20150206970 

Body-tied, strained-channel multi-gate device and methods of manufacturing same


A fin-fet or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/23/15
20150206956 

Semiconductor device and manufacturing the same


A method of manufacturing a semiconductor device includes forming an active pattern protruding from a semiconductor substrate, forming a dummy gate pattern crossing over the active pattern, forming gate spacers on opposite first and second sidewalls of the dummy gate pattern, removing the dummy gate pattern to form a gate region exposing an upper surface and sidewalls of the active pattern between the gate spacers, recessing the upper surface of the active pattern exposed by the gate region to form a channel recess region, forming a channel pattern in the channel recess region by a selective epitaxial growth (seg) process, and sequentially forming a gate dielectric layer and a gate electrode covering an upper surface and sidewalls of the channel pattern in the gate region. The channel pattern has a lattice constant different from that of the semiconductor substrate..
Samsung Electronics Co., Ltd.


07/23/15
20150206939 

Epitaxy in semiconductor structure and menufacuting the same


The present disclosure provides a semiconductor structure having an insulating layer positioning on a substrate; a semiconductor fin partially located in the insulating layer; and a metal gate over the semiconductor fin and the insulating layer. The semiconductor fin includes a first region including a first lattice constant and a second region in proximity to the metal gate, including a second lattice constant.
Taiwan Semiconductor Manufacturing Company Ltd.


07/23/15
20150206760 

Substrate mask patterns, methods of forming a structure on a substrate, methods of forming a square lattice pattern from an oblique lattice pattern, and methods of forming a pattern on a substrate


A method of forming a pattern on a substrate comprises forming spaced, upwardly-open, cylinder-like structures projecting longitudinally outward of a base. Sidewall lining is formed over inner and over outer sidewalls of the cylinder-like structures, and that forms interstitial spaces laterally outward of the cylinder-like structures.
Micron Technology, Inc.


07/23/15
20150204924 

Computationally screening the stability of battery electrode materials with mixtures of redox couple elements


A mixture stability criterion asserts that a mixture of at least two redox elements in a crystal lattice will be unstable during charge and discharge cycles unless a set of charged ground state configurations at a specified value of a mixing ratio for the redox elements and a set of discharged ground state configurations at the same value of mixing ratio both consist of the same derivative superstructures. All members of the charged ground state set and all members of the discharged ground state set are within a same energy threshold value of the lowest-energy member of each set.
Samsung Electronics Co., Ltd.


07/23/15
20150204074 

Point-supported element or flat concrete ceiling


The invention relates to a point-supported element or flat concrete ceiling (bd) that comprises a transverse force and punching reinforcement (b) into which a lattice beam (1) that tapers on a support vertical axis (a) is integrated, wherein the lattice beam comprises lower chords (u) and a continuous upper chord (o) or anchoring elements (10) arranged with open spaces (z) between one another and at least one serpentine diagonal strut section (d) with upper and lower bent portions (11, 12) between each two successive diagonal struts (s1, s2), said bent portions being secured in securing points (so, su). The diagonal struts (s1, s2) are angled in the same manner upwards and in the direction of the support (t).
Filigran Tragersysteme Gmbh & Co.kg


07/16/15
20150200321 

Directly bonded, lattice-mismatched semiconductor device


A semiconductor device may include a first subassembly and a second subassembly. The first subassembly may include a first bonding layer.
The Boeing Company


07/16/15
20150200246 

Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication


Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.. .
Taiwan Semiconductor Manufacturing Company, Ltd.


07/16/15
20150200105 

Production method


A production methods includes providing a substrate including a lattice plane that extends in a non-symmetrical manner and such that it is offset at an angle α from at least a first or second main surface region of the substrate, the first and second main surface regions extending parallel to each other; anisotropic etching, starting from the first main surface region, into the substrate so as to obtain an etching structure which includes, in a plane extending perpendicularly to the first main surface region, two different etching angles relative to the first main surface region; arranging a cover layer on the first main surface region, so that the cover layer lies against the etching structure in at least some sections; and removing, section-by-section, the material of the substrate starting from the second main surface region in the area of the deformed cover layer, so that the cover layer is exposed in at least one window region.. .
Fraunhofer-gesellschaft Zur Foerderung Der Angewandten Forschung E.v.


07/16/15
20150199582 

Character recognition apparatus and method


According to one embodiment, a character recognition apparatus includes a first generation unit, an estimation unit, a second generation unit and a search unit. The first generation unit generates a user dictionary that a preferred character is registered.
Kabushiki Kaisha Toshiba


07/16/15
20150198845 

Display device


A display device includes a first base substrate, a second base substrate, pixels, a first polarizer, and a second polarizer. The first base substrate includes light transmitting areas and a light blocking area surrounding each of the light transmitting areas.
Samsung Display Co., Ltd.


07/16/15
20150198764 

High-birefringence hollow-core fibers and techniques for making same


A hollow core fiber has a cladding comprising a matrix of cells, wherein each cell comprises a hole and a wall surrounding the hole. The fiber further has a hollow core region comprising a core gap in the matrix of cells, wherein the core gap spans a plurality of cells and has a boundary defined by the interface of the core gap.
Ofs Fitel, Llc


07/16/15
20150198530 

Method for producing optically stimulated luminescene dosage detection crystal


A method for producing an optically stimulated luminescene (osl) dosage detection crystal is disclosed, where an al2o3 is first covered with carbon. The carbon atoms are diffused then in vacuum into the al2o3 lattices.

07/16/15
20150198477 

Device for detecting single photon available at room temperature and method thereof


Disclosed are a device for detecting a single photon available at a room temperature, which includes: a signal transmitting unit including a first electrode and a second electrode spaced apart from each other and at least one nanostructure disposed between the first electrode and the second electrode, the first electrode receiving a signal from the signal generating unit; a photonic crystal lattice structure for receiving a photon, the photonic crystal lattice structure having an optical waveguide for guiding the received photon to the first electrode, the optical waveguide being formed by a plurality of dielectric structures; and a single photon detector for detecting a photon by analyzing a signal output to the second electrode, and a method for detecting a single photon using the device.. .
Korea Institute Of Science And Technology


07/09/15
20150194985 

Encoding device and generating message matrix


A method for arranging a plurality of message blocks in a lattice form and generating a message matrix includes deciding lengths of rows of the message matrix such that a length difference is equal to or less than a first critical point, deciding lengths of the message blocks such that a length difference is equal to or less than a second critical point, and arranging the message blocks in each row of the message matrix such that a length difference of columns of the message matrix is equal to or less than a third critical point.. .
Korea Advanced Institute Of Science And Technology


07/09/15
20150194972 

Optical lattice clock, clock device and laser light source


Various embodiments improve accuracy by increasing the number of atoms engaged in a clock transitions in an optical lattice clock. An exemplary optical lattice clock an embodiment comprises an optical waveguide, an optical path, a laser light source, and a laser cooler.
Riken


07/09/15
20150194666 

Methods of making metal-doped nickel oxide active materials


Methods of making high-energy cathode active materials for primary alkaline batteries are described. The primary batteries include a cathode having an alkali-deficient nickel(iv)-containing oxide including one or more metals such as co, mg, al, ca, y, mn, and/or non-metals such as b, si, ge or a combination of metal and/or non-metal atoms as dopants partially substituted for ni and/or li in the crystal lattice; an anode; a separator between the cathode and the anode; and an alkaline electrolyte solution..
The Gillette Company


07/09/15
20150194526 

Method for manufacturing semiconductor device with recess, epitaxial growth and diffuson


A semiconductor device including a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate..
Sony Corporation


07/09/15
20150194307 

Strained fin structures and methods of fabrication


Methods for fabricating a strained fin structure are provided which include: providing a virtual substrate material over a substrate structure, the virtual substrate material having a virtual substrate lattice constant and a virtual substrate lattice structure; providing a first material over a region of the virtual substrate material, the first material acquiring a strained first material lattice structure by, in part, conforming to the virtual substrate lattice structure; and etching a first fin pattern into the first material. The method may include providing a second material over a second region of the virtual substrate material, the second material acquiring a strained lattice structure by, in part, conforming to the virtual substrate lattice structure, and etching a fin pattern into the second material.
Globalfoundries Inc.


07/09/15
20150194150 

System and handling repeat queries due to wrong asr output by modifying an acoustic, a language and a semantic model


Disclosed herein are systems, computer-implemented methods, and computer-readable storage media for handling expected repeat speech queries or other inputs. The method causes a computing device to detect a misrecognized speech query from a user, determine a tendency of the user to repeat speech queries based on previous user interactions, and adapt a speech recognition model based on the determined tendency before an expected repeat speech query.
At&t Intellectual Property I, L.p.


07/09/15
20150193559 

Method for creating three dimensional lattice structures in computer-aided design models for additive manufacturing


Methods for creating three dimensional lattice structures in computer-aided design models. A method includes receiving a solid model containing a plurality of boundary surfaces for a void region, computing a bounding box of the solid model and a plurality of grid points on an axis-aligned grid within the bounding box, creating a lattice cell layout for a lattice structure within the void region, computing an implicit model defined by a scalar value for each of the grid points on the axis-aligned grid, extracting the lattice structure in the solid model based on the implicit model..
Siemens Product Lifecycle Management Software Inc.


07/09/15
20150193050 

Lattice structure for capacitance sensing electrodes


A sensor array includes a first sensor element of a unit cell and a second sensor element of the unit cell. The unit cell includes core traces of the first sensor element, where the core traces are the widest portion of the first sensor element.
Cypress Semiconductor Corporation


07/09/15
20150191698 

Adipose-derived stem cells and lattices


The present invention provides adipose-derived stem cells and lattices. In one aspect, the present invention provides a lipo-derived stem cell substantially free of adipocytes and red blood cells and clonal populations of connective tissue stem cells.
University Of Pittsburgh Of The Commonwealth System Of Higher Education


07/09/15
20150190971 

Method for structure preserving topology optimization of lattice structures for additive manufacturing


Methods for structure preserving topology optimization of lattice structures for additive manufacturing. A method includes receiving an initial lattice model, a physical objective of the initial lattice model to be optimized, forces to be applied to the initial lattice model and their respective locations, and an optimal volume ratio for an optimized lattice model, computing a bounding box of the initial lattice model and an axis-aligned voxel grid, computing an implicit scalar field representation of an initial volume ratio of the initial lattice model, mapping the loads to their respective locations in the axis-aligned voxel grid, performing an additive topology optimization on the initial lattice model to create the optimized lattice model until the initial volume ratio satisfies the optimal volume ratio, and storing the optimized lattice model..
Siemens Product Lifecycle Management Software Inc.


07/09/15
20150190691 

Multi-panel lacrosse pocket


A unitary pocket for a lacrosse head having two or more panels formed in lattice patterns, joined together lengthwise, and secured within the head of a lacrosse stick with little or no stringing. All panels are die-cut or laser-cut from flat sheet material with a pattern of cutouts, or alternatively molded as such to provide the lattice-patterns.

07/02/15
20150189267 

Image projection device and calibration method thereof


There is provided an image projection device including a camera, a projector configured to project an image, a camera calibration unit configured to perform calibration of the camera, a projector calibration unit configured to perform calibration of the projector, and an image correction unit configured to correct the image projected from the projector based on a result of the calibration. The projector calibration unit performs ray tracing of a known checker pattern on which structural light is projected by the projector, and estimates parameters by acquiring correspondence relation between a lattice point of the checker pattern and projector coordinates..
Sony Corporation


07/02/15
20150188134 

Cathode active material for lithium-ion battery, cathode for lithium-ion battery and lithium-ion battery


A cathode active material for lithium-ion battery is provided, which provides good battery characteristics such as cycle characteristics. The cathode active material for lithium-ion battery is expressed by the composition formula: lixni1-ymyoα, wherein m is one or more selected from ti, cr, mn, fe, co, cu, al, sn, mg and zr; 0.9≦x≦1.2; 0<y≦0.5; and 2.0≦α≦2.2, wherein the crystallite size obtained by analyzing the xrd pattern is 870 Å or more and the unit lattice volume is 101.70 Å3 or less..
Jx Nippon Mining & Metals Corporation


07/02/15
20150188034 

Magnetic tunnel junction device


A magnetic tunnel junction device includes: a first magnetic layer that has an easy axis vertical to a surface; a non-magnetic layer on the first magnetic layer; and a second magnetic layer that has an easy axis vertical to a surface on the non-magnetic layer, and an interface layer formed of a heussler alloy between the non-magnetic layer and at least one of the first and second magnetic layers. The at least one of the first and second magnetic layers is formed of mnga.

07/02/15
20150187973 

Solar cell and manufacturing method thereof


A solar cell includes a semiconductor substrate of a first conductivity; a pillar-shaped structure constituted by a semiconductor of the first conductivity, the pillar-shaped structure being formed on the semiconductor substrate; a superlattice layer including a barrier layer and a quantum structure layer that are alternately deposited on a side wall of the pillar-shaped structure, the quantum structure layer being constituted by a material having a smaller energy bandgap than that of the barrier layer, the quantum structure layer including a wurtzite type crystal part and a zinc blende type crystal part that are alternately arranged along an axial direction of the pillar-shaped structure; and a semiconductor layer of a second conductivity that is formed so as to surround the superlattice layer, the second conductivity being an opposite conductivity to that of the first conductivity.. .
Fujitsu Limited


07/02/15
20150187962 

Schottky barrier diode and manufacturing the same


A schottky barrier diode includes: an n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate; a first p+ region disposed on the n− type epitaxial layer; an n type epitaxial layer disposed on the n− type epitaxial layer and the first p+ region; a second p+ region disposed on the n type epitaxial layer, and being in contact with the first p+ region; a schottky electrode disposed on the n type epitaxial layer and the second p+ region; and an ohmic electrode disposed on a second surface of the n+ type silicon carbide substrate. Also, the first p+ region has a lattice shape including a plurality of vertical portions and horizontal portions connecting both ends of the respective vertical portions to each other..
Hyundai Motor Company


07/02/15
20150187944 

Semiconductor liner of semiconductor device


The disclosure relates to a fin field effect transistor (finfet). An exemplary finfet comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower portion, an upper portion, and a middle portion between the lower portion and upper portion, wherein the fin structure comprises a first semiconductor material having a first lattice constant; a pair of notches extending into opposite sides of the middle portion; and a semiconductor liner adjoining the lower portion comprising a second semiconductor material having a second lattice constant greater than the first lattice constant..
Taiwan Semiconductor Manufacturing Company, Ltd.


07/02/15
20150187924 

Low sheet resistance gan channel on si substrates using inaln and algan bi-layer capping stack


Transistors or transistor layers include an inaln and algan bi-layer capping stack on a 2deg gan channel, such as for gan mos structures on si substrates. The gan channel may be formed in a gan buffer layer or stack, to compensate for the high crystal structure lattice size and coefficient of thermal expansion mismatch between gan and si.

07/02/15
20150187499 

Ceramic powder and multi-layer ceramic capacitor


A multi-layer ceramic capacitor is made by alternately layering a dielectric layer constituted by a sintered body of a ceramic powder, and an internal electrode layer. The ceramic powder contains barium titanate powder having a perovskite structure with a median size of 200 nm or smaller as measured by sem observation, wherein the barium titanate powder is such that the percentage of barium titanate particles having twin defects in the barium titanate powder is 13% or more as measured by tem observation and that its crystal lattice c/a is 1.0080 or more.
Taiyo Yuden Co., Ltd.


07/02/15
20150187444 

Energy generation apparatus and method


A practical technique for inducing and controlling the fusion of nuclei within a solid lattice. A reactor includes a loading source to provide the light nuclei which are to be fused, a lattice which can absorb the light nuclei, a source of phonon energy, and a control mechanism to start and stop stimulation of phonon energy and/or the loading of reactants.
Brillouin Energy Corp.


07/02/15
20150184398 

Apparatus and related methods of paving a subsurface


Disclosed may be an intermediate surface for supporting a small paver, wherein the surface can also be used to exchange heat with the pavers. In one embodiment, the apparatus may be a hextray defined by a frame with a hexagonal lattice for supporting pavers.

06/25/15
20150181191 

Synthesis-parameter generation device for three-dimensional measurement apparatus


A plurality of units (4) constituted by a projector (6) that projects a periodic lattice onto a measurement target (1) and a camera (8) that images the projected lattice are included around the measurement target (1), and three-dimensional coordinates measured by the respective units (4) are composited by coordinate conversion. A first lattice that is displayed on a reference surface (42) is imaged, and phases with respect to the first lattice are obtained for respective pixels of the cameras (8) and stored.
Shima Seiki Mfg., Ltd.


06/25/15
20150180630 

Scattered pilot pattern and channel estimation mimo-ofdm systems


A method and apparatus are provided for reducing the number of pilot symbols within a mimo-ofdm communication system, and for improving channel estimation within such a system. For each transmitting antenna in an ofdm transmitter, pilot symbols are encoded so as to be unique to the transmitting antenna.
Blackberry Limited


06/25/15
20150179863 

Avalanche photodiode utilizing interfacial misfit array


According to some embodiments of the present invention, an avalanche photodiode includes a first electrode, a second electrode spaced apart from the first electrode, a photon absorber layer formed to be in electrical connection with the first electrode, and a charge-carrier multiplication layer formed to be in electrical connection with the second electrode. The photon absorber layer is a semiconducting material that has a first lattice constant, and the charge-carrier multiplication layer is a semiconducting material that has a second lattice constant that is different from the first lattice constant.
Lancaster University Business Enterprises Ltd


06/25/15
20150179861 

Etching of infrared sensor membrane


The invention relates to an infrared thermal sensor comprising a substrate having a cavity, a cavity bottom wall formed by a continuous substrate surface. The sensor comprises a membrane adapted for receiving heat from incident infrared radiation, a beam suspending the membrane, and a thermocouple.
Melexis Technologies Nv


06/25/15
20150179845 

Solid-state imaging device, light detecting device, and electronic apparatus


A solid-state imaging device includes a multi-quantum wells (mqw) structure which combines and uses a non-group iv lattice matching-based compound semiconductor with an absolute value of a mismatch ratio of less than 1% on a silicon substrate so as to have sensitivity to at least infrared light.. .
Sony Corporation


06/25/15
20150179768 

Fin structure of semiconductor device


The disclosure relates to a fin field effect transistor (finfet). An exemplary finfet comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising an upper portion comprising a first semiconductor material having a first lattice constant, wherein the upper portion comprises a first substantially vertical portion having a first width and a second substantially vertical portion having a second width less than the first width over the first substantially vertical portion; and a lower portion comprising a second semiconductor material having a second lattice constant less than the first lattice constant, wherein a top surface of the lower portion has a third width less than the first width; and a gate structure covering the second substantially vertical portion..
Taiwan Semiconductor Manufacturing Company, Ltd.


06/25/15
20150179742 

Active regions with compatible dielectric layers


A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material.

06/25/15
20150179664 

Heterogeneous semiconductor material integration techniques


Techniques are disclosed for heteroepitaxial growth of a layer of lattice-mismatched semiconductor material on an initial substrate, and transfer of a defect-free portion of that layer to a handle wafer or other suitable substrate for integration. In accordance with some embodiments, transfer may result in the presence of island-like oxide structures on the handle wafer/substrate, each having a defect-free island of the lattice-mismatched semiconductor material embedded within its upper surface.

06/25/15
20150179166 

Decoder, decoding method, and computer program product


According to an embodiment, a decoder includes a token operating unit, a node adder, and a connection detector. The token operating unit is configured to, every time a signal or a feature is input, propagate each of a plurality of tokens, which is an object assigned with a state of the of a path being searched, according to a digraph until a state or a transition assigned with a non-empty input symbol is reached.
Kabushiki Kaisha Toshiba


06/25/15
20150178584 

Shape detection and ellipse fitting of a polygon


A method of shape detection detects a figure with a contouring loop method that extracts at least one iso-contour polygon from a set of pixels in an image using a triangular lattice superimposed over the set of pixels of the image. Then starting from an original triangle, the iso-contour polygon is extracted by selecting an intensity chroma value within the set of pixels between three corners of a triangle to find a directed line segment that represent the crossing of the intensity value within the triangle, and an exit point of the directed line segment and a nearest triangle which contains the next directed line segment of the at least one iso-contour polygon are determined to create a first matrix of points on the at least one iso-contour polygon, until arriving at the original triangle..

06/25/15
20150177727 

Numerical controller provided with function of correcting displacement error caused by work


A numerical controller uses a work lattice region setting unit and a rotation axis work lattice region setting unit to form lattice points for error correction and uses a work-caused translation correction amount setting unit to set a correction amount of a work-caused translation error. A work-caused translation correction amount calculation unit calculates a correction amount at a tool center point position, and a correction section of the numerical controller adds the work-caused translation correction amount to positions of three commanded linear axes for error correction..
Fanuc Corporation


06/25/15
20150177438 

Display having backlight with narrowband collimated light sources


A display has an array of display pixels formed from display layers such as one or more polarizer layers, a substrate on which an array of display pixel elements such as color filter elements and downconverter elements are formed, a liquid crystal layer, and a thin-film transistor layer that includes display pixel electrodes and display pixel thin-film transistors for driving control signals onto the display pixel electrodes to modulate light passing through the display pixels. A light source such as one or more laser diodes or light-emitting diodes may be used to generate light for the display.
Apple Inc.


06/25/15
20150176775 

Display having backlight with narrowband collimated light sources


A display has an array of display pixels formed from display layers such as one or more polarizer layers, a substrate on which an array of display pixel elements such as color filter elements and downconverter elements are formed, a liquid crystal layer, and a thin-film transistor layer that includes display pixel electrodes and display pixel thin-film transistors for driving control signals onto the display pixel electrodes to modulate light passing through the display pixels. A light source such as one or more laser diodes or light-emitting diodes may be used to generate light for the display.
Apple Inc.


06/25/15
20150176293 

Movable centring for port platforms


Movable centring for platforms in ports which comprises a mobile structure (1) with various formworks (2) and is supported on piles (3). The support of the mobile structure (1) on the piles (3) is carried out by means of, at least, two supporting devices (5), wherein each supporting device (5) comprises one front supporting beam (6d), which comprises at least two coupling pieces (18), one rear supporting beam (6t) which comprises at least two coupling pieces (18) and a lattice (7), beneath each supporting beam (6d, 6t).
Rubrica Ingenieria Y Arquitectura, S.l.




Popular terms: [SEARCH]

Lattice topics: Semiconductor, Semiconductor Device, Semiconductor Material, Crystallin, Disconnect, Transistors, Replacement Gate, Semiconductor Devices, Dislocations, Dislocation, Image Processing, Coordinates, Surface Plasmon Polariton, Antenna Array

Follow us on Twitter
twitter icon@FreshPatents

###

This listing is a sample listing of patent applications related to Lattice for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Lattice with additional patents listed. Browse our RSS directory or Search for other possible listings.


0.3422

4384

1 - 1 - 101