This page is updated frequently with new Lattice-related patent applications.
|Methods of making metal-doped nickel oxide active materials|
Methods of making high-energy cathode active materials for primary alkaline batteries are described. The primary batteries include a cathode having an alkali-deficient nickel(iv)-containing oxide including one or more metals such as co, mg, al, ca, y, mn, and/or non-metals such as b, si, ge or a combination of metal and/or non-metal atoms as dopants partially substituted for ni and/or li in the crystal lattice; an anode; a separator between the cathode and the anode; and an alkaline electrolyte solution..
Duracell U.s. Operations, Inc.
|Method of manufacturing light-emitting device|
A method of manufacturing a light-emitting device includes providing a resin sheet that includes a lattice-patterned reflective material-containing portion and film-shaped phosphor-containing portions covering lattice openings of the reflective material-containing portion, placing the resin sheet on a substrate mounting a plurality of light-emitting elements such that each of the plurality of light-emitting elements is surrounded by the reflective material-containing portion and is covered on the top with the phosphor-containing portion, after placing the resin sheet on the substrate, softening the resin sheet by heating such that the phosphor-containing portions are adhered to the respective upper surfaces of the plurality of light-emitting elements and the reflective material-containing portion or the phosphor-containing portions is/are adhered to the side surfaces of the plurality of light-emitting elements, and curing the resin sheet and then cutting the substrate and the resin sheet to singulate individual light-emitting devices.. .
Toyoda Gosei Co., Ltd.
|Semiconductor structure with stress-reducing buffer structure|
A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 gpa and 2.0 gpa.
Sensor Electronic Technology, Inc.
|System and light-emitting devices on lattice-matched metal substrates|
Light-emitting devices and methods, wherein, in some embodiments, the devices each include a first mirror having a first face, wherein the first mirror includes a metal and, in some embodiments, is a grown-epitaxial metal mirror (gemm); and an epitaxial structure, wherein the epitaxial structure is lattice matched with and in contact with at least a first portion of the first face of the first mirror, wherein the epitaxial structure includes an active region configured to emit light at a wavelength λ, and wherein the active region is located a first non-zero distance away from the first face of the first mirror such that there is plasmonic coupling between the active region and the first mirror.. .
|Multijunction solar cell assembly for space applications|
A multijunction solar cell assembly and its method of manufacture including first and second discrete and different semiconductor body subassemblies which are electrically interconnected to form a five junction solar cell, each semiconductor body subassembly including first, second, third and fourth lattice matched subcells; wherein the average band gap of all four cells in each subassembly is greater than 1.44 ev.. .
Solaero Technologies Corp.
|Multijunction metamorphic solar cell assembly for space applications|
A multijunction solar cell and its method of manufacture including interconnected first and second discrete semiconductor regions disposed adjacent and parallel to each other in a single semiconductor body, including first top subcell, second (and possibly third) lattice matched middle subcells; a graded interlayer adjacent to the last middle solar subcell; and a bottom solar subcell adjacent to said graded interlayer being lattice mismatched with respect to the last middle solar subcell; wherein the interconnected regions form at least a four junction solar cell by a series connection being formed between the bottom solar subcell in the first semiconductor region and the bottom solar subcell in the second semiconductor region.. .
Solaero Technologies Corp.
|Multiple-junction photovoltaic cell based on antimonide materials|
A photovoltaic cell is provided that can be used under high levels of solar concentration (≧1000 suns). The present cell includes at least one junction produced on a substrate based on gallium antimonide, the at least one junction having two alloys based on an antimonide material (ga1-xalxasysb1-y) lattice-matched on the substrate gasb.
Centre National De La Recherche Scientifique
|Lattice matched multijunction solar cell assemblies for space applications|
A multijunction solar cell and its method of manufacture including interconnected first and second discrete semiconductor regions disposed adjacent and parallel to each other in a single semiconductor body, including first top subcell, second (and possibly third) lattice matched middle subcells; and a bottom solar subcell adjacent to said last middle subcell and lattice matched thereto; wherein the interconnected regions form at least a four junction solar cell by a series connection being formed between the bottom solar subcell in the first semiconductor region and the bottom solar subcell in the second semiconductor region.. .
Solaero Technologies Corp.
|Lattice matchable alloy for solar cells|
An alloy composition for a subcell of a solar cell is provided that has a bandgap of at least 0.9 ev, namely, ga1-xinxnyas1-y-zsbz with a low antimony (sb) content and with enhanced indium (in) content and enhanced nitrogen (n) content, achieving substantial lattice matching to gaas and ge substrates and providing both high short circuit currents and high open circuit voltages in gainnassb subcells for multijunction solar cells. The composition ranges for ga1-xinxnyas1-y-zsbz are 0.07≦x≦0.18, 0.025≦y≦0.04 and 0.001≦z≦0.03..
Solar Junction Corporation
|Methods to introduce sub-micrometer, symmetry-breaking surface corrugation to silicon substrates to increase light trapping|
Provided is a method for fabricating a nanopatterned surface. The method includes forming a mask on a substrate, patterning the substrate to include a plurality of symmetry-breaking surface corrugations, and removing the mask.
Transistor, fabricating the same, and electronic device including the same
A semiconductor device includes a stressed substrate stressed by a first stress, a first stressed channel formed in the substrate and having the first stress, and a first strained gate electrode strained by a first strain generating element. A first strained gate electrode is formed over the first stressed channel, the first strained gate electrode including a first lattice-mismatched layer to induce a second stress to the first stressed channel..
Sk Hynix Inc.
Computer simulation of physical processes including modeling of laminar-to-turbulent transition
A computer-implemented method for simulating fluid flow using a lattice boltzmann (lb) approach that includes assigning values for the wall shear stress on a per-facet (e.g., per-surfel) basis based on whether the fluid flow is laminar or turbulent is described herein.. .
Right-angle waveguide based on square-hole-type square-lattice photonic crystal and dual compensation scattering cylinders with low refractive index
Disclosed in the present invention is a square-hole square-lattice photonic crystal orthogonal waveguide having low refractive index twin compensation scattering columns, being a photonic crystal consisting of a low refractive-index first medium column in a high refractive-index background medium arranged in a square crystal lattice, there being removed from said photonic crystal one row and one column of the low refractive-index first medium so as to form an orthogonal waveguide; columns of a second and a third low refractive-index medium are configured at two turning points respectively of said orthogonal waveguide; the second and third medium columns are compensation scattering columns; said second and third medium compensation scattering columns are low refractive-index medium columns or air holes; the first medium column is a low refractive-index medium square column or square air hole. The structure of the present invention features very low reflectivity and an extremely high rate of data transmission, and facilitates integration of large scale light paths, thus affording wider space for application of photonic crystals..
Right-angle waveguide based on circular-cylinder-type square-lattice photonic crystal and dual compensation scattering cylinders with high refractive index
A right angle waveguide having a circular rod-type square lattice photonic crystal and dual compensation scattering rods having a high refractive index. The right angle waveguide is a photonic crystal formed from first dielectric rods having a high refractive index arranged in a background dielectric having a low refractive index according to a square lattice.
Right-angle waveguide based on square-cylinder-type square-lattice photonic crystal and single compensation scattering cylinder with high refractive index
A right angle waveguide having a square rod-type square lattice photonic crystal and a single compensation scattering rod having a high refractive index. The right angle waveguide is a photonic crystal formed from first dielectric rods having a high refractive index arranged in a background dielectric having a low refractive index according to a square lattice.
Right-angle waveguide based on square-cylinder-type square-lattice photonic crystal and dual compensation scattering cylinders with high refractive index
A right angle waveguide having a square rod-type square lattice photonic crystal and dual compensation scattering rods having a high refractive index. The right angle waveguide is a photonic crystal formed from first dielectric rods having a high refractive index arranged in a background dielectric having a low refractive index according to a square lattice.
Graphene-based magnetic hall sensor for fluid flow analysis at nanoscale level
A method of detecting a particle comprises magnetizing a particle using an ac magnetic field; generating an ac voltage in a sensing device having a conductive substantially 2-dimensional lattice structure from the magnetized particle; superimposing a dc magnetic field on the generated ac voltage in the sensing device; and measuring an ac hall voltage at the sensing device.. .
International Business Machines Corporation
Utility tower lifting apparatus and method
A utility tower lifting apparatus and method for raising a lattice tower in addition to carried transmission cables without disturbing the tower foundation, disconnecting the cables, or requiring de-energization of the transmission lines.. .
Ampjack Industries Ltd.
Methods of synthesizing chabazite zeolites with controlled aluminum distribution and structures made therefrom
A method of synthesizing chabazite zeolites with controlled aluminum distribution. The method utilizes a source of an organic structure-directing agent, a source of an inorganic structure-directing agent, a source of aluminum and a source of silicon to form a synthesis gel which is subjected to a crystallization process to crystallize a chabazite zeolite with controlled aluminum distribution.
Purdue Research Foundation
Point-in-time copy with chain cloning
A method and system for storage copy with chain cloning are provided, including providing a volume with one or more snapshots in the form of a dependency chain, where the volume and one or more snapshots are volume nodes in the dependency chain and providing associated metadata required to maintain the one or more snapshots; cloning the dependency chain to create at least one a sparse copy chain including sparse copies of the volume and the one or more snapshots resulting in sparse volume nodes, resulting in a lattice structure of the dependency chain of volume nodes and one or more sparse copy chains of cloned volume nodes.. .
International Business Machines Corporation
Lattice structure valve/regulator body
A method of manufacturing a body of a fluid control apparatus using additive manufacturing, the method including forming an inner wall having an outside surface and an inside surface, an area surrounding an inlet, an area surrounding an outlet, and an area surrounding a fluid flow path, wherein the inner wall provides a fluid boundary and connects the inlet and the outlet. The method further including forming a portion of the inner wall that receives a valve seat, forming a portion of the inner wall that receives a control stem and a control element, and forming a lattice structure by depositing a solidifiable material onto the inner wall in a predetermined pattern, wherein the lattice structure is three-dimensional and includes a plurality of connected lattice members..
Emerson Process Management Regulator Technologies, Inc.
Three-dimensional printed dental appliances using lattices
Method and apparatus for fabricating an oral appliance are described for correcting malocclusions on a dentition of a subject. A three-dimensional representation of the dentition may be captured and a free-form structure having a lattice structure which matches at least part of a surface of the dentition is generated.
Ulab Systems, Inc.
Multiple access in an orthogonal time frequency space communication system
A method and system for multiple access in a system utilizing two-dimensional signal modulation. The method includes spreading data symbols arranged in a two-dimensional information domain onto sets of grid points respectively associated with different users in a time-frequency domain.
Cohere Technologies, Inc.
Material layer stack, light emitting element, light emitting package, and fabricating light emitting element
Disclosed herein are a material layer stack, a light emitting element, a light emitting package, and a method of fabricating a light emitting element. The material layer stack includes: a substrate having a first lattice constant; and a semiconductor layer grown on the substrate, the semiconductor layer having a second lattice constant that is different from the first lattice constant.
Samsung Electronics Co., Ltd.
Low temperature poly-silicon tft substrate structure and manufacture method thereof
The present invention provides a low temperature poly-silicon tft substrate structure and a manufacture method thereof. By providing the amorphous silicon layers in the drive tft area and the display tft area with different thicknesses, of which the thickness of the amorphous silicon layer in the drive tft area is smaller, and the thickness of the amorphous silicon layer in the display tft area is larger, and thus, in the excimer laser annealing process, different crystallization results are generated with the amorphous silicon layers in the drive tft area and the display tft area under the function of the laser with the same energy to achieve the control to the grain diameters of the crystals.
Shenzhen China Star Optoelectronics Technology Co., Ltd.
Methods and systems for creating networks
The automata processor workbench (ap workbench) is an application for creating and editing designs of ap networks (e.g., one or more portions of the state machine engine, one or more portions of the fsm lattice, or the like) based on, for example, an automata network markup language (anml). For instance, the application may include a tangible, non-transitory computer-readable medium configured to store instructions executable by a processor of an electronic device, wherein the instructions include instructions to represent an automata network as a graph..
Micron Technology, Inc.
Optical-capacitive sensor panel device and manufacturing same
The present disclosure provides an optical-capacitive sensor panel device. In one aspect, the panel device includes a a transparent substrate having a first surface; an optical sensor array formed on the first surface of the transparent substrate, the optical sensor array including a plurality of photosensitive pixels spaced apart from each other and arranged on the first surface to form a lattice structure; a plurality of row electrodes formed on the optical sensor array and electrically coupled to a first group of the photosensitive pixels; a plurality of column electrodes formed on the optical sensor array crossing the row electrodes and electrically coupled to a second group of the photosensitive pixels; and an insulating layer formed between the row electrodes and the column electrodes..
Bidirectional Display, Inc.
Variable height telescoping lattice tower
A variable height telescoping tower includes a base section and a second lower most section nested within the base section and extendable from within the base section. The second lower most section includes a plurality of vertically spaced lock apertures disposed thereon.
Us Tower Corp.
Coated cutting tool and producing the same
An embodiment of the invention provides a coated cutting tool having a base material and a hard coating, in which: the hard coating is formed from a nitride or a carbonitride having an al content of from 50 at. % to 68 at.
Mitsubishi Hitachi Tool Engineering, Ltd.
Structural porous biomaterial and implant formed of same
An implant comprising a porous microstructure is disclosed which has an external surface, where at least a region of the external surface is formed of the porous microstructure. The microstructure is defined by at least one lattice of cells.
The Royal Institution For The Advancement Of Learning/mcgill University
Electrode material for lithium-ion rechargeable battery
An electrode material for a lithium-ion rechargeable battery includes particles which are made of lifexmn1-w-x-y-zmgycazawpo4 (here, a represents at least one element selected from co, ni, zn, al, and ga, 0≦w≦0.05, 0.05≦x≦0.35, 0.01≦y≦0.10, and 0.0001≦z≦0.002), have an orthorhombic crystal structure, and have a space group of pmna, in which a change ratio (v1−v2)/v1 between a lattice volume v1 of lifexmn1-w-x-y-zmgycazawpo4 and a lattice volume v2 of fexmn1-w-x-y-zmgycazawpo4 obtained by chemically deintercalating li from lifexmn1-w-x-y-zmgycazawpo4 is in a range of 0.06 to 0.09.. .
Group iii nitride semiconductor light-emitting device
The present invention provides a group iii nitride semiconductor light-emitting device exhibiting improved emission efficiency. The group iii nitride semiconductor light-emitting device includes a base layer, an n-type superlattice layer, a light-emitting layer, and a p-type cladding layer, each of the layers being made of group iii nitride semiconductor.
Toyoda Gosei Co., Ltd.
Four junction inverted metamorphic solar cell
A multijunction solar cell which includes: an upper first solar subcell having a first band gap; a second solar subcell adjacent to said upper first solar subcell and having a second band gap smaller than said first band gap; a third solar subcell adjacent to said second solar subcell and having a third band gap smaller than said second band gap; a graded interlayer adjacent to said third solar subcell, said graded interlayer having a fourth band gap greater than said third band gap; and a lower fourth solar subcell adjacent to said graded interlayer, said lower fourth solar subcell having a fifth band gap smaller than said third band gap such that said lower fourth solar subcell is lattice mismatched with respect to said third solar subcell.. .
Solaero Technologies Corp.
Optoelectric devices comprising hybrid metamorphic buffer layers
In one aspect, semiconductor structures are described herein. A semiconductor structure, in some implementations, comprises a first semiconductor layer having a first bandgap and a first lattice constant and a second semiconductor layer having a second bandgap and a second lattice constant.
The Boeing Company
Semiconductor devices including source/drain regions having multiple epitaxial patterns
A semiconductor device includes an active pattern protruding from a substrate, a gate structure crossing over the active pattern, and source/drain regions disposed on the active pattern at opposite sides of the gate structure. Each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the first epitaxial pattern.
Samsung Electronics Co., Ltd.
Stacked nanowire devices formed using lateral aspect ratio trapping
A method for manufacturing a semiconductor device comprises depositing alternating layers of a plurality of first dielectric layers and a plurality of second dielectric layers on a substrate in a stacked configuration, forming one or more first openings in the stacked configuration to a depth penetrating below an upper surface of a bottom second dielectric layer of the plurality of second dielectric layers, forming one or more second openings in the stacked configuration to a depth corresponding to an upper surface of the substrate or below an upper surface of the substrate, removing the plurality of second dielectric layers from the stacked configuration to form a plurality of gaps, and epitaxially growing a semiconductor material from a seed layer in the one or more second openings to fill the one or more first and second openings and the plurality of gaps, wherein defects caused by a lattice mismatch between the epitaxially grown semiconductor material and a material of the substrate are contained at a bottom portion of the one or more second openings.. .
International Business Machines Corporation
Diode-based devices and methods for making the same
In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.. .
Taiwan Semiconductor Manufacturing Company, Ltd.
Thin film transistor, array substrate and manufacturing method thereof, and display device
The present invention provides a thin film transistor comprising an active layer, the active layer has a superlattice structure, and comprises a plurality of semiconductor layers and an insulating layer between every two adjacent semiconductor layers, a thickness of each of the semiconductor layers and the insulating layers is in nanometer range, and the plurality of semiconductor layers are made of at least one of metal oxide semiconductor and metal nitride oxide semiconductor. The present invention further provides an array substrate and a manufacturing method thereof, and a display device.
Boe Technology Group Co., Ltd.
Dynamic adaptation of language models and semantic tracking for automatic speech recognition
Generally, this disclosure provides systems, devices, methods and computer readable media for adaptation of language models and semantic tracking to improve automatic speech recognition (asr). A system for recognizing phrases of speech from a conversation may include an asr circuit configured to transcribe a user's speech to a first estimated text sequence, based on a generalized language model.
Data recognition in content
The disclosure relates to recognizing data such as items or entities in content. In some aspects, content may be received and feature information, such as face recognition data and voice recognition data may be generated.
Comcast Cable Communications, Llc
Solid state illumination device based on non-radiative energy transfer
There is provided an illumination device comprising: a wavelength converting layer comprising a photon emitting donor configured to absorb energy to reach an excited state, and a photon emitting acceptor; an energy source configured to provide energy to the donor such that the donor reach the excited state; wherein the donor and the acceptor are selected and arranged at a distance from each other such that non-radiative transfer of excitation energy from the donor to the acceptor occur, and wherein the acceptor is configured to emit a photon at a second wavelength after the transfer of energy; the illumination device further comprising a periodic plasmonic antenna array, arranged on the substrate and embedded within the wavelength converting layer, and comprising a plurality of individual antenna elements arranged in an antenna array plane, the plasmonic antenna array being configured to support a first lattice resonance at the second wavelength, arising from coupling of localized surface plasmon resonances in the individual antenna elements to photonic modes supported by the system comprising the plasmonic antenna array and the wavelength converting layer, wherein the plasmonic antenna array is configured to comprise plasmon resonance modes such that light emitted from the plasmonic antenna array has an anisotropic angle distribution.. .
Koninklijke Philips N.v.
Slicing machines, knife assemblies, and methods for slicing products
Methods and equipment suitable for slicing products into lattice-type slices or chips. The methods and equipment utilize a knife assembly that includes a corrugated knife having oppositely-disposed surfaces that terminate at a cutting edge.
Urschel Laboratories, Inc.
Parallel information processing apparatus, determining communication protocol, and medium
A parallel information processing apparatus includes a group of switches configured to have a topology of a latin square, and nodes connected with a switch among the group of switches. The parallel information processing apparatus also include a memory and a processor configured to designate (n×k) units of blocks in the group of switches included in a lattice structure in the topology of the latin square; to generate information about communication protocol that includes communication directions having different slopes for m (m≦k) units of the nodes, and the number of hops set for the respective communication directions having the different slopes; and to execute communication for the m units of the nodes of the units of the block, based on the information about communication protocol, so as to execute part-to-part communication between the m units of the nodes of the respective units of the blocks..
Negative electrode active material for lithium ion rechargeable battery and negative electrode using the same
A negative electrode active material for a lithium ion secondary battery, made up of substantially spherical graphite particles (a), having fine protrusions on the surfaces thereof and obtained by impregnating and coating substantially spherical graphite particles with a mixture of pitch and carbon black, followed by baking in a range of 900 to 1500° c. In accordance with raman spectroscopic analysis of the particles (a) using argon laser raman scattering light, there exists a g-band composite peak comprising peaks in the vicinity of 1600 cm−1, and 1580 cm−1, respectively, and at least one peak in the vicinity of d-band at 1380 cm−1, an interlayer distance of the lattice plane d002, obtained by wide-range x-ray diffraction, being in the range of 0.335 to 0.337 nm..
Nippon Carbon Co., Ltd.
Semiconductor device having magnetic tunnel junction structure and fabricating the same
A semiconductor device and a method of forming the semiconductor device are disclosed. The semiconductor device includes a lower electrode and a magnetic tunnel junction structure disposed on the lower electrode.
The present invention provides a light-emitting device suppressing the reduction in the light output while improving the response speed. As shown in fig.
Toyoda Gosei Co., Ltd.
Semiconductor structure and the manufacturing method thereof
The present disclosure provides a finfet. The finfet includes a silicon-on-insulator (soi) with an insulator; a plurality of fin structures on the insulator; an isolation on the insulator, and between two adjacent fin structures in the plurality of fin structures; and an oxide layer between each of the plurality of fin structures and the insulator, wherein the insulator comprises silicon germanium oxide.
Taiwan Semiconductor Manufacturing Company Ltd.
Self-aligned sige finfet
A self-aligned sige finfet device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium.
Semiconductor structure with enhanced withstand voltage
A semiconductor structure including a substrate, a buffer layer, a superlattice formed on the buffer layer , the superlattice including a pattern including n layers made of different materials, n being at least equal to 2, each layer including an alxgayinwbzn type material where x+y+w+z=1, the thickness of each layer being less than the critical thickness thereof, the number of patterns being at least equal to 50, an insert layer wherein the material has a first lattice parameter, a layer of gan material, wherein the lattice parameter is greater than the first lattice parameter such that the layer of gan material is compressed by the insert layer.. .
Commissariat A L'energie Atomique Et Aux Energies Alternatives