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This page is updated frequently with new Lattice-related patent applications. Subscribe to the Lattice RSS feed to automatically get the update: related Lattice RSS feeds. RSS updates for this page: Lattice RSS RSS


Schottky barrier diode and method of manufacturing the same

Schottky barrier diode and method of manufacturing the same

Energy generation apparatus and method

Energy generation apparatus and method

Energy generation apparatus and method

Solar cell and manufacturing method thereof

Date/App# patent app List of recent Lattice-related patents
07/02/15
20150189267
 Image projection device and calibration method thereof patent thumbnailnew patent Image projection device and calibration method thereof
There is provided an image projection device including a camera, a projector configured to project an image, a camera calibration unit configured to perform calibration of the camera, a projector calibration unit configured to perform calibration of the projector, and an image correction unit configured to correct the image projected from the projector based on a result of the calibration. The projector calibration unit performs ray tracing of a known checker pattern on which structural light is projected by the projector, and estimates parameters by acquiring correspondence relation between a lattice point of the checker pattern and projector coordinates..
07/02/15
20150188134
 Cathode active material for lithium-ion battery, cathode for lithium-ion battery and lithium-ion battery patent thumbnailnew patent Cathode active material for lithium-ion battery, cathode for lithium-ion battery and lithium-ion battery
A cathode active material for lithium-ion battery is provided, which provides good battery characteristics such as cycle characteristics. The cathode active material for lithium-ion battery is expressed by the composition formula: lixni1-ymyoα, wherein m is one or more selected from ti, cr, mn, fe, co, cu, al, sn, mg and zr; 0.9≦x≦1.2; 0<y≦0.5; and 2.0≦α≦2.2, wherein the crystallite size obtained by analyzing the xrd pattern is 870 Å or more and the unit lattice volume is 101.70 Å3 or less..
07/02/15
20150188034
 Magnetic tunnel junction device patent thumbnailnew patent Magnetic tunnel junction device
A magnetic tunnel junction device includes: a first magnetic layer that has an easy axis vertical to a surface; a non-magnetic layer on the first magnetic layer; and a second magnetic layer that has an easy axis vertical to a surface on the non-magnetic layer, and an interface layer formed of a heussler alloy between the non-magnetic layer and at least one of the first and second magnetic layers. The at least one of the first and second magnetic layers is formed of mnga.
07/02/15
20150187973
 Solar cell and manufacturing method thereof patent thumbnailnew patent Solar cell and manufacturing method thereof
A solar cell includes a semiconductor substrate of a first conductivity; a pillar-shaped structure constituted by a semiconductor of the first conductivity, the pillar-shaped structure being formed on the semiconductor substrate; a superlattice layer including a barrier layer and a quantum structure layer that are alternately deposited on a side wall of the pillar-shaped structure, the quantum structure layer being constituted by a material having a smaller energy bandgap than that of the barrier layer, the quantum structure layer including a wurtzite type crystal part and a zinc blende type crystal part that are alternately arranged along an axial direction of the pillar-shaped structure; and a semiconductor layer of a second conductivity that is formed so as to surround the superlattice layer, the second conductivity being an opposite conductivity to that of the first conductivity.. .
07/02/15
20150187962
 Schottky barrier diode and  manufacturing the same patent thumbnailnew patent Schottky barrier diode and manufacturing the same
A schottky barrier diode includes: an n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate; a first p+ region disposed on the n− type epitaxial layer; an n type epitaxial layer disposed on the n− type epitaxial layer and the first p+ region; a second p+ region disposed on the n type epitaxial layer, and being in contact with the first p+ region; a schottky electrode disposed on the n type epitaxial layer and the second p+ region; and an ohmic electrode disposed on a second surface of the n+ type silicon carbide substrate. Also, the first p+ region has a lattice shape including a plurality of vertical portions and horizontal portions connecting both ends of the respective vertical portions to each other..
07/02/15
20150187944
 Semiconductor liner of semiconductor device patent thumbnailnew patent Semiconductor liner of semiconductor device
The disclosure relates to a fin field effect transistor (finfet). An exemplary finfet comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower portion, an upper portion, and a middle portion between the lower portion and upper portion, wherein the fin structure comprises a first semiconductor material having a first lattice constant; a pair of notches extending into opposite sides of the middle portion; and a semiconductor liner adjoining the lower portion comprising a second semiconductor material having a second lattice constant greater than the first lattice constant..
07/02/15
20150187924
 Low sheet resistance gan channel on si substrates using inaln and algan bi-layer capping stack patent thumbnailnew patent Low sheet resistance gan channel on si substrates using inaln and algan bi-layer capping stack
Transistors or transistor layers include an inaln and algan bi-layer capping stack on a 2deg gan channel, such as for gan mos structures on si substrates. The gan channel may be formed in a gan buffer layer or stack, to compensate for the high crystal structure lattice size and coefficient of thermal expansion mismatch between gan and si.
07/02/15
20150187499
 Ceramic powder and multi-layer ceramic capacitor patent thumbnailnew patent Ceramic powder and multi-layer ceramic capacitor
A multi-layer ceramic capacitor is made by alternately layering a dielectric layer constituted by a sintered body of a ceramic powder, and an internal electrode layer. The ceramic powder contains barium titanate powder having a perovskite structure with a median size of 200 nm or smaller as measured by sem observation, wherein the barium titanate powder is such that the percentage of barium titanate particles having twin defects in the barium titanate powder is 13% or more as measured by tem observation and that its crystal lattice c/a is 1.0080 or more.
07/02/15
20150187444
 Energy generation apparatus and method patent thumbnailnew patent Energy generation apparatus and method
A practical technique for inducing and controlling the fusion of nuclei within a solid lattice. A reactor includes a loading source to provide the light nuclei which are to be fused, a lattice which can absorb the light nuclei, a source of phonon energy, and a control mechanism to start and stop stimulation of phonon energy and/or the loading of reactants.
07/02/15
20150184398
 Apparatus and related methods of paving a subsurface patent thumbnailnew patent Apparatus and related methods of paving a subsurface
Disclosed may be an intermediate surface for supporting a small paver, wherein the surface can also be used to exchange heat with the pavers. In one embodiment, the apparatus may be a hextray defined by a frame with a hexagonal lattice for supporting pavers.
06/25/15
20150181191

Synthesis-parameter generation device for three-dimensional measurement apparatus


A plurality of units (4) constituted by a projector (6) that projects a periodic lattice onto a measurement target (1) and a camera (8) that images the projected lattice are included around the measurement target (1), and three-dimensional coordinates measured by the respective units (4) are composited by coordinate conversion. A first lattice that is displayed on a reference surface (42) is imaged, and phases with respect to the first lattice are obtained for respective pixels of the cameras (8) and stored.
Shima Seiki Mfg., Ltd.
06/25/15
20150180630

Scattered pilot pattern and channel estimation mimo-ofdm systems


A method and apparatus are provided for reducing the number of pilot symbols within a mimo-ofdm communication system, and for improving channel estimation within such a system. For each transmitting antenna in an ofdm transmitter, pilot symbols are encoded so as to be unique to the transmitting antenna.
Blackberry Limited
06/25/15
20150179863

Avalanche photodiode utilizing interfacial misfit array


According to some embodiments of the present invention, an avalanche photodiode includes a first electrode, a second electrode spaced apart from the first electrode, a photon absorber layer formed to be in electrical connection with the first electrode, and a charge-carrier multiplication layer formed to be in electrical connection with the second electrode. The photon absorber layer is a semiconducting material that has a first lattice constant, and the charge-carrier multiplication layer is a semiconducting material that has a second lattice constant that is different from the first lattice constant.
Lancaster University Business Enterprises Ltd
06/25/15
20150179861

Etching of infrared sensor membrane


The invention relates to an infrared thermal sensor comprising a substrate having a cavity, a cavity bottom wall formed by a continuous substrate surface. The sensor comprises a membrane adapted for receiving heat from incident infrared radiation, a beam suspending the membrane, and a thermocouple.
Melexis Technologies Nv
06/25/15
20150179845

Solid-state imaging device, light detecting device, and electronic apparatus


A solid-state imaging device includes a multi-quantum wells (mqw) structure which combines and uses a non-group iv lattice matching-based compound semiconductor with an absolute value of a mismatch ratio of less than 1% on a silicon substrate so as to have sensitivity to at least infrared light.. .
Sony Corporation
06/25/15
20150179768

Fin structure of semiconductor device


The disclosure relates to a fin field effect transistor (finfet). An exemplary finfet comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising an upper portion comprising a first semiconductor material having a first lattice constant, wherein the upper portion comprises a first substantially vertical portion having a first width and a second substantially vertical portion having a second width less than the first width over the first substantially vertical portion; and a lower portion comprising a second semiconductor material having a second lattice constant less than the first lattice constant, wherein a top surface of the lower portion has a third width less than the first width; and a gate structure covering the second substantially vertical portion..
Taiwan Semiconductor Manufacturing Company, Ltd.
06/25/15
20150179742

Active regions with compatible dielectric layers


A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material.
06/25/15
20150179664

Heterogeneous semiconductor material integration techniques


Techniques are disclosed for heteroepitaxial growth of a layer of lattice-mismatched semiconductor material on an initial substrate, and transfer of a defect-free portion of that layer to a handle wafer or other suitable substrate for integration. In accordance with some embodiments, transfer may result in the presence of island-like oxide structures on the handle wafer/substrate, each having a defect-free island of the lattice-mismatched semiconductor material embedded within its upper surface.
06/25/15
20150179166

Decoder, decoding method, and computer program product


According to an embodiment, a decoder includes a token operating unit, a node adder, and a connection detector. The token operating unit is configured to, every time a signal or a feature is input, propagate each of a plurality of tokens, which is an object assigned with a state of the of a path being searched, according to a digraph until a state or a transition assigned with a non-empty input symbol is reached.
Kabushiki Kaisha Toshiba
06/25/15
20150178584

Shape detection and ellipse fitting of a polygon


A method of shape detection detects a figure with a contouring loop method that extracts at least one iso-contour polygon from a set of pixels in an image using a triangular lattice superimposed over the set of pixels of the image. Then starting from an original triangle, the iso-contour polygon is extracted by selecting an intensity chroma value within the set of pixels between three corners of a triangle to find a directed line segment that represent the crossing of the intensity value within the triangle, and an exit point of the directed line segment and a nearest triangle which contains the next directed line segment of the at least one iso-contour polygon are determined to create a first matrix of points on the at least one iso-contour polygon, until arriving at the original triangle..
06/25/15
20150177727

Numerical controller provided with function of correcting displacement error caused by work


A numerical controller uses a work lattice region setting unit and a rotation axis work lattice region setting unit to form lattice points for error correction and uses a work-caused translation correction amount setting unit to set a correction amount of a work-caused translation error. A work-caused translation correction amount calculation unit calculates a correction amount at a tool center point position, and a correction section of the numerical controller adds the work-caused translation correction amount to positions of three commanded linear axes for error correction..
Fanuc Corporation
06/25/15
20150177438

Display having backlight with narrowband collimated light sources


A display has an array of display pixels formed from display layers such as one or more polarizer layers, a substrate on which an array of display pixel elements such as color filter elements and downconverter elements are formed, a liquid crystal layer, and a thin-film transistor layer that includes display pixel electrodes and display pixel thin-film transistors for driving control signals onto the display pixel electrodes to modulate light passing through the display pixels. A light source such as one or more laser diodes or light-emitting diodes may be used to generate light for the display.
Apple Inc.
06/25/15
20150176775

Display having backlight with narrowband collimated light sources


A display has an array of display pixels formed from display layers such as one or more polarizer layers, a substrate on which an array of display pixel elements such as color filter elements and downconverter elements are formed, a liquid crystal layer, and a thin-film transistor layer that includes display pixel electrodes and display pixel thin-film transistors for driving control signals onto the display pixel electrodes to modulate light passing through the display pixels. A light source such as one or more laser diodes or light-emitting diodes may be used to generate light for the display.
Apple Inc.
06/25/15
20150176293

Movable centring for port platforms


Movable centring for platforms in ports which comprises a mobile structure (1) with various formworks (2) and is supported on piles (3). The support of the mobile structure (1) on the piles (3) is carried out by means of, at least, two supporting devices (5), wherein each supporting device (5) comprises one front supporting beam (6d), which comprises at least two coupling pieces (18), one rear supporting beam (6t) which comprises at least two coupling pieces (18) and a lattice (7), beneath each supporting beam (6d, 6t).
Rubrica Ingenieria Y Arquitectura, S.l.
06/25/15
20150175432

Magnesium modified ultra-stable rare earth y-type molecular sieve and preparation method therefor


The present invention provides a magnesium-modified ultra-stable rare earth type y molecular sieve and the preparation method thereof, which method is carried out by subjecting a nay molecular sieve as the raw material to a rare earth exchange and a dispersing pre-exchange, then to an ultra-stabilization calcination treatment, and finally to a magnesium modification. The molecular sieve comprises 0.2 to 5% by weight of magnesium oxide, 1 to 20% by weight of rare earth oxide, and not more than 1.2% by weight of sodium oxide, and has a crystallinity of 46 to 63%, and a lattice parameter of 2.454 nm to 2.471 nm.
Petrochina Company Limited
06/25/15
20150174442

Gripper wraps


Embodiments of the current invention are directed towards solving the need for weightlifting wraps which prevent slippage, increase rebound potential, allow simpler application, and provide greater stability. An embodiment of the invention comprises: gripper wraps made of stretchable material; the gripper wraps having exposed rubber strands on one outer surface of the gripper wraps; the exposed rubber strands arranged in an offset lattice configuration, wherein the exposed rubber strands have a coefficient of friction sufficient to grip the previous layer of wrap..
06/18/15
20150171275

Gan based semiconductor light-emitting device and producing same


A gan based semiconductor light-emitting device is provided. The light-emitting device includes a first gan based compound semiconductor layer of an n-conductivity type; an active layer; a second gan based compound semiconductor layer; an underlying layer composed of a gan based compound semiconductor, the underlying layer being disposed between the first gan based compound semiconductor layer and the active layer; and a superlattice layer composed of a gan based compound semiconductor doped with a p-type dopant, the superlattice layer being disposed between the active layer and the second gan based compound semiconductor layer..
Sony Corporation
06/18/15
20150171252

Solar cell apparatus


A solar cell apparatus includes a substrate where a transmission area and a non-transmission area adjacent to the transmission area are defined; a solar cell disposed at the non-transmission area on the substrate; and a lattice pattern disposed at the non-transmission area.. .
Lg Innotek Co., Ltd.
06/18/15
20150171242

Solid-state imaging device and electronic apparatus


A solid-state imaging device includes a photoelectric conversion device that includes a non-chalcopyrite-based compound semiconductor of at least one layer, which is lattice bonded or pseudo lattice bonded, and is formed on a silicon substrate, and a chalcopyrite-based compound semiconductor of at least one layer which is formed on the non-chalcopyrite-based compound semiconductor.. .
Sony Corporation
06/18/15
20150171187

Finfets and methods for forming the same


A finfet and methods for forming a finfet are disclosed. A structure comprises a substrate, a fin, a gate dielectric, and a gate electrode.
Taiwan Semiconductor Manufacturing Company, Ltd.
06/18/15
20150170838

Laminated ceramic capacitor and manufacturing laminated ceramic capacitor


A laminated ceramic capacitor that includes a ceramic laminated body of a plurality of stacked ceramic dielectric layers, a plurality of internal electrodes opposed to each other with the ceramic dielectric layers interposed therebetween within the ceramic laminated body, and external electrodes provided on the outer surface of the ceramic laminated body and electrically connected to the internal electrodes. The internal electrodes contain ni as a main constituent, and the ni constituting the internal electrodes has a lattice constant in the range of 0.3250 nm to 0.3450 nm..
Murata Manufacturing Co., Ltd.
06/18/15
20150169290

Method of spectral tests of multiplicative congruential random number generators


The present invention discloses a new method of spectral tests, on multiplicative congruential generator (d,z,n) or (d,z) comprising an odd integer d for the modulus and an integer z coprime with d for the multiplier and an integer n coprime with d for the seed and generating the sequence of integers {nk:≡nzk−1 mod(d). .
1≦nk≦d, k=1,2, . . . } consecutively and giving the output random number sequence by realizing the arithmetic {vk:=nk/d
06/18/15
20150168609

Antireflective article, image display device, and production mold for antireflective article


In order to improve the scratch resistance of an antireflective article having a moth-eye structure, an antireflective article is provided that has fine protrusions densely arranged therein, has the interval between adjacent fine protrusions being no more than the shortest wavelength for an electromagnetic wavelength band for antireflection, and wherein: the fine protrusions are arranged in a non-lattice shape in the planar view; and mesh division lines formed upon the valley sections between each adjacent fine protrusions and surrounding each fine protrusion match voronoi tessellation having the center of gravity of the fine protrusions, in the planar view as the generating point therefor, in at least one area of the antireflective article.. .
Dai Nippon Printing Co., Ltd.
06/18/15
20150167644

Lattice tower assembly for a wind turbine


The present subject matter is directed to a lattice tower covering and/or assembly for a wind turbine. The lattice tower assembly includes a plurality of structural members connected together to define an open lattice tower.
General Electric Company
06/18/15
20150167198

Substrate structures and methods


A process for separating a substrate from an epitaxial layer comprises forming a multilayer substrate comprising a substrate, a lattice matching layer and an epitaxial layer. The method further comprises etching the lattice matching layer by one of a liquid or a vapor phase acid.
Tivra Corporation
06/11/15
20150163923

Sub-micron laser patterning of graphene and 2d materials


An appropriately configured pulsed laser is focused onto a graphene sheet and is used to form a desired pattern in the graphene. When the laser pulse strikes the graphene, it modifies the bonding state of the carbon atoms in the graphene lattice, acting as a “blade” and causing a separation in the graphene sheet at the site of the laser pulse without causing damage to the surrounding graphene.
The Government Of The United States Of America, As Represented By The Secretary Of The Navy
06/11/15
20150162622

Large-surface-area, unsupported catalyst for electro-chemical processes and producing same


A catalyst is to avoid the corrosion of a support and still have an active surface area of more than 30 m2/gmetal, preferably more than 50 m2/gmetal, particularly preferably more than 70 m2/gmetal. It has a high dispersion, achieving high stability and high activity (selectivity).
Technische Universitaet Dresden
06/11/15
20150162485

Ohmic n-contact formed at low temperature in inverted metamorphic multijunction solar cells


A method of forming a multijunction solar cell including an upper subcell, a middle subcell, and a lower subcell by providing a substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on the substrate having a first band gap; forming a second solar subcell over the first solar subcell having a second band gap smaller than the first band gap; forming a graded interlayer over the second subcell, the graded interlayer having a third band gap greater than the second band gap; forming a third solar subcell over the graded interlayer having a fourth band gap smaller than the second band gap such that the third subcell is lattice mismatched with respect to the second subcell; and forming a contact composed of a sequence of layers over the first subcell at a temperature of 280° c. Or less and having a contact resistance of less than 5×10−4 ohms-cm2..
Emcore Solar Power, Inc.
06/11/15
20150162471

Phototransistor device


The present disclosure provides a heterostructure bipolar phototransistor configured for providing an output signal in response to an external impinging light beam. The heterostructure bipolar phototransistor comprises an emitter region and a collector region being doped so that they are of the same conductivity type; a base region interposed between the emitter region and the collector region, the base region being doped so that it is of the opposite conductivity type than the emitter region and the collector region; and an absorption region interposed between the base region and the collector region, wherein the absorption region comprises (or is formed of) a superlattice..
Elta Systems Ltd.
06/11/15
20150162447

Finfet having superlattice stressor


A fin field effect transistor (finfet) device is provided. The finfet includes a superlattice layer and a strained layer.
Taiwan Semiconductor Manufacturing Company, Ltd.
06/11/15
20150162446

Cmos devices with stressed channel regions, and methods for fabricating the same


Complementary metal-oxide-semiconductor (cmos) devices with stressed channel regions are provided. Each cmos device comprises an field effect transistor (fet) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes.
International Business Machines Corporation
06/11/15
20150160481

Optical device having multiple quantum well structure lattice-matched to gaas substrate, and depth image acquisition apparatus and 3d image acquisition apparatus including the optical device


An optical device includes a gallium arsenide (gaas) substrate, and a multiple quantum well structure formed on the gaas substrate and having a quantum well layer and a quantum barrier layer. In the optical device, the quantum well layer is formed of a first semiconductor material that has a bandgap energy which is lower than that of the gaas substrate and receives a compressive strain from the gaas substrate, and the quantum barrier layer is formed of a second semiconductor material that has a bandgap energy which is higher than that of the gaas substrate and receives a tensile strain from the gaas substrate..
Samsung Electronics Co., Ltd.
06/11/15
20150160306

Orthogonal fluxgate sensor


There is provided an orthogonal fluxgate sensor including: a magnetic core unit having a lattice structure; first and second coils enclosing the magnetic core unit in a solenoid form; and a third coil surrounding the magnetic core unit and the first and second coils, wherein the first and second coils are disposed to be perpendicular to one another, and when an alternating current (ac) power source is connected to at least one of the first and second coils, an ac voltmeter is connected to the third coil, and when the ac power source is connected to the third coil, the ac voltmeter is connected to at least one of the first and second coils.. .
Samsung Electro-mechanics Co., Ltd.
06/11/15
20150160005

Three-dimensional measurement apparatus, and three-dimensional measurement method


A lattice is projected multiple times from projectors (p1; p2) onto a measurement target object (1) while being shifted, the measurement target object (1) onto which the lattice is projected is imaged by a camera (c1), and conversion into the three-dimensional shape of the measurement target object (1) is performed. Two projectors (p1; p2) are provided respectively at positions that are close to and far from the camera (c1), and, using phases obtained from images captured during projection from the projector (p1) that is provided at the position close to the camera (c1), phases obtained from images captured during projection from the projector (p2) that is provided at the position far from the camera (c1) are converted into phases by which positions in line of sight directions from the camera (c1) are uniquely indicated.
Shima Seiki Mfg., Ltd.
06/11/15
20150159366

Collapsible cellular insulation


Multi-layered insulation is disclosed for having a collapsed configuration in which one dimension of the insulation is minimized to reduce the volume for storage. The multi-layered insulation has an expanded configuration in which the dimension is maximized to separate outer layers of the insulation.
L'garde, Inc.
06/11/15
20150158442

Hybrid crash box for vehicle


Provided is a hybrid crash box for a vehicle that includes a latticed box pipe connected with a bumper beam and a mount mounted on a bumper stay. The latticed box pipe may include a metallic hollow pipe and plastic lattices integrally formed in the hollow pipe by injection molding.
Hyundai Motor Company
06/11/15
20150156974

Vertical landscaping system


A system which includes a series of hanging baskets having latticed walls and on which a substrate or mesh for plants is arranged. The baskets being hung either from guides attached by screws to a wall in order to form a vertical planting system adjacent to the wall, or mounted on posts attached independently to the ground in order to form separations or divisions between private and common areas or to separate two rooms.
06/04/15
20150155478

Quantum well device with lateral electrodes


An apparatus includes a substrate having a planar top surface, a sequence of crystalline semiconductor layers located on the planar surface, and first and second sets of electrodes located over the sequence. The sequence of crystalline semiconductor layers has a 2d quantum well therein.
Alcatel Lucent
06/04/15
20150155420

Optical device based on bismuth-containing iii-v compound multilayer semiconductors


Optical devices based on bismuth-containing iii-v compound semiconductor materials are disclosed. The optical device includes an optically active pseudomorphic superlattice formed on a substrate.
Arizona Board Of Regents On Behalf Of Arizona State University
06/04/15
20150155357

Iii-nitride semiconductor structures with strain absorbing interlayers


There are disclosed herein various implementations of semiconductor structures including iii-nitride interlayer modules. One exemplary implementation comprises a substrate and a first transition body over the substrate.
International Rectifier Corpoation
06/04/15
20150155160

Diamond semiconductor system and method


Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein the donor atoms contribute conduction electrons with mobility greater than 770 cm2/vs to the diamond lattice at 100 kpa and 300k, and wherein the n-type donor atoms are introduced to the lattice through ion tracks..
06/04/15
20150152664

Node structures for lattice frames


A node structure (12, 14) for connecting two or more convergent members (16, 26) of a lattice frame to each other and to one or more other members of the lattice frame. The node structure (12, 14) comprises a pair of opposed spaced-apart faces (30) that are substantially planar and substantially parallel to each other.
Vestas Wind Systems A/s
06/04/15
20150151859

Fragmentation and dispensing apparatus of gel plate and fragmentation and dispensing the same


Using a microtiter plate 10 and a pressing tool 20, a gel plate 30 is divided into gel fragments 31 and the gel fragments 31 are then dispensed into respective wells 11 of the microtiter plate 10. In the microtiter plate 10, end portions 13 of a lattice-shaped partition wall 12 constituting the wells 11 of a square shape are formed to be sharp.
06/04/15
20150151284

Ultra-stable rare earth y-type molecular sieve and preparation method therefor


The present invention provides an ultra-stable rare earth type y molecular sieve and the preparation method thereof, which method is carried out by subjecting a nay molecular sieve as the raw material to a rare earth exchange and a dispersing pre-exchange, then to an ultra-stabilization calcination treatment. The molecular sieve comprises 1 to 20% by weight of rare earth oxide, not more than 1.2% by weight of sodium oxide, has a crystallinity of 51 to 69%, and a lattice parameter of 2.451 nm to 2.469 nm.
Petrochina Company Limited
05/28/15
20150147880

Contact structure and formation thereof


A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure.
Taiwan Semiconductor Manufacturing Company Limited
05/28/15
20150147663

Electrical energy storage device with non-aqueous electrolyte


An electrical energy storage device 20 is disclosed as a secondary battery device 22 having an anode 28 containing aluminum and indium and a cathode 38 that includes an electroactive layer 42 with a host lattice 44 having a conjugated system with delocalized it electrons. A dopant 48 containing aluminum is bonded with and intercalated in the host lattice 44.
05/28/15
20150146756

Semiconductor light emitting element


A semiconductor light emitting element includes an n-type light guide layer containing a group iii nitride semiconductor, an active layer, and a p-type light guide layer, in which the n-type light guide layer includes a semiconductor superlattice layer which is a stack of superlattice layers, the semiconductor superlattice layer having a structure in which group iii nitride semiconductors a and group iii nitride semiconductors b are alternately stacked, each of the semiconductors a and each of the semiconductors b being stacked in each of the superlattice layers, a relationship eg (a)>eg (b) holds, the semiconductor a is a film containing alinn, and the film contains oxygen (o) at a concentration of at least 1×1018 cm−3, the semiconductor a has a film thickness of at most 5 nm, and a current is injected in a stacking direction of the superlattice layers.. .
Panasonic Intellectual Property Management Co., Ltd.
05/28/15
20150146341

Ald dielectric films with leakage-reducing impurity layers


A thin sub-layer (<15 Å) of an impurity is formed under, over, or inside a thicker layer (˜30-100 Å) of a high-k (k>12) host material. The sub-layer may be formed by atomic layer deposition (ald).
Intermolecular Inc.
05/28/15
20150145513

Hybrid saturation recovery-inversion recovery pulse sequence for improved nmr logging of boreholes


A nuclear magnetic resonance (nmr) logging method includes providing a hybrid pulse sequence having a saturation pulse, an inversion pulse, and a detection sequence. The method also includes measuring echo signals in response to the hybrid pulse sequence.
Halliburton Energy Services, Inc.
05/28/15
20150145105

High-resistive silicon substrate with a reduced radio frequency loss for a radio-frequency integrated passive device


The application relates to a high-resistivity silicon substrate (100) with a reduced radio frequency loss for a radio frequency integrated passive device. The substrate comprising a bulk zone (110) comprising high-resistivity bulk silicon and a preserved sub-surface lattice damage zone (120b) comprising fractured silicon above the bulk zone.
Okmetic Oyj
05/28/15
20150145001

Selective nanoscale growth of lattice mismatched materials


Exemplary embodiments provide materials and methods of forming high-quality semiconductor devices using lattice-mismatched materials. In one embodiment, a composite film including one or more substantially-single-particle-thick nanoparticle layers can be deposited over a substrate as a nanoscale selective growth mask for epitaxially growing lattice-mismatched materials over the substrate..
05/28/15
20150144999

Structure and finfet device with buried sige oxide


The present disclosure provides a semiconductor device that includes a substrate of a first semiconductor material; a fin feature having a first portion, a second portion and a third portion stacked on the substrate; an isolation feature formed on the substrate and disposed on sides of the fin feature; semiconductor oxide features including a second semiconductor material, disposed on recessed sidewalls of the second portion, defining dented voids overlying the semiconductor oxide features and underlying the third portion; and a gate stack disposed on the fin feature and the isolation feature. The gate stack includes a gate dielectric layer extended into and filling in the dented voids.
Taiwan Semiconductor Manufacturing Company, Ltd.
05/28/15
20150144998

Fin structure of semiconductor device


A fin structure of a semiconductor device, such as a fin field effect transistor (finfet), and a method of manufacture, is provided. In an embodiment, trenches are formed in a substrate, and a liner is formed along sidewalls of the trenches, wherein a region between adjacent trenches define a fin.
Taiwan Semiconductor Manufacturing Company, Ltd.
05/28/15
20150144962

Complementarily strained finfet structure


A complementary fin field-effect transistor (finfet) includes a p-type device having a p-channel fin. The p-channel fin may include a first material that is lattice mismatched relative to a semiconductor substrate.
Qualcomm Incorporated
05/28/15
20150144880

Non-planar gate all-around device and fabrication thereof


A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant.
Intel Corporation
05/28/15
20150144878

Semiconductor devices including superlattice depletion layer stack and related methods


A semiconductor device may include an alternating stack of superlattice and bulk semiconductor layers on a substrate, with each superlattice layer including a plurality of stacked group of layers, and each group of layers of the superlattice layer including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include spaced apart source and drain regions in an upper bulk semiconductor layer of the alternating stack of superlattice and bulk semiconductor layers, and a gate on the upper bulk semiconductor layer between the spaced apart source and drain regions..
Mears Technologies, Inc.
05/28/15
20150144877

Vertical semiconductor devices including superlattice punch through stop layer and related methods


A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion.
Mears Technologies, Inc.
05/28/15
20150144871

Laterally-injected light-emitting diode and laser diode


A p-type superlattice is used to laterally inject holes into an iii-nitride multiple quantum well active layer, enabling efficient light extraction from the active area. Laterally-injected light-emitting diodes and laser diodes can enable brighter, more efficient devices that impact a wide range of wavelengths and applications.
Sandia Corporation
05/28/15
20150144865

Phase-change memory and semiconductor recording/reproducing device


Technology capable of improving performance of a phase-change memory is provided. A recording/reproducing film contains sn (tin), sb (antimony), and te (tellurium) and also contains an element x having a bonding strength with te stronger than a bonding strength between sn and te and a bonding strength between sb and te.
National Institute Of Advanced Industrial Science And Technology


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Lattice topics: Semiconductor, Semiconductor Device, Semiconductor Material, Crystallin, Disconnect, Transistors, Replacement Gate, Semiconductor Devices, Dislocations, Dislocation, Image Processing, Coordinates, Surface Plasmon Polariton, Antenna Array

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