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Lattice patents


This page is updated frequently with new Lattice-related patent applications.

new patent Monolithic nanophotonic device on a semiconductor substrate
A photonic light generating device is provided on a portion of a first semiconductor material. The photonic light generating device includes a second semiconductor material that has a different lattice constant than the lattice constant of the first semiconductor material and that is capable of generating and emitting light.
International Business Machines Corporation

new patent Composite quantum-dot materials for photonic detectors
A composite quantum-dot photodetector comprising a substrate with a colloidally deposited thin film structure forming a photosensitive region, the thin film containing at least one type of a nanocrystal quantum-dot, whereby the nanocrystal quantum dots are spaced by ligands to form a lattice, and the lattice of the quantum dots has an infill material that forms an inorganic matrix that isolates the nanocrystal quantum dots from atmospheric exposure.. .
Vadient Optics, Llc.

new patent Fin structure of semiconductor device
The disclosure relates to a fin field effect transistor (finfet). An exemplary finfet comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising an upper portion comprising a first semiconductor material having a first lattice constant, wherein the upper portion comprises a first substantially vertical portion having a first width and a second substantially vertical portion having a second width less than the first width over the first substantially vertical portion; and a lower portion comprising a second semiconductor material having a second lattice constant less than the first lattice constant, wherein a top surface of the lower portion has a third width less than the first width; and a gate structure covering the second substantially vertical portion..
Taiwan Semiconductor Manufacturing Company, Ltd.

new patent Horizontal gate all around device isolation
Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hgaa) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate.
Applied Materials, Inc.

new patent Adaptive multi-stage disturbance rejection
Apparatus and method for controlling the position of a control object using a multi-stage actuator. In some embodiments, a multi-stage actuator is provided with first and second actuation stages adapted to position a control object.
Seagate Technology Llc

new patent Lattice mast having an open framework structure in particular an electricity pylon or telecommunication mast, and increasing the stability of lattice masts having an open framework structure
The invention relates to a lattice mast (1) with an open framework structure of angled profiles (3), in particular an electricity pylon or telecommunications mast, comprising at least one or more cladding profiles (9a, 9b) which extend over at least part of the length of at least one angled profile (3), wherein at least one cladding profile has a curved incident-flow surface and forms a flow shielding of a wind-exposed edge of the angled profile (3), wherein the incident-flow surface is at least approximately spherically curved and has a flow resistance coefficient which is less than that of the unshielded angled profile (3).. .
Rwe Innogy Gmbh

new patent Method for manufacturing three-dimensional lattice truss structure using flexible linear bodies
A method for manufacturing a three-dimensional lattice truss structure using flexible wires, including: arranging a plurality of out-of-plane wires; forming crossing portions between the plurality of out-of-plane wires; inserting a plurality of in-plane wires in the crossing portions; translating the plurality of in-plane wires in the z-direction; and inserting boundary rods in the y- or x-direction inside the plurality of out-of-plane wire groups.. .
Industry Foundation Of Chonnam National University

new patent Engineered band gaps
An optoelectronic device as well as its methods of use and manufacture are disclosed. In one embodiment, an optoelectronic device includes first and second semiconducting atomically thin layers with corresponding first and second lattice directions.
Massachusetts Institute Of Technology

Dual mode iii-v superlattice avalanche photodiode
In one aspect, an avalanche photodiode, includes an absorber, a first superlattice structure directly connected to the absorber and configured to multiply holes and a second superlattice structure directly connected to the first superlattice structure and configured to multiply electrons. The first and second superlattice structures include iii-v semiconductor material.
Raytheon Company

Aspect ratio trapping (art) for fabricating vertical semiconductor devices
Aspect ratio trapping (art) approaches for fabricating vertical semiconductor devices and vertical semiconductor devices fabricated there from are described. For example, a semiconductor device includes a substrate with an uppermost surface having a first lattice constant.
Intel Corporation

Lattice structure interfacing

Methods, systems, and apparatus, including medium-encoded computer program products, for designing three dimensional lattice structures include, in one aspect, a method including: obtaining a lattice within a 3d lattice design space for a 3d model being created with a 3d modeling program; identifying junctions in the lattice that are potential sources of particle traps at an interface between the 3d lattice design space and a surface present in the 3d model; and removing the potential sources of particle traps by modifying cell space defined between the identified junctions and the surface. In addition, the surface can be a surface of a solid region defined in the 3d model, and the method can include: identifying beams in the lattice having junctions lying on the surface; and extending each of the identified beams by a length amount to cause overlap between the identified beams and the solid region..
Within Technologies Ltd.

System and assembling tower sections of a wind turbine lattice tower structure

In one aspect, a method for assembling a tower section of a lattice tower structure for a wind turbine on a tower assembly fixture may generally include installing a first trolley onto a first fixture arm of the fixture and installing a second trolley onto a second fixture arm of the fixture. In addition, the method may include securing a first support leg of the tower section to the first trolley, securing a second support leg of the tower section to the second trolley and coupling at least one secondary support member between the first and seconds support legs..
General Electric Company

Gas barrier film and producing it

The invention provides a gas barrier film with low deterioration in the gas barrier property before and after high-temperature hot water treatment. The gas barrier film has a gas barrier coating film, formed as a composite film comprising a network structure having a mesh structure with si—o—si bonds as the basic lattice and a water-soluble polymer crystallized as microcrystals, incorporated into the mesh of the network structure, wherein a barrier coating agent, obtained by mixing a condensate solution of an alkoxysilane hydrolysate prepared as a mixed solution in which the proportion of bonded states of the silicon atoms of the condensate with q1 and q2 structures is at least 60% of the total silicon atoms, with a crystalline water-soluble polymer, is coated on a base material film, either after forming or without forming an aluminum oxide vapor deposition film, to form a coating layer..
Dai Nippon Printing Co., Ltd.

Packing box, packing method and unpacking method

A packing box including lattice members which are arranged in a stacked state into stages, a stage-partition plate which is arranged between the stages of the lattice members, two or more inner tubular-trunk frames which are provided in a stacking direction of the lattice members to surround one or more stages of the lattice members, an outer tubular-trunk frame surrounding an outside of two or more stages of the inner tubular-trunk frames, a bottom lid which is arranged under the outer tubular-trunk frame, and a top lid which is arranged on the outer tubular-trunk frame.. .
Mitsubishi Materials Corporation

Tissue thickness compensator comprising resilient members

A tissue thickness compensator comprising at least one woven lattice can be positioned in the end effector of a surgical instrument. A fastener cartridge that is positioned in the end effector can comprise at least one cavity configured to receive a fastener.
Ethicon Endo-surgery, Llc

Hair bands with easy to change fashion accessories and storage and display cases

The present invention is directed to a hair band for keeping hair out of the face of the wearer, comprising a band having two surfaces, an inner surface that contacts the head and hair of an individual, which is formed to fit the head over the hair in a vertical orientation, and an outer surface that face away from the head, wherein the band has a multitude of magnets distributed along the length of the band, or wherein the band has an opening through the inner and outer surfaces that runs the majority of the length of the band. In one embodiment, the opening has a soft plastic or silicon strip inserted therein, wherein the strip has a series of openings or holes formed down its length or the opening has a lattice formed within the opening of the band, wherein the lattice is created by a series of crisscrossing strings or strands, and the holes formed by the lattice allow for one or more tabs to be inserted therein to allow fashion accessories that have tabs to be attached to the hair band.

Method of using a sacrifical gate structure to make a metal gate finfet transistor

A self-aligned sige finfet device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium.
Stmicroelectronics, Inc.

Semiconductor devices

Semiconductor devices include a channel layer on a substrate, the channel layer including a material having a lattice constant different from a lattice constant of the substrate, a first gate electrode on the channel layer, a first source region of a first conductivity type at a first side of the first gate electrode, a first body region of a second conductivity type under the first source region and contacting the first source region, a first drain region of the first conductivity type disposed at a second side of the first gate electrode, a first drift region of the first conductivity type under the first drain region and contacting the first drain region, and a first stud region in the channel layer and the first drift region. The first stud region has an impurity concentration higher than an impurity concentration of the first drift region..
Samsung Electronics Co., Ltd.

Ultrathin superlattice of mno/mn/mnn and other metal oxide/metal/metal nitride liners and caps for copper low dielectric constant interconnects

An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure.
International Business Machines Corporation

Method of forming fin structure of semiconductor device

A method of forming a fin structure of a semiconductor device, such as a fin field effect transistor (finfet) is provided. In an embodiment, trenches are formed in a substrate, and a liner is formed along sidewalls of the trenches, wherein a region between adjacent trenches define a fin.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor wafer, semiconductor device diced from semiconductor wafer, and manufacturing semiconductor device

A semiconductor wafer is provided with a substrate, a gan type semiconductor film which is laminated on the substrate, a plurality of element regions which are provided on the gan type semiconductor film, a dielectric film which is laminated on the gan type semiconductor film, and a dicing region which has a dicing groove which is provided in a lattice form without passing through the dielectric film described above so as to partition the element regions described above. Then, an end on the element region side of the dicing groove is higher or lower than a central portion of the dicing groove in a width direction in a bottom surface of the dicing groove..
Sharp Kabushiki Kaisha

Circumferential coating material and circumferentially coated honeycomb structure

A circumferential coating material contains colloidal silica, silicon carbide, and titanium oxide different in particle diameters from silicon carbide, coats a circumferential surface of a honeycomb structure monolithically formed by extrusion, including as a main component, cordierite having a porosity of 50 to 75%, and forms a circumferential coating layer. A circumferentially coated honeycomb structure has a honeycomb structure comprising latticed porous partition walls defining and forming a plurality of polygonal cells forming through channels and extending from one end face to the other end face, and a circumferential coating layer formed by coating at least a part of a circumferential surface of the honeycomb structure with the circumferential coating material..
Ngk Insulators, Ltd.

Synthesis of oxygen-mobility enhanced ceo2 and use thereof

Disclosed are catalysts capable of catalyzing the dry reforming of methane. The catalysts have a core-shell structure with the shell surrounding the core.
Sabic Global Technologies B.v.

Light emitting diode having well and/or barrier layers with superlattice structure

A light emitting diode includes an n-type gan-based semiconductor compound layer, a p-type gan-based semiconductor compound layer, and an active region disposed between the p-type and n-type layers, the active region comprising alternately laminated well layers and barrier layers. The well layers comprise alxinyga1−(x+y)n, where 0≦x, y≦1, the barrier layers comprise alxinyga1−(x+y)n, where 0≦x, y≦1, and at least one of the barrier layers comprises first and second layers having different compositions..
Seoul Viosys Co., Ltd.

Integrated multi-color light emitting device made with hybrid crystal structure

An integrated hybrid crystal light emitting diode (“led”) display device that may emit red, green, and blue colors on a single wafer. The various embodiments may provide double-sided hetero crystal growth with hexagonal wurtzite iii-nitride compound semiconductor on one side of (0001) c-plane sapphire media and cubic zinc-blended iii-v or ii-vi compound semiconductor on the opposite side of c-plane sapphire media.
U.s.a. As Represented By The Administrator Of The National Aeronautics And Space Administration

Multi solar cell

A multi-junction solar cell having a first subcell made of an ingaas compound. The first subcell has a first lattice constant and a second subcell has a second lattice constant.
Azur Space Solar Power Gmbh

Quantum-dot-in-perovskite solids

The present disclosure provides a composite material of a pre-formed crystalline or polycrystalline semiconductor particles embedded in a crystalline or polycrystalline perovskite matrix material. The pre-formed crystalline or polycrystalline semiconductor particles and and crystalline or polycrystalline perovskite being selected so that any lattice mismatch between the two lattices does not exceed about 10%.
The Governing Council Of The University Of Toronto

Iii-v gate-all-around field effect transistor using aspect ratio trapping

Embodiments of the invention provide methods for forming iii-v gate-all-around field effect transistors on silicon substrates that utilize aspect-ratio trapping to reduce or eliminate dislocation defects associated with lattice mismatches. A field dielectric material defining a trench is formed on a crystalline silicon substrate.
International Business Machines Corporation

Crystalline semiconductor growth on amorphous and poly-crystalline substrates

A multilayer semiconductor structure including at least in part a substrate and an iii-n film layer. The substrate's constant of thermal expansion being substantially matched to the iii-n film's constant of thermal expansion.
Tivra Corporation

System and assembling tower sections of a wind turbine lattice tower structure

A system for assembling a tower section of a lattice tower structure for a wind turbine may generally include a tower assembly fixture having a plurality of radially extending fixture arms, wherein each fixture arm extends between a first end and a second end. In addition, the system may include a plurality of trolleys.
General Electric Company

Partial cuff

Aspects of the present disclosure are directed toward providing enhanced structural support to an organ. As may be implemented in accordance with one or more embodiments, an apparatus includes structure configured and arranged to partially encircle a tubular organ, having a semi-cylindrical shape with a tapered end and blunt end of the cylinder.

Soles for sport shoes

The present invention generally relates to soles in particular midsoles for sports shoes. According to an aspect, an additively manufactured sole is provided.
Adidas Ag

Rc lattice delay

An integrated constant time delay circuit utilized in continuous-time (ct) analog-to-digital converters (adcs) can be implemented with an rc lattice structure to provide, e.g., a passive all-pass lattice filter. Additional poles created by decoupling capacitors can be used to provide a low-pass filtering effect in some embodiments.
Analog Devices Global

Piezoelectric thin film and piezoelectric thin film device

A piezoelectric thin film contains potassium sodium niobate represented by general formula (k1-xnax)nbo3 and catio3, wherein the lattice spacing calculated from the diffraction peak of the (001) plane in an x-ray diffraction profile of the piezoelectric thin film is 3.975 Å or less, and the ratio i101/i001 of the diffraction peak intensity i101 of the (101) plane to the diffraction peak intensity i001 of the (001) plane in the x-ray diffraction profile of the piezoelectric thin film 3 satisfies the relationship log10(i101/i001)≦−2.10.. .
Murata Manufacturing Co., Ltd.

Light emitting diode

A light emitting diode includes a gan substrate having a c-plane as a lamination surface; an n-type gan layer which is laminated on the gan substrate and which includes a first n-type gan layer, an n-type intermediate layer, and a second n-type gan layer; and an algan strain adjustment layer laminated on the n-type gan layer. Furthermore, the light emitting diode includes a light-emitting layer which is laminated on the algan strain adjustment layer and which has a multi-quantum well structure having well layers and barrier layers, which are made of ingan having a lattice constant in an a-axis direction larger than that of the algan strain adjustment layer; and a p-type algan cladding layer laminated on the light emitting layer..
Panasonic Intellectual Property Management Co., Ltd.

Optoelectronic detectors having a dilute nitride layer on a substrate with a lattice parameter nearly matching gaas

Optoelectronic detectors having one or more dilute nitride layers on substrates with lattice parameters matching or nearly matching gaas are described herein. A semiconductor can include a substrate with a lattice parameter matching or nearly matching gaas and a first doped iii-v layer over the substrate.
Iqe, Plc

Staircase avalanche photodiode with a staircase multiplication region composed of an alinassb alloy

A staircase avalanche photodiode with a staircase multiplication region composed of an alinassb alloy. The photodiode includes a buffer layer adjacent to a substrate and an avalanche multiplication region adjacent to the buffer layer, where the avalanche multiplication region includes a graded alinassb alloy grown lattice-matched or psuedomorphically strained on either inas or gasb.
University Of Virginia Patent Foundation

Strain compensation in transistors

An embodiment includes a device comprising: a first epitaxial layer, coupled to a substrate, having a first lattice constant; a second epitaxial layer, on the first layer, having a second lattice constant; a third epitaxial layer, contacting an upper surface of the second layer, having a third lattice constant unequal to the second lattice constant; and an epitaxial device layer, on the third layer, including a channel region; wherein (a) the first layer is relaxed and includes defects, (b) the second layer is compressive strained and the third layer is tensile strained, and (c) the first, second, third, and device layers are all included in a trench. Other embodiments are described herein..
Intel Corporation

Quantum well mosfet channels having lattice mismatch with metal source/drains, and conformal regrowth source/drains

Embodiments described include straining transistor quantum well (qw) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a mos channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well..
Intel Corporation

Interposer with lattice construction and embedded conductive metal structures

A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material.
International Business Machines Corporation

Lattice topics:
  • Semiconductor
  • Semiconductor Device
  • Semiconductor Material
  • Crystallin
  • Disconnect
  • Transistors
  • Replacement Gate
  • Semiconductor Devices
  • Dislocations
  • Dislocation
  • Image Processing
  • Coordinates
  • Surface Plasmon Polariton
  • Antenna Array

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    This listing is a sample listing of patent applications related to Lattice for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Lattice with additional patents listed. Browse our RSS directory or Search for other possible listings.


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