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Lattice patents


This page is updated frequently with new Lattice-related patent applications.

 Resonant cavity strained iii-v photodetector and led on silicon substrate patent thumbnailResonant cavity strained iii-v photodetector and led on silicon substrate
An optoelectronic device that includes a germanium containing buffer layer atop a silicon containing substrate, and a first distributed bragg reflector stack of iii-v semiconductor material layers on the buffer layer. The optoelectronic device further includes an active layer of iii-v semiconductor material present on the first distributed bragg reflector stack, wherein a difference in lattice dimension between the active layer and the first distributed brag reflector stack induces a strain in the active layer.
International Business Machines Corporation

 Semiconductor light-receiving device patent thumbnailSemiconductor light-receiving device
A semiconductor light-receiving device includes: a semi-insulating substrate; and a buffer layer, a p-type contact layer, a light absorption layer, a p-type field alleviating layer, an avalanche multiplication layer, an n-type field alleviating layer and an n-type contact layer laminated in order on the semi-insulating substrate, wherein the buffer layer includes a superlattice obtained by alternately laminating an inp layer and an alxgayin1-x-yas layer (0.16≦x≦0.48, 0≦y≦0.31) and does not absorb light of a wavelength band absorbed by the light absorption layer.. .
Mitsubishi Electric Corporation

 Breakdown resistant hemt substrate and device patent thumbnailBreakdown resistant hemt substrate and device
A compound semiconductor device structure having a main surface and a rear surface includes a silicon substrate including first and second substrate layers. The first substrate layer extends to the rear surface.
Infineon Technologies Austria Ag

 Strained group iv channels patent thumbnailStrained group iv channels
Disclosed herein is a semiconductor structure including: (i) a monocrystalline substrate having a top surface, (ii) a non-crystalline structure overlying the monocrystalline substrate and including an opening having a width smaller than 10 microns and exposing part of the top surface of the monocrystalline substrate. The semiconductor structure also includes (iii) a buffer structure having a bottom surface abutting the part and a top surface having less than 108 threading dislocations per cm2, the buffer structure being made of a material having a first lattice constant.
Imec Vzw

 Low temperature poly-silicon tft substrate structure and manufacture method thereof patent thumbnailLow temperature poly-silicon tft substrate structure and manufacture method thereof
The present invention provides a low temperature poly-silicon tft substrate structure and a manufacture method thereof. By providing the buffer layers in the drive tft area and the display tft area with different thicknesses, of which the thickness of the buffer layer in the drive tft area is larger, and the thickness of the buffer layer in the display tft area is smaller, different temperature grades are formed in the crystallization process of the polysilicon to achieve the control to the grain diameters of the crystals.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

 Nonvolatile semiconductor memory device patent thumbnailNonvolatile semiconductor memory device
According to one embodiment, a nonvolatile semiconductor memory device includes a first structure having a first insulating layer, a semiconductor layer, and a second insulating layer stacked in this order in a first direction, the first structure extending in a second direction, memory cells provided on a surface of the semiconductor layer facing in a third direction, and connected in series in the second direction, and a third insulating layer contacting at least one of first and second end portions of the first structure in the second direction and not covering at least a part of an area between the first and second end portions. A lattice spacing of semiconductor atoms in the semiconductor layer in the second direction is larger than a lattice spacing of the semiconductor atoms in the semiconductor layer in the first direction..
Kabushiki Kaisha Toshiba

 Interconnection structure patent thumbnailInterconnection structure
An interconnection structure fabrication method is provided. The method includes providing a substrate; forming a conductive film with a first thickness and having a first lattice structure and a first grain size, wherein the first thickness is greater than the first grain size; and performing an annealing process to change the first lattice structure of the conductive film to a second lattice structure and to change the first grain size to a second grain size.
Semiconductor Manufacturing International (shanghai) Corporation

 Semiconductor package patent thumbnailSemiconductor package
Provided is a semiconductor package including a substrate; at least one semiconductor chip mounted on the substrate; a molding element, which is arranged on the substrate and encapsulates the at least one semiconductor chip; and a lattice element, which is arranged inside the molding element, where the lattice element includes a body having a plurality of openings.. .
Samsung Electronics Co., Ltd.

 Laser processing method patent thumbnailLaser processing method
There is provided a laser processing method of laser-processing a wafer along a plurality of streets formed in a lattice manner on a top surface of the wafer, the wafer having devices formed in a plurality of regions partitioned by the streets, the laser processing method including: a wafer holding step of holding an undersurface of the wafer by a chuck table; a resin supplying step of supplying a water-soluble liquid resin to the top surface of the wafer; a protective film forming step of forming a protective film p on the wafer as a result of drying the water-soluble liquid resin by irradiating the water-soluble liquid resin with light from a xenon flash lamp; a laser irradiating step of irradiating the wafer with a laser beam through the protective film along the streets; and a cleaning step of cleaning the wafer after the laser irradiating step.. .
Disco Corporation

 Porous fin as compliant medium to form dislocation-free heteroepitaxial films patent thumbnailPorous fin as compliant medium to form dislocation-free heteroepitaxial films
A method for forming a heteroepitaxial layer includes forming an epitaxial grown layer on a monocrystalline substrate and patterning the epitaxial grown layer to form fins. The fins are converted to porous fins.
International Business Machines Corporation

Method for manufacturing a resin-impregnatable sheet-like spacer for a highvoltage component, a spacer manufactured according to the method, a highvoltage component comprising the spacer and an arrangement for performing the method

The method is provided for manufacturing a perforated sheet-like high-voltage insulating spacer for a high-voltage component, which component comprises a field grading condenser core with the spacer which is wound in spiral form around an axis, with electrically conducting layers which are inserted between successive windings of the spacer, and with a polymeric matrix which penetrates the spacer and which embeds the spacer and the layers. The method comprises at least steps as follows: an electrically insulating tape, and the patterned tape is expanded at right angle to the cutting lines in order to form a spacer with a perforated three-dimensional lattice structure.
Abb Schweiz Ag

Visual aggregation modeler performance analysis and optimization of databases

An aggregation lattice provides an effective visualization tool to integrate complex and multifaceted feedback required for aggregation modeling. The aggregation lattice provides a framework for reasoning about aggregates, qualifying workloads that benefit from them, and picking most effective levels from a total performance perspective.
Infokarta, Inc.

Touch sensor electrode, touch panel and display device

A touch sensor electrode includes first electrodes arrayed in a first direction on a first surface of a substrate and each extending along a second direction perpendicular to the first direction, and second electrodes arrayed in the second direction on a second surface of the substrate and each extending along the first direction. Each one of the first and second electrodes includes reference pattern elements, each having a main line and a sub-line and forming a pattern with reference to a reference direction, which is the first direction for the first electrodes and the second direction for the second electrodes, respectively.
Toppan Printing Co., Ltd.

Textile constructs formed with fusible filaments

A textile construct with a performance film formative built into a textile structure. The textile construct needs only to be subject to a fusing agent to cause the performance film formative to convert from its lattice structure (e.g., knit or woven structure) into a film that is built into a retained lattice structure of the textile.
The North Face Apparel Corp.

Carrier arrangement for storing and/or transporting and/or cleaning dishware or other items

Carrier arrangement (1) for storing and/or transporting and/or cleaning dishware or other items, wherein the carrier arrangement (1) has at least one carrier plate (2) with at least one lattice-shaped structure (3), wherein the lattice-shaped structure (3) is formed by lattice rods (5) which are arranged in a rectangular shape, in particular a square shape, and surround rectangular, in particular square, openings (4), and wherein the carrier arrangement (1) has at least one fastening base (6) which is fastenable or fastened with a clamping action on the lattice-shaped structure (3), wherein the fastening base (6) is fastenable or fastened with a clamping action in one of the rectangular, in particular square, openings (4).. .
Fries Planungs - Und Marketinggesellschaft M.b.h.

Light emitting diode and manufacturing the same

A light emitting diode and a method of manufacturing the light emitting diode are provided. The light emitting diode includes an n-type semiconductor layer, an inclined type superlattice thin film layer, an active layer, and a p-type semiconductor layer.
Industry Foundation Of Chonnam National University

Photoelectric conversion element

A photoelectric conversion element includes a superlattice semiconductor layer including barrier sub-layers and quantum sub-layers (quantum dot sub-layers) alternately stacked and also includes a wavelength conversion layer containing a wavelength conversion material converting the wavelength of incident light. The wavelength conversion layer converts incident light into light with a wavelength corresponding to an optical transition from a quantum level of the conduction band of the superlattice semiconductor layer to a continuum level of the conduction band..
The University Of Tokyo

Method of forming a finfet having an oxide region in the source/drain region

Embodiments of the present disclosure include a semiconductor device, a finfet device, and methods for forming the same. An embodiment is a semiconductor device including a first semiconductor fin extending above a substrate, the first semiconductor fin having a first lattice constant, an isolation region surrounding the first semiconductor fin, and a first source/drain region in the first semiconductor fin, the first source/drain having a second lattice constant different from the first lattice constant.
Taiwan Semiconductor Manufacturing Company, Ltd.

Methods and improving micro-led devices

A μled device comprising: a substrate and an epitaxial layer grown on the substrate and comprising a semiconductor material, wherein at least a portion of the substrate and the epitaxial layer define a mesa; an active layer within the mesa and configured, on application of an electrical current, to generate light for emission through a light emitting surface of the substrate opposite the mesa, wherein the crystal lattice structure of the substrate and the epitaxial layer is arranged such that a c-plane of the crystal lattice structure is misaligned with respect to the light emitting surface.. .
Oculus Vr, Llc

Multi-wafer based light absorption apparatus and applications thereof

Structures and techniques introduced here enable the design and fabrication of photodetectors (pds) and/or other electronic circuits using typical semiconductor device manufacturing technologies meanwhile reducing the adverse impacts on pds performance. Examples of the various structures and techniques introduced here include, but not limited to, a pre-pd homogeneous wafer bonding technique, a pre-pd heterogeneous wafer bonding technique, a post-pd wafer bonding technique, their combinations, and a number of mirror equipped pd structures.
Artilux Corporation

Semiconductor memory device and manufacturing the same

A semiconductor memory device according to an embodiment, includes a stacked body, first and second semiconductor pillars and a contact. The stacked body includes insulating films and electrode films stacked alternately along a first direction.
Kabushiki Kaisha Toshiba

Three dimensional woven lattices as novel multi-functional architectures

The present invention is directed to devices formed from three-dimensional (3d) structures composed of metallic, ceramic or polymeric wires or bundles and yarns of wires that are either solid or hollow like a tube. The devices of the present invention offer the potential for 3d structures with multiple properties optimized concurrently, in some cases using a topology optimization routine that includes the 3d manufacturing constraints.
The Johns Hopkins University

Three dimensional lattice weaves with tailored damping properties

The present invention is directed to three dimensional weaves composed of wires or yarns that offer the potential for damping not achievable with solid materials, including high temperature damping. Three damping mechanisms have been identified: (1) internal material damping, (2) frictional energy dissipation (coulomb damping), and (3) inertial damping (tuned mass damping).
The Johns Hopkins University

Diffuser part for a gas turbine

A diffuser component for a gas turbine is provided, where a fluid flow in the direction of a combustion chamber of the gas turbine can be slowed down by the diffuser component, and a flow cross-section of the diffuser component, which is defined by a diffuser wall is widened to do so. The diffuser wall is at least locally braced, in that at least one stiffening element with a lattice-type structure is provided on the diffuser wall..
Rolls-royce Deutschland Ltd & Co Kg

Increasing zinc sulfide hardness

The hardness of zinc sulfide is increased by adding selective elements within a specified range to the crystal lattice of the zinc sulfide. The increased hardness over conventional zinc sulfide does not substantially compromise the optical properties of the zinc sulfide.
Dow Global Technologies Llc

Graphene and hexagonal boron nitride planes and associated methods

Graphene layers made of primarily sp2 bonded atoms and associated methods are disclosed. In one aspect, for example, a method of forming a graphite film can include heating a solid substrate under vacuum to a solubilizing temperature that is less than a melting point of the solid substrate, solubilizing carbon atoms from a graphite source into the heated solid substrate, and cooling the heated solid substrate at a rate sufficient to form a graphite film from the solubilized carbon atoms on at least one surface of the solid substrate.

Fusion cage implant with lattice structure and grooves

Various exemplary embodiments relate to a spinal implant for insertion between two vertebrae, the spinal implant including: a cage including: a frame sized to be inserted between the two vertebrae; a lattice structure disposed at least partially within the frame and exposed on a first and second sides of the frame to permit bone growth into the lattice structure, wherein the first and second sides are on opposite sides of the frame; and grooves on the first and second side of the cage configured to interface with the two vertebrae, wherein the cage is formed of layers of trabeculite™ material fused together.. .
Rhausler, Inc.

Monolithic nanophotonic device on a semiconductor substrate

A photonic light generating device is provided on a portion of a first semiconductor material. The photonic light generating device includes a second semiconductor material that has a different lattice constant than the lattice constant of the first semiconductor material and that is capable of generating and emitting light.
International Business Machines Corporation

Composite quantum-dot materials for photonic detectors

A composite quantum-dot photodetector comprising a substrate with a colloidally deposited thin film structure forming a photosensitive region, the thin film containing at least one type of a nanocrystal quantum-dot, whereby the nanocrystal quantum dots are spaced by ligands to form a lattice, and the lattice of the quantum dots has an infill material that forms an inorganic matrix that isolates the nanocrystal quantum dots from atmospheric exposure.. .
Vadient Optics, Llc.

Fin structure of semiconductor device

The disclosure relates to a fin field effect transistor (finfet). An exemplary finfet comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising an upper portion comprising a first semiconductor material having a first lattice constant, wherein the upper portion comprises a first substantially vertical portion having a first width and a second substantially vertical portion having a second width less than the first width over the first substantially vertical portion; and a lower portion comprising a second semiconductor material having a second lattice constant less than the first lattice constant, wherein a top surface of the lower portion has a third width less than the first width; and a gate structure covering the second substantially vertical portion..
Taiwan Semiconductor Manufacturing Company, Ltd.

Horizontal gate all around device isolation

Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hgaa) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate.
Applied Materials, Inc.

Adaptive multi-stage disturbance rejection

Apparatus and method for controlling the position of a control object using a multi-stage actuator. In some embodiments, a multi-stage actuator is provided with first and second actuation stages adapted to position a control object.
Seagate Technology Llc

Lattice mast having an open framework structure in particular an electricity pylon or telecommunication mast, and increasing the stability of lattice masts having an open framework structure

The invention relates to a lattice mast (1) with an open framework structure of angled profiles (3), in particular an electricity pylon or telecommunications mast, comprising at least one or more cladding profiles (9a, 9b) which extend over at least part of the length of at least one angled profile (3), wherein at least one cladding profile has a curved incident-flow surface and forms a flow shielding of a wind-exposed edge of the angled profile (3), wherein the incident-flow surface is at least approximately spherically curved and has a flow resistance coefficient which is less than that of the unshielded angled profile (3).. .
Rwe Innogy Gmbh

Method for manufacturing three-dimensional lattice truss structure using flexible linear bodies

A method for manufacturing a three-dimensional lattice truss structure using flexible wires, including: arranging a plurality of out-of-plane wires; forming crossing portions between the plurality of out-of-plane wires; inserting a plurality of in-plane wires in the crossing portions; translating the plurality of in-plane wires in the z-direction; and inserting boundary rods in the y- or x-direction inside the plurality of out-of-plane wire groups.. .
Industry Foundation Of Chonnam National University

Engineered band gaps

An optoelectronic device as well as its methods of use and manufacture are disclosed. In one embodiment, an optoelectronic device includes first and second semiconducting atomically thin layers with corresponding first and second lattice directions.
Massachusetts Institute Of Technology

Dual mode iii-v superlattice avalanche photodiode

In one aspect, an avalanche photodiode, includes an absorber, a first superlattice structure directly connected to the absorber and configured to multiply holes and a second superlattice structure directly connected to the first superlattice structure and configured to multiply electrons. The first and second superlattice structures include iii-v semiconductor material.
Raytheon Company

Aspect ratio trapping (art) for fabricating vertical semiconductor devices

Aspect ratio trapping (art) approaches for fabricating vertical semiconductor devices and vertical semiconductor devices fabricated there from are described. For example, a semiconductor device includes a substrate with an uppermost surface having a first lattice constant.
Intel Corporation

Lattice structure interfacing

Methods, systems, and apparatus, including medium-encoded computer program products, for designing three dimensional lattice structures include, in one aspect, a method including: obtaining a lattice within a 3d lattice design space for a 3d model being created with a 3d modeling program; identifying junctions in the lattice that are potential sources of particle traps at an interface between the 3d lattice design space and a surface present in the 3d model; and removing the potential sources of particle traps by modifying cell space defined between the identified junctions and the surface. In addition, the surface can be a surface of a solid region defined in the 3d model, and the method can include: identifying beams in the lattice having junctions lying on the surface; and extending each of the identified beams by a length amount to cause overlap between the identified beams and the solid region..
Within Technologies Ltd.

System and assembling tower sections of a wind turbine lattice tower structure

In one aspect, a method for assembling a tower section of a lattice tower structure for a wind turbine on a tower assembly fixture may generally include installing a first trolley onto a first fixture arm of the fixture and installing a second trolley onto a second fixture arm of the fixture. In addition, the method may include securing a first support leg of the tower section to the first trolley, securing a second support leg of the tower section to the second trolley and coupling at least one secondary support member between the first and seconds support legs..
General Electric Company

Gas barrier film and producing it

The invention provides a gas barrier film with low deterioration in the gas barrier property before and after high-temperature hot water treatment. The gas barrier film has a gas barrier coating film, formed as a composite film comprising a network structure having a mesh structure with si—o—si bonds as the basic lattice and a water-soluble polymer crystallized as microcrystals, incorporated into the mesh of the network structure, wherein a barrier coating agent, obtained by mixing a condensate solution of an alkoxysilane hydrolysate prepared as a mixed solution in which the proportion of bonded states of the silicon atoms of the condensate with q1 and q2 structures is at least 60% of the total silicon atoms, with a crystalline water-soluble polymer, is coated on a base material film, either after forming or without forming an aluminum oxide vapor deposition film, to form a coating layer..
Dai Nippon Printing Co., Ltd.

Packing box, packing method and unpacking method

A packing box including lattice members which are arranged in a stacked state into stages, a stage-partition plate which is arranged between the stages of the lattice members, two or more inner tubular-trunk frames which are provided in a stacking direction of the lattice members to surround one or more stages of the lattice members, an outer tubular-trunk frame surrounding an outside of two or more stages of the inner tubular-trunk frames, a bottom lid which is arranged under the outer tubular-trunk frame, and a top lid which is arranged on the outer tubular-trunk frame.. .
Mitsubishi Materials Corporation

Tissue thickness compensator comprising resilient members

A tissue thickness compensator comprising at least one woven lattice can be positioned in the end effector of a surgical instrument. A fastener cartridge that is positioned in the end effector can comprise at least one cavity configured to receive a fastener.
Ethicon Endo-surgery, Llc

Hair bands with easy to change fashion accessories and storage and display cases

The present invention is directed to a hair band for keeping hair out of the face of the wearer, comprising a band having two surfaces, an inner surface that contacts the head and hair of an individual, which is formed to fit the head over the hair in a vertical orientation, and an outer surface that face away from the head, wherein the band has a multitude of magnets distributed along the length of the band, or wherein the band has an opening through the inner and outer surfaces that runs the majority of the length of the band. In one embodiment, the opening has a soft plastic or silicon strip inserted therein, wherein the strip has a series of openings or holes formed down its length or the opening has a lattice formed within the opening of the band, wherein the lattice is created by a series of crisscrossing strings or strands, and the holes formed by the lattice allow for one or more tabs to be inserted therein to allow fashion accessories that have tabs to be attached to the hair band.

Method of using a sacrifical gate structure to make a metal gate finfet transistor

A self-aligned sige finfet device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium.
Stmicroelectronics, Inc.

Semiconductor devices

Semiconductor devices include a channel layer on a substrate, the channel layer including a material having a lattice constant different from a lattice constant of the substrate, a first gate electrode on the channel layer, a first source region of a first conductivity type at a first side of the first gate electrode, a first body region of a second conductivity type under the first source region and contacting the first source region, a first drain region of the first conductivity type disposed at a second side of the first gate electrode, a first drift region of the first conductivity type under the first drain region and contacting the first drain region, and a first stud region in the channel layer and the first drift region. The first stud region has an impurity concentration higher than an impurity concentration of the first drift region..
Samsung Electronics Co., Ltd.

Ultrathin superlattice of mno/mn/mnn and other metal oxide/metal/metal nitride liners and caps for copper low dielectric constant interconnects

An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure.
International Business Machines Corporation

Method of forming fin structure of semiconductor device

A method of forming a fin structure of a semiconductor device, such as a fin field effect transistor (finfet) is provided. In an embodiment, trenches are formed in a substrate, and a liner is formed along sidewalls of the trenches, wherein a region between adjacent trenches define a fin.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor wafer, semiconductor device diced from semiconductor wafer, and manufacturing semiconductor device

A semiconductor wafer is provided with a substrate, a gan type semiconductor film which is laminated on the substrate, a plurality of element regions which are provided on the gan type semiconductor film, a dielectric film which is laminated on the gan type semiconductor film, and a dicing region which has a dicing groove which is provided in a lattice form without passing through the dielectric film described above so as to partition the element regions described above. Then, an end on the element region side of the dicing groove is higher or lower than a central portion of the dicing groove in a width direction in a bottom surface of the dicing groove..
Sharp Kabushiki Kaisha

Lattice topics:
  • Semiconductor
  • Semiconductor Device
  • Semiconductor Material
  • Crystallin
  • Disconnect
  • Transistors
  • Replacement Gate
  • Semiconductor Devices
  • Dislocations
  • Dislocation
  • Image Processing
  • Coordinates
  • Surface Plasmon Polariton
  • Antenna Array

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    This listing is a sample listing of patent applications related to Lattice for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Lattice with additional patents listed. Browse our RSS directory or Search for other possible listings.


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