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Lattice C patents



      
           
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Date/App# patent app List of recent Lattice C-related patents
04/17/14
20140103396
 Strain-inducing semiconductor regions patent thumbnailnew patent Strain-inducing semiconductor regions
A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate.
04/17/14
20140103293
 Group iii nitride semiconductor light-emitting element patent thumbnailnew patent Group iii nitride semiconductor light-emitting element
A group iii nitride semiconductor light-emitting element provided with: a semiconductor layer obtained by laminating a first semiconductor layer of a first conduction type, a light-emitting layer, and a second semiconductor layer of an opposite second conduction type; a first electrode connected to the first semiconductor layer; and a second electrode provided on the surface of the second semiconductor layer; the light-emitting layer including a first gallium indium nitride layer of a first indium composition, disposed on a side opposite the light extraction direction; a second gallium indium nitride layer of a second indium composition less than the first, disposed on the light extraction direction side from the first gallium indium nitride layer; and an intermediate layer containing a material of a smaller lattice constant than the materials constituting the first and second gallium indium nitride layers, provided between the first and second gallium indium nitride layers.. .
03/27/14
20140084340
 Contact structure of semiconductor device patent thumbnailContact structure of semiconductor device
The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ild) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; and a metal layer filling a coated opening of the dielectric layer..
03/27/14
20140084298
 Nitride compound semiconductor device and manufacturing method thereof patent thumbnailNitride compound semiconductor device and manufacturing method thereof
A nitride compound semiconductor device includes: a substrate; a buffer layer formed on the substrate and including a plurality of composite layers each layered of: a first layer formed of a nitride compound semiconductor; and a second layer formed of a nitride compound semiconductor containing aluminum and having a lattice constant smaller than a lattice constant of the first layer; a semiconductor operating layer formed on the buffer layer; and a plurality of electrodes formed on the semiconductor operating layer. At least one of the second layers has oxygen added therein..
03/20/14
20140080294
 Method for manufacturing a semiconductor structure patent thumbnailMethod for manufacturing a semiconductor structure
According to an embodiment, a method for manufacturing a semiconductor structure includes providing a first monocrystalline semiconductor portion having a first lattice constant in a reference direction and forming a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion.. .
03/06/14
20140065774
 Embedded planar source/drain stressors for a finfet including a plurality of fins patent thumbnailEmbedded planar source/drain stressors for a finfet including a plurality of fins
Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed.
03/06/14
20140064047
 Magnetic recording medium and magnetic recording and reproducing apparatus patent thumbnailMagnetic recording medium and magnetic recording and reproducing apparatus
A magnetic recording medium of the present invention includes an under layer formed on a substrate, and a magnetic layer, formed on the under layer, which contains an alloy having an l10-type crystal structure as a main component. The under layer includes, in order from the substrate side, a first under layer with a lattice constant a of 2.87 Å≦a<3.04 Å, a second under layer having a bcc structure with a lattice constant a of 3.04 Å≦a<3.18 Å, a third under layer having a bcc structure with a lattice constant a of 3.18 Å≦a<3.31 Å, and an upper under layer having a nacl-type crystal structure.
03/06/14
20140060631
 Compound semiconductor solar battery and method for manufacturing compound semiconductor solar battery patent thumbnailCompound semiconductor solar battery and method for manufacturing compound semiconductor solar battery
A compound semiconductor solar battery including a first compound semiconductor photoelectric conversion cell (40a), a second compound semiconductor photoelectric conversion cell (40b) provided on the first compound semiconductor photoelectric conversion cell (40a), and a compound semiconductor buffer layer (41) provided between the first compound semiconductor photoelectric conversion cell (40a) and the second compound semiconductor photoelectric conversion cell (40b), the first compound semiconductor photoelectric conversion cell (40a) and the compound semiconductor buffer layer (41) being provided adjacent to each other, and a ratio of a difference in lattice constant between the first compound semiconductor photoelectric conversion cell (40a) and a compound semiconductor layer (30) provided in a position closest to the first compound semiconductor photoelectric conversion cell (40a) among compound semiconductor layers constituting the compound semiconductor buffer layer (41) being not less than 0.15% and not more than 0.74%, and a method for manufacturing the same are provided.. .
02/27/14
20140056211
 Lattice coding scheme for two-way multi-relay wireless communications patent thumbnailLattice coding scheme for two-way multi-relay wireless communications
One embodiment comprises a method for a relay node. The method comprises receiving a first message combination comprising at least one encoded message from a first neighboring node and at least one encoded message from a second neighboring node.
02/20/14
20140051229
 Sub-10 nm graphene nanoribbon lattices patent thumbnailSub-10 nm graphene nanoribbon lattices
A graphene lattice comprising an ordered array of graphene nanoribbons is provided in which each graphene nanoribbon in the ordered array has a width that is less than 10 nm. The graphene lattice including the ordered array of graphene nanoribbons is formed by utilizing a layer of porous anodized alumina as a template which includes dense alumina portions and adjacent amorphous alumina portions.
02/20/14
20140048888
Strained structure of a semiconductor device
A semiconductor device comprises a substrate comprising a major surface; a p-type field effect transistor (pfet) comprising: a p-gate stack over the major surface, a p-strained region in the substrate adjacent to one side of the p-gate stack, wherein a lattice constant of the p-strained region is different from a lattice constant of the substrate, wherein the p-strained region has a first top surface higher than the major surface; and a p-silicide region on the p-strained region; and an n-type field effect transistor (nfet) comprising: an n-gate stack over the major surface, an n-strained region in the substrate adjacent to one side of the n-gate stack, wherein a lattice constant of the n-strained region is different from a lattice constant of the substrate, wherein the n-strained region has a second top surface lower than the major surface and a n-silicide region on the n-strained region.. .
02/20/14
20140048848
Layered semiconductor substrate and method for manufacturing it
A layered semiconductor substrate has a monocrystalline first layer based on silicon, having a first thickness and a first lattice constant a1 determined by a first dopant element and a first dopant concentration, and in direct contact therewith, a monocrystalline second layer based on silicon, having a second thickness and a second lattice constant a2, determined by a second dopant element and a second dopant concentration, and a monocrystalline third layer comprising a group iii nitride, the second layer located between the first layer and the third layer, wherein a2>a1, wherein the crystal lattice of the first layer and the second layer are lattice-matched, and wherein the bow of the layered semiconductor substrate is in the range from −50 μm to 50 μm.. .
02/20/14
20140048819
Semiconductor light-emitting device
According to one embodiment, a semiconductor light-emitting device includes: a first conductivity type first semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in a (0001) surface; a second conductivity type second semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in the (0001) surface; a light emitting layer provided between the first semiconductor layer and the second semiconductor layer, containing a nitride semiconductor crystal, and having an average lattice constant larger than the lattice constant of the first semiconductor layer; and a first stress application layer provided on a side opposite to the light emitting layer of the first semiconductor layer and applying a compressive stress to the first semiconductor layer.. .
02/20/14
20140048817
Light emitting device with improved extraction efficiency
In embodiments of the invention, a semiconductor structure comprising a iii-nitride light emitting layer disposed between an n-type region and a p-type region is grown on a substrate. The substrate is a non-iii-nitride material.
02/20/14
20140048770
Nitride semiconductor wafer, nitride semiconductor device, and method for growing nitride semiconductor crystal
According to one embodiment, a nitride semiconductor wafer includes a silicon substrate, a lower strain relaxation layer provided on the silicon substrate, an intermediate layer provided on the lower strain relaxation layer, an upper strain relaxation layer provided on the intermediate layer, and a functional layer provided on the upper strain relaxation layer. The intermediate layer includes a first lower layer, a first doped layer provided on the first lower layer, and a first upper layer provided on the first doped layer.
02/20/14
20140048764
Sub-10 nm graphene nanoribbon lattices
A graphene lattice comprising an ordered array of graphene nanoribbons is provided in which each graphene nanoribbon in the ordered array has a width that is less than 10 nm. The graphene lattice including the ordered array of graphene nanoribbons is formed by utilizing a layer of porous anodized alumina as a template which includes dense alumina portions and adjacent amorphous alumina portions.
02/13/14
20140045284
Semiconductor buffer structure, semiconductor device including the same, and method of manufacturing semiconductor device using semiconductor buffer structure
A method of manufacturing a semiconductor device includes forming a silicon substrate, forming a buffer layer on the silicon substrate, and forming a nitride semiconductor layer on the buffer layer. The buffer layer includes a first layer, a second layer, and a third layer.
02/13/14
20140042500
Contact structure of semiconductor device
The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; a ge-containing dielectric layer over the strained material; and a metal layer over the ge-containing dielectric layer..
02/13/14
20140042492
Semiconductor buffer structure, semiconductor device and method of manufacturing the semiconductor device using the semiconductor buffer structure
A semiconductor buffer structure may include a silicon substrate and a buffer layer that is formed on the silicon substrate. The buffer layer may include a first layer, a second layer formed on the first layer, and a third layer formed on the second layer.
02/06/14
20140037041
Spacer grid for nuclear fuel assembly for reducing high frequency vibration
Disclosed herein is a spacer grid for a nuclear fuel assembly which is formed from grid strips of an improved structure, thus reducing flow-induced high-frequency vibration. The spacer grid has dimples or grid springs for supporting fuel rods and is formed from a plurality of grid strips assembled in a lattice shape to form lattice cells.
02/06/14
20140037040
Spacer grid for nuclear fuel assembly for reducing flow-induced vibration
Disclosed herein is a spacer grid for a nuclear fuel assembly. The spacer grid has dimples for supporting fuel rods and is formed from grid strips which are assembled in a lattice shape to form lattice cells.
01/16/14
20140013695
Modular building panel
An improved modular building panel and system for building construction is disclosed. The improved modular building panel comprises a novel honeycomb or lattice core comprising multiple layers of corrugated, preferably metal, components mechanically connected by any means known in the art, but which may be chemical bonding.
01/09/14
20140007995
Cobalt-base alloy with high heat resistance and high strength and process for producing the same
A process for producing a co-base alloy which has a basic composition including, in terms of mass proportion, 0.1%-10% al, 3.0-45% w, and co as the remainder and has an intermetallic compound of the l12 type [co3 (al, w)] dispersed and precipitated therein. Part of the co may be replaced with ni, ir, fe, cr, re, or ru, while part of the al and w may be replaced with ni, ti, nb, zr, v, ta or hf.
12/26/13
20130346066
Joint decoding of words and tags for conversational understanding
Joint decoding of words and tags may be provided. Upon receiving an input from a user comprising a plurality of elements, the input may be decoded into a word lattice comprising a plurality of words.
12/26/13
20130344668
Strain-inducing semiconductor regions
A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate.
12/19/13
20130337333
Positive electrode active material for lithium ion battery, method of producing the same, electrode for lithium ion battery, and lithium ion battery
Provided is a positive electrode active material for lithium ion batteries, which is capable of realizing stability and safety at a high voltage, a high energy density, high load characteristics, and long-term cycle characteristics by controlling a crystal shape of limnpo4 particles having a crystal structure very suitable for li diffusion or controlling an average primary particle size, a production method thereof, an electrode for lithium ion batteries, and a lithium ion battery. The positive electrode active material for lithium ion batteries of the invention is a positive electrode active material for lithium ion batteries, which is formed from limnpo4.
12/19/13
20130334666
Plasma-assisted atomic layer epitaxy of cubic and hexagonal inn and its alloys with aln at low temperatures
Described herein is a method for growing indium nitride (inn) materials by growing hexagonal and/or cubic inn using a pulsed growth method at a temperature lower than 300° c. Also described is a material comprising inn in a face-centered cubic lattice crystalline structure having an nacl type phase..
12/19/13
20130334568
Multilayer substrate structure and method of manufacturing the same
A multilayer substrate structure comprises a substrate, a thermal matching layer formed on the substrate and a lattice matching layer above the thermal matching layer. The thermal matching layer includes at least one of molybdenum, molybdenum-copper, mullite, sapphire, graphite, aluminum-oxynitrides, silicon, silicon carbide, zinc oxides, and rare earth oxides.
12/19/13
20130334536
Single-crystal reo buffer on amorphous siox
A method of forming a layer of amorphous silicon oxide positioned between a layer of rare earth oxide and a silicon substrate. The method includes providing a crystalline silicon substrate and depositing a layer of rare earth metal on the silicon substrate in an oxygen deficient ambient at a temperature above approximately 500° c.
12/19/13
20130333611
Lattice matching layer for use in a multilayer substrate structure
A lattice matching layer for use in a multilayer substrate structure comprises a lattice matching layer. The lattice matching layer includes a first chemical element and a second chemical element.
12/12/13
20130328106
Semiconductor device and method for manufacturing semiconductor device
Provided are a nitride-based semiconductor element with reduced leak current, and a manufacturing method thereof. The semiconductor element comprises a substrate; a buffer region that is formed above the substrate; an active layer that is formed on the buffer region; and at least two electrodes that are formed on the active layer.
12/12/13
20130327384
Multi-junction solar cell and manufacturing method therefor
The present invention provides a multi-junction solar cell capable of increasing the degree of freedom of the selection of compound semiconductors. The multi-junction solar cell 1 includes a layered structure section 4 including compound semiconductor photovoltaic devices 2 and 3 matched in lattice constant with each other and joined to each other, and a nanopillar structure section 7 including a compound semiconductor photovoltaic device or a plurality of compound semiconductor photovoltaic devices 5 and 6 joined to each other..
12/05/13
20130323899
High performance cmos device design
A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate.
12/05/13
20130320446
Semiconductor structure and method for forming the same
A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a semiconductor substrate; a rare earth oxide layer formed on the semiconductor substrate; a channel region formed on the rare earth oxide layer; and a source region and a drain region formed at both sides of the channel region respectively, in which a relationship between a lattice constant a of the rare earth oxide layer and a lattice constant b of a semiconductor material of the channel region and/or the source region and the drain region is a=(n±c)b, where n is an integer, c is a mismatch ratio of lattice constants, and 0<c≦15%..
12/05/13
20130320413
Semiconductor structure and method for forming the same
A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a semiconductor substrate; a trench formed in the semiconductor substrate, in which a rare earth oxide layer is formed in the trench; a channel region partly or entirely formed on the rare earth oxide layer; and a source region and a drain region formed at both sides of the channel region, respectively.
12/05/13
20130320399
Embedded planar source/drain stressors for a finfet including a plurality of fins
Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed.
11/28/13
20130313686
Method for manufacturing semiconductor device, epitaxial substrate for use therein and semi-finished semiconductor device
A method for manufacturing a semiconductor device includes: (a) providing a base unit made of a material having a first lattice constant; (b) forming a first sacrificial layer made of a material having a second lattice constant on the base unit and a second sacrificial layer made of a material having a third lattice constant on the first sacrificial layer, the first lattice constant ranging between the second and third lattice constants so that two lattice stresses in opposite directions occur in the epitaxial substrate; (c) forming an epitaxial unit on the second sacrificial layer; (d) forming a permanent substrate on the epitaxial unit; and (e) removing the epitaxial unit.. .
11/21/13
20130307031
Semiconductor structure, semiconductor device having a semiconductor structure, and method for manufacturing a semiconductor structure
According to an embodiment, a semiconductor structure includes a first monocrystalline semiconductor portion having a first lattice constant in a reference direction; a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion; and a metal layer formed on and in contact with the second monocrystalline semiconductor portion.. .
11/21/13
20130307024
Semiconductor device and method for manufacturing semiconductor device
Provided is a semiconductor device that includes a substrate, a first buffer region formed over the substrate, a second buffer region formed on the first buffer region, an active layer formed on the second buffer region, and at least two electrodes formed on the active layer. The first buffer region includes at least one composite layer in which a first semiconductor layer and a second semiconductor layer are sequentially stacked.
11/21/13
20130307023
Semiconductor device and method for manufacturing semiconductor device
Provided is a semiconductor device that has a buffer layer with which a dislocation density is decreased. The semiconductor device includes a substrate, a buffer region formed over the substrate, an active layer formed on the buffer region, and at least two electrodes formed on the active layer.
11/21/13
20130306979
Semiconductor substrate and semiconductor device, and manufacturing method of semiconductor substrate
A gan-based semiconductor is epitaxially grown on a silicon substrate with a surface orientation of (111). The difference between the lattice constant of the gan and the silicon (111) surface is approximately 17%, which is quite large.
11/14/13
20130301668
6.1 angstrom iii-v and ii-vi semiconductor platform
Use of semiconductor materials having a lattice constant of within +/−1.6% of 6.1 angstroms facilitates improved semiconductor device performance and new semiconductor structures, for example integration of field-effect devices and optoelectronic devices on a single wafer. High-mobility channels are enabled, improving device performance..
11/14/13
20130300421
System for detecting underwater geological formations in particular for the localization of hydrocarbon formulations
The present invention relates to a system (100) for detecting underwater geological formations, in particular for the localization of reservoirs of hydrocarbons such as oil and/or natural gas, comprising an electromagnetic transmission device (10) which can be moved within an area to be surveyed (101) through sea surface tow means (14) along an advance direction (a) and at least one electromagnetic reception device (20) positioned in the area to be surveyed (101) and characterized in that the electromagnetic reception device (20) comprises at least one flat structure (20a) consisting of a plurality of linear elements (21) constrained to each other according to a bidimensional lattice configuration and a plurality of reception electrodes (22, 22a), wherein each reception electrode (22, 22a), of the plurality of reception electrodes (22, 22a) is constrained in correspondence with an intersection between pairs of said linear elements (21).. .
11/14/13
20130299236
Joining method, joint structure, electronic device, method for manufacturing electronic device and electronic part
A method of joining a first metal member having at least a surface made of a first metal to a second metal member having at least a surface made of a second metal with a joining material sandwiched therebetween. The joining material includes a low melting point metal having a lower melting point than the first metal and/or the second metal.
11/07/13
20130295741
Semiconductor device and method for manufacturing semiconductor device
A semiconductor device including a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate..
11/07/13
20130292697
Gallium nitride based light emitting diode and fabrication method thereof
A light emitting diode (led) and a method for fabricating the same, capable of improving brightness by forming a ingan layer having a low concentration of indium, and whose lattice constant is similar to that of an active layer of the led, is provided. The led includes: a buffer layer disposed on a sapphire substrate; a gan layer disposed on the buffer layer; a doped gan layer disposed on the gan layer; a gan layer having indium disposed on the gan layer; an active layer disposed on the gan layer having indium; and a p-type gan disposed on the active layer.
10/31/13
20130288447
Vertical polysilicon-germanium heterojunction bipolar transistor
A vertical heterojunction bipolar transistor (hbt) includes doped polysilicon having a doping of a first conductivity type as a wide-gap-emitter with an energy bandgap of about 1.12 ev and doped single crystalline ge having a doping of the second conductivity type as the base having the energy bandgap of about 0.66 ev. Doped single crystalline ge having of doping of the first conductivity type is employed as the collector.
10/31/13
20130285020
Compressive (pfet) and tensile (nfet) channel strain in nanowire fets fabricated with a replacement gate process
A method of fabricating a fet device is provided which includes the following steps. Nanowires/pads are formed in a soi layer over a box layer, wherein the nanowires are suspended over the box.
10/24/13
20130280466
Large diameter, high quality sic single crystals, method and apparatus
A method and system of forming large-diameter sic single crystals suitable for fabricating high crystal quality sic substrates of 100, 125, 150 and 200 mm in diameter are described. The sic single crystals are grown by a seeded sublimation technique in the presence of a shallow radial temperature gradient.
10/24/13
20130277713
As/sb compound semiconductors grown on si or ge substrate
An as(arsenic)/sb(antimony) compound semiconductor is grown on a si(silicon) or ge (germanium) substrate. With the present invention, island-like growth on the si or ge substrate owing to lattice constant mismatch is prevented.
10/17/13
20130269760
Photovoltaic junction for a solar cell
A photovoltaic junction for a solar cell is provided. The photovoltaic junction has an intrinsic region comprising a multiple quantum well stack formed from a series of quantum wells separated by barriers, in which the tensile stress in some of the quantum wells is partly or completely balanced by compressive stress in the others of the quantum wells.
10/10/13
20130267078
Processes for preparing stressed semiconductor wafers and for preparing devices including the stressed semiconductor wafers
Processes for preparing a stressed semiconductor wafer and processes for preparing devices including a stressed semiconductor wafer are provided herein. An exemplary process for preparing a stressed semiconductor wafer includes providing a semiconductor wafer of a first material having a first crystalline lattice constant.
10/10/13
20130264578
N-polar iii-nitride transistors
An n-polar iii-n transistor includes a iii-n buffer layer, a first iii-n barrier layer, and a iii-n channel layer, the iii-n channel layer having a gate region and a plurality of access regions on opposite sides of the gate region. The compositional difference between the first iii-n barrier layer and the iii-n channel layer causes a conductive channel to be induced in the access regions of the iii-n channel layer.
10/03/13
20130259080
Anisotropic strain control in semipolar nitride quantum wells by partially or fully relaxed aluminum indium gallium nitride layers with misfit dislocations
An epitaxial structure for a iii-nitride based optical device, comprising an active layer with anisotropic strain on an underlying layer, where a lattice constant and strain in the underlying layer are partially or fully relaxed in at least one direction due to a presence of misfit dislocations, so that the anisotropic strain in the active layer is modulated by the underlying layer.. .
10/03/13
20130258548
Ceramic powder and multi-layer ceramic capacitor
A ceramic powder that contains, as a main composition, barium titanate powder having a perovskite structure with an average particle size (median size) of 200 nm or smaller as measured by sem observation, wherein the the barium titanate powder is such that the percentage of barium titanate particle having twin defects in the barium titanate powder is less than 10% as measured by tem observation and that its crystal lattice c/a is 1.0075 or more. The ceramic powder is particularly useful in the formation of thin dielectric layers of 1 μm or less and can be used to manufacture mlccs having both desired capacity and longevity traits..
10/03/13
20130258547
Ceramic powder and multi-layer ceramic capacitor
A ceramic powder that contains, as a main composition, barium titanate powder having a perovskite structure with an average particle size (median size) of 200 nm or smaller as measured by sem observation, wherein the barium titanate powder is such that the percentage of barium titanate particles having twin defects in the barium titanate powder is 13% or more as measured by tem observation and that its crystal lattice c/a is 1.0080 or more. The ceramic powder has a wide range of optimum sintering temperatures and thus offers excellent productivity and is particularly useful in the formation of thin dielectric layers of 1 μm or less..
09/26/13
20130251375
Receiver, transmitter and communication system
According to one embodiment, a receiver includes an image sensor, a synchronization controller, and a data generator. The image sensor detects a visible ray having a lattice-shaped emission pattern.
09/26/13
20130248927
Contact structure of semiconductor device
A contact structure for a semiconductor device includes a substrate comprising a major surface and a cavity. A bottom surface of the cavity is lower than the major surface.
09/19/13
20130244364
Method of forming a composite substrate
In a method according to embodiments of the invention, a iii-nitride layer is grown on a growth substrate. The iii-nitride layer is connected to a host substrate.
09/19/13
20130244114
Lithium titanate particles and process for producing the lithium titante particles, mg-containing lithium titanate particles and process for producing the mg-containing lithium particles, negative electrode active substance particles for non-aqueous electrolyte secondary batteries, and non-aqeous electrolyte secondary battery
According to the present invention, there are provided lithium titanate particles which exhibit an excellent initial discharge capacity and an enhanced high-efficiency discharge capacity retention rate as an active substance for non-aqueous electrolyte secondary batteries and a process for producing the lithium titanate particles, and mg-containing lithium titanate particles. The present invention relates to lithium titanate particles with a spinel structure comprising tio2 in an amount of not more than 1.5%, li2tio3 in an amount of not less than 1% and not more than 6%, and li4ti5o12 in an amount of not less than 94% and not more than 99% as determined according to rietveld analysis when indexed with fd-3m by xrd, and having a specific surface area of 7 to 15 m2/g as measured by bet method, a process for producing lithium titanate particles comprising the steps of adding and mixing a water-soluble lithium solution into a water suspension of an oxide of titanium having a bet specific surface area of 40 to 400 m2/g and a primary particle diameter of 5 to 50 nm and subjecting the resulting mixed suspension to aging reaction at a temperature of 50 to 100° c.; subjecting the resulting reaction product to filtration, drying and pulverization; and subjecting the obtained dry particles to heat-calcination treatment at a temperature of 550 to 800° c., and mg-containing lithium titanate particles having a composition represented by the formula: lixmgytizo4 wherein x, z>0; 0.01≦y≦0.20; 0.01≦y/z≦0.10; and 0.5≦(x+y)/z≦1.0, the mg-containing lithium titanate particles having a bet specific surface area of 5 to 50 m2/g, a spinel single phase as a crystal structure, and a lattice constant (a) represented by a value of 0.050y+8.3595<a≦0.080y+8.3595 (Å)..
09/19/13
20130240950
Semiconductor device having tipless epitaxial source/drain regions
A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate.
09/19/13
20130240936
Light-emitting diode and light-emitting diode lamp
The present invention relates to a light-emitting diode which has an emission wavelength of 655 nm or more, excellent monochromatic properties, high output, high luminance, high efficiency and fast response time, has such a characteristic that the intensity of light emitted from a light extraction surface and traveling in a direction perpendicular to the light extraction surface has high directivity, and can release heat to the outside with high efficiency; and a light-emitting diode lamp. The light-emitting diode includes a compound semiconductor layer (11) which includes at least a pn-junction-type light-emitting section (3) and a strain adjustment layer (13) laminated on the light-emitting section (3); wherein the light-emitting section (3) has a laminated structure composed of a strained light-emitting layer having a composition formula (alxga1-x)yin1-yp (0≦x≦0.1, 0.37≦y≦0.46) and a barrier layer, wherein the strain adjustment layer (13) can be penetrated by light from the light-emitting section (3) and has a smaller lattice constant than those of the strained light-emitting layer and the barrier layer; and wherein a functional substrate (5) is bonded to a surface (11b) of the compound semiconductor layer (11) which is located on the opposite side with respect to the light extraction surface (11a) through a reflective structure (4)..
09/19/13
20130240902
Semiconductor arrangement
A first semiconductor zone of a first conduction type is formed from a semiconductor base material doped with first and second dopants. The first and second dopants are different substances and also different from the semiconductor base material.
09/12/13
20130235863
Apparatus and method of managing peripheral wireless lan radio signal for positioning service
The present disclosure relates to providing a positioning service by managing a plurality of peripheral wireless lan signals. The positioning service system collects peripheral wireless lan radio signals by scanning peripheral access points (aps), stores ap information of each of peripheral wireless lan radio signals in each lattice cell of a database.
09/12/13
20130234204
Fin field effect transistors including multiple lattice constants and methods of fabricating the same
A field effect transistor (fet) structure may include a fin on a substrate having a first lattice constant and at least two different lattice constant layers on respective different axially oriented surfaces of the fin, wherein the at least two different lattice constant layers each comprise lattice constants that are different than the first lattice constant and each other.. .
09/12/13
20130234106
Semiconductor light-emitting device
According to one embodiment, a semiconductor light-emitting device includes: a first conductivity type first semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in a (0001) surface; a second conductivity type second semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in the (0001) surface; a light emitting layer provided between the first semiconductor layer and the second semiconductor layer, containing a nitride semiconductor crystal, and having an average lattice constant larger than the lattice constant of the first semiconductor layer; and a first stress application layer provided on a side opposite to the light emitting layer of the first semiconductor layer and applying a compressive stress to the first semiconductor layer.. .
09/12/13
20130233618
Conductive material, bonding method using the same, and bonded structure
A conductive material that includes a metal component consisting of a first metal and a second metal having a melting point higher than that of the first metal, wherein the first metal is sn or an alloy containing 70% by weight or more of sn, and the second metal is a metal or alloy which forms an intermetallic compound having a melting point of 310° c. Or higher with the first metal and has a lattice constant difference of 50% or greater between itself and the intermetallic compound generated at the circumference of the second metal..
09/12/13
20130233238
Methods and mask structures for substantially defect-free epitaxial growth
Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, the method may comprise providing a substrate comprising a first crystalline material, where the first crystalline material has a first lattice constant; providing a mask structure on the substrate, where the mask structure comprises a first level comprising a first opening extending through the first level (where a bottom of the first opening comprises the substrate), and a second level on top of the first level, where the second level comprises a plurality of second trenches positioned at a non-zero angle with respect to the first opening.
09/05/13
20130228743
Light emitting diode
A light emitting diode including a substrate, a p-type and n-type semiconductor layers, an active layer, an interlayer, an electron barrier layer, a first and a second electrodes are provided. The active layer is located between the n-type and p-type semiconductor layers, and includes multiple quantum barrier layers and quantum wells located between any two quantum barrier layers.
08/29/13
20130224858
Adipose-derived stem cells and lattices
The present invention provides adipose-derived stem cells and lattices. In one aspect, the present invention provides a lipo-derived stem cell substantially free of adipocytes and red blood cells and clonal populations of connective tissue stem cells.
08/29/13
20130221461
Ferromagnetic tunnel junction structure and magnetoresistive effect device and spintronics device utilizing same
A ferromagnetic tunnel junction structure comprising a first ferromagnetic layer, a second ferromagnetic layer, and a tunnel barrier layer that is interposed between the first ferromagnetic layer and the second ferromagnetic layer, wherein the tunnel barrier layer includes a crystalline non-magnetic material having constituent elements that are similar to those of an crystalline oxide that has spinel structure as a stable phase structure; the non-magnetic material has a cubic structure having a symmetry of space group fm-3m or f-43m in which atomic arrangement in the spinel structure is disordered; and an effective lattice constant of the cubic structure is substantially half of the lattice constant of the oxide of the spinel structure.. .
08/29/13
20130221326
High bandgap iii-v alloys for high efficiency optoelectronics
High bandgap alloys for high efficiency optoelectronics are disclosed. An exemplary optoelectronic device may include a substrate, at least one al1-xinxp layer, and a step-grade buffer between the substrate and at least one al1-xinxp layer.


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Lattice C topics: Semiconductor, Crystallin, Dislocations, Dislocation, Barium Titanate, Perovskite, Gallium Nitride, Semiconductor Material, Replacement Gate, Bipolar Transistor, Electronic Device, Semiconductors, Semiconductor Device, Buffer Layer, Transistors

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