|| List of recent Jitter-related patents
|Enhancing jitter buffer performance through radio level feedback|
A jitter buffer in a voice over lte receiver may be influenced by radio level feedback (rlf) from both local and remote endpoints to preemptively adjust the jitter buffer delay in anticipation of predicted future losses that have a high probability of occurring. The radio events of the rlf and the scenarios that trigger the preemptive adjustments may be identified, and their use may be expressed in terms of mathematical formulas.
|Method and apparatus for processing a video signal|
Method, apparatus and computer program product for processing a video signal, the video signal comprising a plurality of frames, wherein the frames of the video signal are received at a jitter buffer, and the frames are output from the jitter buffer at a variable output rate to account for jitter in the received frames. Variations in the output rate are controlled in dependence upon the visual information content of the video signal, the visual information content of the video signal being the portion of the video signal that is to be displayed when the video signal is played out..
|Audio playback method, apparatus and system|
An audio playback method is provided. The method includes identifying a captured audio data frame according to a type of the audio data frame and sending the identified audio data frame to an audio receiving end.
|Adaptive motion instability detection in video|
Output video frames, which may be stabilized or non-stabilized, may then be stored to a memory. In certain embodiments, video motion instability is scored based on a probability distribution of video frame motion jitter values..
|Allocation of shared resources for virtualized networking|
Technology for allocating network adapter resources such as air interface time and queue space amongst multiple virtual network stations or other virtual adapters is disclosed. As one example, the resource allocation may be based on analysis of the relative latency, jitter, or bandwidth considerations for applications communicating via each of the multiple virtual adapters.
|Communication method and communication apparatus|
The present disclosure provides an orthogonal codes based code division multiplexing method of performing the code division multiplexing of demodulation reference signals in multiple layers of resource blocks by using orthogonal matrices, the method comprising: changing the order of chips in particular rows of a first orthogonal matrix to obtain a second orthogonal matrix with the changed order of chips; and multiplying the chips in respective rows of the second orthogonal matrix by the demodulation reference signals in corresponding layers of resource blocks correspondingly in the time direction to obtain code division multiplexing signals. The technical scheme of the present disclosure can improve the power jitter situation of downlink signals on the time, thereby the usage efficiency of the power amplifier at the base station side can be improved..
|System and method for suppressing jitter in digital data signals including image, video and audio data signals|
A system and method for suppressing jitter in a digital data signal in a signal processor system. The digital data signal has spaced apart byte allocation units wherein such spacing is increased such that unallocated bytes can be identified and removed from the digital data signal.
|Method and apparatus for source-synchronous signaling|
A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (milo) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the milo clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals..
|Serial communication control circuit|
In a serial communication control circuit, serial data transmitted from a transmission processing unit is switched to data generated in a mark ratio improvement data generation unit depending on a switch signal from the transmission processing unit, and is transmitted. Thereby, mark ratio improvement data is inserted in a transmission signal to improve a mark ratio during communication, thereby preventing reception signal's jitters from increasing..
|System, device, and method of voice-over-ip communication|
The present invention includes devices, systems, and methods of voice-over-internet protocol (voip) communication. For example, a method includes: receiving a data stream comprising a set of voip packets; and modifying a real time protocol (rtp) header of at least one of said voip packets to modify a jitter buffer delay of said data stream.
|Optical scanning device, method for manufacturing the optical scanning device, and image forming apparatus|
An optical scanning device includes a deflector configured to deflect a plurality of light beams emitted from a plurality of light emitters that are mutually spaced apart in a sub-scanning direction; an incident optical system configured to steer the plurality of light beams so as to be incident on the deflector; an imaging optical system configured to steer the plurality of light beams so as to be obliquely incident on a surface to be scanned and to form images of the plurality of light emitters on the surface to be scanned; and a correction unit configured to correct a jitter of at least one of the plurality of light beams in a main scanning direction on the basis of irradiation position information, in the sub-scanning direction, of at least one light beam among the plurality of light beams at a point corresponding to the surface to be scanned.. .
|Using clock drift, clock slew, and network latency to enhance machine identification|
Methods and systems for authenticating a user device employ a database of global network latencies categorized and searchable by location and calendar date-time of day usage, providing network latency by geography and by time. The database is constructed using voluminous daily data collected from a world-wide clientele of users who sign in to a particular website.
|Implementing data frequency and data bits per sector (bps) calibration for non-circular disk tracks|
A method, apparatus and a data storage device are provided for implementing data frequency and data bits per sector (bps) calibration for data written on a recordable surface including non-circular disk tracks of a storage device. A sector based bps profile is created for data sectors on the recordable surface.
|Power supply induced signal jitter compensation|
Examples of circuits and methods for compensating for power supply induced signal jitter in path elements sensitive to power supply variation. An example includes a signal path coupling an input to an output, the signal path including a delay element having a first delay and a bias-controlled delay element having a second delay.
|Method and apparatus for smoothing jitter generated by byte stuffing|
Systems and methods for smoothing jitter generated by byte stuffing. A frequency synthesizer comprises a smoothing logic coupled with a pll.
|Distributed phase-correction circuit|
A distributed phase-correction circuit is described. This distributed phase-correction circuit reduces jitter in a delay line by averaging edge delay through local feedback of signals internal to the delay line.
|Femto cell access point passthrough model|
Fixed, differentiated quality of service (qos) is supplied for packetized traffic (e.g., voice and data) intended for femto cell coverage when transmitted concurrently with external broadband traffic. Quality of service differentiation is supplied without an external implementation.
|Continuous phase adjustment based on injection locking|
A phase-modification circuit is described. This phase-modification circuit reduces jitter by injecting a divided reference clock in a phase-locked loop from an auxiliary oscillator and by effectively gradually and completely transferring its phase to a master oscillator.
|Method of managing a jitter buffer, and jitter buffer using same|
The present invention relates to a method of managing a jitter buffer and a jitter buffer using same. The method of managing a jitter buffer includes the steps of: receiving audio information frames; and adjusting a jitter buffer on the basis of the received audio information frames, wherein the adjusting step of the jitter buffer includes compensation of an audio signal, and the compensation of the audio signal can be performed for each sub frame of the audio information frames..
|Rate-controlled optical burst switching|
The invention provides a method and network communication equipment for low latency loss-free burst switching. Burst-transfer schedules are determined by controllers of bufferless core nodes according to specified bitrate allocations and distributed to respective edge nodes.
|High resolution current pulse analog measurement|
A measurement system includes a current source that is arranged to generate a current pulse to charge a capacitor as a function of an input clock signal. The accumulated charge on the capacitor is converted to a sample (e.g., resultant digital value) by an adc (analog-to-digital converter).
|Switching power supply device|
The invention provides a switching power supply device such that the occurrence of noise is reduced by jitter control of a switching frequency. The switching power supply device includes a switching power supply device main body wherein a predetermined output direct current voltage is obtained by switching an input alternating current voltage using a switching element, a switching control unit that controls the switching frequency in accordance with a feedback voltage that indicates the difference between an output set voltage and the output direct current voltage, a jitter control unit that applies jitter to the switching frequency, and a jitter amplitude control unit that changes jitter amplitude caused by the jitter control unit in accordance with the feedback voltage..
|Portable device and method for providing non-contact interface|
A method for controlling operations of a portable device through a touch-free user input in the portable device having a projector module is provided. To this end, once the projector module is driven, an application execution screen is projected through the projector module, and if a proximity event is detected, a camera module is activated to acquire an image from which a user gesture is recognized.
|Systems and methods for determining and displaying multi-line foreign language translations in real time on mobile devices|
The present invention is related to systems and methods for translating language text on a mobile camera device offline without access to the internet. More specifically, the present invention relates to systems and methods for displaying text of a first language and a translation of the first language text into a second language text which is displayed in real time in augmented reality on the mobile device.
|Method & circuit for parasitic capacitance cancellation for self capacitance sensing|
Apparatus and methods to measure capacitance changes for a touch-sensitive capacitive matrix are described. Charge-removal circuits and measurement techniques may be employed to cancel deleterious effects of parasitic capacitances in the touch-sensitive capacitive matrix.
|Syncless unit interval variation tolerant pwm receiver circuit, system and method|
A pwm receiver circuit receives and demodulates pulse width modulated (pwm) data signals without requiring synchronization such that no synchronization preamble need be provided with the pwm data signal. Embodiments may consume less power since there is no need to repeatedly synchronize a pll, counter or other circuitry to the pwm data signal.
|V+hu 2 +l power converter control with capacitor current ramp compensation|
Operation of a switching power converter having an output capacitor having a small equivalent series resistance (esr) is stabilized and jitter reduced by sensing capacitor current with gain and combining the resulting signal with the output voltage signal to provide a feedback signal to control switching of the power converter. Capacitor current can be sensed without interfering with operation of the filter capacitor by providing a branch circuit having a time constant matched to the output or filter capacitor but an arbitrarily high impedance so as to be effectively lossless.
|Methods for dynamically adaptive bit-leveling by incremental sampling, jitter detection, and exception handling|
A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device.
|Dynamically adaptive bit-leveling for data interfaces|
A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device.
|Jitter buffering system and method of jitter buffering|
A jitter buffering system and a method of jitter buffering. The jitter buffering system may be embodied in a quality of service (qos) management server, including: (1) a network interface controller (nic) configured to receive one-way-delay statistics regarding a video stream transmitted to a client, and (2) a processer configured to employ the one-way-delay statistics to calculate and recognize jitter and subsequently generate a command for the client to enable jitter buffering..
|Method and related network element providing delay measurement in an optical transport network|
A delay measurement method of a path (p) or path segment through a transport network and a corresponding network nodes (ne1, ne2) for performing the delay measurement are described, which provide a higher precision and lower jitter. An originating network node (ne1) inserts a delay measurement request signal (req) into an overhead subfield of a first data unit and transmits the first data unit over the path (p) or path segment to a far-end network node (ne2) as part of framed transport signals.
|Image synchronization of scanning wafer inspection system|
An inspection system comprises a beam generator module for deflecting spots across scan portions of a specimen. The system also includes detection channels for sensing light emanating from a specimen in response to an incident beam directed towards such specimen and generating a detected image for each scan portion.
|Receiver circuit, semiconductor integrated circuit, and test method|
A receiver circuit includes a cdr circuit, a jitter generator unit, a test pattern generator unit, and a comparator unit. The jitter generator unit generates jitter having first characteristics (frequency and amplitude).
|Injection locking of gain switched diodes for spectral narrowing and jitter stabilization|
Pulse power can be stabilized by applying spectrally narrow pulses to a laser diode during gain switching. An injection locking laser with a narrow emission bandwidth is tuned to a gain bandwidth of a laser diode to be gain switched.
|Low-power and all-digital phase interpolator-based clock and data recovery architecture|
The proposed invention is about an improved method for serial-in and serial-out transceiver applications. The proposed system includes a dual loop phase locked loop (pll) architecture having a pll and a phase rotator (pr)-based delay locked loop (dll).
|Timestamp estimation and jitter correction using downstream fifo occupancy|
First, a packet may be received and a timestamp value may be placed on the packet. The timestamp value may comprise a place time value comprising a time when the timestamp was placed on the packet plus a delay time value comprising an estimated time delay between when the timestamp was placed on the packet and when the packet leaves a port exit.
|System and method for jitter mitigation in time division multiple access (tdma) communications systems|
A tdma jitter buffer includes a receiver, a processor and a comparator. The receiver can receive a data transmission signal via a channel of a communications system, and can receive one or more delay factors measured at a transmission end of the channel, wherein each delay factor is associated with a respective data packet.
|Synchronous semiconductor memory device having dual delay locked loop circuit and method of managing dual delay locked loop circuit|
A synchronous semiconductor memory device includes a first delay locked loop circuit and a second delay locked loop circuit. The first delay locked loop circuit has a first delay line and generates a first clock hat is delay-synchronized with a clock applied as a signal for a data output timing control.
|Cascaded camera motion estimation, rolling shutter detection, and camera shake detection for video stabilization|
An easy-to-use online video stabilization system and methods for its use are described. Videos are stabilized after capture, and therefore the stabilization works on all forms of video footage including both legacy video and freshly captured video.
|Tilting to scroll|
In one embodiment, a method includes sending information to display an image on a screen. A scroll range for the image may be determined based on dimensions of the image.
|Frequency synthesis with gapper|
Systems and methods for frequency synthesis using a gapper. A frequency synthesizer may comprise a gapper, a first integer divider and a phase locked loop (pll).
|Phase interpolator based output waveform synthesizer for low-power broadband transmitter|
Exemplary embodiments of the present invention relate to an output waveform synthesizer using phase interpolators and an on-chip eye opening monitoring (eom) circuit for a low-power transmitter. In order to achieve both small area and low-power consumption in the transmitter design, a single-stage multiphase multiplexer operating in subrate is employed.
|Ring electrode device and method for generating high-pressure pulses|
A method, system, and electrode assembly are disclosed that maximizes the lifetime of electrodes for high energy electrical discharges in water by arranging the electrodes in concentric rings or a stack of concentric rings. The radii and the thickness of the ring electrodes are optimized for electrical reliability, low jitter, and minimal erosion.
|Method and device for reporting cell status|
Determining a distribution delay of a bearer by using a preset delay distribution algorithm according to a preset time period for reporting a cell status; starting a periodic timer of the bearer after the distribution delay elapses, where the periodic timer uses the time period as a period; determining, according to the periodic timer, whether the cell status needs to be reported; and carrying information of the cell status in an uplink data packet of the bearer if the cell status needs to be reported. Thereby avoiding greatly centralized reporting of the cell status and centralized policy adjustment that is performed for the bearers, so that great jitter of service traffic borne on a cell is controlled effectively..
|Transmit reference signal cleanup within a synchronous network application|
A network processor is described that includes a network reference clock processor module for providing an at least substantially low-jitter, low-wander reference signal. In one or more embodiments, the network reference clock processor module includes a digital phase locked loop configured to at least substantially attenuate a wander noise portion from a reference signal.
|Phase locked loop frequency synthesizer with reduced jitter|
A phase locked loop frequency synthesizer has a controlled oscillator for generating an output signal at a desired frequency, a phase/frequency detector module for comparing a feedback signal derived from the controlled oscillator with a reference signal to generate an error signal, a loop filter for processing said at least one error signal from said phase/frequency detector module to generate a combined control signal for the controlled oscillator. The gain of the phase/frequency detector module can be adjusted, preferably by varying the pulse width and pulse cycle, to maintain the overall gain of the phase locked loop within a given range and thereby maximize signal to noise ratio..
|Comprehensive multipath routing for congestion and quality-of-service in communication networks|
A packet routing method includes computing, for each source node in the data network and each destination node in the data network, a set of multiple routes providing a full range of performance from the source node to the destination node. The multiple routes are preferably precomputed and stored.
|Methods and systems for stabilizing live video in the presence of long-term image drift|
Methods and systems stabilization of a camera image for short term or ‘pole shake’ and longer term ‘pole drift’ are provided. The camera is attached to a fixed structure.
|Semiconductor integrated circuit|
In a system in which the phases of a data clock signal and a data signal differ between at an input and at an output, a semiconductor integrated circuit performs a simple ber test without using external equipment and, at the same time, performs a jitter evaluation required for a margin evaluation.. .
|Output current compensation for jitter in input voltage for dimmable led lamps|
An led controller reduces jitter of an led lamp. In one embodiment, the led controller includes a jitter detection circuit adapted to determine an amount of jitter in an input voltage signal.
|Handling method and device for cell concatenation|
A handling method for cell concatenation, includes receiving a cell of a packet before a concatenation timeout period expires and before the total number of received cells of the packet reaches a concatenation number. The method further includes determining whether an end-of-packet cell of the packet is received.
|Controller of a power converter with adjustable jitter amplitude and method of generating adjustable jitter amplitude thereof|
A controller of a power converter with adjustable jitter amplitude includes a feedback pin, a logic circuit, an auxiliary pin, and a current sensing pin. The feedback pin is used for receiving a feedback voltage from a secondary side of the power converter.
|Methods providing packet communications including jitter buffer emulation and related network nodes|
Packet communications may be provided over a wireless channel between a radio network node and a wireless terminal. The wireless terminal may include a jitter buffer configured to reduce jitter resulting from different delays of data packets received at the wireless terminal.
|Cascaded pll for reducing low-frequency drift in holdover mode|
A cascaded phase-locked loop (pll) clock generation technique reduces frequency drift of a low-jitter clock signal in a holdover mode. An apparatus includes a first pll circuit configured to generate a control signal based on a first clock signal and a first divider value.
|In-kernel srcu implementation with reduced os jitter|
A technique for implementing srcu with reduced os jitter may include: (1) providing a pair of critical section counters for each cpu; (2) when entering an srcu read-side critical section, incrementing one of the critical section counters associated with a first grace period; (3) when exiting an srcu read-side critical section, decrementing one of the critical section counters associated with the first grace period; (4) when performing a data update, initiating the second grace period and performing a counter summation operation that sums the critical section counters associated with the first grace period to generate a critical section counter sum; (5) storing a snapshot value for each critical section counter during the summing; and (6) if the critical section counter sum indicates there are no active srcu read-side critical sections for the first grace period, rechecking by comparing the snapshot values to current values of the critical section counters.. .
|Characterization of motion-related error in a stream of moving micro-entities|
Apparatus and methods for detecting and characterizing motion-related error of moving micro-entities are described. Motion-related error may occur in streams of moving micro-entities, and may represent a deviation in and expected arrival time or an uncertainty in position of a micro-entity.
|Method for actively controlling the optical output of a seed laser|
Seed pulse generators for fiber amplifier systems include a seed pump controller coupled to a seed pump laser diode. A photodetector is situated to detect seed pulse generation, and is coupled to the seed pump controller so that seed pumping is decreased upon pulse detection.
|Content aware video resizing|
In accordance with some embodiments, jitter accompanying video resizing, can be reduced or even eliminated by analyzing the content that is to be depicted and resizing based on the nature of the content being depicted. As a result, dominant objects in one frame can be handled in a way that reduces or eliminates video jitter or sliding..
|Semiconductor device design method and design apparatus|
A relationship between distance from a back bias control section which outputs a control signal for controlling a back bias of a transistor and an amount of noise in the control signal outputted from the back bias control section is found. An increase of jitter corresponding to the amount of the noise in a clock transmitted on a clock path connected to a circuit section (ip macro) is found on the basis of the relationship between the distance from the back bias control section and the amount of the noise.
|Compensation of motion-related error in a stream of moving micro-entities|
Apparatus and methods for detecting, characterizing, and compensating motion-related error of moving micro-entities are described. Motion-related error may occur in streams of moving micro-entities, and may represent a deviation in and expected arrival time or an uncertainty in position of a micro-entity within the stream.
|Receiver having limiter-enhanced data eye openings|
A communication system having a receiver with a linear path and a nonlinear path. As the receiver receives a data signal, it adaptively equalizes the received signal, and amplitude-limits the equalized signal in the nonlinear path using a saturable amplifier limiter or the like.
|Technique for filtering of clock signals|
In one embodiment, a clock generator generates a clock signal, and a clock channel generates a filtered clock signal from the clock signal. The clock channel comprises at least one filter that (i) attenuates noise in at least one nyquist zone of the clock signal adjacent to the fundamental frequency and (ii) passes at least one harmonic frequency of the clock signal other than the fundamental frequency.
|System and method for precise, accurate and stable optical timing information definition including internally self-consistent substantially jitter free timing reference|
An optoelectronic timing system includes an optical timing compensation system in which optical pulses from a semiconductor laser are advanced or retarded based upon an expected arrival time. The pulses are directed into a number of time-quantifiable optical paths.
Disclosed is an optical transceiver 1 including a phase locked loop circuit 3a configured to receive a reference clock cl1 and remove a jitter component of the reference clock cl1; a second phase locked loop circuit 3b configured to receive an output of the first phase locked loop circuit, generate a multiplied clock cl3 synchronized with the output, and when the frequency of the output deviates from a predetermined range and is in an abnormal state, output an alarm signal alm1; and an optical transmitter module 5 configured to output an optical output signal modulated based on the multiplied clock cl3 and electrical signals d1, d2, d3, and d4 from the outside.. .
|Ofdm clock recovery|
Receiver synchronization techniques (rst), contributing more accurate synchronization of receiver clock to ofdm composite frame combined with much faster acquisition time and better stability of the receiver clock, and phase and frequency recovery techniques, comprising a software controlled clock synthesizer (sccs) for high accuracy phase & frequency synthesis producing synchronized low jitter clock from external time referencing signals or time referencing messages wherein sccs includes a hybrid pll (hpll) enabling 1-50,000 frequency multiplication with very low output jitter independent of reference clock quality.. .
|Laser range finding|
Using a hand-held range finding device to range an object in a field of view is difficult due to user-induced jitter. In particular, user-induced jitter introduces uncertainty as to which object in a field of view is actually ranged.
|Mechanism for facilitating dynamic phase detection with high jitter tolerance for images of media streams|
A mechanism for facilitating dynamic phase detection with high jitter tolerance for images of media streams is described. In one embodiment, a method includes calculating stability optimization of an image of a media stream based on a plurality of pixels of two or more consecutive frames relating to a plurality of phases of the image, calculating sharpness optimization of the image, and selecting a best phase of the plurality of phases based on the stability and sharpness optimization of the image.
A jitter monitor includes: a voltage generating circuit configured to generate a first voltage that is varied with time at a predetermined inclination; a voltage reducing circuit configured to reduce the first voltage by a predetermined voltage in synchronization with a first clock signal so as to generate a second voltage that is varied with time at the predetermined inclination in synchronization with the first clock signal; and a sampling circuit configured to sample a portion having the predetermined inclination of the second voltage.. .
|Timing controller of display device and method for driving the same|
In a timing controller capable of decreasing flicker of an image to be displayed and a method of driving the same, the timing controller includes: a timing signal generator outputting a scan starting signal and clock signals to a scan driving unit; a sensing unit sensing status transition time points of the scan starting signal and the scan signal outputted from the scan driving unit for a plurality of frame periods; an estimator estimating a delay value and a jitter value with respect to the status transition time points; and an off-set signal generator generating an off-set signal for controlling the scan starting signal or the clock signals based on the delay value and the jitter value. The timing signal generator, in response to the off-set signal, regulates timings of the scan starting signal and the clock signals..
|Inductor design with metal dummy features|
Techniques are disclosed for enhancing performance of integrated or on-chip inductors by implementing a schema of conductive metal dummies in the design thereof. In some cases, a metal dummy schema may be disposed in a layer proximate an upper surface of the inductor.
|Determining worst-case bit patterns based upon data-dependent jitter|
The patent application discloses mechanisms that, for a given channel step or edge response, bit interval, and data dependent jitter table can directly determine the minimal eye or bit error rate opening by building a worst case pattern considering the effect of data dependent jitter. These mechanisms can be based on building an indexed table of jitter samples, preparing a structure in the form of connected elements corresponding to the jitter samples, and then applying dynamic programming to determine paths through the connected elements..