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Methods and circuits for reducing clock jitter


Methods and circuits for reducing clock jitter

Clock spurs reduction technique

Marvell World Trade Ltd

Clock spurs reduction technique

Clock spurs reduction technique


Synchronization processing device, synchronization processing method, and program

Date/App# patent app List of recent Jitter-related patents
 Ethernet carrier group alarm (cga) patent thumbnailEthernet carrier group alarm (cga)
Novel tools and techniques for providing network state information to customer equipment. In some embodiments, an operations, administration, and management (“oam”) server might determine a status of a network connection between at least two network devices, might generate state information indicating the determined status of the network connection, and might send the state information to one or more customer equipment, using in-band signaling over a band between the at least two network devices.
Centurylink Intellectual Property Llc
 Methods and circuits for reducing clock jitter patent thumbnailMethods and circuits for reducing clock jitter
A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled.
Rambus Inc.
 Clock spurs reduction technique patent thumbnailClock spurs reduction technique
Aspects of the disclosure provide a circuit having a jittered clock generator. The jittered clock generator is configured to add jitter of a controlled characteristic to a first clock signal of a clock frequency to generate a second clock signal to be used by a transceiver for operating at a radio frequency.
Marvell World Trade Ltd
 Synchronization processing device, synchronization processing method, and program patent thumbnailSynchronization processing device, synchronization processing method, and program
The present technology relates to a synchronization processing device, a synchronization processing method, and a program, which make it possible to achieve frequency synchronization in a shorter period of time. A jitter amount calculation unit calculates a jitter amount on the basis of a synchronization packet containing time information.
Sony Corporation
 Voice communication method and apparatus and  operating jitter buffer patent thumbnailVoice communication method and apparatus and operating jitter buffer
Voice communication method and apparatus and method and apparatus for operating jitter buffer are described. Audio blocks are acquired in sequence.
Dolby Laboratories Licensing Corporation
 Controller for generating jitters in a quasi resonant mode and  generating jitters in a quasi resonant mode patent thumbnailController for generating jitters in a quasi resonant mode and generating jitters in a quasi resonant mode
A controller for generating jitters in a quasi resonant mode includes a feedback pin, a voltage generation unit, a pulse generator, and a comparator. The feedback pin is used for receiving a feedback voltage from a secondary side of a power converter.
Leadtrend Technology Corp.
 Jitter-based transmission control method patent thumbnailJitter-based transmission control method
A jitter-based transmission control method is disclosed. In the jitter-based transmission control method, several packets are sent applying a current congestion window size by at least one sender device through a network switch device.
National Central University
 Fast motion detection with gpu patent thumbnailFast motion detection with gpu
Disclosed are systems and methods for determining when to focus a digital camera to capture a scene. A current frame and a prior frame are differenced to determine a frame difference.
Motorola Mobility Llc
 System and  efficient post-processing video stabilization with camera path linearization patent thumbnailSystem and efficient post-processing video stabilization with camera path linearization
Described herein are methods, systems, and apparatus to process video images to remove jitteriness due to hand shake. In one aspect, a camera is configured to capture raw video composed of a series of successive image frames of a scene of interest.
Qualcomm Incorporated
 System clock jitter correction patent thumbnailSystem clock jitter correction
A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency.
Q-analog Corporation

High-speed low-jitter communication system

Communication apparatus and techniques, such as for optical communication, can include providing a reference frequency derived from an atomic energy level transition or a molecular energy level transition, generating at least two specified optical carrier signals at least in part using the reference frequency, coherently modulating the specified optical carrier signals using respective baseband information signals to provide respective coherently-modulated optical subcarriers. A combined optical information signal comprising the optical subcarriers can be transmitted to a receiver, such as via a fiber optic cable.
Raytheon Company

Frequency multiplier jitter correction

A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency.
Iq-analog Corporation

Method and system for synchronizing positron emission tomography (pet) detector modules

A detector module (50) for a positron emission tomography (pet) system (10) includes an optical transceiver (66) receiving an optical data stream from a pet processing system (48). The data stream includes a pulse train carrying a command to generate sync/reset pulses.
Koninklijke Philips N.v

Swept source optical coherence tomography and stabilizing phase thereof

In an embodiment, a computer 16, which generates tomographic images based on spectral interference signals detected by a light detector 15 from overlaid reference light emitted by a swept-source type light source 2 of a ss-oct, split, and then reflected by a fixed reference mirror 8 on one hand and object light reflected by an object to be measured 6 on the other, is caused to function to apply rough correction using a first correction means and then apply detailed correction using a second correction means, to stabilize the phases of the ss-oct. The phases can be stabilized by eliminating, without adding any expensive, complex hardware, the jitter between the wavelength scanning of a light source of ss-oct and the timing of collecting the scan data with the light detector as spectral interference signals..
University Of Tsukuba

Clock jitter and power supply noise analysis

Disclosed are a method, system, and/or apparatus to perform clock jitter and power supply noise analysis. In one embodiment, a method may include receiving a first signal, which may be a clock signal, then generating a second signal based on the first signal.
Nvidia Corporation

Circuits for dynamically adaptive bit-leveling by sweep sampling with automatic jitter avoidance

A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device.
Uniquify, Inc.

Suppression of fixed-pattern jitter using fir filters

Fir filters for compensating for fixed pattern jitter, and methods of constructing the same, are disclosed. In one embodiment, a fir filter filters a signal having a desired frequency component, with the coefficients of the fir filter selected so that the filter is the equivalent of two combined fir filters, one having the desired frequency at the filter's peak output frequency, and a second in which the signal is delayed by a time equal to half of a period of a different frequency which is desired to be removed from the on signal.
Ess Technology, Inc.

Implementing a high quality voip device

A method is provided for voice over internet protocol (voip) devices to communicate over an internet protocol (ip) network. The method includes synchronizing the voip devices using one or more dual-tone multi-frequency (dtmf) codes over a telephone network, retransmissions of voice packets in bursts, retransmissions of voice packets following a time lag, adjusting the number of retransmissions based on quality of service, retransmission of a missing voice packet identified in a list received from a peer device, discarding low energy voice frames in a jitter buffer to prevent overflow, stopping playout at a low energy voice frame when the jitter buffer is below a minimum buffer size, and selective transmission and retransmission of voice packets based on their energy levels..
Arcsoft (shanghai) Technology Company, Ltd.

Beacon jitter prediction for wireless local area network (lan) devices

A method for activating a wireless communication device, the method may include receiving, by the wireless communication device, a sequence of periodic transmissions; estimating, for each periodic transmission of the sequence of periodic transmissions and before a reception of the periodic transmission, an expected time of arrival of the periodic transmission; calculating, for each periodic transmission, a timing difference attribute that is responsive to at least a difference between a timing of arrival of the periodic transmission and an expected time of arrival of the periodic transmission; selecting a selected periodic transmission out of the sequence of periodic transmissions, wherein the selected periodic transmission is associated with a smallest timing difference attribute out of the timing difference attributes associated with the periodic transmissions of the sequence of periodic transmissions; estimating, before a reception of a future periodic transmission that does not belong to the sequence of periodic transmissions, an estimated time of arrival of the future periodic transmission in response to the selecting of the selected periodic transmission and a periodic transmission period; determining a wakening time for wakening the wireless communication device in response to the estimated time of arrival of the future periodic transmission; and wakening the wireless communication device at the wakening time and searching for the future periodic transmission.. .
Dsp Group Ltd.

Frequency synthesis with gapper and multi-modulus divider

Systems and methods for frequency synthesis using a gapper and a multi-modulus divider. A frequency synthesizer may comprise a gapper, a multi-modulus divider and a phase locked loop (pll).
Applied Micro Circuits Corporation

Methods for dynamically adaptive bit-leveling by sweep sampling with automatic jitter avoidance

A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device.
Uniquify, Inc.

Interaction device corrective parameters

The techniques described herein are directed to receiving parameters directed to correcting spatial error and/or jitter associated with an interaction device connected to a computing device. In some instances, the parameters are encrypted parameters that may be decrypted and consumed to correct the spatial error and/or the jitter associated with the interaction device.
Microsoft Corporation

Method for estimating network jitter in transmitting coded media data

The present invention relates to a method for estimating network jitter, which has the effect of more precisely estimating network jitter by using time information corresponding to a transmission time, which is transmitted from a transport layer in a transmitting end to a receiving end.. .
Electronics And Telecommunications Research Institute

Enhancing jitter buffer performance through radio level feedback

A jitter buffer in a voice over lte receiver may be influenced by radio level feedback (rlf) from both local and remote endpoints to preemptively adjust the jitter buffer delay in anticipation of predicted future losses that have a high probability of occurring. The radio events of the rlf and the scenarios that trigger the preemptive adjustments may be identified, and their use may be expressed in terms of mathematical formulas.

Method and processing a video signal

Method, apparatus and computer program product for processing a video signal, the video signal comprising a plurality of frames, wherein the frames of the video signal are received at a jitter buffer, and the frames are output from the jitter buffer at a variable output rate to account for jitter in the received frames. Variations in the output rate are controlled in dependence upon the visual information content of the video signal, the visual information content of the video signal being the portion of the video signal that is to be displayed when the video signal is played out..

Audio playback method, apparatus and system

An audio playback method is provided. The method includes identifying a captured audio data frame according to a type of the audio data frame and sending the identified audio data frame to an audio receiving end.

Adaptive motion instability detection in video

Output video frames, which may be stabilized or non-stabilized, may then be stored to a memory. In certain embodiments, video motion instability is scored based on a probability distribution of video frame motion jitter values..

Allocation of shared resources for virtualized networking

Technology for allocating network adapter resources such as air interface time and queue space amongst multiple virtual network stations or other virtual adapters is disclosed. As one example, the resource allocation may be based on analysis of the relative latency, jitter, or bandwidth considerations for applications communicating via each of the multiple virtual adapters.

Communication method and communication apparatus

The present disclosure provides an orthogonal codes based code division multiplexing method of performing the code division multiplexing of demodulation reference signals in multiple layers of resource blocks by using orthogonal matrices, the method comprising: changing the order of chips in particular rows of a first orthogonal matrix to obtain a second orthogonal matrix with the changed order of chips; and multiplying the chips in respective rows of the second orthogonal matrix by the demodulation reference signals in corresponding layers of resource blocks correspondingly in the time direction to obtain code division multiplexing signals. The technical scheme of the present disclosure can improve the power jitter situation of downlink signals on the time, thereby the usage efficiency of the power amplifier at the base station side can be improved..

System and suppressing jitter in digital data signals including image, video and audio data signals

A system and method for suppressing jitter in a digital data signal in a signal processor system. The digital data signal has spaced apart byte allocation units wherein such spacing is increased such that unallocated bytes can be identified and removed from the digital data signal.

Method and source-synchronous signaling

A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (milo) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the milo clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals..

Serial communication control circuit

In a serial communication control circuit, serial data transmitted from a transmission processing unit is switched to data generated in a mark ratio improvement data generation unit depending on a switch signal from the transmission processing unit, and is transmitted. Thereby, mark ratio improvement data is inserted in a transmission signal to improve a mark ratio during communication, thereby preventing reception signal's jitters from increasing..

System, device, and voice-over-ip communication

The present invention includes devices, systems, and methods of voice-over-internet protocol (voip) communication. For example, a method includes: receiving a data stream comprising a set of voip packets; and modifying a real time protocol (rtp) header of at least one of said voip packets to modify a jitter buffer delay of said data stream.

Optical scanning device, manufacturing the optical scanning device, and image forming apparatus

An optical scanning device includes a deflector configured to deflect a plurality of light beams emitted from a plurality of light emitters that are mutually spaced apart in a sub-scanning direction; an incident optical system configured to steer the plurality of light beams so as to be incident on the deflector; an imaging optical system configured to steer the plurality of light beams so as to be obliquely incident on a surface to be scanned and to form images of the plurality of light emitters on the surface to be scanned; and a correction unit configured to correct a jitter of at least one of the plurality of light beams in a main scanning direction on the basis of irradiation position information, in the sub-scanning direction, of at least one light beam among the plurality of light beams at a point corresponding to the surface to be scanned.. .

Using clock drift, clock slew, and network latency to enhance machine identification

Methods and systems for authenticating a user device employ a database of global network latencies categorized and searchable by location and calendar date-time of day usage, providing network latency by geography and by time. The database is constructed using voluminous daily data collected from a world-wide clientele of users who sign in to a particular website.

Implementing data frequency and data bits per sector (bps) calibration for non-circular disk tracks

A method, apparatus and a data storage device are provided for implementing data frequency and data bits per sector (bps) calibration for data written on a recordable surface including non-circular disk tracks of a storage device. A sector based bps profile is created for data sectors on the recordable surface.

Power supply induced signal jitter compensation

Examples of circuits and methods for compensating for power supply induced signal jitter in path elements sensitive to power supply variation. An example includes a signal path coupling an input to an output, the signal path including a delay element having a first delay and a bias-controlled delay element having a second delay.

Method and smoothing jitter generated by byte stuffing

Systems and methods for smoothing jitter generated by byte stuffing. A frequency synthesizer comprises a smoothing logic coupled with a pll.

Distributed phase-correction circuit

A distributed phase-correction circuit is described. This distributed phase-correction circuit reduces jitter in a delay line by averaging edge delay through local feedback of signals internal to the delay line.

Femto cell access point passthrough model

Fixed, differentiated quality of service (qos) is supplied for packetized traffic (e.g., voice and data) intended for femto cell coverage when transmitted concurrently with external broadband traffic. Quality of service differentiation is supplied without an external implementation.

Continuous phase adjustment based on injection locking

A phase-modification circuit is described. This phase-modification circuit reduces jitter by injecting a divided reference clock in a phase-locked loop from an auxiliary oscillator and by effectively gradually and completely transferring its phase to a master oscillator.

Method of managing a jitter buffer, and jitter buffer using same

The present invention relates to a method of managing a jitter buffer and a jitter buffer using same. The method of managing a jitter buffer includes the steps of: receiving audio information frames; and adjusting a jitter buffer on the basis of the received audio information frames, wherein the adjusting step of the jitter buffer includes compensation of an audio signal, and the compensation of the audio signal can be performed for each sub frame of the audio information frames..

Rate-controlled optical burst switching

The invention provides a method and network communication equipment for low latency loss-free burst switching. Burst-transfer schedules are determined by controllers of bufferless core nodes according to specified bitrate allocations and distributed to respective edge nodes.

High resolution current pulse analog measurement

A measurement system includes a current source that is arranged to generate a current pulse to charge a capacitor as a function of an input clock signal. The accumulated charge on the capacitor is converted to a sample (e.g., resultant digital value) by an adc (analog-to-digital converter).

Switching power supply device

The invention provides a switching power supply device such that the occurrence of noise is reduced by jitter control of a switching frequency. The switching power supply device includes a switching power supply device main body wherein a predetermined output direct current voltage is obtained by switching an input alternating current voltage using a switching element, a switching control unit that controls the switching frequency in accordance with a feedback voltage that indicates the difference between an output set voltage and the output direct current voltage, a jitter control unit that applies jitter to the switching frequency, and a jitter amplitude control unit that changes jitter amplitude caused by the jitter control unit in accordance with the feedback voltage..

Portable device and providing non-contact interface

A method for controlling operations of a portable device through a touch-free user input in the portable device having a projector module is provided. To this end, once the projector module is driven, an application execution screen is projected through the projector module, and if a proximity event is detected, a camera module is activated to acquire an image from which a user gesture is recognized.

Systems and methods for determining and displaying multi-line foreign language translations in real time on mobile devices

The present invention is related to systems and methods for translating language text on a mobile camera device offline without access to the internet. More specifically, the present invention relates to systems and methods for displaying text of a first language and a translation of the first language text into a second language text which is displayed in real time in augmented reality on the mobile device.

Method & circuit for parasitic capacitance cancellation for self capacitance sensing

Apparatus and methods to measure capacitance changes for a touch-sensitive capacitive matrix are described. Charge-removal circuits and measurement techniques may be employed to cancel deleterious effects of parasitic capacitances in the touch-sensitive capacitive matrix.

Syncless unit interval variation tolerant pwm receiver circuit, system and method

A pwm receiver circuit receives and demodulates pulse width modulated (pwm) data signals without requiring synchronization such that no synchronization preamble need be provided with the pwm data signal. Embodiments may consume less power since there is no need to repeatedly synchronize a pll, counter or other circuitry to the pwm data signal.

V+hu 2 +l power converter control with capacitor current ramp compensation

Operation of a switching power converter having an output capacitor having a small equivalent series resistance (esr) is stabilized and jitter reduced by sensing capacitor current with gain and combining the resulting signal with the output voltage signal to provide a feedback signal to control switching of the power converter. Capacitor current can be sensed without interfering with operation of the filter capacitor by providing a branch circuit having a time constant matched to the output or filter capacitor but an arbitrarily high impedance so as to be effectively lossless.

Methods for dynamically adaptive bit-leveling by incremental sampling, jitter detection, and exception handling

A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device.

Dynamically adaptive bit-leveling for data interfaces

A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device.

Jitter buffering system and jitter buffering

A jitter buffering system and a method of jitter buffering. The jitter buffering system may be embodied in a quality of service (qos) management server, including: (1) a network interface controller (nic) configured to receive one-way-delay statistics regarding a video stream transmitted to a client, and (2) a processer configured to employ the one-way-delay statistics to calculate and recognize jitter and subsequently generate a command for the client to enable jitter buffering..

Method and related network element providing delay measurement in an optical transport network

A delay measurement method of a path (p) or path segment through a transport network and a corresponding network nodes (ne1, ne2) for performing the delay measurement are described, which provide a higher precision and lower jitter. An originating network node (ne1) inserts a delay measurement request signal (req) into an overhead subfield of a first data unit and transmits the first data unit over the path (p) or path segment to a far-end network node (ne2) as part of framed transport signals.

Image synchronization of scanning wafer inspection system

An inspection system comprises a beam generator module for deflecting spots across scan portions of a specimen. The system also includes detection channels for sensing light emanating from a specimen in response to an incident beam directed towards such specimen and generating a detected image for each scan portion.

Receiver circuit, semiconductor integrated circuit, and test method

A receiver circuit includes a cdr circuit, a jitter generator unit, a test pattern generator unit, and a comparator unit. The jitter generator unit generates jitter having first characteristics (frequency and amplitude).

Injection locking of gain switched diodes for spectral narrowing and jitter stabilization

Pulse power can be stabilized by applying spectrally narrow pulses to a laser diode during gain switching. An injection locking laser with a narrow emission bandwidth is tuned to a gain bandwidth of a laser diode to be gain switched.

Low-power and all-digital phase interpolator-based clock and data recovery architecture

The proposed invention is about an improved method for serial-in and serial-out transceiver applications. The proposed system includes a dual loop phase locked loop (pll) architecture having a pll and a phase rotator (pr)-based delay locked loop (dll).

Timestamp estimation and jitter correction using downstream fifo occupancy

First, a packet may be received and a timestamp value may be placed on the packet. The timestamp value may comprise a place time value comprising a time when the timestamp was placed on the packet plus a delay time value comprising an estimated time delay between when the timestamp was placed on the packet and when the packet leaves a port exit.

System and jitter mitigation in time division multiple access (tdma) communications systems

A tdma jitter buffer includes a receiver, a processor and a comparator. The receiver can receive a data transmission signal via a channel of a communications system, and can receive one or more delay factors measured at a transmission end of the channel, wherein each delay factor is associated with a respective data packet.

Synchronous semiconductor memory device having dual delay locked loop circuit and managing dual delay locked loop circuit

A synchronous semiconductor memory device includes a first delay locked loop circuit and a second delay locked loop circuit. The first delay locked loop circuit has a first delay line and generates a first clock hat is delay-synchronized with a clock applied as a signal for a data output timing control.

Cascaded camera motion estimation, rolling shutter detection, and camera shake detection for video stabilization

An easy-to-use online video stabilization system and methods for its use are described. Videos are stabilized after capture, and therefore the stabilization works on all forms of video footage including both legacy video and freshly captured video.

Tilting to scroll

In one embodiment, a method includes sending information to display an image on a screen. A scroll range for the image may be determined based on dimensions of the image.

Frequency synthesis with gapper

Systems and methods for frequency synthesis using a gapper. A frequency synthesizer may comprise a gapper, a first integer divider and a phase locked loop (pll).

Phase interpolator based output waveform synthesizer for low-power broadband transmitter

Exemplary embodiments of the present invention relate to an output waveform synthesizer using phase interpolators and an on-chip eye opening monitoring (eom) circuit for a low-power transmitter. In order to achieve both small area and low-power consumption in the transmitter design, a single-stage multiphase multiplexer operating in subrate is employed.

Ring electrode device and generating high-pressure pulses

A method, system, and electrode assembly are disclosed that maximizes the lifetime of electrodes for high energy electrical discharges in water by arranging the electrodes in concentric rings or a stack of concentric rings. The radii and the thickness of the ring electrodes are optimized for electrical reliability, low jitter, and minimal erosion.

Method and device for reporting cell status

Determining a distribution delay of a bearer by using a preset delay distribution algorithm according to a preset time period for reporting a cell status; starting a periodic timer of the bearer after the distribution delay elapses, where the periodic timer uses the time period as a period; determining, according to the periodic timer, whether the cell status needs to be reported; and carrying information of the cell status in an uplink data packet of the bearer if the cell status needs to be reported. Thereby avoiding greatly centralized reporting of the cell status and centralized policy adjustment that is performed for the bearers, so that great jitter of service traffic borne on a cell is controlled effectively..

Transmit reference signal cleanup within a synchronous network application

A network processor is described that includes a network reference clock processor module for providing an at least substantially low-jitter, low-wander reference signal. In one or more embodiments, the network reference clock processor module includes a digital phase locked loop configured to at least substantially attenuate a wander noise portion from a reference signal.

Phase locked loop frequency synthesizer with reduced jitter

A phase locked loop frequency synthesizer has a controlled oscillator for generating an output signal at a desired frequency, a phase/frequency detector module for comparing a feedback signal derived from the controlled oscillator with a reference signal to generate an error signal, a loop filter for processing said at least one error signal from said phase/frequency detector module to generate a combined control signal for the controlled oscillator. The gain of the phase/frequency detector module can be adjusted, preferably by varying the pulse width and pulse cycle, to maintain the overall gain of the phase locked loop within a given range and thereby maximize signal to noise ratio..

Comprehensive multipath routing for congestion and quality-of-service in communication networks

A packet routing method includes computing, for each source node in the data network and each destination node in the data network, a set of multiple routes providing a full range of performance from the source node to the destination node. The multiple routes are preferably precomputed and stored.

Methods and systems for stabilizing live video in the presence of long-term image drift

Methods and systems stabilization of a camera image for short term or ‘pole shake’ and longer term ‘pole drift’ are provided. The camera is attached to a fixed structure.

Semiconductor integrated circuit

In a system in which the phases of a data clock signal and a data signal differ between at an input and at an output, a semiconductor integrated circuit performs a simple ber test without using external equipment and, at the same time, performs a jitter evaluation required for a margin evaluation.. .

Popular terms: [SEARCH]

Jitter topics: Duty Cycle Correction, Differential Amplifier, Duty Cycle, Frequency Detector, Photosensitive Drum, Simulation, Cell Phone, Data Packet, Mean Opinion Score, Network Communication, Signal Processing, Sequencing, Transmitter, Asynchronous, High Performance Serial Bus

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