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Jitter

Jitter-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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Dynamic jitter buffer size adjustment
At&t Mobility Ii Llc
June 22, 2017 - N°20170180275

In a particular implementation, a method includes dynamically adjusting a size of a buffer of a receiving terminal based on a comparison of a signal quality metric associated with a wireless communication channel between the receiving terminal and a transmitting terminal to a signal quality threshold. The method also includes storing a first set of data packets of a plurality ...
Method and apparatus for handling network jitter
Xiaomi Inc.
June 22, 2017 - N°20170180263

A method for handling network jitter is provided. The method includes: receiving a plurality of data packets and recording a receiving time of each data packet; calculating time intervals between all adjacent data packets according to the receiving time of each data packet; identifying a probability distribution of the time intervals according to a plurality of preset intervals; calculating a ...
Automated detection and analysis of call conditions in communication system
Unify Square, Inc.
June 15, 2017 - N°20170171048

A computing device automatically detects technical conditions for calls, such as voice calls, in a communication system. The technical conditions include transport type (e. G., tcp, udp), connection type (e. G., wired, wireless local area network, mobile/cellular), packet loss, latency, and jitter. The computing device performs automatic analysis of the detected technical conditions. The automatic analysis may include comparing ...
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Local phase detection in realigned oscillator
Infineon Technologies Ag
June 01, 2017 - N°20170155395

Representative implementations of devices and techniques provide reduced jitter and local phase detection for a controlled oscillator. An edge of a reference signal is injected at a point within the oscillator, and replaces an edge of the generated oscillation signal at the injection point. A phase difference of the injected reference signal and the oscillation signal is measured locally and ...
Prediction-based touch contact tracking
Egalax_empia Technology Inc.
June 01, 2017 - N°20170153768

When an external object approaches or touches a touch sensor, predicted locations of the external object can be generated by detected locations according to signals from the touch sensor. The latest predicted location is shifted backwards towards the latest reported location for a portion of the distance between the predicted location and the latest reported location to generate a new ...
Optical scanning device and image forming apparatus
Canon Kabushiki Kaisha
June 01, 2017 - N°20170153570

The present invention relates to an optical scanning device and an image forming apparatus. In order to suppress jitter, the degree of convergence of a first incident optical system and the degree of convergence of a second incident optical system are both equal to or greater than 0, and the degree of convergence of the second incident optical system is greater ...
Jitter Patent Pack
Download 96+ patent application PDFs
Jitter Patent Applications
Download 96+ Jitter-related PDFs
For professional research & prior art discovery
inventor
  • 96+ full patent PDF documents of Jitter-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Technique for filtering of clock signals
Canon Kabushiki Kaisha
May 25, 2017 - N°20170149465

In one embodiment, a clock generator generates a clock signal, and a clock channel generates a filtered clock signal from the clock signal. The clock channel comprises at least one filter that (i) attenuates noise in at least one nyquist zone of the clock signal adjacent to the fundamental frequency and (ii) passes at least one harmonic frequency of the ...
Circuit arrangement for controlling power transistors of a power converter
Canon Kabushiki Kaisha
May 25, 2017 - N°20170149428

A circuit arrangement for controlling power transistors of a power converter includes a logic circuit configured to generate a pulse-width modulation (pwm) signal and a clock generator configured to generate a clock signal. A first and a second isolator are configured to galvanically isolate transmission of the pwm signal and the clock signal into a high-voltage portion of the power ...
Systems and methods for end-to-end object detection
Canon Kabushiki Kaisha
May 25, 2017 - N°20170147905

Presented are systems and methods that provide a unified end-to-end detection pipeline for object detection that achieves impressive performance in detecting very small and highly overlapped objects in face and car images. Various embodiments of the present disclosure provide for an accurate and efficient one-stage fcn-based object detector that may be optimized end-to-end during training. Certain embodiments train the object ...
Clock jitter emulation
Canon Kabushiki Kaisha
May 25, 2017 - N°20170147725

An emulator emulating a dut emulates a clock generator for generating clock signals of the dut with jitter. As part of generating clock signals, the emulator generates a jitter clock value for each clock signal. To generate a jitter clock value for a clock signal, the emulator identifies a clock parameter stored for the clock signal and sums the clock ...
Allocation of shared resources for virtualized networking
Microsoft Technology Licensing, Llc
May 18, 2017 - N°20170142732

Technology for allocating network adapter resources such as air interface time and queue space amongst multiple virtual network stations or other virtual adapters is disclosed. As one example, the resource allocation may be based on analysis of the relative latency, jitter, or bandwidth considerations for applications communicating via each of the multiple virtual adapters. The resource allocation may also be ...
Multi-channel audio over a wireless network
Caavo Inc
May 18, 2017 - N°20170142535

Embodiments described herein reduce latency and improve packet delivery when transmitting audio packets from a source device to one or more sink devices. For example, one or more operating modes that introduce latency when transmitting packets may be disabled at the source device and/or sink device(s). Additionally, certain operational behavior of the source device and/or sink device(...
Video decoding and rendering using combined jitter and frame buffer
Cybrook Inc.
May 18, 2017 - N°20170142434

Systems, apparatuses and methods for decoding and encoding a video stream having a plurality of frames using a ring (circular) buffer are disclosed. When decoding, a decoder can receive packets from an encoder and store them in a circular buffer. The circular buffer can store packets until packets comprising complete frames are received. Storing multiple partial or complete frames in ...
Jitter Patent Pack
Download 96+ patent application PDFs
Jitter Patent Applications
Download 96+ Jitter-related PDFs
For professional research & prior art discovery
inventor
  • 96+ full patent PDF documents of Jitter-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Delay and jitter limited wireless mesh network scheduling
Wipro Limited
May 11, 2017 - N°20170135124

Schedule and channel assignment in a wireless mesh network (wmn) includes: forming a representation of a sequence of permutation matrices from an n×n rate matrix. The entries of the rate matrix define the bandwidth of links between nodes of the wmn. Each permutation matrix represents active radio links between nodes. The sequence of permutation matrices defines a sequence ...
Methods to minimize the recovered clock jitter
Huawei Technologies Co., Ltd.
May 11, 2017 - N°20170134189

A circuit according to an embodiment includes a first slicer connected to an input port and a threshold circuit connected to a threshold port of the first slicer and configured to generate a first threshold voltage according to at least a first magnitude of a nominal value of a leading bit in a signal received at the input port. The ...
Clock and data recovery having shared clock generator
Rambus Inc.
May 11, 2017 - N°20170134153

This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local cdr circuits, and associated cdr error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local cdr circuits is generated at a controllable oscillation frequency as a function of a combination ...
Reference-less frequency detector with high jitter tolerance
Futurewei Technologies, Inc.
May 04, 2017 - N°20170126236

An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, ...
Method and apparatus for voice communication based on voice activity detection
Dolby Laboratories Licensing Corporation
April 27, 2017 - N°20170118142

Voice communication method and apparatus and method and apparatus for operating jitter buffer are described. Audio blocks are acquired in sequence. Each of the audio blocks includes one or more audio frames. Voice activity detection is performed on the audio blocks. In response to deciding voice onset for a present one of the audio blocks, a subsequence of the sequence ...
System and method of providing improved throughput control under delay-based congestion situation in a network
Citrix Systems, Inc.
April 27, 2017 - N°20170118119

An apparatus and method of providing improved throughput on delay-based congestions comprising a packet engine and a delay-based congestion controller. The packet engine detecting a delay jitter that is caused by a layer 2 retransmission of a data packet, is configured to measure a round trip time (rtt) value. The delay-based congestion controller is configured to receive the rtt value and ...
User defined protocol for zero-added-jitter and error free transmission of layer-2 datagrams across lossy packet-switched ...
Citrix Systems, Inc.
April 27, 2017 - N°20170118008

A zero-added-jitter protocol for transmission of datagrams over packet-switched networks between two or more connected microprocessor devices with negligible packet delay variation, adjustable forward error correction, congestion control, and negative acknowledgment datagram recovery. A method for the analysis and preservation of the instantaneous bitrate and packet spacing provides for the output of the datagrams to a network facing provider edge ...
Frequency synthesizer with injection locked oscillator
Infineon Technologies Ag
April 27, 2017 - N°20170117907

Representative implementations of devices and techniques provide reduced jitter for a controlled oscillator. An edge of a reference signal is injected at various points within the oscillator, and is replaced for an edge of the generated oscillation signal at the injection point.
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