|| List of recent Jitter-related patents
|Phase locked loop frequency synthesizer with reduced jitter|
A phase locked loop frequency synthesizer has a controlled oscillator for generating an output signal at a desired frequency, a phase/frequency detector module for comparing a feedback signal derived from the controlled oscillator with a reference signal to generate an error signal, a loop filter for processing said at least one error signal from said phase/frequency detector module to generate a combined control signal for the controlled oscillator. The gain of the phase/frequency detector module can be adjusted, preferably by varying the pulse width and pulse cycle, to maintain the overall gain of the phase locked loop within a given range and thereby maximize signal to noise ratio..
|Comprehensive multipath routing for congestion and quality-of-service in communication networks|
A packet routing method includes computing, for each source node in the data network and each destination node in the data network, a set of multiple routes providing a full range of performance from the source node to the destination node. The multiple routes are preferably precomputed and stored.
|Methods and systems for stabilizing live video in the presence of long-term image drift|
Methods and systems stabilization of a camera image for short term or ‘pole shake’ and longer term ‘pole drift’ are provided. The camera is attached to a fixed structure.
|Semiconductor integrated circuit|
In a system in which the phases of a data clock signal and a data signal differ between at an input and at an output, a semiconductor integrated circuit performs a simple ber test without using external equipment and, at the same time, performs a jitter evaluation required for a margin evaluation.. .
|Output current compensation for jitter in input voltage for dimmable led lamps|
An led controller reduces jitter of an led lamp. In one embodiment, the led controller includes a jitter detection circuit adapted to determine an amount of jitter in an input voltage signal.
|Handling method and device for cell concatenation|
A handling method for cell concatenation, includes receiving a cell of a packet before a concatenation timeout period expires and before the total number of received cells of the packet reaches a concatenation number. The method further includes determining whether an end-of-packet cell of the packet is received.
|Controller of a power converter with adjustable jitter amplitude and method of generating adjustable jitter amplitude thereof|
A controller of a power converter with adjustable jitter amplitude includes a feedback pin, a logic circuit, an auxiliary pin, and a current sensing pin. The feedback pin is used for receiving a feedback voltage from a secondary side of the power converter.
|Methods providing packet communications including jitter buffer emulation and related network nodes|
Packet communications may be provided over a wireless channel between a radio network node and a wireless terminal. The wireless terminal may include a jitter buffer configured to reduce jitter resulting from different delays of data packets received at the wireless terminal.
|Cascaded pll for reducing low-frequency drift in holdover mode|
A cascaded phase-locked loop (pll) clock generation technique reduces frequency drift of a low-jitter clock signal in a holdover mode. An apparatus includes a first pll circuit configured to generate a control signal based on a first clock signal and a first divider value.
|In-kernel srcu implementation with reduced os jitter|
A technique for implementing srcu with reduced os jitter may include: (1) providing a pair of critical section counters for each cpu; (2) when entering an srcu read-side critical section, incrementing one of the critical section counters associated with a first grace period; (3) when exiting an srcu read-side critical section, decrementing one of the critical section counters associated with the first grace period; (4) when performing a data update, initiating the second grace period and performing a counter summation operation that sums the critical section counters associated with the first grace period to generate a critical section counter sum; (5) storing a snapshot value for each critical section counter during the summing; and (6) if the critical section counter sum indicates there are no active srcu read-side critical sections for the first grace period, rechecking by comparing the snapshot values to current values of the critical section counters.. .
|Characterization of motion-related error in a stream of moving micro-entities|
Apparatus and methods for detecting and characterizing motion-related error of moving micro-entities are described. Motion-related error may occur in streams of moving micro-entities, and may represent a deviation in and expected arrival time or an uncertainty in position of a micro-entity.
|Method for actively controlling the optical output of a seed laser|
Seed pulse generators for fiber amplifier systems include a seed pump controller coupled to a seed pump laser diode. A photodetector is situated to detect seed pulse generation, and is coupled to the seed pump controller so that seed pumping is decreased upon pulse detection.
|Content aware video resizing|
In accordance with some embodiments, jitter accompanying video resizing, can be reduced or even eliminated by analyzing the content that is to be depicted and resizing based on the nature of the content being depicted. As a result, dominant objects in one frame can be handled in a way that reduces or eliminates video jitter or sliding..
|Semiconductor device design method and design apparatus|
A relationship between distance from a back bias control section which outputs a control signal for controlling a back bias of a transistor and an amount of noise in the control signal outputted from the back bias control section is found. An increase of jitter corresponding to the amount of the noise in a clock transmitted on a clock path connected to a circuit section (ip macro) is found on the basis of the relationship between the distance from the back bias control section and the amount of the noise.
|Compensation of motion-related error in a stream of moving micro-entities|
Apparatus and methods for detecting, characterizing, and compensating motion-related error of moving micro-entities are described. Motion-related error may occur in streams of moving micro-entities, and may represent a deviation in and expected arrival time or an uncertainty in position of a micro-entity within the stream.
|Receiver having limiter-enhanced data eye openings|
A communication system having a receiver with a linear path and a nonlinear path. As the receiver receives a data signal, it adaptively equalizes the received signal, and amplitude-limits the equalized signal in the nonlinear path using a saturable amplifier limiter or the like.
|Technique for filtering of clock signals|
In one embodiment, a clock generator generates a clock signal, and a clock channel generates a filtered clock signal from the clock signal. The clock channel comprises at least one filter that (i) attenuates noise in at least one nyquist zone of the clock signal adjacent to the fundamental frequency and (ii) passes at least one harmonic frequency of the clock signal other than the fundamental frequency.
|System and method for precise, accurate and stable optical timing information definition including internally self-consistent substantially jitter free timing reference|
An optoelectronic timing system includes an optical timing compensation system in which optical pulses from a semiconductor laser are advanced or retarded based upon an expected arrival time. The pulses are directed into a number of time-quantifiable optical paths.
Disclosed is an optical transceiver 1 including a phase locked loop circuit 3a configured to receive a reference clock cl1 and remove a jitter component of the reference clock cl1; a second phase locked loop circuit 3b configured to receive an output of the first phase locked loop circuit, generate a multiplied clock cl3 synchronized with the output, and when the frequency of the output deviates from a predetermined range and is in an abnormal state, output an alarm signal alm1; and an optical transmitter module 5 configured to output an optical output signal modulated based on the multiplied clock cl3 and electrical signals d1, d2, d3, and d4 from the outside.. .
|Ofdm clock recovery|
Receiver synchronization techniques (rst), contributing more accurate synchronization of receiver clock to ofdm composite frame combined with much faster acquisition time and better stability of the receiver clock, and phase and frequency recovery techniques, comprising a software controlled clock synthesizer (sccs) for high accuracy phase & frequency synthesis producing synchronized low jitter clock from external time referencing signals or time referencing messages wherein sccs includes a hybrid pll (hpll) enabling 1-50,000 frequency multiplication with very low output jitter independent of reference clock quality.. .
|Laser range finding|
Using a hand-held range finding device to range an object in a field of view is difficult due to user-induced jitter. In particular, user-induced jitter introduces uncertainty as to which object in a field of view is actually ranged.
|Mechanism for facilitating dynamic phase detection with high jitter tolerance for images of media streams|
A mechanism for facilitating dynamic phase detection with high jitter tolerance for images of media streams is described. In one embodiment, a method includes calculating stability optimization of an image of a media stream based on a plurality of pixels of two or more consecutive frames relating to a plurality of phases of the image, calculating sharpness optimization of the image, and selecting a best phase of the plurality of phases based on the stability and sharpness optimization of the image.
A jitter monitor includes: a voltage generating circuit configured to generate a first voltage that is varied with time at a predetermined inclination; a voltage reducing circuit configured to reduce the first voltage by a predetermined voltage in synchronization with a first clock signal so as to generate a second voltage that is varied with time at the predetermined inclination in synchronization with the first clock signal; and a sampling circuit configured to sample a portion having the predetermined inclination of the second voltage.. .
|Timing controller of display device and method for driving the same|
In a timing controller capable of decreasing flicker of an image to be displayed and a method of driving the same, the timing controller includes: a timing signal generator outputting a scan starting signal and clock signals to a scan driving unit; a sensing unit sensing status transition time points of the scan starting signal and the scan signal outputted from the scan driving unit for a plurality of frame periods; an estimator estimating a delay value and a jitter value with respect to the status transition time points; and an off-set signal generator generating an off-set signal for controlling the scan starting signal or the clock signals based on the delay value and the jitter value. The timing signal generator, in response to the off-set signal, regulates timings of the scan starting signal and the clock signals..
|Inductor design with metal dummy features|
Techniques are disclosed for enhancing performance of integrated or on-chip inductors by implementing a schema of conductive metal dummies in the design thereof. In some cases, a metal dummy schema may be disposed in a layer proximate an upper surface of the inductor.
|Determining worst-case bit patterns based upon data-dependent jitter|
The patent application discloses mechanisms that, for a given channel step or edge response, bit interval, and data dependent jitter table can directly determine the minimal eye or bit error rate opening by building a worst case pattern considering the effect of data dependent jitter. These mechanisms can be based on building an indexed table of jitter samples, preparing a structure in the form of connected elements corresponding to the jitter samples, and then applying dynamic programming to determine paths through the connected elements..
|Bicmos gate driver for class-s radio frequency power amplifier|
The invention may be embodied in a resynchronizing, push-pull drive circuit for driving the gate electrodes of a digital class-s radio frequency power amplifier (rf-pa). A binary bitstream received from a bitstream generator, such as a sigma-delta modulator, viterbi-based optimal-bit-pattern modulator sigma-delta, or other suitable modulator, is resynchronized to a low-jitter master clock, then converted to fast-rise, high-swing complementary digital signals to drive the gates of the class-s rf-pa.
|Device timing adjustments and methods for supporting dash over broadcast|
The systems, methods, and devices of the various embodiments enable a receiver device to adjust timing of requests for segments based on the actual times when the segments will be available on the receiver device. In various embodiments, a receiver device may be enabled to modify a segment availability timeline in which the availability times of the segments are adjusted to provide the actual times when segments will be available on the receiver device.
|System and method for removal of jitter from seismic data|
A system and method are provided for reducing jitter in collected seismic data. The collected seismic data includes both original seismic data, e.g., original traces, and other seismic data, e.g., interpolated traces.
|Method and apparatus for generating jitter-related data|
A jitter-associated data generator is provided for generating data associated with jitter. The jitter-associated data generator comprises a first circuit, a second circuit, and a third circuit.
|Synchronous transfer of streaming data in a distributed antenna system|
Embodiments of the invention provide a method, distributed antenna system, and components that generate a jitter reduced clock signal from a binary encoded data stream transmitted over a communication medium. The method includes receiving a modulated signal that includes the binary encoded data stream and generating a recovered clock signal that is phase locked to the binary encoded data stream.
|Communication method, communication terminal, supervisor terminal and related computer programmes|
A communication method in a communications network is provided. The method includes, in a communications network in which a communication link has been communication link having been allocated by a resource manager module in accordance with a first value of a characteristic of data rate, latency or jitter required for providing a first service on the said link between a first and a second communication terminal, the steps of transmitting a request to replace the said first communication service by a second communication service between at least the first and second terminals; further to receipt of the said request by the resource manager module of the network, replacing by the said resource manager module of the first value of the said characteristic by a second value required for providing the said second service; and providing the second communication service instead of the first communication service between the first and second terminals on the said communication link..
|Audio or voice signal processor|
A voice or audio signal processor for processing received network packets received over a communication network to provide an output signal, the voice or audio signal processor comprising a jitter buffer being configured to buffer the received network packets, a voice or audio decoder being configured to decode the received network packets as buffered by the jitter buffer to obtain a decoded voice or audio signal, a controllable time scaler being configured to amend a length of the decoded voice or audio signal to obtain a time scaled voice or audio signal as the output voice or audio signal, and an adaptation control means being configured to control an operation of the time scaler in dependency on a processing complexity measure.. .
|Distortion measurement for limiting jitter in pam transmitters|
Methods and test equipment for measuring jitter in a pulse amplitude modulated (pam) transmitter. Under one procedure, a first two-level pam signal test pattern is used to measure clock-related jitter separated into random and deterministic components, while a second two-level pam signal test pattern is used to measure oven-odd jitter (eoj).
|Multipath communication in a network|
Ways of sending data over a network over a single path or over multiple parallel paths on an as-needed basis depending upon network conditions, and/or other factors, are described. For example, if a computing device detects sufficient jitter and/or latency at one or more network interfaces, the data may be sent over two or more communication paths using two or more network interfaces..
|Systems and methods for reduction of motor jitter while driving an electric motor|
An apparatus for driving a motor comprises a drive signal generation circuit configured to produce pulses on a pulse-width modulated drive signal in response to a control signal. A detection circuit is coupled to receive a commutation signal from the motor to monitor the speed of the motor.
|Method for data transmission among ecus and/or measuring devices|
A method for accelerated data transmission among electronic control units (ecus) and/or measuring devices in the context of motor vehicles is provided. In order to enable an accelerated data transmission, in particular fast (low) event cycle times, a low jitter and a high data throughput, the architecture of the data transmission is split up into (i) a control plane implemented in software operating on configuration, calibration and/or diagnostics data (“cd” data), and (ii) a data plane implemented in hardware transporting measurement data (“m” data) and/or prototyping data (“rp” data)..
|Data sending or receiving method, device, and apparatus used in optical fiber transmission|
The present invention relates to a fiber transmission field and provides a data sending or receiving method, device, and apparatus used in optical fiber transmission. The method includes: detecting data to be transmitted; encoding one bit pulse width to m parts if the to-be-transmitted data is 0, wherein the first part is a high-level, the later m−1 part is a low-level; encoding one bit pulse width to n parts if the to-be-transmitted data is 1, wherein the first part is a high level, and the later n−1 part is a low-level, the m is not equal to the n but both are integer which is greater than or equal to 2; and sending the encoded level signal.
|Apparatus and method for reducing jitter in periodic signals|
The present invention provides an apparatus and method for reducing jitter in a periodic signal. The apparatus comprises: a frequency discriminator configured to receive the periodic signal and feedback of an output signal of the apparatus and calculate an estimate value for a length of a current period of the periodic signal; a phase discriminator configured to receive the periodic signal and determine an adjustment factor for the length of the current period of an input signal according to the input signal in a previous period of the periodic signal and the output signal in the previous period of the apparatus; and an adjustor configured to determine the period length of the output signal in the current period according to the estimate value for the length of the current period and the adjustment factor for the length of the current period..
The electronic device and a corresponding signal processing method disclosed herein reduces electromagnetic noise. To that end, the electronic device includes a delay line, an oscillator, and a modulator.
|Method and device for determining a jitter buffer level|
A buffer level for jitter data buffer is determined. A frame payload size difference is determined for a plurality of video frames encoded into data packets sequentially received from a network.
|Methods and circuits for reducing clock jitter|
A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled.
|Signal processing apparatus and signal processing method thereof|
A signal processing apparatus which processes a voice packet is provided. The signal processing apparatus includes: a network jitter measurer which estimates network jitter using a weighting of a network jitter variance according to a network state, a compression and output unit which compresses or outputs a voice frame based on the estimated network jitter, and a loss concealer which divides a voice packet loss into short-term loss concealment and long-term loss concealment, and performs loss concealment in a different way depending on whether the voice packet loss is the short-term loss concealment or the long-term loss concealment..
|Method and apparatus to eliminate frequency holes in a memory i/o system|
Various methods and apparatus for managing signals between a processor and a memory device are disclosed. In one aspect, a method of managing signals between a processor and a memory device wherein the processor and the memory device are operatively coupled by a data signal path and a clock signal path is provided.
|Controller for generating jitters in a constant current mode of a power converter and method thereof|
A controller for generating jitters in a constant current mode of a power converter includes a current pin, an auxiliary pin, a constant current control unit, and a control signal generation unit. The current pin is used for receiving a primary side voltage determined according to a resistor and a primary side current flowing through the power converter.
|Method and system for improving audio fidelity in an hdmi system|
Hdmi is a digital audio and video communications protocol commonly used in consumer electronics. Hdmi is particularly synonymous with high fidelity audio and video.
|System and method for object tracking anti-jitter filtering|
Object tracking anti-jitter filtering systems and methods. A plurality of raw location points for a tracking tag attached to a tracked object is received.
|Implementing compact current mode logic (cml) inductor capacitor (lc) voltage controlled oscillator (vco) for high-speed data communications|
A method and a phase locked loop (pll) circuit for implementing compact current mode logic inductor capacitor voltage controlled oscillator for high speed communications, and a design structure on which the subject circuit resides are provided. The pll circuit includes a current mode logic (cml) inductor capacitor (lc) voltage controlled oscillator (vco).
|Selectable phase or cycle jitter detector|
Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements.
|High precision synchronized measured value acquisition|
The invention relates to a method for wire bound, high precision, temporal synchronization of measured value acquisition in a measurement system designed as a space coordinate measurement apparatus having a plurality of measurement sub-units with signaling of a time for triggering the measured value acquisition by means of a trigger signal and with the respective acquisition and intermediate storage of a measured value in the measurement sub-unit at the time determined by the trigger signal. Each acquisition of the measured value is carried out in the measurement sub-units in a time quantified manner with a local timing signal of the measurement sub-unit.
|Delay and jitter limited wireless mesh network scheduling|
Schedule and channel assignment in a wireless mesh network (wmn) includes: forming a representation of a sequence of permutation matrices from an n×n rate matrix. The entries of the rate matrix define the bandwidth of links between nodes of the wmn.
|Method and system for an audio pipeline architecture|
Described are the architecture of such a system, algorithms for time synchronization during a multiway conferencing session, methods to fight with network imperfections such as jitter to improve synchronization, methods of introducing buffering delays to create handicaps for players with faster connections, methods which help players with synchronization (such as a synchronized metronome during a music conferencing session), methods for synchronized recording and live delivery of synchronized data to the audience watching the distributed interaction live over the internet.. .
|Method for reducing execution jitter in multi-core processors within an information handling system|
A method of reducing execution jitter includes a processor having several cores and control logic that receives core configuration parameters. Control logic determines if a first set of cores are selected to be disabled.
|Method of establishing an oscillator clock signal|
A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component.
|Digitally controlled jitter injection for built in self-testing (bist)|
A digitally controlled jitter injection apparatus for built in self-testing includes a transceiver circuit having a transmitter circuit and a receiver circuit. The digitally controlled jitter injection apparatus also includes a generator that generates a composite jitter including multi-tone jitter components.
|Jitter tolerant receiver|
An embodiment of the invention includes a receiver with reduced error terms and incoming jitter tracking that improves jitter tolerance. An embodiment provides these benefits based on a voltage integrator that recovers data and clock information from incoming signals without use of a pll, pi, cdr, and the like.
|Laser swept source with controlled mode locking for oct medical imaging|
An optical coherence analysis system uses a laser swept source that is constrained to operate in a mode locked condition. This is accomplished by synchronously changing the laser cavity's gain and/or phase based on the round trip travel time of light in the cavity.
|Stereoscopic spectacles control device, display device, and stereoscopic spectacles control method|
A phase error detection unit measures a phase error between an external synchronization signal and a spectacles control signal that is fed back, more specifically, a discrepancy between vertical synchronization timing and shutter opening/closing timing, that is, jitter. A timing correction unit corrects the shutter opening/closing timing, using the measured jitter.
|Nesting using rigid body simulation|
Embodiments of the invention provide systems and methods for nesting objects in 2d sheets and 3d volumes. In one embodiment, a nesting application simplifies the shapes of parts and performs a rigid body simulation of the parts dropping into a 2d sheet or 3d volume.
|Systems and methods for assessing jitter buffers|
A system having one or more processors and a memory, sends a plurality of test audio packets at a level of signal complexity deviating from a model level of signal complexity to a destination device through one or more networks. The system then receives a response to the plurality of test audio packets, where the response is indicative of a value for a quality of service characteristic associated with the one or more networks, and where the value for the quality of service characteristic is determined by how the plurality of test audio packets deviate from the model level of signal complexity when received by a remote device.
|Prediction-based touch contact tracking|
When an external object approaches or touches a touch sensor, predicted locations of the external object can be generated by detected locations according to signals from the touch sensor. The latest predicted location is shifted backwards towards the latest reported location for a portion of the distance between the predicted location and the latest reported location to generate a new reported location, whereby jittering of the reported locations caused by noise in the signals of the touch sensor can be reduced or filtered..
|Jitter suppression in type i delay-locked loops|
In one embodiment, a delay-locked loop (dll) for synchronizing a phase of a periodic digital output signal with a phase of a periodic digital input signal includes a deskew element responsive to the periodic digital input signal to the dll and the periodic digital output signal from the dll for suppressing jitter in the periodic digital output signal by synchronizing transitions in the periodic digital output signal with transitions in the periodic digital input signal and generating a final jitter-suppressed periodic digital output signal.. .
|Phase-locked loop with loop gain calibration, gain measurement method, gain calibration method and jitter measurement method for phase-locked loop|
The invention provides a phase-locked loop with loop gain calibration and methods for measuring an oscillator gain, gain calibration and jitter measurement for a phase-locked loop. The method for measuring an oscillator gain of a phase-locked loop includes the steps of providing a varying code at an input end of the oscillator; outputting excess reference phase information by a reference phase integral path and outputting excess feedback phase information based on the varying code by a feedback phase integral path; and obtaining an estimated gain information of the oscillator based on the excess reference phase information and the excess feedback phase information..
|System and method for seed laser mode stabilization|
A method and apparatus for stabilizing the seed laser in a laser produced plasma (lpp) extreme ultraviolet (euv) light system are disclosed. In one embodiment, the cavity length of the laser may be adjusted by means of a movable mirror forming one end of the cavity.
|Adaptive jitter buffer management for networks with varying conditions|
An apparatus and method for detecting and analyzing spikes in network jitter and the estimation of a jitter buffer target size is disclosed. Detected spikes may be classified as jump spikes or slope spikes, and a clipped size of detected spikes may be used in the estimation of the jitter buffer target.
|Timing calibration for on-chip interconnect|
One embodiment sets forth a timing calibration technique for on-chip source-synchronous, complementary metal-oxide-semiconductor (cmos) repeater-based interconnect. Two transition patterns may be applied to calibrate the delay of an on-chip data or clock wire.
|System and method for frequency multiplier jitter correction|
A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency.
|Methods and structure for on-chip clock jitter testing and analysis|
Methods and structure for on-chip self-test of clock jitter for an application clock signal generated within an integrated circuit (ic). Features and aspects hereof provide for acquisition of samples of an application clock signal within the ic and counting the number of samples having a predetermined value.
|Sampling circuit, a/d converter, d/a converter, and codec|
An a/d converter comprising: a sampling circuit including a continuous section, a sampling and holding section for intermittently sampling an input signal based on an analog signal input from the continuous section to hold and transfer the sampled signal, and a digital section for outputting a signal transferred from the sampling and holding section as a digital signal; and a control circuit for supplying a clock signal in which jitter is not added to the continuous section and supplying a clock signal in which the jitter is added to the sampling and holding section.. .
|Phase locked loop|
A phase locked loop comprises a loop filter and a charge pump circuit. The loop filter comprises a parallel capacitor, a serial resistor and a serial capacitor.
|Video buffer management technique|
The video data buffering apparatus and associated methods provide audio and video data buffering in a video processing device. Specifically, the system relates to the use of a circular buffer and linked list fifo employed in a video processing system, wherein video data packets from multiple video streams are stored in a common buffer to compensate for transport packet jitter.