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Jitter

Jitter-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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NEW Digital phase locked loop for low jitter applications
International Business Machines Corporation
February 15, 2018 - N°20180048321

A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of ...
NEW Shielding real-time workloads from os jitter due to expedited grace periods
International Business Machines Corporation
February 15, 2018 - N°20180046521

A technique for shielding real-time workloads from operating system (os) jitter due to expedited read-copy update (rcu) grace periods. In accordance with the disclosed technique, a kernel parameter is set to indicate that expedited rcu grace periods are to be suppressed. The kernel parameter is checked to see if it is set. A normal non-expedited rcu grace period is invoked ...
NEW Shielding real-time workloads from os jitter due to expedited grace periods
International Business Machines Corporation
February 15, 2018 - N°20180046468

A technique for shielding real-time workloads from operating system (os) jitter due to expedited read-copy update (rcu) grace periods. In accordance with the disclosed technique, a kernel parameter is set to indicate that expedited rcu grace periods are to be suppressed. The kernel parameter is checked to see if it is set. A normal non-expedited rcu grace period is invoked ...
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Dejittering system
Vasona Networks Inc.
February 08, 2018 - N°20180042036

Described embodiments include a system that includes a network interface and a processor. The network interface is configured to receive, at a first time, a packet transmitted from a source communication terminal over a communication network en route to a target communication terminal, before the packet passes through a particular portion of the communication network, and to receive the packet ...
System and method of providing compression technique for jitter sensitive application through multiple network links
Citrix Systems, Inc.
February 08, 2018 - N°20180041439

An appliance for providing compression technique for jitter sensitive application through multiple network links is described. The appliance has one or more processors and includes a link quality estimator, a jitterless compressor, and a link switcher. The link quality estimator is configured to measure latency over a first link and a second link, wherein the second link has a longer ...
Cache friendly jittered hemispherical sampling
Thomson Licensing
February 08, 2018 - N°20180040155

An apparatus for use in producing lighting effects comprising a plurality of graphic processing units, each graphic processing unit for jittering a first ray, having a direction, to result in a second ray, the second ray having a direction not the same as the first ray; and each graphic processing unit having a plurality of threads for processing rays for ...
Jitter Patent Pack
Download 96+ patent application PDFs
Jitter Patent Applications
Download 96+ Jitter-related PDFs
For professional research & prior art discovery
inventor
  • 96+ full patent PDF documents of Jitter-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Method and apparatus for removing jitter in audio data transmission
Telefonaktiebolaget Lm Ericsson (publ)
January 25, 2018 - N°20180026746

In accordance with an example embodiment of the present invention, disclosed is a method and an apparatus thereof for removing jitter introduced by a packet switched network. Each received audio frame comprises a primary portion and a redundancy portion. The redundancy portion comprises a partial redundant copy of a previous frame that is offset by k frames. If a frame ...
Method of improving clock recovery and related device
Novatek Microelectronics Corp.
January 18, 2018 - N°20180019863

A method for a mobile industry processor interface (mipi) master device for improving clock recovery at a mipi slave device includes: transmitting a symbol sequence including a plurality of consecutive symbols which include at least one of a first symbol value and a second symbol value to the mipi slave device prior to transmitting packet data to the mipi slave ...
Systems and methods for reducing electromagnetic interference using switching frequency jittering
On-bright Electronics (shanghai) Co., Ltd.
January 18, 2018 - N°20180019664

System and method are provided for regulating a power converter. The system includes a signal processing component configured to receive a first input signal and a second input signal, process information associated with the first input signal and the second input signal, and output a drive signal to a switch based on at least information associated with the first input ...
Clock jitter measurement circuit and semiconductor device including the same
Samsung Electronics Co., Ltd.
January 11, 2018 - N°20180011142

A circuit for measuring clock jitter includes: an internal signal generator configured to generate an internal clock signal and a single pulse signal, respectively synchronized with an input clock signal; a plurality of delay units being connected in series with each other and configured to generate respective delayed clock signals; a plurality of latch circuits configured to latch the single ...
Facilitation of handover coordination based on voice activity data
At&t Mobility Ii Llc
January 04, 2018 - N°20180007595

A more efficient network can be achieved by leveraging an adaptive dejitter buffer. The dejitter buffer can be dynamically adjusted based off a network data analysis. A communication handover can be adjusted or shifted based on voice inactivity data related to a forecasted punctuation. The dejitter buffer memory/depth of a mobile device can also be adjusted in accordance with ...
Nesting using rigid body simulation
Autodesk, Inc.
January 04, 2018 - N°20180004871

Embodiments of the invention provide systems and methods for nesting objects in 2d sheets and 3d volumes. In one embodiment, a nesting application simplifies the shapes of parts and performs a rigid body simulation of the parts dropping into a 2d sheet or 3d volume. In the rigid body simulation, parts begin from random initial positions on one or more ...
Injecting cpu time jitter to improve entropy quality for random number generator
International Business Machines Corporation
January 04, 2018 - N°20180004486

Aspects of present disclosure relate to random number generator, a method and a computer program product of improving entropy quality of the random number generator. The method may include: receiving, at an input/output interface module of the random number generator, a request to generate a random number having a predetermined number of random bits, and starting a random bit ...
Jitter Patent Pack
Download 96+ patent application PDFs
Jitter Patent Applications
Download 96+ Jitter-related PDFs
For professional research & prior art discovery
inventor
  • 96+ full patent PDF documents of Jitter-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Method and system for transmission and low-latency real-time output and/or processing of an audio ...
Sennheiser Electronic Gmbh & Co. Kg
December 28, 2017 - N°20170374164

A method for transmission and low-latency real-time output and/or processing of an audio data stream that is transmitted from at least one transmitter to at least one receiver over a jittering transmission path. The method includes a calibration for determining a distribution of latencies in transmission of packets of the audio data stream, whereby a group of packets of ...
System and method for mtu size reduction in a packet network
Huawei Technologies Co., Ltd.
December 28, 2017 - N°20170373982

Systems and methods are disclosed that reduce the maximum transmission unit (mtu) size associated with an output port when a jitter sensitive packet flow utilizes the output port. This may reduce the amount of jitter introduced into the jitter sensitive packet flow. In one embodiment, a method includes transmitting packets through an output port. The output port has an mtu ...
Systems and methods for controlling isochronous data streams
Qualcomm Incorporated
December 28, 2017 - N°20170373881

Systems and methods for controlling isochronous data streams are disclosed. Particular aspects of the present disclosure are designed to be used with almost any isochronous data stream, but are well-suited for use with the universal serial bus (usb) protocol. Further, aspects of the present disclosure are flexible to accommodate existing configuration possibilities within the usb protocol as well as accommodate ...
Clock synchronizer and method of establishing an output clock
December 28, 2017 - N°20170373826

A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (tll) with an ...
Phase frequency detector and accurate low jitter high frequency wide-band phase lock loop
Circuit Seed ,llc
December 28, 2017 - N°20170373697

A novel phase locked loop design utilizing novel phase-frequency detector, charge pump, loop filter and voltage controlled oscillator is disclosed. The phase-frequency detector includes a dual reset d-flip flop for use in multi-ghz phase locked loops. Traditional dead zone issues associated with phase frequency detector are improved/addressed by use with a charge transfer-based pll charge pump.
Digital phase locked loop for low jitter applications
International Business Machines Corporation
December 28, 2017 - N°20170373695

A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of ...
Introducing jitter to a switching frequency by way of modulating current limit
Power Integrations, Inc.
December 28, 2017 - N°20170373589

A controller includes a switch controller coupled to a power switch coupled to an energy transfer element. The switch controller is coupled to receive a current sense signal representative of a drain current through the power switch. The switch controller is coupled to generate a drive signal to control switching of the power switch in response to the current sense ...
Fractional divider using a calibrated digital-to-time converter
Integrated Device Technology, Inc.
December 21, 2017 - N°20170364034

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a divided clock signal and a control signal in response to (i) an input clock signal and (ii) a configuration signal. The second circuit may be configured to generate an output clock signal in response to (i) the control signal and (ii) ...
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