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Jitter patents

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Date/App# patent app List of recent Jitter-related patents
 Method and a device for low intrusive fast estimation of the bandwidth available between two ip nodes patent thumbnailnew patent Method and a device for low intrusive fast estimation of the bandwidth available between two ip nodes
A method and a device are provided for estimating the bandwidth available at the level of the ip layer for a stream between a source node and a destination node connected by a path made up of one or more links. The stream is transported by a heterogeneous telecommunications network that may include at least one radio segment over a portion of the path.
 Method and  reducing jitters of video frames patent thumbnailnew patent Method and reducing jitters of video frames
A method for reducing the jitters of video frames is provided, which includes the steps of dividing a frame into multiple blocks, selecting at least one block according to a variance of each block, determining a global motion vector of the frame in a direction according to the selected block(s), and performing motion compensation on the frame in the direction according to the global motion vector.. .
 Equalization for high speed input/output (i/o) link patent thumbnailnew patent Equalization for high speed input/output (i/o) link
Described are systems and apparatuses to mitigate the timing margin loss caused by inter-symbol interference (isi) in high speed input/output (i/o) interfaces. Data dependent jitter (ddj) compensation techniques that may be utilized in the transmission or receiving circuitry of the i/o interface, including capturing bit data values of a data signal prior to an identified data transition, and delaying/advancing the transmission/reception the data signal or a corresponding clock signal based on these bit data values..
 Clock recovery using quantized phase error samples using jitter frequency-dependent quantization thresholds and loop gains patent thumbnailnew patent Clock recovery using quantized phase error samples using jitter frequency-dependent quantization thresholds and loop gains
A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a phase-adjusted clock and an input data signal.
 Hierarchical/lossless packet preemption to reduce latency jitter in flow-controlled packet-based networks patent thumbnailHierarchical/lossless packet preemption to reduce latency jitter in flow-controlled packet-based networks
Methods, apparatus, and systems for implementing hierarchical and lossless packet preemption and interleaving to reduce latency jitter in flow-controller packet-based networks. Fabric packets are divided into a plurality of data units, with data units for different fabric packets buffered in separate buffers.
 Clock and data recovery circuit patent thumbnailClock and data recovery circuit
A clock and data recovery (cdr) circuit employing zero-crossing linearizing (zcl) technique. The circuit including a voltage controlled oscillator (vco), an inject-locked divider (ild), a variable delay unit, a linearized loop, a bang-bang loop, and a loop filter (lp).
Fudan University
 Distortion measurement for limiting jitter in pam transmitters patent thumbnailDistortion measurement for limiting jitter in pam transmitters
Methods and test equipment for measuring jitter in a pulse amplitude modulated (pam) transmitter. Under one procedure, a first two-level pam signal test pattern is used to measure clock-related jitter separated into random and deterministic components, while a second two-level pam signal test pattern is used to measure oven-odd jitter (eoj).
Intel Corporation
 Efficient power supply noise measurement based on timing uncertainty patent thumbnailEfficient power supply noise measurement based on timing uncertainty
A power supply noise measurement device for inclusion with an integrated circuit, the integrated circuit having a functional block, the noise measurement device comprising: a signal generator configured to provide a clock signal to the functional block, an antenna comprising a transistor, and being located proximate to the functional block, the antenna being configured to receive the clock signal from the signal generator, and a jitter estimator configured to provide a measure of the relative jitter between a signal output from the antenna and a reference clock signal, wherein the transistor of the antenna receives electrical power from the same power source that delivers power to the functional block.. .
St-ericsson Sa
 Jitter buffer emulation for rtp streams in passive network monitoring systems patent thumbnailJitter buffer emulation for rtp streams in passive network monitoring systems
A method for emulating a jitter buffer by a telecommunications network monitoring probe includes determining an rtp timestamp for each of the plurality of received rtp packets. An actual time of arrival is determined for each of the plurality of rtp packets.
Tektronix, Inc.
 Minimizing symmetrical latency impact by jitter buffer for tdm ces patent thumbnailMinimizing symmetrical latency impact by jitter buffer for tdm ces
A method and system are provided for allowing time-alignment of teleprotection measurements of power signals. Teleprotection observations are communicated between teleprotection ends through a packet switched network.
Alcatel-lucent Canada Inc.

Techniques for reduced jitter in digital isolators

An apparatus for communicating using an isolation channel includes a transmitter circuit having a first terminal configured to communicate a first signal. The first signal oscillates in response to a data signal having a first signal level and is constant in response to the data signal having a second signal level.
Silicon Laboratories Inc.

Apparatus for reducing periodic jitter in a ring oscillator

Described is an apparatus which comprises: a first power supply node to provide power supply current; a ring oscillator, coupled to the first power supply node, to generate an oscillating output according to change in the power supply current provided to the ring oscillator; and a second power supply node; a circuit, coupled to the second power supply node, to replicate time-average (e.g., dc) behavior of the ring oscillator; and a feedback mechanism having inputs coupled to the first and second power supply nodes, and an output to control current in the circuit.. .

Image synchronization of scanning wafer inspection system

An inspection system comprises a beam generator module for deflecting spots across scan portions of a specimen. The system also includes detection channels for sensing light emanating from a specimen in response to an incident beam directed towards such specimen and generating a detected image for each scan portion.
Kla-tencor Corporation

Increasing an area from which reconstruction from a computer generated hologram may be viewed

A method of enlarging an observation window from which the reconstruction from a computer generated hologram (cgh) may be viewed, including reproducing a cgh, and shifting a location of an exit pupil or observation window of an optical system reproducing the cgh. A method of increasing a viewing angle from which the reconstruction from a computer generated hologram (cgh) may be seen, including producing a plurality of instances of a cgh, projecting each one of the instances in a different direction so that a first exit pupil of a first instance is close to a second exit pupil of a second instance.
Real View Imaging Ltd.

Low latency digital jitter termination for repeater circuits

A circuit for reducing jitter in a digital signal is provided, comprising a clock and data recovery stage operative to receive an input data signal and generate in response thereto a recovered data signal, a recovered clock signal, and an unfiltered interpolator code; a filter stage operative to receive the unfiltered interpolator code and generate in response thereto a filtered clock signal; and a memory component operative to receive the recovered data signal, the recovered clock signal, and the filtered clock signal; sample the recovered data signal using the recovered clock signal; store the resulting sampled bits; and generate an output data signal by selecting stored bits using the filtered clock signal.. .
Semtech Canada Corporation

Multi-tier quality of service wireless communications networks

The present disclosure pertains to improved communication quality of service (qos) in communication networks. Higher service tiers may guarantee that a specific vocoder or bit rate is used.
Privilege Wireless Llc

Method and offline switch mode power supply with dithered switching frequency

A circuit for use in a switched mode power supply comprising includes an integrated circuit, a transformer, a capacitor, a low voltage circuit and a current limiting resistor. The ic jitters the switching frequency of the switch based on a bias voltage of the integrated circuit.
Landis+gyr, Inc.

Video stabilisation with deblurring

Methods of processing a frame in a video sequence of digital images are described, the methods comprising: determining a global motion vector for the frame relative to a previous frame in the sequence; deriving a jitter function from the global motion vector, the jitter function comprising an estimate of undesired motion of the frame relative to the previous frame; determining whether the frame is blurred above a first predetermined threshold; and if so, stabilising the frame using the jitter function and applying a deblur function to the frame.. .
St-ericsson Sa

Frequency jitter circuit and method

An oscillator generates a clock signal according to a voltage, a current and a capacitance, and a frequency jitter circuit and method use a random number to modulate the voltage, the current or the capacitance, or a count value to modulate the capacitance, to jitter the frequency of the clock signal.. .

Internal jitter tolerance tester with an internal jitter generator

The internal accumulated jitter generator may include a prbs generator, a digital loop filter, an accumulator, and a gain controller. The accumulated jitter generator also may be replaced with the internal sinusoid jitter generator.

Method and 2d/3d switchable displaying

A method for 2d/3d switchable displaying includes: real-time detecting a 3d display area; when a change of the 3d display area is detected, calculating a gradient coefficient based on a number of frame of change and a rate of the change of the 3d display area; adjusting a 3d image area and a 3d grating area based on the calculated gradient coefficient; and performing a stereoscopic display by the adjusted 3d image area and the adjusted 3d grating area. When the 3d display area starts a change and ends the change, the 3d display area gradually is switched to be 2d display and switched to be 3d display respectively, so that a gradient visual effect is achieved, and the problems of viewing image jitter and 3d effect mistake caused by pixel arrangement and hardware control in the 3d display area being not synchronized can be avoided..
Superd Co. Ltd

Jitter mitigating phase locked loop circuit

Systems and methods for efficient jitter mitigation or removal from a gapped signal. A phase mitigation module is employed to generate discrete correction values for modifying phase error signals detected between a gapped signal and a feedback signal of the pll.
Applied Micro Circuits Corporation

Jitter buffer

Methods, transmitter, receiver and computer program product for transmitting or receiving data of a real-time communication event, the data being transmitted from the transmitter to a jitter buffer of the receiver. At least one processing parameter describing how data is to be processed for transmission from the transmitter to the jitter buffer in the real-time communication event is determined at the transmitter.
Microsoft Corporation

Adapting a jitter buffer

A receiver receives a first data stream and a second data stream from a transmitting device over a packet-based communication network, the first data stream being of a first media type (e.g. Audio) and the second data stream being of a second media type (e.g.
Microsoft Corporation

System clock jitter correction

A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency.
Iq-analog Corporation

On die jitter tolerance test

A system and method are disclosed for performing on die jitter tolerance testing. A set of clocks are generated based on an input signal.
Parade Technologies, Inc.

Digital frequency band detector for clock and data recovery

A frequency band estimator for use in a data receiver or the like to enhance sinusoidal jitter tolerance by the clock and data recovery device (cdr) in the receiver. The detector uses two moving-average filters of different tap lengths that receive a gain-controlled signal from within the cdr.
Lsi Corporation

Jitter determination of noisy electrical signals

A jitter analysis system includes an electronic circuit having a noisy electrical signal with jitter along a baseline of the signal. The jitter analysis system also includes a sampling unit coupled to the noisy electrical signal that provides waveform samples of the noisy electrical timing signal and a jitter detection unit coupled to the sampling unit that provides baseline crossings of the noisy electrical signal, wherein the baseline crossings are determined from a selection of the waveform samples proximate the baseline of the signal.
Nvidia Corporation

Mechanism for facilitating dynamic phase detection with high jitter tolerance for images of media streams

A mechanism for facilitating dynamic phase detection with high jitter tolerance for images of media streams is described. In one embodiment, a method includes calculating stability optimization of an image of a media stream based on a plurality of pixels of two or more consecutive frames relating to a plurality of phases of the image, calculating sharpness optimization of the image, and selecting a best phase of the plurality of phases based on the stability and sharpness optimization of the image.
Silicon Image, Inc.

Adaptive buffers for media players

A system and method relate to determining am initial buffer size associated with a buffer and modifying the initial buffer size when jitter is detected. The initial buffer size may be determined and modified based on a maximum initial buffer size, and the maximum initial buffer size may be determined based on delays associated with storing data to the buffer.
Verizon Patent And Licensing Inc.

Image forming apparatus

An image forming apparatus suppressing jitter from occurring includes an image carrier, and a developer carrier supplying a developer to the image carrier, wherein the developer carrier includes an elastic layer having a thickness of 2.5 mm or less and having an md-1 hardness of 40 degrees or more.. .
Oki Data Corporation

Apparatus, system, and improving equalization with a software equalization algorithm

A system and method consistent with the present disclosure includes determining a jitter tolerance of a particular lane of a communication link corresponding to each of a plurality of equalization coefficients. Further, determining a particular equalization coefficient of the plurality of equalization coefficients that provides a maximum jitter tolerance.

Adjusting a jitter buffer based on inter arrival jitter

This disclosure relates to adjusting a jitter buffer at a wireless device based on inter-arrival-jitter (iaj). In one embodiment, an iaj value may be calculated for each of multiple received packets.
Apple Inc.

Clock and data recovery having shared clock generator

This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local cdr circuits, and associated cdr error signals are aggregated or otherwise combined.
Rambus Inc.

Dynamic object tracking for user interfaces

Systems and approaches provide for user interfaces (uis) that are based on object tracking. For example, the object may be a user's head or face.
Amazon Technologies, Inc.

Systems, devices and methods for tracking objects on a display

Systems, devices and methods for improved tracking with an electronic device are disclosed. The disclosures employ advanced exposure compensation and/or stabilization techniques.
Qualcomm Incorporated

Data processing

In a telecommunications network including at least a user device and a network node separated by at least a packet-switched part of the telecommunications network, the user device including a primary jitter buffer having a constant packet play-out rate, the network node including a secondary jitter buffer, incoming packets destined for the user device are received and passed through the secondary jitter buffer of the network node downstream towards the primary jitter buffer of the user device. The departure times of packets passing through the secondary jitter buffer of the network node downstream towards the primary jitter buffer of the user device are monitored.
Metaswitch Networks Ltd

Systems and methods of improving the quality of voip communications

Methods of addressing problems in a voice over internet protocol (voip) telephony system include collecting data on network events, analyzing the data, and taking corrective action when possible. If an ip telephony device is registering with the voip telephony system more frequently than necessary, which can indicate the ip telephony device is unnecessarily jumping between proxy services, the ip telephony device is instructed to re-initialize itself.
Vonage Network, Llc

Method and suppressing a deterministic clock jitter

A method for generating an output clock comprising: detecting a timing difference between a first input clock and a second input clock to generate a phase error signal; generating a masked phase error signal by masking the phase error signal based on a deterministic jitter indicator signal; generating an oscillator control signal by filtering the masked phase error signal; and generating the output clock in accordance with the oscillator control signal.. .
Realtek Semiconductor Corp.

Crystal oscillator circuit having low power consumption, low jitter and wide operating range

A crystal oscillator circuit includes: a crystal resonator circuit, generating an oscillation signal; an inverting amplification circuit, whose first amplifier input end is coupled to receive the oscillation signal, in which an inverting amplifier outputs an inverting amplified output signal; a bias circuit, having a bias circuit input end and a bias circuit output end, in which the bias circuit output end generates a bias circuit output signal controlled by the bias circuit input end, and the bias circuit output signal is coupled to a second amplifier input end; and a peak detection circuit, comparing the inverting amplified output signal with a reference signal, regulating a peak detector output signal, and feeding the peak detector output signal into the bias circuit input end, in which the bias circuit includes a self-adjusting circuit, for isolating a power supply from a second input end of the inverting amplifier.. .
Capital Microelectronics Co., Ltd.

Waveform conversion circuit with reduced jitter

An ac-inverting amplifier for a waveform conversion circuit includes a first mos transistor of a first conductivity type having a gate that receives an input signal, a drain that provides an inverted amplified output signal, and a source coupled to a first power supply voltage. A current source provides a first bias current and a second bias current in proportion to the first bias current.

Ethernet carrier group alarm (cga)

Novel tools and techniques for providing network state information to customer equipment. In some embodiments, an operations, administration, and management (“oam”) server might determine a status of a network connection between at least two network devices, might generate state information indicating the determined status of the network connection, and might send the state information to one or more customer equipment, using in-band signaling over a band between the at least two network devices.
Centurylink Intellectual Property Llc

Methods and circuits for reducing clock jitter

A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled.
Rambus Inc.

Clock spurs reduction technique

Aspects of the disclosure provide a circuit having a jittered clock generator. The jittered clock generator is configured to add jitter of a controlled characteristic to a first clock signal of a clock frequency to generate a second clock signal to be used by a transceiver for operating at a radio frequency.
Marvell World Trade Ltd

Synchronization processing device, synchronization processing method, and program

The present technology relates to a synchronization processing device, a synchronization processing method, and a program, which make it possible to achieve frequency synchronization in a shorter period of time. A jitter amount calculation unit calculates a jitter amount on the basis of a synchronization packet containing time information.
Sony Corporation

Voice communication method and apparatus and operating jitter buffer

Voice communication method and apparatus and method and apparatus for operating jitter buffer are described. Audio blocks are acquired in sequence.
Dolby Laboratories Licensing Corporation

Controller for generating jitters in a quasi resonant mode and generating jitters in a quasi resonant mode

A controller for generating jitters in a quasi resonant mode includes a feedback pin, a voltage generation unit, a pulse generator, and a comparator. The feedback pin is used for receiving a feedback voltage from a secondary side of a power converter.
Leadtrend Technology Corp.

Jitter-based transmission control method

A jitter-based transmission control method is disclosed. In the jitter-based transmission control method, several packets are sent applying a current congestion window size by at least one sender device through a network switch device.
National Central University

Fast motion detection with gpu

Disclosed are systems and methods for determining when to focus a digital camera to capture a scene. A current frame and a prior frame are differenced to determine a frame difference.
Motorola Mobility Llc

System and efficient post-processing video stabilization with camera path linearization

Described herein are methods, systems, and apparatus to process video images to remove jitteriness due to hand shake. In one aspect, a camera is configured to capture raw video composed of a series of successive image frames of a scene of interest.
Qualcomm Incorporated

System clock jitter correction

A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency.
Q-analog Corporation

High-speed low-jitter communication system

Communication apparatus and techniques, such as for optical communication, can include providing a reference frequency derived from an atomic energy level transition or a molecular energy level transition, generating at least two specified optical carrier signals at least in part using the reference frequency, coherently modulating the specified optical carrier signals using respective baseband information signals to provide respective coherently-modulated optical subcarriers. A combined optical information signal comprising the optical subcarriers can be transmitted to a receiver, such as via a fiber optic cable.
Raytheon Company

Frequency multiplier jitter correction

A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency.
Iq-analog Corporation

Method and system for synchronizing positron emission tomography (pet) detector modules

A detector module (50) for a positron emission tomography (pet) system (10) includes an optical transceiver (66) receiving an optical data stream from a pet processing system (48). The data stream includes a pulse train carrying a command to generate sync/reset pulses.
Koninklijke Philips N.v

Swept source optical coherence tomography and stabilizing phase thereof

In an embodiment, a computer 16, which generates tomographic images based on spectral interference signals detected by a light detector 15 from overlaid reference light emitted by a swept-source type light source 2 of a ss-oct, split, and then reflected by a fixed reference mirror 8 on one hand and object light reflected by an object to be measured 6 on the other, is caused to function to apply rough correction using a first correction means and then apply detailed correction using a second correction means, to stabilize the phases of the ss-oct. The phases can be stabilized by eliminating, without adding any expensive, complex hardware, the jitter between the wavelength scanning of a light source of ss-oct and the timing of collecting the scan data with the light detector as spectral interference signals..
University Of Tsukuba

Clock jitter and power supply noise analysis

Disclosed are a method, system, and/or apparatus to perform clock jitter and power supply noise analysis. In one embodiment, a method may include receiving a first signal, which may be a clock signal, then generating a second signal based on the first signal.
Nvidia Corporation

Circuits for dynamically adaptive bit-leveling by sweep sampling with automatic jitter avoidance

A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device.
Uniquify, Inc.

Suppression of fixed-pattern jitter using fir filters

Fir filters for compensating for fixed pattern jitter, and methods of constructing the same, are disclosed. In one embodiment, a fir filter filters a signal having a desired frequency component, with the coefficients of the fir filter selected so that the filter is the equivalent of two combined fir filters, one having the desired frequency at the filter's peak output frequency, and a second in which the signal is delayed by a time equal to half of a period of a different frequency which is desired to be removed from the on signal.
Ess Technology, Inc.

Implementing a high quality voip device

A method is provided for voice over internet protocol (voip) devices to communicate over an internet protocol (ip) network. The method includes synchronizing the voip devices using one or more dual-tone multi-frequency (dtmf) codes over a telephone network, retransmissions of voice packets in bursts, retransmissions of voice packets following a time lag, adjusting the number of retransmissions based on quality of service, retransmission of a missing voice packet identified in a list received from a peer device, discarding low energy voice frames in a jitter buffer to prevent overflow, stopping playout at a low energy voice frame when the jitter buffer is below a minimum buffer size, and selective transmission and retransmission of voice packets based on their energy levels..
Arcsoft (shanghai) Technology Company, Ltd.

Beacon jitter prediction for wireless local area network (lan) devices

A method for activating a wireless communication device, the method may include receiving, by the wireless communication device, a sequence of periodic transmissions; estimating, for each periodic transmission of the sequence of periodic transmissions and before a reception of the periodic transmission, an expected time of arrival of the periodic transmission; calculating, for each periodic transmission, a timing difference attribute that is responsive to at least a difference between a timing of arrival of the periodic transmission and an expected time of arrival of the periodic transmission; selecting a selected periodic transmission out of the sequence of periodic transmissions, wherein the selected periodic transmission is associated with a smallest timing difference attribute out of the timing difference attributes associated with the periodic transmissions of the sequence of periodic transmissions; estimating, before a reception of a future periodic transmission that does not belong to the sequence of periodic transmissions, an estimated time of arrival of the future periodic transmission in response to the selecting of the selected periodic transmission and a periodic transmission period; determining a wakening time for wakening the wireless communication device in response to the estimated time of arrival of the future periodic transmission; and wakening the wireless communication device at the wakening time and searching for the future periodic transmission.. .
Dsp Group Ltd.

Frequency synthesis with gapper and multi-modulus divider

Systems and methods for frequency synthesis using a gapper and a multi-modulus divider. A frequency synthesizer may comprise a gapper, a multi-modulus divider and a phase locked loop (pll).
Applied Micro Circuits Corporation

Methods for dynamically adaptive bit-leveling by sweep sampling with automatic jitter avoidance

A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device.
Uniquify, Inc.

Interaction device corrective parameters

The techniques described herein are directed to receiving parameters directed to correcting spatial error and/or jitter associated with an interaction device connected to a computing device. In some instances, the parameters are encrypted parameters that may be decrypted and consumed to correct the spatial error and/or the jitter associated with the interaction device.
Microsoft Corporation

Method for estimating network jitter in transmitting coded media data

The present invention relates to a method for estimating network jitter, which has the effect of more precisely estimating network jitter by using time information corresponding to a transmission time, which is transmitted from a transport layer in a transmitting end to a receiving end.. .
Electronics And Telecommunications Research Institute

Enhancing jitter buffer performance through radio level feedback

A jitter buffer in a voice over lte receiver may be influenced by radio level feedback (rlf) from both local and remote endpoints to preemptively adjust the jitter buffer delay in anticipation of predicted future losses that have a high probability of occurring. The radio events of the rlf and the scenarios that trigger the preemptive adjustments may be identified, and their use may be expressed in terms of mathematical formulas.

Method and processing a video signal

Method, apparatus and computer program product for processing a video signal, the video signal comprising a plurality of frames, wherein the frames of the video signal are received at a jitter buffer, and the frames are output from the jitter buffer at a variable output rate to account for jitter in the received frames. Variations in the output rate are controlled in dependence upon the visual information content of the video signal, the visual information content of the video signal being the portion of the video signal that is to be displayed when the video signal is played out..

Audio playback method, apparatus and system

An audio playback method is provided. The method includes identifying a captured audio data frame according to a type of the audio data frame and sending the identified audio data frame to an audio receiving end.

Adaptive motion instability detection in video

Output video frames, which may be stabilized or non-stabilized, may then be stored to a memory. In certain embodiments, video motion instability is scored based on a probability distribution of video frame motion jitter values..

Allocation of shared resources for virtualized networking

Technology for allocating network adapter resources such as air interface time and queue space amongst multiple virtual network stations or other virtual adapters is disclosed. As one example, the resource allocation may be based on analysis of the relative latency, jitter, or bandwidth considerations for applications communicating via each of the multiple virtual adapters.

Communication method and communication apparatus

The present disclosure provides an orthogonal codes based code division multiplexing method of performing the code division multiplexing of demodulation reference signals in multiple layers of resource blocks by using orthogonal matrices, the method comprising: changing the order of chips in particular rows of a first orthogonal matrix to obtain a second orthogonal matrix with the changed order of chips; and multiplying the chips in respective rows of the second orthogonal matrix by the demodulation reference signals in corresponding layers of resource blocks correspondingly in the time direction to obtain code division multiplexing signals. The technical scheme of the present disclosure can improve the power jitter situation of downlink signals on the time, thereby the usage efficiency of the power amplifier at the base station side can be improved..

System and suppressing jitter in digital data signals including image, video and audio data signals

A system and method for suppressing jitter in a digital data signal in a signal processor system. The digital data signal has spaced apart byte allocation units wherein such spacing is increased such that unallocated bytes can be identified and removed from the digital data signal.

Method and source-synchronous signaling

A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (milo) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the milo clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals..

Popular terms: [SEARCH]

Jitter topics: Duty Cycle Correction, Differential Amplifier, Duty Cycle, Frequency Detector, Photosensitive Drum, Simulation, Cell Phone, Data Packet, Mean Opinion Score, Network Communication, Signal Processing, Sequencing, Transmitter, Asynchronous, High Performance Serial Bus

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