|| List of recent Ion Implant-related patents
|Methods of forming semiconductor devices with metal silicide using pre-amorphization implants and devices so formed|
A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (pai) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region.
|Method for manufacturing soi wafer|
The present invention is directed to a method for manufacturing an soi wafer, the method by which treatment that removes the outer periphery of a buried oxide film to obtain a structure in which a peripheral end of an soi layer of an soi wafer is located outside a peripheral end of the buried oxide film, and, after heat treatment is performed on the soi wafer in a reducing atmosphere containing hydrogen or an atmosphere containing hydrogen chloride gas, an epitaxial layer is formed on a surface of the soi layer. As a result, there is provided a method that can manufacture an soi wafer having a desired soi layer thickness by performing epitaxial growth without allowing a valley-shaped step to be generated in an soi wafer with no silicon oxide film in a terrace portion, the soi wafer fabricated by an ion implantation delamination method..
|Method for manufacturing semiconductor device|
It is an object to provide a highly reliable semiconductor device, a semiconductor device with low power consumption, a semiconductor device with high productivity, and a method for manufacturing such a semiconductor device. Impurities left remaining in an oxide semiconductor layer are removed without generating oxygen deficiency, and the oxide semiconductor layer is purified to have an extremely high purity.
|Isolated through silicon via and isolated deep silicon via having total or partial isolation|
Disclosed are a structure for improving electrical signal isolation in a semiconductor substrate and an associated method for the structure's fabrication. The structure includes a deep trench having sidewalls disposed in the semiconductor substrate.
|A non-uniform lateral profile of two-dimensional electron gas charge density in type iii nitride hemt devices using ion implantation through gray scale mask|
A high electron mobility field effect transistor (hemt) includes a two dimensional electron gas (2deg) in the drift region between the gate and the drain that has a non-uniform lateral 2deg distribution that increases in a direction in the drift region from the gate to the drain.. .
|Excited gas injection for ion implant control|
An ion source includes an ion chamber housing defining an ion source chamber, the ion chamber housing having a side with a plurality of apertures. The ion source also includes an antechamber housing defining an antechamber.
|Reversible acute occlusion implant, delivery catheter and method|
A permanent reversible acute occlusion implantable device and method are described for immediate occlusion of a body lumen, such as the fallopian tubes of the human female, but which can be reopened when necessary at a later date.. .
|Insertion tools and methods for an electrical stimulation implant|
In some embodiments, a method includes inserting at least a distal end portion of an insertion tool within a body. The distal end portion of the insertion tool is coupled to an electronic implant having a stimulation portion, a terminal portion and a substantially flexible conductor disposed between the stimulation portion and the terminal portion.
|Silicon carbide semiconductor device and manufacturing method therefor|
In the manufacture of a silicon carbide semiconductor device having a termination region being a jte region or flr, the margin of the amount of etching for removing a damage layer formed in the surface of the termination region is enlarged. A silicon carbide semiconductor device has a termination region being a jte (junction termination extension) region or an flr (field limiting ring) at a termination of the semiconductor elements.
|Method of manufacturing a semiconductor device|
A method of manufacturing a semiconductor device, which comprises: providing a semiconductor substrate; forming a dummy gate structure and a spacer surrounding the dummy gate structure on the semiconductor substrate; forming source/drain regions on both sides of the gate structure within the semiconductor substrate using the dummy gate structure and the spacer as a mask; forming an interlayer dielectric layer on the upper surface of the semiconductor substrate, the upper surface of the interlayer dielectric layer being flush with the upper surface of the dummy gate structure; removing at least a part of the dummy gate structure so as to form a trench surrounded by the spacer; performing tilt angle ion implantation into the semiconductor substrate using the interlayer dielectric layer and spacer as a mask so as to form an asymmetric halo implantation region; sequentially forming a gate dielectric layer and a metal gate in the trench. The present invention prevents the halo implanted ions from entering into the source/drain regions, thus reducing the source/drain junction capacitance; and the asymmetric halo implantation region can reduce the static power dissipation of the semiconductor device..
|Copper interconnect structure and its formation|
A structure with improved electromigration resistance and methods for making the same. A structure having improved electromigration resistance includes a bulk interconnect having a dual layer cap and a dielectric capping layer.
|Substrate diode formed by angled ion implantation processes|
A substrate diode device having an anode and a cathode includes a doped well positioned in a bulk layer of an soi substrate. A first doped region is positioned in the doped well, the first doped region being for one of the anode or the cathode, the first doped region having a first long axis and a second doped region positioned in the doped well.
|High electron mobility transistors and methods of manufacturing the same|
According to example embodiments, high electron mobility transistors (hemts) may include a discontinuation region in a channel region. The discontinuation region may include a plurality of 2deg unit regions that are spaced apart from one another.
|Bulk metallic glass feedstock with a dissimilar sheath|
Described herein is a feedstock including a core comprising bmg and a sheath attached the core. The sheath has a different physical property, a different chemical property or both from the core.
|Interposition implants for the hand|
An implant couples a first bone of a hand to a second bone of the hand. The implant includes a body that defines a median plane.
|Methods of forming semiconductor devices with embedded semiconductor material as source/drain regions using a reduced number of spacers|
In one example, a method disclosed herein includes the steps of forming a gate structure for a first transistor and a second transistor above a semiconducting substrate, forming a liner layer above the gate structures and performing a plurality of extension ion implant processes through the liner layer to form extension implant regions in the substrate for the first transistor and the second transistor. The method further includes forming a first sidewall spacer proximate the gate structure for the first transistor and a patterned hard mask layer positioned above the second transistor, performing at least one etching process to remove the first sidewall spacer, the patterned hard mask layer and the liner layer, forming a second sidewall spacer proximate both of the gate structures and performing a plurality of source/drain ion implant processes to form deep source/drain implant regions in the substrate for the first transistor and the second transistor..
|Ion implantation method and ion implanter|
An ion implantation method and an ion implanter with a beam profiler are proposed in this invention. The method comprises setting scan conditions, detecting the ion beam profile, calculating the dose profile according to the detected ion beam profile and scan conditions, determining the displacement for ion implantation and implanting ions on a wafer surface.
|Protective cover for interbody fusion devices|
A protective cover prevents undesired leakage of materials out of a spinal implant. In one embodiment, the implant is a lateral interbody fusion implant that accommodates biologically active material to promote bone ingrowth.
|Dynamic and non-dynamic interspinous fusion implant and bone growth stimulation system|
An interspinous fusion device is described. The interspinous fusion device includes a spacer member and an anchor member.
|Ion beam dimension control for ion implantation process and apparatus, and advanced process control|
A process control method is provided for ion implantation methods and apparatuses, to produce a high dosage area on a substrate such as may compensate for noted non-uniformities. In an ion implantation tool, separately controllable electrodes are provided as multiple sets of opposed electrodes disposed outside an ion beam.
|Method to tailor location of peak electric field directly underneath an extension spacer for enhanced programmability of a prompt-shift device|
A method to enhance the programmability of a prompt-shift device is provided, which reduces the programming time to sub-millisecond times, by altering the extension and halo implants, instead of simply omitting the same from one side of the device as is the case in the prior art prompt-shift devices. In one embodiment, no additional masks are employed.
|Method for making field effect transistor|
The present invention provides a method for making a field effect transistor, comprising of the following steps: providing a silicon substrate with a first type, forming a shallow trench by photolithography and etching processes, and forming silicon dioxide shallow trench isolations inside the shallow trench; forming by deposition a high-k gate dielectric layer and a metal gate electrode layer on the substrate and the shallow trench isolations; forming a gate structure by photolithography and etching processes; forming source/drain extension regions by ion implantation of dopants of a second type; depositing an insulating layer to form sidewalls tightly adhered to the sides of the gate; forming source/drain regions and pn junction interfaces between the source/drain region and the silicon substrate by ion implantation of dopants of the second type; and performing microwave annealing to activate implanted ions. The novel process of making a field effect transistor in the present invention can achieve impurity activation in the source/drain area at a low temperature and can reduce the influence of source/drain annealing on high-k gate dielectric and metal gate electrode..
|Method for manufacturing reverse-blocking semiconductor element|
In a method of manufacturing a reverse-blocking semiconductor element, a tapered groove is formed and ions are implanted into a rear surface and the tapered groove. Then, a furnace annealing process and a laser annealing process are performed to form a rear collector layer and a separation layer on the side surface of the tapered groove.
|Doped core trigate fet structure and method|
Techniques for fabricating a field effect transistor (fet) device having a doped core and an undoped or counter-doped epitaxial shell are provided. In one aspect, a method of fabricating a fet device is provided.
|Enhancement mode iii-nitride transistors with single gate dielectric structure|
According to one embodiment, a iii-nitride transistor includes a conduction channel formed between first and second iii-nitride bodies, the conduction channel including a two-dimensional electron gas. The transistor also includes at least one gate dielectric layer having a charge confined within to cause an interrupted region of the conduction channel and a gate electrode operable to restore the interrupted region of the conduction channel.
|Methods of forming self-aligned contacts for a semiconductor device|
One illustrative method disclosed herein involves forming gate structures for first and second spaced-apart transistors above a semiconducting substrate, forming an etch stop layer above the substrate and the gate structures, performing at least one angled ion implant process to implant at least one etch-inhibiting species into less than an entirety of the etch stop layer, after performing at least one angled ion implant process, forming a layer of insulating material above the etch stop layer, performing at least one first etching process to define an opening in the layer of insulating material and thereby expose a portion of the etch stop layer, performing at least one etching process on the exposed portion of the etch stop layer to define a contact opening therethrough that exposes a doped region formed in the substrate, and forming a conductive contact in the opening that is conductively coupled to the doped region.. .
|Methods of forming self-aligned contacts for a semiconductor device formed using replacement gate techniques|
One illustrative method disclosed herein involves forming an etch stop layer above a plurality of sacrificial gate structures, performing an angled ion implant process to implant an etch-inhibiting species into less than an entirety of the etch stop layer, and forming a layer of insulating material above the etch stop layer. The method further includes removing the sacrificial gate structures, forming replacement gate structures, forming a hard mask layer above the replacement gate structures and layer of insulating material, forming a patterned hard mask layer, performing another etching process through the patterned hard mask layer to define an opening in the layer of insulating material to expose a portion of the etch stop layer, performing another etching process on the exposed portion to define a contact opening therethrough that exposes a doped region and forming a conductive contact in the opening that is conductively coupled to the doped region..
|System and method for aligning substrates for multiple implants|
A system and method are disclosed for aligning substrates during successive process steps, such as ion implantation steps, is disclosed. Implanted regions are created on a substrate.
|Techniques for patterning multilayer magnetic memory devices using ion implantation|
A method of patterning a substrate includes providing a layer stack comprising a plurality of layers on a base portion of the substrate, where the layer stack includes an electrically conductive layer and a magnetic layer. The method further includes forming a first mask feature on an outer surface of the layer stack above a first protected region and a second mask feature on the outer surface of the layer stack above a second protected region, and directing ions towards the layer stack to magnetically isolate and electrically isolate the first protected region from the second protected region..
|Plasma potential modulated ion implantation system|
An ion implantation system including a plasma source, a mask-slit, and a plasma chamber. The plasma source is configured to generate a plasma within the plasma chamber in response to the introduction of a gas therein.
|Plasma potential modulated ion implantation apparatus|
An ion implantation apparatus including a first plasma chamber, a second plasma chamber and an extraction electrode disposed therebetween. The first and second plasma chambers configured to house respective plasmas in response to the introduction of a different feed gases therein.
|Expandable interbody fusion implant|
Disclosed is an expandable interbody fusion implant that is configured to have an initial configuration having a first footprint width suitable for being inserted into an intervertebral space and an expanded configuration having a second footprint width that is greater than the first footprint width. The implant may include a first body member and a second body member that is pivotally coupled to the first body member.
|Interbody fusion implant and related methods|
An implant for performing interbody fusion within a human spine, inserters for such an implant, and associated methodology. The implant is preferably formed in situ from at least two separate but lockable members (a base member and a closure member).
|Spinal facet augmentation implant and method|
A spinal facet joint implant suitable for minimally invasive implantation and capable of transitioning from a compact first configuration to an expanded second configuration is made of a swellable and compressible fluid absorbing polymer. The implant is dimensioned and configured, while in the first configuration, to fit within the lumen of a surgical needle.
|Stimulation of the amygdalohippocampal complex to treat neurological conditions|
A system and/or method treating for a neurological disorder by brain region stimulation. The system and/or method comprises a probe and a device to provide stimulation.
|Semiconductor device and method of fabricating the same|
A method of fabricating a semiconductor device includes performing pre-halo ion implantation on a semiconductor substrate, forming a first epitaxial layer over the entire upper surface of the semiconductor substrate, forming a second epitaxial layer over the entire surface of the first epitaxial layer, and forming a transistor at an active region of the second epitaxial layer. The first epitaxial layer prevents the ions implanted in the semiconductor substrate in the pre-halo implantation process from diffused into the second epitaxial layer under the effects of a process used to form the transistor..
|Apparatus for monitoring ion implantation|
An apparatus for monitoring an ion distribution of a wafer comprises a first sensor and a sensor. The first sensor, the second senor and the wafer are placed in an effective range of a uniform ion implantation current profile.
|Trenched semiconductor structure|
A trenched semiconductor structure comprises a semiconductor substrate, an epitaxial layer, an ion implantation layer, a termination region dielectric layer, an active region dielectric layer, and a first polysilicon layer. The epitaxial layer doped with impurities of a first conductive type is formed on the semiconductor substrate.
|Finfet non-volatile memory and method of fabrication|
A method of manufacturing a finfet non-volatile memory device and a finfet non-volatile memory device structure. A substrate is provided and a layer of semiconductor material is deposited over the substrate.
|System and method of ion beam source for semiconductor ion implantation|
An apparatus comprises an ionization chamber for providing ions during a process of ion implantation, and an electron beam source device inside the ionization chamber. The electron beam source device comprises a field emission array having a plurality of emitters for generating electrons in vacuum under an electric field..
|Methods of forming a fine pattern on a substrate and methods of forming a semiconductor device having a fine pattern|
The inventive concept provides methods of manufacturing semiconductor devices having a fine pattern. In some embodiments, the methods comprise forming an etch-target film on a substrate, forming a first mask pattern on the etch-target film, forming a second mask pattern by performing an ion implantation process in the first mask pattern, and etching the etch-target film using the second mask pattern..