|| List of recent Integrated Circuit-related patents
|Security within integrated circuits|
A method for hindering detection of information unintentionally leaked from a secret held in a memory unit is described, the method including receiving a triggering event waiting for at least a first amount of time to pass after the receipt of the triggering event, the memory unit being in a non-operational state during the at least a first amount of time after the at least a first amount of time has passed, changing at least one first condition under which the memory unit operates, thereby causing the memory unit to enter an operational state, waiting for a second amount of time to pass after the changing at least one first condition, and changing, after the second amount of time, at least one second condition under which the memory unit operates, thereby causing the memory unit to enter the non-operational state, wherein access to the secret information is enabled only during the second amount of time, and detection of secret information unintentionally leaked is limited during the first amount of time. Related apparatus and methods are also described..
|Method and device for reconstructing scan chains based on bidirectional preference selection in physical design|
Provided are methods and devices of organizing scan chains in an integrated circuit. One method comprises generating first preference information representing prioritized listing of a plurality of scanning elements for each of a plurality of scan chains based on a first criterion, generating second preference information representing prioritized listing of the plurality of scan chains for each of the plurality of scanning elements based on a second criterion and at a computing device, assigning each of the plurality of the scanning elements to one of the plurality of the scan chains based on the first preference information and the second preference information..
|Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperatures|
A method of optimizing power and timing for an integrated circuit (ic) chip, which uses an ic technology that exhibits temperature inversion, by modifying a voltage supplied to the ic chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges. A high voltage is selected that meets a closed timing analysis across a full temperature range to meet a timing performance and a low voltage is selected to meet the timing performance and the power performance across a lower temperature range to a temperature cut point in the higher temperature range.
|Power/performance optimization through temperature/voltage control|
A method of optimizing power and timing for an integrated circuit (ic) chip, identifies a plurality of valid temperature and voltage combinations that allow integrated circuit chips produced according to the integrated circuit chip design to operate within average power consumption goals and timing delay goals. Such a method selects temperature cut points from the valid temperature and voltage combinations for each of the integrated circuit chips, calculates a power consumption amount of each of the temperature cut points, and adjusts the temperature cut points based on the power consumption amount until the temperature cut points achieve the average power consumption goals.
|Structured latch and local-clock-buffer planning|
Latches and local-clock-buffers are automatically placed during integrated circuit physical synthesis. Prior to physically laying out the datapath, locations are assigned for the latches based on a logical representation of the datapath and on the fixed placements of pins.
|Early design cycle optimzation|
Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together.
|Techniques for electromigration stress determination in interconnects of an integrated circuit|
In one or more embodiments, one or more methods, processes, and/or systems described can determine stress failures in interconnect segments of integrated circuit designs and correct those failure via modifying the interconnect segments of the integrated circuit designs with one or more additions to the interconnect segments of the integrated circuit designs. Potentials can be received from a simulation, and one or more failures of an interconnect segment can be determined via the potentials from the simulation.
|Method and system for layout parasitic estimation|
A system comprises an electronic design automation (eda) tool, for generating a schematic design of an integrated circuit (ic), generating a layout from the schematic design, editing the layout, and verifying the schematic design and layout. At least one non-transitory, computer readable storage medium, is provided for storing data representing the schematic design and the layout, the layout having a network of routing paths connecting at least two active layer devices of the ic design.
|Techniques for checking computer-aided design layers of a device to reduce the occurrence of missing deck rules|
A technique for computer-aided design layer checking of an integrated circuit design includes generating a representation of a device (e.g., a parameterized cell). Computer-aided design (cad) layers are sequentially removed from the parameterized cell and a determination is made as to whether expected errors are detected or missed by an associated deck.
|Machine-learning based datapath extraction|
A datapath extraction tool uses machine-learning models to selectively classify clusters of cells in an integrated circuit design as either datapath logic or non-datapath logic based on cluster features. A support vector machine and a neural network can be used to build compact and run-time efficient models.
|Layout modification method and system|
A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (ic) layout, representing a set of photomasks for fabricating an ic having the ic layout such that the ic meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the ic layout, such that replacement of the proper subset of the first devices by second devices in a revised ic layout satisfies a second specification value different from the first specification value.
|Integrated circuit design method with dynamic target point|
The present disclosure provides one embodiment of an integrated circuit (ic) method. The method includes receiving an ic design layout having a pattern, assigning target points to segments of the pattern, and producing first a simulated contour of the pattern based on the assigned target points.
|Boundary scan path method and system with functional and non-functional scan cell memories|
An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells.
|Repair control circuit and semiconductor integrated circuit using the same|
A repair control circuit and a semiconductor integrated circuit using the same, which can reduce test time, are provided. The semiconductor integrated circuit includes a plurality of memory blocks in which a plurality of word lines are arranged, a plurality of word line drivers driving one or more of the plurality of word lines in response to a plurality of memory block selection signals, and a repair control circuit determining whether to perform a repair through comparison of repair addresses generated in response to surplus addresses and the plurality of memory block selection signals with external addresses..
|Apparatus and methods for activation of communication devices|
A method that incorporates teachings of the subject disclosure may include, for example, storing, by a universal integrated circuit card (uicc) including at least one processor, a digital root certificate locking a communication device to a network provider, and disabling an activation of the communication device responsive to receiving an indication of a revocation of the stored digital root certificate from a certificate authority, wherein the indication of the revocation of the stored digital root certificate is associated with a revocation of permission for an identity authority to issue a security activation information to the communication device on behalf of the network provide. Other embodiments are disclosed..
|Integrated circuit devices and methods for scheduling and executing a restricted load operation|
An integrated circuit device comprising at least one instruction processing module arranged to compare validation data with data stored within a target register upon receipt of a load validation instruction. Wherein, the instruction processing module is further arranged to proceed with execution of a next sequential instruction if the validation data matches the stored data within the target register, and to load the validation data into the target register if the validation data does not match the stored data within the target register..
|Methods and apparatus for efficient communication between caches in hierarchical caching design|
In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing efficient communication between caches in hierarchical caching design. For example, in one embodiment, such means may include an integrated circuit having a data bus; a lower level cache communicably interfaced with the data bus; a higher level cache communicably interfaced with the data bus; one or more data buffers and one or more dataless buffers.
|Method for determining coordinates|
A method for determining the coordinates of a point on the surface of an object is provided. A source system, such as an obirch system, is used to analyze and detect faults in an integrated circuit on a semiconductor die.
|Manufacturing control based on a final design structure incorporating both layout and client-specific manufacturing information|
Disclosed are embodiments of an improved design method, the results of which are a final design structure for an integrated circuit that incorporates, not only layout information, but also client-specific manufacturing information (e.g., import/export information, service requests, processing directives, purchase order requirements, design rule information, etc.) in the same data format in hierarchical form. Also disclosed are embodiments of a manufacturing control method and system.
|Apparatus and method for adaptive multimedia reception and transmission in communication environments|
The present invention provides a method and apparatus for configuration of adaptive integrated circuitry, to provide one or more operating modes or other functionality in a communication device, such as a cellular telephone, a gsm telephone, another type of mobile telephone or mobile station, or any other type of media communication device, including video, voice or radio, or other forms of multimedia. The adaptive integrated circuitry is configured and reconfigured for multiple tasks, such as channel acquisition, voice transmission, or multimedia and other data processing.
|Wireless control apparatus, wireless communication system, control program, and integrated circuit|
In sorm (spectrum-overlapped resource allocation), interference to other cells caused by an increase in transmit power of mobile station apparatuses is suppressed. A wireless control apparatus allows a plurality of wireless terminal apparatuses to locate transmit signals at part of frequencies in a system band in an overlapping manner, and determines frequencies at which the individual wireless terminal apparatuses locate transmit signals, so that an interference level of the entire system band is suppressed to be lower than or equal to a certain value.
|Portable data storage device|
A portable data storage device has a shell, an integrated circuit (ic) received in the shell, and a plug connecting with the ic. The plug includes an insulating housing partially extending out of the shell, a shield enclosing the insulating housing, and a number of contacts assembled to the insulating housing.
|Methods of forming a pattern in a material and methods of forming openings in a material to be patterned|
Methods of forming a pattern in a material and methods of forming openings in a material to be patterned are disclosed, such as a method that includes exposing first portions of a first material to radiation through at least two apertures of a mask arranged over the first material, shifting the mask so that the at least two apertures overlap a portion of the first portions of the first material, and exposing second portions of the first material to radiation through the at least two apertures. The first portions and the second portions will overlap in such a way that non-exposed portions of the first material are arranged between the first portions and second portions.
|Methods for fabricating integrated circuits having improved spacers|
Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a gate structure.
|Method for manufacturing semiconductor device|
A release layer formed over a substrate; at least one of thin film integrated circuits is formed over the release layer; a film is formed over each of the at least one of thin film integrated circuits; and the release layer is removed by using an etchant; thus, the at least one of thin film integrated circuits is peeled from the substrate. A semiconductor device is formed by sealing the peeled thin film integrated circuit by lamination or the like..
|Method for fabricating semiconductor components having lasered features containing dopants|
A method for fabricating semiconductor components includes the steps of providing a semiconductor substrate having a circuit side, a back side and integrated circuits and circuitry on the circuit side; thinning the substrate from the back side to a selected thickness to form a thinned substrate; applying a dopant to the back side of the thinned substrate; and laser processing the back side of the thinned substrate to form a plurality of patterns of lasered features containing the dopant. The dopant can be selected to modify properties of the semiconductor substrate such as carrier properties, gettering properties, mechanical properties or visual properties..
|Process for fabricating an integrated circuit having trench isolations with different depths|
A process for fabricating an integrated circuit includes, in a stack of layers including a silicon substrate overlaid with a buried insulating layer overlaid with a silicon layer, etching first trenches into the silicon substrate, depositing a silicon nitride layer on the silicon layer to fill the first trenches and form first trench isolations, forming a mask on the silicon nitride layer, etching second trenches into the silicon substrate, in a pattern defined by the mask, to a depth greater than a depth of the first trenches, filling the second trenches with an electrical insulator to form second trench isolations, carrying out a chemical etch until the silicon layer is exposed, and forming a fet by forming a channel, a source, and a drain of the field effect transistor in the silicon layer.. .
|Method of lithography process with an under isolation material layer|
A method of forming a integrated circuit pattern. The method includes forming gate stacks on a substrate, two adjacent gate stacks of the gate stacks being spaced away by a dimension g; forming a nitrogen-containing layer on the gate stacks and the substrate; forming a dielectric material layer on the nitrogen-containing layer, the dielectric material layer having a thickness t substantially less than g/2; coating a photoresist layer on the dielectric material layer; and patterning the photoresist layer by a lithography process..
|Integrated circuit device with well controlled surface proximity and method of manufacturing same|
An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device.
|Methods of forming a through via structure|
Methods of manufacturing an integrated circuit device including a through via structure are provided. The methods may include forming an isolation trench through a substrate to form an inner substrate, which is enclosed by the isolation trench and forming an insulating layer in the isolation trench and on a surface of the substrate.
|Post-deposition cleaning methods and formulations for substrates with cap layers|
One embodiment of the present invention is a method of fabricating an integrated circuit. The method includes providing a substrate having a metal and dielectric damascene metallization layer and depositing substantially on the metal a cap.
|Systems and methods for controlling electromagnetic interference for integrated circuit modules|
Systems and methods disclose reduction of conductive paint overspray while maintaining paint thickness uniformity over the perimeter of a cap encapsulating at least one integrated circuit (ic) module on a panel of ic modules. The layer of conductive paint electrically couples with wirebonds on the panel to form at least part of an electromagnetic interference (emi) or radio frequency interference (rfi) shield that attenuates emi or rfi during operation of the ic module.
|Systems and methods for providing electromagnetic interference shielding for integrated circuit modules|
Systems and methods disclose maintaining paint thickness uniformity over the surface of a cap encapsulating at least one integrated circuit (ic) module on a panel of ic modules. The layer of conductive paint electrically couples with wirebonds on the panel to form at least part of an electromagnetic interference (emi) or radio frequency interference (rfi) shield that attenuates emi or rfi during operation of the ic module.
|Low loss directional coupling between highly dissimilar optical waveguides for high refractive index integrated photonic circuits|
An optocoupler, an optical interconnect and method of manufacture providing same are provided for coupling an optical signal between a high refractive index waveguide of an integrated circuit and a waveguide external to the integrated circuit. The optocoupler includes a thinned high refractive index waveguide having a thickness configured to exhibit an effective refractive index substantially matching a refractive index of the external waveguide..
|Method and apparatus for protecting the transfer of data|
According to one embodiment, a method of descrambling digital multimedia content starts by sending an out-of-band request for encrypted control data to a headend. A descrambler integrated circuit may then receive digital program data in a scrambled format and the encrypted control data.
|Asynchronous sample rate converter for digital radio tuners|
Asrc may adjust the second sample rate in accordance with the feedback signal. The rf unit, the adc, and the asrc may be implemented on a single integrated circuit (ic)..
|Multi-channel code-division multiplexing in front-end integrated circuits|
A code-division multiplexing (cdm) system utilized in multi-channel (mc) front-end integrated circuits to significantly reduce the power consumption of such systems. The cdm system extends data compression advantages to uncorrelated and weakly correlated mc signals through the introduction of a new multi-channel signal binning and multiplexing (mcsbm) method and architecture.
|Semiconductor integrated circuit device|
A semiconductor integrated circuit device that detects an operation error of an sram caused by a device variation fluctuating with time is provided. In the sram, a memory cell has a transfer mos transistor whose gate is connected to a word line.
|Integrated circuit and apparatuses including the same|
An integrated includes a memory cell, a bit line connected to the memory cell, a boosting circuit to boost the bit line up to a boosting voltage during a pre-charge operation pre-charging the bit line, and a regulation circuit connected between the bit line and an output terminal and determines a logic level of the output terminal according to the voltage of the bit line.. .
|On-chip memory testing|
An integrated circuit is described that has a substrate with a memory array with dedicated support hardware formed on the substrate. An access wrapper circuit is coupled to address and data lines of the memory array and to control lines of the dedicated support hardware.
|Roic control signal generator|
A control signal generator to generate control signals for a readout integrated circuit (roic) includes a content addressable memory (cam) and a random access memory (ram). The cam may have data stored within it that is indicative of times at which control signal switching events are to occur during generation of the control signals.
|Haircutting shears with illuminated level|
The haircutting shears with illuminated level are adapted to aid a hairstylist in performing precise haircutting procedures. The shears are provided with a spirit level encased in an illuminated housing, which is disposed on the outer surface of one of the blades of the shears.
|Integrated circuit packaging system with heatsink cap and method of manufacture thereof|
A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an integrated circuit to the substrate; molding an encapsulation directly on the integrated circuit and the substrate; forming a trench in the encapsulation having a trench bottom surface and surrounding the integrated circuit; and mounting a heatsink having a heatsink rim over the integrated circuit with the heatsink rim within the trench and the heatsink electrically isolated from the substrate.. .