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Integrated Circuit

Integrated Circuit-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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Circuit board for cof package
Silicon Works Co., Ltd.
July 20, 2017 - N°20170208679

The present invention relates to a circuit board for cof (chip on film) package, which is capable of preventing an influence of coupling noise on a core block of an integrated circuit. The circuit board may include: a base film defined a core block region overlapping a predetermined location of a core block within an integrated circuit and having the ...
Integrated circuit for receiving and transmitting component carrier configuration information
Sun Patent Trust
July 20, 2017 - N°20170208593

Disclosed are a transmission device and a transmission method with which it is possible to prevent delays in data transmission and to minimize the increase in the number of bits necessary for the notification of a cc to be used, in cases where a cc to be used is added during communication employing carrier aggregation. When a component carrier is ...
Data packet processing system on a chip
Lantiq Beteiligun-grmbh & Co. Kg
July 20, 2017 - N°20170208015

An on-chip data packet processing method and corresponding integrated circuit, wherein data packets are received at an ingress port and processed with an on-chip wire-speed engine. The processing comprises adding metadata to the data packets, forwarding the processed data to an on-chip qos unit, altering the metadata of the data packets and/or providing further metadata to the data packets. ...
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Integrated circuit having a multiplying injection-locked oscillator
Rambus Inc.
July 20, 2017 - N°20170207791

Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the ...
Integrated circuit having a clock deskew circuit that includes an injection-locked oscillator
Rambus Inc.
July 20, 2017 - N°20170207790

Methods and apparatuses featuring an injection-locked oscillator (ilo) are described. In some embodiments, an ilo can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ilo can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to ...
Integrated circuit device and delay circuit device having varied delay time structure
Macronix International Co., Ltd.
July 20, 2017 - N°20170207777

An electronic circuit includes a forward delay circuit having a plurality of first stages. Each of the first stages is configured to introduce a delay time, the delay times of the first stages being varied. The electronic circuit further includes a control circuit coupled to the forward delay circuit, and a backward delay circuit coupled to the control circuit and ...
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Digital step attenuator
Peregrine Semiconductor Corporation
July 20, 2017 - N°20170207769

Digital step attenuator (dsa) configurations which are capable of handling high power signals, have low insertion loss and parasitic effects, have few or no glitches between state transitions, have minimal effect on chip area and power dissipation on an integrated circuit (ic) die (or “chip”), and provide flexibility of design for various applications. Embodiments utilize one ...
Dual port transimpedance amplifier with separate feedback
Honeywell International Inc.
July 20, 2017 - N°20170207760

A transimpedance amplifier circuit with an ac signal path and a dc bias path separate from the ac signal path that may be used with a wide variety of sensors such as mems accelerometers, photo detectors and pressure sensors. The circuit includes a high impedance input pseudo-resistor that minimizes the area needed on an integrated circuit and configured to minimize ...
E-fuse/switch by back end of line (beol) process
Renesas Electronics America Inc.
July 20, 2017 - N°20170207642

An apparatus and method for use in devices such as rechargeable battery packs. The apparatus, in one embodiment, includes an integrated circuit comprising a first circuit, a second circuit, and a thin film transistor (tft). The first circuit is configured to generate a square wave signal. The second circuit is configured to convert the square wave signal to a direct ...
3d photonic integration with light coupling elements
Biond Photonics Inc.
July 20, 2017 - N°20170207600

Methods for realizing integrated lasers and photonic integrated circuits on complimentary metal-oxide semiconductor (cmos)-compatible silicon (si) photonic chips, potentially containing integrated electronics, are disclosed. The integration techniques rely on light coupling with integrated light coupling elements such as turning mirrors, lenses, and surface grating couplers. Light is coupled from between two or more substrates using the light coupling elements. ...
Packaged devices with antennas
Apple Inc.
July 20, 2017 - N°20170207524

A packaged device may include electrical components such as integrated circuits that are mounted to a substrate such as a printed circuit substrate. Plastic may be molded to the printed circuit substrate over the integrated circuits. The molded plastic may include one or more shots of plastic and may include laser-sensitizable plastic material. Antenna structures may be supported by molded ...
Secondary battery
Lumimodule Optical Corporation
July 20, 2017 - N°20170207495

A secondary battery including: at least one first metal plate serving as a positive terminal; at least one second metal plate serving as a negative terminal; a separator material disposed between the at least one first metal plate and the at least one second metal plate for separating a positive terminal material on the at least one first metal plate ...
Rram device with data storage layer having increased height
Taiwan Semiconductor Manufacturing Co., Ltd.
July 20, 2017 - N°20170207387

The present disclosure relates to an integrated circuit, which includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a lower metal layer, an intermediate metal layer disposed over the lower metal layer, and an upper metal layer disposed over the intermediate metal layer. An upper surface of the lower metal layer and ...
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Integrated Circuit Patent Applications
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  • 3515+ full patent PDF documents of Integrated Circuit-related inventions.
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Wafer-level back-end fabrication systems and methods
Flir Systems, Inc.
July 20, 2017 - N°20170207271

Systems and methods may be provided for fabricating infrared focal plane arrays. The methods include providing a device wafer, applying a coating to the device wafer, mounting the device wafer to a first carrier wafer, thinning the device wafer while the device wafer is mounted to the first carrier wafer, releasing the device wafer from the first carrier wafer, singulating ...
Integrated circuits with high voltage and high density capacitors and methods of producing the same
Globalfoundries Singapore Pte. Ltd.
July 20, 2017 - N°20170207209

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a high voltage capacitor having a first high voltage plate, a second high voltage plate directly overlying the first high voltage plate, and a high voltage dielectric film between the first and second high voltage plates. The integrated circuit also includes a ...
Devices, packaged semiconductor devices, and semiconductor device packaging methods
Taiwan Semiconductor Manufacturing Company, Ltd.
July 20, 2017 - N°20170207197

Devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a device includes a first interconnect structure, a first integrated circuit die coupled to the first interconnect structure, and a second integrated circuit die disposed over and coupled to the first integrated circuit die. A second interconnect structure is disposed over the second integrated circuit ...
Integrated circuit structures with recessed conductive contacts for package on package
Intel Corporation
July 20, 2017 - N°20170207196

Disclosed herein are integrated circuit (ic) structures having recessed conductive contacts for package on package (pop). For example, an ic structure may include: an ic package having a first resist surface; a recess disposed in the first resist surface, wherein a bottom of the recess includes a second resist surface; a first plurality of conductive contacts located at the first ...
Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture
Micron Technology, Inc.
July 20, 2017 - N°20170207195

Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a semiconductor device package includes a plurality of package contacts and a semiconductor die having a plurality of first die bond pads, a plurality of second die bond pads, and a plurality of duplicate die bond pads having the ...
Backside contacts for integrated circuit devices
Taiwan Semiconductor Manufacturing Company, Ltd.
July 20, 2017 - N°20170207169

A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a transistor formed at a front side of the semiconductor substrate. A source/drain region of the transistor is disposed in the well region. A well pickup region is disposed in the well region, wherein the well pickup region is at a back side of the ...
Bridge interconnection with layered interconnect structures
Intel Corporation
July 20, 2017 - N°20170207168

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include ...
Method, apparatus, and system for offset metal power rail for cell design
Globalfoundries Inc.
July 20, 2017 - N°20170207165

At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device comprising an asymmetrically placed metal formation. A design for an integrated circuit device is received. The design comprises at least one functional cell. A first metal formation is placed asymmetrically about a first cell boundary of the functional cell for providing additional space for ...
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