|| List of recent Integrated Circuit-related patents
| Nonvolatile memory device having authentication, and methods of operation and manufacture thereof|
A memory device package encloses two separate die, one being a standard nonvolatile memory integrated circuit (“ic”) die, and the other being any suitable authentication ic die. Either die may be stacked upon the other, or the die may be placed side-by-side.
| Computer program product containing instructions for providing a processor the capability of executing an application derived from a compiled form|
An integrated circuit card is used with a terminal. The integrated circuit card includes a memory that stores an interpreter and an application that has a high level programming language format.
| Method and circuit to implement a static low power retention state|
An apparatus to pre-condition an operating integrated circuit (ic) device in a static low power retention state. The apparatus includes a pseudo random number generator that generates a pseudo random number value to pre-condition the static low power retention state of the operating ic device.
| Design optimization for circuit migration|
An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon.
| Integrated circuit designed and manufactured using diagonal minimum-width patterns|
An integrated circuit comprising a plurality of standard cell circuit elements is disclosed, wherein for at least one layer of the integrated circuit, a majority of minimum-width patterns are in a preferred diagonal orientation.. .
| Memory array with redundant bits and memory element voting circuits|
An integrated circuit may have an array of memory elements. Each memory element may have multiple memory cells.
| Parallel scan distributors and collectors and process of testing integrated circuits|
An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits.
| Semiconductor integrated circuit with bist circuit|
According to an embodiment, a semiconductor integrated circuit includes a memory, a bypass circuit, a first selection unit, a compression unit, and a comparison unit. The bypass circuit bypasses the test signal to output a bypass signal.
| Fault repair apparatus, fault repair method and storage medium storing fault repair program|
The fault repair apparatus according to an exemplary aspect of the invention includes, a detection unit that detects a fault in the integrated circuit being equipped with a memory storing configuration data (config-data), and a circuit element whose logic operation is defined by the config-data; and outputs fault information; a memory unit that memorizes a fault area specification table which correlates whether or not a description in the config-data related to the fault information exists in any of memory areas to identification information which identifies the memory area; a specification unit that specifies a failed memory area from the fault information and the fault area specification table; and a correction unit that, about the config-data stored in the failed memory area, detects and corrects error data which does not agree with an expected value.. .
| Method, apparatus and system for binding mtc device and uicc|
A method for binding a machine type communication (mtc) device and a universal integrated circuit card (uicc) is disclosed. The method includes: during a process of establishment of a shared key, a network application function (naf) acquires identity information of the mtc device and identity information of the uicc (101); the naf establishes a binding relationship between the mtc device and the uicc based on the identity information of the mtc device and the identity information of the uicc, and stores the binding relationship into a binding relationship table stored by the naf (102).
| Memory controller with clock-to-strobe skew compensation|
A clock signal is transmitted to first and second integrated circuit (ic) components via a clock signal line, the clock signal having a first arrival time at the first ic component and a second, later arrival time at the second ic component. A write command is transmitted to the first and second ic components to be sampled by those components at respective times corresponding to transitions of the clock signal, and write data is transmitted to the first and second ic components in association with the write command.
| Integrated circuit for computing target entry address of buffer descriptor based on data block offset, method of operating same, and system including same|
A method of operating an integrated circuit is provided. The method includes receiving a data block offset from a second storage device, obtaining a target entry address using the data block offset, and reading an entry among a plurality of entries comprised in a buffer descriptor stored in a first storage device based on the target entry address.
| Integrated circuit devices, systems and methods having automatic configurable mapping of input and/or output data connections|
Integrated circuit devices are disclosed with receive ports having mapping circuits automatically configurable to change a logical mapping of data received on receive-data connections. Automatic configuration can be based on a data value included within a received data set.
| Speech recognition device and method, and semiconductor integrated circuit device|
A semiconductor integrated circuit device for speech recognition includes a conversion candidate setting unit that receives text data indicating words or sentences together with a command and sets the text data in a conversion list in accordance with the command; a standard pattern extracting unit that extracts, from a speech recognition database, a standard pattern corresponding to at least a part of the words or sentences indicated by the text data that is set in the conversion list; a signal processing unit that extracts frequency components of an input speech signal and generates a feature pattern indicating distribution of the frequency components; and a match detecting unit that detects a match between the feature pattern generated from at least a part of the speech signal and the standard pattern and outputs a speech recognition result.. .
| Apparatus and method for improved optical detection of particles in fluid|
A number of fluidic-photonic devices for allowing optical detection, systems employing such devices, and related methods of operation and fabrication of such devices are disclosed herein. In at least some embodiments, the devices can serve as flow cytometry devices and/or employ microfluidic channels.
| Monitoring aging of silicon in an integrated circuit device|
A mechanism is provided for determining a modeled age of a mufti-core processor. For each core in a set of cores in the multi-core processor, a determination is made of a temperature, a voltage, and a frequency at regular intervals for a set of degradations and a set of voltage domains, thereby forming the modeled age of the multi-core processor.
| Testing system and method of inter-integrated circuit bus|
A testing system configured to test real-time signals of an i2c bus of a motherboard includes an oscillograph and a testing device. The motherboard comprises an i2c master control device and an i2c slave device connected to the i2c master control device by the i2c bus.
| Positioning apparatus, integrated circuit apparatus, electronic device and program|
A positioning apparatus 1 includes a first positioning unit 10 that performs first positioning processing that is performed based on a radio signal, an autonomous positioning sensor 20 that detects a state of the positioning apparatus 1, a second positioning unit 30 that performs second positioning processing that is performed based on an output of the autonomous positioning sensor 20, an attitude determining unit 40 that determines whether or not the attitude of the positioning apparatus 1 has been changed based on the output of the autonomous positioning sensor 20, and a control unit 50 that controls the first positioning unit 10. The control unit 50 performs control so as to cause the first positioning unit 10 to perform the first positioning processing if the attitude determining unit 40 determines that the attitude of the positioning apparatus 1 has been changed..
| Implantable shunt system and associated pressure sensors|
A hermetically sealed biocompatible pressure sensor module configured for implant at a desired site at which a pressure is to be measured. Anodic bonding of the pressure module package components which have similar thermal coefficients of expansion provides low stress bonding and maintains long term reliability, dependability and accuracy.
| Delta delay approach for ultrasound beamforming on an asic|
Systems are disclosed for ultrasound beamforming on an application specific integrated circuit (asic). In certain embodiments, the system includes an ultrasound probe that includes a plurality of transducer elements electrically coupled to an asic.
| Methods for coordinated signal reception across integrated circuit boundaries|
A wireless electronic device having first and second baseband processors is provided. In one suitable arrangement, radio-frequency power splitters and adjustable low noise amplifiers may be form in the receive paths.
| Shared filter for transmit and receive paths|
Shared filters used for both transmit and receive paths are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, or a circuit module) may include a filter and a switch.
| Methods of patterning small via pitch dimensions|
Integrated circuit methods are described. The methods include providing a photomask that includes two main features for two via openings and further includes an optical proximity correction (opc) feature linking the two main features; forming a hard mask layer on a substrate, the hard mask layer including two trench openings; forming a patterned resist layer over the hard mask layer using the photomask, wherein the patterned resist layer includes a peanut-shaped opening with two end portion aligned with the two trench openings of the hard mask layer, respectively; and performing a first etch process to the substrate using the hard mask layer and the patterned resist layer as a combined etch mask..
| Making an integtated circuit module with dual leadframes|
A method of making an integrated circuit module starts with a top leadframe strip comprising a plurality of integrally connected top leadframes. A plurality of flipchip dies are mounted on the top leadframe strip with solder bumps of each flipchip bonded to predetermined pad portions on each of the top leadframes.
| Packaged integrated circuit devices with through-body conductive vias, and methods of making same|
A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material.. .
| Wafer packaging method|
A wafer packaging method includes the following steps. A wafer having a plurality of integrated circuit units is provided.
| Positive tone organic solvent developed chemically amplified resist|
Provided is a method for developing positive-tone chemically amplified resists with an organic developer solvent having at least one polyhydric alcohol, such as ethylene glycol and/or glycerol, alone or in combination with an additional organic solvent, such as isopropyl alcohol, and/or water. The organic solvent developed positive tone resists described herein are useful for lithography pattern forming processes; for producing semiconductor devices, such as integrated circuits (ic); and for applications where basic solvents are not suitable, such as the fabrication of chips patterned with arrays of biomolecules or deprotection applications that do not require the presence of acid moieties..
| Differential thermistor circuit|
This document discusses, among other things, an apparatus and method for providing temperature information. In an example, an integrated circuit apparatus can include a first resistor configured to be coupled to a first terminal of a temperature-sensitive resistance, a second resistor configured to be coupled to a second terminal of the temperature-sensitive resistance, and a temperature information circuit configured to receive a first voltage from the first terminal of the temperature-sensitive resistance and a second voltage from the second terminal of the temperature-sensitive resistance.
| Apparatus and method for controlling transaction flow in integrated circuits|
Various embodiments of a method and apparatus for controlling transaction flow in a communications fabric is disclosed. In one embodiment, an ic includes a communications fabric connecting multiple agents to one another.
| Mobile station apparatus, communication system, communication method, and integrated circuit|
In a communication system including multiple mobile station apparatuses and at least one base station apparatus, the base station apparatus efficiently controls transmission of an uplink signal to the mobile station apparatuses. A path loss calculator calculates path loss on the basis of a reference signal received by a reception processing unit.
| Trench isolation implantation|
Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth of the dielectric material. Embodiments further include methods of fabricating the trench structures with the implant of energetic species to the predetermined depth.
| Insulating low signal loss substrate, integrated circuits including a non-silicon substrate and methods of manufacture of integrated circuits|
A microelectronic circuit having at least one component adjacent a carrier which is not a semiconductor or sapphire.. .
| Compact media player|
An electronic device such as a media player may be formed from electrical components such as integrated circuits, buttons, and a battery. Electrical input-output port contacts may be used to play audio and to convey digital signals.
| Semiconductor device, reticle method for checking position misalignment and method for manufacturing position misalignment checking mark|
According to one embodiment, there is provided a semiconductor device including a circuit area in which an integrated circuit is formed, a position misalignment checking mark of which a contrasting density is detected under polarized illumination and is not detectable under non-polarized illumination, and a peripheral pattern that is disposed on a periphery of the position misalignment checking mark and has a contrasting density that is not detectable under the polarized illumination.. .
| Integrated multi-channel analog front end and digitizer for high speed imaging applications|
A module for high speed image processing includes an image sensor for generating a plurality of analog outputs representing an image and a plurality of hdds for concurrently processing the plurality of analog outputs. Each hdd is an integrated circuit configured to process in parallel a predetermined set of the analog outputs.
| Semiconductor device controlling source driver and display device including the semiconductor device the same|
A semiconductor device includes: a transmitter transforming n data into first serial data and transmitting the first serial data through a first transmission line and transforming m data into second serial data and transmitting the second serial data through a second transmission line, where n and m are natural numbers at least one of which is greater than 1; a first driver integrated circuit (ic) group including n driver ics; and a second driver ic group including m driver ics, wherein each of the n driver ics receives the first serial data through the first transmission line and is driven by part of the first serial data, each of the m driver ics receives the second serial data through the second transmission line and is driven by part of the second serial data, and each of the n data and the m data includes identification information about a driver ic.. .
| Fuse circuit and semiconductor integrated circuit device|
Provided is a semiconductor integrated circuit device including a fuse circuit whose area and cost are minimized by a simple circuit configuration. The fuse circuit includes a first fuse and a second fuse having substantially the same shape and different sheet resistances, which are connected in series between terminals with different potentials.
| Amplifiers with multiple outputs and configurable degeneration inductor|
Multi-output amplifiers with configurable source degeneration inductance and having good performance are disclosed. In an exemplary design, an apparatus (e.g., a wireless device or an integrated circuit) includes a gain transistor and a configurable degeneration inductor for an amplifier.
| Synchronized charge pump-driven input buffer and method|
An integrated circuit includes (a) an analog-to-digital converter operated according to a first clock signal; and (b) a charge pump circuit providing a negative power supply voltage to the integrated circuit, the charge pump circuit being operated according to a second clock signal having a frequency that is different from a frequency of the first clock signal, such that a noise level introduced by the charge pump into the analog-to-digital converter is less than the average noise level over a predetermined range of frequencies for the second clock signal. The integrated circuit may further include a clock divider circuit (e.g., a programmable clock divider) that generates both the first clock signal and the second clock signal..
| On-die programming of integrated circuit bond pads|
Soc and sip designs are configured with an antifuse link within the die to allow on-die programming of bond wires connecting package lead fingers to the bond pads on the die. This permits alteration of the bond pad connections for the die, particularly for the ground voltage ground signal (vss) connections on the bond pad, at the testing stage after the die package and the power supply have been installed on the pcb.
| Semiconductor integrated circuit|
In a system in which the phases of a data clock signal and a data signal differ between at an input and at an output, a semiconductor integrated circuit performs a simple ber test without using external equipment and, at the same time, performs a jitter evaluation required for a margin evaluation.. .
| State machine for low-noise clocking of high frequency clock|
Methods, apparatus, and fabrication techniques relating to management of noise arising from capacitance in a clock tree of an integrated circuit. In some embodiments, the methods comprise receiving a signal to adjust a clock having a first rate to a second rate; and ramping, in response to receiving the signal, the clock from the first rate to the second rate, wherein the ramping comprises changing the frequency of the clock to at least one third rate between the first and second rates..
| Operational time extension|
Some embodiments provide a reconfigurable integrated circuit (“ic”). This ic has several reconfigurable circuits, each having several configurations for several configuration cycles.
| Socket device for an ic test|
Disclosed herein is a socket device for an integrated circuit (ic) test. The device includes: a socket which is provided with a pin guide plate that can guide and protect a spring contact so as to prevent damage to or breakage of the spring contact that electrically connects an ic lead to a pcb; and an ic insert provided with a guide plate.
| Semiconductor integrated circuit device|
A semiconductor integrated circuit device according to an embodiment includes at least one first transistor connected at its source to an input power supply line, connected at its drain to an output power supply line, and connected at its gate to a first control line, at least one second transistor connected at its source to the input power supply line, connected at its drain to the output power supply line, and connected at its gate to a second control line, a first buffer which drives the first control line, a second buffer configured to receive a control signal input via the first control line and drive the second control line, and a plurality of transfer gates provided to divide the first control line into a plurality of pieces, the plurality of transfer gates being capable of connecting pieces obtained by dividing the first control line.. .
| Bumpless build-up layer package with pre-stacked microelectronic devices|
The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (bbul) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package..
| Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects|
Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device.
| Integrated circuit interconnects and methods of making same|
A dielectric layer is formed on a substrate and patterned to form an opening. The opening is filled and the dielectric layer is covered with a metal layer.
| Integrated circuit (ic) having electrically conductive corrosion protecting cap over bond pads|
An integrated circuit (ic) die has a top side surface providing circuitry including active circuitry configured to provide a function, including at least one bond pad formed from a bond pad metal coupled to a node in the circuitry. A dielectric passivation layer is over a top side surface of a substrate providing a contact area which exposes the bond pad.
| Packaged semiconductor device|
A packaged semiconductor device includes a substrate including a first major surface, a second major surface, first vias running between the first major surface and the second major surface, first contact pads contacting the first vias at the first major surface, second contact pads contacting the first vias at the second major surface, and an opening between the first major surface and the second major surface. A first integrated circuit (ic) die is positioned in the opening in the substrate.
| Dual-flag stacked die package|
In one embodiment, a semiconductor package includes a first and a second die flag, wherein the first and second die flags are separated by a gap. First and second metal oxide semiconductor field effect transistor (mosfet) die are on the first and the second die flags, respectively.
| Ic package with stainless steel leadframe|
Various aspects of the disclosure are directed to integrated circuit (ic) die leadframe packages. In accordance with one or more embodiments, a stainless steel leadframe apparatus has a polymer-based layer that adheres to both stainless steel and ic die encapsulation, with the stainless steel conducting signals/data between respective surfaces for communicating with the packaged ic die.
| Information encoding using wirebonds|
A method and structure for encoding information on an integrated circuit chip. The method includes selecting a set of chip pads of the integrated circuit chip for encoding the information; encoding the information during a wirebonding process, the wirebonding process comprising forming ball bonds on chip pads of the integrated circuit chip and wedge bonds on leadframe fingers adjacent to one or more edges of the integrated circuit chip, the ball bonds and the wedge bonds connected by respective and integral wires; and wherein the information is encoded by varying one or more wirebonding parameters on each chip pad of the set of chip pads, the wirebonding parameters selected from the group consisting of the location of a ball bond, the diameter of a ball bond, both the location and diameter of a ball bond, the location of a wedge bond and combinations thereof..
| Thermal via for 3d integrated circuits structures|
A three dimensional integrated circuit (3d-ic) structure, method of manufacturing the same and design structure thereof are provided. The 3d-ic structure includes two chips having a dielectric layer, through substrate vias (tsvs) and pads formed on the dielectric layer.
| Three precision resistors of different sheet resistance at same level|
An integrated circuit contains three thin film resistors over a dielectric layer. The first resistor body includes only a bottom thin film layer and the first resistor heads include the bottom thin film layer, a middle thin film layer and a top thin film layer.
| Semiconductor device having electrode and manufacturing method thereof|
The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an electrode. An exemplary structure for a semiconductor device comprises a semiconductor substrate; an electrode over the semiconductor substrate, wherein the electrode comprises a trench in an upper portion of the electrode; and a dielectric feature in the trench..
| Channel doping extension beyond cell boundaries|
An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode.
| Integrated circuit with standard cells|
A die includes a plurality of rows of standard cells. Each of all standard cells in the plurality of rows of standard cells includes a transistor and a source edge, wherein a source region of the transistor is adjacent to the source edge.
| Capacitors comprising slot contact plugs and methods of forming the same|
An integrated circuit includes a semiconductor substrate, and an insulation region extending from a top surface of the semiconductor substrate into the semiconductor substrate. An inter-layer dielectric (ild) is overlying the insulation region.
| Display device|
A display device includes a substrate and a flexible circuit having one of its ends bonded to the substrate. The substrate comprises a pixel array.
| Displays with shared flexible substrates|
An electronic device may be provided with a display such as an organic light-emitting diode display. The display may include an array of display pixels formed on a polymer substrate layer.
| Integrated circuit devices and fabricating method thereof|
An integrated circuit device includes a first transistor having a first channel between a first source/drain, and a second transistor having a second channel between a second source/drain. The first transistor operates based on a first amount of current and the second transistor operates based on a second amount of current different from the first amount of current.
| Sealed infrared imagers|
The architecture, design and fabrication of array of suspended micro-elements with individual seals are described. Read out integrated circuit is integrated monolithically with the suspended elements for low parasitics and high signal to noise ratio detection of changes of their electrical resistance.
|Integrated circuit pad modeling|
A method of modeling an integrated circuit chip includes generating a model of a bond pad using a design tool running on a computer device. The method also includes connecting a first inductor, a first resistor, and a first set of parallel-resistor-inductor elements in series between a first node and a second node in the model.
|Layout method and system for multi-patterning integrated circuits|
A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an ic that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks.
|Scan warmup scheme for mitigating di/dt during scan test|
We report methods relating to scan warmup of integrated circuit devices. One such method may comprise loading a scan test stimulus to and unloading a scan test response from a first set of logic elements of an integrated circuit device at a scan clock first frequency equal to a test clock frequency; adjusting the scan clock from the first frequency to a second frequency by a scan warmup unit, wherein the scan clock second frequency is equal to a system clock frequency; and capturing the scan test response by a shift logic at the scan clock second frequency.
|Test control using existing ic chip pins|
An apparatus and method are provided for testing normal circuitry in an integrated circuit, the method including writing test protocols into a plurality of test registers using an enable pin and a switch pin in a first mode, storing a logic high signal in one of the plurality of test registers once the writing is completed, switching from the first mode to a second mode if the one of the plurality of test registers stores the logic high signal, and testing the normal circuitry using the enable pin and the switch pin in the second mode.. .
|Single-pin command technique for mode selection and internal data access|
A single pin is used to control an operating mode of an integrated circuit and to supply serial data to a host controller. The internal operating mode can be changed by changing a static level on an input/output terminal and maintaining that static level longer than a first time threshold.
|Method and apparatus for determining tunable parameters to use in power and performance management|
Various method and apparatus embodiments for selecting tunable operating parameters in an integrated circuit (ic) are disclosed. In one embodiment, an ic includes a number of various functional blocks each having a local management circuit.
|Method and system for enhanced performance in serial peripheral interface|
A method of conducting an operation in an integrated circuit having a plurality of memory cells includes receiving an operating command for the memory cells and receiving a first address segment associated with the memory cells in at least one clock cycle after receiving the operating command. The method further includes receiving a first performance enhancement indicator in at least one clock cycle after ending the first address segment while before starting to transfer data, for determining whether an enhanced operation is to be performed..