|| List of recent Integrated Circuit-related patents
|Power routing in standard cells|
An integrated circuit created from a cell library of compact cells. The cell library includes cells having a metal trace routed along the boundary of the cells for carrying a power supply voltage.
|Method and system for forming patterns with charged particle beam lithography|
In a method for fracturing or mask data preparation or mask process correction for charged particle beam lithography, a plurality of shots are determined that will form a pattern on a surface, where shots are determined so as to reduce sensitivity of the resulting pattern to changes in beam blur (βf). In some embodiments, the sensitivity to changes in βf is reduced by varying the charged particle surface dosage for a portion of the pattern.
|Eda tool and method, and integrated circuit formed by the method|
A method comprises: accessing data representing a layout of a layer of an integrated circuit (ic) comprising a plurality of polygons defining circuit patterns to be divided among a number (n) of photomasks for multi-patterning a single layer of a semiconductor substrate, where n is greater than one. For each set of n parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least n−1 stitches are inserted in each polygon within that set to divide each polygon into at least n parts, such that adjacent parts of different polygons are assigned to different photomasks from each other.
|Hierarchical access of test access ports in embedded core integrated circuits|
An integrated circuit can have plural core circuits, each having a test access port that is defined in ieee standard 1149.1. Access to and control of these ports is though a test linking module.
|Selective per-cycle masking of scan chains for system level test|
Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor.
|At-speed scan testing of interface functional logic of an embedded memory or other circuit core|
An integrated circuit comprises scan test circuitry and at least one circuit core coupled to the scan test circuitry. The scan test circuitry comprises input and output scan chains coupled to respective input and output interfaces of the circuit core via respective functional logic blocks, and interface signal selection circuitry.
|Memory system with calibrated data communication|
An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a dram. The dram receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value.
|Method and apparatus for latency reduction|
Aspects of the disclosure provide an integrated circuit that includes a plurality of input/output (io) circuits, an instruction receiving circuit and control circuits. The io circuits are configured to receive a plurality of bit streams corresponding to an instruction to the integrated circuit.
|Polyimides, coating composition formed therefrom and use thereof|
A polyimide (pi) having two —cooh capping groups at each end is provided. A coating composition is further provided, which contains the pi and a hardening agent having 2 to 6 functional groups capable of reacting with —cooh.
|Systems and methods for superconducting integrated circuits|
A superconducting integrated circuit may include a magnetic flux transformer having an inner inductive coupling element and an outer inductive coupling element that surrounds the inner inductive coupling element along at least a portion of a length thereof. The magnetic flux transformer may have a coaxial-like geometry such that a mutual inductance between the first inductive coupling element and the second inductive coupling element is sub-linearly proportional to a distance that separates the first inner inductive coupling element from the first outer inductive coupling element.
|Transmission device, transmission/reception device, integrated circuit, and communication state monitoring method|
Provided is a transmission device including a transmission unit that includes an antenna coil and performs communication with an external device by electromagnetic coupling, a signal output unit that generates a signal of a predetermined frequency and outputs the generated signal to the transmission unit, a communication monitor unit that monitors information about a current flowing through the antenna coil and determines a communication state based on the monitored information, and a communication correction unit that corrects a communication characteristic based on a determination result of the communication state in the communication monitor unit.. .
|Methods for fabricating integrated circuits with improved semiconductor fin structures|
Methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes providing a mandrel layer overlying a semiconductor substrate and patterning the mandrel layer into mandrel structures.
|Elongated via structures|
An integrated circuit structure includes a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings.
|Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via|
A method for fabricating through-silicon vias (tsvs) for semiconductor devices is provided. Specifically, the method involves utilizing copper contact pads in a back-end-of-line wiring level, wherein the copper contact pads act as cathodes for performing an electroplating technique to fill tsvs with plated-conductive material (e.g., copper) from an electroplating solution.
|Diffusion resistor with reduced voltage coefficient of resistance and increased breakdown voltage using cmos wells|
Integrated circuits and manufacturing methods are presented for creating diffusion resistors (101, 103) in which the diffusion resistor well is spaced from oppositely doped wells to mitigate diffusion resistor well depletion under high biasing so as to provide reduced voltage coefficient of resistivity and increased breakdown voltage for high-voltage applications.. .
|Methods of forming multiple n-type semiconductor devices with different threshold voltages on a semiconductor substrate|
One illustrative method disclosed herein involves forming an integrated circuit product comprised of first and second n-type transistors formed in and above first and second active regions, respectively. The method generally involves performing a common threshold voltage adjusting ion implantation process on the first and second active regions, forming the first and second transistors, performing an amorphization ion implantation process to selectively form regions of amorphous material in the first active region but not in the second active region, after performing the amorphization ion implantation process, forming a capping material layer above the first and second transistors and performing a re-crystallization anneal process to convert at least portions of the regions of amorphous material to a crystalline material.
|Method for fabricating integrated circuit with different gate heights and different materials|
A method for fabricating an integrated circuit includes the following steps of: providing a substrate with at least one isolation structure formed therein so as to separate the substrate into a first active region with a first stacked structure formed thereon and a second active region with a second stacked structure formed thereon; forming an interlayer dielectric layer covering the first stacked structure and the second stacked structure; and planarizing the interlayer dielectric layer to expose the top surface of the first stacked structure, wherein the second stacked structure is still covered by the interlayer dielectric layer after planarizing.. .
|Process for improving package warpage and connection reliability through use of a backside mold configuration (bsmc)|
A backside mold configuration (bsmc) process for manufacturing packaged integrated circuits includes applying a mold compound to a side of a packaging substrate opposite an attached die. The mold compound is deposited on a dielectric (such as photo resist).
|Sensor array package|
Various methods for forming a low profile assembly are described. The low profile assembly may include an integrated circuit.
|Front side copper post joint structure for temporary bond in tsv application|
A method of forming an integrated circuit structure is provided. The method includes providing a substrate, the substrate having a conductive pad thereon.
|Using interrupted through-silicon-vias in integrated circuits adapted for stacking|
In an integrated circuit (ic) adapted for use in a stack of interconnected ics, interrupted through-silicon-vias (tsvs) are provided in addition to uninterrupted tsvs. The interrupted tsvs provide signal paths other than common parallel paths between the ics of the stack.
|Adhesion of ferroelectric material to underlying conductive capacitor plate|
Deposition of lead-zirconium-titanate (pzt) ferroelectric material over iridium metal, in the formation of a ferroelectric capacitor in an integrated circuit. The capacitor is formed by the deposition of a lower conductive plate layer having iridium metal as a top layer.
|Object detection apparatus, object detection method, storage medium, and integrated circuit|
An object detection apparatus, a program, and an integrated circuit enable the contour of an object to be detected in an appropriate manner in an image including an object and its background with almost no contrast between them in a predetermined direction of the image. A vertical direction edge extraction filter in a filtering unit extracts, from an input image, a contour component in a first direction (e.g., vertical direction) of the image.
|Methods and systems for high bandwidth chip-to-chip communications interface|
Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between integrated circuit chips with low power utilization. Communication is performed using group signaling over multiple wires using a vector signaling code, where each wire carries a low-swing signal that may take on more than two signal values..
|Waveguide-coupled vertical cavity laser|
An integrated circuit includes an optical source that provides an optical signal to an optical waveguide. In particular, the optical source may be implemented by fusion-bonding a iii-v semiconductor to a semiconductor layer in the integrated circuit.
|Wireless communication system, mobile station device, base station device, wireless communication method, and integrated circuit|
Efficient transmission and reception of a random access response message is performed between a base station device and a mobile station device. When a random access preamble is transmitted from a primary cell, the mobile station device monitors a first control channel of the primary cell.
|Protection for system configuration information|
Systems and methods for detecting power attacks related to subnormal read voltage on an integrated circuit. Upon initiating power up of the integrated circuit and prior to reading configuration information from non-volatile memory (nvm), test cells associated with the nvm are read first.
|Semiconductor integrated circuit adapted to output pass/fail results of internal operations|
In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.. .
|Mixed voltage non-volatile memory integrated circuit with power saving|
An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage and is generated by a voltage regulator that receives the first voltage.
|Integrated circuit, method for driving the same, and semiconductor device|
An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided.
|Configurable buffer for an integrated circuit|
In one embodiment, an internal buffer may be provided within an integrated circuit (ic) to convert a signal to an output current to be output via a pin of the ic, under control of a switch which can be controlled based on a configuration setting of the ic, and may selectively directly couple the signal to the pin when the ic is coupled to an external driver circuit.. .
|Shielding module integrating antenna and integrated circuit component|
The present invention provides a shielding module integrating antenna and integrated circuit component, which comprises an artificial magnetic conductor board, an antenna, a common ground face, a plurality of first via holes, a shielding slot, a plurality of second via holes, and an ic component. The ic component is embedded in the shielding slot formed between the common ground face and surrounded by the plurality of second via holes of the artificial magnetic conductor board.
|Integrated transformer balun with enhanced common-mode rejection for radio frequency, microwave, and millimeter-wave integrated circuits|
Apparatus and method example embodiments provide an improved common mode rejection ratio in high frequency transformer baluns. According to an example embodiment of the invention, an apparatus comprises a first winding of at least one turn forming a primary coil, having first and second differential leads oriented in a first direction, the primary coil formed in a first conductive layer over a substrate and the first differential lead of the primary coil being grounded; and a second winding of at least one turn forming a secondary coil, having a third and fourth differential leads oriented in a second direction offset by an angle of greater than zero degrees and less than 180 degrees from the first direction, the secondary coil formed in a second conductive layer separated by an insulating layer from the first conductive layer..
|Apparatus for a radio frequency integrated circuit|
A low noise amplifier for radio frequency integrated circuits having an adaptive input and operating mode selection. The low noise amplifier comprises two inputs which can be operated in different configurations.
|Compensating for process variation in integrated circuit fabrication|
Systems and methods for reducing process sensitivity in integrated circuit (“ic”) fabrication. An integrated circuit structure is provided that includes a first integrated circuit device having at least one parameter influenced by process variation in a first manner.
|User registers implemented with routing circuits in a configurable ic|
Some embodiments of the invention provide a configurable integrated circuit (“ic”). The configurable ic includes a set of configurable logic circuits for configurably performing a set of functions.
|Integrated circuit identification and dependability verification using ring oscillator based physical unclonable function and age detection circuitry|
One feature pertains to an integrated circuit (ic) that includes a first plurality of ring oscillators configured to implement, in part, a physically unclonable function (puf). The ic further includes a second plurality of ring oscillators configured to implement, in part, an age sensor circuit, and also a ring oscillator selection circuit that is coupled to the first plurality of ring oscillators and the second plurality of ring oscillators.
|Interconnection structure for an integrated circuit|
The disclosure relates to a method of fabricating an interconnection structure of an integrated circuit, comprising the steps of: forming a first conductive element within a first dielectric layer; depositing a first etch stop layer above the first conductive element and the first dielectric layer; forming an opening in the first etch stop layer above the first conductive element, to form a first connection area; depositing a second dielectric layer above the etch stop layer and above the first conductive element in the connection area; etching the second dielectric layer to form at least one hole which is at least partially aligned with the connection area; and filling the hole with a conductive material to form a second conductive element in electrical contact with the first conductive element.. .
|Chip package for high-count chip stacks|
A chip package is described. This chip package includes a substrate having a side at an angle relative to the top and bottom surfaces of the substrate that is between that of a direction parallel to the top and bottom surfaces and that of a direction perpendicular to the top and bottom surfaces (i.e., between 0° and 90°).
|Method for providing electrical connections to spaced conductive lines|
An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask.
|Method and apparatus providing integrated circuit having redistribution layer with recessed connectors|
A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to expose a portion of the stud and then forming a conductive layer inside the trench and in electrical contact with the stud.. .
|Structure and method of forming a pad structure having enhanced reliability|
An integrated circuit structure includes a substrate, and a first metal layer over the substrate. The integrated circuit structure further includes a second insulating layer over the first metal layer, the second insulating layer having a damascene opening and two via openings.
|Methods and systems for fabrication of low-profile mems cmos devices|
A mems integrated circuit including a plurality of layers where a portion includes one or more electronic elements on a semiconductor material substrate. The circuit includes a structure of interconnection layers having a bottom layer of conductor material and a top layer of conductor material where the layers are separated by at least one layer of dielectric material.
|Power distribution and thermal solution for direct stacked integrated circuits|
Some implementations provide an apparatus that includes a package substrate, a first die coupled to the package substrate, and a second die coupled to the first die. The die package also includes a heat spreader coupled to the second die, the heat spreader configured to (i) dissipate heat from the second die, and (ii) provide an electrical path for a power signal to the second die.
|Three-dimensional (3-d) integrated circuits (3dics) with graphene shield, and related components and methods|
A three-dimensional (3-d) integrated circuit (3dic) with a graphene shield is disclosed. In certain embodiments, at least a graphene layer is positioned between two adjacent tiers of the 3dic.
|Finfets with reduced parasitic capacitance and methods of forming the same|
An integrated circuit structure includes a semiconductor substrate, a semiconductor strip over a portion of the semiconductor substrate, and a shallow trench isolation (sti) region on a side of the semiconductor strip. The sti region includes a dielectric layer, which includes a sidewall portion on a sidewall of the semiconductor strip and a bottom portion.
|Ion reduced, ion cut-formed three-dimensional (3d) integrated circuits (ic) (3dics), and related methods and systems|
Ion-reduced, ion cut-formed three-dimensional (3d) integrated circuits (ic) (3dics) are disclosed. Related methods and systems are also disclosed.
|Solar powered ic chip|
A self-powered circuit package includes a substrate and an integrated circuit (ic). The ic is mounted on a surface of the substrate.
|Interconnect wiring switches and integrated circuits including the same|
An electronic circuit, includes a plurality of electronic devices configured as interconnected to provide one or more circuit functions and at least one interconnect structure that includes a first patterned conductor connected to a terminal of a first electronic device in the electronic circuit. A second patterned conductor is connected to a terminal of a second electronic device in the electronic circuit.
|Low impedance interface circuit to maximize bandwidth and provide bias control|
A multichannel application specific integrated circuit (asic) for interfacing with an array of photodetectors in a positron emission tomography (pet) imaging system includes a front end circuit configured to be coupled to the photodetectors and to receive discrete analog signals therefrom. The asic further includes a time discriminating circuit operably coupled to the front end circuit and configured to generate a hit signal based on a combination of the discrete analog signals, and an energy discriminating circuit operably coupled to the front end circuit and configured to generate a summed energy output signal based on each of the discrete analog signals and summed row and column output signals based on each of the discrete analog signals.
|Flexible smart card transponder|
This smart card transponder is made extremely flexible by being ultrathin. Its thickness of only 0.25 mm is achieved by using all ultrathin flexible substrates.
|Temperature stabilization in semiconductors using the magnetocaloric effect|
Apparatus and methods incorporate magnetocaloric materials in integrated circuit chip-carrier structures for electronic packages. An integrated circuit chip is electrically connected to a substrate.
|Method for determining interface timing of integrated circuit automatically and related machine readable medium thereof|
A method for determining an interface timing of an integrated circuit includes: reading a netlist file and a timing constraint file of the integrated circuit, and determining a first interface port of the netlist file according to the netlist file and the timing constraint file; determining a first transmission path and a load on the first transmission path between the first interface port and a specific circuit element in the netlist file; generating an interface circuit file according to the first transmission path and the load on the first transmission path; and calculating a first signal transmission time of the first transmission path out according to the interface circuit file.. .
|Automatic generation of wire tag lists for a metal stack|
Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition.
|Pattern-based replacement for layout regularization|
Methods and systems for generating a regularized integrated circuit layout are disclosed. Pattern replacement of various portions of wiring within an integrated circuit layout with a common pattern is performed in order to generate a regularized layout.
|Boosting transistor performance with non-rectangular channels|
Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate..
|Methods for manufacturing integrated circuit devices having features with reduced edge curvature|
A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line.
|Retargeting semiconductor device shapes for multiple patterning processes|
A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features.
|Multiple-capture dft system for detecting or locating crossing clock-domain faults during scan-test|
A method for providing ordered capture clocks to detect or locate faults within n clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where n>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in n test stimuli to all said scan cells within said n clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said n clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.. .
|Integrated circuit testing with power collapsed|
Provided are apparatus and methods for testing an integrated circuit. In an exemplary method for testing an integrated circuit, a test controller and a power manager are integrated into a main power domain of the integrated circuit.
|Tunable sector buffer for wide bandwidth resonant global clock distribution|
A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode..
|Adaptive temperature and power calculation for integrated circuits|
Methods, apparatus, and fabrication processes relating to thermal calculations of an integrated circuit device are reported. The methods may comprise determining a power consumption by a power entity of an integrated circuit, the power entity comprising at least one functional element of the integrated circuit; determining a temperature of a thermal entity, the thermal entity comprising a subset of the power entity; and adjusting at least one of a voltage or an operating frequency of at least one functional element of the power entity, based upon the temperature of the thermal entity being greater than or equal to a predetermined threshold temperature for the thermal entity..
|Method and apparatus for cutting senior store latency using store prefetching|
In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for cutting senior store latency using store prefetching. For example, in one embodiment, such means may include an integrated circuit or an out of order processor means that processes out of order instructions and enforces in-order requirements for a cache.
|Memory system topologies including a buffer device and an integrated circuit memory device|
Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path.
|Integrated circuit using i2c bus and control method thereof|
An integrated circuit for controlling a slave device is provided. The integrated circuit includes a pin, a micro-controller and an inter integrated circuit (i2c) bus controller coupled between the micro-controller and the pin.
|Device for measuring integrated circuit current and method of measuring integrated circuit current using the device|
A method of extracting an integrated circuit (ic) current is provided. The method includes generating a transfer function value by using a voltage measured in a node nearest an input terminal of the ic, substituting the generated transfer function value for a reverse fast fourier transform function, so as to extract the ic voltage, and extracting the ic current from the extracted ic voltage through a simulation in a time domain..
|Mobile station device, communication system, communication method, and integrated circuit|
In a system including at least one base station device, the base station device efficiently controls uplink signals. A mobile station device includes a path loss calculation unit 4051 configured to calculate path losses, each based on one of a plurality of types of reference signals received by a reception processing unit 401, a transmit power setting unit 4053 configured to set a desired transmit power for an uplink signal using the path losses calculated by the path loss calculation unit 4051, and a power headroom control unit 4055 configured to generate a power headroom using the desired transmit power set by the transmit power setting unit 4053, the power headroom being information concerning transmit power to spare, and configured to control transmission of the power headroom.
|Methods for optical proximity correction in the design and fabrication of integrated circuits|
A method of manufacturing an optical lithography mask includes providing a patterned layout design comprising a plurality of polygons, correcting the patterned layout design using optical proximity correction (opc) by adjusting widths and lengths of one or more of the plurality of polygons, to generate a corrected patterned layout design, converting the corrected patterned layout design into a mask writer-compatible format, to generate a mask writer-compatible layout design comprising the plurality of polygons, and biasing each polygon in the plurality of polygons with a bias that accounts for large-scale density values of the patterned layout design, to generate a biased, mask writer-compatible layout design.. .
|Multi-direction design for bump pad structures|
An integrated circuit structure includes a semiconductor chip having a first region and a second region; a dielectric layer formed on the first region and the second region of the semiconductor chip; a first elongated under-bump metallization (ubm) connector formed in the dielectric layer and on the first region of the semiconductor chip and having a first longer axis extending in a first direction; and a second elongated ubm connector formed in the dielectric layer on the second region of the semiconductor chip and having a second longer axis extending in a second direction. The first direction is different from the second direction..
|Methods for fabricating integrated circuits having embedded electrical interconnects|
A method for fabricating integrated circuits includes providing a substrate including a protecting layer over an oxide layer and etching a recess through the protecting layer and into the oxide layer. A barrier material is deposited over the substrate to form a barrier layer including a first region in the recess and a second region outside the recess.
|Integrated circuits including ild structure, systems, and fabrication methods thereof|
A method of forming an integrated circuit comprises forming a gate of a transistor over a substrate. The method further comprises forming a connecting line over the substrate, the connecting line being coupled with an active area of the transistor.
|Memory devices and formation methods|
A method includes forming an electrical insulator material over an integrated circuit having a metal-containing conductive interconnect and activating a dopant in a semiconductor material of a substrate to provide a doped region. The doped region provides a junction of opposite conductivity types.
|Integration of shallow trench isolation and through-substrate vias into integrated circuit designs|
A method of manufacturing an ic, comprising providing a substrate having a first side and a second opposite side, forming a sti opening in the first side of the substrate and forming a partial tsv opening in the first side of the substrate and extending the partial tsv opening. The extended partial tsv opening is deeper into the substrate than the sti opening.
|Methods for fabricating integrated circuits having gate to active and gate to gate interconnects|
Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes forming a dummy gate structure including a dummy gate electrode having sidewalls and overlying a semiconductor substrate and first and second sidewall spacers on the sidewalls of the dummy gate electrode.
It is an object of the invention to improve the production efficiency in sealing a thin film integrated circuit and to prevent the damage and break. Further, it is another object of the invention to prevent a thin film integrated circuit from being damaged in shipment and to make it easier to handle the thin film integrated circuit.