|| List of recent Integrated Circuit-related patents
| Self-aligned double patterning via enclosure design|
A design methodology for determining a via enclosure rule for use with a self-aligned double pattern (sadp) technique is disclosed. The shape of the block mask serves as a criterion for choosing a via enclosure rule.
| Dummy shoulder structure for line stress reduction|
Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate.
| Modeling mechanical behavior with layout-dependent material properties|
Computer-implemented techniques for modeling the mechanical behavior of integrated circuits using layout-dependent material properties are disclosed. The back end of line wiring that connects an integrated circuit to a substrate undergoes stresses and strains due to many heating and cooling cycles during a chip's packaging and lifecycle.
| Variable code rate transmission|
An integrated circuit device includes an output buffer circuit that provides a first output having a first code rate. The first output is provided in response to a first indication of a change in a parameter that affects an error rate of the first output.
| Error protection for integrated circuits|
A method for providing error detection and/or correction to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding a first error control mechanism to the array of storage cells in the insensitive direction. The method also includes adding a second error control mechanism to the array of storage cells in the sensitive direction.
| Scan chain in an integrated circuit|
In an embodiment, a scannable storage element includes an input circuit for providing a first signal at first node based on a data input and a scan input, where the scan input is of pull-up logic in functional mode. The input circuit includes a first pull-up path comprising a switch receiving data input and a switch receiving scan enable input, and second pull-up path comprising a switch receiving scan input, first pull-down path comprising a switch receiving the scan enable input and a switch receiving the scan input, and second pull-down path comprising a switch receiving the data input.
| At-speed scan testing of clock divider logic in a clock module of an integrated circuit|
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells.
| Generation of simulated errors for high-level system validation|
A device, integrated circuit and method for generating simulated errors are disclosed. In the disclosed device, integrated circuit and method, an original data value is read from a memory.
| Power-up restriction|
Techniques are disclosed relating to power management within an integrated circuits. In one embodiment an apparatus is disclosed that includes a circuit and a power management unit.
| Simd instructions for data compression and decompression|
An execution unit configured for compression and decompression of numerical data utilizing single instruction, multiple data (simd) instructions is described. The numerical data includes integer and floating-point samples.
| Data compression and decompression using simd instructions|
Compression and decompression of numerical data utilizing single instruction, multiple data (simd) instructions is described. The numerical data includes integer and floating-point samples.
| Hybrid hard disk drive having a flash storage processor|
An apparatus is described that is configured to control operations in a hybrid hard disk drive. In an implementation, the apparatus includes a hybrid flash storage processor connected to the host interface that is configured to communicatively couple a flash storage component and to a hard disk integrated circuit chip.
| Neural activity recording apparatus and method of using same|
An apparatus to enable individuals to record neural activity. The apparatus is designed to be produced at a low cost and may be configured to be disposable or capable of a limited number of uses.
| Poly oligosiloxysilane|
The present invention relates to a new synthesis procedure for a family of silica based polymer materials synthesized through the interconnection of silicate oligomers with reactive silanes. By using this synthesis it is possible to generate novel silica based polymer materials.
| Position estimation device, position estimation method, program, and integrated circuit|
A position estimation device including: a provisional position setting unit which sets current position information indicating an estimated current position of a wireless terminal; a distance estimation unit which estimates, using receiving strengths of signals received from plural wireless stations, distance information indicating distances from the plural wireless stations to the wireless terminal; a possible area calculation unit which calculates, using the distance information and map information indicating a spatial structure, an area in the spatial structure which can maintain the distances indicated in the distance information, as a possible area in the spatial structure in which the wireless terminal is likely to be present; and a correction unit which corrects the current position indicated in the current position information to a position within the possible area when the current position is outside the possible area.. .
| Sim profile brokering system|
A method for receiving identity information for a mobile communication device is provided. The method comprises a memory module on the mobile communication device receiving, over a wireless communication link, a device identifier and an authentication key, wherein no identity information had previously been provided to the memory module.
| High resolution printing technique|
A pattern having exceptionally small features is printed on a partially fabricated integrated circuit during integrated circuit fabrication. The pattern is printed using an array of probes, each probe having: 1) a photocatalytic nanodot at its tip; and 2) an individually controlled light source.
| Semiconductor device comprising a passive component of capacitors and process for fabrication|
A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside.
| Method for fabricating solder columns for a column grid array package|
A method for fabricating an electronic device package having a column grid array is disclosed. A column grid array package includes a substrate, an integrated circuit located on a first side of the substrate, and a set of solder columns located on a second side of the substrate.
| Apparatus and method for manufacturing an integrated circuit|
The present invention relates to an apparatus for manufacturing an integrated circuit (10) having a thick film metal layer (14). A layer of metal paste (14) is applied via an application means (24) onto a heat-conducting substrate (12).
| Method of forming wafer-level molded structure for package assembly|
A method of forming an integrated circuit structure is provided. In an embodiment, the method includes bonding top dies onto a bottom wafer and then molding a first molding material onto and in between the top dies and the bottom wafer.
| Open cavity plastic package|
A method for manufacturing open cavity integrated circuit packages, the method comprising: placing a wire-bound integrated circuit in a mold; forcing a pin to contact a die of the wire-bound integrated circuit by applying a force between the pin and the mold; injecting plastic into the mold; allowing the plastic to set around the integrated circuit to form a package having an open cavity defined by the pin; and removing the open cavity integrated circuit package from the mold. A mold for forming a package for an integrated circuit sensor device, comprising: a bottom part for supporting an integrated circuit die; a top part that is operable to be placed on top of said bottom part to form a cavity into which a plastic material can be injected to form the package, wherein the top part of the mold comprises a spring-loaded pin arrangement comprising a cover that covers a sensor area on the integrated circuit die and provides for an opening when the plastic material is injected..
| Contact resistance test structure and method suitable for three-dimensional integrated circuits|
A contact resistance test structure, a method for fabricating the contact resistance test structure and a method for measuring a contact resistance while using the contact resistance test structure are all predicated upon two parallel conductor lines (or multiples thereof) that are contacted by one perpendicular conductor line absent a via interposed there between. The test structure and related methods are applicable within the context of three-dimensional integrated circuits..
| Method of manufacturing and testing a chip package|
A method of producing and testing a chip package is described. The chip package to be produced includes a semiconductor chip containing an integrated circuit and a reinforcing structure attached to the semiconductor chip.
| Single reticle approach for multiple patterning technology|
A reticle for multiple patterning a layer of an integrated circuit die includes a first portion with a first layout pattern for multiple patterning the layer of the integrated circuit die, and a second portion with a second layout pattern for multiple patterning the layer of the integrated circuit die. The first layout pattern is different from the second layout pattern..
| Intelligent bail|
An identification device is configured to be coupled externally to an optoelectronic device to provide connectivity and/or identification information in an optical network in which the optoelectronic device is implemented. The identification device may include an integrated circuit with unique identification information and a plurality of contacts coupled to the integrated circuit and configured to be coupled to an outside identification system.
| Integrated circuit including non-planar structure and waveguide|
One embodiment provides an integrated circuit including a first non-planar structure and a waveguide configured to provide electromagnetic waves to the first non-planar structure. The first non-planar structure provides a first signal in response to at least some of the electromagnetic waves..
| Method of fabricating silicon waveguides with embedded active circuitry|
A method of fabricating silicon waveguides with embedded active circuitry from silicon-on-insulator wafers utilizes photolithographic microfabrication techniques to define waveguide structures and embedded circuit recesses for receiving integrated circuitry. The method utilizes a double masking layer, one layer of which at least partially defines at least one waveguide and the other layer of which at least partially defines the at least one waveguide and at least one embedded circuit recess.
| Audio processing device, audio processing method, audio processing program and audio processing integrated circuit|
Provided is an audio processing device comprising: a feature data generation unit which generates, for each unit section of an audio signal, section feature data expressing features of the audio signal in the unit section; a feature variation calculation unit which calculates, for each unit section, a feature variation value quantifying temporal variation of the features in the unit section, by setting the unit section as a target section and using section feature data of unit sections close to the target section; and a section judgment unit which judges, for each unit section, whether the unit section is a feature unit section including a variation point of the features, based on comparison of a threshold value and the feature variation value. Through the above, the audio processing device can detect feature unit sections from an audio signal of an av content or the like..
| Terminal device, base station device, program, and integrated circuit|
In a cellular system, new precoding that enables the performance of precoding to be adequately utilized is introduced, and thereby throughput is increased. There is provided a terminal device that includes a plurality of transmit antennas and that performs precoding on a transmit signal.
| Systems and methods for packet routing|
Systems and methods to route packets of information within an integrated circuit, across one or more boards, racks, blades, and/or chassis, and/or across a connected network of packet processing engines include various modes of operation. Packets are routed to their destination, for example an individual packet processing engine.
| Integrated circuits and methods for dynamic frequency scaling|
In an integrated circuit, a first delay locked loop circuit is configured to adjust a phase of a first clock signal input to a first clock input terminal, and to at least one of transmit and receive information based on the phase-adjusted first clock signal. A second delay locked loop circuit is configured to adjust a phase of a second clock signal input to a second clock input terminal, and to at least one of transmit and receive information based on the phase-adjusted second clock signal.
| Method and apparatus for increasing yield|
Aspects of the disclosure provide an integrated circuit (ic) that is configured to have an increased yield. The ic includes a memory element configured to store a specific value determined based on a characteristic of the ic, and a controller configured to control an input regulator based on the specific value of the ic.
| Circuit board assembly|
A circuit board assembly with a printed circuit board, which has an smd mounting location for attaching a first integrated circuit having an electrical circuit. A replacement circuit board having the electrical circuit is soldered at the smd mounting location using smd technology..
| Thermal management solution for circuit products|
An apparatus including a cold plate body; a channel module disposed within the cold plate body including a channel body and a plurality of channels projecting through the channel body; and a manifold disposed on the channel module, the manifold including an inlet and an outlet and a first plurality of apertures in fluid communication with the inlet and a second plurality of apertures are in fluid communication with the outlet. A method including introducing a fluid to an integrated cold plate disposed on an integrated circuit device, the integrated cold plate comprising a cold plate body extending about the device, the fluid being introduced into a manifold in fluid communication with a channel module disposed between the manifold and a base plate, the channel module, and including channels to direct the fluid toward the base plate, and collecting the fluid returned to the manifold..
| Pixel test in a liquid crystal on silicon chip|
An example embodiment includes a continuity testing method of a pixel in a liquid crystal on silicon integrated circuit. The method includes writing a first voltage to a pixel.
| Semiconductor device|
In a semiconductor device in which a copper plating layer is used for a conductor of an antenna and in which an integrated circuit and the antenna are formed over the same substrate, an object is to prevent an adverse effect on electrical characteristics of a circuit element due to diffusion of copper, as well as to provide a copper plating layer with favorable adhesiveness. Another object is to prevent a defect in the semiconductor device that stems from poor connection between the antenna and the integrated circuit, in the semiconductor device in which the integrated circuit and the antenna are formed over the same substrate.
| Oscillator and semiconductor integrated circuit device|
An oscillator and a semiconductor integrated circuit device with an internal oscillator capable of compensating the temperature characteristics even when there is a large parasitic capacitance too large to ignore directly between the output terminals of the oscillator. In an oscillator containing an inductance element l, and a capacitive element c, and an amplifier each coupled in parallel across a first and second terminal, the amplifier amplifies the resonance generated by the inductance element and capacitive element and issues an output from the first terminal and the second terminal, and in which a first resistance element with a larger resistance value than the parasitic resistance of the inductance element between the first terminal and the second terminal, is coupled in serial with the capacitive element between the first terminal and the second terminal..
| Bias current circuit and semiconductor integrated circuit|
A bias current circuit controls an oscillator that generates an oscillation signal of a frequency corresponding to an input current. The circuit includes a part that detects fluctuation of a control current for variably controlling the frequency of the oscillation signal and a part that generates an input current in which a fluctuation component of the control current is canceled using a current for cancelling the detected fluctuation of the control current..
| Power supply for integrated circuit|
A power supply that provides a supply voltage to an integrated circuit (ic) includes high and low power regulators and a power management circuit. The high power regulator regulates the supply voltage at a first voltage level and the low power regulator is set to an inactive mode when the ic is in a run mode.
| Optical transmission of test data for testing integrated circuits|
In accordance with one aspect of the present description, integrated circuits may tested by optically transmitting test data over a light beam in addition to or instead of transmitting the test data using mechanical probes. Optically transmitted test data is detected by a photon detector on board the die to be tested.
| Integrated circuits and methods of forming the same with embedded interconnect connection to through-semiconductor via|
Integrated circuits, methods of forming integrated circuits, and methods of sensing voiding between a through-semiconductor via and a subsequent layer that overlies the through-semiconductor via in integrated circuits are provided. An exemplary method of forming an integrated circuit includes forming a plurality of semiconductor devices on a semiconductor substrate.
| On-die all-digital delay measurement circuit|
An all-digital delay measurement circuit (dmc) constructed on an integrated circuit (ic) die characterizes clocking circuits such as full phase rotation interpolators, also constructed on the ic die. The on-die all-digital dmc produces a digital output value proportional to the relative delay between two clocks, normalized to the clock period of the two clocks..
| Semiconductor device and semiconductor module|
A semiconductor device includes an analog integrated circuit and a digital integrated circuit provided on a major surface of a substrate. An analog ground terminal is provided for the analog integrated circuit, and digital ground terminals are provided for the digital integrated circuit.
| Integrated circuits and methods of forming the same with metal layer connection to through-semiconductor via|
Integrated circuits and methods of forming integrated circuits are provided herein, in which a plurality of semiconductor devices is formed on a semiconductor substrate. At least one through-semiconductor via is formed in the semiconductor substrate and an interlayer dielectric layer is formed overlying the at least one through-semiconductor via and the plurality of semiconductor devices.
| Random coded integrated circuit structures and methods of making random coded integrated circuit structures|
Randomized coded arrays and methods of forming a randomized coded array. The methods include: forming a dielectric layer on a semiconductor substrate; forming an array of openings extending through the dielectric layer; introducing particles into a random set of less than all of the openings; and forming a conductive material in each opening of the array of openings, thereby creating the randomized coded array, wherein a first resistance of a pathway through the conductive material in openings containing the particles is different from a second resistance of a path through openings not containing the particles.
| Method of semiconductor integrated circuit fabrication|
A method of fabricating a semiconductor integrated circuit (ic) is disclosed. The method includes providing a substrate.
| Selective local metal cap layer formation for improved electromigration behavior|
A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ild) layer, and forming a second metal line in the ild layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, l, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis.. .
| Selective local metal cap layer formation for improved electromigration behavior|
A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ild); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.. .
| Semiconductor integrated circuit and fabricating the same|
A method of fabricating a semiconductor integrated circuit (ic) is disclosed. The method includes receiving a precursor.
| Integrated circuit structures, semiconductor structures, and semiconductor die|
Methods for fabricating integrated circuit devices on an acceptor substrate devoid of circuitry are disclosed. Integrated circuit devices are formed by sequentially disposing one or more levels of semiconductor material on an acceptor substrate, and fabricating circuitry on each level of semiconductor material before disposition of a next-higher level.
| Integrated circuits with magnetic core inductors and methods of fabrications thereof|
In one embodiment, a method of forming a semiconductor device includes forming a first inductor coil within and/or over a substrate. The first inductor coil is formed adjacent a top side of the substrate.
| Integrated circuit including a directional light sensor|
An integrated circuit and a method of making the same. The integrated circuit includes a semiconductor substrate having a major surface.
| Adaptive fin design for finfets|
A method of designing a standard cell includes determining a minimum fin pitch of semiconductor fins in the standard cell, wherein the semiconductor fins are portions of finfets; and determining a minimum metal pitch of metal lines in a bottom metal layer over the standard cell, wherein the minimum metal pitch is greater than the minimum fin pitch. The standard cell is placed in an integrated circuit and implemented on a semiconductor wafer..
| Finfet integrated circuits with uniform fin height and methods for fabricating the same|
Methods for fabricating finfet integrated circuits with uniform fin height and ics fabricated from such methods are provided. A method includes etching a substrate using an etch mask to form fins.
| Adhesion layer and multiphase ultra-low k dielectric material|
A dielectric material incorporating a graded carbon adhesion layer whereby the content of c increases with layer thickness and a multiphase ultra low k dielectric comprising a porous sicoh dielectric material having a k less than 2.7 and a modulus of elasticity greater than 7 gpa is described. A semiconductor integrated circuit incorporating the above dielectric material in interconnect wiring is described and a semiconductor integrated circuit incorporating the above multiphase ultra low k dielectric in a gate stack spacer of a fet is described..
| Semiconductor integrated circuit|
A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.. .
| A strip-shaped gate-modulated tunneling field effect transistor and a preparation method thereof|
The present invention discloses a strip-shaped gate-modulated tunneling field effect transistor and a preparation method thereof, belonging to a field of field effect transistor logic device and the circuit in cmos ultra large scale integrated circuit (ulsi). The tunneling field effect transistor includes a control gate, a gate dielectric layer, a semiconductor substrate, a highly-doped source region and a highly-doped drain region, where the highly-doped source region and the highly-doped drain region lie on both sides of the control gate, respectively, the control gate has a strip-shaped structure with a gate length greater than a gate width, and at one side thereof is connected to the highly-doped drain region and at the other side thereof extends laterally into the highly-doped source region; a region located below the control gate is a channel region; and the gate width of the control gate is less than twice width of a source depletion layer.
| Chip package having terminal pads of different form factors|
A chip package includes an integrated circuit chip. A first group of terminal pads of the chip package is electrically connected to the integrated circuit chip and a second group of terminal pads of the chip package is electrically connected to the integrated circuit chip.
| Optical i/o system using planar light-wave integrated circuit|
Photonic components are placed on the processor package to bring the optical signal close to the processor die. The processor package includes a substrate to which the processor die is coupled, and which allows the processor die to connect to a printed circuit board.
| Carrying case with multi-frequency shielding|
A carrying case having a first compartment and a second compartment for accommodating a plurality of objects; the first object which is embedded with integrated circuits that can process, store and communicate data on radio frequency identification microprocessors; said second object which is configured to process, store and communicate data on radio frequency identification microprocessors; said inner lining of said carrying case configured to include a radio frequency shielding; said shielding material including a layer of conductive material to attenuate interference fields and signals which are transmitted at varying frequencies and wavelengths; and wherein the shielding material is configured to block access to data which is stored on radio frequency identification microprocessors embedded in either the first object or second object.. .
| Electrochemical sensor device|
There is disclosed an electrochemical sensor device comprising: an integrated electrochemical sensor element having: a substrate; first and second electrodes formed on the upper surface of the substrate; and an electrolyte layer formed on the first and second electrodes so as to electrically contact both the first and second electrodes; and a sensor integrated circuit electrically connected to the first and second electrodes of the integrated electrochemical sensor element. The integrated electrochemical sensor element and the sensor integrated circuit are provided in a single package..
| Electronic component|
An electronic component has a first member in which an electrostatic actuator is provided, a second member in which a drive integrated circuit for driving the electrostatic actuator is provided, and join parts that joins the first member and the second member while a surface on which the electrostatic actuator is provided in the first member and a surface on which the drive integrated circuit is provided in the second member are opposed to each other. The electrostatic actuator and the drive integrated circuit are disposed in a space surrounded by the first member, the second member, and the join parts..
|Systems and methods for detecting and mitigating programmable logic device tampering|
Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as fpgas, have two stages of operation; a configuration stage and a user mode stage.
|Method and apparatus for using dynamic voltage and frequency scaling with circuit-delay based integrated circuit identification|
One feature pertains to a method that includes implementing a physical unclonable function (puf) circuit, and obtaining a first set of output bits from the puf circuit by operating the puf circuit at a first supply voltage level and/or first frequency. Then, at least one of the first supply voltage level is changed to a second supply voltage level and/or the first frequency is changed to a second frequency, where the second supply voltage level and the second frequency are different than the first supply voltage level and the first frequency, respectively.
|Power grid design for integrated circuits|
A method of generating a power grid to supply current to a plurality of cells of an integrated circuit includes routing an initial power grid representing a power usage estimate for the plurality of cells. The method also includes performing power grid analysis prior to routing of signal wires to make a determination of whether the initial power grid meets power requirements of the integrated circuit, and selectively modifying portions of the initial power grid based on the performing the power grid analysis to generate the power grid..
|Automating integrated circuit device library generation in model based metrology|
Various embodiments include computer-implemented methods, computer program products and systems for generating an integrated circuit (ic) library for use in a scatterometry analysis. In some cases, approaches include: obtaining chip design data about at least one ic chip; obtaining user input data about the at least one ic chip; and running an ic library defining program using the chip design data in its original format and the user input data in its original format, the running of the ic library defining program including: determining a process variation for the at least one ic chip based upon the chip design data and the user input data; converting the process variation into shape variation data; and providing the shape variation data in a text format to a scatterometry modeling program for use in the scatterometry analysis..
|One-time programmable integrated circuit security|
One-time programmable integrated circuit security is described. An example of a method of protecting memory assets in an integrated circuit includes sampling values of multiple otp memory arrays and comparing the sampled value of each otp memory array with the sampled value of each other otp memory array and with an unprogrammed otp memory array value.
|Error protection for integrated circuits in an insensitive direction|
A method for providing error detection, or error detection combined with error correction, to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding an error control mechanism to the array of storage cells in the insensitive direction. The insensitive direction is a direction perpendicular to a width of a gate conductor of the storage cells..
|Scan test circuitry comprising at least one scan chain and associated reset multiplexing circuitry|
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells.
|System and method for non-intrusive random failure emulation within an integrated circuit|
The apparatus and methods allow random hardware failure emulation of an integrated circuit (ic) by emulation of potential defects to enable behavior evaluation of the rest of the design in such situation. This emulation can non-intrusively address multiple points of failure.
|Methods and circuits for disrupting integrated circuit function|
Methods and circuits for disrupting integrated circuit function. The circuits include finite state machines connected to memory arrays.
|Secure key storage using physically unclonable functions|
Some implementations disclosed herein provide techniques and arrangements for provisioning keys to integrated circuits/processors. A processor may include physically unclonable functions component, which may generate a unique hardware key based at least on at least one physical characteristic of the processor.
|Integrated circuit device, memory interface module, data processing system and method for providing data access control|
An integrated circuit device comprising at least one memory interface module arranged to be operably coupled between at least one data storage device and a plurality of master devices within a data processing system. The at least one memory interface module comprises a plurality of buffers and at least one data access control module.
|Method for controlling transaction exchanges between two integrated circuits|
Transaction exchanges are controlled between two integrated circuits in a system having the integrated circuits (ics), a power supply supplying power to a link between the ics, thereby enabling transaction exchanges between both ics and a controller controlling the ics and the power supply. This involves receiving an order at the controller, wherein the order requires the link to be closed.
|Debug control circuit|
An integrated circuit includes a bus; a processing unit configured to execute a user program; and a debugging circuit connected to the bus, the debugging circuit transferring a command in a command register to the processing unit via the bus in response to a command transfer request from the processing unit, wherein, when the processing unit halts the execution of the user program and makes a request for the command transfer request to the debugging circuit, the debugging circuit makes a response for freeing the use right of the bus from the processing unit in a period between the command transfer request and the command transfer operation.. .
|Adaptive communication interface|
Embodiments of the invention include a communication interface and protocol for allowing communication between devices, circuits, integrated circuits and similar electronic components having different communication capacities or clock domains. The interface supports communication between any components having any difference in capacity and over any distance.