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Integrated Circuit patents

This page is updated frequently with new Integrated Circuit-related patent applications. Subscribe to the Integrated Circuit RSS feed to automatically get the update: related Integrated RSS feeds. RSS updates for this page: Integrated Circuit RSS RSS

Adaptive communication interface

Semiconductor device and method of manufacturing semiconductor device

Communication apparatus, integrated circuit, and communication method

Date/App# patent app List of recent Integrated Circuit-related patents
 Systems and methods for detecting and mitigating programmable logic device tampering patent thumbnailnew patent Systems and methods for detecting and mitigating programmable logic device tampering
Systems and methods are disclosed for preventing tampering of a programmable integrated circuit device. Generally, programmable devices, such as fpgas, have two stages of operation; a configuration stage and a user mode stage.
 Method and apparatus for using dynamic voltage and frequency scaling with circuit-delay based integrated circuit identification patent thumbnailnew patent Method and apparatus for using dynamic voltage and frequency scaling with circuit-delay based integrated circuit identification
One feature pertains to a method that includes implementing a physical unclonable function (puf) circuit, and obtaining a first set of output bits from the puf circuit by operating the puf circuit at a first supply voltage level and/or first frequency. Then, at least one of the first supply voltage level is changed to a second supply voltage level and/or the first frequency is changed to a second frequency, where the second supply voltage level and the second frequency are different than the first supply voltage level and the first frequency, respectively.
 Power grid design for integrated circuits patent thumbnailnew patent Power grid design for integrated circuits
A method of generating a power grid to supply current to a plurality of cells of an integrated circuit includes routing an initial power grid representing a power usage estimate for the plurality of cells. The method also includes performing power grid analysis prior to routing of signal wires to make a determination of whether the initial power grid meets power requirements of the integrated circuit, and selectively modifying portions of the initial power grid based on the performing the power grid analysis to generate the power grid..
 Automating integrated circuit device library generation in model based metrology patent thumbnailnew patent Automating integrated circuit device library generation in model based metrology
Various embodiments include computer-implemented methods, computer program products and systems for generating an integrated circuit (ic) library for use in a scatterometry analysis. In some cases, approaches include: obtaining chip design data about at least one ic chip; obtaining user input data about the at least one ic chip; and running an ic library defining program using the chip design data in its original format and the user input data in its original format, the running of the ic library defining program including: determining a process variation for the at least one ic chip based upon the chip design data and the user input data; converting the process variation into shape variation data; and providing the shape variation data in a text format to a scatterometry modeling program for use in the scatterometry analysis..
 One-time programmable integrated circuit security patent thumbnailnew patent One-time programmable integrated circuit security
One-time programmable integrated circuit security is described. An example of a method of protecting memory assets in an integrated circuit includes sampling values of multiple otp memory arrays and comparing the sampled value of each otp memory array with the sampled value of each other otp memory array and with an unprogrammed otp memory array value.
 Error protection for integrated circuits in an insensitive direction patent thumbnailnew patent Error protection for integrated circuits in an insensitive direction
A method for providing error detection, or error detection combined with error correction, to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding an error control mechanism to the array of storage cells in the insensitive direction. The insensitive direction is a direction perpendicular to a width of a gate conductor of the storage cells..
 Scan test circuitry comprising at least one scan chain and associated reset multiplexing circuitry patent thumbnailnew patent Scan test circuitry comprising at least one scan chain and associated reset multiplexing circuitry
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells.
 System and method for non-intrusive random failure emulation within an integrated circuit patent thumbnailnew patent System and method for non-intrusive random failure emulation within an integrated circuit
The apparatus and methods allow random hardware failure emulation of an integrated circuit (ic) by emulation of potential defects to enable behavior evaluation of the rest of the design in such situation. This emulation can non-intrusively address multiple points of failure.
 Methods and circuits for disrupting integrated circuit function patent thumbnailnew patent Methods and circuits for disrupting integrated circuit function
Methods and circuits for disrupting integrated circuit function. The circuits include finite state machines connected to memory arrays.
 Secure key storage using physically unclonable functions patent thumbnailnew patent Secure key storage using physically unclonable functions
Some implementations disclosed herein provide techniques and arrangements for provisioning keys to integrated circuits/processors. A processor may include physically unclonable functions component, which may generate a unique hardware key based at least on at least one physical characteristic of the processor.
new patent Integrated circuit device, memory interface module, data processing system and method for providing data access control
An integrated circuit device comprising at least one memory interface module arranged to be operably coupled between at least one data storage device and a plurality of master devices within a data processing system. The at least one memory interface module comprises a plurality of buffers and at least one data access control module.
new patent Method for controlling transaction exchanges between two integrated circuits
Transaction exchanges are controlled between two integrated circuits in a system having the integrated circuits (ics), a power supply supplying power to a link between the ics, thereby enabling transaction exchanges between both ics and a controller controlling the ics and the power supply. This involves receiving an order at the controller, wherein the order requires the link to be closed.
new patent Debug control circuit
An integrated circuit includes a bus; a processing unit configured to execute a user program; and a debugging circuit connected to the bus, the debugging circuit transferring a command in a command register to the processing unit via the bus in response to a command transfer request from the processing unit, wherein, when the processing unit halts the execution of the user program and makes a request for the command transfer request to the debugging circuit, the debugging circuit makes a response for freeing the use right of the bus from the processing unit in a period between the command transfer request and the command transfer operation.. .
new patent Adaptive communication interface
Embodiments of the invention include a communication interface and protocol for allowing communication between devices, circuits, integrated circuits and similar electronic components having different communication capacities or clock domains. The interface supports communication between any components having any difference in capacity and over any distance.
new patent Bioinformatics systems, apparatuses, and methods executed on an integrated circuit processing platform
A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes an integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data.
new patent Vehicle telematics unit management
A method and system for maintaining a wireless carrier system presence at a vehicle telematics unit in a vehicle includes placing the vehicle telematics unit in a quiescent mode that suspends its signal transmitting functions; instructing the vehicle telematics unit to periodically exit the quiescent mode and transmit a query that determines if the wireless carrier system used by a telematics service provider has changed; when the wireless carrier system has changed, receiving a new wireless profile associated with a new wireless carrier system; and storing the new wireless profile in a universal integrated circuit card (uicc) hardwired at the vehicle.. .
new patent Integrated package insertion and loading mechanism (ipilm)
A holding member and system including a first holding member and a second holding member, wherein each of the first holding member and the second holding member are coupled to opposite sides of a load plate of a socket. A holding member includes a body including a pair of arms extending from a first side of the body and spaced to accommodate a portion of an integrated circuit chip package therebetween and at least one clip extending from a second side opposite the first side.
new patent Electron beam plasma chamber
A method and apparatus for tailoring the formation of active species using one or more electron beams to improve gap-fill during an integrated circuit formation process is disclosed herein. The energy of the electron beams may be decreased to maximize electrons leading to radicals or increased to maximize electrons leading to ions, depending on the fill application.
new patent Hybrid conductor through-silicon-via for power distribution and signal transmission
A method of providing signal, power and ground through a through-silicon-via (tsv), and an integrated circuit chip having a tsv that simultaneously provides signal, power and ground. In one embodiment, the method comprises forming a tsv through a semiconductor substrate, including forming a via in the substrate; and forming a multitude of conductive bars in the via.
new patent Communication apparatus, integrated circuit, and communication method
In communication method for communicating via a transmission channel to which first communication apparatuses communicating based on a first communication system, second communication apparatuses communicating based on a second communication system, and third communication apparatuses communicating based on a third communication system are connected, a data transmission domain and a notification domain for notifying a data transmission within the data transmission domain are allocated to the first communication apparatuses, the second communication apparatuses, and the third communication apparatuses, respectively. In the communication method, notices of the data transmission for each of the first communication apparatuses, the second communication apparatuses and the third communication apparatuses are transmitted within the notification domain, and the data transmission domain is reallocated in accordance with the notices transmitted from the first, second and third communication apparatuses..
new patent Methods and apparatus for aligning clock signals on an integrated circuit
A method of aligning clock signals in multiple transceiver channels on an integrated circuit may include adjusting a slave clock signal at a slave transceiver channel based on a master clock signal received from a master transceiver channel. A clock generation circuit and/or a delay circuit in the slave transceiver channel may be used to adjust the slave clock signal to produce an intermediate slave clock signal.
new patent Radio communication system, base station device, mobile station device, radio communication method, and integrated circuit
In a radio communication system in which a mobile station device and a base station device communicate with each other, power of a signal from the mobile station device to the base station device is efficiently controlled. When a finally received dci format for pusch is a dci format 0 or a dci format 4 in which two transport blocks are enabled, a scheduling unit (1013) notifies, to a transmission power control unit (1015), that δpower-offset is 0.
new patent Dynamic random access memory for communications systems
An integrated circuit may comprise a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (dram) cells, and a second one or more dram cells. The first dram cell(s) may be refreshed by the memory refresh circuit whereas the second dram cell(s) is not refreshed by any memory refresh circuit.
new patent Buffering systems for accessing multiple layers of memory in integrated circuits
Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory.
new patent Integrated circuit 3d phase change memory array and manufacturing method
A 3d phase change memory device can store multiple bits per cell represented by a plurality of non-overlapping ranges of resistance all of which are established by different resistance ranges corresponding to respective amorphous phase thickness of the phase change memory material. An array of access devices can underlie a plurality of conductive layers, separated from each other and from the array of access devices by insulating layers.
new patent At least one die produced, at least in part, from wafer, and including at least one replicated integrated circuit
An embodiment may include at least one die produced, at least in part, from a wafer, and may include at least one integrated circuit and/or at least one other integrated circuit. These integrated circuits may be mutual replications of each other and may include respective core and additional blocks.
new patent Integrated circuit common-mode filters with esd protection and manufacturing method
An integrated circuit common-mode electromagnetic interference filter incorporating electro-static discharge protection comprising two inductive coils is provided. A pair of primary and secondary spiral inductor coils is disposed corresponding to each other.
new patent Circuit for and method of enabling the discharge of electric charge in an integrated circuit
A circuit for enabling the discharge of electric charge in an integrated circuit is described. The circuit comprises an input/output pad coupled to a first node; a first diode coupled between the first node and a ground node; a transistor coupled in parallel with the first diode between the first node and ground node; and a resistor coupled between a body portion of the transistor and the ground node.
new patent Backside redistribution layer patch antenna
A patch antenna system comprising: an integrated circuit die having an active side including an active layer, and a backside; a dielectric layer formed on the backside; and a redistribution layer formed on the dielectric layer wherein the redistribution layer forms an array of patches. The patch antenna further comprises a plurality of through-silicon vias (tsv), wherein the tsvs electrically connect the array of patches to the active layer..
new patent Variability and aging sensor for integrated circuits
A ring-oscillator-based on-chip sensor (ocs) includes a substrate having a semiconductor surface upon which the ocs is formed. The ocs includes an odd number of digital logic stages formed in and on the semiconductor surface including a first stage and a last stage each including at least one nor gate including a first gate stack and/or a nand gate including a second gate stack.
new patent Integrated circuit chip temperature sensor
A temperature control system having: a resistor formed in a region of a semiconductor, such resistor having a pair of spaced electrodes in ohmic contact with the semiconductor; at least one device formed in another region of the semiconductor thermally proximate the resistor formed region, such device generating heat in the semiconductor; and circuitry, including a reference connected to one of the pair of electrodes, for operating the resistor in saturation and for sensing variation in the resistor in response to the heat generated by the device and for controlling the heat generated by the device in the semiconductor in response to the sensed variation.. .
new patent Well-biasing circuit for integrated circuit
A well-biasing circuit for an integrated circuit (ic) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the ic when the integrated circuit is in stop and standby modes. A switch is connected between a core power supply and the well-bias contact for connecting and disconnecting the core power supply and the well-bias contact when the ic is in run and stop modes, and standby mode, respectively.
new patent Voltage to current converter
The invention provides a voltage to current converter that contains an diode-connected nmos transistor, a diode-connected pmos transistor, and a voltage-controlled signal input circuit. The source of the nmos transistor and the drain of the pmos transistor are connected together and connected to the voltage-controlled signal input circuit in series.
new patent Placement of storage cells on an integrated circuit
A method for configuring the placement of a plurality of storage cells on an integrated circuit includes grouping the plurality of storage cells into a plurality of words, where each of the plurality of words is protected by an error control mechanism. The method also includes placing each of the storage cells on the integrated circuit such that a distance between any two of the storage cells belonging to one of the plurality of words is greater than a minimum distance.
new patent Maintaining a wafer/wafer translator pair in an attached state free of a gasket disposed
A wafer translator and a wafer, removably attached to each other, provides the electrical connection to electrical contacts on integrated circuits on a wafer in such a manner that the electrical contacts are substantially undamaged in the process of making such electrical connections. Various embodiments of the present invention provide a gasketless sealing means for facilitating the formation by vacuum attachment of the wafer/wafer translator pair.
new patent Autonomous charge balancing circuit and method for battery pack
Systems and methods for controlling a vehicle having a traction battery with a plurality of cell groups each having a plurality of serially connected battery cells include balancing each cell of each cell group with a corresponding autonomous cell balancing circuit, and coupling a single output associated with each cell group to an associated battery monitoring circuit. An integrated driver and switch circuit adapts the voltage from an associated cell group for powering battery monitoring integrated circuits with a voltage range corresponding to a single cell voltage range to facilitate use of an existing battery monitoring integrated circuit design and subsequent input to a microprocessor-based battery controller.
new patent Chip arrangement, a method for manufacturing a chip arrangement, integrated circuits and a method for manufacturing an integrated circuit
A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material.. .
new patent Integrated circuit packaging system with molded grid-array mechanism and method of manufacture thereof
A method of manufacture of an integrated circuit packaging system includes: providing a lead-frame having a metal connector mounted thereon and having a peripheral mounting region; forming an insulation cover on the lead-frame and on the metal connector; connecting an integrated circuit die over the insulation cover; forming a top encapsulation on the integrated circuit die with the peripheral mounting region exposed from the top encapsulation; forming a routing layer, having a conductive land, from the lead-frame; and forming a bottom encapsulation partially encapsulating the routing layer and the insulation cover.. .
new patent Hybrid conductor through-silicon-via for power distribution and signal transmission
A method of providing signal, power and ground through a through-silicon-via (tsv), and an integrated circuit chip having a tsv that simultaneously provides signal, power and ground. In one embodiment, the method comprises forming a tsv through a semiconductor substrate, including forming a via in the substrate; and forming a multitude of conductive bars in the via.
new patent Trimming circuit for an integrated circuit and related integrated device
A trimming circuit is configured to carry out a trimming operation on a device portion of an integrated circuit device. The trimming circuit includes: shunt fuses wherein each shunt fuse is coupled in parallel to a trimming resistance, further resistances wherein each further resistance is coupled in parallel to a respective shunt fuse.
new patent Integration of 3d stacked ic device with peripheral circuits
An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region.
new patent Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes: an organic substrate; an integrated circuit and a chip part provided on the organic substrate; a molded section including a central portion and a peripheral portion, and forming, as a whole, a concave shape, the central portion sealing the integrated circuit and the chip part on the organic substrate, and the peripheral portion standing around the central portion; and a solid-state image pickup element provided on the central portion of the molded section, the solid-state image pickup element having a top edge that is lower in position in a thickness direction than a top edge of the peripheral portion of the molded section.. .
new patent Integrated circuits and methods for fabricating integrated circuits with improved silicide contacts
Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming over a semiconductor substrate a gate structure.
new patent Semiconductor structure with suppressed sti dishing effect at resistor region
An integrated circuit includes a semiconductor substrate; a first shallow trench isolation (sti) feature of a first width and a second sti feature of a second width in a semiconductor substrate. The first width is less than the second width.
new patent Power integrated circuit including series-connected source substrate and drain substrate power mosfets
A semiconductor device containing a high voltage mos transistor with a drain drift region over a lower drain layer and channel regions laterally disposed at the top surface of the substrate. Resurf trenches cut through the drain drift region and body region parallel to channel current flow.
new patent Semiconductor integrated circuit device and a method of manufacturing the same
Semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode.. .
new patent Metal-programmable integrated circuits
A metal-programmable integrated circuit may include an array of metal-programmable cells. Each cell may include multi-gate transistor structures in which multiple surfaces of a gate structure serve to control current flow through at least one channel structure.
new patent Finfet device and method of fabricating same
An integrated circuit structure includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate, wherein the isolation regions have opposite sidewalls facing each other. A fin structure includes a silicon fin higher than top surfaces of the isolation regions, a germanium-containing semiconductor region overlapped by the silicon fin, silicon oxide regions on opposite sides of the germanium-containing semiconductor region, and a germanium-containing semiconductor layer between and in contact with the silicon fin and one of the silicon oxide regions..
new patent Bidirectional semiconductor device for protection against electrostatic discharges
An integrated circuit is produced on a bulk semiconductor substrate in a given cmos technology and includes a semiconductor device for protection against electrostatic discharges. The semiconductor device has a doublet of floating-gate thyristors coupled in parallel and head-to-tail.
new patent Multi-chip package and interposer with signal line compression
A multi-chip package with signal line compression for testing of the multi-chip package. The multi-chip package includes an interposer and two or more integrated circuits attached to the interposer.
new patent Focal plane array processing method and apparatus
A digital focal plane array includes an all-digital readout integrated circuit in combination with a detector array. The readout circuit includes unit cell electronics, orthogonal transfer structures, and data handling structures.
new patent Terminal having image data format conversion
There is set forth herein an indicia reading terminal having data format conversion capabilities. The indicia reading terminal includes an image sensor integrated circuit with an image sensor array comprising a plurality of pixels.
new patent Treatment method of electrodeposited copper for wafer-level-packaging process flow
A method of treating a copper containing structure on a substrate is disclosed. The method includes electrodepositing the copper containing structure on a substrate, annealing the copper containing structure, and forming an interface between a pad of the copper containing structure and a solder structure after anneal.
Method of designing semiconductor integrated circuit
A method of designing a semiconductor integrated circuit, includes inserting, between a power supply voltage and a ground voltage, at least two types of capacitor cells which have a different ratio, the ratio being between an inverse number of a capacitance value of a capacitative element and a resistance value of an equivalent series resistance, such that an impedance between the power supply voltage and the ground voltage in a resonance frequency according to capacitances of the at least two types of capacitor cells and an external inductance, and an impedance between the power supply voltage and the ground voltage in a target frequency, are near respective desired values or less than or equal to the respective desired values.. .
Automatic generation of wire tag lists for a metal stack
Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition.
Method and layout of an integrated circuit
An integrated circuit layout includes a p-type active region, an n-type active region, a first metal connection, a second metal connection and a plurality of trunks. The plurality of trunks is formed substantially side-by-side, and in parallel with each other.
Adaptive workload based optimizations coupled with a heterogeneous current-aware baseline design to mitigate current delivery limitations in integrated circuits
A dynamic system coupled with “pre-silicon” design methodologies and “post-silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., controlled collapse chip connection or c4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into c4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per c4 beyond pre-established limits or periods.
Memory module architecture
In accordance with some embodiments, memory modules containing phase change memory elements may be organized so that each memory integrated circuit includes both data and error correcting code. As a result of including the error correcting code in each integrated circuit, extra accesses of the memory module to extract the error correcting code can be avoided, improving the performance of the overall memory module in some embodiments..
Accelerated cache rinse when preparing a power state transition
Methods, integrated circuit devices, and fabrication processes relating to power management transitions of a compute unit comprising a cache are presented. One method includes, responsive to an indication that the compute unit is attempting to enter a low power state, detecting at least one line of the cache differing from the corresponding line in memory, writing differing data from the at least one differing line to the memory, flushing at least one remaining differing line of the cache, and permitting the compute unit to enter the low power state, wherein the detecting and the writing are performed at a first frequency prior to the indication and at a second frequency subsequent the indication, and the second frequency is higher than the first frequency..
Software based application specific integrated circuit
A processing device is provided. A cluster includes a plurality of groups of processing elements.
Method and apparatus for dynamically allocating memory address space between physical memories
A memory address space for each of a plurality of physical memories in a microprocessor-based system is allocated prior to knowing the desired logical size of at least one of the physical memories. At least two of the allocated memory address spaces overlap at least a portion of each other.
Dual or multiple sim standby and active using a single digital baseband
An apparatus comprises two or more sim card connectors in a communication system configured to operate according to a plurality of communication protocols and coupled to at least one processor (610) for processing communication signals, a control unit (632) configured to generate a control signal to select a communication path (629-1, 629-2, 631-1, 631-2, 645-1, 647-1, 647-2) dedicated to an associated sim card connector, and a switch (630) responsive to the control signal to switch the communication signals received from or transmitted to any one of the two or more sim card connectors using the selected communication path. An apparatus comprises a plurality of radio frequency integrated circuit rfics (640-1, 640-2) coupled to a plurality of rf interfaces of a digital baseband (600) of a communication apparatus, the plurality of rfics includes a programmable state machine that executes programmed instructions to perform write to the rfics, thereby enabling rf control..
Duplex filter arrangements for use with tunable narrow band antennas having forward and backward compatibility
A transceiver module and duplexer within a communication device supports a minimized antenna volume and enhances a transfer gain for transmit and receive channels. The duplexer is communicatively coupled to one of multiple antenna and filter matching configurations which include a first configuration that couples receive and transmit filter matching circuits to a single antenna matching circuit.
Isolated wire structures with reduced stress, methods of manufacturing and design structures
An integrated circuit (ic) including a set of isolated wire structures disposed within a layer of the ic, methods of manufacturing the same and design structures are disclosed. The method includes forming adjacent wiring structures on a same level, with a space therebetween.
Methods for metal bump die assembly
Methods for assembling metal bump dies. In an embodiment, a method includes providing an integrated circuit die having a plurality of conductive terminals; depositing solder to form solder depositions on the conductive terminals; providing a substrate having a die attach region on a surface for receiving the integrated circuit die, the substrate having a plurality of conductive traces formed in the die attach region; aligning the integrated circuit die and the substrate and bringing the plurality of conductive terminals and the conductive traces into contact, so that the solder depositions physically contact the conductive traces; and selectively heating the integrated circuit die and the conductive terminals to a temperature sufficient to cause the solder depositions to melt and reflow, forming solder connections between the conductive traces on the substrate and the conductive terminals on the integrated circuit die.
Socket type mems bonding
A method for fabricating an integrated circuit device is disclosed. The method includes providing a first substrate; bonding a second substrate to the first substrate, the second substrate including a microeelectromechanical system (mems) device; and bonding a third substrate to the first substrate..
Method and apparatus for image sensor packaging
Methods and apparatus for packaging a backside illuminated (bsi) image sensor or a bsi sensor device with an application specific integrated circuit (asic) are disclosed. A bond pad array may be formed in a bond pad area of a bsi sensor where the bond pad array comprises a plurality of bond pads electrically interconnected, wherein each bond pad of the bond pad array is of a small size which can reduce the dishing effect of a big bond pad.
Method and apparatus for optical waveguide-to-semiconductor coupling and optical vias for monolithically integrated electronic and photonic circuits
An optical coupler has a waveguide coupled to a grating of multiple scattering units, each scattering unit having a first scattering element formed of a shape in a polysilicon gate layer and a second scattering element formed of a shape in a body silicon layer of a metal-oxide-semiconductor (mos) integrated circuit (ic). The couplers may be used in a system having a coupler on each of a first and second ic, infrared light being formed into a beam passing between the couplers.
Apparatus and methods for reducing common-mode noise in an imaging system
Apparatus and methods reduce common-mode error. An integrated circuit includes a plurality of signal channels, a first proxy channel, and a subtraction block.
Image recognition device, image recognition method, and integrated circuit
An image recognition device that improves the accuracy of generic object recognition compared with conventional technologies by reducing the influence of the position, size, background clutter and the like of an object that is targeted to be recognized in the input image by the generic object recognition. The image recognition device performs a generic object recognition and includes: a segmenting unit configured to segment an input image into a plurality of regions in accordance with meanings extracted from content of the input image; a generating unit configured to compute feature data for each of the plurality of regions and generate feature data of the input image reflecting the computed feature data; and a checking unit configured to check whether or not a recognition-target object is present in the input image in accordance with the feature data of the input image..
Fully integrated dc offset compensation servo feedback loop
The fully integrated dc offset compensation servo feedback loop is an integrator that measures the output signal dc component, and then feeds back and subtracts the measured dc component from the input signal. A larger integrator time constant lowers the high pass corner frequency, which must be very small in order to minimize the loss of the low frequency component of the desired signals.
Circuit substrate structure and method for manufacturing thereof
The invention provides a circuit substrate structure and a method for manufacturing thereof. The circuit substrate structure includes a substrate, a pixel array layer, a display unit, a peripheral circuit layer, at least one integrated circuit chip, a flexible printed circuit board, at least one flattening material layer and a passivation layer.
Mems device with sloped support
A microelectromechanical (mems) device has a movable member supported in elevated position spaced by a sloped support structure above a substrate. The movable member may be a polished metallic plate such as a mirror of a digital micromirror device (dmd) supported by a flexible hinge above an integrated circuit wafer die region.
Image pickup apparatus and integrated circuit therefor, image pickup method, image pickup program, and image pickup system
An imaging device generates distance information for each object in a plurality of images having the same viewpoint. During the generation, the imaging device detects distances from the viewpoint to some of the objects intermittently, and estimates the distances from the viewpoint to the other objects using the detected distances.

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