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Integrated Circuit patents

      

This page is updated frequently with new Integrated Circuit-related patent applications.




 System,  interconnecting circuit boards patent thumbnailSystem, interconnecting circuit boards
In one embodiment, first and second circuit boards may be coupled together. The first circuit board may include a first trace to electrically couple a first integrated circuit to a first via of the first circuit board.
Intel Corporation


 Wavy interconnect for bendable and stretchable devices patent thumbnailWavy interconnect for bendable and stretchable devices
Embodiments of the present disclosure describe a wavy interconnect for bendable and stretchable devices and associated techniques and configurations. In one embodiment, an interconnect assembly includes a flexible substrate defining a plane and a wavy interconnect disposed on the flexible substrate and configured to route electrical signals of an integrated circuit (ic) device in a first direction that is coplanar with the plane, the wavy interconnect having a wavy profile from a second direction that is perpendicular to the first direction and coplanar with the plane.
Intel Corporation


 Terminal device and integrated circuit patent thumbnailTerminal device and integrated circuit
Throughput is improved in a wireless environment in which various types of interference are caused. Included are a reception unit that receives a first reference signal which corresponds to the base station apparatus and a second reference signal which is based on interference information that is configured by the base station apparatus; a channel state information generation unit that generates channel state information based on the first reference signal and the second reference signal; and a transmission unit that transmits the channel state information to the base station apparatus.
Sharp Kabushiki Kaisha


 Terminal device, base station apparatus, and integrated circuit patent thumbnailTerminal device, base station apparatus, and integrated circuit
Degradation in reception performance due to interference is reduced while suppressing control information from increasing. A terminal device receives a first reception signal and a second reception signal, includes a higher layer processing unit that determines naics information indicating whether it is indicated in a higher layer that naics has to be applied, and a control unit that performs control in such a manner that, in a case where the naics is configured in the higher layer, an ack/nack of the first reception signal is transmitted and an ack/nack of the second reception signal is not transmitted.
Sharp Kabushiki Kaisha


 Method for determining and recovering from loss of synchronization, communication units and integrated circuits therefor patent thumbnailMethod for determining and recovering from loss of synchronization, communication units and integrated circuits therefor
A method of recovery from a time-synchronization loss in a communication unit between a first processor supporting physical layer communications and a second processor supporting layer-2 communications is described. The method comprises: detecting, by the first processor, that a loss of sync has occurred between the first and second processors; in response to said detecting, stopping sending subsequent physical layer messages from the first processor to the second processor, for example to allow the second processor to consume any old pending messages; re-starting a messaging process by the first processor by sending at least one new message to the second processor with updated system frame number, sfn, and sub-frame, sf, counter value; and receiving at the first processor at least one subsequent response message from the second processor acknowledging receipt of at least one new message with an indication of the received and updated sfn and sf counter value of that message thereby confirming synchronization being restored..
Freescale Semiconductor, Inc.


 Terminal device, base station device, communication system, control method, and integrated circuit patent thumbnailTerminal device, base station device, communication system, control method, and integrated circuit
In a terminal device that uses a plurality of cells, the plurality of cells are grouped into a cell group for a first base station device and a cell group for a second base station device, and processing for activation/deactivation of the plurality of cells is performed on a cell in the cell group that receive a control element indicating the activation/deactivation, and in a case where the cell group for the second base station is added, a power headroom indicating capacity available for transmit power in the plurality of cells is determined as being triggered, and power headrooms of the plurality of cells that are activated are reported.. .
Sharp Kabushiki Kaisha


 Tamper prevention for electronic subscriber identity module (esim) type parameters patent thumbnailTamper prevention for electronic subscriber identity module (esim) type parameters
Disclosed herein are various techniques for preventing or at least partially securing parameters—e.g., type parameters—of electronic subscriber identity modules (esims) stored within an embedded universal integrated circuit card (euicc) from being inappropriately modified by mobile network operators (mnos). One embodiment sets forth a technique that involves modifying file access properties of the type parameters of esims to make the type parameters readable, but not updatable by the mnos.
Apple Inc.


 Projection system, semiconductor integrated circuit, and image correction method patent thumbnailProjection system, semiconductor integrated circuit, and image correction method
A projection apparatus projects pattern light onto an object, the pattern light including pattern images corresponding to information that indicates coded projection coordinates in a projection coordinate system. Each of the pattern images includes two or more continuous areas.
Panasonic Intellectual Property Corporation Of America


 Integrated circuit with parts activated based on intrinsic features patent thumbnailIntegrated circuit with parts activated based on intrinsic features
A fixed logic integrated circuit is disclosed. The integrated circuit comprises a unique code generator configured to generate a code having a value which is intrinsically unique to the integrated circuit, an enrolment pattern generator configured to generate an enrolment pattern based on the unique code.
Renesas Electronics Europe Gmbh


 Receiving apparatus, receiving method and integrated circuit patent thumbnailReceiving apparatus, receiving method and integrated circuit
A radio communication apparatus is disclosed that enables the influence of the feedback information on the channel capacity to be kept to the minimum without reducing the transmission efficiency of information by transmission of pilot symbol. In the apparatus, a delay dispersion measuring section generates a delay profile using the received signal, and measures delay dispersion indicative of dispersion of delayed versions.
Godo Kaisha Ip Bridge 1


Integrated circuit

Wireless communication wherein channel estimation accuracy is improved while keeping the position of each bit in a frame, even when a modulation system having a large modulation multiple value is used for a data symbol. An encoding operation encodes and outputs transmitting data (bit string) and a bit converting operation converts at least one bit of a plurality of bits constituting a data symbol to be used for channel estimation, among the encoded bit strings, into ‘1’ or ‘0’.
Panasonic Corporation

Semiconductor integrated circuits

A semiconductor integrated circuit includes a scan enable (se) inverter and a clock (ck) inverter on a substrate, a first multiplex part, and a second multiplex part. The se inverter and the ck inverter are aligned in a first direction.

Semiconductor integrated circuit

According to one embodiment, a semiconductor integrated circuit comprises: a first flip-flop including a first input circuit, a first latch, a second latch, and a first output circuit; a second flip-flop including a second input circuit, a third latch, a fourth latch, and a second output circuit; and a clock buffer configured to output a common clock signal to the first flip-flop and the second flip-flop. A first output terminal of the second latch is coupled to an input terminal of the first output circuit, and a second output terminal of the second latch is directly coupled to an input terminal of the second input circuit..
Kabushiki Kaisha Toshiba

Radio frequency circuitr having an integrated harmonic filter and a radio frequency circuit having transistors of different threshold voltages

An integrated circuit that includes a die with an active radio frequency (rf) unit embedded thereon; a first port for receiving an output signal from the active rf unit; a harmonic filter that comprises a first harmonic filter inductor; and a first rf inductive load that is electrically coupled to the first port and is magnetically coupled to the first harmonic filter inductor.. .
Dsp Group Ltd.

Method and sensing multiple voltage values from a single terminal of a power converter controller

A method for regulating an output of a power converter includes receiving a signal at a single terminal of an integrated circuit controller. The signal at the single terminal represents a line input voltage of the power converter during at least a portion of an on time of a power switch.
Power Integrations, Inc.

Cosmetically hidden electrostatic discharge protection structures

Cosmetically hidden electrostatic discharge (esd) protection structures and systems are disclosed herein. In one example, an electronic device is provided.
Microsoft Technology Licensing, Llc

Flip-chip employing integrated cavity filter, and related components, systems, and methods

A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (ic) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive “fence” that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip.
Qualcomm Incorporated

Embedded memory in interconnect stack on silicon die

A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein forming ones of the plurality of first interconnects and a plurality of second interconnects includes embedding memory devices therein. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein ones of the plurality of first interconnects and a plurality of second interconnects includes memory devices embedded therein..
Intel Corporation

Method of manufacture for single crystal capacitor dielectric for a resonance circuit

A method of manufacturing an integrated circuit. This method includes forming an epitaxial material comprising single crystal piezo material overlying a surface region of a substrate to a desired thickness and forming a trench region to form an exposed portion of the surface region through a pattern provided in the epitaxial material.
Akoustis, Inc.

Field-effect transistor, and memory and semiconductor circuit including the same

Provided is a field-effect transistor (fet) having small off-state current, which is used in a miniaturized semiconductor integrated circuit. The field-effect transistor includes a thin oxide semiconductor which is formed substantially perpendicular to an insulating surface, a gate insulating film formed to cover the oxide semiconductor, and a gate electrode which is formed to cover the gate insulating film.
Semiconductor Energy Laboratory Co., Ltd.

Graphene fluorination for integration of graphene with insulators and devices

Embodiments of the present disclosure describe multi-layer graphene assemblies including a layer of fluorinated graphene, dies and systems containing such structures, as well as methods of fabrication. The fluorinated graphene provides an insulating interface to other graphene layers while maintaining the desirable characteristics of the nonfluorinated graphene layers.
Intel Corporation

Semiconductor structure, integrated circuit device, and forming semiconductor structure

A semiconductor structure, integrated circuit device, and method of forming semiconductor structure are provided. In various embodiments, the semiconductor structure includes a substrate containing a high topography region and a low topography region, an outer protection wall on an outer peripheral portion of the high topography region next to the low topography region, and an anti-reflective coating over the outer protection wall, the high topography region, and the low topography region..
Taiwan Semiconductor Manufacturing Co., Ltd.

Display device

A display device is disclosed. In one aspect, the display device includes a substrate including a display area and a non-display area and an input wiring portion and an output wiring portion formed in the non-display area.
Samsung Display Co., Ltd.

Integrated circuit device and manufacturing same

A method for manufacturing an integrated circuit device includes forming a first film on a foundation member. A recess is made in a surface of the foundation member.
Kabushiki Kaisha Toshiba

Semiconductor integrated circuit device and a manufacturing the same

A semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode.. .
Renesas Electronics Corporation

Semiconductor integrated circuit

A semiconductor integrated circuit includes a substrate, a multi-gate transistor device positioned on the substrate, and an ldmos device positioned on the substrate. The substrate includes a plurality of first isolation structures and a plurality of second isolation structures.
United Microelectronics Corp.

Integrated circuit composed of tunnel field-effect transistors and manufacturing same

The present invention provides an integrated circuit formed of tunneling field-effect transistors that includes a first tunneling field-effect transistor in which one of a first p-type region and a first n-type region operates as a source region and the other one operates as a drain region; and a second tunneling field-effect transistor in which one of a second p-type region and a second n-type region operates as a source region and the other one operates as a drain region, the first and second tunneling field-effect transistors being formed in one active region to have the same polarity, the first p-type region and the second n-type region being formed adjacently, the adjacent first p-type region and second n-type region being electrically connected through metal semiconductor alloy film.. .
National Institute Of Advanced Industrial Science And Technology

Method of forming 3d integrated circuit package with panel type lid

Presented herein is a package comprising a carrier device of a device stack and at least one top device of the device stack mounted on a first side of the carrier device. A lid is mounted on the first side of the carrier device, with a first portion of the lid attached to the carrier device and a second portion of the lid extending past and overhanging a respective edge of the carrier device.
Taiwan Semiconductor Manufacturing Company, Ltd.

Making electrical components in handle wafers of integrated circuit packages

A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region.
Invensas Corporation

Monolithic microwave integrated circuits

Low q associated with passive components of monolithic integrated circuits (ics) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 ohm-cm) semiconductor substrates and lower resistance inductors for the ic. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate.
Freescale Semiconductor, Inc.

Via bottom structure and methods of forming

Various embodiments include methods and integrated circuit structures. One method includes: forming a via opening through a trench to expose a portion of an underlying metal line; electrolessly plating a metal layer at a bottom of the via opening over the exposed portion of the underlying metal line, the electrolessly plated metal layer formed of a metal not including copper; depositing a cobalt layer to cover the bottom of the via opening over the electrolessly plated metal layer and sidewalls of the via opening; and growing a copper layer over the cobalt layer to form a line within the trench and a via filling the via opening..
International Business Machines Corporation

Metal on both sides with clock gated-power and signal routing underneath

A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and forming contact points to the second plurality of interconnects, the contact points operable for connection to an external source. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and contact points coupled to the second plurality of interconnects, the contact points operable for connection to an external source..
Intel Corporation

Unidirectional metal on layer with ebeam

Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (cebl) are described. In an example, a layout for a metallization layer of an integrated circuit includes a first region having a plurality of unidirectional lines of a first width and a first pitch and parallel with a first direction.
Intel Corporation

Three-dimensional integrated circuit integration background

Wiring structures, methods for providing a wiring structure, and methods for distributing currents with a wiring structure from one or more through-substrate vias to multiple bumps. A first current is directed from a first through-substrate via of a first electrical resistance through a first connection line to a first bump and directing a second current from the first through-substrate via through a second connection line of a second electrical resistance to a second bump.
International Business Machines Corporation

Method to improve analog fault coverage using test diodes

Implementations of integrated circuits may include: one or more diodes each having an anode and a cathode, each of the one or more diodes may be coupled with a voltage domain. One or more test pins may be coupled with one or more diodes.
Semiconductor Components Industries, Llc

Monolithic wideband trifilar transformer

Transformers that provide impedance transformations within integrated circuits (ics) are disclosed. Embodiments of the transformers may include a plurality of conductors connected in series within one another wherein the conductors are arranged to form transmission lines.
Triquint Semiconductor, Inc.

Semiconductor integrated circuit adapted to output pass/fail results of internal operations

In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.. .
Kabushiki Kaisha Toshiba

Structure and a sram circuit

The present disclosure provides an integrated circuit formed in a semiconductor substrate. The integrated circuit includes a first static random access memory (sram) cell having a first cell size; and a second sram cell having a second cell size greater than the first cell size.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor integrated circuit capable of precisely adjusting delay amount of strobe signal

An interface circuit provided in a semiconductor device supplies an operation clock to an external memory device based on a clock signal (ck) and receives a data signal (dq) and a strobe signal (dqs) from the external memory device. The interface circuit includes a delay circuit delaying the received strobe signal (dqs).
Renesas Electronics Corporation

Driver integrated circuit (ic) chip and display device having the same

A driver integrated circuit (ic) chip includes gamma voltage generators, a line selector, and a data driver. The gamma voltage generators generate gamma voltage sets based on a reference voltage set.
Samsung Display Co., Ltd.

Display frame buffer compression

Techniques are disclosed relating to rendering display frames. In one embodiment, an integrated circuit is disclosed that includes display pipeline circuitry configured to produce, for a display device, a sequence of frames that includes a first frame and a second, subsequent frame.
Apple Inc.

Integrated circuit design

A computer-implemented method of integrated circuit design comprises: using a computer, producing an integrated circuit layout for multiple instances of a circuitry element, wherein interface components in one instance of said circuitry element communicate with complementary interface components in an adjacent instance of said circuitry element, said interface components being identical between said multiple instances; said producing step comprising: for one instance of said circuitry element, generating an integrated circuit layout for said one instance of said circuitry element on the basis of timing parameters of said complementary interface components with which said one instance communicates in use; detecting timing characteristics of said interface components of said one instance of said circuitry element; applying said detected timing characteristics as said timing parameters of said complementary interface components; and repeating said generating step.. .
Arm Limited

Contact resistance mitigation

Various implementations described herein are directed to systems and methods for mitigating contact resistance. In one implementation, a method may include analyzing operating conditions for cells of an integrated circuit.
Arm Limited

Power-density-based clock cell spacing

Techniques for power-density-based clock cell spacing and resulting integrated circuits (ics) are disclosed herein. In one example, the techniques determine power-usage density for different types of clock cells, as power-usage density relates to heat and ir droop.
Qualcomm Incorporated

Input/output signal bridging and virtualization in a multi-node network

In an aspect, an integrated circuit obtains a set of general purpose input/output (gpio) signals for one or more peripheral devices, obtains a first virtual gpio packet that includes the set of gpio signals independent of a central processing unit, and transmits the first virtual gpio packet to the one or more peripheral devices over an i3c bus independent of the central processing unit. The integrated circuit may further obtain a set of configuration signals for configuring one or more gpio pins of the one or more peripheral devices, obtain a second virtual gpio packet that includes the set of configuration signals independent of the central processing unit, and transmit the second virtual gpio packet to the one or more peripheral devices over the i3c bus independent of the central processing unit..
Qualcomm Incorporated

Integrated circuit

An integrated circuit, preferably for controlling vehicle functions, having an analog-digital converter for converting an analog signal into digital measurement values, a dsp unit, connected downstream from the analog-digital converter, for pre-processing the digital measurement values, a central computing unit, connected to the dsp unit so as to transmit data, for further processing of the digital measurement values, the dsp unit being set up to control the analog-digital converter during operation.. .
Robert Bosch Gmbh

Touch input device, vehicle comprising touch input device, and manufacturing touch input device

A touch input device comprising a touch device with which a user is capable of inputting a touch gesture, wherein the touch device includes a base, of which a surface has a concave shape, wherein a depth of the base is gradually increased from an outer portion toward a center portion or is uniformly maintained, a pattern groove formed in the surface of the base, a sense pattern provided in the pattern groove and including a conductive material, a wire for connecting the sense pattern to an integrated circuit, and a coating layer stacked on the base.. .
Hyundai Motor Company

Thermal shield can for improved thermal performance of mobile devices

The invention is directed to a novel solution for improving heat management in computing devices by using thermally active material integrated within a shield can disposed over an integrated circuit or printed circuit board. By integrating the thermally active material within the shield can, isothermal conditions can be maintained for a longer period of time, thereby extending the transient state of a heat-producing system for longer durations, while maintaining slim vertical profiles..
Nvidia Corporation

Current reference circuit and semiconductor integrated circuit including the same

A current reference circuit and a semiconductor ic including the current reference circuit, the current reference circuit including a proportional to absolute temperature (ptat) current generator configured to generate, in an output branch, a first current proportional to a temperature; and a current subtractor configured to generate a reference current by subtracting a second current generated based on a current flowing in an internal branch of the ptat current generator, from the first current flowing in the output branch. The second current is set to have a same temperature-based change characteristic as the first current and a level different from a level of the first current..
Samsung Electronics Co., Ltd.

Display panel structure

A display panel includes a gate integrated circuit, a number of scan lines extending from the gate integrated circuit for transmitting scan signals, a source integrated circuit, a number of data lines extending from the source integrated circuit for transmitting data signals, a number of pixel electrodes for receiving the scan signals and the data signals, and a number of transistors each electrically coupled to a corresponding scan line, a corresponding data line, and a corresponding pixel electrode. The transistors each include a gate electrode, a source electrode, and a drain electrode.
Century Technology (shenzhen) Corporation Limited





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This listing is a sample listing of patent applications related to Integrated Circuit for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Integrated Circuit with additional patents listed. Browse our RSS directory or Search for other possible listings.


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