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Instruction Set

Instruction Set-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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Control transfer termination instructions of an instruction set architecture (isa)
Intel Corporation
October 12, 2017 - N°20170293775

In an embodiment, the present invention includes a processor having an execution logic to execute instructions and a control transfer termination (ctt) logic coupled to the execution logic. This logic is to cause a ctt fault to be raised if a target instruction of a control transfer instruction is not a ctt instruction. Other embodiments are described and claimed.
Message handler compiling and scheduling in heterogeneous system architectures
Advanced Micro Devices, Inc.
October 12, 2017 - N°20170293499

A receiving node in a computer system that includes a plurality of types of execution units receives an active message from a sending node. The receiving node compiles an intermediate language message handler corresponding to the active message into a machine instruction set architecture (isa) message handler and the receiver executes the isa message handler on a selected one of ...
Techniques to provide run-time protections using immutable regions of memory
Intel Corporation
October 05, 2017 - N°20170285987

Various embodiments are generally directed to an apparatus, method and other techniques for determining a region of the memory for which to store information, inserting the information into the region of the memory, and applying one or more characteristics to the region of the memory via an instruction set architecture (isa) operation, the one or more characteristics comprising an immutable ...
Instruction Set Patent Pack
Download 137+ patent application PDFs
Instruction Set Patent Applications
Download 137+ Instruction Set-related PDFs
For professional research & prior art discovery
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  • 137+ full patent PDF documents of Instruction Set-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Exception handling in processor using branch delay slot instruction set architecture
Imagination Technologies Limited
September 28, 2017 - N°20170277539

A processor employs hardware to save the program counter value of the next instruction to be executed in a branch instruction when an exception occurs. This is the branch target address in the case where the exception occurs in the delay slot of a taken branch. The value is saved to a register when an exception occurs. The kernel code ...
Transmission for a powertrain system
Gm Global Technology Operations Llc
September 21, 2017 - N°20170268669

A transmission variator includes a first pulley rotatably attached to an intermediate member of a geartrain, and a second pulley rotatably attached to an output member that is rotatably coupled to the driveline. The geartrain includes an input member, a planetary gear set, a first clutch, a second clutch and an intermediate member. The second clutch is a low drag ...
Isa-ported container images
International Business Machines Corporation
September 07, 2017 - N°20170255462

A software container image that includes components dependent on a first computer instruction set architecture (isa) is ported to enable a container to execute using the container image on a computer having a second isa different from the first. Porting the container image entails replacing components of the container image not compatible with the second isa with equivalent components compatible ...
Instruction Set Patent Pack
Download 137+ patent application PDFs
Instruction Set Patent Applications
Download 137+ Instruction Set-related PDFs
For professional research & prior art discovery
inventor
  • 137+ full patent PDF documents of Instruction Set-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Instruction set for supporting wide scalar pattern matches
Intel Corporation
August 24, 2017 - N°20170242703

A processor includes an instruction decoder to receive an instruction having a first operand, a second operand, and a third operand, and an execution unit coupled to the instruction decoder to execute the instruction, the execution unit to individually perform a shift operation by at least one bit for each of a plurality of data elements stored in a storage ...
Compiler for translating between a virtual image processor instruction set architecture (isa) and target hardware ...
Google Inc.
August 24, 2017 - N°20170242669

A method is described that includes translating higher level program code including higher level instructions having an instruction format that identifies pixels to be accessed from a memory with first and second coordinates from an orthogonal coordinate system into lower level instructions that target a hardware architecture having an array of execution lanes and a shift register array structure that ...
Non-commission pai gow poker games, devices, systems and methods thereo
Google Inc.
August 24, 2017 - N°20170239556

Methods of playing commission-free pai gow poker games are disclosed. The commission-free pai gow poker games have multiple features, including a novel push mechanise and a novel copy-fostering mechanism, that provide a gaming establishment with an adequate house edge without the need to charge a commission on player wins. The features of the commission-free pai gow poker games may be ...
Remote diagnostics of respiratory therapy devices
Resmed Limited
August 24, 2017 - N°20170239432

A system and method is disclosed for performing diagnostics on patient devices (720). The patient devices (720) may include respiratory therapy devices that operate in accordance with instruction sets, such as software or firmware. A server (710) may maintain a database of diagnostic data (718) indicating faults in one or more of a plurality of patient devices (720). The server (710) may transmit this diagnostic data (718) ...
Configurable and programmable multi-core architecture with a specialized instruction set for embedded application based on ...
Synopsys, Inc.
August 17, 2017 - N°20170236053

A programmable architecture specialized for convolutional neural networks (cnns) processing such that different applications of cnns may be supported by the presently disclosed method and apparatus by reprogramming the processing elements therein. The architecture may include an optimized architecture that provides a low-area or footprint and low-power solution desired for embedded applications while still providing the computational capabilities required for ...
Instruction element variability
International Business Machines Corporation
August 17, 2017 - N°20170235810

One or more processors receive one or more variations to one or more first instruction elements in a first instruction set that indicate one or more second instruction elements of a second instruction set. One or more processors determine whether the one or more first instruction elements exceed a threshold of variability. One or more processors determine whether the one ...
Instruction element variability
International Business Machines Corporation
August 17, 2017 - N°20170235778

One or more processors receive one or more variations to one or more first instruction elements in a first instruction set that indicate one or more second instruction elements of a second instruction set. One or more processors determine whether the one or more first instruction elements exceed a threshold of variability. One or more processors determine whether the one ...
Instruction Set Patent Pack
Download 137+ patent application PDFs
Instruction Set Patent Applications
Download 137+ Instruction Set-related PDFs
For professional research & prior art discovery
inventor
  • 137+ full patent PDF documents of Instruction Set-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Information processing apparatus, information processing method, and storage medium storing program
Canon Kabushiki Kaisha
August 17, 2017 - N°20170235526

When communicating with a printing apparatus used for the print function of an application, communication with the printing apparatus is requested of a second layer constituted by an instruction set which is translated in advance to be able to execute the instruction set by a processor, in a first layer constituted by a script instruction set which is translated to ...
Information processing apparatus, control method for information processing apparatus, and non-transitory computer-readable storage medium
Canon Kabushiki Kaisha
August 10, 2017 - N°20170228199

An information processing apparatus capable of performing a software program including a first program layer with an instruction set to be interpreted and performed by a processor and a second program layer with an instruction set compiled in advance by a unit other than the processor comprises a unit configured to transmit parameter information used for image processing from the ...
Automated title decision processing system
Copart, Inc.
August 03, 2017 - N°20170221074

A system for vehicle title reassignment for vehicles has first and second tables of qualification. The first table defines a definable set of rules for selecting a state to retitle a vehicle responsive to a plurality of input parameters. The second table defines a second definable set of rules for selecting a title brand to retitle the vehicle responsive to ...
Processing unit, in-memory data processing apparatus and method
Electronics And Telecommunications Research Institute
July 27, 2017 - N°20170213581

A processing unit, and an in-memory data processing apparatus. The in-memory data processing apparatus includes a memory storing data at a determined location, a plurality of selector units selecting a data set to be used for an operation from among the stored data, and a plurality of processing units performing the operation using an instruction set sequentially received from an ...
Instruction set and micro-architecture supporting asynchronous memory access
Ati Technologies Ulc
July 27, 2017 - N°20170212760

A system and method for reducing latencies of main memory data accesses are described. A non-blocking load (nbld) instruction identifies an address of requested data and a subroutine. The subroutine includes instructions dependent on the requested data. A processing unit verifies that address translations are available for both the address and the subroutine. The processing unit continues processing instructions with ...
Reduced instruction set controller for diamond nitrogen vacancy sensor
Lockheed Martin Corporation
July 27, 2017 - N°20170212181

Systems, controllers, and configurations are disclosed for providing precisely timed laser actuation, rf waveform control, and synchronous acquisition of fluorescence information from magnetometry components, such as a dnv sensor. A controller for a dnv sensor may include a rf waveform generator for generating a rf waveform for a rf signal for a dnv sensor and a digital control for controlling ...
System and method for controlling a continuously variable transmission
Gm Global Technology Operations Llc
July 27, 2017 - N°20170211700

A continuously variable transmission (cvt) for a vehicle includes an input member, an output member and a variator assembly including a first pulley rotatably coupled to the input member and a second pulley rotatably coupled to the output. The first and second pulleys are rotatably coupled by a flexible continuous rotatable device. A control system is provided including an instruction ...
Scalable compute fabric
Intel Corporation
July 20, 2017 - N°20170206113

A method and apparatus for providing a scalable compute fabric are provided herein. The method can include determining a workflow for processing by the scalable compute fabric, wherein the workflow is based on an instruction set. A pipeline can be configured dynamically for processing the workflow, and the workflow is executed using the pipeline. A computing device can include a ...
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