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Instruction Set

Instruction Set-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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Offloading execution of an application by a network connected device
Advanced Micro Devices, Inc.
December 07, 2017 - N°20170353397

A client device detects one or more servers to which an application can be offloaded. The client device receives information from the servers regarding their graphics processing unit (gpu) compute resources. The client device selects one of the servers to offload the application based on such factors as the gpu compute resources, other performance metrics, power, and bandwidth/latency/quality ...
Method and apparatus for allocating hardware acceleration instruction to memory controller
Huawei Technologies Co., Ltd.
December 07, 2017 - N°20170351525

A method and an apparatus for allocating a hardware acceleration instruction to a memory controller to balance load of memory controllers, where the method includes, after dividing a plurality of hardware acceleration instructions into different instruction sets according to dependency relationships among the plurality of hardware acceleration instructions, a first mapping relationship between the instruction sets and memory controllers in ...
Unaligned instruction relocation
International Business Machines Corporation
December 07, 2017 - N°20170351501

In one embodiment, a computer-implemented method includes receiving source code to be compiled into an executable file for an unaligned instruction set architecture (isa). Aligned assembled code is generated, by a computer processor. The aligned assembled code complies with an aligned isa and includes aligned processor code for a processor and aligned accelerator code for an accelerator. A first linking ...
Instruction Set Patent Pack
Download 137+ patent application PDFs
Instruction Set Patent Applications
Download 137+ Instruction Set-related PDFs
For professional research & prior art discovery
inventor
  • 137+ full patent PDF documents of Instruction Set-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Cpu obfuscation for cloud applications
International Business Machines Corporation
November 30, 2017 - N°20170344757

A cloud deployment system is used for obfuscating cpu operation codes in a set of machines operating in a distributed computing environment. A reprogrammable microcode replaces a hardware instruction set, the microcode layer containing a set of original operation codes. A first transform of the set of original operation codes produces a first set of transformed operation codes. A first ...
Belt drive system for an internal combustion engine
Gm Global Technology Operations Llc
November 30, 2017 - N°20170343083

A belt drive system for rotatably coupling an internal combustion engine to an electric machine is described. The belt drive system includes a serpentine belt and a hydraulic strut tensioner, wherein the hydraulic strut tensioner is disposed to exert a tension force on the serpentine belt. A controller is operatively connected to the electric machine and includes an instruction set ...
Variable glyph encoding
Blackberry Limited
November 23, 2017 - N°20170337902

A system and method for graphically encoding text. A textual data set comprising a plurality of encoded text characters that corresponding to at least one text character to be visually rendered is received. Based on the textual data set, a drawing instruction set is determined that has a respective drawing instruction to draw at least part of a glyph of ...
Instruction Set Patent Pack
Download 137+ patent application PDFs
Instruction Set Patent Applications
Download 137+ Instruction Set-related PDFs
For professional research & prior art discovery
inventor
  • 137+ full patent PDF documents of Instruction Set-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Apparatus for hardware accelerated machine learning
1026 Labs, Inc.
November 09, 2017 - N°20170323224

An architecture and associated techniques of an apparatus for hardware accelerated machine learning are disclosed. The architecture features multiple memory banks storing tensor data. The tensor data may be concurrently fetched by a number of execution units working in parallel. Each operational unit supports an instruction set specific to certain primitive operations for machine learning. An instruction decoder is employed ...
Information assurance system for secure program execution
The Boeing Company
November 09, 2017 - N°20170323098

An enhanced information assurance system may comprise an improved computer including a central processing unit (cpu) emulator configured to extend the available machine instruction set. The cpu emulator may be configured to emulate machine language instructions taken from a nonnative set of secure opcodes. The cpu emulator may ensure that instructions and data in random access memory (ram) remain encrypted ...
Method and apparatus for matching vehicle ecu programming to current vehicle operating conditions
Zonar Systems, Inc.
November 09, 2017 - N°20170322907

Disclosed herein are techniques for implementing vehicle ecu reprogramming, so the ecu programming, which plays a large role in vehicle performance characteristics, is tailored to current operational requirements, which may be different than the operational characteristics selected by the manufacturer when initially programming the vehicle ecu (or ecus) with specific instruction sets, such as fuel maps. In one embodiment, a ...
Engine-agnostic event monitoring and predicting systems and methods
Wal-mart Stores, Inc.
November 09, 2017 - N°20170322806

Embodiments relate to event monitoring, identifying and predicting system comprises at least one database comprising an incoming data stream; a plurality of available data processing engines, each of the plurality of available data processing engines requiring an engine-specific event identifying instruction set; an abstraction engine configured to receive at least one engine-agnostic event identifying instruction set and convert the at ...
Method and system for supporting intelligent export and integration of analytic system data
Wal-mart Stores, Inc.
November 02, 2017 - N°20170316447

A system and methods configured for intelligent export and integration of analytics system data, by which user input either drives or controls a control mechanism (e. G., instruction set or a programming language), which allows or executes export of data into downstream databases and programs in a way that allows direct use of the data by those systems without use ...
Microprocessor with supplementary commands for binary search and associated search method
Wal-mart Stores, Inc.
November 02, 2017 - N°20170315808

A microprocessor for a vehicle control device includes: an instruction set; a register section with a status register, a first flag being provided in the status register for storing a logical result of a comparison operation; and an arithmetic logical unit. The status register comprises a second flag for storing the logical result of a second comparison operation. The instruction ...
Architecture and instruction set to support integer division
Wal-mart Stores, Inc.
November 02, 2017 - N°20170315779

A processor includes a core and a plurality of registers including a first register, a second register, and a third register. The core is configured to perform a division operation that includes execution of a sign extraction instruction in which a sign of at least one of a numerator value and a denominator value is stored, a conditional subtraction instruction ...
Instruction Set Patent Pack
Download 137+ patent application PDFs
Instruction Set Patent Applications
Download 137+ Instruction Set-related PDFs
For professional research & prior art discovery
inventor
  • 137+ full patent PDF documents of Instruction Set-related inventions.
  • Exact USPTO filing data with full-text, images, drawings & claims.
  • Index pages: Table View and Image-Grid View layouts. All images in each PDF.
Architecture and instruction set for implementing advanced encryption standard (aes)
Intel Corporation
October 26, 2017 - N°20170310470

A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, ...
Architecture and instruction set for implementing advanced encryption standard (aes)
Intel Corporation
October 26, 2017 - N°20170310469

A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, ...
Architecture and instruction set for implementing advanced encryption standard (aes)
Intel Corporation
October 26, 2017 - N°20170310468

A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, ...
Architecture and instruction set for implementing advanced encryption standard (aes)
Intel Corporation
October 26, 2017 - N°20170310467

A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, ...
Architecture and instruction set for implementing advanced encryption standard (aes)
Intel Corporation
October 26, 2017 - N°20170310466

A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, ...
Architecture and instruction set for implementing advanced encryption standard (aes)
Intel Corporation
October 26, 2017 - N°20170310465

A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, ...
Architecture and instruction set for implementing advanced encryption standard (aes)
Intel Corporation
October 26, 2017 - N°20170310464

A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, ...
Architecture and instruction set for implementing advanced encryption standard (aes)
Intel Corporation
October 26, 2017 - N°20170310463

A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, ...
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