|| List of recent Hard Mask-related patents
|Method for manufacturing small-size fin-shaped structure|
A method for manufacturing a small-size fin-shaped structure, comprising: forming a first mask layer and a second mask layer on a substrate in sequence; etching the first mask layer and the second mask layer to form a hard mask pattern, wherein a second mask layer pattern is wider than a first mask layer pattern; eliminating the second mask layer pattern; and performing a dry etching of the substrate by taking the first mask layer pattern as a mask, so as to form a fin-shaped structure. According to the method for manufacturing a small-size fin-shaped structure of the present invention, firstly a large-size hard mask is prepared, then a width controllable small-size hard mask is prepared through a wet corrosion, and finally the bulk silicon wafer is etched, so as to obtain the required small-size fin-shaped structure, thereby improving the electrical properties and the integration level of the device, simplifying the processes and reducing the cost..
|Method of forming a metal contact opening with a width that is smaller than the minimum feature size of a photolithographically-defined opening|
The width of a metal contact opening is formed to be smaller than the minimum feature size of a photolithographically-defined opening. The method forms the metal contact opening by first etching the fourth layer of a multilayered hard mask structure to have a number of trenches that expose the third layer of the multilayered hard mask structure.
|Method for forming resistance-switching memory cell with multiple electrodes using nano-particle hard mask|
In a fabrication process for reversible resistance-switching memory cells, a bottom electrode layer is coated with nano-particles. The nano-particles are used to etch the bottom electrode layer, forming multiple narrow, spaced apart bottom electrode structures for each memory cell.
|Finfet/tri-gate channel doping for multiple threshold voltage tuning|
An embodiment method of controlling threshold voltages in a fin field effect transistor (finfet) includes forming a dummy gate over a central portion of a fin, the central portion of the fin disposed between exterior portions of the fin unprotected by the dummy gate, removing the exterior portions of the fin and replacing the exterior portions of the fin with an epitaxially-grown silicon-containing material, applying a spin-on resist over the dummy gate and the epitaxially-grown silicon-containing material and then removing the spin-on resist over the hard mask of the dummy gate, etching away the hard mask and a polysilicon of the dummy gate to expose a gate oxide of the dummy gate, the gate oxide disposed over the central portion of the fin, and implanting ions into the central portion of the fin through the gate oxide disposed over the central portion of the fin.. .
|Method of manufacturing mram memory elements|
A stt-mram comprises a method to form magnetic random access memory (mram) element array having ultra small dimensions using double photo exposures and etch of their hard masks. The memory cells are located at the cross section of two ultra-narrow photo-resist lines suspended between two large photo-resist bases.
|Method for forming isolation structure|
A method for forming an isolation structure includes the following steps. A hard mask layer is formed on a substrate and a trench is formed in the substrate and the hard mask layer.
|Methods for fabricating electrically-isolated finfet semiconductor devices|
Fabrication methods for semiconductor device structures are provided. In an exemplary embodiment, a method of fabricating an electrically-isolated finfet semiconductor device includes the steps of forming a silicon oxide layer over a semiconductor substrate including a silicon material and forming a first hard mask layer over the silicon oxide layer.
|Method for fabricating power semiconductor device|
A method for fabricating a power semiconductor device is disclosed. A substrate having thereon a plurality of die regions and scribe lanes is provided.
|Method of manufacturing a magnetoresistive device|
A method of manufacturing a magnetoresistive-based device includes etching a hard mask layer, the etching having a selectivity greater than 2:1 and preferably less than 5:1 of the hard mask layer to a photo resist thereover. Optionally, the photo resist is trimmed prior to the etch, and oxygen may be applied during or just subsequent to the trim of the photo resist to increase side shrinkage.
|Color filter including clear pixel and hard mask|
Embodiments of an apparatus including a color filter arrangement formed on a substrate having a pixel array formed therein. The color filter arrangement includes a clear filter having a first clear hard mask layer and a second clear hard mask layer formed thereon, a first color filter having the first clear hard mask layer and the second hard mask layer formed thereon, a second color filter having the first clear hard mask layer formed thereon, and a third color filter having no clear hard mask layer formed thereon.
|Manufacturing of fet devices having lightly doped drain and source regions|
Embodiments described herein generally relate to methods of manufacturing n-type lightly doped drains and p-type lightly doped drains. In one method, a photoresist mask is used to etch a transistor, and the mask is left in place (i.e., reused) to protect other devices and poly while a high energy implantation is performed in alignment with the photoresist mask, such that the implantation is adjacent to the etched transistor.
|Self-adjusting gate hard mask|
An intermediate wafer includes a substrate having a surface and a first dummy gate plug disposed upon a structure, e.g., a fin, supported by the substrate surface; a second dummy gate plug disposed upon the substrate surface; and a first layer in which the first dummy gate plug and the second dummy gate plug are embedded. The first layer exhibits a non-planar surface topography characterized by a depression due at least to a presence of the first dummy gate plug.
|Self-adjusting gate hard mask|
A method provides an intermediate semiconductor device structure and includes providing a water having first dummy gate plugs and second dummy gate plugs embedded in a first layer having a non planar wafer surface topography due at least to a presence of the fist dummy gate plugs; depositing at least one second layer over the first layer, the at least one second layer comprising a hard mask material; and removing at least a portion of the second layer to form a substantially planar wafer surface topography over the first dummy gate plugs and the second dummy gate plugs prior to gate conductor deposition.. .
|Semiconductor device and method for manufacturing the semiconductor device|
When an oxide semiconductor film is microfabricated to have an island shape, with the use of a hard mask, unevenness of an end portion of the oxide semiconductor film can be suppressed. Specifically, a hard mask is formed over the oxide semiconductor film, a resist is formed over the hard mask, light exposure is performed to form a resist mask, the hard mask is processed using the resist mask as a mask, the oxide semiconductor film is processed using the processed hard mask as a mask, the resist mask and the processed hard mask are removed, a source electrode and a drain electrode are formed in contact with the processed oxide semiconductor film, a gate insulating film is formed over the source electrode and the drain electrode, and a gate electrode is formed over the gate insulating film, the gate electrode overlapping with the oxide semiconductor film..
|Method of fabricating mos device|
Provided is a method of fabricating a mos device including the following steps. At least one gate structure is formed on a substrate, wherein the gate structure includes a gate conductive layer and a hard mask layer disposed on the gate conductive layer.
|Manufacturing method of power mosfet using a hard mask as a stop layer between sequential cmp steps|
A manufacturing method of a power mosfet employs a hard mask film over a portion of the wafer surface as a polishing stopper, between two successive polishing steps. After embedded epitaxial growth is performed in a state where a hard mask film for forming trenches is present in at least a scribe region of a wafer, primary polishing is performed by using the hard mask film as a stopper, and secondary polishing is then performed after the hard mask film is removed..
|Method of fabricating a semiconductor device having a capping layer|
A method of semiconductor device fabrication includes forming a first dummy gate structure in a first region of a semiconductor substrate and forming a second dummy gate structure in a second region of the semiconductor substrate. A protective layer (e.g., oxide and/or silicon nitride hard mask) is formed on the second dummy gate structure.
|Metal lines having etch-bias independent height|
A dielectric material stack including at least a via level dielectric material layer, at least one patterned etch stop dielectric material portion, a line level dielectric material layer, and optionally a dielectric cap layer is formed over a substrate. At least one patterned hard mask layer including a first pattern can be formed above the dielectric material stack.
|Fin field-effect transistors and fabrication method thereof|
A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate, and forming a plurality of fins with hard mask layers and an isolation structure.
|Semiconductor device and method of manufacturing the same|
According to a method of manufacturing a semiconductor device, hard mask lines are formed in parallel in a substrate and the substrate between the hard mask lines is etched to form grooves. A portion of the hard mask line and a portion of the substrate between the grooves are etched.
|Titanium oxynitride hard mask for lithographic patterning|
A vertical stack including a dielectric hard mask layer and a titanium nitride layer is formed over an interconnect-level dielectric material layer such as an organosilicate glass layer. The titanium nitride layer may be partially or fully converted into a titanium oxynitride layer, which is subsequently patterned with a first pattern.
|Method of fabricating capacitor structure|
A method of fabricating a capacitor structure includes the following steps. Firstly, a substrate is provided.
|Lithographic material stack including a metal-compound hard mask|
A lithographic material stack including a metal-compound hard mask layer is provided. The lithographic material stack includes a lower organic planarizing layer (opl), a dielectric hard mask layer, and the metal-compound hard mask layer, an upper opl, an optional anti-reflective coating (arc) layer, and a photoresist layer.
|Photo resist trimmed line end space|
One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (hm) region is formed above a first hm region.
|Patterned line end space|
One or more techniques or systems for forming a line end space structure are provided herein. In some embodiments, a first patterned second hard mask (hm) region is formed above a first hm region.
|Multi-patterning method and device formed by the method|
A multi-patterning method includes: patterning at least two first openings in a hard mask layer over a substrate using a first mask; forming spacers within two of the at least two first openings, each spacer having a spacer opening therein for patterning a respective first circuit pattern over the substrate, wherein each spacer defines a pattern-free region adjacent to a respective one of the at least two first circuit patterns, and patterning a second circuit pattern in the hard mask layer using a second mask. The second circuit pattern is located between and excluded from the pattern free regions adjacent the at least two first circuit patterns..
|Buried hard mask for embedded semiconductor device patterning|
Methods and apparatus for manufacturing semiconductor devices, and such semiconductor devices, are described. According to various aspects of the disclosure, a semiconductor device can be manufactured by forming a core region of the semiconductor device and forming a periphery region of the semiconductor device.
|Reducing gate height variance during semiconductor device formation|
In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a fet with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates.
|Hard mask etch stop for tall fins|
A hard mask etch stop is formed on the top surface of tall fins to preserve the fin height and protect the top surface of the fin from damage during etching steps of the transistor fabrication process. In an embodiment, the hard mask etch stop is formed using a dual hard mask system, wherein a hard mask etch stop layer is formed over the surface of a substrate, and a second hard mask layer is used to pattern a fin with a hard mask etch stop layer on the top surface of the fin.
|Method of manufacturing a magnetoresistive device|
A method of manufacturing a magnetoresistive-based device includes a metal hard mask that is inert to a top electrode etch chemistry and that has low sputter yield during a magnetic stack sputter. The metal hard mask is patterned by the photo resist and the photo mask is then stripped and the top electrode (overlying magnetic materials of the magnetoresistive-based device) is patterned by the metal hard mask..
|Method for isotropic etching|
The realization of the intermediate hard mask and the etching of the hard mask made from carbon-doped boron (b:c) being done in said inductive coupling plasma etching reactor (icp).. .
|Patterning process method for semiconductor devices|
A method for forming a semiconductor device that includes a siarc layer formed over a photoresist film which is formed over spacer portions which are formed on a spacer assist layer which is formed over a hard mask layer. The siarc layer has an etch rate substantially similar to the etch rate of the spacer assist layer.
|Deposit/etch for tapered oxide|
A process for fabricating a tapered field plate dielectric for high-voltage semiconductor devices is disclosed. The process may include depositing a thin layer of oxide, depositing a polysilicon hard mask, depositing a resist layer and etching a trench area, performing deep silicon trench etch, and stripping the resist layer.
|Semiconductor structure and method of fabricating mos device|
Provided is a semiconductor structure including a gate structure, a first spacer, and a second spacer. The gate structure is formed on a substrate and includes a gate material layer, a first hard mask layer disposed on the gate material layer, and a second hard mask layer disposed on the first hard mask layer.
|Embedded polysilicon resistor in integrated circuits formed by a replacement gate process|
An embedded resistor structure in an integrated circuit that can be formed in a replacement gate high-k metal gate metal-oxide-semiconductor (mos) technology process flow. The structure is formed by etching a trench into the substrate, either by removing a shallow trench isolation structure or by silicon etch at the desired location.
|Method for manufacturing semiconductor device using thin hard mask and structure manufactured by the same|
A method for manufacturing semiconductor device is disclosed. A substrate with a plurality of protruding strips formed vertically thereon is provided.
|Method of forming semiconductor device including silicide layers|
A method includes forming a gate structure on a semiconductor material region, wherein the gate structure includes spacer elements abutting a gate electrode layer. The gate electrode layer is etched to provide a recess.
|Manufacturing method of semiconductor device|
When forming, over the substrate by the gate-last process, a mosfet of a core region driven by a first power supply voltage and a mosfet of a high-voltage region driven by a second power supply voltage higher than the first power supply voltage, the thickness of the hard mask film formed over a dummy gate film of the high-voltage region is made thicker than that of the hard mask film formed over a dummy gate film of the core region, prior to a process of patterning a dummy gate of the mosfet of the core region and the mosfet of the high-voltage region. Thereby, the breakdown voltage of mosfet of the high-voltage region can be ensured..
|Oxygen-containing ceramic hard masks and associated wet-cleans|
A method of forming an oxygen-containing ceramic hard mask film on a semiconductor substrate involves receiving a semiconductor substrate in a plasma-enhanced chemical vapor deposition (pecvd) process chamber and depositing forming by pevcd on the substrate an oxygen-containing ceramic hard mask film, the film being etch selective to low-k dielectric and copper, resistant to plasma dry-etch and removable by wet-etch. The method may further involve removing the oxygen-containing ceramic hard mask film from the substrate with a wet etch.
|Electrostatic discharge devices for integrated circuits|
A junction diode array for use in protecting integrated circuits from electrostatic discharge can be fabricated to include symmetric and/or asymmetric junction diodes of various sizes. The diodes can be configured to provide low voltage and current discharge via unencapsulated contacts, or high voltage and current discharge via encapsulated contacts.
|Spacer divot sealing method and semiconductor device incorporating same|
A semiconductor structure in fabrication includes a nfet and a pfet. Spacers adjacent gate structures of the nfet and pfet have undesired divots that can lead to substrate damage from chemicals used in a subsequent etch.
|Manufacturing method of nonvolatile memory device and nonvolatile memory device|
A method of manufacturing a non-volatile memory device comprises: forming a first electrode layer; a variable resistance material layer, a second electrode layer; and a hard mask layer, forming a first resist mask extending in a first direction on the hard mask layer; forming a first hard mask extending in the first direction by etching the hard mask layer using the first resist mask; forming a second resist mask extending in a second direction, on the first hard mask such that the width of the second resist mask is greater than the width of the first resist mask; forming a second hard mask by etching the first hard mask using the second resist mask; and forming a variable resistance element by patterning, by etching the second electrode layer, the variable resistance material layer and the first electrode layer using the second hard mask.. .
|Method for fabricating trench type transistor|
A method for fabricating a trench type transistor. An epitaxial layer is provided on a semiconductor substrate.
|Method for manufacturing a magnetoresistive sensor|
A method for manufacturing a magnetic sensor that allows the sensor to be constructed with a very narrow track width and with smooth, well defined side walls. A tri-layer mask structure is deposited over a series of sensor layers.
|Interconnect structure and fabrication method|
A carbon-containing dielectric layer can be formed on a substrate. A protective layer can be formed on the carbon-containing dielectric layer to prevent carbon loss from the carbon-containing dielectric layer by performing a surface treatment to the carbon-containing dielectric layer using a gas at least containing silicon and hydrogen.
|Ztcr poly resistor in replacement gate flow|
An integrated circuit having a replacement gate mos transistor and a polysilicon resistor may be formed by removing a portion at the top surface of the polysilicon layer in the resistor area. A subsequently formed gate etch hard mask includes a mos hard mask segment over a mos sacrificial gate and a resistor hard mask segment over a resistor body.
|Method for removing hard mask oxide and making gate structure of semiconductor devices|
A method includes forming a first gate above a semiconductor substrate, forming a hard mask on the first gate, and forming a contact etch stop layer (cesl) on the hard mask. No hard mask is removed between the step of forming the hard mask and the step of forming the cesl.
|Pattern improvement in multiprocess patterning|
Improved fidelity to an integrated circuit pattern design in a semiconductor structure ultimately produced is achieved by modeling material removal and deposition processes in regard to materials, reactant, feature size, feature density, process parameters and the like as well as the effects of such parameters on etch and material deposition bias due to microloading and rie lag (including inverse rie lag) and using the models to work backward through the intended manufacturing method steps, including hard mask pattern decomposition, to morphologically develop feature patterns for use in most or all process steps which will result in the desired feature sizes and shapes at the completion of the overall process. Modeling of processes may be simplified through use of process assist features to locally adjust rates of material deposition and removal..
|Self-aligned deep trench capacitor, and method for making the same|
A method for forming a trench capacitor includes providing a substrate of a semiconductor material having a hard mask layer; etching the hard mask layer and the substrate to form at least one trench extending into the substrate; and performing pull-back etching on the hard mask layer. In the pull-back etching, a portion of the hard mask layer defining and adjacent to side walls of an opening of the at least one trench is removed.
|Magnetoresistive element and method of manufacturing the same|
According to one embodiment, a magnetoresistive element manufacturing method is provided. In this magnetoresistive element manufacturing method, a first ferromagnetic layer, tunnel barrier layer, and second ferromagnetic layer are sequentially formed on a substrate.
|Recessing and capping of gate structures with varying metal compositions|
A approach for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ild) over the substrate adjacent the spacers; forming a first trench in the ild down to the dummy gate electrode; removing the dummy gate electrode to form a second trench below the first trench; forming a metal gate structure in the first and second trenches; and forming a gate cap over the metal gate structure..
|Nor flash device manufacturing method|
An embodiment of a nor flash device manufacturing method is disclosed, which includes: providing a substrate having a first polycrystalline silicon layer disposed thereon; forming a first hard mask layer on the first polycrystalline silicon layer; etching the first hard mask layer to form a first opening, and cleaning a gas pipeline connected to an etching cavity before etching the first hard mask layer; forming a second hard mask layer on the first hard mask layer, and the second hard mask layer covers the bottom and side wall of the first opening; etching the second hard mask layer to form a second opening, the width of the second opening is smaller than the width of the first opening; etching the first polycrystalline silicon, forming a floating gate. The nor flash device manufacturing method of the present invention improves the yield of the nor flash device..
|Method of forming gate structure|
A method of forming a gate structure includes the steps of: providing a substrate; sequentially forming a polysilicon layer, a hard mask layer, an anti-reflection layer and a photoresist layer over the substrate; etching the hard mask layer using the anti-reflection layer and the photoresist layer as a mask; performing a siconi process to trim the etched hard mask layer until the trimmed hard mask layer has a desired critical dimension; and etching the polysilicon layer to form a gate structure using the trimmed hard mask layer as a mask. The method is capable of precise control of the width and profile of the trimmed hard mask layer and can thereby result in a gate structure with a smaller critical dimension and an improved profile..
|Plasma etching method|
A plasma etching method performs plasma etching on a sample, which has laminated films containing a variable layer of a magnetic film, a barrier layer of an insulating material, and a fixed layer of a magnetic film, using a hard mask, which includes at least one of a ta film and a tin film. The plasma etching method includes a first step of etching the laminated films using n2 gas; and a second step of etching the laminated films after the first step using mixed gas of n2 gas and gas containing carbon elements..
|Method for manufacturing a magnetic write head using novel mask structure|
A method for manufacturing a magnetic write pole of a magnetic write head that achieves improved write pole definition reduced manufacturing cost and improves ease of photoresist mask re-work. The method includes the use of a novel bi-layer hard mask beneath a photoresist mask.
|Dual epi cmos integration for planar substrates|
Silicon germanium regions are formed adjacent gates electrodes over both n-type and p-type regions in an integrated circuit. A hard mask patterned by lithography then protects structures over the p-type region while the silicon germanium is selectively removed from over the n-type region, even under remnants of the hard mask on sidewall spacers on the gate electrode.
|Fin recess last process for finfet fabrication|
A method includes forming isolation regions extending from a top surface of a semiconductor substrate into the semiconductor substrate, and forming a hard mask strip over the isolation regions and a semiconductor strip, wherein the semiconductor strip is between two neighboring ones of the isolation regions. A dummy gate strip is formed over the hard mask strip, wherein a lengthwise direction of the dummy gate strip is perpendicular to a lengthwise direction of the semiconductor strip, and wherein a portion of the dummy gate strip is aligned to a portion of the semiconductor strip.
|Lithography process using directed self assembly|
A method includes forming a patterned hard mask layer, with a trench formed in the patterned hard mask layer. A bulk co-polymer (bcp) coating is dispensed in the trench, wherein the bcp coating includes poly-styrele (ps) and poly methyl metha crylate (pmma).
|Low-k damage free integration scheme for copper interconnects|
A method includes forming a sacrificial layer on a substrate. A hard mask layer is formed on the sacrificial layer.
|Dual damascene process|
A method for forming dual damascene structures in a semiconductor structure is disclosed. The method generally includes etching a substrate using a first hard mask to form a plurality of first trenches and vias, forming a set of first conductive lines and via interconnects, removing the first hard mask, etching the substrate using a second hard mask to form a plurality of second trenches and vias, and forming a set of second conductive lines and via interconnects.
|Forming method of an annular storage unit of a magneto-resistive memory|
The present invention discloses a method of forming an annular storage structure of a magneto-resistive memory. It relates to the manufacturing process of the semiconductor devices.
|Method for removing a patterned hard mask layer|
The present disclosure provides embodiments of a method that includes providing a substrate having a patterned material layer and a patterned hard mask layer disposed on the patterned material layer, wherein the patterned material layer includes a material feature having a first dimension and the patterned hard mask layer includes a hard mask feature covering the material feature. The method also includes forming, on the substrate and the hard mask feature, a patterned resist layer with an opening that exposes the hard mask feature and has a second dimension as a function of the first dimension; etching back the resist film; and removing the patterned hard mask layer..
|Streamlined process for vertical semiconductor devices|
The present disclosure provides a streamlined approach to forming vertically structured devices such as deep trench capacitors. Trenches and a contact plate bridging the trenches are formed using one lithographic process.
|Dual gate process|
The control of gate widths is improved for system-on-a-chip (soc) devices which require multiple gate dielectric “gate” thicknesses, e.g., for analog and digital processing on the same chip. A hard mask is formed to protect a thick gate while the thin gate region is etched to remove oxide (sometimes referred to as a preclean step).
|Method of manufacturing semiconductor device|
Provided is a method of manufacturing a semiconductor device in which a via hole and a trench are formed in a low dielectric constant film using a hard mask film having at least three layers. In a process of forming the hard mask film having at least three layers, the hard mask film formed of an insulating material and the hard mask film formed of a metal material, amorphous silicon or polycrystalline silicon are alternately laminated..
|Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material|
In one example, the method includes forming a plurality of isolation structures in a semiconducting substrate that define first and second active regions where first and second transistor devices, respectively, will be formed, forming a hard mask layer on a surface of the substrate above the first and second active regions, wherein the hard mask layer comprises at least one of carbon, fluorine, xenon or germanium ions, performing a first etching process to remove a portion of the hard mask layer and expose a surface of one of the first and second active regions, after performing the first etching process, forming a channel semiconductor material on the surface of the active region that was exposed by the first etching process, and after forming the channel semiconductor material, performing a second etching process to remove remaining portions of the hard mask layer that were not removed during the first etching process.. .
|Mold manufacturing mask blanks and method of manufacturing mold|
A fine pattern is formed with high pattern precision, and a time required for fabricating a mold is considerably shortened. Provided are mask blanks used for manufacturing a sub-master mold by transferring the fine pattern provided on a surface of an original mold by imprint, having a hard mask layer including a chromium compound layer expressed by a chemical formula croxnycz (x>0), on a substrate..
|Reduction chemistry for etching|
An etching is performed with reduction chemistry to prevent erosion of a hard mask. Embodiments include forming a hard mask over one or more layers above a substrate, patterning the hard mask to form openings in the hard mask, and etching the one or more layers with an etchant including hydrogen (h2) to remove portions of the one or more layers to form one or more vertical interconnect accesses (vias).
|Semiconductor device and method for manufacturing the same|
According to one embodiment, a semiconductor device includes a first insulating film formed above a substrate, wires formed on the first insulating film, an air gap formed between the adjacent wires, and a second insulating film formed on the wires and the air gap. Each of the wires has a metal film formed on the first insulating film and a hard mask formed on the metal film, the hard mask has a first layer and a second layer, a second internal angle formed by the under surface and the side surface of the second layer on a cross section of the second layer is smaller than a first internal angle formed by the under surface and the side surface of the first layer on a cross section of the first layer, and the top surface of the air gap is higher than the top surface of the metal film..
|Dual hard mask lithography process|
A first metallic hard mask layer over an interconnect-level dielectric layer is patterned with a line pattern. At least one dielectric material layer, a second metallic hard mask layer, a first organic planarization layer (opl), and a first photoresist are applied above the first metallic hard mask layer.
|Random access memory device and manufacturing method for nodes thereof|
A manufacturing method for the nodes of the ram device, includes the steps as follows: forming a sti layer on a substrate to divide the substrate into several active areas; sequentially forming a first insulating layer and a hard mask layer on the substrate; etching the first insulating layer to form a first hole for exposing the sti layer and partial of the active areas; filling a conductive material in the first hole to form a conductor; forming a protective layer on the top surface of the conductor, wherein each protective layer has an opening aligning the sti layer; etching the conductor from the opening until the sti layer to form a second hole for exposing the sti layer, wherein each conductor is divided into two nodes by the second hole arranged therebetween; and forming a second insulating layer in the second hole for electrically isolating the nodes.. .