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Date/App# patent app List of recent Hard Mask-related patents
04/10/14
20140099779
 Reverse tone sti formation patent thumbnailnew patent Reverse tone sti formation
A method includes forming a hard mask over a substrate, patterning the hard mask to form a first plurality of trenches, and filling a dielectric material into the first plurality of trenches to form a plurality of dielectric regions. The hard mask is removed from between the plurality of dielectric regions, wherein a second plurality of trenches is left by the removed hard mask.
04/10/14
20140099771
 Reverse tone sti formation patent thumbnailnew patent Reverse tone sti formation
A method includes forming a hard mask over a substrate, patterning the hard mask to form a first plurality of trenches, and filling a dielectric material into the first plurality of trenches to form a plurality of dielectric regions. The hard mask is removed from between the plurality of dielectric regions, wherein a second plurality of trenches is left by the removed hard mask.
04/10/14
20140099760
 Method for fabricating semiconductor device patent thumbnailnew patent Method for fabricating semiconductor device
A method for fabricating a semiconductor device, wherein the method comprises steps as follows: a dummy gate with a poly-silicon gate electrode and a passive device having a poly-silicon element layer are firstly provided. A hard mask layer is then formed on the dummy gate and the passive device.
04/10/14
20140099583
 Simultaneous photoresist development and neutral polymer layer formation patent thumbnailnew patent Simultaneous photoresist development and neutral polymer layer formation
A photoresist layer is lithographically exposed to form lithographically exposed photoresist regions and lithographically unexposed photoresist regions. The photoresist layer is developed with a non-polar or weakly polar solvent including a dissolved neutral polymer material.
04/10/14
20140098459
 Capacitor and contact structures, and formation processes thereof patent thumbnailnew patent Capacitor and contact structures, and formation processes thereof
Capacitor and contact structures are provided, as well as methods for forming the capacitor and contact structures. The methods include, for instance, providing a layer of conductive material above a conductive structure and above a lower electrode of a capacitor; etching the layer of conductive material to define a conductive material hard mask and an upper electrode of the capacitor, the conductive material hard mask being disposed at least partially above the conductive structure; and forming a first conductive contact structure and a second conductive contact structure, the first conductive contact structure extending through an opening in the conductive material hard mask and conductively contacting the conductive structure, and the second conductive contact structure conductively contacting one of the lower electrode of the capacitor, or the upper electrode of the capacitor..
04/03/14
20140094017
 Manufacturing method for a shallow trench isolation patent thumbnailManufacturing method for a shallow trench isolation
A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed.
04/03/14
20140091400
 Gate dielectric of semiconductor device patent thumbnailGate dielectric of semiconductor device
A method of fabricating a semiconductor device having a different gate structure in each of a plurality of device regions is described. The method may include a replacement gate process.
04/03/14
20140091372
 Method for producing semiconductor device and semiconductor device patent thumbnailMethod for producing semiconductor device and semiconductor device
In a first step, a planar silicon layer is formed on a silicon substrate and first and second pillar-shaped silicon layers are formed on the planar silicon layer; a second step includes forming an oxide film hard mask on the first and second pillar-shaped silicon layers, and forming a second oxide film on the planar silicon layer, the second oxide film being thicker than a gate insulating film; and a third step includes forming the gate insulating film around each of the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a metal film and a polysilicon film around the gate insulating film, the polysilicon film having a thickness that is smaller than one half a distance between the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a third resist for forming a gate line, and performing anisotropic etching to form the gate line.. .
04/03/14
20140091273
 Resistive random access memory and fabrication method thereof patent thumbnailResistive random access memory and fabrication method thereof
A resistive random access memory (rram) unit includes at least one bit line extending along a first direction, at least one word line disposed on a substrate and extending along a second direction so as to intersect the bit line, a hard mask layer on the word line to isolate the word line from the bit line, a first memory cell on a sidewall of the word line, and a second memory cell on the other sidewall of the word line.. .
03/27/14
20140087540
 Method for forming trench isolation patent thumbnailMethod for forming trench isolation
A trench isolation method is disclosed. A substrate having thereon a pad layer and a hard mask is provided.
03/27/14
20140084486
Reliable interconnect for semiconductor device
A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided.
03/27/14
20140084481
System and method of novel encapsulated multi metal branch foot structures for advanced back end of line
A plurality of metal tracks are formed in a plurality of intermetal dielectric layers stacked in an integrated circuit die. Thin protective dielectric layers are formed around the metal tracks.
03/27/14
20140084465
System and method of novel mx to mx-2
A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer.
03/27/14
20140084233
Electrode structure for a non-volatile memory device and method
A method of forming a resistive switching device includes forming a wiring structure over a first dielectric and substrate, forming a junction layer over the wiring structure, forming a resistive switching layer over the junction layer, forming an active metal over the resistive switching layer, forming a tungsten layer over the active metal, forming a barrier layer over the tungsten, depositing a mask over the barrier layer, etching the barrier layer to form a hard mask, etching the junction layer, the resistive switching layer, the active metal layer, and the adhesion layer using the hard mask to form a stack of material, while the adhesion layer maintains adhesion between the barrier layer and the active metal and while side walls of the stack of material have reduced contaminants and have reduced gap regions between the barrier layer and the resistive switching layer.. .
03/20/14
20140077342
Semiconductor device having buried layer and method for forming the same
Semiconductor devices having a buried layer and methods for forming the same are disclosed. In an exemplary method, a hard mask layer can be provided on a semiconductor substrate.
03/20/14
20140077145
Semiconductor device and method of manufacturing the same
The method of manufacturing a semiconductor device selectively forms a resist film on the multilayer gate film and the gate side wall insulating film extending on the semiconductor substrate. An upper part of the gate side wall insulating film and the hard mask film selectively are removed by etching using the resist film as a mask so as to expose a surface of the metal film.
03/06/14
20140065834
Method of manufacturing mold for nano-imprint and substrate fabricating method
Provided is a method of manufacturing a mold for nano-imprint, for forming a projection/recess pattern on a surface of a silicon substrate, including: etching a substrate to form the projection/recess pattern on the surface of the silicon substrate by applying dry-etching to the silicon substrate using a hard mask pattern as a mask, in a state of covering the surface of the silicon substrate with the hard mask pattern made of a chromium-based material; and applying dry-etching to the silicon substrate in etching the substrate using a fluorine-based gas as a reactive gas of an etching gas used for the dry-etching applied to the silicon substrate, and adding an inert gas to the etching gas.. .
03/06/14
20140065832
Enhanced finfet process overlay mark
An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region.
03/06/14
20140065828
Selective fin cut process
A process is provided for selective removal of one or more unwanted fins during finfet device fabrication. In one aspect, the process includes: providing a conformal protective layer over multiple fin structures on a substrate; patterning one or more openings over the unwanted fin structure(s); and removing at least a top portion of the unwanted fin structure(s) exposed through the opening(s), the removing including removing at least a portion of the conformal protective layer over the unwanted fin structure(s) exposed through the opening(s).
03/06/14
20140065795
Method for forming trench isolation
A trench isolation method is disclosed. A substrate having thereon a pad layer and a hard mask is provided.
03/06/14
20140065739
Method for hybrid encapsulation of an organic light emitting diode
Methods and apparatus for encapsulating organic light emitting diode (oled) structures disposed on a substrate using a hybrid layer of material are provided. The encapsulation methods may be performed as single or multiple chamber processes.
03/06/14
20140061827
Metal protection layer over sin encapsulation for spin-torque mram device applications
A magnetic thin film deposition is patterned and protected from oxidation during subsequent processes, such as bit line formation, by an oxidation-prevention encapsulation layer of sin. The sin layer is then itself protected during the processing by a metal overlayer, preferably of ta, al, tin, tan or w.
03/06/14
20140061790
Split-gate lateral diffused metal oxide semiconductor device
A semiconductor device includes a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions.
02/27/14
20140057442
Semiconductor device with silicon-containing hard mask and method for fabricating the same
A semiconductor device includes a semiconductor substrate having an etch target layer provided on the surface thereof, and a hard mask layer formed over the etch target layer and including silicon, wherein the hard mask layer includes a dual structure including a first area and a second area having a larger etch rate than the first area, in order to increase an etching selectivity of the hard mask layer.. .
02/27/14
20140054754
Optically reactive masking
Systems and methods are presented for filling an opening with material of a high integrity. A material having properties in a first physical state suitable for formation of a hard mask layer and in a second physical state having properties facilitating removal of the former hard mask layer is utilized.
02/27/14
20140054584
Semiconductor device and manufacturing method thereof
A semiconductor device is provided which includes an n-type semiconductor layer and a p-type semiconductor layer coexisting in the same wiring layer without influences on the properties of a semiconductor layer. The semiconductor device includes a first wiring layer with a first wiring, a second wiring layer with a second wiring, and first and second transistors provided in the first and second wiring layers.
02/27/14
20140054534
Self-aligned interconnection for integrated circuits
Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device..
02/27/14
20140054264
Method of manufacturing nanoimprint stamp
Methods of manufacturing a nanoimprint stamp are provided. The method may include forming a pattern on a surface of a master substrate, depositing an etch barrier layer on a surface of a stamp substrate, coating a photoresist on one of the surfaces of the master substrate and the stamp substrate on which an etch barrier layer is formed, forming a photoresist pattern by pressing the master substrate against the stamp substrate, forming a hard mask by etching the etch barrier layer using the photoresist pattern, and etching the stamp substrate using the hard mask as an etch mask..
02/20/14
20140051239
Disposable carbon-based template layer for formation of borderless contact structures
After formation of gate stacks, a carbon-based template layer is deposited over the gate stacks, and is optionally planarized to provide a planar top surface. A hard mask layer and a photoresist layer are subsequently formed above the carbon-based template layer.
02/20/14
20140048884
Disposable carbon-based template layer for formation of borderless contact structures
After formation of gate stacks, a carbon-based template layer is deposited over the gate stacks, and is optionally planarized to provide a planar top surface. A hard mask layer and a photoresist layer are subsequently formed above the carbon-based template layer.
02/13/14
20140045124
Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes: forming an etching mask layer on a semiconductor substrate having an etching target layer, patterning the etching mask layer to form a plurality of etching mask patterns, and forming a subsidiary layer surrounding the etching mask patterns having a uniform critical dimension and gap to form hard mask patterns including the subsidiary layer and the etching mask patterns.. .
02/06/14
20140038423
Coating treatment method and coating treatment apparatus
In the present invention, a masking solution is supplied to an edge portion of a front surface of a substrate rotated around a vertical axis to form a masking film at the edge portion of the substrate, a hard mask solution is supplied to the front surface of the substrate to form a hard mask film on the front surface of the substrate, a hard mask film removing solution dissolving the hard mask film is supplied to the hard mask film formed at the edge portion of the substrate to remove the hard mask film formed at the edge portion of the substrate, and a masking film removing solution dissolving the masking film is supplied to the masking film to remove the masking film at the edge portion of the substrate.. .
02/06/14
20140038412
Interconnect formation using a sidewall mask layer
Embodiments described herein provide approaches for interconnect formation in a semiconductor device using a sidewall mask layer. Specifically, a sidewall mask layer is deposited on a hard mask in a merged via region of the semiconductor device following removal of a planarization layer previously formed on the hard mask.
02/06/14
20140038399
Method for fabricating an aperture
A method for fabricating an aperture is disclosed. The method includes the steps of: forming a hard mask containing carbon on a surface of a semiconductor substrate; and using a non-oxygen element containing gas to perform a first etching process for forming a first aperture in the hard mask.
02/06/14
20140038341
Method of producing semiconductor device, solid-state imaging device, method of producing electric apparatus, and electric apparatus
There is provided a method of producing a semiconductor device. The method includes the steps of: forming a first hard mask having an opening above a substrate; forming a sacrificial film above a side surface of the opening of the first hard mask; forming a second hard mask in the opening having the sacrificial film above the side surface; removing the sacrificial film after the second hard mask is formed; ion implanting a first conductivity-type impurity through the first hard mask; and ion implanting a second conductivity-type impurity through the first and second hard masks..
02/06/14
20140035009
Semiconductor device structures and methods of forming semiconductor structures
A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane.
01/30/14
20140030890
Super-self-aligned contacts and method for making the same
A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion.
01/30/14
20140030885
Method for forming dual damascene opening
A method for forming a dual damascene opening includes the following steps. Firstly, a first hard mask layer with a trench pattern is formed over a material layer.
01/30/14
20140030880
Method of semiconductor integrated circuit fabrication
A method of fabricating a semiconductor integrated circuit (ic) is disclosed. The method includes receiving a semiconductor device.
01/30/14
20140030868
Deposit/etch for tapered oxide
A process for fabricating a tapered field plate dielectric for high-voltage semiconductor devices is disclosed. The process may include depositing a thin layer of oxide, depositing a polysilicon hard mask, depositing a resist layer and etching a trench area, performing deep silicon trench etch, and stripping the resist layer.
01/30/14
20140027923
Non-lithographic hole pattern formation
A metal layer is deposited over a material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation or nitridation.
01/30/14
20140027917
Non-lithographic line pattern formation
A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation.
01/30/14
20140027914
Protection of under-layer conductive pathway
Systems and methods are presented for preventing removal of material comprising a metal gate during removal of a mask layer in a semiconductor structure. Upon exposure of the metal line during formation of a via opening the exposed portion of the metal line undergoes chemical modification to form a passivation layer.
01/30/14
20140027878
Self-aligned trench over fin
A stack of a first hard mask portion and a second hard mask portion is formed over a semiconductor material layer by anisotropically etching a stack, from bottom to top, of a first hard mask layer and a second hard mask layer. The first hard mask portion is laterally recessed by an isotropic etch.
01/30/14
20140027825
Threshold voltage adjustment in a fin transistor by corner implantation
When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins..
01/30/14
20140027818
Gate recessed fdsoi transistor with sandwich of active and etch control layers
The structure and the fabrication methods herein implement a fully depleted, recessed gate silicon-on-insulator (soi) transistor with reduced access resistance, reduced on-current variability, and strain-increased performance. This transistor is based on an soi substrate that has an epitaxially grown sandwich of sige and si layers that are incorporated in the sources and drains of the transistors.
01/30/14
20140027783
Semiconductor device and method of manufacturing the same
The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located between the plurality of source and drain regions along a first direction; characterized in that the plurality of gate stack structures enclose the plurality of channel regions. In accordance with the semiconductor device and the method of manufacturing the same of the present invention, an all-around nanowire metal multi-gate is formed in self-alignment by punching through and etching the fins at which the channel regions are located using a combination of the hard mask and the dummy gate, thus the device performance is enhanced..
01/23/14
20140024219
Image transfer process employing a hard mask layer
At least one mask layer formed over a substrate includes at least one of a dielectric material and a metallic material. By forming a first pattern in one of the at least one mask layer, a patterned mask layer including said first pattern is formed.
01/23/14
20140023834
Image transfer process employing a hard mask layer
At least one mask layer formed over a substrate includes at least one of a dielectric material and a metallic material. By forming a first pattern in one of the at least one mask layer, a patterned mask layer including said first pattern is formed.
01/23/14
20140022839
Method and system for providing magnetic junctions having improved characteristics
A method and apparatus provide a magnetic memory including magnetic junctions on a substrate. The apparatus include an rie chamber and an ion milling chamber.
01/16/14
20140017894
Methods of manufacturing semiconductor devices
Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a material layer is formed over a workpiece.
01/16/14
20140014621
Analysis of pattern features
The embodiments disclose a method for an electron curing reverse-tone process, including depositing an etch-resistant layer onto a patterned imprinted resist layer fabricated onto a hard mask layer deposited onto a substrate, curing the etch-resistant layer using an electron beam dose during etching processes of imprinted pattern features into the hard mask and into the substrate and using analytical processes to quantify reduced pattern feature placement drift errors and to quantify increased pattern feature size uniformity of imprinted pattern features etched.. .
01/09/14
20140011341
Methods of forming finfet devices with alternative channel materials
One method involves providing a substrate comprised of first and second semiconductor materials, performing an etching process through a hard mask layer to define a plurality of trenches that define first and second portions of a fin for a finfet device, wherein the first portion is the first material and the second portion is the second material, forming a layer of insulating material in the trenches, performing a planarization process on the insulating material, performing etching processes to remove the hard mask layer and reduce a thickness of the second portion, thereby defining a cavity, performing a deposition process to form a third portion of the fin on the second portion, wherein the third portion is a third semiconducting material that is different from the second material, and performing a process such that a post-etch upper surface of the insulating material is below an upper surface of the third portion.. .
01/02/14
20140004449
Blankmask and method for fabricating photomask using the same
Provided is a blankmask with a light-shielding layer including a light block layer and an anti-reflective layer, and a hard mask film. The light block layer and the anti-reflective layer are formed by combining a layer formed of a mosi compound and a layer formed of a motasi compound.
01/02/14
20140001594
Schottky diode with leakage current control structures
A schottky diode includes a device structure having a central portion and a plurality of fingers. Distal portions of the fingers overlie leakage current control (lcc) regions.
01/02/14
20140001556
Semiconductor device and method for manufacturing semiconductor device
A memory cell and a peripheral circuit each having a gate electrode are formed on a semiconductor substrate. The periphery of the gate electrodes is covered with an organic insulating layer.
01/02/14
20140001432
Applications for nanopillar structures
A disclosed method of fabricating a hybrid nanopillar device includes forming a mask on a substrate and a layer of nanoclusters on the hard mask. The hard mask is then etched to transfer a pattern formed by the first layer of nanoclusters into a first region of the hard mask.
12/26/13
20130341801
Redeposition control in mram fabrication process
Methods and structures are described to reduce metallic redeposition material in the memory cells, such as mtj cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer.
12/19/13
20130337652
Mask pattern for hole patterning and method for fabricating semiconductor device using the same
A method for fabricating a semiconductor device includes forming an etching target layer over a substrate including a first region and a second region; forming a hard mask layer over the etching target layer; forming a first etch mask over the hard mask layer, wherein the first etch mask includes a plurality of line patterns and a sacrificial spacer layer formed over the line patterns; forming a second etch mask over the first etch mask, wherein the second etch mask includes a mesh type pattern and a blocking pattern covering the second region; removing the sacrificial spacer layer; forming hard mask layer patterns having a plurality of holes by etching the hard mask layer using the second etch mask and the first etch mask; and forming a plurality of hole patterns in the first region by etching the etching target layer using the hard mask layer patterns.. .
12/19/13
20130337651
Double patterning strategy for contact hole and trench in photolithography
A method of lithography patterning includes forming a first etch stop layer, a second etch stop layer, and a hard mask layer on a material layer. The materials of the first etch stop layer and the second etch stop layer are selected by the way that there is a material gradient composition between the second etch stop layer, the first etch stop layer, and the material layer.
12/19/13
20130337582
Mram etching processes
Various embodiments of the invention relate to etching processes used in fabrication of mtj cells in an mram device. The various embodiments can be used in combination with each other.
12/12/13
20130330660
Hard mask spacer structure and fabrication method thereof
A hard mask spacer structure includes a first spacer on a device layer, the first spacer defining a plurality of hole patterns and at least an asteriated hole pattern between the hole patterns; and a second spacer on the first spacer and inlaid into the asteriated hole pattern, thereby rounding the asteriated hole pattern.. .
12/12/13
20130328199
Semiconductor device with spacers for capping air gaps and method for fabricating the same
A method for fabricating memory device includes forming a bit line pattern including a first conductive layer and a hard mask stacked over a substrate, forming a sacrificial layer on sidewalls of the bit line pattern, forming a second conductive layer in contact with the sacrificial layer and adjacent to the bit line pattern, recessing the second conductive layer, forming an air gap between the recessed second conductive layer and the first conductive layer by removing the sacrificial layer, and forming an air gap capping layer on sidewalls of the hard mask to cap entrance of the air gap.. .
12/12/13
20130328173
High aspect ratio and reduced undercut trench etch process for a semiconductor substrate
A hydrofluorocarbon gas is employed as a polymer deposition gas in an anisotropic etch process employing an alternation of an etchant gas and the polymer deposition gas to etch a deep trench in a semiconductor substrate. The hydrofluorocarbon gas can generate a thick carbon-rich and hydrogen-containing polymer on sidewalls of a trench at a thickness on par with the thickness of the polymer on a top surface of the semiconductor substrate.
12/12/13
20130328111
Recessing and capping of gate structures with varying metal compositions
A method for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ild) over the substrate adjacent the spacers; forming a first trench in the ild down to the dummy gate electrode; removing the dummy gate electrode to form a second trench below the first trench; forming a metal gate structure in the first and second trenches; and forming a gate cap over the metal gate structure..
12/05/13
20130323876
Image device and methods of forming the same
A method of forming of an image sensor device includes a patterned hardmask layer is formed over a substrate. The patterned hard mask layer has a plurality of first openings in a periphery region, and a plurality of second openings in a pixel region.
12/05/13
20130320539
Method and apparatus for back end of line semiconductor device processing
Methods and apparatus are disclosed for the back end of line process for fabrication of integrated circuits (ics). The inter-metal dielectric (imd) layer between two metal layers may comprise an etching stop layer over a metal layer, a low-k dielectric layer over the etching stop layer, a dielectric hard mask layer over the low-k dielectric layer, an nitrogen free anti-reflection layer (nfarl) over the dielectric hard mask layer, and a metal-hard-mask (mhm) layer of a thickness in a range from about 180 Å to about 360 Å over the nfarl.
11/28/13
20130316539
Method for reducing morphological difference between n-doped and undoped polysilicon gates after etching
The present invention discloses a method for reducing the morphological difference between n-doped and undoped poly-silicon gates after etching, comprising the following sequential steps: depositing a hard mask layer on a substrate template having n-doped poly-silicon and undoped poly-silicon to form an n-doped poly-silicon hard mask layer and an undoped poly-silicon hard mask layer respectively, and etching the undoped poly-silicon hard mask layer to make a thickness difference between the n-doped poly-silicon hard mask layer and the undoped poly-silicon hard mask layer; depositing an anti-reflection layer, and etching according to a predetermined pattern until exposing the n-doped poly-silicon, wherein when the n-doped poly-silicon is exposed, the undoped poly-silicon is etched to a certain degree; and removing residuals on the surface of the above formed structure, and etching to form an n-doped poly-silicon gate and an undoped poly-silicon gate, respectively.. .
11/28/13
20130316470
Method which can form contact holes in wafer of semiconductor
The present invention relates to the field of semiconductor integrated circuits, and particularly relates to a method which can form a contact hole in a wafer of semiconductor material. The invention has proposed a method which can form a contact hole in a wafer of semiconductor: measuring and comparing a critical dimension (cd) of a position corresponding to the contact hole in the hard mask with the cd required in the technology, and then, based on the measurement, adjusting the cd of the position corresponding to the contact hole in the hard mask, by conformal deposition or etching technology, to fit a requirement of the technology; the method can reduce process costs while improving production capacity..
11/28/13
20130316272
Reflective mask blank for euv lithography
In the hard mask layer, the total content of cr and either one of n and o is from 85 to 99.9 at %, and the content of h is from 0.1 to 15 at %.. .
11/28/13
20130313717
Spacer for enhancing via pattern overlay tolerence
After formation of line openings in a hard mask layer, hard mask level spacers are formed on sidewalls of the hard mask layer. A photoresist is applied and patterned to form a via pattern including a via opening.
11/28/13
20130313646
Structure and method for fabricating fin devices
A structure and method of forming a semiconductor device with a fin is provided. In an embodiment a hard mask is utilized to pattern a gate electrode layer and is then removed.


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Hard Mask topics: Semiconductor, Semiconductor Device, Etching Process, Ion Implant, Semiconductor Material, Integrated Circuit, Buffer Layer, Conductive Layer, Semiconductor Circuit, Replacement Gate, Silicide Formation, Novolac Resin, Semiconductor Substrate, Patterned Media, Coercivity

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