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This page is updated frequently with new Germanium-related patent applications. Subscribe to the Germanium RSS feed to automatically get the update: related Germanium RSS feeds. RSS updates for this page: Germanium RSS RSS


Matrix and method for purifying and/or isolating nucleic acids

Worm memory device and process of manufacturing the same

Date/App# patent app List of recent Germanium-related patents
08/14/14
20140225214
 Image sensor comprising isolated germanium photodetectors integrated with a silicon substrate and silicon circuitry patent thumbnailImage sensor comprising isolated germanium photodetectors integrated with a silicon substrate and silicon circuitry
In accordance with the invention, an improved image sensor comprises an array of germanium photosensitive elements integrated with a silicon substrate and integrated with silicon readout circuits. The silicon transistors are formed first on a silicon substrate, using well known silicon wafer fabrication techniques.
08/07/14
20140221638
 Matrix and method for purifying and/or isolating nucleic acids patent thumbnailMatrix and method for purifying and/or isolating nucleic acids
The present invention relates to matrix materials suitable for use in purifying and/or isolating nucleic acids from a biological sample, which matrix comprises a surface comprising at least one element selected from the group consisting of germanium, tin and/or lead, or at least one salt thereof, and methods related therewith.. .
08/07/14
20140220771
 Worm memory device and process of manufacturing the same patent thumbnailWorm memory device and process of manufacturing the same
A process of manufacturing a write-once-read-many-times memory, at least includes the following steps: (a) providing a substrate as a lower electrode; (b) depositing a first oxide layer on the substrate; (c) depositing at least one or more silicon/germanium (si/ge) layers on the first oxide layer; (d) depositing a second oxide layer on the at least one or more si/ge layers; (e) carrying out a rapid thermal annealing to form sige nanocrystals embedded in the first dioxide layer and the second oxide layer; and (f) depositing a conductive layer on the second oxide layer as an upper electrode. The sige nanocrystals embedded in the al2o3 bilayer as the active layer of the worm memory offers high thermal stability, so that low operating voltage, fast writing, ideal reading durability, persistence at high temperature, and the highly reliable memory performance for effectively reading data at high temperature can be achieved..
08/07/14
20140220766
 Planar semiconductor growth on iii-v material patent thumbnailPlanar semiconductor growth on iii-v material
A semiconductor structure includes a iii-v monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the iii-v monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the iii-v monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided..
08/07/14
20140220733
 Antimony and germanium complexes useful for cvd/ald of metal thin films patent thumbnailAntimony and germanium complexes useful for cvd/ald of metal thin films
Antimony, germanium and tellurium precursors useful for cvd/ald of corresponding metal-containing thin films are described, along with compositions including such precursors, methods of making such precursors, and films and microelectronic device products manufactured using such precursors, as well as corresponding manufacturing methods. The precursors of the invention are useful for forming germanium-antimony-tellurium (gst) films and microelectronic device products, such as phase change memory devices, including such films..
08/07/14
20140217588
 Methods of forming copper-based nitride liner/passivation layers for conductive copper structures and the resulting device patent thumbnailMethods of forming copper-based nitride liner/passivation layers for conductive copper structures and the resulting device
One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material..
08/07/14
20140217480
 Methods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer patent thumbnailMethods of forming silicon/germanium protection layer above source/drain regions of a transistor and a device having such a protection layer
Disclosed herein are various methods of forming a silicon/germanium protection layer above source/drain regions of a transistor. One method disclosed herein includes forming a plurality of recesses in a substrate proximate the gate structure, forming a semiconductor material in the recesses, forming at least one layer of silicon above the semiconductor material, and forming a cap layer comprised of silicon germanium on the layer of silicon.
08/07/14
20140217468
 Planar semiconductor growth on iii-v material patent thumbnailPlanar semiconductor growth on iii-v material
A semiconductor structure includes a iii-v monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the iii-v monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the iii-v monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided..
08/07/14
20140217408
 Buffer layer for high performing and low light degraded solar cells patent thumbnailBuffer layer for high performing and low light degraded solar cells
Methods for forming a photovoltaic device include forming a buffer layer between a transparent electrode and a p-type layer. The buffer layer includes a doped germanium-free silicon base material.
08/07/14
20140216534
 Buffer layer for high performing and low light degraded solar cells patent thumbnailBuffer layer for high performing and low light degraded solar cells
Methods for forming a photovoltaic device include forming a buffer layer between a transparent electrode and a p-type layer. The buffer layer includes a doped germanium-free silicon base material.
07/31/14
20140213007
Internal electrical contact for enclosed mems devices
A method of fabricating electrical connections in an integrated mems device is disclosed. The method comprises forming a mems wafer.
07/31/14
20140209985
Germanium photodetector schottky contact for integration with cmos and si nanophotonics
A method of forming an integrated photonic semiconductor structure having a photodetector device and a cmos device may include depositing a dielectric stack over the photodetector device such that the dielectric stack encapsulates the photodetector. An opening is etched into the dielectric stack down to an upper surface of a region of an active area of the photodetector.
07/31/14
20140209976
Transistors and methods of manufacturing the same
A transistor and a method of manufacturing the same are disclosed. The transistor includes a first epitaxial layer, a channel layer, a gate structure and an impurity region.
07/24/14
20140206134
Low temperature deposition of phase change memory materials
A system and method for forming a phase change memory material on a substrate, in which the substrate is contacted with precursors for a phase change memory chalcogenide alloy under conditions producing deposition of the chalcogenide alloy on the substrate, at temperature below 350° c., with the contacting being carried out via chemical vapor deposition or atomic layer deposition. Various tellurium, germanium and germanium-tellurium precursors are described, which are useful for forming gst phase change memory films on substrates..
07/24/14
20140203337
Method of forming gate dielectric layer and method of fabricating semiconductor device
A method for fabricating a semiconductor device includes ion-implanting germanium into a monocrystalline silicon-containing substrate; forming a gate oxide layer over a surface of the monocrystalline silicon-containing substrate and forming, under the gate oxide layer, a germanium-rich region in which the germanium is concentrated, by performing a plasma oxidation process; and crystallizing the germanium-rich region by performing an annealing process.. .
07/24/14
20140203327
Deep gate-all-around semiconductor device having germanium or group iii-v active layer
Deep gate-all-around semiconductor devices having germanium or group iii-v active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate.
07/24/14
20140203325
Integration of germanium photo detector in cmos processing
A method and device are provided for forming an integrated ge or ge/si photo detector in the cmos process by non-selective epitaxial growth of the ge or ge/si. Embodiments include forming an n-well in a si substrate; forming a transistor or resistor in the si substrate; forming an ild over the si substrate and the transistor or resistor; forming a si-based dielectric layer on the ild; forming a poly-si or a-si layer on the si-based dielectric layer; forming a trench in the poly-si or a-si layer, the si-based dielectric layer, the ild, and the n-well; forming ge or ge/si in the trench; and removing the ge or ge/si, the poly-si or a-si layer, and the si-based dielectric layer down to an upper surface of the ild.
07/17/14
20140200384
Dehydrogenation manganese-containing catalyst, its use and method of preparation
A catalyst composition useful for the dehydrogenation of hydrocarbon comprises components (a)-(g). Component (a) is a catalyst substrate.
07/17/14
20140199841
Process for the manufacture of semiconductor devices comprising the chemical mechanical polishing of elemental germanium and/or si1-xgex material in the presence of a cmp composition having a ph value of 3.0 to 5.5
A process for the manufacture of semiconductor devices comprising the chemical mechanical polishing of elemental germanium and/or si1-xgex material with 0.1≦x<1 in the presence of a chemical mechanical polishing (cmp) composition having a ph value in the range of from 3.0 to 5.5 and comprising: (a) inorganic particles, organic particles, or a mixture or composite thereof (b) at least one type of an oxidizing agent, and (c) an aqueous medium.. .
07/17/14
20140199825
Silicon-germanium heterojunction tunnel field effect transistor and preparation method thereof
A silicon/germanium (sige) heterojunction tunnel field effect transistor (tfet) and a preparation method thereof are provided, in which a source region of a device is manufactured on a silicon germanium (sige) or ge region, and a drain region of the device is manufactured in a si region, thereby obtaining a high on-state current while ensuring a low off-state current. Local ge oxidization and concentration technique is used to implement a silicon germanium on insulator (sgoi) or germanium on insulator (goi) with a high ge content in some area.
07/17/14
20140199813
Transistor with longitudinal strain in channel induced by buried stressor relaxed by implantation
Processes for making field effect transistors relax a buried stressor layer to induce strain in a silicon surface layer above the buried stressor layer. The buried stressor layer is relaxed and the surface layer is strained by implantation into at least the buried stressor layer, preferably on both sides of a portion of the surface layer that is to be stressed.
07/17/14
20140199614
Composite, and electrode and fuel cell including the composite
Wherein m1 is silicon (si), germanium (ge), molybdenum (mo), or a combination thereof, and 0≦x≦0.3 and 0≦y≦3; and a yttria-stabilized zirconia including cerium (ce), titanium (ti), or a combination thereof.. .
07/17/14
20140197507
Buried waveguide photodetector
A method of forming an integrated photonic semiconductor structure having a photodetector and a cmos device may include forming the cmos device on a first silicon-on-insulator region, forming a silicon optical waveguide on a second silicon-on-insulator region, and forming a shallow trench isolation (sti) region surrounding the silicon optical waveguide such that the shallow trench isolation electrically isolating the first and second silicon-on-insulator region. Within a first region of the sti region, a first germanium material is deposited adjacent a first side wall of the semiconductor optical waveguide.
07/17/14
20140197458
Finfet device and method of fabricating same
An integrated circuit structure includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate, wherein the isolation regions have opposite sidewalls facing each other. A fin structure includes a silicon fin higher than top surfaces of the isolation regions, a germanium-containing semiconductor region overlapped by the silicon fin, silicon oxide regions on opposite sides of the germanium-containing semiconductor region, and a germanium-containing semiconductor layer between and in contact with the silicon fin and one of the silicon oxide regions..
07/17/14
20140196774
Multi-junction iii-v solar cell
A multi junction solar cell structure includes a top photovoltaic cell including iii-v semiconductor materials and a silicon-based bottom photovoltaic cell. A thin, germanium-rich silicon germanium buffer layer is provided between the top and bottom cells.
07/17/14
20140196773
Multi-junction iii-v solar cell
A multi junction solar cell structure includes a top photovoltaic cell including iii-v semiconductor materials and a silicon-based bottom photovoltaic cell. A thin, germanium-rich silicon germanium buffer layer is provided between the top and bottom cells.
07/10/14
20140193321
Method for producing higher silanes
The invention relates to a method for producing dimeric and/or trimeric silicon compounds, in particular silicon halogen compounds. The claimed method is also suitable for producing corresponding germanium compounds.
07/10/14
20140191332
Pfet devices with different structures and performance characteristics
Disclosed herein is a device that includes a first pfet transistor formed in and above a first active region of a semiconducting substrate, a second pfet transistor formed in and above a second active region of the semiconducting substrate, wherein at least one of a thickness of the first and second channel semiconductor materials or a concentration of germanium in the first and second channel semiconductor materials are different.. .
07/10/14
20140191326
Photonics device and cmos device having a common gate
A semiconductor chip having a photonics device and a cmos device which includes a photonics device portion and a cmos device portion on a semiconductor chip; a metal or polysilicon gate on the cmos device portion, the metal or polysilicon gate having a gate extension that extends toward the photonics device portion; a germanium gate on the photonics device portion such that the germanium gate is coplanar with the metal or polysilicon gate, the germanium gate having a gate extension that extends toward the cmos device portion, the germanium gate extension and metal or polysilicon gate extension joined together to form a common gate; spacers formed on the germanium gate and the metal or polysilicon gate; and nitride encapsulation formed on the germanium gate.. .
07/10/14
20140191302
Photonics device and cmos device having a common gate
A semiconductor chip having a photonics device and a cmos device which includes a photonics device portion and a cmos device portion on a semiconductor chip; a metal or polysilicon gate on the cmos device portion, the metal or polysilicon gate having a gate extension that extends toward the photonics device portion; a germanium gate on the photonics device portion such that the germanium gate is coplanar with the metal or polysilicon gate, the germanium gate having a gate extension that extends toward the cmos device portion, the germanium gate extension and metal or polysilicon gate extension joined together to form a common gate; spacers formed on the germanium gate and the metal or polysilicon gate; and nitride encapsulation formed on the germanium gate. A method is also disclosed pertaining to fabricating the semiconductor chip..
07/10/14
20140191252
Complementary metal oxide semiconductor device, optical apparatus including the same, and method of manufacturing the same
A complementary metal oxide semiconductor (cmos) device includes an n-type first transistor on a silicon substrate, the n-type first transistor including a group iii-v compound semiconductor substrate, and a p-type second transistor on the silicon substrate, the p-type second transistor including a germanium based substrate.. .
07/10/14
20140191180
Low temperature p+ polycrystalline silicon material for non-volatile memory device
A method of forming a non-volatile memory device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region of the substrate.
07/03/14
20140187021
Method of healing defect at junction of semiconductor device using germanium
This invention relates to a method of healing defects at junctions of a semiconductor device, which includes growing a p-ge layer on a substrate, performing ion implantation on the p-ge layer to form an n+ ge region or performing in-situ doping on the p-ge layer and then etching to form an n+ ge region or depositing an oxide film on the p-ge layer and performing patterning, etching and in-situ doping to form an n+ ge layer, forming a capping oxide film, performing annealing at 600˜700° c. For 1˜3 hr, and depositing an electrode, and in which annealing enables ge defects at n+/p junctions to be healed and the depth of junctions to be comparatively reduced, thus minimizing leakage current, thereby improving properties of the semiconductor device and achieving high integration and fineness of the semiconductor device..
07/03/14
20140185981
Silicon photonics photodetector integration
A method of forming an integrated photonic semiconductor structure having a photonic device and adjacent cmos devices may include depositing a first silicon nitride layer over the adjacent cmos devices and depositing an oxide layer over the first silicon nitride layer, wherein the oxide layer conformally covers the first silicon nitride layer and the underlying adjacent cmos devices to form a substantially planarized surface over the adjacent cmos devices. A second silicon nitride layer is then deposited over the oxide layer and a region corresponding to forming the photonic device.
07/03/14
20140183666
Flourine-stabilized interface
Methods for forming an electronic device having a fluorine-stabilized semiconductor substrate surface are disclosed. In an exemplary embodiment, a layer of a high-κ dielectric material is formed together with a layer containing fluorine on a semiconductor substrate.
06/26/14
20140179973
Method of olefin metathesis using a catalyst based on a spherical material comprising oxidised metal particles trapped in a mesostructured matrix
A process for metathesis of olefins, bringing olefins into contact with a catalyst activated by heating to a temperature in the range 100° c. To 1000° c.
06/26/14
20140179958
Catalysts and processes for producing butanol
In one embodiment, the invention is to a process for producing a catalyst composition for converting ethanol to higher alcohols, such as butanol. The process comprises contacting magnesium carbonate with one or more metal precursors to form a catalyst intermediate and calcining the catalyst intermediate to form the catalyst composition that comprises the one or more metals and magnesium oxide.
06/26/14
20140179110
Methods and apparatus for processing germanium containing material, a iii-v compound containing material, or a ii-vi compound containing material disposed on a substrate using a hot wire source
Methods and apparatus for processing a germanium containing material, a iii-v compound containing material, or a ii-vi compound containing material disposed on a substrate using a hot wire source are provided herein. In some embodiments, a method for processing a material disposed on a substrate, wherein the material is at least one of a germanium containing material, a iii-v compound containing material, or a ii-vi compound containing material, includes providing a hydrogen containing gas to a first process chamber having a plurality of filaments; flowing a current through the plurality of filaments to raise a temperature of the plurality of filaments to a first temperature sufficient to decompose at least a portion of the hydrogen containing gas to form hydrogen atoms; and treating a surface of an exposed material on a substrate by exposing the material to hydrogen atoms formed by the decomposition of the hydrogen containing gas..
06/26/14
20140179095
Methods and systems for controlling gate dielectric interfaces of mosfets
Embodiments provided herein describe methods and systems for forming gate dielectrics for field effect transistors. A substrate including a germanium channel and a germanium oxide layer on a surface of the germanium channel is provided.
06/26/14
20140179049
Silicon/germanium-based nanoparticle pastes with ultra low metal contamination
Silicon based nanoparticle inks are described with very low metal contamination levels. In particular, metal contamination levels can be established in the parts-per-billion range.
06/26/14
20140178777
Protected anode, lithium air battery including the same, and method of preparing ion conductive protective layer
Wherein m is at least one element selected from titanium (ti), zirconium (zr), and germanium (ge), 0≦a≦1, 0≦b≦1, 0≦c≦1, 0≦d≦0.5, 0≦e≦0.1, and 0≦f≦1.. .
06/26/14
20140175676
Method for bonding of group iii-nitride device-on-silicon and devices obtained thereof
A method for flip chip bonding a gan device formed on a silicon substrate is described. The method includes providing a silicon substrate having a gan device thereon, the gan device comprising at least one gallium-nitride layer near the silicon substrate and remote from the silicon substrate a dielectric layer comprising at least one via configured to electrically contact the at least one gallium-nitride layer, forming a stiffener layer over the gan device leaving the at least one via exposed, flip chip bonding the gan device to a submount, wherein the stiffener layer physically contacts the submount and the submount is electrically connected to the at least gallium-nitride layer through the via, and completely removing the silicon substrate exposing the gan device.
06/26/14
20140175618
Transition metal aluminate and high k dielectric semiconductor stack
Methods of forming a high k dielectric semiconductor stack are described. A semiconductor substrate is provided, in which the native oxide layer is removed.
06/26/14
20140175556
Semiconductor device having v-shaped region
Among other things, a semiconductor device or transistor and a method for forming the semiconductor device are provided for herein. The semiconductor device comprises one or more v-shaped recesses in which stressed monocrystalline semiconductor material, such as silicon germanium, is grown, to form at least one of a source or a drain of the semiconductor device.
06/26/14
20140175543
Conversion of thin transistor elements from silicon to silicon germanium
Embodiments of the present disclosure provide techniques and configurations associated with conversion of thin transistor elements from silicon (si) to silicon germanium (sige). In one embodiment, a method includes providing a semiconductor substrate having a channel body of a transistor device disposed on the semiconductor substrate, the channel body comprising silicon, forming a cladding layer comprising germanium on the channel body, and annealing the channel body to cause the germanium to diffuse into the channel body.
06/26/14
20140175513
Structure and method for integrated devices on different substartes with interfacial engineering
The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first semiconductor material and a first reactivity; and a low reactivity capping layer of disposed on the semiconductor substrate, wherein the low reactivity capping layer includes a second semiconductor material and a second reactivity less than the first reactivity, the low reactivity capping layer includes silicon germanium si1−xgex and x is less than about 30%..
06/26/14
20140175510
Germanium photodetector and method of fabricating the same
Provided is a germanium photodetector having a germanium epitaxial layer formed without using a buffer layer and a method of fabricating the same. In the method, an amorphous germanium layer is formed on a substrate.
06/26/14
20140175490
Silicon-germanium light-emitting element
Provided is an element structure whereby it is possible to produce a silicon-germanium light-emitting element enclosing an injected carrier within a light-emitting region. Also provided is a method of manufacturing the structure.
06/19/14
20140170852
Process for the manufacture of semiconductor devices comprising the chemical mechanical polishing of elemental germanium and/or si1-xgex material in the presence of a cmp composition comprising a specific organic compound
A process for the manufacture of semiconductor devices comprising the chemical mechanical polishing of elemental germanium and/or si1-xgex material with 0.1≦x<1 in the presence of a chemical mechanical polishing (cmp) composition comprising: (a) inorganic particles, organic particles, or a mixture or composite thereof, (b) at least one type of an oxidizing agent, (c) at least one type of an organic compound which comprises at least {k} moieties (z), but excluding salts whose anions are inorganic and whose only organic cation is [nr11r12r13r14]+, wherein {k} is 1, 2 or 3, (z) is a hydroxyl (—oh), alkoxy (—or1), heterocyclic alkoxy (—or1 as part of a heterocyclic structure), carboxylic acid (—cooh), carboxylate (—coor2), amino (—nr3r4), heterocyclic amino (—nr3r4 as part of a heterocyclic structure), imino (═n—r5 or —n═r6), heterocyclic imino (═n—r5 or —n═r6 as part of a heterocyclic structure), phosphonate (—p(=0)(or7)(or8)), phosphate (-0-p(=0)(or9)(or10)), phosphonic acid (—p(=0)(oh)2), phosphoric acid (-0-p(=0)(oh)2) moiety, or their protonated or deprotonated forms, r1, r2, r7, r9 is—independently from each other—alkyl, aryl, alkylaryl, or arylalkyl, r3, r4, r5, r8, r10 is—independently from each other—h, alkyl, aryl, alkylaryl, or arylalkyl, r6 is alkylene, or arylalkylene, r11, r12, r13 is—independently from each other—h, alkyl, aryl, alkylaryl, or arylalkyl, and r11, r12, r13 does not comprise any moiety (z), r14 is alkyl, aryl, alkylaryl, or arylalkyl, and r14 does not comprise any moiety (z), and (d) an aqueous medium.. .
06/19/14
20140170839
Methods of forming fins for a finfet device wherein the fins have a high germanium content
One illustrative method disclosed herein includes forming a silicon/germanium fin in a layer of insulating material, wherein the fin has a first germanium concentration, recessing an upper surface of the layer of insulating material so as to expose a portion of the fin, performing an oxidation process so as to oxidize at least a portion of the fin and form a region in the exposed portion of the fin that has a second germanium concentration that is greater than the first germanium concentration, removing the oxide materials from the fin that was formed during the oxidation process and forming a gate structure that is positioned around at least the region having the second germanium concentration.. .
06/19/14
20140170827
Tunneling field effect transistor (tfet) formed by asymmetric ion implantation and method of making same
An embodiment integrated circuit device and a method of making the same. The embodiment method includes forming a first nitride layer over a gate stack supported by a substrate, implanting germanium ions in the first nitride layer in a direction forming an acute angle with a top surface of the substrate, etching away germanium-implanted portions of the first nitride layer to form a first asymmetric nitride spacer confined to a first side of the gate stack, the first asymmetric nitride spacer protecting a first source/drain region of the substrate from a first ion implantation, and implanting ions in a second source/drain region of the substrate on a second side of the gate stack unprotected by the first asymmetric nitride spacer to form a first source/drain..
06/19/14
20140170826
Biaxial strained field effect transistor devices
A process for forming contacts to a field effect transistor provides edge relaxation of a buried stressor layer, inducing strain in an initially relaxed surface semiconductor layer above the buried stressor layer. A process can start with a silicon or silicon-on-insulator substrate with a buried silicon germanium layer having an appropriate thickness and germanium concentration.
06/19/14
20140170817
Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications
A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an si material and a sil-xgex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising ge/sil-ygey and a covering region comprising sio2 and enclosing the center region..
06/19/14
20140167108
Semiconductor devices with germanium-rich active layers & doped transition layers
Semiconductor device stacks and devices made there from having ge-rich device layers. A ge-rich device layer is disposed above a substrate, with a p-type doped ge etch suppression layer (e.g., p-type sige) disposed there between to suppress etch of the ge-rich device layer during removal of a sacrificial semiconductor layer richer in si than the device layer.
06/12/14
20140162436
Inorganic nanostructure reactive direct-write and growth
Methods for forming inorganic nanostructures are provided. The methods create the inorganic nanostructures by positioning a writing electrode (e.g., a conductive “stamp”) spaced nanometers above a substrate such that a precursor is intermediate the two.
06/12/14
20140162426
Bipolar transistor manufacturing method, bipolar transistor and integrated circuit
Disclosed is a method of manufacturing a bipolar transistor, comprising providing a substrate (10) comprising a first isolation region (12) separated from a second isolation region by an active region (11) comprising a collector impurity; forming a layer stack over said substrate, said layer stack comprising a base layer (14, 14′), a silicon capping layer (15) over said base layer and a silicon-germanium (sige) base contact layer (40) over said silicon capping layer; etching the sige base contact layer to form an emitter window (50) over the collector impurity, wherein the silicon emitter cap layer is used as etch stop layer; forming sidewall spacers (22) in the emitter window; and filling the emitter window with an emitter material (24). A bipolar transistor manufactured in accordance with this method and an ic comprising one or more of such bipolar transistors are also disclosed..
06/12/14
20140159183
High-efficiency bandwidth product germanium photodetector
A high-efficiency bandwidth product germanium photodetector includes a silicon substrate having an opening-down three-sided groove formed by etching; a metallic reflective mirror layer formed by plating along an internal periphery of the opening-down three-sided groove of the silicon substrate; a light absorbent layer between the metallic reflective mirror layer and a dielectric reflective mirror layer. The light absorbent layer can be p-i-n type or other types.
06/12/14
20140159129
Near-infrared-visible light adjustable image sensor
The disclosure belongs to the field of semiconductor photoreceptors, in particular to a near-infrared-visible light adjustable image sensor. By adding a transfer transistor, the disclosure integrates a silicon-based photoelectric diode and a silicon germanium-based photoelectric diode on the same chip to realize that the silicon-based photoelectric diode and a silicon germanium-based photoelectric diode are controlled by the same readout circuit at different time, thus widening the spectrum response scope of the photoreceptor, realizing high integration and multifunction of the chip and reducing the manufacturing cost of the chip.
06/12/14
20140158964
Semiconductor devices having blocking layers and methods of forming the same
A semiconductor device includes a lower interconnection having second conductivity-type impurities on a substrate having first conductivity-type impurities. A switching device is on the lower interconnection.
06/05/14
20140154883
Tungsten nucleation process to enable low resistivity tungsten feature fill
Methods for depositing low resistivity tungsten in features of substrates in semiconductor processing are disclosed herein. Methods involve using a germanium-containing reducing agent during tungsten nucleation layer deposition to achieve thin, low resistivity nucleation layers..
06/05/14
20140154875
Method of epitaxial germanium tin alloy surface preparation
Methods of preparing a clean surface of germanium tin or silicon germanium tin layers for subsequent deposition are provided. An overlayer of ge, doped ge, another gesn or sigesn layer, a doped gesn or sigesn layer, an insulator, or a metal can be deposited on a prepared gesn or sigesn layer by positioning a substrate with an exposed germanium tin or silicon germanium tin layer in a processing chamber, heating the processing chamber and flowing a halide gas into the processing chamber to etch the surface of the substrate using either thermal or plasma assisted etching followed by depositing an overlayer on the substantially oxide free and contaminant free surface.
06/05/14
20140151886
Semiconductor element and method for manufacturing semiconductor element
Provided is a semiconductor element in which atomic interdiffusion between a semiconductor region and an electrode is suppressed and increase in the contact resistance is suppressed even in cases where the semiconductor element is exposed to high temperatures during the production processes or the like. A semiconductor element of the present invention is provided with: a semiconductor region that contains silicon; an electrode that contains aluminum; and a diffusion barrier layer that is interposed between the semiconductor region and the electrode and contains germanium.
06/05/14
20140151814
Methods for forming fins for metal oxide semiconductor device structures
Methods are disclosed for forming fins in transistors. In one embodiment, a method of fabricating a device includes forming silicon fins on a substrate and forming a dielectric layer on the substrate and adjacent to the silicon fins such that an upper region of each silicon fin is exposed.
06/05/14
20140151750
Heterojunction bipolar transistor
Structures and methods of making a heterojunction bipolar transistor (hbt) device that include: an n-type collector region disposed within a crystalline silicon layer; a p-type intrinsic base comprising a boron-doped silicon germanium crystal that is disposed on a top surface of an underlying crystalline si layer, which is bounded by shallow trench isolators (stis), and that forms angled facets on interfaces of the underlying crystalline si layer with the shallow trench isolators (stis); a ge-rich, crystalline silicon germanium layer that is disposed on the angled facets and not on a top surface of the p-type intrinsic base; and an n-type crystalline emitter disposed on a top surface and not on the angled lateral facets of the p-type intrinsic base.. .
06/05/14
20140151644
Heterojunction tunneling field effect transistors, and methods for fabricating the same
The present invention relates to a heterojunction tunneling effect transistor (tfet), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type.
06/05/14
20140151639
Nanomesh complementary metal-oxide-semiconductor field effect transistors
An alternating stack of first and second semiconductor layers is formed. Fin-defining mask structures are formed over the alternating stack.
05/22/14
20140142329
Catalyst support and process for the preparation thereof
An amorphous catalyst support comprising at least a first oxide selected from the group consisting of: silica, germanium oxide, titanium oxide, zirconium oxide or mixtures thereof, preferably silica gel beads or diatomaceous earth; a group 3 metal oxide; and anions in an amount not greater than 10% by weight of the catalyst support; wherein the group 3 metal oxide is incorporated in the first oxide structure at the molecular level. The catalyst support is prepared by (a) mixing the first oxide, with an anhydrous source of the group 3 metal oxide, and water, at a ph above 11, thus forming a suspension, (b) washing the catalyst support with water, (c) separating the catalyst support from the water, and (d) optionally drying and/or calcining the catalyst support.
05/22/14
20140141542
Methods for depositing films on sensitive substrates
Methods and apparatus to form films on sensitive substrates while preventing damage to the sensitive substrate are provided herein. In certain embodiments, methods involve forming a bilayer film on a sensitive substrate that both protects the underlying substrate from damage and possesses desired electrical properties.


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Germanium topics: Semiconductor, Semiconductor Material, Transistors, Crystallin, Optical Fiber, Bipolar Transistor, Electrical Signal, Level Shift, Source Follower, Transimpedance Amplifier, Photodiode, Semiconductor Substrate, Semiconductors, Plasma Doping, Fluorescent Probe

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