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Germ-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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Digital alloy germanium heterojunction solar cell
International Business Machines Corporation
June 22, 2017 - N°20170179316

A photovoltaic device includes a digital alloy buffer layer including a plurality of alternating layers of semiconductor material. An absorption layer epitaxially is grown on the digital alloy buffer layer, an intrinsic layer is formed on the absorption layer and a doped layer is formed on the intrinsic layer. A conductive contact is formed on the doped layer.
Mos devices with non-uniform p-type impurity profile
Taiwan Semiconductor Manufacturing Company, Ltd.
June 22, 2017 - N°20170179287

An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and a recess extending into the semiconductor substrate, wherein the recess is adjacent to the gate stack. A silicon germanium region is disposed in the recess, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is ...
Method for making iii-v nanowire quantum well transistor
Zing Semiconductor Corporation
June 22, 2017 - N°20170179269

The present invention provides a field effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first iii-v compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first iii-v compound layer, and source/drain electrodes ...
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Method for manufacturing a si-based high-mobility cmos device with stacked channel layers, and resulting devices
Imec Vzw
June 22, 2017 - N°20170178971

A device and method for manufacturing a si-based high-mobility cmos device is provided. The method includes the steps of: (i) providing a silicon substrate having a first insulation layer on top and a trench into the silicon; (ii) manufacturing a iii-v semiconductor channel layer above the first insulation layer by depositing a first dummy layer of a sacrificial material, covering ...
Single crystal rhombohedral epitaxy of sige on sapphire at 450°c - 500°c substrate ...
U.s.a. As Represented By The Administrator Of The National Aeronautics And Space Administration
June 22, 2017 - N°20170178903

Various embodiments may provide a low temperature (i. E., less than 850° c.) method of silicon-germanium (sige) on sapphire (al2o3) (sige/sapphire) growth that may produce a single crystal film with less thermal loading effort to the substrate than conventional high temperature (i. E., temperatures above 850° c.) methods. The various embodiments may alleviate the thermal loading requirement of ...
Silicon germanium thickness and composition determination using combined xps and xrf technologies
U.s.a. As Represented By The Administrator Of The National Aeronautics And Space Administration
June 22, 2017 - N°20170176357

Systems and approaches for silicon germanium thickness and composition determination using combined xps and xrf technologies are described. In an example, a method for characterizing a silicon germanium film includes generating an x-ray beam. A sample is positioned in a pathway of said x-ray beam. An x-ray photoelectron spectroscopy (xps) signal generated by bombarding said sample with said x-ray beam ...
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Methods for improving plant embryo development
Weyerhaeuser Nr Company
June 22, 2017 - N°20170175076

Provided is a method of improving plant embryo development and/or germination. The method comprises developing plant embryos in the presence of nitric oxide (no). The method entails the step of incubating plant embryogenic suspensor mass (esm) in, or on, a development medium containing a nitric oxide donor for a period of time to develop mature somatic embryos. The method ...
Electrochemical system for disinfecting and cleaning contact lenses
Novartis Ag
June 22, 2017 - N°20170173206

The present invention is generally related to a lens care system and method for disinfecting and cleaning contact lenses. A lens care system or method of the invention is based on electrolysis of an aqueous chloride solution for generating germicide species (e. G., chlorine, hypochlorous acid, hypochlorite, or combinations thereof) and subsequent in-situ electrolysis of hypochlorous acid or hypochlorite in ...
Room and area disinfection utilizing pulsed light with modulated power flux and light systems with ...
Xenex Disinfection Services Llc.
June 22, 2017 - N°20170173195

Disinfection methods and apparatuses are provided which generate pulses of germicidal light at a frequency greater than 20 hz and project the pulses of light to surfaces at least 1. 0 meter from the disinfection apparatus. The pulses of light comprise a pulse duration and an energy flux sufficient to generate a power flux between approximately 200 w/m2 and approximately 5000 w/m2 of ...
Methods for producing corn plants with northern leaf blight resistance and compositions thereof
Monsanto Technology Llc
June 22, 2017 - N°20170172098

The present disclosure is in the field of plant breeding and disease resistance. The disclosure provides methods for breeding corn plants having northern leaf blight (nlb) resistance using marker-assisted selection. The disclosure further provides corn germplasm resistant to nlb. The disclosure also provides markers associated with nlb resistance loci for introgressing these loci into elite germplasm in a breeding program, ...
Transistor, circuit, semiconductor device, display device, and electronic device
Semiconductor Energy Laboratory Co., Ltd.
June 15, 2017 - N°20170170326

A transistor in which a change in characteristics is small is provided. A circuit, a semiconductor device, a display device, or an electronic device in which a change in characteristics of the transistor is small is provided. The transistor includes an oxide semiconductor; a channel region is formed in the oxide semiconductor; the channel region contains indium, an element m, ...
Silicon germanium alloy fins with reduced defects
International Business Machines Corporation
June 15, 2017 - N°20170170321

A silicon germanium alloy is formed on sidewall surfaces of a silicon fin. An oxidation process or a thermal anneal is employed to convert a portion of the silicon fin into a silicon germanium alloy fin. In some embodiments, the silicon germanium alloy fin has a wide upper portion and a narrower lower portion. In such an embodiment, the wide ...
Source and drain stressors with recessed top surfaces
Taiwan Semiconductor Manufacturing Company, Ltd.
June 15, 2017 - N°20170170319

An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are ...
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Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region
Stmicroelectronics, Inc.
June 15, 2017 - N°20170170299

An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes: forming a gate stack structure on an epitaxial silicon region, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; encapsulating the epitaxial silicon region under the gate stack structure with ...
Extremely thin silicon-on-insulator silicon germanium device without edge strain relaxation
International Business Machines Corporation
June 15, 2017 - N°20170170197

A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium ...
Extremely thin silicon-on-insulator silicon germanium device without edge strain relaxation
International Business Machines Corporation
June 15, 2017 - N°20170170195

A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium ...
Tall strained high percentage silicon germanium fins for cmos
International Business Machines Corporation
June 15, 2017 - N°20170170182

A silicon germanium alloy (sige) fin having a first germanium content is provided within first and second device regions. Each sige fin is located on a sacrificial material stack and an oxide material surrounds each sige fin. A germanium layer is formed atop each sige fin within one of the device regions, while a sige layer having a second germanium ...
Novel channel silicon germanium formation method
International Business Machines Corporation
June 15, 2017 - N°20170170178

A method of making a channel region in a semiconductor device includes providing a substrate having a first transistor area arranged adjacent to a second transistor area; growing an epitaxial layer on the second transistor area of the substrate; forming a trench in the substrate between the first transistor area and the second transistor area; performing a condensation technique to ...
Bulk silicon germanium finfet
International Business Machines Corporation
June 15, 2017 - N°20170170173

A bulk sige finfet which includes: a plurality of sige fins and a bulk semiconductor substrate, the sige fins extending from the bulk semiconductor substrate; the sige fins having a top portion and a bottom portion, a part of the bottom portion being doped to form a punchthrough stop; the bulk semiconductor substrate having a top portion in contact with ...
Selective oxidation of buried silicon-germanium to form tensile strained silicon finfets
International Business Machines Corporation
June 15, 2017 - N°20170170079

An integrated circuit included n-type finfets in an n-region and p-type finfets in a p-region. The integrated circuit includes: an n-type fin in the n-region comprising a silicon (si) fin portion disposed on an oxidized fin portion, the si fin portion consisting essentially of si, and the oxidized fin portion consisting essentially of si, germanium (ge) and oxygen; and a ...
Novel channel silicon germanium formation method
International Business Machines Corporation
June 15, 2017 - N°20170170055

A method of making a channel region in a semiconductor device includes providing a substrate having a first transistor area arranged adjacent to a second transistor area; growing an epitaxial layer on the second transistor area of the substrate; forming a trench in the substrate between the first transistor area and the second transistor area; performing a condensation technique to ...
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