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Frequency Detector patents

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 Signal booster for a controllable antenna system patent thumbnailSignal booster for a controllable antenna system
A controllable antenna system is disclosed. The system comprises a directional antenna configured to be directed in a selected direction.
Wilson Electronics, Llc


 Apparatus for determining or monitoring the fill level of a medium in a container patent thumbnailApparatus for determining or monitoring the fill level of a medium in a container
An apparatus for determining or monitoring the fill level or a predetermined limit level of a medium in a container, comprising a self excited system comprising an oscillation producing unit for producing electromagnetic waves within a predetermined frequency band; at least one sensor having an electrode, wherein the sensor is arranged at a predetermined angle to the longitudinal axis of the container, wherein the electrode is supplied with the electromagnetic waves, wherein the at least one sensor is arranged relative to the medium in such a manner that the phase of the electromagnetic waves reflected at the interface of the medium changes under the influence of the medium; and a feedback loop, which feeds the electromagnetic waves back to the at least one sensor, whereby the frequency of the self excited system is determined, a frequency detector, which registers the frequency of the electromagnetic waves, and an evaluation unit, which based on the registered frequency ascertains the relative dielectric constant and/or the permeability of the medium dependent on the respective fill level and based on the ascertained relative dielectric constant or the permeability of the medium determines the fill level or the reaching of the predetermined limit level of the medium in the container.. .
Endress+hauser Gmbh+co. Kg


 Phase locked loop with sub-harmonic locking prevention functionality patent thumbnailPhase locked loop with sub-harmonic locking prevention functionality
Embodiments relate to type-i plls that do not lock at a sub-harmonic frequency of a reference clock signal by controlling timing of charging or discharging of one or more capacitors in the plls. A phase frequency detector (pfd) of a type-i pll can prevent sub-harmonic locking by generating a clear output signal to cause a sampling capacitor of pll's loop filter to discharge only during a time period when the sampling capacitor is not being charged.
Lattice Semiconductor Corporation


 Servo controller for measuring lubrication characteristics of a machine by experimental modal analysis patent thumbnailServo controller for measuring lubrication characteristics of a machine by experimental modal analysis
A servo controller includes: a sinusoidal wave disturbance input unit for supplying a sinusoidal wave disturbance to a speed control loop including a speed command generator, a torque command generator and a speed detector; a frequency response calculator for estimating the gain and phase from the output of the speed control loop; a resonance frequency detector for detecting resonance frequencies at which the gain becomes maximum; a resonance mode characteristics analyzer for estimating resonance characteristics from the frequency response; and, a reference modal damping ratio retainer for retaining a reference modal damping ratio as a resonance characteristic corresponding to the reference lubricating condition, and the resonance mode characteristics analyzer calculates lubrication characteristics on the basis of the reference modal damping ratio and the measured modal damping ratio at the resonance frequency corresponding to the reference modal damping ratio.. .
Fanuc Corporation


 Gear shifting from binary phase detector to pam phase detector in cdr architecture patent thumbnailGear shifting from binary phase detector to pam phase detector in cdr architecture
A device and method for providing clock data recovery (cdr) in a receiver is disclosed. The method comprises receiving a phase amplitude modulation (pam) signal; on startup, using a non-return-to-zero (nrz)-based phase frequency detector (pfd) to acquire signal frequency from the received pam signal; and responsive to a determination, switching to a pam phase detector (pd) for steady state operation..
Texas Instruments Incorporated


 High performance phase frequency detectors patent thumbnailHigh performance phase frequency detectors
A phase frequency detector with two stages of operation; each stage containing two d flip-flops. Each d flip-flop is interconnected to eliminate detection dead zone while avoiding glitches and incorrect output conditions for fast phase locked loop convergence and wide-band applications..
Wright State University


 Apparatus and  detecting phase lock in an electronic device patent thumbnailApparatus and detecting phase lock in an electronic device
The present disclosure provides a method and a phase lock detection apparatus for detecting whether a phase of an output signal is locked to the phase of a reference signal. The apparatus includes a first divider that individually frequency-divides first and second pulse signals, a phase frequency detector that outputs third and fourth pulse signals that correspond to a phase difference between the frequency-divided first and second pulse signals, a second divider that individually frequency-divides the third and fourth pulse signals, and a determiner that determines whether a phase of the second pulse signal is locked, based on the frequency-divided third and fourth pulse signals..
Samsung Electronics Co., Ltd


 Apparatus and  combining multiple charge pumps in phase locked loops patent thumbnailApparatus and combining multiple charge pumps in phase locked loops
A frequency synthesizer includes circuitry configured to generate two or more feedback clocks based on the oscillation signals output from a voltage-controlled oscillator. The circuitry also modulates the feedback clocks based on fractional offsets from a reference clock frequency for input into two or more phase and frequency detectors.
Broadcom Corporation


 Eeg-based brain-machine interface  recognizing human-intention using flickering visual stimulus patent thumbnailEeg-based brain-machine interface recognizing human-intention using flickering visual stimulus
A brain-machine interface apparatus and a method of the same are provided. To elaborate the brain-machine interface apparatus may include a display where a plurality of light-emitting points (or lines) flickering with their individual set frequencies are arranged a flickering controller that divides the plurality of the light-emitting points (or lines) into a plurality of groups, and sets the set frequencies for the groups; an eeg measurement unit that detects eeg signals of a user who watches the display without gaze-shift; a frequency detector that detects one or more (their harmonic or combination) frequency components from the measured eeg signals; a shape analysis unit that decodes an originally intended shape according to the user's imagination based on the one or more detected frequency components and the set frequencies; and a result output unit that outputs information of the embodied originally intended shape..
Korea University Research And Business Foundation


 Dynamic measurement of frequency synthesizer noise spurs or phase noise patent thumbnailDynamic measurement of frequency synthesizer noise spurs or phase noise
A method of measuring phase noise (pn). A pll frequency synthesizer is provided including a first phase frequency detector (pfd) receiving a reference frequency signal coupled to a first charge pump (cp) coupled to a vco having an output fedback to the first pfd through a feedback divider that provides a divided frequency signal to the first pfd which outputs an error signal, and pn measurement circuitry including a replica cp coupled to an output of a second pfd or the first pfd.

Differential phase-frequency detector


A phase-frequency detector (pfd) is electrically coupled to a charge pump of a phase-locked-loop (pll). The pfd includes a first differential latch electrically coupled to the charge pump.
International Business Machines Corporation


Signal acquisition and distance variation measurement system for laser ranging interferometers


A signal acquisition and distance variation measurement system for laser ranging interferometers comprising a signal acquisition unit. This unit comprises a frequency detection subsystem to detect the frequency of a received laser beam measurement signal which is buried in noise, wherein the subsystem comprises an acquisition subsystem with a wavelet packet decomposition unit and a phase/frequency detector pll; a main pll unit being coupled to the frequency detection subsystem for receiving the detected frequency of the measurement signal for phase estimation of the measurement signal; and a phasemeter band detection subsystem for detecting whether the measurement signal frequency is higher or lower than a reference signal frequency of a reference laser beam by operating a known change to the frequency of the reference signal and measuring the consequent change in the frequency of an interference signal for having the phase of reference signal locked to the measurement signal phase..
Airbus Ds Gmbh


Electric brake device


A brake device includes a control device which performs feedback control using a braking force of a linear motion mechanism as a controlled variable. The control device includes a computing unit for computing an operating quantity (voltage applied to an electric motor) for canceling out fluctuations in braking force, and a frequency detector for detecting the frequency of the operating quantity.
Ntn Corporation


Transmitting and receiving digital and analog signals across an isolator using amplitude modulation


Various embodiments of systems for transmitting and receiving a plurality of signals across an isolation material are disclosed. In one embodiment, a first signal may be modulated into a first modulated signal.
Avago Technologies General Ip (singapore) Pte. Ltd.


Phase frequency detector (pfd) circuit with improved lock time


Described examples include circuitry and methods to control lock time of a phase lock loop (pll) or other locking circuit, in which a phase frequency detector (pfd) circuit is switched from a first mode to provide a control input signal to a charge pump as a pulse signal having a pulse width corresponding to a phase difference between a reference clock signal and a feedback clock signal to a second mode to hold the control input signal at a constant value for a predetermined time in response to detected cycle slip conditions to enhance loop filter current during frequency transitions to reduce lock time for the locking circuit.. .

Integrated circuit capacitors for analog microcircuits


Dual gate fd-soi transistors are used as mosfet capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate fd-soi devices helps to reduce unstable oscillations and improve circuit performance.

Microelectromechanical device having an oscillating mass and a forcing stage, and controlling a microelectromechanical device


A microelectromechanical device includes: a body; a movable mass, elastically coupled to the body and oscillatable with respect to the body according to a degree of freedom; a frequency detector, configured to detect a current oscillation frequency of the movable mass; and a forcing stage, capacitively coupled to the movable mass and configured to provide energy to the movable mass through forcing signals having a forcing frequency equal to the current oscillation frequency detected by the frequency detector, at least in a first transient operating condition.. .

Conveyor belt measuring system


A conveyor belt and a sensing system for sensing various conditions on a conveyor belt. The belt includes an array of sensing elements embedded in the belt to measure belt conditions.

Clock monitor and system on chip including the same


A system on chip includes a plurality of function blocks configured to perform predetermined functions, respectively, a clock control unit configured to generate a plurality of operating clock signals that are provided to the plurality of function blocks, respectively, a clock monitor configured to monitor frequencies of the operating clock signals to generate an interrupt signal, and a processor configured to control the frequencies of the operating clock signals based on the interrupt signal. The clock monitor includes a selector configured to select one of the operating clock signals to provide a selected clock signal, a frequency detector configured to detect a frequency of the selected clock signal to provide a detection frequency, and an interrupt generator configured to generate the interrupt signal based on the detection frequency, where the interrupt signal indicates a frequency abnormality of the operating clock signal corresponding to the selected clock signal..
Samsung Electronics Co., Ltd.


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Rf circuit


An rf circuit for providing phase coherent signals, an rf heating apparatus comprising the rf circuit and a method for providing phase coherent signals in an rf circuit. The rf circuit has a first frequency synthesiser including a fractional-n phase locked loop and a second frequency synthesiser including an integer-n phase locked loop.
Nxp B.v.


Integrated circuit with distributed clock tampering detectors


A circuit configuration for secure application includes several internal frequency detectors arranged in digital units at critical points of an integrated circuit. The clock detectors are concealed in the digital part of the integrated circuit each as a standard cell (flip-flop unit) in order to prevent any external manipulation and in order to hide its function.
Em Microelectronic-marin Sa


Display apparatus and driving the display apparatus


A display apparatus includes an image analyzer that analyzes image data and outputs an interrupt signal at a period during which the image data of a low frequency change to the image data of a high frequency, a frequency detector that detects the high frequency, a frame rate controller that outputs a vertical synch signal of the high frequency in response to the interrupt signal, a polarity compensation controller that determines a last frame of the low frequency based on an interrupt period at which the interrupt signal is generated, generates a reversed polarity signal with respect to a polarity signal of the last frame and outputs the reversed polarity signal during a polarity compensation period close to the interrupt period, and a data driver circuit that outputs a data signal based on the reversed polarity signal to a data line during the polarity compensation period.. .
Samsung Display Co., Ltd.


Rotary speed sensor


The present utility model relates to a rotary speed sensor, comprising at least one sensor element (1), an analog signal processing block (2), a digital core (5) and a digital output end (10), wherein the analog signal processing block (2) comprises an analog signal regulating block (3) and an analog comparator (4), the digital core (5) comprises a digital signal processing means (7), wherein the digital core (5) additionally comprises a frequency detector (6), for detecting a frequency of a magnetic input signal of the rotary speed sensor, so that when the frequency is greater than a predetermined frequency, a time continuous signal path comprising the analog signal processing block (2) is formed, and when the frequency is smaller than a predetermined frequency, a time discrete digital signal path comprising the digital signal processing means (7) is formed.. .
Infineon Technologies Ag


Referenceless clock recovery circuit with wide frequency acquisition range


A full-rate referenceless clock-data recovery architecture with neither a frequency detector nor a lock detector that allows both frequency and phase locking in a single loop. According to one embodiment, a referenceless clock data recovery (cdr) circuit, comprises a digital control circuit (dcc), a phase and strobe point detector circuit (pspd), and an lc voltage control oscillator (lc vco) electrically coupled to the pspd and dcc such that a frequency of the lc vco decreases when a negative strobe point is detected and an initial frequency of the lc vco is higher than an input data bit rate..
The Regents Of The University Of California


Circuits and methods for eliminating reference spurs in fractional-n frequency synthesis


Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (pll) such as a frac-n pll of a frequency synthesizer can include a phase frequency detector (pfd) configured to receive a reference signal and a feedback signal.
Skyworks Solutions, Inc.


Fast acquisition frequency detector


A phase-frequency detector (pfd) circuit that includes a binary phase detector and a ternary phase detector coupled to the binary phase detector. The binary phase detector is configured to, based on the pfd circuit being in a frequency acquisition state, compare a clock signal with a data signal and output up and down signals based on the comparison.
Texas Instruments Incorporated


Position detection apparatus of micro-electromechanical system and detection method thereof


A position detection apparatus for detecting position information of a micro-electromechanical system apparatus includes an oscillating circuit, a carrier frequency detector, and a demodulator. The oscillating circuit generates an oscillating signal according to an equivalent capacitance provided by the micro-electromechanical system apparatus.
Lite-on Technology Corporation


Broadband frequency detector


Provided is a broadband frequency detector, more particularly, to a frequency detector detecting all the signals for guiding the safe vehicle operation, and radar signals for determining vehicle speeds. The broadband frequency detector comprises: a horn antenna configured to receive signals having specific frequencies; a first amplifier configured to receive the signals having specific frequencies from the horn antenna; a mixer unit configured to receive signals from the first amplifier, wherein the signals are low noise amplified therein; and a second amplifier, arranged in parallel with the amplifier, for transferring signals to the mixer unit after low noise amplifying the signal received from the horn antenna, wherein the second amplifier includes a transistor and a first microwave circuit unit for matching the impedance of the horn antenna and the impedance of the transistor..
Djp Co., Ltd.


Apparatus and methods for tuning a voltage controlled oscillator


Apparatus and methods for tuning a voltage controlled oscillator (vco) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a vco clock signal using a vco coupled to a capacitor array, dividing the vco clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal m and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval..
Skyworks Solutions, Inc.


Method for suppression of spurs from a free running oscillator in frequency division duplex (fdd) and time division duplex (tdd) wireless systems


Embodiments of this disclosure include methods in which spurs generated by the drifting of an oscillation frequency of an oscillation signal provided by a free-running oscillator may be minimized and/or eliminated from an output signal of a phase locked loop (pll). Methods include minimizing the mixing gain between the oscillation signal and a power signal provided to the pll.
Broadcom Corporation


Systems and methods for use in authenticating an object


A system for use in authenticating an object is provided. The system includes a radio-frequency identification tag coupled to the object and an interrogation system.
The Boeing Company


Low spurious synthesizer circuit and method


An offset phase locked loop synthesizer comprising: an input; an output; a voltage controlled oscillator (vco), the vco output coupled to the synthesizer output; a phase frequency detector having a reference input, a feed-back input, and an output; a mixer having a first mixer input coupled to the synthesizer input and a second mixer input coupled to the vco output; a first divider for frequency dividing a signal by a first value and having an input coupled to the mixer output and an output coupled to the second input of the phase frequency detector; a second divider for frequency dividing a signal by a second value and having an input coupled to the synthesizer input and an output coupled to the reference input of the phase frequency detector; and a low pass filter coupled between the output of the phase frequency detector and the vco input.. .
Nanowave Technologies Inc.


Broadband frequency detector


Provided is a broadband frequency detector, more particularly, to a frequency detector detecting all the signals for guiding the safe vehicle operation, and radar signals for determining vehicle speeds. The broadband frequency detector comprises: a horn antenna configured to receive signals having specific frequencies; a first amplifier configured to receive the signals having specific frequencies from the horn antenna; a mixer unit configured to receive signals from the first amplifier, wherein the signals are low noise amplified therein; and a second amplifier, arranged in parallel with the amplifier, for transferring signals to the mixer unit after low noise amplifying the signal received from the horn antenna, wherein the second amplifier includes a transistor..
Djp Co., Ltd.,


Weighing system using a conveyor belt


Either the capacitor or the inductive coil can be a force-sensitive element. Measuring circuits external to the belt include an oscillator having a coil that inductively couples to the resonant circuit in the belt as it passes closely by.

Phase locked loop having dual bandwidth and operating the same


A phase locked loop having a dual bandwidth is disclosed. The phase locked loop divides a loop filter into a zero filter and a pole filter, disposes the zero filter in front of a phase-frequency detector (pfd), and performs high-pass filtering on a voltage-controlled oscillator (vco) noise with a maximum bandwidth and performs low-pass filtering on a charge pump noise (cp noise) with a minimum bandwidth to divide the vco noise and the cp noise..

Portable mri imaging and tissue analysis


The present invention discloses a portable magnetic resonance method and device for tissue analysis including a magnetic field generator, a radio frequency source, a radio frequency detector, a power source, and a processor configured for receiving radio frequency signals and for analyzing those signals to determine discriminatory tissue characteristics in a planar section of a region of interest within a patient's body, with the magnetic field generator positioned outside of the patient's body, and more preferably hand held in proximity to the patient's body. The processor is configured to direct the radio frequency source to produce a radio frequency field in varying planar sections of the region of interest at larmor frequencies such that spins resonant with the larmor frequency in the particular planar section of the region of interest are excited.

Referenceless clock and data recovery circuit


A circuit and method for referenceless cdr with improved efficiency and jitter tolerance by using an additional loop for frequency detection. Such an improved circuit includes a frequency detector for identifying whether an initial recovered clock signal is faster or slower than the actual bit rate of the received data stream.
Stmicroelectronics International N.v.


Integrated circuit capacitors for analog microcircuits


Dual gate fd-soi transistors are used as mosfet capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate fd-soi devices helps to reduce unstable oscillations and improve circuit performance.
Stmicroelectronics International N.v.


Broadband frequency detector


A frequency detector detecting all the signals for guiding the safe vehicle operation, and radar signals for determining vehicle speeds. The broadband frequency detector comprises: a horn antenna configured to receive signals having specific frequencies; a first amplifier configured to receive the signals having specific frequencies from the horn antenna; a mixer unit configured to receive signals from the first amplifier, wherein the signals are low noise amplified therein; and a second amplifier, arranged in parallel with the amplifier, for transferring signals to the mixer unit after low noise amplifying the signal received from the horn antenna..
Djp Co., Ltd.


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Power conversion device and power conversion method


A transformer steps down an input ac power, and supplies the ac power to a converter. The primary voltage of the transformer detected by a voltage detector is supplied to a converter controller and a frequency detector via a bpf.
Mitsubishi Electric Corporation


Don-doff detection using antenna detuning


A wearable device having corresponding computer-readable media comprises: an antenna; a radio-frequency transmitter configured to provide radio-frequency signals to the antenna; a radio-frequency detector having an input electrically coupled to the antenna; an analog-to-digital converter electrically coupled to an output of the radio-frequency detector; and a controller configured to determine whether the wearable device is being worn based on an output of the analog-to-digital converter.. .
Plantronics, Inc.


Broadband frequency detector


A broadband frequency detector detecting all the signals for guiding the safe vehicle operation, and radar signals for determining vehicle speeds comprises: a horn antenna configured to receive signals having specific frequencies; an amplifier configured to receive the signals having specific frequencies from the horn antenna; a mixer unit configured to receive signals from the amplifier, wherein the signals are low noise amplified therein; a coupler, arranged in parallel with the amplifier, for transferring the signals to the mixer unit by passing through the signals within a specific frequency range among the signals received from the horn antenna.. .
Djp Co., Ltd.


Digitally phase locked low dropout regulator


Described is an apparatus which comprises: a first oscillator to generate a first clock signal a second oscillator to generate a second clock signal; a phase frequency detector to detect phase difference between the first and second clock signals, and to generate a phase difference; and an output stage, coupled to a load, to generate a power supply for the load according to the phase difference.. .
Intel Corporation


Half-rate clock and data recovery circuit


A half-rate clock and data recovery (cdr) circuit includes a first and a second gated voltage-controlled oscillators (gvcos) and a first and a second frequency detectors. The first frequency detector generates a first output current according to a reference signal and a second divided clock, and the second frequency detector generates a second output current according to a first divided clock and the second divided clock.
Ncku Research And Development Foundation


Phase frequency detector


Described is an apparatus comprising: a first phase frequency detector (pfd) to determine a coarse phase difference between a first clock signal and a second clock signal, the first pfd to generate a first output indicating the coarse phase difference; and a second pfd, coupled to the first pfd, to determine a fine phase difference between the first clock signal and the second clock signal, the second pfd to generate a second output indicating the fine phase difference.. .

Charge pump calibration for dual-path phase-locked loop


Embodiments of the invention are generally directed to charge pump calibration for a dual-path phase-locked loop circuit. An embodiment of an apparatus includes a phase frequency detector; an integral path including a first charge pump; a proportional path including a second charge pump; and a calibration mechanism for the first charge pump and the second charge pump, the calibration mechanism including a phase detector to detect whether a reference clock signal or a feedback clock signal is leading or lagging in phase and to generate a signal indicating which clock signal is leading or lagging, a first memory element and a second memory element to store the signal from the phase detector, a first control logic to adjust current for the first charge pump based on the value stored in the first memory element, and a second control logic to adjust current for the second charge pump based on the value stored in the second memory element..
Silicon Image, Inc.


Multi-lane re-timer circuit and multi-lane reception system


A multi-lane re-timer circuit includes: a clock generation circuit to generate a base clock; and reception circuits to generate a reception clock and receive input data signals from lanes, wherein each of the reception circuits includes: a phase frequency detector to generate phase difference signal and frequency difference signal between the input data signal and the reception clock; a clock data regeneration controller to generate a control signal based on the phase difference signal; a phase rotator to generate the reception clock from the base clock; and a decision circuit to receive the input data signal, and wherein the clock generation circuit includes: an input selector to select a signal; a charge pump to generate a charge signal; a loop filter to remove a high frequency component from the charge signal to output a voltage control signal; and a voltage controlled oscillator to generate the reception clock.. .
Fujitsu Limited


Clock recovery using quantized phase error samples using jitter frequency-dependent quantization thresholds and loop gains


A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a phase-adjusted clock and an input data signal.
Lsi Corporation


Local oscillator frequency calibration


A frequency locked loop for generating a clock signal, comprising: a controllable oscillator configured to, in dependence on a control signal, generate an oscillator signal having an oscillator signal frequency; a frequency divider coupled to the controllable oscillator configured to reduce the oscillator signal frequency to form a divided oscillator signal frequency; and a frequency detector coupled to the frequency divider and configured to generate the control signal in dependence on a reference signal frequency; wherein the frequency divider comprises a first counter and a second counter, the first counter configured to be clocked by the oscillator signal and to produce a first counter output signal, and the second counter configured to be clocked by the first counter output signal.. .
Cambridge Silicon Radio Limited


Stacked cmos phase-locked loop


A phase-locked loop includes a first semiconductor layer and a second semiconductor layer spaced apart from the first semiconductor layer. The first semiconductor layer has formed thereon a phase frequency detector circuit having a reference frequency input, a feedback frequency input, an up output and a down output, a charge pump circuit having a first input coupled to the up output and a second input coupled to the down output, and an output, and a loop filter circuit coupled to the charge pump.
Taiwan Semiconductor Manufacturing Co., Ltd.


Non-invasive resonant frequency detection in corona ignition systems


A corona ignition system including a corona igniter, an energy supply, and a frequency detector is provided. The energy supply provides energy to the corona igniter during corona events which are spaced from one another by idle periods, during which no energy is provided to the corona igniter.
Federal-mogul Ignition Company


Systems and methods to monitor current in switching converters


Various embodiments of the invention increase current monitoring accuracy in switching converters. In particular, certain embodiments of the invention allow reduce noise associated with transients that are typically generated at transitions when power fets are turn on and off and allow to accurately sense inductor dc current of switching converters, thereby, increase current monitoring accuracy without requiring any blanking circuitry.
Maxim Integrated Products, Inc.


Semiconductor integrated circuit and testing the semiconductor integrated circuit


A semiconductor integrated circuit includes a memory having bit cells; and a frequency detector outputting a switching signal to switch a test mode from first to second test modes. Further, the memory includes an internal clock generator generating an internal clock in synchronization with the external clock; a writing part writing data into the bit cells based on the internal clock; a delayed clock generator generating a delayed clock by adding a designated delay to the internal clock; a first selector inputting the internal clock and the delayed clock, and, when the frequency of the high-speed clock is less than a designated frequency, selecting the delayed clock based on the switching signal; and a reading part reading the data of the bit cells based on the delayed clock..

Axle alignment sensor assembly for steering system of a machine


An axle alignment sensor assembly, which includes an enclosure, an oscillator, a frequency detector, an output switch driver, a ferrite component, and an electrostatic discharge (esd) protection component, is disclosed. The oscillator is positioned at the sensing end and is configured to generate a magnetic field.
Caterpillar Inc.


Dead-zone free charge pump phase-frequency detector


A charge-pump phase-frequency detector includes first and second flip-flops first and second delay circuits, a charge pump circuit and a reset gate. The flip-flops each have a respective data input connected to a fixed logic level, a reset input, a data output, and a clock input.
Keysight Technologies, Inc.


Jitter mitigating phase locked loop circuit


Systems and methods for efficient jitter mitigation or removal from a gapped signal. A phase mitigation module is employed to generate discrete correction values for modifying phase error signals detected between a gapped signal and a feedback signal of the pll.
Applied Micro Circuits Corporation


Pll frequency synthesizer with multi-curve vco implementing closed loop curve searching using charge pump current modulation


A phase-locked loop circuit using a multi-curve voltage-controlled oscillator (vco) having a set of operating curves, each operating curve corresponding to a different frequency range over a control voltage range. The phase-locked loop circuit includes a phase and frequency detector driving a charge pump and a digital control circuit configured to perform a closed loop curve search operation to select one of the operating curves in the multi-curve vco and to perform a curve tracking operation using the selected operating curve, the selected operating curve being used by the vco to generate an output signal with an output frequency being equal or close to a target frequency of the phase-locked loop.
Micrel, Inc.


Clock data recovery device and display device including the same


A clock data recovery device includes a clock recovery device for separating a recovery clock signal and a data signal from an input signal and generating a clock fail signal in response to noise of the input signal; a clock generator for receiving a control voltage to generate one or more delay clock signals, delaying the recovery clock signal to generate the delay clock signals in a first mode, delaying the generated delay clock signal to generate the delay clock signal in a second mode, and switching the first mode to the second mode in response to the clock fail signal; and a phase frequency detector for comparing at least one of the delay clock signals with the recovery clock signal to generate a voltage adjusting signal; and a control voltage generator for receiving the voltage adjusting signal to generate the control voltage.. .
Samsung Electronics Co., Ltd.


System and detecting a fundamental frequency of an electric power system


A system and method to detect the fundamental frequency of an electric input signal using a feedback control loop including a phase error detector, a loop controller, and a digitally controlled oscillator. The frequency detector may detect the fundamental frequency of an electric input signal and produce an output signal representing the fundamental frequency of the electric input signal.
Analog Devices, Inc.


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Connecting interface unit and memory storage device


A connecting interface unit and a memory storage device without a crystal oscillator are provided and include a frequency detector, a phase detector, an oscillator, a sampling circuit and a transmitter circuit. The frequency detector and the phase detector respectively detect frequency difference and phase difference between an input signal from a host system and a reference signal to generate a frequency signal and a phase signal.
Phison Electronics Corp.


Circuits and methods for pulse radio receivers


Circuits and methods comprising: a radio frequency amplifier that powers off in response to an enable signal; a demodulator that outputs an rz signal; an all-digital clock and data recovery circuit comprising: a phase detector that includes a tri-state phase frequency detector for use when in an acquisition mode and a hogge phase detector for use when in a communication mode, that receives the rz signal, and that outputs a phase detector output from the tri-state phase frequency detector when in the acquisition mode and from the hogge phase detector when in the communication mode, a loop filter that receives the phase detector output from the phase detector and produces a loop filter output that is the sum of a proportional path of the loop filter and an integral path of the loop filter, and a numerical controlled oscillator that receives the loop filter output and produces the enable signal.. .

Clock data recovery circuit, timing controller including the same, and driving the timing controller


Provided is a clock data recovery circuit including a phase-frequency detector configured to detect a frequency and phase of a reference clock signal and control a frequency and phase of an internal clock signal based on the detected frequency, a frequency detector configured to detect a frequency of a data signal and, based on the detected frequency of the data signal, adjust the frequency of the internal clock signal; and a phase detector configured to detect a phase of the data signal based on the detected frequency of the data signal and adjust the phase of the internal clock signal. Accordingly, a timing controller that includes the clock data recovery circuit is capable of establishing data communication at high speeds when the system is powered on/off to reduce power consumption.

Apparatus and real time harmonic spectral analyzer


In one embodiment, a measuring device may comprise two oscillators. The first oscillator may generate a local reference signal in a frequency detector to detect a fundamental frequency of the ac.
Analog Devices, Inc.


Phase detector, phase-frequency detector, and digital phase locked loop


A phase detector includes a phase comparing circuit configured to detect and output a phase difference between a first clock signal and a second clock signal, a latch circuit configured to latch an output signal of the phase comparing circuit and output a phase detection signal, and an initial voltage control circuit configured to control an initial voltage of an input terminal of the latch circuit according to a control signal.. .
Industry-university Cooperation Foundation Hanyang University


Fast filter calibration apparatus


A method comprises generating a calibration signal by a clock generator, feeding the calibration signal to a first filter through a first switch unit, comparing an output of the first filter with the calibration signal through a frequency detector and a phase comparator and generating a first updated bandwidth code to adjust a bandwidth frequency of the first filter.. .
Taiwan Semiconductor Manufacturing Company, Ltd.


Conductive thin film detector


The invention is directed to products used to detect and methods for detecting conductive materials in the presence of non-conductive materials, including non-conductive materials having dielectric properties. Specifically, the product is a conductive thin film detector, which is, preferably, a hand-held device designed to detect the presence of metal in, on, or under an object.
United States Of America As Represented By The Federal Bureau Of Investigation, Dept. Of Justic


Digital pll with hybrid phase/frequency detector and digital noise cancellation


Digital phase-locked loop (pll) with dynamic hybrid (mixed analog/digital signal) delta-sigma (ΔΣ) phase/frequency detector (ΔΣ pfd). A hybrid 2nd-order ΔΣ pfd may be implemented based on a continuous-time 1st-order ΔΣ analog-to-digital converter (adc) enhanced to 2nd-order via closed loop frequency detection.

Digital phase locked loop with hybrid delta-sigma phase/frequency detector


A pll includes independent frequency-locking and phase-locking operational modes. In addition, the pll includes a hybrid (e.g., mixed-analog/digital signal) 2nd-order delta-sigma (ds) phase/frequency detector.

Pll frequency synthesizer with multi-curve vco implementing closed loop curve searching using charge pump current modulation


A phase-locked loop circuit using a multi-curve voltage-controlled oscillator (vco) having a set of operating curves, each operating curve corresponding to a different frequency range over a control voltage range. The phase-locked loop circuit includes a phase and frequency detector driving a charge pump and a digital control circuit configured to generate a curve select signal using a closed loop curve search operation to select one of the operating curves in the multi-curve vco, the selected operating curve being used by the vco to generate an output signal with an output frequency being equal or close to a target frequency of the phase-locked loop.

Geographic locating remote endpoint monitor device, system, and methodology thereof


A phase-locked loop frequency synthesizer includes an l-state pulse width modulator configured to receive a reference frequency signal and at least one entry from a frequency table, and to output at least one n/n+1 modulus signals corresponding to the at least one entry from the frequency table. The synthesizer includes a divide by n/n+1 controllable modulus divider configured to receive the at least one n/n+1 modulus signals and to divide the output frequency signal by the at least one n/n+1 modulus signals to generate a second reference frequency signal.

Current detecting device


A current detecting device includes an exciting coil (3) wound around a magnetic core (2) enclosing a conductor through which flows a measurement current, and an oscillator circuit (4) that generates a square wave voltage which is supplied to the exciting coil (3). Furthermore, the current detecting device includes a duty detector circuit (5) that detects the measurement current based on variation in the duty ratio of the square wave voltage output from the oscillator circuit (4), a frequency detector circuit (7) that detects an overcurrent of the measurement current based on the frequency of the square wave voltage output from the oscillator circuit (4), and an oscillation amplitude detector circuit (6) that detects an overcurrent of the measurement current based on the magnitude of the square wave voltage output from the oscillator circuit (4)..

Method and smoothing jitter generated by byte stuffing


Systems and methods for smoothing jitter generated by byte stuffing. A frequency synthesizer comprises a smoothing logic coupled with a pll.

Phase-locked loop system and operation


A phase-locked loop system has a controlled oscillator that provides an output clock signal based on a oscillator control signal, a feedback path configured to provide a feedback signal based on the output clock signal, a phase detector configured to provide a phase dependent signal based on the feedback signal and a reference clock signal, a phase evaluation block configured to provide the oscillator control signal based on the phase dependent signal, a frequency detector that determines whether the frequency ratio between the output clock signal and the reference clock signal has a desired value, and a control logic. The control logic is configured to, during a start-up period, disable the phase evaluation block upon determination of the desired value of the frequency ratio; detect, after disabling the phase evaluation block, a subsequent clock edge of the reference clock signal; and enable, in response to the detection of the subsequent clock edge, the phase evaluation block..

Energy harvesting cochlear implant


The invention is related to a totally implantable cochlear implant having a transducer which is a piezoelectric vibration energy harvester to be mounted on the ossicular chain or the tympanic membrane to detect the frequency of oscillations and generate the required voltage to stimulate the relevant auditory nerves. The invention enables patients' continuous access to sound, since it eliminates the outside components of conventional cochlear implants.

Method and system for detecting an airborne trigger


An apparatus includes a cantilevered element including a coating material having an affinity for at least one compound. The apparatus further includes a first capacitive plate and a second capacitive plate that are each spaced from and capacitively coupled to the cantilevered element.

Magnetic induction feedback mechanism for a heating system and the method using the same


A heating system for heating a magnetic inducible container is disclosed, wherein the heating system includes a frequency detector for detecting the frequency of the current through an inductor coil and a control unit coupled to the frequency detector to adjust the heat generated by the heating system according to the variation of the frequencies detected by the frequency detector.. .

Microelectromechanical device having an oscillating mass and a forcing stage, and controlling a microelectromechanical device


A microelectromechanical device includes: a body; a movable mass, elastically coupled to the body and oscillatable with respect to the body according to a degree of freedom; a frequency detector, configured to detect a current oscillation frequency of the movable mass; and a forcing stage, capacitively coupled to the movable mass and configured to provide energy to the movable mass through forcing signals having a forcing frequency equal to the current oscillation frequency detected by the frequency detector, at least in a first transient operating condition.. .

Method and system for detecting flicker


An image processing system includes a plurality of active pixels and a plurality of flicker pixels. The active pixels output active pixel signals at a first readout frequency, and the flicker pixels output flicker pixel signals at a second readout frequency greater than the first readout frequency.

Method and closed loop control of supply and/or comparator common mode voltage in a successive approximation register analog to digital converter


A method and apparatus for controlling supply voltage for a successive approximation register analog to digital converter and comparator common mode voltage. The method comprises: measuring a successive approximation register conversion time; comparing the successive approximation register conversion time with a desired conversion time; and if necessary, performing a closed loop adjustment of at least one of the supply and/or comparator common mode voltage.

Phase locked loop frequency synthesizer with reduced jitter


A phase locked loop frequency synthesizer has a controlled oscillator for generating an output signal at a desired frequency, a phase/frequency detector module for comparing a feedback signal derived from the controlled oscillator with a reference signal to generate an error signal, a loop filter for processing said at least one error signal from said phase/frequency detector module to generate a combined control signal for the controlled oscillator. The gain of the phase/frequency detector module can be adjusted, preferably by varying the pulse width and pulse cycle, to maintain the overall gain of the phase locked loop within a given range and thereby maximize signal to noise ratio..

Line frequency detector


A line frequency detector receives an input signal representing a power source and detects a line frequency of the power source based on the input signal. The line frequency detector includes a first band pass filter having a pass band centered at an upper end of an expected frequency range of the power source and a second band pass filter having a pass band centered at a lower end of the expected frequency range.

Adaptive real-time control of de-emphasis level in a usb 3.0 signal conditioner based on incoming signal frequency range


An apparatus comprises a differential equalizer having: a) a first differential input, b) a second differential input, c) a first differential output, and d) a second differential output; a frequency detector coupled to the first and second differential inputs; an amplifier coupled to a first differential output and a second differential output of the differential equalizer; and a logical combiner having a first input coupled to an output of the frequency detector and an output coupled to a control input of the amplifier, wherein the logical combiner can mask at least one received de-emphasis parameter.. .

Apparatus for measuring moisture content amount and/or coating amount of coating layer of sheet-shaped base material


A first isolator, which is disposed in a direction where a signal is transmitted only to an antenna direction, is connected directly to a connector portion of an antenna on an oscillation side without a cable, and a second isolator 15b, which is disposed in a direction where a signal is transmitted only to a receiver direction, is connected directly to the connector portion of the antenna on a receiver side without a cable. A data processing apparatus includes a peak level detector, a resonant frequency detector, and an arithmetic part for calculating a moisture content amount and a coating amount of a coating layer of a sample based on the detection values detected by these detectors..

Phase frequency detector and charge pump for phase lock loop fast-locking


The present invention provides for a solution to reduce locking time with satisfactory performance without the need for significant footprint area for the phase lock loop (pll) circuits by boosting phase frequency detector (pfd) and charge pump (cp) gains through various circuitry configurations that employ one or more flip-flops, delay elements and advanced circuitry techniques.. .

Integrated circuit with calibrated pulling effect correction


A frequency-control circuit includes a phase frequency detector configured to receive a reference frequency signal and generate an output detection signal. The phase frequency detector can be configured to detect a difference in phase and frequency between the reference frequency signal and a feedback of the output frequency signal.

Integrated circuit with calibrated pulling effect correction


A frequency-control circuit includes a phase frequency detector configured to receive a reference frequency signal and generate an output detection signal. The phase frequency detector can be configured to detect a difference in phase and frequency between the reference frequency signal and a feedback of the output frequency signal.

Phase locked loop circuit


A phase locked loop circuit is provided which includes a bang-bang phase frequency detector configured to receive a reference signal and a feedback signal, detect a phase difference between the reference signal and the feedback signal, output a detection signal on the based on a result of the detection; an analog-digital mixed filter configured to receive the detection signal and output a control signal on the basis of the received detection signal; a voltage controlled oscillator configured to output an output signal in response to the control signal; and a divider configured to divide the output signal by n to output as the feedback signal. The detection signal is a digital signal, and the control signal is an analog signal..

Phase frequency detector circuit


A phase-frequency detector (pfd) circuit is disclosed. The pfd circuit includes a pfd portion adapted to detect frequency and phase difference of two input signals and to generate control signals according to the detected frequency and phase difference and a delay and reset portion adapted to delay the generated control signals, to generate reset signals for resetting the pfd portion based on a combination of the control signals and the delayed control signals, and to provide the generated reset signals to the pfd portion..

Fractional-n frequency synthesizer with low quantization noise


A fractional-n frequency synthesizer with low quantization noise includes a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator a divider and a delta-sigma modulator. The delta-sigma modulator computes “n” to the loop filter in the output current of the charge pump.

Sub-gate delay adjustment using digital locked-loop


A delay locked loop (dll) includes a delay line that delays a clock signal to generate a delayed clock signal, a phase frequency detector (pfd) for detecting a phase and/or frequency difference between the clock signal and the delayed clock signal, and a charge pump having an adjustable bias current for converting the phase and/or frequency difference taking into account a bias current adjustment into a control voltage, in which the control voltage controls an amount of delay in the delayed clock signal.. .

Monitoring a condition of a solid state charge device in electrostatic printing


An apparatus to monitor a condition of a solid state charge device (sscd)) useful in electrostatic printing includes a power supply and a frequency detector. The power supply provides current to the sscd, and includes a resonant controller.

Phase-locked loop


The pll includes a voltage-controlled oscillator (vco), a frequency down conversion circuit, a phase-frequency detector (pfd), and an adjusting circuit. The vco is configured to generate an output dock signal.

Phase frequency detector circuit


A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal.

Sub-gate delay adjustment using digital locked-loop


A delay locked loop (dll) includes a delay line that delays a clock signal to generate a delayed clock signal, a phase frequency detector (pfd) for detecting a phase and/or frequency difference between the clock signal and the delayed clock signal, and a charge pump having an adjustable bias current for converting the phase and/or frequency difference taking into account a bias current adjustment into a control voltage, in which the control voltage controls an amount of delay in the delayed clock signal.. .

Apparatus and methods for tuning a voltage controlled oscillator


Apparatus and methods for tuning a voltage controlled oscillator (vco) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a vco clock signal using a vco coupled to a capacitor array, dividing the vco clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal m and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval..

Phase locked loop


An optical phase-locked loop (opll) comprising a phase-frequency detector; first and second lasers; a local oscillator; a detector and a low pass filter connected in a circuit comprising a feedback path. The opll can also include a pre-scaler, a second local oscillator and a mixer..

X-ray diagnostic apparatus and storage medium storing x-ray diagnostic program


An x-ray diagnostic apparatus includes a peak frequency detector detecting a peak frequency of a first harmonic in a moiré pattern of a grid in an image; a harmonic remover removing the first harmonic and a second harmonic in the moiré pattern from the image in accordance with the peak frequency of the first harmonic to obtain a first and second harmonic removed image; a harmonic extracting-filter generating unit calculating a peak frequency of a third harmonic in the moiré pattern in accordance with the peak frequency of the first harmonic to generate a harmonic extracting filter to extract the third harmonic; a harmonic extracting unit extracting the third harmonic from the first and second harmonic removed image based on the harmonic extracting filter; and a harmonic subtracting unit subtracting the extracted third harmonic from the first and second harmonic removed image to obtain a third harmonic removed image.. .



Frequency Detector topics:
  • Frequency Detector
  • Loop Filter
  • Reference Voltage
  • Frequency Divider
  • Generates A Frequency
  • Feedback Signal
  • State Machine
  • Peripheral Devices
  • Synthesizer
  • Calibration
  • Frequency Band
  • Wireless Communication Device
  • Low Frequency
  • Synchronization
  • Phase Shift


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