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Flash Memory patents



      
           
This page is updated frequently with new Flash Memory-related patent applications. Subscribe to the Flash Memory RSS feed to automatically get the update: related Flash RSS feeds. RSS updates for this page: Flash Memory RSS RSS


Flash memory-hosted local and remote out-of-service platform manageability

Distributed procedure execution and file systems on a memory interface

Page allocation for flash memories

Date/App# patent app List of recent Flash Memory-related patents
07/17/14
20140201598
 Solid state drive and data retention method thereof patent thumbnailSolid state drive and data retention method thereof
A data retention method is provided. After the solid state drive is powered on, a current date information is received from a host.
07/17/14
20140201568
 Flash memory-hosted local and remote out-of-service platform manageability patent thumbnailFlash memory-hosted local and remote out-of-service platform manageability
A method, apparatus, and system are disclosed. In one embodiment, the method determines whether one or more manageability conditions are present in a computer system, and then invokes an out-of-service manageability remediation environment stored within a portion of a flash device in the computer system when one or more manageability conditions are present..
07/17/14
20140201431
 Distributed procedure execution and file systems on a memory interface patent thumbnailDistributed procedure execution and file systems on a memory interface
Nonvolatile memory (e.g., flash memory, solid-state disk) is included on memory modules that are on a dram memory channel. Nonvolatile memory residing on a dram memory channel may be integrated into the existing file system structures of operating systems.
07/17/14
20140201426
 Page allocation for flash memories patent thumbnailPage allocation for flash memories
Technologies are described herein for allocating pages in a flash memory. Some example technologies may receive multiple data elements and a write request to write the multiple data elements to the flash memory.
07/17/14
20140198578
 Method of operating a split gate flash memory cell with coupling gate patent thumbnailMethod of operating a split gate flash memory cell with coupling gate
A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the first region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate.
07/17/14
20140198569
 Flash memory, flash memory system and operating method of the same patent thumbnailFlash memory, flash memory system and operating method of the same
A flash memory, a flash memory system, and an operating method thereof. The method of operating a flash memory includes counting the number of memory cells having threshold voltages included in a first adjacent threshold voltage range (defined by a first reference read voltage for distinguishing between initially separated adjacently located threshold voltage distributions and a first search read voltage having a first voltage difference from the first reference read voltage), and a second adjacent threshold voltage range (defined by the first reference read voltage and a second search read voltage having a second voltage difference from the first reference read voltage), and setting a first optimal read voltage based on the difference between the first and second counted numbers of the memory cells..
07/10/14
20140195722
 Storage system which realizes asynchronous remote copy using cache memory composed of flash memory, and control method thereof patent thumbnailStorage system which realizes asynchronous remote copy using cache memory composed of flash memory, and control method thereof
The first storage apparatus provides a primary logical volume, and the second storage apparatus has a secondary logical volume. When the first storage apparatus receives a write command to the primary logical volume, a package processor in a flash package allocates first physical area in the flash memory chip to first cache logical area for write data and stores the write data to the allocated first physical area.
07/10/14
20140192599
 Test partitioning for a non-volatile memory patent thumbnailTest partitioning for a non-volatile memory
Systems and methods are provided for testing a non-volatile memory, such as a flash memory. The non-volatile memory may be virtually partitioned into a test region and a general purpose region.
07/10/14
20140192594
 P-channel 3d memory array patent thumbnailP-channel 3d memory array
A p-channel flash memory device including a 3d nand array has excellent performance characteristics. Techniques for operating 3d, p-channel nand arrays include selective programming, selective (bit) erase, and block erase.
07/10/14
20140192581
 Programmable and flexible reference cell selection method for memory devices patent thumbnailProgrammable and flexible reference cell selection method for memory devices
Systems, methods, and computer program products for programmable reference cell selection for flash memory are disclosed. An exemplary system includes an array of interconnected cells and a flexible decoder.
07/03/14
20140189222
Method for performing data shaping, and associated memory device and controller thereof
A method for performing data shaping is applied to a controller of a flash memory, where the flash memory includes a plurality of blocks. The method includes: performing a program optimization operation according to original data and a plurality of shaping codes, in order to generate trace back information corresponding to a trellis diagram and utilize the trace back information as side information; and dynamically selecting at least one shaping code from the shaping codes according to the side information to perform data shaping on the original data..
07/03/14
20140189219
Solid state storage element and method
A method and system for storing and retrieving data using flash memory devices. One example system includes an apparatus within a flash memory configuration.
07/03/14
20140189210
Memory system having an unequal number of memory die
A flash memory system having unequal number of memory die and method for operation is disclosed. The memory includes a plurality of flash memory die distributed unevenly among different control lines, such that there are an unequal number of die between control lines.
07/03/14
20140189209
Multi-layer memory system having multiple partitions in a layer
A multi-layer memory and method for operation is disclosed. The memory includes multiple layers, where each layer includes flash memory cells having a greater bit per cell capacity than then prior layer and each layer may include a plurality of partitions having blocks exclusively associated with a particular data type.
07/03/14
20140189208
Method and system for program scheduling in a multi-layer memory
A multi-layer memory and method for operation is disclosed. The memory includes an interface, at least one flash memory die having a plurality of layers and a controller.
07/03/14
20140189207
Method and system for managing background operations in a multi-layer memory
A multi-layer memory and method for performing background maintenance operations are disclosed. The memory includes a plurality of flash memory die having multiple layers, where each layer is made up of flash memory cells having a greater bit per cell storage capacity than then prior layer and each layer may have a plurality of partitions for different data types.
07/03/14
20140189206
Method and system for managing block reclaim operations in a multi-layer memory
A multi-later memory and method for operation is disclosed. The memory includes at least one flash memory die having multiple layers and a controller configured to execute block reclaim operations in a layer of the flash memory die until a net gain of at least one additional free block has been made in the layer.
07/03/14
20140189201
Flash memory interface using split bus configuration
A system having a split bus flash memory and a method for operating the split bus flash memory is disclosed. The system may include a controller, a non-volatile memory (including first and second non-volatile memory chips) and the system bus.
07/03/14
20140189200
Flash memory using virtual physical addresses
A system and method for using virtual physical addresses in a non-volatile memory device are disclosed. The physical layout of the non-volatile memory device may have physical die that are not a power-of-2 in number.
07/03/14
20140189197
Sharing serial peripheral interface flash memory in a multi-node server system on chip platform environment
Methods and apparatus related to sharing serial peripheral interface (spi) flash memory in a multi-node server soc (system on chip) platform environment are described. In one embodiment, multi-port non-volatile memory is shared by a plurality of system on chip (soc) devices.
07/03/14
20140185378
Multi-bit flash memory device and memory cell array
A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2″ pages of data.
07/03/14
20140185376
Method and system for asynchronous die operations in a non-volatile memory
A mass storage memory system and method of operation is disclosed. The memory includes an interface adapted to receive data from a host, a plurality of flash memory die and a controller, where the controller is configured to receive a first command and read or write data synchronously across the plurality of die based on a first command, and to receive a second command and read or write data asynchronously and independently in each die based on a second command.
06/26/14
20140181532
Encrypted flash-based data storage system with confidentiality mode
Raw or unencrypted data is encrypted using a standard encryption algorithm and stored in a flash memory array. The raw or unencrypted data may be pre-processed before it is encrypted.
06/26/14
20140181374
Speculative copying of data from main buffer cache to solid-state secondary cache of a storage server
A network storage server includes a main buffer cache to buffer writes requested by clients before committing them to primary persistent storage. The server further uses a secondary cache, implemented as low-cost, solid-state memory, such as flash memory, to store data evicted from the main buffer cache or data read from the primary persistent storage.
06/26/14
20140177341
Semiconductor device
In this flash memory, after first and second nodes are precharged to a power supply voltage, a sense amplifier is activated, and signals appearing at the first and second nodes are held in a register. With output signals of the register, a transistor is rendered conductive, so that a constant current source for offset compensation is connected to the first or second node.
06/26/14
20140177334
Circuit for sensing mlc flash memory
A circuit for sensing a multi-level cell (mlc) flash memory is disclosed. The circuit comprises a plurality of first decoding units, a second decoding unit and a data latch.
06/26/14
20140177333
Row decoding circuit and memory
A row decoding circuit and a memory are provided. The row decoding circuit is adapted for providing a word line operation voltage and a control-gate line operation voltage to a dual-bit split gate flash memory array, and includes a dummy row decoding unit, at least one row decoding unit and a driving voltage generating circuit.
06/26/14
20140175534
Semiconductor device manufacturing method
In a process of dividing gates of multi-layered films in fabricating a nand flash memory having a three-dimensional structure, a pattern is prevented from deforming and falling. A ratio of a length l to a height h of control gate groups configuring a memory cell of the flash memory is set to be less than 1.65 which is a range in which buckling does not occur.
06/19/14
20140173380
Error recovery for flash memory
An indication of a page type which failed error correction decoding is received. A threshold to adjust is selected from a plurality of thresholds based at least in part on the page type.
06/19/14
20140173294
Techniques for emulating an eeprom device
Disclosed are various embodiments of an emulation device for generating a cryptographic hash value associated with program data stored in a memory of a computing device. Validation data is generated based upon the cryptographic hash value and a flush counter of the computing device.
06/19/14
20140173191
Semiconductor memory system having a snapshot function
In a semiconductor memory computer equipped with a flash memory, use of backed-up data is enabled. The semiconductor memory computer includes an address conversion table for detecting physical addresses of at least two pages storing data by designating a logical address from one of logical addresses to be designated by a reading request.
06/19/14
20140169104
Nonvolatile flash memory structures including fullerene molecules and methods for manufacturing the same
Embodiments of tunneling barriers and methods for same can embed molecules exhibiting a monodispersion characteristic into a dielectric layer (e.g., between first and second layers forming a dielectric layer). In one embodiment, by embedding c60 molecules inbetween first and second insulating layers forming a dielectric layer, a field sensitive tunneling barrier can be implemented.
06/19/14
20140169101
Method compensation operating voltage, flash memory device, and data storage device
Disclosed is a method generating a compensated operating voltage, such as a read voltage, in a non-volatile memory device, and a related non-volatile memory device. The operating voltage is compensated in response to one or more memory cell conditions such as temperature variation, programmed data state or physical location of a selected memory cell, page information for selected memory cell, or the location of a selected word line..
06/19/14
20140169099
Memory array
A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process..
06/19/14
20140167977
System on a module for smart grid nodes
A system on a module and techniques for use and operation in multiple different smart grid devices and/or nodes are described herein. One example of a system on a module includes a processor, a flash memory device in communication with the processor, and a ram memory device in communication with the processor.
06/19/14
20140167141
Charge trapping split gate embedded flash memory and associated methods
Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming an dielectric layer at a first region and at a second region of a semiconductor substrate.
06/19/14
20140167055
Method of processing a silicon wafer and a silicon integrated circuit
Methods and systems for processing a silicon wafer are disclosed. A method includes providing a flash memory region in the silicon wafer and providing a bipolar transistor with a polysilicon external base in the silicon wafer.
06/12/14
20140164868
Flash memory read error recovery with soft-decision decode
An apparatus having a circuit and one or more processor is disclosed. The circuit is configured to receive a codeword from a memory.
06/12/14
20140164845
Host computer and method for testing sas expanders
In a method for testing serial attached small computer system interface (sas) expanders using a host computer, the host computer connects to a master sas expander through a first serial port, and connects to slave sas expanders through a second serial port. The host computer sends a test command to the master sas expander to test the master sas expander, and stores the test result of the master sas expander into a flash memory of the master sas expander.
06/12/14
20140164822
Host computer and method for managing sas expanders of sas expander storage system
In a method for managing serial attached small computer system interface (sas) expanders using a host computer, the host computer connects to an sas expander storage system through a redundant array of independent disks (raid) card. The sas expander storage system includes a first switch device, a first sas expander, a second sas expander, a second switch, a flash memory, and hard disk drives.
06/12/14
20140164678
Intelligent detection device of solid state hard disk combining a plurality of nand flash memory cards and detecting method for the same
An intelligent detection device of solid state hard disks combining a plurality of nand flash memory card, and detecting method for the same. Wherein, a central processing unit (cpu) controls a control unit, and is connected electrically to a plurality of flash card insertion slots, for a plurality of nand flash memory card to be inserted in.
06/12/14
20140164677
Using a logical to physical map for direct user space communication with a data storage device
A data storage device includes multiple flash memory devices, where each of the flash memory devices is arranged into multiple blocks having multiple pages for storing data. The data storage device includes a memory controller operationally coupled with the flash memory devices.
06/12/14
20140164676
Using a virtual to physical map for direct user space communication with a data storage device
A data storage device includes multiple flash memory devices, where each of the flash memory devices are arranged into multiple blocks having multiple pages for storing data. The data storage device includes a memory controller that is operationally coupled with the flash memory devices.


Popular terms: [SEARCH]

Flash Memory topics: Flash Memory, Memory Cell, Memory Cells, Memory Device, Touch Screen, Nand Flash, Data Storage, Random Access, Volatile Memory, Error Correction, Electronic Device, Storage Device, Circuit Board, Integrated Circuit, Interleaving

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This listing is a sample listing of patent applications related to Flash Memory for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Flash Memory with additional patents listed. Browse our RSS directory or Search for other possible listings.
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