|| List of recent Flash Memory-related patents
|Statistical adaptive error correction for a flash memory|
A method for implementing adaptive error correction in a memory, comprising the steps of (a) decoding a page of data read from a memory, (b) selecting one of a plurality of histograms based on a measured code word error rate of the decoded page and (c) applying an error correction code rate based on the selected histogram. The error correction code rate allows the memory to use a minimum number of error correction bits to provide reliable operation of the memory..
|Method and apparatus for power loss recovery in a flash memory-based ssd|
The present invention relates to a storage device that uses a flash memory that performs power loss recovery, and to a method of power loss recovery by using the storage device using the flash memory. The storage device stores change information on metadata in physical pages in which one or more logical pages are compressed and stored.
|Scheduling of reactive i/o operations in a storage environment|
A system and method for effectively scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network.
|Selectively programming data in multi-level cell memory|
Devices, systems, methods, and other embodiments associated with accessing memory are described. In one embodiment, a method detects that a power quality associated with a volatile memory in a computing device meets a threshold value and in response thereto, reprogramming data from the volatile memory to a flash memory comprising multi-level cells.
|Operating system based dram and flash management|
A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more flash memory devices that are employed for random access memory applications.
|Remote plasma radical treatment of silicon oxide|
Embodiments described herein generally relate to methods for manufacturing flash memory devices. In one embodiment, the method includes generating a plasma comprising nitrogen-containing radicals in a remote plasma applicator, flowing the plasma comprising nitrogen-containing radicals into a processing region of the processing chamber where a semiconductor device is disposed, wherein the semiconductor device has a substrate comprising an oxide layer formed thereon, exposing an exposed surface of the oxide layer to the nitrogen-containing radicals, and incorporating nitrogen in the exposed surface of the oxide layer of the substrate..
|Method of programming flash memory|
A method of programming a nand flash memory cell string. The method includes a pre-boost stage configured to elevate channel voltage of a selected memory cell, and a boost stage is introduced after the pre-boost stage.
|Memory system performing multi-step erase operation based on stored metadata|
A memory system, comprising a flash memory comprising multiple memory blocks, and a controller configured to erase each of the memory blocks using multiple steps. The controller stores, for each of the memory blocks, metadata indicating which of the multiple steps have been completed, and erases each of the memory blocks based on the stored metadata..
|Fast-reading nand flash memory|
In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line from the read voltage to a discrimination voltage.. .
|Flash memory cells having trenched storage elements|
An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench.
|Secure replay protected storage|
Embodiments of the invention enable secure standard storage flash memory devices such as spi flash memory devices to achieve replay protection for securely stored data. Embodiments of the invention utilize flash memory controllers, flash memory devices, unique device keys and hmac key logic to create secure execution environments for various components..
|Method and device for storing data in a flash memory using address mapping for supporting various block sizes|
The present invention relates to a method and device for storing data in a flash memory using address mapping for supporting various block sizes. A storage device determines the size of a block that a host system uses on the basis of the size of data that the host system requests and uses the determined block size as a mapping unit.
|Memory method and apparatus with button release|
A flash memory device apparatus and method is provided such that data or programming information is uploaded or downloaded between the flash memory device and a host, in response to a single-press of a button associated with the flash memory device. The system can facilitate a number of operations including saving an active window application or associated data, transferring media files to or from media players, providing device-specific and/or data-specific transfer of applications or data and/or providing protection of transferred data or applications..
|Flash multiple-pass write with accurate first-pass write|
An indication to store a data value in flash memory is received. An accurate coarse write is performed on the flash memory, including by: storing a first voltage level in the flash memory and setting a configuration setting of the flash memory to a first setting.
|High density vertical structure nitride flash memory|
A charge trap type of memory having a memory channel with vertical and possibly horizontal components is described. The invention includes a new operation method of simultaneous hole and electron injection operation for high speed and high reliability non-volatile memories, as well as high-density non-volatile memories.
|Method and apparatus for leakage suppression in flash memory in response to external commands|
Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells.
|Charge-trap type flash memory device having low-high-low energy band structure as trapping layer|
A charge-trap type flash memory device having a low-high-low energy band as a trapping layer embeds al2o3 between si3n4 and hfo2 as a ct layer. Most injected charged can be trapped at an interface of si3n4/al2o3.
|High-speed memory system|
The disclosed embodiments relate to a flash-based memory module having high-speed serial communication. The flash-based memory module comprises, among other things, a plurality of i/o modules, each configured to communicate with an external device over one or more external communication links, a plurality of flash-based memory cards, each comprising a plurality of flash memory devices, and a plurality of crossbar switching elements, each being connected to a respective one of the flash-based memory cards and configured to allow each one of the i/o modules to communicate with the respective one of the flash-based memory cards.
|Memory buffer with one or more auxiliary interfaces|
The present memory system includes a memory buffer having an interface arranged to buffer data and/or command bytes being written to or read from the ram chips residing on a dimm by a host controller. The memory buffer further includes at least one additional interface arranged to buffer data and/or command bytes between the host controller or ram chips and one or more external devices coupled to the at least one additional interface.
|Cooperative flash memory control|
This disclosure provides for host-controller cooperation in managing nand flash memory. The controller maintains information for each erase unit which tracks memory usage.
|Providing subsciber identity module function|
A host processing apparatus (100) and a user removable memory (40) are disclosed. The host processing apparatus (100) and the user removable memory (40) are, in use, connected to one another by respective connectors.
|Flash memory and associated programming method|
A flash memory includes a program voltage generator, plural memory units, a current limiter, and a multi-bit program control unit. The program voltage generator is used for providing a constant program voltage during a detecting cycle and providing a dynamically-adjustable program voltage during a program cycle.
|Methods of manufacturing nand flash memory devices|
A nand flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction. .
|Techniques for surfacing host-side flash storage capacity to virtual machines|
Techniques for surfacing host-side flash storage capacity to a plurality of vms running on a host system are provided. In one embodiment, the host system creates, for each vm in the plurality of vms, a flash storage space allocation in a flash storage device that is locally attached to the host system.
|Microcontroller for pollution control system for an internal combustion engine|
A pollution control system for an internal combustion engine includes a microcontroller and a power supply, a plurality of sensors configured to measure operating parameters of the engine, and a pcv valve responsive to a control signal from the microcontroller and configured to regulate a flow rate of blow-by gasses in the engine. The microcontroller includes programmable flash memory connected to a control processor, a power supply input, a sensor input configured to receive data from an engine sensor, and a signal output configured to transmit a signal from the control processor so as to control operation of a pcv valve regulating a flow rate of blow-by gasses in the engine..
|Dynamic detection method for latent slow-to-erase bit for high performance and high reliability flash memory|
A method and apparatus for detecting a latent slow bit (e.g., a latent slow-to-erase bit) in a non-volatile memory (nvm) is disclosed. A maximum number of soft program pulses among addresses during an erase cycle is counted.
|Flash memory module for realizing high reliability|
A flash memory module may include a plurality of flash memory chips. The memory chips may include one or more blocks.
A memory system includes a flash memory including a block having first sub-blocks and second sub-blocks different from each other, the second sub-blocks including free pages only; and a controller configured to erase the flash memory in units of the sub-blocks, and in a garbage collection operation, the controller is configured to copy data of a valid page of the first sub-blocks to at least one of the second sub-blocks.. .
|Endoscope apparatus and deterioration detection method of polarization element of endoscope|
An endoscope apparatus includes a flash memory that stores a reference value of a color balance adjustment value of an endoscopic image of an endoscope that picks up an object through a polarizer. The endoscope calculates, from the reference value and the color balance adjustment value of the endoscope after elapse of a predetermined time period, an amount of change in the color balance adjustment value; judges whether or not the calculated amount of change is equal to or larger than a predetermined threshold; and, when the amount of change is equal to or larger than the predetermined threshold, outputs a predetermined output..
|Solid state drive|
Provided is a solid state drive suitable for an increase in capacity. The solid state drive includes a flash memory, and a capacitor electrically connected to the flash memory.
|Solid state drive and data retention method thereof|
A data retention method is provided. After the solid state drive is powered on, a current date information is received from a host.
|Flash memory-hosted local and remote out-of-service platform manageability|
A method, apparatus, and system are disclosed. In one embodiment, the method determines whether one or more manageability conditions are present in a computer system, and then invokes an out-of-service manageability remediation environment stored within a portion of a flash device in the computer system when one or more manageability conditions are present..
|Distributed procedure execution and file systems on a memory interface|
Nonvolatile memory (e.g., flash memory, solid-state disk) is included on memory modules that are on a dram memory channel. Nonvolatile memory residing on a dram memory channel may be integrated into the existing file system structures of operating systems.
|Page allocation for flash memories|
Technologies are described herein for allocating pages in a flash memory. Some example technologies may receive multiple data elements and a write request to write the multiple data elements to the flash memory.
|Method of operating a split gate flash memory cell with coupling gate|
A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the first region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate.
|Flash memory, flash memory system and operating method of the same|
A flash memory, a flash memory system, and an operating method thereof. The method of operating a flash memory includes counting the number of memory cells having threshold voltages included in a first adjacent threshold voltage range (defined by a first reference read voltage for distinguishing between initially separated adjacently located threshold voltage distributions and a first search read voltage having a first voltage difference from the first reference read voltage), and a second adjacent threshold voltage range (defined by the first reference read voltage and a second search read voltage having a second voltage difference from the first reference read voltage), and setting a first optimal read voltage based on the difference between the first and second counted numbers of the memory cells..
|Storage system which realizes asynchronous remote copy using cache memory composed of flash memory, and control method thereof|
The first storage apparatus provides a primary logical volume, and the second storage apparatus has a secondary logical volume. When the first storage apparatus receives a write command to the primary logical volume, a package processor in a flash package allocates first physical area in the flash memory chip to first cache logical area for write data and stores the write data to the allocated first physical area.
|Test partitioning for a non-volatile memory|
Systems and methods are provided for testing a non-volatile memory, such as a flash memory. The non-volatile memory may be virtually partitioned into a test region and a general purpose region.
|P-channel 3d memory array|
A p-channel flash memory device including a 3d nand array has excellent performance characteristics. Techniques for operating 3d, p-channel nand arrays include selective programming, selective (bit) erase, and block erase.
|Programmable and flexible reference cell selection method for memory devices|
Systems, methods, and computer program products for programmable reference cell selection for flash memory are disclosed. An exemplary system includes an array of interconnected cells and a flexible decoder.