|| List of recent Flash Memory-related patents
| Error tolerant or streaming storage device|
A method of storing data includes receiving general purpose (gp) data and special error tolerant or streaming (ets) data, storing the gp data using a data storage method, and storing the ets data using a different data storage method which affects the access rate, resilience to errors, data integrity, storage density, or storage capacity. The storage medium, which can include a disk drive, flash memory, or holographic memory, is utilized differently depending on the required quality of service in aspects including block size, storage of error correction codes, utilization of error correction codes, storage area density, physical format pattern, storage verification, or reaction to failed storage verification.
| Flash storage controller execute loop|
A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor.
| Programming mode for multi-layer storage flash memory array and switching control method thereof|
The present invention relates to a programming mode for improving the reliability of a multi-layer storage flash memory device in a semiconductor storage field. The present invention provides several programming modes for improving the reliability of a multi-layer storage flash memory device and switching control methods thereof, based on the technical conception of skipping some specific logic pages in the programming process to reduce the impact of the floating gate coupling effect on the operation of the flash memory.
| Raid configuration in a flash memory data storage device|
A method of storing data in a flash memory data storage device that includes a plurality of memory chips is disclosed. The method includes determining a number of memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips and defining a second partition of the data storage device via a host coupled to the data storage device, where the second partition includes a second subset of the plurality of memory chips.
| Use of high endurance non-volatile memory for read acceleration|
A high endurance, short retention nand memory is used as a read cache for a memory of a higher level of non-volatility, such as standard nand flash memory or a hard drive. The combined memory system identifies frequently read logical addresses of the main non-volatile memory or specific read sequences and stores the corresponding data in cache nand to accelerate host reads.
| Data decompression method for a controller equipped with limited ram|
A method of operating a controller to decompress a compressed data file stored on a host computer, and store the resulting uncompressed data in a flash memory. The processor loads compressed data into random access memory (ram) until a predetermined amount of compressed data is present in the ram.
| Method of manufacturing flash memory cell|
A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ono) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ono spacer, and forming a floating gate at outer sides of the ono spacer on the second dielectric layer, respectively.. .
| Non-volatile semiconductor memory having multiple external power supplies|
A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory.
| Integrated circuit device|
A booster circuit is configured, such that: in response to a reading request for reading data from a flash memory, when a voltage of an output terminal detected by a voltage detection circuit is not higher than a voltage, an oscillator outputs a control clock signal of predetermined on time and off time to a transistor of a boost converter to perform switching control of the transistor; and when the voltage detection circuit detects that the voltage of the output terminal reaches a voltage, an oscillator outputs a control clock signal of an on time and an off time input from a selection circuit to a transistor of a boost converter to perform switching control of the transistor.. .
| Three dimensional stacked semiconductor structure and method for manufacturing the same|
A three dimensional stacked semiconductor structure comprises a stack including plural oxide layers and conductive layers arranged alternately, at least a contact hole formed vertically to the oxide layers and the conductive layers, and extending to one of the conductive layers, an insulator formed at the sidewall of the contact hole, a conductor formed in the contact hole and connecting the corresponding conductive layer, and the corresponding conductive layer comprises a silicide. The silicide could be formed at edges or an entire body of the corresponding conductive layer.
|Extending the capabilities of existing devices without making modifications to the existing devices|
A system of extending functionalities of a host device using a smart flash storage device comprises the host device having a host interface and configured to perform a specific function to generate a first set of data. The host device is coupled with a flash storage device.
|Variable over-provisioning for non-volatile storage|
Dynamically varying over-provisioning (op) enables improvements in lifetime, reliability, and/or performance of a solid-state disk (ssd) and/or a flash memory therein. A host coupled to the ssd writes newer data to the ssd.
|Metadata rebuild in a flash memory controller following a loss of power|
A method of rebuilding metadata in a flash memory controller following a loss of power is provided. The method includes reading logical address information associated with an area of flash memory, and using time stamp information to determine if data stored in the flash memory area are valid..
|System, method and apparatus for handling power limit restrictions in flash memory devices|
A system, method and apparatus for dynamic power management including creating a model for each task of multiple tasks performed by a circuit, the model including a corresponding power requirement value for each task, selecting each task for execution, executing the selected task when the corresponding power requirement value does not exceed an average power consumption cap of an execution window, determining an actual power consumption of the selected task during execution of the selected task and storing the actual power consumption corresponding to the selected task as the corresponding power requirement value for the selected task. A memory system can include a memory die, a data bus coupled to the memory die, a power supply coupled to the memory die, a power monitor coupled to the memory die and the power supply and a controller coupled to the data bus and the memory die..
|Multi-port semiconductor memory device with multi-interface|
A semiconductor memory device is provided which includes a first port configured to connect to a first processor and including a first interface circuit; a second port configured to connect to a second processor and including a second interface circuit; and a memory cell array including a first memory area connected to the first and second ports in common. The first memory area includes a plurality of magneto-resistive random access memory cells.
|Full metal gate replacement process for nand flash memory|
A nand flash memory chip is made by forming sacrificial control gate structures and sacrificial select structures, and subsequently replacing these sacrificial structures with metal. Filler structures are formed between sacrificial control gate structures and are subsequently removed to form air gaps between neighboring control gate lines and between floating gates..
|Storage system including a plurality of flash memory devices|
A storage system including a storage device which includes media for storing data from a host computer, a medium controller for controlling the media, a plurality of channel controllers for connecting to the host computer through a channel and a cache memory for temporarily storing data from the host computer, wherein the media have a restriction on a number of writing times. The storage device includes a bus for directly transferring data from the medium controller to the channel controller..
|Computing system and method of managing data in the computing system|
A computing system a storage device and a file system. The storage device includes a storage area having flash memory.
|Flash memory dual in-line memory module management|
Systems and methods to manage memory on a dual in-line memory module (dimm) are provided. A particular method may include receiving at a flash application-specific integrated circuit (asic) a request from a processor to access data stored in a flash memory of a dimm.
|Microcontroller with integrated interface enabling reading data randomly from serial flash memory|
A microcontroller includes a microprocessor, a serial flash memory interface, and input/output (i/o) terminals for coupling the serial flash memory interface to external serial flash memory. The microprocessor is operable to generate instruction frames that trigger respective commands to read data from specified addresses in the external serial flash memory.
|Method, apparatus, and manufacture for staggered start for memory module|
A method, apparatus, and manufacture for memory device startup is provided. Flash memory devices are configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory is arranged to load the random access memory with instructions for the flash memory, and then execute a first portion of the instructions for the flash memory.
|Method for programming and reading flash memory by storing last programming page number|
The invention is to provide a method for programming and reading a flash memory, storing the last programming page in a block while programming the flash memory, judging the programming times in the cell of the block by means of the last programming page and the order and distribution of the page in the predefined page distribution list of the block while reading the flash memory, and selecting the predefined voltage based on the judged programming times to implement the reading process for raising reading performance.. .
|Support lines to prevent line collapse in arrays|
Methods for preventing line collapse during the fabrication of nand flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be provided to prevent the collapse of closely spaced device structures during fabrication.
|Error estimation module and estimation method thereof for flash memory|
The present invention relates to the field of data storage, and more particularly to an estimation technology in an error correction process of a flash memory. The present invention provides an error estimation module and an error estimation method thereof for a flash memory.
|Flash memory and accessing method thereof|
A flash memory and an accessing method thereof are provided. The accessing method includes steps of receiving a plurality of contiguous accessing commands, sequentially selecting a plurality of word lines corresponding to the accessing commands, and accessing a plurality of memory cells on each of the word lines according to the accessing commands sequentially.
|Hardware integrity verification|
A flash memory management method and apparatus provides for the separation of the command and data paths so that communication paths may be used more efficiently, taking account of the characteristics of nand flash circuits where the times to read, write and erase data differ substantially. A unique sequence identifier is assigned to a write command and associated data and association of the data and commands are validated prior to writing to the memory by comparing the unique sequence numbers of the data and command prior to executing the command.
|Mobile financial transaction system and method|
Mobile financial transaction system and method are disclosed for use with mobile payment and secure financial service platform. With the method and system disclosed, users can perform mobile financial transactions with a handheld mobile device.
|Flash memory with p-type floating gate|
Methods for manufacturing non-volatile memory devices including peripheral transistors with reduced and less variable gate resistance are described. In some embodiments, a nand-type flash memory may include floating-gate transistors and peripheral transistors (or non-floating-gate transistors).
|Method for presenting custom content in set top box and set top box|
A method for presenting a custom content in a set top box and a set top box are disclosed. The method includes checking a display cache and a flash memory of a set top box after the set top box is powered on, writing a custom content in the flash memory into the display cache if the display cache and the flash memory of the set top box are checked correct, controlling the custom content written into the display cache to be presented to a user on a video terminal, and, after the custom content written into the display cache is controlled to be presented to the user on the video terminal, checking a hardware device other than the display cache and the flash memory in the set top box, starting an operating system of the set top box, and performing network authentication..
|Error correcting for improving reliability by combination of storage system and flash memory device|
According to this invention, a highly reliable memory device that uses up a life of a flash memory can be provided. The memory device is a nonvolatile memory device including a plurality of memory cells, in which: each of the plurality of memory cells is an fet which includes a floating gate; the plurality of memory cells are divided into a plurality of deletion blocks; and the nonvolatile memory device reads data stored in a first deletion block, detects and corrects an error contained in the read data, stores, when the number of bits of the detected error exceeds a threshold, the corrected data in a second deletion block, sets a smaller value as the threshold as an error frequency detected in the first deletion block is higher, and sets a smaller value as the threshold as the number of deletion times executed in the first deletion block is larger..
|Flash memory architecture with separate storage of overhead and user data|
A memory device has a plurality of dedicated data blocks for storing user data and a plurality of dedicated overhead blocks for storing overhead data. A dedicated overhead block of the plurality of dedicated overhead blocks has a plurality of overhead segments.
|Embedded multimedia card (emmc), host controlling emmc, and method operating emmc system|
An embedded multimedia card (emmc) includes a flash memory and an emmc controller that controls operation of the flash memory. The emmc controller includes a command register that receives from a host a command set defining a next operation specifying second data simultaneously with a transfer of first data specified by a current operation, a first memory that stores the first data, and a second memory that stores the second data..
|Data storage device and flash memory control method thereof|
A mapping table h2f update technique for a flash memory is disclosed. In a disclosed data storage device, the controller updates a logical-to-physical address mapping table between a host and the flash memory in accordance with a group count of a buffer block of the flash memory.
|Flash memory controller having dual mode pin-out|
A memory controller of a data storage device, which communicates with a host, is configurable to have at least two different pinout assignments for interfacing with respective different types of memory devices. Each pinout assignment corresponds to a specific memory interface protocol.
|Data storing method, memory controller and memory storage apparatus|
A data storing method for a memory storage apparatus having a flash memory module is provided. The method includes detecting the operating temperature of the memory storage device through a thermal sensor and determining whether the operating temperature of the memory storage device is larger than a predetermined temperature.
|Embedded multimedia card (emmc), host for controlling emmc, and method operation for emmc system|
An emmc includes flash memory including an extended card specific data (csd) register (“ext_csd register”), and an emmc controller that controls operation of the flash memory. The emmc controller is receives a clock from a host via a clock line, receives a send_ext_csd command from the host via a command line, and provides the host with emmc information stored in the ext_csd register via a data bus in response to the send_ext_csd command, the emmc information including maximum operating frequency information for the emmc..
|Processes for nand flash memory fabrication|
Narrow word lines are formed in a nand flash memory array using a double patterning process in which sidewall spacers define word lines. Sidewall spacers also define edges of select gates so that spacing between a select gate and the closest word line is equal to spacing between adjacent word lines..
|Methods of making word lines and select lines in nand flash memory|
A nand flash memory chip includes word lines formed by etching through concentric conductive loops and, in the same etch step, etching through a conductive strip to form select lines. A conductive loop forms two word lines which are in different erase blocks and are separately controlled by peripheral circuits..
|Data storage device and flash memory control method thereof|
Storage space allocation and a wear leveling technique for a flash memory module are disclosed. The flash memory module includes a plurality of flash chips.
|Embedded nonvolatile memory elements having resistive switching characteristics|
Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer.