|| List of recent Flash Memory-related patents
| Flash memory system having abnormal wordline detector and abnormal wordline detection method|
A flash memory controller for a flash memory system includes an ecc circuit that receives first page data and second page data read from the flash memory, and respectively counts a first number of fail bits in the first page data and a second number of fail bits in the second page data, an abnormal wordline detector configured to compare the first number of fail bits and second number of fail bits to derive a fail bit change rate between the first page data and the second page data, and generate an abnormal wordline detection signal in response to the fail bit change rate, and a control unit that controls operation of the flash memory in response to the abnormal wordline detection signal.. .
| Flash memory read scrub and channel tracking|
An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) read data from a region of a memory circuit during a read scrub of the region and (ii) generate a plurality of statistics based on (a) the data and (b) one or more bit flips performed during an error correction of the data.
| Measuring platform components with a single trusted platform module|
In accordance with some embodiments, a single trusted platform module per platform may be used to handle conventional trusted platform tasks as well as those that would arise prior to the existence of a primary trusted platform module in conventional systems. Thus one single trusted platform module may handle measurements of all aspects of the platform including the baseboard management controller.
| Data accessing method for flash memory storage device having data perturbation module, and storage system and controller using the same|
A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module.
| Flash storage device and control method for flash memory|
A flash memory is used in data storage and is further stored with a logical-to-physical address mapping table and a write protection mapping table. The write protection mapping table shows the write protection statuses of the different logical addresses.
| Solid-state drive device|
A solid state drive (ssd) device using a flash memory and including a non-volatile memory that differs in type from the flash memory. The ssd device receives data to be written to the flash memory; stores the received data in the non-volatile memory; stores the data stored in the non-volatile memory to the flash memory; and stores, in the non-volatile memory, flow data indicating a flow of tasks to be undertaken while storing the received data in the non-volatile memory and storing the data stored in the non-volatile memory to the flash memory..
| Flash memory devices and controlling methods therefor|
A flash memory controller is provided. The flash memory controller includes a read/write unit, a state machine, a processing unit, and a reserve unit.
| Integrated storage and switching for memory systems|
An integrated networked storage and switching apparatus comprises one or more flash memory controllers, a system controller, and a network switch integrated within a common chassis. The integration of storage and switching enables the components to share a common power supply and temperature regulation system, achieving efficient use of available space and power, and eliminating added complexity of external cables between the switch a storage devices.
| Non-volatile memory device, method for controlling the same, and data processing system using the control method|
A non-volatile memory device, a method for controlling the same, and a data processing system using the device and method are disclosed, which relates to a technology for controlling operations of a flash memory device. The non-volatile memory device comprises a cell array configured to comprise a plurality of cells coupled between a word line and a bit line; a drive controller configured to calculate a constant value corresponding to variation in word-line resistance values measured at individual word-line positions, combine the constant value with a word-line address, and set a rising time of the word line; and a voltage provider configured to provide a bias voltage in response to the rising time set in the drive controller..
| Flash memory device and operating method thereof|
A semiconductor memory device includes a current sourcing unit configured to supply a given current to a source line when a read operation is performed, a memory cell string configured to store data and receive the given current from the source line, and a data sensing unit configured to sense the given current transferred from the memory cell string to a bit line and latch the sensed given current in a data form.. .
| Nor flash memory array structure, mixed nonvolatile flash memory and memory system comprising the same|
A nor flash memory array structure is provided, comprising: a substrate (100); and a two dimensional memory array structure formed on the substrate (100) and comprising: a plurality of memory cell columns arranged in a first direction, and each memory cell column including a plurality of memory cells (300), in which each memory cell (300) comprises: a channel region (308) located on the substrate (100), a gate structure located on the channel region (308) and formed by a tunneling oxide layer (304), a silicon nitride layer (303), a barrier oxide layer (302) and a polysilicon gate layer (301) stacked sequentially, a source region (306) and a drain region (305) located at a first edge and a second edge of the gate structure respectively; a plurality of word lines wl; a source line sl for connecting the source regions of all the memory cells; and a plurality of bit lines bl.. .
| Method of storing data on a flash memory device|
Methods and apparatus are disclosed, such as those involving a flash memory device. One such method includes storing data on memory cells on a memory block including a plurality of word lines and a plurality of memory cells on the word lines.
| Chassis with separate thermal chamber for solid state memory|
A chassis for a network storage system contains a first thermal chamber that houses conventional electronic components and a second thermal chamber that houses non-volatile solid state memory such as flash memory. A cooling system keeps the electronics in first thermal chamber below their maximum junction temperature.
|Memory system having nand-type flash memory and memory controller used in the system|
According to one embodiment, a memory system includes a nand-type flash memory and a memory controller. A comparison module of the memory controller compares a first threshold voltage distribution of a first memory area with a second threshold voltage distribution of the first memory area acquired earlier than the first threshold voltage distribution, if an error is detected in data read from the first memory area.
|Storage device firmware and manufacturing software|
Storage device firmware (fw) and manufacturing software techniques include access to fw images and communication of a manufacturing software tool. The manufacturing software tool enables download of the fw images into an i/o device and controlling a manufacturing test of the i/o device that is a storage device providing a storage capability.
|Storage devices including non-volatile memory and memory controller and methods of allocating write memory blocks|
Storage devices including a flash memory and a memory controller, and write memory block allocating methods of the storage devices are provided. A write memory block allocating method may include storing a pre-allocation table in a random access memory (ram) of a memory controller.
|Flash memory controller, flash memory system, and flash memory control method|
A flash memory controller configures, in a polling interval storage part, a polling interval, which is a time interval for outputting an acquisition signal for acquiring from a flash memory, information showing whether or not the execution of programing or erasing has ended after the execution of the programming or erasing has started with respect to the flash memory. The flash memory controller sends either a program command or an erase command to the flash memory, and thereafter, outputs the acquisition signal in accordance with the configured polling interval until information denoting that the execution of either the programming or the erasing has ended is received..
|Host apparatus and memory device|
According to one embodiment, a host apparatus is capable of accessing memory device. The host apparatus includes application software, a dedicated file system, and an interface circuit.
|Point of sale multi-functional devices|
Improvements in a point of sale multi-functional device are disclosed. The device can operate as a stand-along unit or as a tablet companion device.
|Portable assemblies, systems, and methods for providing functional or therapeutic neurostimulation|
Neurostimulation assemblies, systems, and methods make possible the providing of short-term therapy or diagnostic testing by providing electrical connections between muscles and/or nerves inside the body and stimulus generators and/or recording instruments mounted on the surface of the skin or carried outside the body. Neurostimulation assemblies, systems, and methods may include a carrier and an electronics pod, the electronics pod including stimulation generation circuitry and user interface components.
|Linecards with pluggable interfaces for pluggable optical amplifiers and other pluggable devices|
A linecard includes at least one pluggable device, a linecard processor, and a centralized host processor. The linecard also includes an interface that supports a pluggable device.
|Threshold optimization for flash memory|
Described embodiments provide enhanced read accuracy of a multi-level cell (mlc) flash memory. A read request for desired cells is received by a media controller of the memory.
|Structures and methods for making nand flash memory|
A nand flash memory chip includes wide openings in an inter-poly dielectric layer through which gaps are later etched to define structures such as select gates. Such select gates are asymmetric, with inter-poly dielectric on a side adjacent to a memory cell and no inter-poly dielectric on a side away from a memory cell.
|Wireless router remote firmware upgrade|
A wireless router receives a firmware update from a remote server, and destructively overwrites router firmware in flash memory in a chunk-wise manner, and then writes a kernel memory before going live with upgraded firmware. Some routers authenticate the firmware image.
|Memory address translation method for flash storage system|
A memory address translation method for flash storage system is disclosed. There are two level mapping tables to reduce overhead of mapping table management.
|Dynamic formation of garbage collection units in a memory|
Method and apparatus for managing data in a memory, such as but not limited to a flash memory. In accordance with some embodiments, a memory is provided with a plurality of addressable data storage blocks which are arranged into a first set of garbage collection units (gcus).
|System and method for emulating an eeprom in a non-volatile memory device|
The invention relates to an electronic memory system, and more specifically, to a system for emulating an electrically erasable programmable read only memory in a non-volatile memory device, and a method of emulating an electrically erasable programmable read only memory in a non-volatile memory device. According to an embodiment, a system for emulating an electrically erasable programmable read only memory is provided, the system including a flash memory, wherein the flash memory is configurable into a first region and a second region, wherein the first region is adapted to store a first class of data and the second region is adapted to store a second, different class of data..
|Method of executing wear leveling in a flash memory device according to ambient temperature information and related flash memory device|
A method of executing wear leveling in a flash memory device includes determining whether a current temperature is in a normal operating temperature range of the flash memory device, and reprogramming data associated with data blocks to another location in a flash memory array when the current temperature is in the normal operating temperature range of the flash memory device, wherein the data is programmed in a temperature out of the normal operating temperature range of the flash memory device.. .
|Memory system and memory controller|
According to one embodiment, a memory system includes a nand-type flash memory and a memory controller. The memory controller includes a monitoring module and a determination module.
|Operating method for memory system including nonvolatile ram and nand flash memory|
An operating method for a memory system including a nonvolatile random access memory (nvram) and a nand flash memory includes; performing a normal read operation directed to the target memory cell in response to a read request, determining that a read fail has occurred as a result of the normal read operation, then performing a read retry operation by iterations directed to the target memory cell according to a first read retry scheme until a pass read retry iteration successfully reads the target memory cell, and storing pass information associated with the pass read retry iteration in the nvram.. .
|Flash memory device including key control logic and encryption key storing method|
A flash memory device is provided which includes a plurality of memory cells connected with a word line and including a key cell to store an encryption key; a data input/output circuit configured to receive the encryption key; and key control logic configured to control a program operation on the key cell and to use a column address of the key cell as the encryption key.. .
|Enterprise server with flash storage modules|
A server system, such as an enterprise server, may include an array of memory devices. The memory devices may include non-volatile or flash memory and be referred to as flash storage modules (“fsm”).
|Semiconductor memory devices|
A flash memory capable of writing or deleting a split block is provided. A flash memory includes a memory array comprising a plurality of blocks, and a word line selection circuit, wherein each of the plurality of blocks is formed by a plurality of cell units in a well.
|Common line current for program level determination in flash memory|
In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—is determined from the total current passing through the population of memory cells under read conditions, as observed on a common line, for example a source line in nand flash memory.. .
|Soft-decision compensation for flash channel variation|
In an ssd controller reading from flash memory, subsequent to failure of an initial soft-decision decoding attempt based on a nominal llr, soft-decision re-decoding attempts are made using compensated llr soft-decision information sets, pre-calculated at respective read-equilibrium points corresponding to mean shifts and variance change in the actual charge-state distributions of the flash memory channel. According to embodiment, soft-decision re-decoding attempts are performed without a retry read, or overlapped with one or more retry reads.
|Device based wear leveling|
A system for improving the management and usage of blocks based on intrinsic endurance may be used to improve memory usage for flash memory, such as a memory card. The overall card endurance may be extended by cycling blocks with higher intrinsic endurance over the lowest endurance target of the worst block.
|Encrypted-transport solid-state disk controller|
An encrypted transport ssd controller has an interface for receiving commands, storage addresses, and exchanging data with a host for storage of the data in a compressed (and optionally encrypted) form in non-volatile memory (nvm), such as flash memory. Encrypted data received from the host is decrypted and compressed using lossless compression for advantageously reducing flash memory write amplification.
|Flash memory utilizing a high-k metal gate|
According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric o one layer includes a first high-k dielectric material.