|| List of recent Flash Memory-related patents
| Memory system and wear-leveling method thereof|
Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller.
| Lsi and information processing system|
The controller lsi is connected to an spi flash memory having a deep power down mode (dpm), and brings the spi flash memory to the dpm and then brings itself to low power consumption mode (lpm) that volatilizes data in a ram. This invention solves the problem that the controller lsi cannot release the peripheral device from the dpm upon returning from the lpm due to the volatilization of the data.
| Methods and systems for reducing churn in flash-based cache|
A storage device includes a flash memory-based cache for a hard disk-based storage device and a controller that is configured to limit the rate of cache updates through a variety of mechanisms, including determinations that the data is not likely to be read back from the storage device within a time period that justifies its storage in the cache, compressing data prior to its storage in the cache, precluding storage of sequentially-accessed data in the cache, and/or throttling storage of data to the cache within predetermined write periods and/or according to user instruction.. .
| Methods and systems for reducing churn in flash-based cache|
A storage device includes a flash memory-based cache for a hard disk-based storage device and a controller that is configured to limit the rate of cache updates through a variety of mechanisms, including determinations that the data is not likely to be read back from the storage device within a time period that justifies its storage in the cache, compressing data prior to its storage in the cache, precluding storage of sequentially-accessed data in the cache and/or throttling storage of data to the cache within predetermined write periods and/or according to user instruction.. .
| Mitigate flash write latency and bandwidth limitation|
A method of operating a memory system is provided. The method includes a controller that regulates read and write access to one or more flash memory devices that are employed for random access memory applications.
| Method for programming a flash memory|
A method of programming a flash memory is described. The method includes partitioning a flash memory into a first group having a first level of write-protection, a second group having a second level of write-protection, and a third group having a third level of write-protection.
| Method and apparatus for reading data stored in flash memory by referring to binary digit distribution characteristics of bit sequences read from flash memory|
A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.. .
| Reduced complexity reliability computations for flash memories|
Methods and apparatus are provided for computing reliability values, such as log likelihood ratios (llrs), with reduced complexity for flash memory devices. Data from a flash memory device that stores m bits per cell using 2̂m possible states is processed by obtaining at least two soft read voltage values corresponding to two reference voltages v0 and v1, wherein the two reference voltages v0 and v1 are between two adjacent states of the 2̂m possible states; and converting the at least two soft read voltage values to a log likelihood ratio for a region between the two reference voltages v0 and v1 using probability density functions only for the two adjacent states.
| Thermal regulation for solid state memory|
A chassis for a storage system contains a digital chamber that houses conventional electronic components and a thermal chamber that houses non-volatile solid state memory such as flash memory. A temperature regulating system monitors temperature within the digital chamber to keep the components therein below their maximum junction temperature.
| Nand flash memory unit and nand flash memory array|
A nand flash memory unit is described, including a string of memory cells connected in series, s/d regions coupled to two terminals of the string, at least one select transistor couple between a terminal of the string and an s/d region, and at least one erase transistor couple between the at least one select transistor and an s/d region. The select transistor is for selecting the string of memory cells.
|Method and apparatus for reading data from non-volatile memory|
Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array.
|Mass storage controller volatile memory containing metadata related to flash memory storage|
A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor.
|Hybrid drive that implements a deferred trim list|
A hybrid drive controller maintains a deferred trim list that holds a subset of logical addresses of writes performed on magnetic disks. For example, if a write command is issued to an lba space that overlaps a portion stored in flash memory and the write is to be performed on the magnetic disks, the trimming of the overlapping portion in the flash memory will be deferred.
|Dynamic data caches, decoders and decoding methods|
Examples described include dynamic data caches (ddcs), decoders and decoding methods that may fit into a smaller width area. The ddcs, decoders and decoding method may be used in flash memory devices.
|3d stacked nand flash memory array having ssl status check buildings for monitoring threshold voltages of string selection transistors and methods for monitoring and operating the same|
Disclosed is a 3d stacked nand flash memory array having ssl status check buildings for monitoring threshold voltages of string selection transistors, a monitoring method of threshold voltages of string selection transistors by the ssl status check buildings, and an operating method thereof.. .
|Flash memory device reducing layout area|
A flash memory device reducing a layout area is provided. In the flash memory device, even power transistors and odd power transistors of a plurality of power connection portions corresponding to a plurality of pairs of bit lines and even select transistors and odd select transistors of a plurality of select connection portions corresponding thereto are disposed in one common active region.
|3d nand flash memory|
A memory device includes an array of nand strings of memory cells. The device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips.
|Nand flash memory device|
A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.. .
|Statistical adaptive error correction for a flash memory|
A method for implementing adaptive error correction in a memory, comprising the steps of (a) decoding a page of data read from a memory, (b) selecting one of a plurality of histograms based on a measured code word error rate of the decoded page and (c) applying an error correction code rate based on the selected histogram. The error correction code rate allows the memory to use a minimum number of error correction bits to provide reliable operation of the memory..
|Method and apparatus for power loss recovery in a flash memory-based ssd|
The present invention relates to a storage device that uses a flash memory that performs power loss recovery, and to a method of power loss recovery by using the storage device using the flash memory. The storage device stores change information on metadata in physical pages in which one or more logical pages are compressed and stored.
|Scheduling of reactive i/o operations in a storage environment|
A system and method for effectively scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network.
|Selectively programming data in multi-level cell memory|
Devices, systems, methods, and other embodiments associated with accessing memory are described. In one embodiment, a method detects that a power quality associated with a volatile memory in a computing device meets a threshold value and in response thereto, reprogramming data from the volatile memory to a flash memory comprising multi-level cells.
|Operating system based dram and flash management|
A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more flash memory devices that are employed for random access memory applications.
|Remote plasma radical treatment of silicon oxide|
Embodiments described herein generally relate to methods for manufacturing flash memory devices. In one embodiment, the method includes generating a plasma comprising nitrogen-containing radicals in a remote plasma applicator, flowing the plasma comprising nitrogen-containing radicals into a processing region of the processing chamber where a semiconductor device is disposed, wherein the semiconductor device has a substrate comprising an oxide layer formed thereon, exposing an exposed surface of the oxide layer to the nitrogen-containing radicals, and incorporating nitrogen in the exposed surface of the oxide layer of the substrate..
|Method of programming flash memory|
A method of programming a nand flash memory cell string. The method includes a pre-boost stage configured to elevate channel voltage of a selected memory cell, and a boost stage is introduced after the pre-boost stage.
|Memory system performing multi-step erase operation based on stored metadata|
A memory system, comprising a flash memory comprising multiple memory blocks, and a controller configured to erase each of the memory blocks using multiple steps. The controller stores, for each of the memory blocks, metadata indicating which of the multiple steps have been completed, and erases each of the memory blocks based on the stored metadata..
|Fast-reading nand flash memory|
In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line from the read voltage to a discrimination voltage.. .
|Flash memory cells having trenched storage elements|
An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench.
|Secure replay protected storage|
Embodiments of the invention enable secure standard storage flash memory devices such as spi flash memory devices to achieve replay protection for securely stored data. Embodiments of the invention utilize flash memory controllers, flash memory devices, unique device keys and hmac key logic to create secure execution environments for various components..
|Method and device for storing data in a flash memory using address mapping for supporting various block sizes|
The present invention relates to a method and device for storing data in a flash memory using address mapping for supporting various block sizes. A storage device determines the size of a block that a host system uses on the basis of the size of data that the host system requests and uses the determined block size as a mapping unit.
|Memory method and apparatus with button release|
A flash memory device apparatus and method is provided such that data or programming information is uploaded or downloaded between the flash memory device and a host, in response to a single-press of a button associated with the flash memory device. The system can facilitate a number of operations including saving an active window application or associated data, transferring media files to or from media players, providing device-specific and/or data-specific transfer of applications or data and/or providing protection of transferred data or applications..
|Flash multiple-pass write with accurate first-pass write|
An indication to store a data value in flash memory is received. An accurate coarse write is performed on the flash memory, including by: storing a first voltage level in the flash memory and setting a configuration setting of the flash memory to a first setting.
|High density vertical structure nitride flash memory|
A charge trap type of memory having a memory channel with vertical and possibly horizontal components is described. The invention includes a new operation method of simultaneous hole and electron injection operation for high speed and high reliability non-volatile memories, as well as high-density non-volatile memories.
|Method and apparatus for leakage suppression in flash memory in response to external commands|
Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells.
|Charge-trap type flash memory device having low-high-low energy band structure as trapping layer|
A charge-trap type flash memory device having a low-high-low energy band as a trapping layer embeds al2o3 between si3n4 and hfo2 as a ct layer. Most injected charged can be trapped at an interface of si3n4/al2o3.
|High-speed memory system|
The disclosed embodiments relate to a flash-based memory module having high-speed serial communication. The flash-based memory module comprises, among other things, a plurality of i/o modules, each configured to communicate with an external device over one or more external communication links, a plurality of flash-based memory cards, each comprising a plurality of flash memory devices, and a plurality of crossbar switching elements, each being connected to a respective one of the flash-based memory cards and configured to allow each one of the i/o modules to communicate with the respective one of the flash-based memory cards.
|Memory buffer with one or more auxiliary interfaces|
The present memory system includes a memory buffer having an interface arranged to buffer data and/or command bytes being written to or read from the ram chips residing on a dimm by a host controller. The memory buffer further includes at least one additional interface arranged to buffer data and/or command bytes between the host controller or ram chips and one or more external devices coupled to the at least one additional interface.
|Cooperative flash memory control|
This disclosure provides for host-controller cooperation in managing nand flash memory. The controller maintains information for each erase unit which tracks memory usage.
|Providing subsciber identity module function|
A host processing apparatus (100) and a user removable memory (40) are disclosed. The host processing apparatus (100) and the user removable memory (40) are, in use, connected to one another by respective connectors.