|| List of recent Flash Memory-related patents
|Techniques for surfacing host-side flash storage capacity to virtual machines|
Techniques for surfacing host-side flash storage capacity to a plurality of vms running on a host system are provided. In one embodiment, the host system creates, for each vm in the plurality of vms, a flash storage space allocation in a flash storage device that is locally attached to the host system.
|Microcontroller for pollution control system for an internal combustion engine|
A pollution control system for an internal combustion engine includes a microcontroller and a power supply, a plurality of sensors configured to measure operating parameters of the engine, and a pcv valve responsive to a control signal from the microcontroller and configured to regulate a flow rate of blow-by gasses in the engine. The microcontroller includes programmable flash memory connected to a control processor, a power supply input, a sensor input configured to receive data from an engine sensor, and a signal output configured to transmit a signal from the control processor so as to control operation of a pcv valve regulating a flow rate of blow-by gasses in the engine..
|Dynamic detection method for latent slow-to-erase bit for high performance and high reliability flash memory|
A method and apparatus for detecting a latent slow bit (e.g., a latent slow-to-erase bit) in a non-volatile memory (nvm) is disclosed. A maximum number of soft program pulses among addresses during an erase cycle is counted.
|Flash memory module for realizing high reliability|
A flash memory module may include a plurality of flash memory chips. The memory chips may include one or more blocks.
A memory system includes a flash memory including a block having first sub-blocks and second sub-blocks different from each other, the second sub-blocks including free pages only; and a controller configured to erase the flash memory in units of the sub-blocks, and in a garbage collection operation, the controller is configured to copy data of a valid page of the first sub-blocks to at least one of the second sub-blocks.. .
|Endoscope apparatus and deterioration detection method of polarization element of endoscope|
An endoscope apparatus includes a flash memory that stores a reference value of a color balance adjustment value of an endoscopic image of an endoscope that picks up an object through a polarizer. The endoscope calculates, from the reference value and the color balance adjustment value of the endoscope after elapse of a predetermined time period, an amount of change in the color balance adjustment value; judges whether or not the calculated amount of change is equal to or larger than a predetermined threshold; and, when the amount of change is equal to or larger than the predetermined threshold, outputs a predetermined output..
|Solid state drive|
Provided is a solid state drive suitable for an increase in capacity. The solid state drive includes a flash memory, and a capacitor electrically connected to the flash memory.
|Solid state drive and data retention method thereof|
A data retention method is provided. After the solid state drive is powered on, a current date information is received from a host.
|Flash memory-hosted local and remote out-of-service platform manageability|
A method, apparatus, and system are disclosed. In one embodiment, the method determines whether one or more manageability conditions are present in a computer system, and then invokes an out-of-service manageability remediation environment stored within a portion of a flash device in the computer system when one or more manageability conditions are present..
|Distributed procedure execution and file systems on a memory interface|
Nonvolatile memory (e.g., flash memory, solid-state disk) is included on memory modules that are on a dram memory channel. Nonvolatile memory residing on a dram memory channel may be integrated into the existing file system structures of operating systems.
|Page allocation for flash memories|
Technologies are described herein for allocating pages in a flash memory. Some example technologies may receive multiple data elements and a write request to write the multiple data elements to the flash memory.
|Method of operating a split gate flash memory cell with coupling gate|
A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the first region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate.
|Flash memory, flash memory system and operating method of the same|
A flash memory, a flash memory system, and an operating method thereof. The method of operating a flash memory includes counting the number of memory cells having threshold voltages included in a first adjacent threshold voltage range (defined by a first reference read voltage for distinguishing between initially separated adjacently located threshold voltage distributions and a first search read voltage having a first voltage difference from the first reference read voltage), and a second adjacent threshold voltage range (defined by the first reference read voltage and a second search read voltage having a second voltage difference from the first reference read voltage), and setting a first optimal read voltage based on the difference between the first and second counted numbers of the memory cells..
|Storage system which realizes asynchronous remote copy using cache memory composed of flash memory, and control method thereof|
The first storage apparatus provides a primary logical volume, and the second storage apparatus has a secondary logical volume. When the first storage apparatus receives a write command to the primary logical volume, a package processor in a flash package allocates first physical area in the flash memory chip to first cache logical area for write data and stores the write data to the allocated first physical area.
|Test partitioning for a non-volatile memory|
Systems and methods are provided for testing a non-volatile memory, such as a flash memory. The non-volatile memory may be virtually partitioned into a test region and a general purpose region.
|P-channel 3d memory array|
A p-channel flash memory device including a 3d nand array has excellent performance characteristics. Techniques for operating 3d, p-channel nand arrays include selective programming, selective (bit) erase, and block erase.
|Programmable and flexible reference cell selection method for memory devices|
Systems, methods, and computer program products for programmable reference cell selection for flash memory are disclosed. An exemplary system includes an array of interconnected cells and a flexible decoder.
|Method for performing data shaping, and associated memory device and controller thereof|
A method for performing data shaping is applied to a controller of a flash memory, where the flash memory includes a plurality of blocks. The method includes: performing a program optimization operation according to original data and a plurality of shaping codes, in order to generate trace back information corresponding to a trellis diagram and utilize the trace back information as side information; and dynamically selecting at least one shaping code from the shaping codes according to the side information to perform data shaping on the original data..
|Solid state storage element and method|
A method and system for storing and retrieving data using flash memory devices. One example system includes an apparatus within a flash memory configuration.
|Memory system having an unequal number of memory die|
A flash memory system having unequal number of memory die and method for operation is disclosed. The memory includes a plurality of flash memory die distributed unevenly among different control lines, such that there are an unequal number of die between control lines.
|Multi-layer memory system having multiple partitions in a layer|
A multi-layer memory and method for operation is disclosed. The memory includes multiple layers, where each layer includes flash memory cells having a greater bit per cell capacity than then prior layer and each layer may include a plurality of partitions having blocks exclusively associated with a particular data type.
|Method and system for program scheduling in a multi-layer memory|
A multi-layer memory and method for operation is disclosed. The memory includes an interface, at least one flash memory die having a plurality of layers and a controller.
|Method and system for managing background operations in a multi-layer memory|
A multi-layer memory and method for performing background maintenance operations are disclosed. The memory includes a plurality of flash memory die having multiple layers, where each layer is made up of flash memory cells having a greater bit per cell storage capacity than then prior layer and each layer may have a plurality of partitions for different data types.
|Method and system for managing block reclaim operations in a multi-layer memory|
A multi-later memory and method for operation is disclosed. The memory includes at least one flash memory die having multiple layers and a controller configured to execute block reclaim operations in a layer of the flash memory die until a net gain of at least one additional free block has been made in the layer.
|Flash memory interface using split bus configuration|
A system having a split bus flash memory and a method for operating the split bus flash memory is disclosed. The system may include a controller, a non-volatile memory (including first and second non-volatile memory chips) and the system bus.
|Flash memory using virtual physical addresses|
A system and method for using virtual physical addresses in a non-volatile memory device are disclosed. The physical layout of the non-volatile memory device may have physical die that are not a power-of-2 in number.
|Sharing serial peripheral interface flash memory in a multi-node server system on chip platform environment|
Methods and apparatus related to sharing serial peripheral interface (spi) flash memory in a multi-node server soc (system on chip) platform environment are described. In one embodiment, multi-port non-volatile memory is shared by a plurality of system on chip (soc) devices.
|Multi-bit flash memory device and memory cell array|
A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2″ pages of data.
|Method and system for asynchronous die operations in a non-volatile memory|
A mass storage memory system and method of operation is disclosed. The memory includes an interface adapted to receive data from a host, a plurality of flash memory die and a controller, where the controller is configured to receive a first command and read or write data synchronously across the plurality of die based on a first command, and to receive a second command and read or write data asynchronously and independently in each die based on a second command.
|Encrypted flash-based data storage system with confidentiality mode|
Raw or unencrypted data is encrypted using a standard encryption algorithm and stored in a flash memory array. The raw or unencrypted data may be pre-processed before it is encrypted.
|Speculative copying of data from main buffer cache to solid-state secondary cache of a storage server|
A network storage server includes a main buffer cache to buffer writes requested by clients before committing them to primary persistent storage. The server further uses a secondary cache, implemented as low-cost, solid-state memory, such as flash memory, to store data evicted from the main buffer cache or data read from the primary persistent storage.
In this flash memory, after first and second nodes are precharged to a power supply voltage, a sense amplifier is activated, and signals appearing at the first and second nodes are held in a register. With output signals of the register, a transistor is rendered conductive, so that a constant current source for offset compensation is connected to the first or second node.
|Circuit for sensing mlc flash memory|
A circuit for sensing a multi-level cell (mlc) flash memory is disclosed. The circuit comprises a plurality of first decoding units, a second decoding unit and a data latch.
|Row decoding circuit and memory|
A row decoding circuit and a memory are provided. The row decoding circuit is adapted for providing a word line operation voltage and a control-gate line operation voltage to a dual-bit split gate flash memory array, and includes a dummy row decoding unit, at least one row decoding unit and a driving voltage generating circuit.
|Semiconductor device manufacturing method|
In a process of dividing gates of multi-layered films in fabricating a nand flash memory having a three-dimensional structure, a pattern is prevented from deforming and falling. A ratio of a length l to a height h of control gate groups configuring a memory cell of the flash memory is set to be less than 1.65 which is a range in which buckling does not occur.
|Error recovery for flash memory|
An indication of a page type which failed error correction decoding is received. A threshold to adjust is selected from a plurality of thresholds based at least in part on the page type.
|Techniques for emulating an eeprom device|
Disclosed are various embodiments of an emulation device for generating a cryptographic hash value associated with program data stored in a memory of a computing device. Validation data is generated based upon the cryptographic hash value and a flush counter of the computing device.
|Semiconductor memory system having a snapshot function|
In a semiconductor memory computer equipped with a flash memory, use of backed-up data is enabled. The semiconductor memory computer includes an address conversion table for detecting physical addresses of at least two pages storing data by designating a logical address from one of logical addresses to be designated by a reading request.
|Nonvolatile flash memory structures including fullerene molecules and methods for manufacturing the same|
Embodiments of tunneling barriers and methods for same can embed molecules exhibiting a monodispersion characteristic into a dielectric layer (e.g., between first and second layers forming a dielectric layer). In one embodiment, by embedding c60 molecules inbetween first and second insulating layers forming a dielectric layer, a field sensitive tunneling barrier can be implemented.
|Method compensation operating voltage, flash memory device, and data storage device|
Disclosed is a method generating a compensated operating voltage, such as a read voltage, in a non-volatile memory device, and a related non-volatile memory device. The operating voltage is compensated in response to one or more memory cell conditions such as temperature variation, programmed data state or physical location of a selected memory cell, page information for selected memory cell, or the location of a selected word line..
A memory array used in the field of semiconductor technology includes a plurality of memory cells, bit lines, word lines perpendicular to the bit lines, and first/second control lines. The memory array uses split-gate memory cells, wherein two memory bit cells of a memory cell share one word line, thereby the read, program and erase of the memory cell can be realized by applying different voltages to the word line, two control gates and source/drain regions; the word line sharing structure enables a split-gate flash memory to effectively reduce the chip area and avoid over-erase problems while maintaining electrical isolation performance of the chip unchanged and not increasing the complexity of the process..