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Semiconductor
Semiconductor Substrate
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Field Effect Transistor
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Leakage Current
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Finfet patents



      
           
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Date/App# patent app List of recent Finfet-related patents
04/17/14
20140106529
 Finfet device with silicided source-drain regions and method of making same using a two step anneal patent thumbnailnew patent Finfet device with silicided source-drain regions and method of making same using a two step anneal
A thermal annealing flow process includes the steps of: depositing a metal or metal alloy on a silicon semiconductor structure, performing a first annealing of a rapid thermal anneal (rta) type to produce a metal rich phase in a portion of the silicon semiconductor structure, removing unreacted metal or metal alloy and performing a second annealing as a millisecond annealing at a temperature that is below a melt temperature of the silicon material present in the silicon semiconductor structure.. .
04/17/14
20140106528
 Finfet circuits with various fin heights patent thumbnailnew patent Finfet circuits with various fin heights
A method of forming a fin field effect transistor (finfet) includes forming a plurality of fins of varying heights on a substrate and forming a first gate structure on one or more fins of a first height to form a first finfet structure and a second gate structure on one or more fins of a second height to form a second finfet structure. The method includes epitaxially forming an epitaxial fill material on the one or more fins of the first finfet structure and the second finfet structure.
04/17/14
20140103455
 Fet devices with oxide spacers patent thumbnailnew patent Fet devices with oxide spacers
Transistors including oxide spacers and methods of forming the same. Embodiments include planar fets including a gate on a semiconductor substrate, oxide spacers on the gate sidewalls, and source or drain regions at least partially in the substrate offset from the gate by the oxide spacers.
04/17/14
20140103453
 Control fin heights in finfet structures patent thumbnailnew patent Control fin heights in finfet structures
A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 Å, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region.
04/17/14
20140103451
 Finfet circuits with various fin heights patent thumbnailnew patent Finfet circuits with various fin heights
A fin field-effect transistor (finfet) assembly includes a first finfet device having fins of a first height and a second finfet device having fins of a second height. Each of the first and second finfet devices includes an epitaxial fill material covering source and drain regions of the first and second finfet devices.
04/17/14
20140103437
 Random doping fluctuation resistant finfet patent thumbnailnew patent Random doping fluctuation resistant finfet
An improved fin field-effect transistor (finfet) is built on a compound fin, which has a doped core and lightly doped epitaxial channel region between that core and the gate dielectric. The improved structure reduces finfet random doping fluctuations when doping is used to control threshold voltage.
04/17/14
20140103435
 Vertical source/drain junctions for a finfet including a plurality of fins patent thumbnailnew patent Vertical source/drain junctions for a finfet including a plurality of fins
Fin-defining mask structures are formed over a semiconductor material layer. A semiconductor material portion is formed by patterning the semiconductor material layer, and a disposable gate structure is formed over the fin-defining mask structures.
04/10/14
20140097506
 Fin field effect transistor, and method of forming the same patent thumbnailFin field effect transistor, and method of forming the same
The description relates to a fin field effect transistor (finfet). An exemplary structure for a finfet includes a fin having a first height above a first surface of a substrate, where a portion of the fin has first tapered sidewalls, and the fin has a top surface.
04/10/14
20140097465
 Silicon controlled rectifier (scr) device for bulk finfet technology patent thumbnailSilicon controlled rectifier (scr) device for bulk finfet technology
Some aspects relate to a semiconductor device disposed on a semiconductor substrate. The device includes an sti region that laterally surrounds a base portion of a semiconductor fin.
03/27/14
20140085966
 Field effect transistors including asymmetrical silicide structures and related devices patent thumbnailField effect transistors including asymmetrical silicide structures and related devices
A fin field effect transistor (finfet) can include a source region and a drain region of the finfet. A gate of the finfet can cross over a fin of the finfet between the source and drain regions.
03/20/14
20140080276
Technique for forming a finfet device
A three-dimensional structure disposed on a substrate is processed so as to alter the etch rate of material disposed on at least one surface of the structure. In some embodiments, a conformal deposition of material is performed on the three-dimensional structure.
03/20/14
20140080275
Multigate finfets with epitaxially-grown merged source/drains
Method of forming multi-gate finfets with epitaxially-grown merged source/drains. Embodiments of the invention may include forming a plurality of semiconductor fins joined by a plurality of inter-fin semiconductor regions, depositing a sacrificial gate over a center portion of each of the plurality of fins, forming a first merge layer over a first end of each of the plurality of fins to form a first merged fin region, forming a second merge layer over the second end of each of the plurality of fins to form a second merged fin region, etching a portion of the first merged fin region to form a first source/drain base region, etching a portion of the second merged fin region to form a second source/drain base region, forming a first source/drain region on the first source/drain base region, and forming a second source/drain region on the second source/drain base region..
03/20/14
20140077331
Diode structures using fin field effect transistor processing and method of forming the same
A method of forming one or more diodes in a fin field-effect transistor (finfet) device includes forming a hardmask layer having a fin pattern, said fin pattern including an isolated fin area, a fin array area, and a finfet area. The method further includes etching a plurality of fins into a semiconductor substrate using the fin pattern, and depositing a dielectric material over the semiconductor substrate to fill spaces between the plurality of fins.
03/20/14
20140077296
Method and structure for finfet with finely controlled device width
A structure and method for fabricating finfets of varying effective device widths is disclosed. Groups of fins are shortened by a predetermined amount to achieve an effective device width that is equivalent to a real (non-integer) number of full-sized fins.
03/20/14
20140077275
Semiconductor device and method with greater epitaxial growth on 110 crystal plane
A semiconductor processing method is provided which promotes greater growth on <110> crystallographic planes than on other crystallographic planes. Growth rates with the process can be reversed compared to typical epitaxial growth processes such that the highest rate of growth occurs on <110> crystallographic planes and the least amount of growth occurs on <100> crystallographic planes.
03/20/14
20140077146
Semiconductor device including finfet device
A memory element includes a finfet select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element..
03/13/14
20140070360
Finfets with vertical fins and methods for forming the same
In a method for forming a device, a (110) silicon substrate is etched to form first trenches in the (110) silicon substrate, wherein remaining portions of the (110) silicon substrate between the first trenches form silicon strips. The sidewalls of the silicon strips have (111) surface orientations.
03/13/14
20140070322
Methods of forming different finfet devices with different threshold voltages and integrated circuit products containing such devices
One illustrative method disclosed herein involves forming a first fin for a first finfet device in and above a semiconducting substrate, wherein the first fin is comprised of a first semiconductor material that is different from the material of the semiconducting substrate and, after forming the first fin, forming a second fin for a second finfet device that is formed in and above the semiconducting substrate, wherein the second fin is comprised of a second semiconductor material that is different from the material of the semiconducting substrate and different from the first semiconductor material.. .
03/13/14
20140070318
Reducing resistance in source and drain regions of finfets
A semiconductor structure includes a semiconductor fin on a top surface of a substrate, wherein the semiconductor fin includes a middle section having a first width; and a first and a second end section connected to opposite ends of the middle section, wherein the first and the second end sections each comprises at least a top portion having a second width greater than the first width. The semiconductor structure further includes a gate dielectric layer on a top surface and sidewalls of the middle section of the semiconductor fin; and a gate electrode on the gate dielectric layer..
03/13/14
20140070294
Finfet trench circuit
A finfet trench circuit is disclosed. Finfets are integrated with trench capacitors by employing a trench top oxide over a portion of the trench conductor.
03/06/14
20140065832
Enhanced finfet process overlay mark
An overlay mark suitable for use in manufacturing nonplanar circuit devices and a method for forming the overlay mark are disclosed. An exemplary embodiment includes receiving a substrate having an active device region and an overlay region.
03/06/14
20140065828
Selective fin cut process
A process is provided for selective removal of one or more unwanted fins during finfet device fabrication. In one aspect, the process includes: providing a conformal protective layer over multiple fin structures on a substrate; patterning one or more openings over the unwanted fin structure(s); and removing at least a top portion of the unwanted fin structure(s) exposed through the opening(s), the removing including removing at least a portion of the conformal protective layer over the unwanted fin structure(s) exposed through the opening(s).
03/06/14
20140065811
Replacement metal gate semiconductor device formation using low resistivity metals
Embodiments of the present invention relate to approaches for forming rmg finfet semiconductor devices using a low-resistivity metal (e.g., w) as an alternate gap fill metal. Specifically, the semiconductor will typically comprise a set (e.g., one or more) of dielectric stacks formed over a substrate to create one or more trenches/channels (e.g., short/narrow and/or long/wide trenches/channels).
03/06/14
20140065802
Techniques for metal gate workfunction engineering to enable multiple threshold voltage finfet devices
Techniques are provided for gate work function engineering in fin fet devices using a work function setting material an amount of which is provided proportional to fin pitch. In one aspect, a method of fabricating a fin fet device includes the following steps.
03/06/14
20140065782
Method of making a finfet device
A finfet device is fabricated by first receiving a finfet precursor. The finfet precursor includes a substrate and fin structures on the substrate.
03/06/14
20140065780
Split-channel transistor and methods for forming the same
A fin field-effect transistor (finfet) includes a fin, which includes a channel splitter having a first bandgap, and a channel including a first portion and a second portion on opposite sidewalls of the channel splitter. The channel has a second bandgap smaller than the first bandgap.
03/06/14
20140065779
Method for manufacturing finfet
Designs and fabrication of a finfet are provided. In one implementation, the fabrication can include forming a dielectric stripe on a substrate; implanting ions to the substrate by using the dielectric stripe as a mask so as to convert a surface layer of the substrate to an amorphous layer; forming an amorphous semiconductor layer on the substrate covering the dielectric stripe and recrystallizing each of the amorphous layer and the amorphous semiconductor layer to be a monocrystalline layer; processing regions beside two ends of the dielectric stripe to form a protective layer, the regions being predesigned as source and drain regions; forming recrystallized semiconductor spacers at two sides of the dielectric stripe uncovered by the protective layer, and forming recrystallized semiconductor blocks on regions covered by the protective layer; removing the dielectric stripe between the spacers so that the spacers can be formed as fin bodies..
03/06/14
20140065774
Embedded planar source/drain stressors for a finfet including a plurality of fins
Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed.
03/06/14
20140061820
Bulk finfet with controlled fin height and high-k liner
A method of forming a semiconductor device that includes forming a material stack on a semiconductor substrate, the material stack including a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, wherein the second dielectric layer is a high-k dielectric. Openings are formed through the material stack to expose a surface of the semiconductor substrate.
03/06/14
20140061817
Hybrid gate process for fabricating finfet device
Provided is a method of fabricating a semiconductor device that includes forming first and second fins over first and second regions of a substrate, forming first and second gate structures over the first and second fins, the first and second gate structures including first and second poly gates, forming an inter-level dielectric (ild) over the substrate, performing a chemical mechanical polishing on the ild to expose the first and second poly gates, forming a mask to protect the first poly gate of the first gate structure, removing the second poly gate thereby forming a first trench, removing the mask, partially removing the first poly gate thereby forming a second trench, forming a work function metal layer partially filling the first and second trenches, forming a fill metal layer filling a remainder of the first and second trenches, and removing the metal layers outside the first and second trenches.. .
03/06/14
20140061801
Fin field effect transistor layout for stress optimization
The present disclosure describes a layout for stress optimization. The layout includes a substrate, at least two fin field effect transistors (finfet) cells formed in the substrate, a finfet fin designed to cross the two finfet cells, a plurality of gates formed on the substrate, and an isolation unit formed between the first finfet cell and the second finfet cell.
03/06/14
20140061796
Techniques for metal gate workfunction engineering to enable multiple threshold voltage finfet devices
Techniques are provided for gate work function engineering in fin fet devices using a work function setting material an amount of which is provided proportional to fin pitch. In one aspect, a fin fet device is provided.
03/06/14
20140061794
Finfet with self-aligned punchthrough stopper
A finfet with self-aligned punchthrough stopper and methods of manufacture are disclosed. The method includes forming spacers on sidewalls of a gate structure and fin structures of a finfet device.
03/06/14
20140061793
Sublithographic width finfet employing solid phase epitaxy
A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure.
03/06/14
20140061744
Finfet circuit
A capacitor includes a semiconductor substrate. The capacitor also includes a first terminal having a fin disposed on a surface of the semiconductor substrate.
03/06/14
20140061734
Finfet with reduced parasitic capacitance
A gate dielectric and a gate electrode are formed over a plurality of semiconductor fins. An inner gate spacer is formed and source/drain extension regions are epitaxially formed on physically exposed surface of the semiconductor fins as discrete components that are not merged.
03/06/14
20140061728
Gate biasing electrodes for fet sensors
A fet sensor with a gate biasing electrode is disclosed in one embodiment. In another embodiment, a process for forming a finfet sensor with a polysilicon gate biasing electrode is disclosed.
02/27/14
20140054723
Isolation structures for finfet semiconductor devices
One illustrative device disclosed herein includes a plurality of fins separated by a trench formed in a semiconducting substrate, a first layer of insulating material positioned in the trench, the first layer of insulating material having an upper surface that is below an upper surface of the substrate, an isolation layer positioned within the trench above the first layer of insulating material, the isolation layer having an upper surface that is below the upper surface of the substrate, a second layer of insulating material positioned within the trench above the isolation layer, the second layer of insulating material having an upper surface that is below the upper surface of the substrate, and a gate structure positioned above the second layer of insulating material.. .
02/27/14
20140054722
Finfet cell architecture with power traces
A finfet block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates.
02/27/14
20140054706
Multi-fin finfet device including epitaxial growth barrier on outside surfaces of outermost fins and related methods
A multi-fin finfet device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof.
02/27/14
20140054705
Silicon germanium channel with silicon buffer regions for fin field effect transistor device
A fin field effect transistor (finfet) device includes a substrate; first and second source/drain regions located on the substrate; and a fin located on the substrate between the first and second source/drain regions. The fin includes a silicon germanium channel region and first and second silicon buffer regions located in the fin adjacent to and on either side of the silicon germanium channel region.
02/27/14
20140054650
Method for increasing fin density
The present disclosure is directed to a method of manufacturing a finfet structure in which at least one initial set of fin structures is formed by photolithographic processes, followed by forming an additional fin structure by epitaxial growth of a semiconductor material between the initial set of fin structures. The method allows for formation of finfet structures having increased fin density..
02/27/14
20140054648
Needle-shaped profile finfet device
Structures and methods are presented relating to formation of finfet semiconducting devices. A finfet device is presented comprising fin(s) formed on a substrate, wherein the fin(s) has a needle-shaped profile.
02/27/14
20140054547
Device with strained layer for quantum well confinement and method for manufacturing thereof
The disclosed technology relates to transistors having a strained quantum well for carrier confinement, and a method for manufacturing thereof. In one aspect, a finfet or a planar fet device comprises a semiconductor substrate, a strain-relaxed buffer layer comprising ge formed on the semiconductor substrate, a channel layer formed on the strain-relaxed buffer layer, and a strained quantum barrier layer comprising sige interposed between and in contact with the strain-relaxed buffer layer and the channel layer.
02/20/14
20140050007
Finfet based one-time programmable device
According to one embodiment, a one-time programmable (otp) device comprises a memory finfet in parallel with a sensing finfet. The memory finfet and the sensing finfet share a common source region, a common drain region, and a common channel region.
02/20/14
20140048881
Method of manufacturing a body-contacted soi finfet
A semiconductor structure including a body-contacted finfet device and methods form manufacturing the same. The method may include forming one or more semiconductor fins on a soi substrate, forming a semiconductive body contact region connected to the bottom of the fin(s) in the buried insulator region, forming a sacrificial gate structure over the body region of the fin(s), forming a source region on one end of the fin(s), forming a drain region on the opposite end of the fin(s), replacing the sacrificial gate structure with a metal gate, and forming electrical contacts to the source, drain, metal gate, and body contact region.
02/13/14
20140042556
Fin field effect transistor devices with self-aligned source and drain regions
Improved fin field effect transistor (finfet) devices and methods for the fabrication thereof are provided. In one aspect, a field effect transistor device is provided.
02/13/14
20140042551
Sram integrated circuits with buried saddle-shaped finfet and methods for their fabrication
Sram ics and methods for their fabrication are provided. One method includes depositing photoresist on a first oxide layer overlying a silicon substrate, forming a pattern of locations, using said photoresist, for the formation of two inverters, each having a pull up transistor, a pull down transistor, and a pass gate transistor on said oxide layer.
02/13/14
20140042547
High density bulk fin capacitor
A high density bulk fin capacitor is disclosed. Fin capacitors are formed near finfets by further etching the fin capacitors to provide more surface area, resulting in increased capacitance density.
02/06/14
20140038402
Dual work function finfet structures and methods for fabricating the same
A method for fabricating a dual-workfunction finfet structure includes depositing a first workfunction material in a layer in a plurality of trenches of the finfet structure, depositing a low-resistance material layer over the first workfunction material layer, and etching the low-resistance material layer and the first workfunction material layer from a portion of the finfet structure. The method further includes depositing a second workfunction material in a layer in a plurality of trenches of the portion and depositing a stress material layer over the second workfunction material layer..
02/06/14
20140038369
Method of forming fin-field effect transistor (finfet) structure
Various embodiments include methods of forming semiconductor structures. In one embodiment, a method includes: providing a precursor structure including a substrate and a set of fins overlying the substrate; forming a dummy epitaxy between the fins in the set of fins; masking a first group of fins in the set of fins and the dummy epitaxy between the first group of fins in the set of fins; removing the dummy epitaxy to expose a second group of the fins; forming a first in-situ doped epitaxy between the exposed fins; masking the second group of fins in the set of fins and the in-situ doped epitaxy between the second group of fins in the set of fins; unmasking the first group of fins; removing the dummy epitaxy layer between the first group of fins to expose of the first group of fins; and forming a second in-situ doped epitaxy between the exposed fins..
02/06/14
20140035057
Integrated circuits with aligned (100) nmos and (110) pmos finfet sidewall channels
An integrated circuit device that includes a plurality of multiple gate finfets (mugfets) is disclosed. Fins of different crystal orientations for pmos and nmos mugfets are formed through amorphization and crystal regrowth on a direct silicon bonded (dsb) hybrid orientation technology (hot) substrate.
02/06/14
20140035053
Finfet cell architecture with insulator structure
A finfet block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets.
02/06/14
20140035043
Finfets with multiple fin heights
An integrated circuit structure includes a semiconductor substrate, and a finfet over the semiconductor substrate. The finfet includes a semiconductor fin; a gate dielectric on a top surface and sidewalls of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region at an end of the semiconductor fin.
02/06/14
20140035008
Cmos with channel p-finfet and channel n-finfet having different crystalline orientations and parallel fins
An integrated circuit includes at least one single-crystal fin having a first crystal orientation. The integrated circuit also includes at least one single-crystal fin having a second crystal orientation.
01/30/14
20140030876
Methods for fabricating high carrier mobility finfet structures
A method for fabricating an integrated circuit having a finfet structure includes providing a semiconductor substrate comprising silicon and a high carrier mobility material, forming one or more fin structures on the semiconductor substrate, and subjecting the substrate to a condensation process for the condensation of the high carrier mobility material. The condensation process results in the formation of condensed fin structures formed substantially entirely of the high carrier mobility material and a layer of silicon oxide formed over the condensed fin structures.
01/30/14
20140030864
Method of edram dt strap formation in finfet device structure
The specification and drawings present a new method, device and computer/software related product (e.g., a computer readable memory) are presented for realizing edram strap formation in fin fet device structures. Semiconductor on insulator (soi) substrate comprising at least an insulator layer between a first semiconductor layer and a second semiconductor layer is provided.
01/30/14
20140027863
Merged fin finfet with (100) sidewall surfaces and method of making same
A merged fin finfet and method of fabrication. The finfet includes: two or more single-crystal semiconductor fins on a top surface of an insulating layer on semiconductor substrate, each fin of the two or more fins having a central region between and abutting first and second end regions and opposite sides, top surfaces and sidewalls of the two or more fins are (100) surfaces and the longitudinal axes of the two or more fins aligned with a [100] direction; a gate dielectric layer on each fin of the two or more fins; an electrically conductive gate over the gate dielectric layer over the central region of each fin of the of two or more fins; and a merged source/drain comprising an a continuous layer of epitaxial semiconductor material on ends of each fin of the two or more fins, the ends on a same side of the conductive gate..
01/30/14
20140027855
Nanowire fet and finfet hybrid technology
Hybrid nanowire fet and finfet devices and methods for fabrication thereof are provided. In one aspect, a method for fabricating a cmos circuit having a nanowire fet and a finfet includes the following steps.
01/30/14
20140027831
Method of edram dt strap formation in finfet device structure
The specification and drawings present a new method, device and computer/software related product (e.g., a computer readable memory) are presented for realizing edram strap formation in fin fet device structures. Semiconductor on insulator (soi) substrate comprising at least an insulator layer between a first semiconductor layer and a second semiconductor layer is provided.
01/30/14
20140027816
High mobility strained channels for fin-based transistors
Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., finfets such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (sige) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used.
01/30/14
20140027058
Cmos with channel p-finfet and channel n-finfet having different crystalline orientations and parallel fins
An integrated circuit fabrication apparatus is configured to fabricate an integrated circuit with at least one p-finfet device and at least one n-finfet device. A bonding control processor is configured to bond a first silicon layer having a first crystalline orientation to a second silicon layer having a second crystalline orientation that is different from the first crystalline orientation.
01/23/14
20140024198
Post-gate isolation area formation for fin field effect transistor device
A method for fin field effect transistor (finfet) device formation includes forming a plurality of fins on a substrate; forming a gate region over the plurality of fins; and forming isolation areas for the finfet device after formation of the gate region, wherein forming the isolation areas for the finfet device comprises performing one of oxidation or removal of a subset of the plurality of fins.. .
01/16/14
20140015055
Finfet structures and methods for fabricating the same
A method is disclosed for fabricating an integrated circuit in a replacement-gate process flow utilizing a dummy-gate structure overlying a plurality of fin structures. The method includes removing the dummy-gate structure to form a first void space, depositing a shaper material to fill the first void space, removing a portion of the plurality of fin structures to form a second void space, epitaxially growing a high carrier mobility material to fill the second void space, removing the shaper material to form a third void space, and depositing a replacement metal gate material to fill the third void space..
01/16/14
20140015048
Finfet with trench field plate
An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, a trench formed in the pad layer, the trench extending through an interface of the body portion and the drift region portion, a gate formed in the trench and over a top surface of the pad layer along the interface of the body portion and the drift region portion, an oxide formed in the trench on opposing sides of the gate, and a field plate embedded in the oxide on each of the opposing sides of the gate.. .
01/16/14
20140015015
Finfet device with a graphene gate electrode and methods of forming same
One illustrative device disclosed herein includes at least one fin comprised of a semiconducting material, a layer of gate insulation material positioned adjacent an outer surface of the fin, a gate electrode comprised of graphene positioned on the layer of gate insulation material around at least a portion of the fin, and an insulating material formed on the gate electrode.. .


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Finfet topics: Semiconductor, Semiconductor Substrate, Integrated Circuit, Semiconductor Material, Field Effect Transistor, Semiconductor Device, Semiconductor Devices, Finfet Structure, Semiconductor Wafer, Implantation, Leakage Current, Memory Cell, Crystallin, Amorphous Semiconductor, Transistors

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