|| List of recent Finfet Structure-related patents
|Method for increasing fin density|
The present disclosure is directed to a method of manufacturing a finfet structure in which at least one initial set of fin structures is formed by photolithographic processes, followed by forming an additional fin structure by epitaxial growth of a semiconductor material between the initial set of fin structures. The method allows for formation of finfet structures having increased fin density..
|Dual work function finfet structures and methods for fabricating the same|
A method for fabricating a dual-workfunction finfet structure includes depositing a first workfunction material in a layer in a plurality of trenches of the finfet structure, depositing a low-resistance material layer over the first workfunction material layer, and etching the low-resistance material layer and the first workfunction material layer from a portion of the finfet structure. The method further includes depositing a second workfunction material in a layer in a plurality of trenches of the portion and depositing a stress material layer over the second workfunction material layer..
|Methods for fabricating high carrier mobility finfet structures|
A method for fabricating an integrated circuit having a finfet structure includes providing a semiconductor substrate comprising silicon and a high carrier mobility material, forming one or more fin structures on the semiconductor substrate, and subjecting the substrate to a condensation process for the condensation of the high carrier mobility material. The condensation process results in the formation of condensed fin structures formed substantially entirely of the high carrier mobility material and a layer of silicon oxide formed over the condensed fin structures.
|Finfet structures and methods for fabricating the same|
A method is disclosed for fabricating an integrated circuit in a replacement-gate process flow utilizing a dummy-gate structure overlying a plurality of fin structures. The method includes removing the dummy-gate structure to form a first void space, depositing a shaper material to fill the first void space, removing a portion of the plurality of fin structures to form a second void space, epitaxially growing a high carrier mobility material to fill the second void space, removing the shaper material to form a third void space, and depositing a replacement metal gate material to fill the third void space..
|Finfet structure with multiple workfunctions and method for fabricating the same|
A method for fabricating a multiple-workfunction finfet structure includes depositing a first workfunction material in a layer in a plurality of trenches of the finfet structure and etching the first workfunction material layer so as to completely remove the first workfunction material layer from all but a first trench of the plurality of trenches. Further, the method includes depositing a second workfunction material in a layer in the plurality of trenches and etching the second workfunction material layer so as to completely remove the second workfunction material layer from all but a second trench of the plurality of trenches.
|Plural differential pair employing finfet structure|
A plural differential pair may include a first semiconductor fin having first and second drain areas. First and second body areas may be disposed on the fin between the first and second drain areas.
|Methods for manufacturing metal gates|
Provided are methods for making metal gates suitable for finfet structures. The methods described herein generally involve forming a high-k dielectric material on a semiconductor substrate; depositing a high-k dielectric cap layer over the high-k dielectric material; depositing a pmos work function layer having a positive work function value; depositing an nmos work function layer; depositing an nmos work function cap layer over the nmos work function layer; removing at least a portion of the pmos work function layer or at least a portion of the nmos work function layer; and depositing a fill layer.
|Dummy finfet structure and method of making same|
A finfet device may include a dummy finfet structure laterally adjacent an active finfet structure to reduce stress imbalance and the effects of stress imbalance on the active finfet structure. The finfet device comprises an active finfet comprising a plurality of semiconductor fins, and a dummy finfet comprising a plurality of semiconductor fins.
|Semiconductor devices and manufacturing and design methods thereof|
Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active finfet disposed over a workpiece comprising a first semiconductive material, the active finfet comprising a first fin.
|Replacement-gate finfet structure and process|
A fin field effect transistor (finfet) structure and method of making the finfet including a silicon fin that includes a channel region and source/drain (s/d) regions, formed on each end of the channel region, where an entire bottom surface of the channel region contacts a top surface of a lower insulator and bottom surfaces of the s/d regions contact first portions of top surfaces of a lower silicon germanium (sige) layer. The finfet structure also includes extrinsic s/d regions that contact a top surface and both side surfaces of each of the s/d regions and second portions of top surfaces of the lower sige layer.
|Finfet structure with novel edge fins|
A semiconductor device including field-effect transistors (finfets) formed on a silicon substrate. The device includes a number of active areas each having a number of equally-spaced fins separated into regular fins and at least one edge fin, a gate structure over the regular fins, and a drain region as well as a source region electrically connected to the regular fins and disconnected to the at least one edge fin.
|Control fin heights in finfet structures|
A device includes a substrate, an isolation region at a top surface of the substrate, and a semiconductor fin over the isolation region. The semiconductor fin has a fin height smaller than about 400 Å, wherein the fin height is measured from a top surface of the semiconductor fin to a top surface of the isolation region.
|Finfet structure and method for making the same|
A finfet device includes a substrate, at least a first fin structure disposed on the substrate, a l-shaped insulator surrounding the first fin structure and exposing, at least partially, the sidewalls of the first fin structure, wherein the height of the l-shaped insulator is inferior to the height of the first fin structure in order to expose parts of the sidewalls surface of the first fin structure, and a gate structure disposed partially on the l-shaped insulator and partially on the first fin structure.. .
|Circuits with linear finfet structures|
A first transistor has source and drain regions within a first diffusion fin. The first diffusion fin projects from a surface of a substrate.
|Finfet structure and method to adjust threshold voltage in a finfet structure|
Finfet structures and methods of manufacturing the finfet structures are disclosed. The method includes performing an oxygen anneal process on a gate stack of a finfet structure to induce vt shift.
|Half-finfet semiconductor device and related method|
According to one embodiment, a half-finfet semiconductor device comprises a gate structure formed over a semiconductor body. The semiconductor body includes a source region comprised of a plurality of fins extending beyond a first side of the gate structure and a continuous drain region adjacent a second side of the gate structure opposite the plurality of fins.
|Method to enable compressively strained pfet channel in a finfet structure by implant and thermal diffusion|
A method of making a semiconductor device patterns a first fin in a pfet region, and patterns a second fin in an nfet region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins.
|Structure having three independent finfet transistors|
A semiconductor chip has a finfet structure with three independently controllable fets on a single fin. The three fets are connected in parallel so that current will flow between a common source and a common drain if one or more of the three independently controllable fets is turned on.
|Finfet devices and methods of manufacture|
A finfet structure and method of manufacture such structure is provided with lowered ceff and enhanced stress. The finfet structure includes a plurality of finfet structures and a stress material forming part of a gate stack and in a space between adjacent ones of the plurality of finfet structures..