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Field Effect Transistor patents



      
           
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Amplifier circuit

Device for controlling the on and off time of the metal oxide semiconductor field effect transistor (mosfet), a device…

Field effect transistor and schottky diode structures

Date/App# patent app List of recent Field Effect Transistor-related patents
07/24/14
20140206165
 Self-aligned trench mosfet and method of manufacture patent thumbnailSelf-aligned trench mosfet and method of manufacture
A trench metal-oxide-semiconductor field effect transistor (mosfet), in accordance with one embodiment, includes a drain region, a plurality of gate regions disposed above the drain region, a plurality of gate insulator regions each disposed about a periphery of a respective one of the plurality of gate regions, a plurality of source regions disposed in recessed mesas between the plurality of gate insulator regions, a plurality of body regions disposed in recessed mesas between the plurality of gate insulator regions and between the plurality of source regions and the drain region. The mosfet also includes a plurality of body contact regions disposed in the each body region adjacent the plurality of source regions, a plurality of source/body contact spacers disposed between the plurality of gate insulator regions above the recessed mesas, a source/body contact disposed above the source/body contact spacers, and a plurality of source/body contact, plugs disposed between the source/body contact spacers and coupling the source/body contact to the plurality of body contact regions and the plurality of source regions..
07/24/14
20140203876
 Amplifier circuit patent thumbnailAmplifier circuit
An amplifier circuit is described comprising a first field effect transistor comprising a first source/drain terminal coupled to a first supply terminal, a second source/drain terminal coupled to an output of the amplifier circuit and a gate terminal; a second field effect transistor comprising a first source/drain terminal coupled to an input of the amplifier circuit, a second source/drain terminal coupled to the gate terminal of the first field effect transistor and a gate terminal; a third field effect transistor comprising a first source/drain terminal coupled to a first bias current source of the amplifier circuit, a second source/drain terminal and a gate terminal coupled to its first source/drain terminal and the gate terminal of the second field effect transistor; a fourth field effect transistor comprising a first source/drain terminal coupled to a second bias current source, a second source/drain terminal coupled to a second supply terminal and a gate terminal coupled to the second source/drain terminal of the third field effect transistor; and a control circuit coupled to the gate of the fourth field effect transistor configured to control the source drain voltage of the fourth field effect transistor by means of the gate of the fourth field effect transistor to be equal to a reference voltage.. .
07/24/14
20140203856
 Device for controlling the on and off time of the metal oxide semiconductor field effect transistor (mosfet), a device spark coating the surfaces of metal workpiece incorporating the said control device and a method of coating metal surfaces using the said device patent thumbnailDevice for controlling the on and off time of the metal oxide semiconductor field effect transistor (mosfet), a device spark coating the surfaces of metal workpiece incorporating the said control device and a method of coating metal surfaces using the said device
The present invention is a device for coating surfaces of metallic work pieces with an electrically conductive material by employing short duration high current packets of pulses in which the work piece forms the cathode and the consumable coating material forms the anode, which are connected to a generator for generating pulses by charging and discharging a bank of capacitors using a mosfet. The invention is also a device for controlling the on and off time of a metal oxide semiconductor field effect transistor (mosfet).
07/24/14
20140203355
 Field effect transistor and schottky diode structures patent thumbnailField effect transistor and schottky diode structures
In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (fet) and schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench.
07/24/14
20140203324
 A strip-shaped gate-modulated tunneling field effect transistor and a preparation method thereof patent thumbnailA strip-shaped gate-modulated tunneling field effect transistor and a preparation method thereof
The present invention discloses a strip-shaped gate-modulated tunneling field effect transistor and a preparation method thereof, belonging to a field of field effect transistor logic device and the circuit in cmos ultra large scale integrated circuit (ulsi). The tunneling field effect transistor includes a control gate, a gate dielectric layer, a semiconductor substrate, a highly-doped source region and a highly-doped drain region, where the highly-doped source region and the highly-doped drain region lie on both sides of the control gate, respectively, the control gate has a strip-shaped structure with a gate length greater than a gate width, and at one side thereof is connected to the highly-doped drain region and at the other side thereof extends laterally into the highly-doped source region; a region located below the control gate is a channel region; and the gate width of the control gate is less than twice width of a source depletion layer.
07/17/14
20140199828
 Scaled equivalent oxide thickness for field effect transistor devices patent thumbnailScaled equivalent oxide thickness for field effect transistor devices
A field effect transistor device includes a first gate stack portion including a dielectric layer disposed on a substrate, a first tin layer disposed on the dielectric layer, a metallic layer disposed on the dielectric layer, and a second tin layer disposed on the metallic layer, a first source region disposed adjacent to the first gate stack portion, and a first drain region disposed adjacent to the first gate stack portion.. .
07/17/14
20140199825
 Silicon-germanium heterojunction tunnel field effect transistor and preparation method thereof patent thumbnailSilicon-germanium heterojunction tunnel field effect transistor and preparation method thereof
A silicon/germanium (sige) heterojunction tunnel field effect transistor (tfet) and a preparation method thereof are provided, in which a source region of a device is manufactured on a silicon germanium (sige) or ge region, and a drain region of the device is manufactured in a si region, thereby obtaining a high on-state current while ensuring a low off-state current. Local ge oxidization and concentration technique is used to implement a silicon germanium on insulator (sgoi) or germanium on insulator (goi) with a high ge content in some area.
07/17/14
20140199813
 Transistor with longitudinal strain in channel induced by buried stressor relaxed by implantation patent thumbnailTransistor with longitudinal strain in channel induced by buried stressor relaxed by implantation
Processes for making field effect transistors relax a buried stressor layer to induce strain in a silicon surface layer above the buried stressor layer. The buried stressor layer is relaxed and the surface layer is strained by implantation into at least the buried stressor layer, preferably on both sides of a portion of the surface layer that is to be stressed.
07/17/14
20140198423
 Current limiter circuit for control and protection of mosfet patent thumbnailCurrent limiter circuit for control and protection of mosfet
A circuit for controlling a metal oxide semiconductor field effect transistor (mosfet) to generate a dc output voltage from a dc input voltage includes a first mosfet and a second mosfet. The circuit includes a gate resistor coupled to the first mosfet.
07/17/14
20140197877
 System for a contactless control of a field effect transistor patent thumbnailSystem for a contactless control of a field effect transistor
The invention stems from the realization that it is possible to control the electric field in the gate region of a field effect transistor (mos, fet etc.) without changing the net charge of the gate electrode or without resorting to electrical conduction. According to an aspect of the invention, the electric field is changed by modifying the charge distribution within the gate electrode without materially adding or subtracting charge carriers to it or changing its net charge.
07/17/14
20140197493
Defect reduction for formation of epitaxial layer in source and drain regions
The embodiments of mechanisms for forming source/drain (s/d) regions of field effect transistors (fets) described enable forming an epitaxially grown silicon-containing layer with reduced number of particles on surface of recesses. The described mechanisms also reduce the effect of the residual particles on the epitaxial growth.
07/17/14
20140197467
High voltage junction field effect transistor structure
A jfet structure includes a first jfet having a first terminal and a second jfet neighboring with the first jfet. Both jfets commonly share the first terminal and the first terminal is between the gate of each jfet.
07/17/14
20140197466
N-channel metal-oxide field effect transistor with embedded high voltage junction gate field-effect transistor
A semiconductor device comprising a high-voltage (hv) n-type metal oxide semiconductor (nmos) embedded hv junction gate field-effect transistor (jfet) is provided. An hv nmos with embedded hv jfet may include, according to a first example embodiment, a substrate, an n-type well region disposed adjacent to the substrate, a p-type well region disposed adjacent to the n-type well region, and first and second n+ doped regions disposed adjacent to the n-type well and on opposing sides of the p-type well region.
07/17/14
20140197463
Metal-programmable integrated circuits
A metal-programmable integrated circuit may include an array of metal-programmable cells. Each cell may include multi-gate transistor structures in which multiple surfaces of a gate structure serve to control current flow through at least one channel structure.
07/17/14
20140197411
Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device
A methodology enabling the formation of steep channel profiles for devices, such as ssrw fets, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing sti regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between sti regions; forming a recess in the doped silicon wafer between the sti regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming si:c on the doped silicon wafer in the recess..
07/10/14
20140194719
Long-term implantable silicon carbide neural interface device using the electrical field effect
Field effect devices, such as capacitors and field effect transistors, are used to interact with neurons. Cubic silicon carbide is biocompatible with the neuronal environment and has the chemical and physical resilience required to withstand the body environment and does not produce toxic byproducts.
07/10/14
20140191659
Led lamp control circuit
An led lamp control circuit comprises a rectifier circuit, an led light source load, a constant current circuit, and a first temperature detect switch circuit. The led light source load comprises at least one group of leds.
07/10/14
20140191325
Fin-shaped field effect transistor (finfet) structures having multiple threshold voltages (vt) and method of forming
Various embodiments include fin-shaped field effect transistor (finfet) structures that enhance work function and threshold voltage (vt) control, along with methods of forming such structures. The finfet structures can include a p-type field effect transistor (pfet) and an n-type field effect transistor (nfet).
07/10/14
20140191318
Complementary metal oxide semiconductor field effect transistor, metal oxide semiconductor field effect transistor and manufacturing method thereof
A complementary metal oxide semiconductor field-effect transistor (mosfet) includes a substrate, a first mosfet and a second mosfet. The first mosfet is disposed on the substrate within a first transistor region and the second mosfet is disposed on the substrate within a second transistor region.
07/10/14
20140191292
Methods and systems for point of use removal of sacrificial material
A method of manufacturing a sensor, the method including forming an array of chemically-sensitive field effect transistors (chemfets), depositing a dielectric layer over the chemfets in the array, depositing a protective layer over the dielectric layer, etching the dielectric layer and the protective layer to form cavities corresponding to sensing surfaces of the chemfets, and removing the protective layer. The method further includes, etching the dielectric layer and the protective layer together to form cavities corresponding to sensing surfaces of the chemfets.
07/03/14
20140187012
Customized shield plate for a field effect transistor
A customized shield plate field effect transistor (fet) includes a semiconductor layer, a gate dielectric, a gate electrode, and at least one customized shield plate. The shield plate includes a conductive layer overlying a portion of the gate electrode, one of the gate electrode sidewalls, and a portion of the substrate adjacent to the sidewall.
07/03/14
20140187007
Mosfet including asymmetric source and drain regions
At least one drain-side surfaces of a field effect transistor (fet) structure, which can be a structure for a planar fet or a fin fet, is structurally damaged by an angled ion implantation of inert or electrically active dopants, while at least one source-side surface of the transistor is protected from implantation by a gate stack and a gate spacer. Epitaxial growth of a semiconductor material is retarded on the at least one structurally damaged drain-side surface, while epitaxial growth proceeds without retardation on the at least one source-side surface.
07/03/14
20140185167
High voltage open-drain electrostatic discharge (esd) protection device
A high voltage open-drain electrostatic discharge (esd) protection device is disclosed, which comprises a high-voltage n-channel metal oxide semiconductor field effect transistor (hv nmosfet) coupled to a high-voltage pad and a low-voltage terminal and receiving a high voltage on the high-voltage pad to operate in normal operation. The high-voltage pad and the hv nmosfet are further coupled to a high-voltage esd unit blocking the high voltage, and receiving a positive esd voltage on the high-voltage pad to bypass an esd current when an esd event is applied to the high-voltage pad.
07/03/14
20140184196
Nanoscale wires, nanoscale wire fet devices, and nanotube-electronic hybrid devices for sensing and other applications
The present invention generally relates to nanotechnology, including field effect transistors and other devices used as sensors (for example, for electrophysiological studies), nanotube structures, and applications. Certain aspects of the present invention are generally directed to transistors such as field effect transistors, and other similar devices.
07/03/14
20140183633
Semiconductor devices and methods of manufacture thereof
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes partially manufacturing a fin field effect transistor (finfet) including a semiconductor fin comprising a first semiconductive material and a second semiconductive material disposed over the first semiconductive material.
07/03/14
20140183599
Field effect transistor
Field effect transistors are provided. An active region protrudes from a substrate and a gate electrode is provided on the active region.
07/03/14
20140183453
Field effect transistor having double transition metal dichalcogenide channels
A field effect transistor (fet) includes first and second channels stacked on a substrate, the first and second channels formed of a transition metal dichalcogenide, a source electrode and a drain electrode contacting both the first channel and the second channel, each of the source electrode and the drain electrode having one end between the first channel and the second channel, and a first gate electrode corresponding to at least one of the first channel and the second channel.. .
07/03/14
20140183452
Field effect transistor with channel core modified for a backgate bias and method of fabrication
A semiconductor device includes a substrate and a source structure and a drain structure formed on the substrate. At least one nanowire structure interconnects the source structure and drain structure and serves as a channel therebetween.
07/03/14
20140183451
Field effect transistor with channel core modified to reduce leakage current and method of fabrication
A semiconductor device includes a channel structure formed on a substrate, the channel structure being formed of a semiconductor material. A gate structure covers at least a portion of the surface of the channel structure and is formed of a film of insulation material and a gate electrode.
06/26/14
20140179095
Methods and systems for controlling gate dielectric interfaces of mosfets
Embodiments provided herein describe methods and systems for forming gate dielectrics for field effect transistors. A substrate including a germanium channel and a germanium oxide layer on a surface of the germanium channel is provided.
06/26/14
20140179047
Field effect transistor-based bio-sensor
An apparatus comprises: a sensing element formed on a buried oxide layer of a substrate and providing communication between a source region and a drain region; a gate dielectric layer on the sensing element, the gate dielectric layer defining a sensing surface on the sensing element; a passive surface surrounding the sensing surface; and a compound bound to the sensing surface and not bound to the passive surface, the compound having a ligand specifically configured to preferentially bind a target molecule to be sensed. An electrolyte solution in contact with the sensing surface and the passive surface forms a top gate of the apparatus..
06/26/14
20140176135
Multiturn mri coils in combination with current mode class d amplifiers
Example systems, apparatus, and circuits described herein concern a multi-turn transmit surface coil used in parallel transmission in high field mri. One example apparatus includes a balun network that produces out-of-phase signals that are amplified to drive current-mode class-d (cmcd) field effect transistors (fets) that are connected by a coil that includes an lc (inductance-capacitance) leg.
06/26/14
20140176113
Circuit for outputting reference voltage
A circuit for outputting reference voltage includes: a detecting unit, a feedback unit and an output unit which are respectively connected with an external power source, wherein a plurality of field effect transistors (fets) are provided in the detecting unit, wherein the detecting unit is for detecting foundry corners of the fets therein, the feedback unit is for feeding back and comparing a detecting result of the detecting unit, and outputting information after feeding back and comparing, and the output unit is for outputting reference voltage corresponding to the foundry corners of the fets to an external output terminal. The reference voltage outputted by the circuit for outputting reference voltage of the present invention is capable of varying with foundry corners of the fets, and achieves compensating for foundry corners of the fets..
06/26/14
20140175564
Finfet device
A method for forming a field effect transistor device includes patterning an arrangement of fin portions on a substrate, patterning a gate stack portion over portions of the fin portions and the substrate, growing an epitaxial material from the fin portions that electrically connects portions of adjacent fin structures, and removing a portion of the gate stack portion to expose a portion of the substrate.. .
06/26/14
20140175549
Finfet device
A method for fabricating a field effect transistor device includes removing a portion of a first semiconductor layer and a first insulator layer to expose a portion of a second semiconductor layer, wherein the second semiconductor layer is disposed on a second insulator layer, the first insulator layer is disposed on the second semiconductor layer, and the first semiconductor layer is disposed on the first insulator layer, removing portions of the first semiconductor layer to form a first fin disposed on the first insulator layer and removing portions of the second semiconductor layer to form a second fin disposed on the second insulator layer, and forming a first gate stack over a portion of the first fin and forming a second gate stack over a portion of the second fin.. .
06/26/14
20140175522
Field effect transistor-based bio sensor
An apparatus comprises: a sensing element formed on a buried oxide layer of a substrate and providing communication between a source region and a drain region; a gate dielectric layer on the sensing element, the gate dielectric layer defining a sensing surface on the sensing element; a passive surface surrounding the sensing surface; and a compound bound to the sensing surface and not bound to the passive surface, the compound having a ligand specifically configured to preferentially bind a target molecule to be sensed. An electrolyte solution in contact with the sensing surface and the passive surface forms a top gate of the apparatus..
06/26/14
20140175517
Field effect transistor
A field effect transistor (fet) disclosed herein comprising a substrate, a c-doped semiconductor layer disposed on the substrate, a channel layer disposed on the c-doped semiconductor layer, and an electron supply layer disposed on the channel layer. The fet further comprises a diffusion barrier layer disposed between the c-doped semiconductor layer and the channel layer, wherein the diffusion barrier layer contacts the channel layer directly..
06/26/14
20140175509
Lattice mismatched hetero-epitaxial film
An embodiment concerns forming an epi film on a substrate where the epi film has a different lattice constant from the substrate. The epi film and substrate may include different materials to collectively form a hetero-epitaxial device having, for example, a si and/or sige substrate and a iii-v or iv film.
06/26/14
20140175451
Normally off gallium nitride field effect transistors (fet)
A heterostructure field effect transistor (hfet) gallium nitride (gan) semiconductor power device comprises a hetero-junction structure comprises a first semiconductor layer interfacing it second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2deg) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero-junction structure for controlling a current flow between the source and drain electrodes in the 2deg layer.
06/26/14
20140175376
Reduced scale resonant tunneling field effect transistor
An embodiment includes a heterojunction tunneling field effect transistor including a source, a channel, and a drain; wherein (a) the channel includes a major axis, corresponding to channel length, and a minor axis that corresponds to channel width and is orthogonal to the major axis; (b) the channel length is less than 10 nm long; (c) the source is doped with a first polarity and has a first conduction band; (d) the drain is doped with a second polarity, which is opposite the first polarity, and the drain has a second conduction band with higher energy than the first conduction band. Other embodiments are described herein..
06/19/14
20140170844
Structure and method of tinv scaling for high k metal gate technology
A complementary metal oxide semiconductor (cmos) structure including a scaled n-channel field effect transistor (nfet) and a scaled p-channel field transistor (pfet) is provided. Such a structure is provided by forming a plasma nitrided, nfet threshold voltage adjusted high k gate dielectric layer portion within an nfet gate stack, and forming at least a pfet threshold voltage adjusted high k gate dielectric layer portion within a pfet gate stack.
06/19/14
20140170842
Method for forming dummy gate
Disclosed is a method of forming a dummy gate in manufacturing a field effect transistor. The method includes a first process of exposing a workpiece having a polycrystalline silicon layer to plasma of hbr gas, and a second process of further exposing the workpiece to the plasma of hbr gas after the first process.
06/19/14
20140170840
Epitaxial formation mechanisms of source and drain regions
The embodiments of mechanisms for forming source/drain (s/d) regions of field effect transistors (fets) descried enable forming an epitaxially grown silicon-containing material without using geh4 in an etch gas mixture of an etch process for a cyclic deposition/etch (cde) process. The etch process is performed at a temperature different form the deposition process to make the etch gas more efficient.
06/19/14
20140170827
Tunneling field effect transistor (tfet) formed by asymmetric ion implantation and method of making same
An embodiment integrated circuit device and a method of making the same. The embodiment method includes forming a first nitride layer over a gate stack supported by a substrate, implanting germanium ions in the first nitride layer in a direction forming an acute angle with a top surface of the substrate, etching away germanium-implanted portions of the first nitride layer to form a first asymmetric nitride spacer confined to a first side of the gate stack, the first asymmetric nitride spacer protecting a first source/drain region of the substrate from a first ion implantation, and implanting ions in a second source/drain region of the substrate on a second side of the gate stack unprotected by the first asymmetric nitride spacer to form a first source/drain..
06/19/14
20140170826
Biaxial strained field effect transistor devices
A process for forming contacts to a field effect transistor provides edge relaxation of a buried stressor layer, inducing strain in an initially relaxed surface semiconductor layer above the buried stressor layer. A process can start with a silicon or silicon-on-insulator substrate with a buried silicon germanium layer having an appropriate thickness and germanium concentration.
06/19/14
20140170779
Coherent spin field effect transistor
A coherent spin field effect transistor is provided by depositing a ferromagnetic base like cobalt on a substrate. A magnetic oxide layer is formed on the cobalt by annealing at temperatures on the order of 1000° k to provide a few monolayer thick layer.
06/19/14
20140169062
Methods of manufacturing embedded bipolar switching resistive memory
Non linear current response circuits can be used in embedded resistive memory cell for reducing power consumption, together with improving reliability of the memory array. The non linear current response circuits can include two back to back leaky pin diodes, two parallel anti-directional pin diodes, two back to back zener-type metal oxide diodes, or ovonic switching elements, along with current limiting resistor for standby power reduction at the low voltage region.
06/19/14
20140167834
Method and apparatus improving gate oxide reliability by controlling accumulated charge
A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (soi) metal-oxide-silicon field effect transistor (mosfet) devices using accumulated charge control (acc) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in soi mosfets, thereby yielding improvements in fet performance characteristics.
06/19/14
20140167187
N metal for finfet
An n work function metal for a gate stack of a field effect transistor (finfet) and method of forming the same are provided. An embodiment finfet includes a fin supported by a semiconductor substrate, the fin extending between a source and a drain and having a channel region, and a gate stack formed over the channel region of the fin, the gate stack including an n work function metal layer comprising an oxidation layer on opposing sides of a tantalum aluminide carbide (taalc) layer..
06/19/14
20140167186
Semiconductor device structures including strained transistor channels
The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in pmos field effect transistors, or tensile strain is wanted in transistor channels, as in nmos field effect transistors, to enhance carrier mobility and transistor speed.
06/19/14
20140167175
Transistor and method of fabricating the same
A field effect transistor is provided. The transistor may include a source electrode and a drain electrode provided spaced apart from each other on a substrate and a ‘+’-shaped gate electrode provided on a portion of the substrate located between the source and drain electrodes..
06/19/14
20140167146
Tunneling field effect transistor and fabrication method thereof
A tunneling field effect transistor (fet) and a method of fabricating the same are provided. The tunneling fet includes a first electrode formed on a substrate, a second electrode disposed over the first electrode with respect to the substrate, a channel layer which connects the first electrode and the second electrode, and a plurality of third electrodes formed on sidewalls of the channel layer, wherein the channel layer is higher than the third electrodes in the criteria of the substrate..
06/19/14
20140167134
Self-aligned vertical nonvolatile semiconductor memory device
The present invention belongs to the technical field of semiconductor memory devices and specifically relates to a self-aligned vertical nonvolatile semiconductor memory device, including: a semiconductor substrate, a drain region of a first doping type, two source regions of a second doping type, a stacked gate used to capture electrons; wherein the drain region, the two source regions and the stacked gate form two tunneling field effect transistors (tfets) sharing one gate and one drain, the drain region current of each of the tfet is affected by the quantity and distribution of the charges in the stacked gate used to capture electrons, the drain is buried in the semiconductor substrate, the source regions above the drain region are separated from the drain through a channel and separated form each other through a region of the first doping type. The semiconductor memory device of the present invention features small unit area and simple manufacturing process.
06/19/14
20140167113
Gallium nitride based semiconductor devices and methods of manufacturing the same
Gallium nitride (gan) based semiconductor devices and methods of manufacturing the same. The gan-based semiconductor device may include a heat dissipation substrate (that is, a thermal conductive substrate); a gan-based multi-layer arranged on the heat dissipation substrate and having n-face polarity; and a heterostructure field effect transistor (hfet) or a schottky electrode arranged on the gan-based multi-layer.
06/19/14
20140167111
Transistor and method of fabricating the same
A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion.
06/19/14
20140166983
Accurate control of distance between suspended semiconductor nanowires and substrate surface
A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer.
06/19/14
20140166982
Accurate control of distance between suspended semiconductor nanowires and substrate surface
A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer.
06/19/14
20140165725
Analysis circuit for field effect transistors having a displaceable gate structure
An analysis circuit for a field effect transistor having a displaceable gate structure, includes a measurement circuit coupled between a supply voltage connection of the analysis circuit and a drain connection of the field effect transistor and configured to output a measurement signal that is dependent on the current strength of a current flowing through the field effect transistor to a measurement connection.. .
06/12/14
20140164795
Bridge circuit for ethernet powered device
A network powered device includes field effect transistors connected as bridge circuit. The bridge circuit includes control circuitry to enable the fets based on completion of a powered device detection sequence performed by power sourcing equipment coupled to the device via an ethernet link..
06/12/14
20140162447
Finfet hybrid full metal gate with borderless contacts
A method for fabricating a field effect transistor device includes patterning a fin on substrate, patterning a gate stack over a portion of the fin and a portion of an insulator layer arranged on the substrate, forming a protective barrier over the gate stack, a portion of the fin and a portion of the insulator layer, the protective barrier enveloping the gate stack, depositing a second insulator layer over portions of the fin and the protective barrier, performing a first etching process to selectively remove portions of the second insulator layer to define cavities that expose portions of source and drain regions of the fin without appreciably removing the protective barrier, and depositing a conductive material in the cavities.. .
06/12/14
20140159205
Low off-state leakage current field effect transistors
A method is presented to decrease the off-state leakage current of the field effect transistors (fets). The presented method comprises of the placement of dopants underneath or anywhere adjacent to the channel which causes an increase in the band barrier at the source edge of the semiconductor of gate region at the off state, providing for less leakage current.
06/12/14
20140159163
Bulk finfet with super steep retrograde well
A method for forming a fin transistor in a bulk substrate includes forming a super steep retrograde well (ssrw) on a bulk substrate. The well includes a doped portion of a first conductivity type dopant formed below an undoped layer.
06/12/14
20140159162
Bulk finfet with super steep retrograde well
A method for forming a fin transistor in a bulk substrate includes forming a super steep retrograde well (ssrw) on a bulk substrate. The well includes a doped portion of a first conductivity type dopant formed below an undoped layer.
06/12/14
20140159161
Measurement of cmos device channel strain by x-ray diffraction
A direct measurement of lattice spacing by x-ray diffraction is performed on a periodic array of unit structures provided on a substrate including semiconductor devices. Each unit structure includes a single crystalline strained material region and at least one stress-generating material region.
06/12/14
20140159142
Recessed channel insulated-gate field effect transistor with self-aligned gate and increased channel length
A metal-oxide-semiconductor transistor (mos) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure.
06/12/14
20140159141
Insulating gate field effect transistor device and method for providing the same
An insulating gate field effect transistor (igfet) device includes a semiconductor body and a gate oxide. The semiconductor body includes a first well region doped with a first type of dopant and a second well region that is doped with an oppositely charged second type of dopant and is located within the first well region.
06/12/14
20140159122
Semiconductor pressure sensor and fabrication method thereof
At a pressure sensor region, a pressure sensor including a fixed electrode, a void and a movable electrode is formed. At a cmos region, a memory cell transistor and a field effect transistor are formed.
06/12/14
20140159050
Field effect transistor and method of fabricating the same
A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a Γ-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the Γ-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode..
06/12/14
20140158990
Tunneling field effect transistor (tfet) with ultra shallow pockets formed by asymmetric ion implantation and method of making same
An embodiment integrated circuit device and a method of making the same. The embodiment integrated circuit includes a substrate supporting a source with a first doping type and a drain with a second doping type on opposing sides of a channel region in the substrate, and a pocket disposed in the channel region, the pocket having the second doping type and spaced apart from the drain between about 2 nm and about 15 nm.
06/12/14
20140158985
Semiconductor heterostructure field effect transistor and method for making thereof
A heterostructure field effect transistor is provided comprising a semiconductor wire comprising in its longitudinal direction a source and a drain region, a channel region in between the source and drain region and in its transversal direction for the source region, a source core region and a source shell region disposed around the source core region, the source shell region having in its transversal direction for the drain region, a drain core region and a drain shell region disposed around the drain core region, the drain shell region having in its transversal direction for the channel region, a channel core region and a channel shell region disposed around the channel core region; wherein the thickness of the channel shell region is smaller than the thickness of the source shell region and is smaller than the thickness of the drain shell region.. .


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Field Effect Transistor topics: Field Effect Transistor, Semiconductor, Semiconductor Device, Transistors, Integrated Circuit, Conductive Layer, Microprocessor, Disconnect, Leakage Current

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