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Field Effect Transistor patents



      
           
This page is updated frequently with new Field Effect Transistor-related patent applications. Subscribe to the Field Effect Transistor RSS feed to automatically get the update: related Field RSS feeds. RSS updates for this page: Field Effect Transistor RSS RSS


Non-volatile memory system with reset control mechanism and method of operation thereof

Low-dropout regulator and method for voltage regulation

Changing effective work function using ion implantation during dual work function metal gate integration

Date/App# patent app List of recent Field Effect Transistor-related patents
08/14/14
20140227850
 Finfet/tri-gate channel doping for multiple threshold voltage tuning patent thumbnailFinfet/tri-gate channel doping for multiple threshold voltage tuning
An embodiment method of controlling threshold voltages in a fin field effect transistor (finfet) includes forming a dummy gate over a central portion of a fin, the central portion of the fin disposed between exterior portions of the fin unprotected by the dummy gate, removing the exterior portions of the fin and replacing the exterior portions of the fin with an epitaxially-grown silicon-containing material, applying a spin-on resist over the dummy gate and the epitaxially-grown silicon-containing material and then removing the spin-on resist over the hard mask of the dummy gate, etching away the hard mask and a polysilicon of the dummy gate to expose a gate oxide of the dummy gate, the gate oxide disposed over the central portion of the fin, and implanting ions into the central portion of the fin through the gate oxide disposed over the central portion of the fin.. .
08/14/14
20140226390
 Non-volatile memory system with reset control mechanism and method of operation thereof patent thumbnailNon-volatile memory system with reset control mechanism and method of operation thereof
A method of operation of a non-volatile memory system includes: providing a control field effect transistor having a source electrode and a body-tie electrode; coupling a resistive storage element to the source electrode; and opening a well switch coupled to the body-tie electrode for increasing a well voltage and resetting the resistive storage element by the source electrode floating on the well voltage.. .
08/14/14
20140225580
 Low-dropout regulator and method for voltage regulation patent thumbnailLow-dropout regulator and method for voltage regulation
A low-dropout regulator (1) comprises a differential amplifier (3) with a reference input (5) for applying a reference voltage (vin), a feedback input (7) and an amplifier output (9). An output transistor (11) has a control connection (13) connected to the amplifier output (9), and a control section connected between a first supply potential terminal (vdd) and a voltage output (15) of the low-dropout regulator (1).
08/14/14
20140225199
 Changing effective work function using ion implantation during dual work function metal gate integration patent thumbnailChanging effective work function using ion implantation during dual work function metal gate integration
Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (fet) region and a second-type fet region; forming a metal layer having a first effective work function compatible for a first-type fet over the first-type fet region and the second-type fet region; and changing the first effective work function to a second, different effective work function over the second-type fet region by implanting a species into the metal layer over the second-type fet region..
08/14/14
20140225193
 Carbon nanostructure device fabrication utilizing protect layers patent thumbnailCarbon nanostructure device fabrication utilizing protect layers
Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing.. .
08/14/14
20140225186
 Lateral extended drain metal oxide semiconductor field effect transistor (ledmosfet) with tapered airgap field plates patent thumbnailLateral extended drain metal oxide semiconductor field effect transistor (ledmosfet) with tapered airgap field plates
Disclosed are embodiments of a lateral, extended drain, metal oxide semiconductor, field effect transistor (ledmosfet) having tapered dielectric field plates positioned laterally between conductive field plates and opposing sides of a drain drift region of the ledmosfet. Each dielectric field plate comprises, in whole or in part, an airgap.
08/14/14
20140225175
 Semiconductor constructions, dram arrays, and methods of forming semiconductor constructions patent thumbnailSemiconductor constructions, dram arrays, and methods of forming semiconductor constructions
The invention includes methods for utilizing partial silicon-on-insulator (soi) technology in combination with fin field effect transistor (finfet) technology to form transistors particularly suitable for utilization in dynamic random access memory (dram) arrays. The invention also includes dram arrays having low rates of refresh.
08/14/14
20140225166
 Biological and chemical sensors patent thumbnailBiological and chemical sensors
Device structures, fabrication methods, and design structures for a biological and chemical sensor used to detect a property of a substance. The device structure includes a drain and a source of a field effect transistor formed at a frontside of a substrate.
08/07/14
20140221052
 Switch design for light up phone cases patent thumbnailSwitch design for light up phone cases
A mobile phone call flashing apparatus equipped with an electronic switch relates to the field of electronic products and comprises an electric power supply, a capacitor, a first resistance, a second resistance, a switch, a first integrated block, a second integrated block, a conductor field effect transistor, and a first light-emitting diode through a sixth light-emitting diode. It can make up the deficiency in the prior art, allow users to be able to control the light-emitting status at the time of incoming calls or messages autonomously, greatly satisfy modern people's psychological needs in their pursuit of fashionable visual effects, and enjoy extensive applicability and market prospects..
08/07/14
20140220909
 High freuency semiconductor switch and wireless device patent thumbnailHigh freuency semiconductor switch and wireless device
A high frequency semiconductor switch has a first terminal, second terminals, a first through fet group, second through fet groups and a shunt fet group. The first through fet group has first field effect transistors connected serially with each other.
08/07/14
20140220756
Methods of forming semiconductor devices by forming a semiconductor layer above source/drain regions prior to removing a gate cap layer
One example of a method disclosed herein for forming a gate electrode in a field effect transistor comprises forming a gate structure above a semiconductor substrate, the gate structure comprising a gate electrode and a gate cap layer positioned above the gate electrode, forming sidewall spacers adjacent the sidewalls of the gate structure, forming a semiconductor layer above portions of the source/drain regions not covered by the gate structure and the sidewall spacers and performing at least one etching process to remove the gate cap layer from above the gate electrode and to remove at least a portion of the semiconductor layer.. .
08/07/14
20140220755
Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor.
08/07/14
20140220748
Method for fabricating complementary tunneling field effect transistor based on standard cmos ic process
Disclosed herein is a method for fabricating a complementary tunneling field effect transistor based on a standard cmos ic process, which belongs to the field of logic devices and circuits of field effect transistors in ultra large scaled integrated (ulsi) circuits. In the method, an intrinsic channel and body region of a tfet are formed by means of complementary p-well and n-well masks in the standard cmos ic process to form a well doping, a channel doping and a threshold adjustment by implantation.
08/07/14
20140218098
Rf switches having increased voltage swing uniformity
Radio-frequency (rf) switch circuits are disclosed providing uniform voltage swing across a transmit switch for improved device performance. A switching circuit includes a switch having field effect transistors (fets) defining an rf signal path between the input port and the output port, the switch configured to be capable of being in a first state corresponding to the input and output ports being electrically connected so as to allow passage of the rf signal therebetween, and a second state corresponding to the input and output ports being electrically isolated.
08/07/14
20140217497
Mosfet with curved trench feature coupling termination trench to active trench
A metal oxide semiconductor field effect transistor (mosfet) in and on a semiconductor surface provides a drift region of a first conductivity type. A plurality of active area trenches in the drift region, and first and second termination trenches are each parallel to and together sandwiching the active area trenches.
08/07/14
20140217329
Diketopyrrolopyrrole oligomers and compositions, comprising diketopyrrolopyrrole oligomers
The present invention relates to compositions, comprising (a) a compound of the formula (i), and (b) a polymeric material, to specific oligomers of the formula i, and their use as organic semiconductor in organic devices, especially in organic photovoltaics (solar cells) and photodiodes, or in a device containing a diode and/or an organic field effect transistor. High efficiency of energy conversion, excellent field-effect mobility, good on/off current ratios and/or excellent stability can be observed, when the compositions, or oligomers according to the invention are used in organic field effect transistors, organic photovoltaics (solar cells) and photodiodes..
07/31/14
20140213036
Forming structures on resistive substrates
A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.. .
07/31/14
20140213026
Trench metal oxide semiconductor field effect transistor with embedded schottky rectifier using reduced masks process
A trench mosfet with embedded schottky rectifier having at least one anti-punch through implant region using reduced masks process is disclosed for avalanche capability enhancement and cost reduction. The source regions have a higher doping concentration and a greater junction depth along sidewalls of the trenched source-body contacts than along adjacent channel regions near the gate trenches..
07/31/14
20140211354
Wireless communication base station with current limiting capability
A wireless communication system base station (20) includes a base station transceiver (26) that has at least one operative component (32) for facilitating wireless communications. A current limiting device (36) includes at least one field effect transistor for selectively controlling current flow to a capacitive stability device (34) associated with at least one of the operative components (32).
07/31/14
20140210009
High voltage finfet structure
Methods for forming fin-shaped field effect transistors (finfets) capable of withstanding high voltage applications and the resulting devices are disclosed. Embodiments include forming a source and a drain on a substrate, forming a thin body (fin) on the substrate and connecting the source and the drain, forming a gate over top and side surfaces of a first part of the fin, thereby defining a drain-side fin region of the fin between the gate and the drain, and forming a shielding region over top and side surfaces of a second part of the fin in the drain-side fin region..
07/31/14
20140209982
Self-aligned well structures for low-noise chemical sensors
In one implementation, a chemical detection device is described. The device includes a chemically-sensitive field effect transistor including a floating gate conductor coupled to a gate dielectric and having an upper surface, and a sensing material on the upper surface.
07/31/14
20140209848
Memory constructions
Some embodiments include memory constructions having a plurality of bands between top and bottom electrically conductive materials. The bands include chalcogenide bands alternating with non-chalcogenide bands.
07/24/14
20140206165
Self-aligned trench mosfet and method of manufacture
A trench metal-oxide-semiconductor field effect transistor (mosfet), in accordance with one embodiment, includes a drain region, a plurality of gate regions disposed above the drain region, a plurality of gate insulator regions each disposed about a periphery of a respective one of the plurality of gate regions, a plurality of source regions disposed in recessed mesas between the plurality of gate insulator regions, a plurality of body regions disposed in recessed mesas between the plurality of gate insulator regions and between the plurality of source regions and the drain region. The mosfet also includes a plurality of body contact regions disposed in the each body region adjacent the plurality of source regions, a plurality of source/body contact spacers disposed between the plurality of gate insulator regions above the recessed mesas, a source/body contact disposed above the source/body contact spacers, and a plurality of source/body contact, plugs disposed between the source/body contact spacers and coupling the source/body contact to the plurality of body contact regions and the plurality of source regions..
07/24/14
20140203876
Amplifier circuit
An amplifier circuit is described comprising a first field effect transistor comprising a first source/drain terminal coupled to a first supply terminal, a second source/drain terminal coupled to an output of the amplifier circuit and a gate terminal; a second field effect transistor comprising a first source/drain terminal coupled to an input of the amplifier circuit, a second source/drain terminal coupled to the gate terminal of the first field effect transistor and a gate terminal; a third field effect transistor comprising a first source/drain terminal coupled to a first bias current source of the amplifier circuit, a second source/drain terminal and a gate terminal coupled to its first source/drain terminal and the gate terminal of the second field effect transistor; a fourth field effect transistor comprising a first source/drain terminal coupled to a second bias current source, a second source/drain terminal coupled to a second supply terminal and a gate terminal coupled to the second source/drain terminal of the third field effect transistor; and a control circuit coupled to the gate of the fourth field effect transistor configured to control the source drain voltage of the fourth field effect transistor by means of the gate of the fourth field effect transistor to be equal to a reference voltage.. .
07/24/14
20140203856
Device for controlling the on and off time of the metal oxide semiconductor field effect transistor (mosfet), a device spark coating the surfaces of metal workpiece incorporating the said control device and a method of coating metal surfaces using the said device
The present invention is a device for coating surfaces of metallic work pieces with an electrically conductive material by employing short duration high current packets of pulses in which the work piece forms the cathode and the consumable coating material forms the anode, which are connected to a generator for generating pulses by charging and discharging a bank of capacitors using a mosfet. The invention is also a device for controlling the on and off time of a metal oxide semiconductor field effect transistor (mosfet).
07/24/14
20140203355
Field effect transistor and schottky diode structures
In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (fet) and schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench.
07/24/14
20140203324
A strip-shaped gate-modulated tunneling field effect transistor and a preparation method thereof
The present invention discloses a strip-shaped gate-modulated tunneling field effect transistor and a preparation method thereof, belonging to a field of field effect transistor logic device and the circuit in cmos ultra large scale integrated circuit (ulsi). The tunneling field effect transistor includes a control gate, a gate dielectric layer, a semiconductor substrate, a highly-doped source region and a highly-doped drain region, where the highly-doped source region and the highly-doped drain region lie on both sides of the control gate, respectively, the control gate has a strip-shaped structure with a gate length greater than a gate width, and at one side thereof is connected to the highly-doped drain region and at the other side thereof extends laterally into the highly-doped source region; a region located below the control gate is a channel region; and the gate width of the control gate is less than twice width of a source depletion layer.
07/17/14
20140199828
Scaled equivalent oxide thickness for field effect transistor devices
A field effect transistor device includes a first gate stack portion including a dielectric layer disposed on a substrate, a first tin layer disposed on the dielectric layer, a metallic layer disposed on the dielectric layer, and a second tin layer disposed on the metallic layer, a first source region disposed adjacent to the first gate stack portion, and a first drain region disposed adjacent to the first gate stack portion.. .
07/17/14
20140199825
Silicon-germanium heterojunction tunnel field effect transistor and preparation method thereof
A silicon/germanium (sige) heterojunction tunnel field effect transistor (tfet) and a preparation method thereof are provided, in which a source region of a device is manufactured on a silicon germanium (sige) or ge region, and a drain region of the device is manufactured in a si region, thereby obtaining a high on-state current while ensuring a low off-state current. Local ge oxidization and concentration technique is used to implement a silicon germanium on insulator (sgoi) or germanium on insulator (goi) with a high ge content in some area.
07/17/14
20140199813
Transistor with longitudinal strain in channel induced by buried stressor relaxed by implantation
Processes for making field effect transistors relax a buried stressor layer to induce strain in a silicon surface layer above the buried stressor layer. The buried stressor layer is relaxed and the surface layer is strained by implantation into at least the buried stressor layer, preferably on both sides of a portion of the surface layer that is to be stressed.
07/17/14
20140198423
Current limiter circuit for control and protection of mosfet
A circuit for controlling a metal oxide semiconductor field effect transistor (mosfet) to generate a dc output voltage from a dc input voltage includes a first mosfet and a second mosfet. The circuit includes a gate resistor coupled to the first mosfet.
07/17/14
20140197877
System for a contactless control of a field effect transistor
The invention stems from the realization that it is possible to control the electric field in the gate region of a field effect transistor (mos, fet etc.) without changing the net charge of the gate electrode or without resorting to electrical conduction. According to an aspect of the invention, the electric field is changed by modifying the charge distribution within the gate electrode without materially adding or subtracting charge carriers to it or changing its net charge.
07/17/14
20140197493
Defect reduction for formation of epitaxial layer in source and drain regions
The embodiments of mechanisms for forming source/drain (s/d) regions of field effect transistors (fets) described enable forming an epitaxially grown silicon-containing layer with reduced number of particles on surface of recesses. The described mechanisms also reduce the effect of the residual particles on the epitaxial growth.
07/17/14
20140197467
High voltage junction field effect transistor structure
A jfet structure includes a first jfet having a first terminal and a second jfet neighboring with the first jfet. Both jfets commonly share the first terminal and the first terminal is between the gate of each jfet.
07/17/14
20140197466
N-channel metal-oxide field effect transistor with embedded high voltage junction gate field-effect transistor
A semiconductor device comprising a high-voltage (hv) n-type metal oxide semiconductor (nmos) embedded hv junction gate field-effect transistor (jfet) is provided. An hv nmos with embedded hv jfet may include, according to a first example embodiment, a substrate, an n-type well region disposed adjacent to the substrate, a p-type well region disposed adjacent to the n-type well region, and first and second n+ doped regions disposed adjacent to the n-type well and on opposing sides of the p-type well region.
07/17/14
20140197463
Metal-programmable integrated circuits
A metal-programmable integrated circuit may include an array of metal-programmable cells. Each cell may include multi-gate transistor structures in which multiple surfaces of a gate structure serve to control current flow through at least one channel structure.
07/17/14
20140197411
Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device
A methodology enabling the formation of steep channel profiles for devices, such as ssrw fets, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing sti regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between sti regions; forming a recess in the doped silicon wafer between the sti regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming si:c on the doped silicon wafer in the recess..
07/10/14
20140194719
Long-term implantable silicon carbide neural interface device using the electrical field effect
Field effect devices, such as capacitors and field effect transistors, are used to interact with neurons. Cubic silicon carbide is biocompatible with the neuronal environment and has the chemical and physical resilience required to withstand the body environment and does not produce toxic byproducts.
07/10/14
20140191659
Led lamp control circuit
An led lamp control circuit comprises a rectifier circuit, an led light source load, a constant current circuit, and a first temperature detect switch circuit. The led light source load comprises at least one group of leds.
07/10/14
20140191325
Fin-shaped field effect transistor (finfet) structures having multiple threshold voltages (vt) and method of forming
Various embodiments include fin-shaped field effect transistor (finfet) structures that enhance work function and threshold voltage (vt) control, along with methods of forming such structures. The finfet structures can include a p-type field effect transistor (pfet) and an n-type field effect transistor (nfet).
07/10/14
20140191318
Complementary metal oxide semiconductor field effect transistor, metal oxide semiconductor field effect transistor and manufacturing method thereof
A complementary metal oxide semiconductor field-effect transistor (mosfet) includes a substrate, a first mosfet and a second mosfet. The first mosfet is disposed on the substrate within a first transistor region and the second mosfet is disposed on the substrate within a second transistor region.
07/10/14
20140191292
Methods and systems for point of use removal of sacrificial material
A method of manufacturing a sensor, the method including forming an array of chemically-sensitive field effect transistors (chemfets), depositing a dielectric layer over the chemfets in the array, depositing a protective layer over the dielectric layer, etching the dielectric layer and the protective layer to form cavities corresponding to sensing surfaces of the chemfets, and removing the protective layer. The method further includes, etching the dielectric layer and the protective layer together to form cavities corresponding to sensing surfaces of the chemfets.
07/03/14
20140187012
Customized shield plate for a field effect transistor
A customized shield plate field effect transistor (fet) includes a semiconductor layer, a gate dielectric, a gate electrode, and at least one customized shield plate. The shield plate includes a conductive layer overlying a portion of the gate electrode, one of the gate electrode sidewalls, and a portion of the substrate adjacent to the sidewall.
07/03/14
20140187007
Mosfet including asymmetric source and drain regions
At least one drain-side surfaces of a field effect transistor (fet) structure, which can be a structure for a planar fet or a fin fet, is structurally damaged by an angled ion implantation of inert or electrically active dopants, while at least one source-side surface of the transistor is protected from implantation by a gate stack and a gate spacer. Epitaxial growth of a semiconductor material is retarded on the at least one structurally damaged drain-side surface, while epitaxial growth proceeds without retardation on the at least one source-side surface.
07/03/14
20140185167
High voltage open-drain electrostatic discharge (esd) protection device
A high voltage open-drain electrostatic discharge (esd) protection device is disclosed, which comprises a high-voltage n-channel metal oxide semiconductor field effect transistor (hv nmosfet) coupled to a high-voltage pad and a low-voltage terminal and receiving a high voltage on the high-voltage pad to operate in normal operation. The high-voltage pad and the hv nmosfet are further coupled to a high-voltage esd unit blocking the high voltage, and receiving a positive esd voltage on the high-voltage pad to bypass an esd current when an esd event is applied to the high-voltage pad.
07/03/14
20140184196
Nanoscale wires, nanoscale wire fet devices, and nanotube-electronic hybrid devices for sensing and other applications
The present invention generally relates to nanotechnology, including field effect transistors and other devices used as sensors (for example, for electrophysiological studies), nanotube structures, and applications. Certain aspects of the present invention are generally directed to transistors such as field effect transistors, and other similar devices.
07/03/14
20140183633
Semiconductor devices and methods of manufacture thereof
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes partially manufacturing a fin field effect transistor (finfet) including a semiconductor fin comprising a first semiconductive material and a second semiconductive material disposed over the first semiconductive material.
07/03/14
20140183599
Field effect transistor
Field effect transistors are provided. An active region protrudes from a substrate and a gate electrode is provided on the active region.
07/03/14
20140183453
Field effect transistor having double transition metal dichalcogenide channels
A field effect transistor (fet) includes first and second channels stacked on a substrate, the first and second channels formed of a transition metal dichalcogenide, a source electrode and a drain electrode contacting both the first channel and the second channel, each of the source electrode and the drain electrode having one end between the first channel and the second channel, and a first gate electrode corresponding to at least one of the first channel and the second channel.. .
07/03/14
20140183452
Field effect transistor with channel core modified for a backgate bias and method of fabrication
A semiconductor device includes a substrate and a source structure and a drain structure formed on the substrate. At least one nanowire structure interconnects the source structure and drain structure and serves as a channel therebetween.
07/03/14
20140183451
Field effect transistor with channel core modified to reduce leakage current and method of fabrication
A semiconductor device includes a channel structure formed on a substrate, the channel structure being formed of a semiconductor material. A gate structure covers at least a portion of the surface of the channel structure and is formed of a film of insulation material and a gate electrode.
06/26/14
20140179095
Methods and systems for controlling gate dielectric interfaces of mosfets
Embodiments provided herein describe methods and systems for forming gate dielectrics for field effect transistors. A substrate including a germanium channel and a germanium oxide layer on a surface of the germanium channel is provided.
06/26/14
20140179047
Field effect transistor-based bio-sensor
An apparatus comprises: a sensing element formed on a buried oxide layer of a substrate and providing communication between a source region and a drain region; a gate dielectric layer on the sensing element, the gate dielectric layer defining a sensing surface on the sensing element; a passive surface surrounding the sensing surface; and a compound bound to the sensing surface and not bound to the passive surface, the compound having a ligand specifically configured to preferentially bind a target molecule to be sensed. An electrolyte solution in contact with the sensing surface and the passive surface forms a top gate of the apparatus..
06/26/14
20140176135
Multiturn mri coils in combination with current mode class d amplifiers
Example systems, apparatus, and circuits described herein concern a multi-turn transmit surface coil used in parallel transmission in high field mri. One example apparatus includes a balun network that produces out-of-phase signals that are amplified to drive current-mode class-d (cmcd) field effect transistors (fets) that are connected by a coil that includes an lc (inductance-capacitance) leg.
06/26/14
20140176113
Circuit for outputting reference voltage
A circuit for outputting reference voltage includes: a detecting unit, a feedback unit and an output unit which are respectively connected with an external power source, wherein a plurality of field effect transistors (fets) are provided in the detecting unit, wherein the detecting unit is for detecting foundry corners of the fets therein, the feedback unit is for feeding back and comparing a detecting result of the detecting unit, and outputting information after feeding back and comparing, and the output unit is for outputting reference voltage corresponding to the foundry corners of the fets to an external output terminal. The reference voltage outputted by the circuit for outputting reference voltage of the present invention is capable of varying with foundry corners of the fets, and achieves compensating for foundry corners of the fets..
06/26/14
20140175564
Finfet device
A method for forming a field effect transistor device includes patterning an arrangement of fin portions on a substrate, patterning a gate stack portion over portions of the fin portions and the substrate, growing an epitaxial material from the fin portions that electrically connects portions of adjacent fin structures, and removing a portion of the gate stack portion to expose a portion of the substrate.. .
06/26/14
20140175549
Finfet device
A method for fabricating a field effect transistor device includes removing a portion of a first semiconductor layer and a first insulator layer to expose a portion of a second semiconductor layer, wherein the second semiconductor layer is disposed on a second insulator layer, the first insulator layer is disposed on the second semiconductor layer, and the first semiconductor layer is disposed on the first insulator layer, removing portions of the first semiconductor layer to form a first fin disposed on the first insulator layer and removing portions of the second semiconductor layer to form a second fin disposed on the second insulator layer, and forming a first gate stack over a portion of the first fin and forming a second gate stack over a portion of the second fin.. .
06/26/14
20140175522
Field effect transistor-based bio sensor
An apparatus comprises: a sensing element formed on a buried oxide layer of a substrate and providing communication between a source region and a drain region; a gate dielectric layer on the sensing element, the gate dielectric layer defining a sensing surface on the sensing element; a passive surface surrounding the sensing surface; and a compound bound to the sensing surface and not bound to the passive surface, the compound having a ligand specifically configured to preferentially bind a target molecule to be sensed. An electrolyte solution in contact with the sensing surface and the passive surface forms a top gate of the apparatus..
06/26/14
20140175517
Field effect transistor
A field effect transistor (fet) disclosed herein comprising a substrate, a c-doped semiconductor layer disposed on the substrate, a channel layer disposed on the c-doped semiconductor layer, and an electron supply layer disposed on the channel layer. The fet further comprises a diffusion barrier layer disposed between the c-doped semiconductor layer and the channel layer, wherein the diffusion barrier layer contacts the channel layer directly..
06/26/14
20140175509
Lattice mismatched hetero-epitaxial film
An embodiment concerns forming an epi film on a substrate where the epi film has a different lattice constant from the substrate. The epi film and substrate may include different materials to collectively form a hetero-epitaxial device having, for example, a si and/or sige substrate and a iii-v or iv film.
06/26/14
20140175451
Normally off gallium nitride field effect transistors (fet)
A heterostructure field effect transistor (hfet) gallium nitride (gan) semiconductor power device comprises a hetero-junction structure comprises a first semiconductor layer interfacing it second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2deg) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero-junction structure for controlling a current flow between the source and drain electrodes in the 2deg layer.
06/26/14
20140175376
Reduced scale resonant tunneling field effect transistor
An embodiment includes a heterojunction tunneling field effect transistor including a source, a channel, and a drain; wherein (a) the channel includes a major axis, corresponding to channel length, and a minor axis that corresponds to channel width and is orthogonal to the major axis; (b) the channel length is less than 10 nm long; (c) the source is doped with a first polarity and has a first conduction band; (d) the drain is doped with a second polarity, which is opposite the first polarity, and the drain has a second conduction band with higher energy than the first conduction band. Other embodiments are described herein..
06/19/14
20140170844
Structure and method of tinv scaling for high k metal gate technology
A complementary metal oxide semiconductor (cmos) structure including a scaled n-channel field effect transistor (nfet) and a scaled p-channel field transistor (pfet) is provided. Such a structure is provided by forming a plasma nitrided, nfet threshold voltage adjusted high k gate dielectric layer portion within an nfet gate stack, and forming at least a pfet threshold voltage adjusted high k gate dielectric layer portion within a pfet gate stack.
06/19/14
20140170842
Method for forming dummy gate
Disclosed is a method of forming a dummy gate in manufacturing a field effect transistor. The method includes a first process of exposing a workpiece having a polycrystalline silicon layer to plasma of hbr gas, and a second process of further exposing the workpiece to the plasma of hbr gas after the first process.
06/19/14
20140170840
Epitaxial formation mechanisms of source and drain regions
The embodiments of mechanisms for forming source/drain (s/d) regions of field effect transistors (fets) descried enable forming an epitaxially grown silicon-containing material without using geh4 in an etch gas mixture of an etch process for a cyclic deposition/etch (cde) process. The etch process is performed at a temperature different form the deposition process to make the etch gas more efficient.
06/19/14
20140170827
Tunneling field effect transistor (tfet) formed by asymmetric ion implantation and method of making same
An embodiment integrated circuit device and a method of making the same. The embodiment method includes forming a first nitride layer over a gate stack supported by a substrate, implanting germanium ions in the first nitride layer in a direction forming an acute angle with a top surface of the substrate, etching away germanium-implanted portions of the first nitride layer to form a first asymmetric nitride spacer confined to a first side of the gate stack, the first asymmetric nitride spacer protecting a first source/drain region of the substrate from a first ion implantation, and implanting ions in a second source/drain region of the substrate on a second side of the gate stack unprotected by the first asymmetric nitride spacer to form a first source/drain..
06/19/14
20140170826
Biaxial strained field effect transistor devices
A process for forming contacts to a field effect transistor provides edge relaxation of a buried stressor layer, inducing strain in an initially relaxed surface semiconductor layer above the buried stressor layer. A process can start with a silicon or silicon-on-insulator substrate with a buried silicon germanium layer having an appropriate thickness and germanium concentration.
06/19/14
20140170779
Coherent spin field effect transistor
A coherent spin field effect transistor is provided by depositing a ferromagnetic base like cobalt on a substrate. A magnetic oxide layer is formed on the cobalt by annealing at temperatures on the order of 1000° k to provide a few monolayer thick layer.
06/19/14
20140169062
Methods of manufacturing embedded bipolar switching resistive memory
Non linear current response circuits can be used in embedded resistive memory cell for reducing power consumption, together with improving reliability of the memory array. The non linear current response circuits can include two back to back leaky pin diodes, two parallel anti-directional pin diodes, two back to back zener-type metal oxide diodes, or ovonic switching elements, along with current limiting resistor for standby power reduction at the low voltage region.
06/19/14
20140167834
Method and apparatus improving gate oxide reliability by controlling accumulated charge
A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (soi) metal-oxide-silicon field effect transistor (mosfet) devices using accumulated charge control (acc) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in soi mosfets, thereby yielding improvements in fet performance characteristics.
06/19/14
20140167187
N metal for finfet
An n work function metal for a gate stack of a field effect transistor (finfet) and method of forming the same are provided. An embodiment finfet includes a fin supported by a semiconductor substrate, the fin extending between a source and a drain and having a channel region, and a gate stack formed over the channel region of the fin, the gate stack including an n work function metal layer comprising an oxidation layer on opposing sides of a tantalum aluminide carbide (taalc) layer..
06/19/14
20140167186
Semiconductor device structures including strained transistor channels
The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in pmos field effect transistors, or tensile strain is wanted in transistor channels, as in nmos field effect transistors, to enhance carrier mobility and transistor speed.
06/19/14
20140167175
Transistor and method of fabricating the same
A field effect transistor is provided. The transistor may include a source electrode and a drain electrode provided spaced apart from each other on a substrate and a ‘+’-shaped gate electrode provided on a portion of the substrate located between the source and drain electrodes..
06/19/14
20140167146
Tunneling field effect transistor and fabrication method thereof
A tunneling field effect transistor (fet) and a method of fabricating the same are provided. The tunneling fet includes a first electrode formed on a substrate, a second electrode disposed over the first electrode with respect to the substrate, a channel layer which connects the first electrode and the second electrode, and a plurality of third electrodes formed on sidewalls of the channel layer, wherein the channel layer is higher than the third electrodes in the criteria of the substrate..
06/19/14
20140167134
Self-aligned vertical nonvolatile semiconductor memory device
The present invention belongs to the technical field of semiconductor memory devices and specifically relates to a self-aligned vertical nonvolatile semiconductor memory device, including: a semiconductor substrate, a drain region of a first doping type, two source regions of a second doping type, a stacked gate used to capture electrons; wherein the drain region, the two source regions and the stacked gate form two tunneling field effect transistors (tfets) sharing one gate and one drain, the drain region current of each of the tfet is affected by the quantity and distribution of the charges in the stacked gate used to capture electrons, the drain is buried in the semiconductor substrate, the source regions above the drain region are separated from the drain through a channel and separated form each other through a region of the first doping type. The semiconductor memory device of the present invention features small unit area and simple manufacturing process.
06/19/14
20140167113
Gallium nitride based semiconductor devices and methods of manufacturing the same
Gallium nitride (gan) based semiconductor devices and methods of manufacturing the same. The gan-based semiconductor device may include a heat dissipation substrate (that is, a thermal conductive substrate); a gan-based multi-layer arranged on the heat dissipation substrate and having n-face polarity; and a heterostructure field effect transistor (hfet) or a schottky electrode arranged on the gan-based multi-layer.
06/19/14
20140167111
Transistor and method of fabricating the same
A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion.


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Field Effect Transistor topics: Field Effect Transistor, Semiconductor, Semiconductor Device, Transistors, Integrated Circuit, Conductive Layer, Microprocessor, Disconnect, Leakage Current

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