|| List of recent Field Effect Transistor-related patents
| Semiconductor radio frequency switch with body contact|
The present disclosure relates to a radio frequency (rf) switch that includes multiple body-contacted field effect transistor (fet) elements coupled in series. The fet elements may be formed using a thin-film semiconductor device layer, which is part of a thin-film semiconductor die.
| Circuit arrangement for protecting against electrostatic discharges|
A circuit arrangement for protecting against electrostatic discharges comprises a diverter (ecl) that is suitable for diverting an electrostatic discharge between a first terminal (io) and a second terminal (vdd, vss), as well as a compensation device (1). The compensation device (1) features a series circuit of a first resistor (rs) and a field effect transistor (t1) that is connected between the first terminal (io) and the second terminal (vdd, vss).
| Dual-flag stacked die package|
In one embodiment, a semiconductor package includes a first and a second die flag, wherein the first and second die flags are separated by a gap. First and second metal oxide semiconductor field effect transistor (mosfet) die are on the first and the second die flags, respectively.
| Field effect transistor and method of manufacturing the same|
A field effect transistor (fet) and a method of manufacturing the same are provided. The fet may include a substrate; a source and a drain, one of which is formed on a bulge formed on a top surface of the substrate, and the other of which is formed in the substrate below but laterally offset from the bulge; a gate formed at a position where the bulge and the top surface of the substrate join each other; and a gate dielectric layer formed between the gate and the bulge and also between the gate and the top surface of the substrate.
| Insulated gate field effect transistor and method of manufacturing the same|
An insulated gate field effect transistor configured to reduce the occurrence of a short-circuit fault, and a method of manufacturing the insulated gate field effect transistor are provided. A fet includes a semiconductor substrate, a gate insulator, a gate electrode, and a conductive member.
| Field effect transistor with self-adjusting threshold voltage|
Methods for forming field effect transistors (fets) with improved on/off current ratios in addition to short charging times and the resulting devices are disclosed. Embodiments include forming a gate oxide layer above a channel region in a substrate, forming a partial self-adjusting threshold voltage layer above a drain-side end of the gate oxide layer, and forming a gate above the partial self-adjusting threshold voltage layer and the gate oxide layer..
| Tfet with nanowire source|
A tunnel field effect transistor (tfet) includes a source region, the source region comprising a first portion of a nanowire; a channel region, the channel region comprising a second portion of the nanowire; a drain region, the drain region comprising a portion of a silicon pad, the silicon pad being located adjacent to the channel region; and a gate configured such that the gate surrounds the channel region and at least a portion of the source region.. .
| Graphene heterostructure field effect transistors|
A field effect transistor includes a substrate, a first graphene (gr) layer on the substrate, a second graphene (gr) layer on the substrate, a fluorographene (grf) layer on the substrate and between the first and second graphene layers, a first ohmic contact on the first graphene layer, a second ohmic contact on the second graphene layer, a gate aligned over the fluorographene layer, and a gate dielectric between the gate and the fluorographene layer and between the gate and the first and second ohmic contacts.. .
| Generation of multiple diameter nanowire field effect transistors|
A system is provided and includes a wafer and a mask. The wafer includes a silicon-on-insulator (soi) structure disposed on a buried oxide (box) layer and has a first region with a first soi thickness and a second region with a second soi thickness, the first and second soi thicknesses being different from one another and sufficiently large such that respective pairs of soi pads connected via respective nanowires with different thicknesses are formable therein.
| Ionic field effect transistor having heterogeneous triangular nanochannel and method of manufacturing the same|
An ionic field effect transistor includes: a substrate; a polymer layer that is formed on the substrate and in which a first flow path and a second flow path that is separately disposed from the first flow path are formed; and a gate electrode that is formed between the substrate and the polymer layer and that contacts the first flow path and the second flow path, wherein a heterogeneous triangular nanochannel that connects the first flow path and the second flow path is formed between the gate electrode and the polymer layer.. .
|Process for the preparation of polymers containing benzohetero [1,3] diazole units|
Process for the preparation of a polymer containing benzohetero[1,3]diazole. Units which comprises reacting at least one disubstituted benzohetero[1,3]diazole compound with at least one heteroaryl compound.
|Trench metal oxide semiconductor with recessed trench material and remote contacts|
Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (mos) barrier schottky (tmbs) device, as well as to the polysilicon regions of a mos field effect transistor (mosfet) section and of a tmbs section in a monolithically integrated tmbs and mosfet (skyfet) device, are employed. The polysilicon is recessed relative to adjacent mesas.
|Junction field effect transistor structure with p-type silicon germanium or silicon germanium carbide gate(s) and method of forming the structure|
Disclosed are embodiments of a junction field effect transistor (jfet) structure with one or more p-type silicon germanium (sige) or silicon germanium carbide (sigec) gates (i.e., a sige or sigec based heterojunction jfet). The p-type sige or sigec gate(s) allow for a lower pinch off voltage (i.e., lower voff) without increasing the on resistance (ron).
|Double gate ion sensitive field effect transistor|
Devices that include a substrate; a source region and a drain region formed within the substrate and having a channel region provided therebetween; a first insulating layer formed over the channel region; a first floating gate formed over the first insulating layer, the first floating gate configured to respond to an analyte in a target material; and a second gate formed over the first floating gate, the second gate capacatively coupled but not electrically connected to the first floating gate.. .
|Fin field effect transistor fabricated with hollow replacement channel|
A method for forming a finfet comprises forming a raised fin between isolation trenches on a substrate. A plurality of sacrificial features is formed on at least a portion of the raised fin, the sacrificial features including a sacrificial gate dielectric and a sacrificial gate electrode having sidewalls.
|Monolithic mosfet and schottky diode for mobile phone boost converter|
A cell phone has a plurality of interconnected electronic components for performing the electrical functions of the phone. A dc/dc converter provides an operating voltage which is applied to power supply terminals of the plurality of interconnected electronic components.
|Vertical jfet with integrated body diode|
A vertical junction field effect transistor (jfet) includes a drain, a source, a gate, a drift region, and a body diode. The source, gate, drift region, and body diode are all disposed in the same compound semiconductor epitaxial layer.
|Methodology for fabricating isotropically recessed source regions of cmos transistors|
A field effect transistor device includes a buried oxide layer, a silicon layer above the buried oxide layer, an isotropically recessed source region, and a gate stack comprising a gate dielectric, a conductive material, and a spacer.. .
|Remote doping of organic thin film transistors|
Organic electronic devices comprising “remotely” doped materials comprising a combination of at least three layers. Such devices can include “remotely p-doped” structures comprising: a channel layer comprising at least one organic semiconductor channel material; a dopant layer, which comprises at least one p-dopant material and optionally at least one organic hole transport material; and a spacer layer disposed between and in electrical contact with both the channel layer and the dopant layer, comprising an organic semiconducting spacer material; or alternatively can include “remotely n-doped” structures comprising a combination of at least three layers: a channel layer comprising at least one organic semiconductor channel material; a dopant layer which comprises at least one organic electron transport material doped with an n-dopant material; and a spacer layer disposed between and in electrical contact with the channel layer and the dopant layer, comprising an organic semiconducting spacer material.
|Finfet/tri-gate channel doping for multiple threshold voltage tuning|
An embodiment method of controlling threshold voltages in a fin field effect transistor (finfet) includes forming a dummy gate over a central portion of a fin, the central portion of the fin disposed between exterior portions of the fin unprotected by the dummy gate, removing the exterior portions of the fin and replacing the exterior portions of the fin with an epitaxially-grown silicon-containing material, applying a spin-on resist over the dummy gate and the epitaxially-grown silicon-containing material and then removing the spin-on resist over the hard mask of the dummy gate, etching away the hard mask and a polysilicon of the dummy gate to expose a gate oxide of the dummy gate, the gate oxide disposed over the central portion of the fin, and implanting ions into the central portion of the fin through the gate oxide disposed over the central portion of the fin.. .
|Non-volatile memory system with reset control mechanism and method of operation thereof|
A method of operation of a non-volatile memory system includes: providing a control field effect transistor having a source electrode and a body-tie electrode; coupling a resistive storage element to the source electrode; and opening a well switch coupled to the body-tie electrode for increasing a well voltage and resetting the resistive storage element by the source electrode floating on the well voltage.. .
|Low-dropout regulator and method for voltage regulation|
A low-dropout regulator (1) comprises a differential amplifier (3) with a reference input (5) for applying a reference voltage (vin), a feedback input (7) and an amplifier output (9). An output transistor (11) has a control connection (13) connected to the amplifier output (9), and a control section connected between a first supply potential terminal (vdd) and a voltage output (15) of the low-dropout regulator (1).
|Changing effective work function using ion implantation during dual work function metal gate integration|
Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (fet) region and a second-type fet region; forming a metal layer having a first effective work function compatible for a first-type fet over the first-type fet region and the second-type fet region; and changing the first effective work function to a second, different effective work function over the second-type fet region by implanting a species into the metal layer over the second-type fet region..
|Carbon nanostructure device fabrication utilizing protect layers|
Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing.. .
|Lateral extended drain metal oxide semiconductor field effect transistor (ledmosfet) with tapered airgap field plates|
Disclosed are embodiments of a lateral, extended drain, metal oxide semiconductor, field effect transistor (ledmosfet) having tapered dielectric field plates positioned laterally between conductive field plates and opposing sides of a drain drift region of the ledmosfet. Each dielectric field plate comprises, in whole or in part, an airgap.
|Semiconductor constructions, dram arrays, and methods of forming semiconductor constructions|
The invention includes methods for utilizing partial silicon-on-insulator (soi) technology in combination with fin field effect transistor (finfet) technology to form transistors particularly suitable for utilization in dynamic random access memory (dram) arrays. The invention also includes dram arrays having low rates of refresh.
|Biological and chemical sensors|
Device structures, fabrication methods, and design structures for a biological and chemical sensor used to detect a property of a substance. The device structure includes a drain and a source of a field effect transistor formed at a frontside of a substrate.
|Switch design for light up phone cases|
A mobile phone call flashing apparatus equipped with an electronic switch relates to the field of electronic products and comprises an electric power supply, a capacitor, a first resistance, a second resistance, a switch, a first integrated block, a second integrated block, a conductor field effect transistor, and a first light-emitting diode through a sixth light-emitting diode. It can make up the deficiency in the prior art, allow users to be able to control the light-emitting status at the time of incoming calls or messages autonomously, greatly satisfy modern people's psychological needs in their pursuit of fashionable visual effects, and enjoy extensive applicability and market prospects..
|High freuency semiconductor switch and wireless device|
A high frequency semiconductor switch has a first terminal, second terminals, a first through fet group, second through fet groups and a shunt fet group. The first through fet group has first field effect transistors connected serially with each other.
|Methods of forming semiconductor devices by forming a semiconductor layer above source/drain regions prior to removing a gate cap layer|
One example of a method disclosed herein for forming a gate electrode in a field effect transistor comprises forming a gate structure above a semiconductor substrate, the gate structure comprising a gate electrode and a gate cap layer positioned above the gate electrode, forming sidewall spacers adjacent the sidewalls of the gate structure, forming a semiconductor layer above portions of the source/drain regions not covered by the gate structure and the sidewall spacers and performing at least one etching process to remove the gate cap layer from above the gate electrode and to remove at least a portion of the semiconductor layer.. .
|Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same|
Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor.
|Method for fabricating complementary tunneling field effect transistor based on standard cmos ic process|
Disclosed herein is a method for fabricating a complementary tunneling field effect transistor based on a standard cmos ic process, which belongs to the field of logic devices and circuits of field effect transistors in ultra large scaled integrated (ulsi) circuits. In the method, an intrinsic channel and body region of a tfet are formed by means of complementary p-well and n-well masks in the standard cmos ic process to form a well doping, a channel doping and a threshold adjustment by implantation.
|Rf switches having increased voltage swing uniformity|
Radio-frequency (rf) switch circuits are disclosed providing uniform voltage swing across a transmit switch for improved device performance. A switching circuit includes a switch having field effect transistors (fets) defining an rf signal path between the input port and the output port, the switch configured to be capable of being in a first state corresponding to the input and output ports being electrically connected so as to allow passage of the rf signal therebetween, and a second state corresponding to the input and output ports being electrically isolated.
|Mosfet with curved trench feature coupling termination trench to active trench|
A metal oxide semiconductor field effect transistor (mosfet) in and on a semiconductor surface provides a drift region of a first conductivity type. A plurality of active area trenches in the drift region, and first and second termination trenches are each parallel to and together sandwiching the active area trenches.
|Diketopyrrolopyrrole oligomers and compositions, comprising diketopyrrolopyrrole oligomers|
The present invention relates to compositions, comprising (a) a compound of the formula (i), and (b) a polymeric material, to specific oligomers of the formula i, and their use as organic semiconductor in organic devices, especially in organic photovoltaics (solar cells) and photodiodes, or in a device containing a diode and/or an organic field effect transistor. High efficiency of energy conversion, excellent field-effect mobility, good on/off current ratios and/or excellent stability can be observed, when the compositions, or oligomers according to the invention are used in organic field effect transistors, organic photovoltaics (solar cells) and photodiodes..
|Forming structures on resistive substrates|
A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.. .
|Trench metal oxide semiconductor field effect transistor with embedded schottky rectifier using reduced masks process|
A trench mosfet with embedded schottky rectifier having at least one anti-punch through implant region using reduced masks process is disclosed for avalanche capability enhancement and cost reduction. The source regions have a higher doping concentration and a greater junction depth along sidewalls of the trenched source-body contacts than along adjacent channel regions near the gate trenches..
|Wireless communication base station with current limiting capability|
A wireless communication system base station (20) includes a base station transceiver (26) that has at least one operative component (32) for facilitating wireless communications. A current limiting device (36) includes at least one field effect transistor for selectively controlling current flow to a capacitive stability device (34) associated with at least one of the operative components (32).
|High voltage finfet structure|
Methods for forming fin-shaped field effect transistors (finfets) capable of withstanding high voltage applications and the resulting devices are disclosed. Embodiments include forming a source and a drain on a substrate, forming a thin body (fin) on the substrate and connecting the source and the drain, forming a gate over top and side surfaces of a first part of the fin, thereby defining a drain-side fin region of the fin between the gate and the drain, and forming a shielding region over top and side surfaces of a second part of the fin in the drain-side fin region..
|Self-aligned well structures for low-noise chemical sensors|
In one implementation, a chemical detection device is described. The device includes a chemically-sensitive field effect transistor including a floating gate conductor coupled to a gate dielectric and having an upper surface, and a sensing material on the upper surface.
Some embodiments include memory constructions having a plurality of bands between top and bottom electrically conductive materials. The bands include chalcogenide bands alternating with non-chalcogenide bands.
|Self-aligned trench mosfet and method of manufacture|
A trench metal-oxide-semiconductor field effect transistor (mosfet), in accordance with one embodiment, includes a drain region, a plurality of gate regions disposed above the drain region, a plurality of gate insulator regions each disposed about a periphery of a respective one of the plurality of gate regions, a plurality of source regions disposed in recessed mesas between the plurality of gate insulator regions, a plurality of body regions disposed in recessed mesas between the plurality of gate insulator regions and between the plurality of source regions and the drain region. The mosfet also includes a plurality of body contact regions disposed in the each body region adjacent the plurality of source regions, a plurality of source/body contact spacers disposed between the plurality of gate insulator regions above the recessed mesas, a source/body contact disposed above the source/body contact spacers, and a plurality of source/body contact, plugs disposed between the source/body contact spacers and coupling the source/body contact to the plurality of body contact regions and the plurality of source regions..
An amplifier circuit is described comprising a first field effect transistor comprising a first source/drain terminal coupled to a first supply terminal, a second source/drain terminal coupled to an output of the amplifier circuit and a gate terminal; a second field effect transistor comprising a first source/drain terminal coupled to an input of the amplifier circuit, a second source/drain terminal coupled to the gate terminal of the first field effect transistor and a gate terminal; a third field effect transistor comprising a first source/drain terminal coupled to a first bias current source of the amplifier circuit, a second source/drain terminal and a gate terminal coupled to its first source/drain terminal and the gate terminal of the second field effect transistor; a fourth field effect transistor comprising a first source/drain terminal coupled to a second bias current source, a second source/drain terminal coupled to a second supply terminal and a gate terminal coupled to the second source/drain terminal of the third field effect transistor; and a control circuit coupled to the gate of the fourth field effect transistor configured to control the source drain voltage of the fourth field effect transistor by means of the gate of the fourth field effect transistor to be equal to a reference voltage.. .
|Device for controlling the on and off time of the metal oxide semiconductor field effect transistor (mosfet), a device spark coating the surfaces of metal workpiece incorporating the said control device and a method of coating metal surfaces using the said device|
The present invention is a device for coating surfaces of metallic work pieces with an electrically conductive material by employing short duration high current packets of pulses in which the work piece forms the cathode and the consumable coating material forms the anode, which are connected to a generator for generating pulses by charging and discharging a bank of capacitors using a mosfet. The invention is also a device for controlling the on and off time of a metal oxide semiconductor field effect transistor (mosfet).
|Field effect transistor and schottky diode structures|
In accordance with an embodiment a structure can include a monolithically integrated trench field-effect transistor (fet) and schottky diode. The structure can include a first gate trench extending into a semiconductor region, a second gate trench extending into the semiconductor region, and a source region flanking a side of the first gate trench.
|A strip-shaped gate-modulated tunneling field effect transistor and a preparation method thereof|
The present invention discloses a strip-shaped gate-modulated tunneling field effect transistor and a preparation method thereof, belonging to a field of field effect transistor logic device and the circuit in cmos ultra large scale integrated circuit (ulsi). The tunneling field effect transistor includes a control gate, a gate dielectric layer, a semiconductor substrate, a highly-doped source region and a highly-doped drain region, where the highly-doped source region and the highly-doped drain region lie on both sides of the control gate, respectively, the control gate has a strip-shaped structure with a gate length greater than a gate width, and at one side thereof is connected to the highly-doped drain region and at the other side thereof extends laterally into the highly-doped source region; a region located below the control gate is a channel region; and the gate width of the control gate is less than twice width of a source depletion layer.
|Scaled equivalent oxide thickness for field effect transistor devices|
A field effect transistor device includes a first gate stack portion including a dielectric layer disposed on a substrate, a first tin layer disposed on the dielectric layer, a metallic layer disposed on the dielectric layer, and a second tin layer disposed on the metallic layer, a first source region disposed adjacent to the first gate stack portion, and a first drain region disposed adjacent to the first gate stack portion.. .
|Silicon-germanium heterojunction tunnel field effect transistor and preparation method thereof|
A silicon/germanium (sige) heterojunction tunnel field effect transistor (tfet) and a preparation method thereof are provided, in which a source region of a device is manufactured on a silicon germanium (sige) or ge region, and a drain region of the device is manufactured in a si region, thereby obtaining a high on-state current while ensuring a low off-state current. Local ge oxidization and concentration technique is used to implement a silicon germanium on insulator (sgoi) or germanium on insulator (goi) with a high ge content in some area.
|Transistor with longitudinal strain in channel induced by buried stressor relaxed by implantation|
Processes for making field effect transistors relax a buried stressor layer to induce strain in a silicon surface layer above the buried stressor layer. The buried stressor layer is relaxed and the surface layer is strained by implantation into at least the buried stressor layer, preferably on both sides of a portion of the surface layer that is to be stressed.
|Current limiter circuit for control and protection of mosfet|
A circuit for controlling a metal oxide semiconductor field effect transistor (mosfet) to generate a dc output voltage from a dc input voltage includes a first mosfet and a second mosfet. The circuit includes a gate resistor coupled to the first mosfet.
|System for a contactless control of a field effect transistor|
The invention stems from the realization that it is possible to control the electric field in the gate region of a field effect transistor (mos, fet etc.) without changing the net charge of the gate electrode or without resorting to electrical conduction. According to an aspect of the invention, the electric field is changed by modifying the charge distribution within the gate electrode without materially adding or subtracting charge carriers to it or changing its net charge.
|Defect reduction for formation of epitaxial layer in source and drain regions|
The embodiments of mechanisms for forming source/drain (s/d) regions of field effect transistors (fets) described enable forming an epitaxially grown silicon-containing layer with reduced number of particles on surface of recesses. The described mechanisms also reduce the effect of the residual particles on the epitaxial growth.
|High voltage junction field effect transistor structure|
A jfet structure includes a first jfet having a first terminal and a second jfet neighboring with the first jfet. Both jfets commonly share the first terminal and the first terminal is between the gate of each jfet.
|N-channel metal-oxide field effect transistor with embedded high voltage junction gate field-effect transistor|
A semiconductor device comprising a high-voltage (hv) n-type metal oxide semiconductor (nmos) embedded hv junction gate field-effect transistor (jfet) is provided. An hv nmos with embedded hv jfet may include, according to a first example embodiment, a substrate, an n-type well region disposed adjacent to the substrate, a p-type well region disposed adjacent to the n-type well region, and first and second n+ doped regions disposed adjacent to the n-type well and on opposing sides of the p-type well region.
|Metal-programmable integrated circuits|
A metal-programmable integrated circuit may include an array of metal-programmable cells. Each cell may include multi-gate transistor structures in which multiple surfaces of a gate structure serve to control current flow through at least one channel structure.
|Method of forming step doping channel profile for super steep retrograde well field effect transistor and resulting device|
A methodology enabling the formation of steep channel profiles for devices, such as ssrw fets, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing sti regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between sti regions; forming a recess in the doped silicon wafer between the sti regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming si:c on the doped silicon wafer in the recess..
|Long-term implantable silicon carbide neural interface device using the electrical field effect|
Field effect devices, such as capacitors and field effect transistors, are used to interact with neurons. Cubic silicon carbide is biocompatible with the neuronal environment and has the chemical and physical resilience required to withstand the body environment and does not produce toxic byproducts.
|Led lamp control circuit|
An led lamp control circuit comprises a rectifier circuit, an led light source load, a constant current circuit, and a first temperature detect switch circuit. The led light source load comprises at least one group of leds.
|Fin-shaped field effect transistor (finfet) structures having multiple threshold voltages (vt) and method of forming|
Various embodiments include fin-shaped field effect transistor (finfet) structures that enhance work function and threshold voltage (vt) control, along with methods of forming such structures. The finfet structures can include a p-type field effect transistor (pfet) and an n-type field effect transistor (nfet).
|Complementary metal oxide semiconductor field effect transistor, metal oxide semiconductor field effect transistor and manufacturing method thereof|
A complementary metal oxide semiconductor field-effect transistor (mosfet) includes a substrate, a first mosfet and a second mosfet. The first mosfet is disposed on the substrate within a first transistor region and the second mosfet is disposed on the substrate within a second transistor region.
|Methods and systems for point of use removal of sacrificial material|
A method of manufacturing a sensor, the method including forming an array of chemically-sensitive field effect transistors (chemfets), depositing a dielectric layer over the chemfets in the array, depositing a protective layer over the dielectric layer, etching the dielectric layer and the protective layer to form cavities corresponding to sensing surfaces of the chemfets, and removing the protective layer. The method further includes, etching the dielectric layer and the protective layer together to form cavities corresponding to sensing surfaces of the chemfets.
|Customized shield plate for a field effect transistor|
A customized shield plate field effect transistor (fet) includes a semiconductor layer, a gate dielectric, a gate electrode, and at least one customized shield plate. The shield plate includes a conductive layer overlying a portion of the gate electrode, one of the gate electrode sidewalls, and a portion of the substrate adjacent to the sidewall.
|Mosfet including asymmetric source and drain regions|
At least one drain-side surfaces of a field effect transistor (fet) structure, which can be a structure for a planar fet or a fin fet, is structurally damaged by an angled ion implantation of inert or electrically active dopants, while at least one source-side surface of the transistor is protected from implantation by a gate stack and a gate spacer. Epitaxial growth of a semiconductor material is retarded on the at least one structurally damaged drain-side surface, while epitaxial growth proceeds without retardation on the at least one source-side surface.
|High voltage open-drain electrostatic discharge (esd) protection device|
A high voltage open-drain electrostatic discharge (esd) protection device is disclosed, which comprises a high-voltage n-channel metal oxide semiconductor field effect transistor (hv nmosfet) coupled to a high-voltage pad and a low-voltage terminal and receiving a high voltage on the high-voltage pad to operate in normal operation. The high-voltage pad and the hv nmosfet are further coupled to a high-voltage esd unit blocking the high voltage, and receiving a positive esd voltage on the high-voltage pad to bypass an esd current when an esd event is applied to the high-voltage pad.
|Nanoscale wires, nanoscale wire fet devices, and nanotube-electronic hybrid devices for sensing and other applications|
The present invention generally relates to nanotechnology, including field effect transistors and other devices used as sensors (for example, for electrophysiological studies), nanotube structures, and applications. Certain aspects of the present invention are generally directed to transistors such as field effect transistors, and other similar devices.
|Semiconductor devices and methods of manufacture thereof|
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes partially manufacturing a fin field effect transistor (finfet) including a semiconductor fin comprising a first semiconductive material and a second semiconductive material disposed over the first semiconductive material.
|Field effect transistor|
Field effect transistors are provided. An active region protrudes from a substrate and a gate electrode is provided on the active region.
|Field effect transistor having double transition metal dichalcogenide channels|
A field effect transistor (fet) includes first and second channels stacked on a substrate, the first and second channels formed of a transition metal dichalcogenide, a source electrode and a drain electrode contacting both the first channel and the second channel, each of the source electrode and the drain electrode having one end between the first channel and the second channel, and a first gate electrode corresponding to at least one of the first channel and the second channel.. .
|Field effect transistor with channel core modified for a backgate bias and method of fabrication|
A semiconductor device includes a substrate and a source structure and a drain structure formed on the substrate. At least one nanowire structure interconnects the source structure and drain structure and serves as a channel therebetween.
|Field effect transistor with channel core modified to reduce leakage current and method of fabrication|
A semiconductor device includes a channel structure formed on a substrate, the channel structure being formed of a semiconductor material. A gate structure covers at least a portion of the surface of the channel structure and is formed of a film of insulation material and a gate electrode.