|| List of recent Error Correction-related patents
| Controller, information processing system, method of controlling controller, and program|
A controller includes: a low-level error correction section configured to execute low-level error correction in which an error in a code word is corrected with use of a predetermined decoding algorithm; and a high-level soft-decision error correction section configured to execute high-level soft-decision error correction in which the error in the code word is corrected with use of a high-level algorithm when the error correction by the low-level error correction section has failed, the high-level algorithm being a soft-decision decoding algorithm having higher error correction capability than error correction capability of the predetermined decoding algorithm.. .
| Time protocol latency correction based on forward error correction status|
One embodiment provides a method for time protocol latency correction based on forward error correction (fec) status. The method includes determining, by a network node element, if a forward error correction (fec) decoding mode is enabled or disabled for a packet received from a link partner in communication with the network node element.
| Method and apparatus for transporting an 8b/10b coded video stream across a 64b/66b coded link|
A video transport system is provided for transporting as 8b/10b coded video stream across a 64b/66b coded link, wherein forward error correction is provided without the overhead of the prior art. The system also provides a system with the ability to recover 64b/66b encoded blocks that have corrupt sync bits..
| Dynamic aperture holographic multiplexing|
Systems and methods for dynamic aperture holographic multiplexing are disclosed. One example process may include recording a set of holograms in a recording medium by varying both the reference beam angular aperture and the signal beam angular aperture.
|Methods and systems for 2-dimensional forward error correction coding|
A communication system and a method are disclosed. The communication system includes an encoder configured to encode source data and output an encoded frame including a plurality of rows and a plurality of columns.
|Systems, methods, apparatus, and computer program products for providing forward error correction with low latency|
Systems, methods, apparatus, and computer program products for providing forward error correction with low latency to live streams in networks are provided. One example method includes receiving source data at a first rate, outputting the source data at a rate less than the first rate, collecting the source data in a buffer, fec decoding the source data, thereby generating decoded data; and outputting the decoded data at a rate equal to the first rate, either after collecting the source data in the buffer for a predetermined time duration or after collecting a predetermined amount of the source data in the buffer..
|Error protection for integrated circuits in an insensitive direction|
A method for providing error detection, or error detection combined with error correction, to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding an error control mechanism to the array of storage cells in the insensitive direction. The insensitive direction is a direction perpendicular to a width of a gate conductor of the storage cells..
|Error correction with extended cam|
A memory system includes a memory and a content addressable memory (cam). The memory includes a plurality of address locations, wherein each address location configured to store data and one or more error correction bits corresponding to the data.
|Adaptation of analog memory cell read thresholds using partial ecc syndromes|
A method includes storing data that is encoded with an error correction code (ecc) in a group of analog memory cells. The memory cells in the group are read using multiple sets of read thresholds.
|Shared error protection for register banks|
A method for adding error detection, or error detection combined with error correction, to a plurality of register banks includes grouping the plurality of register banks into an array. The method also includes adding a first error control mechanism to the array in a first direction and adding a second error control mechanism to the array in a second direction.
|Apparatus and methods thereof for error correction in split core current transformers|
Apparatus and methods are provided for electrical parameter measurements at points of interest, such as circuit breakers, machines, and the like. The devices which comprise of components that may require corrections, such as the errors induced by, but not limited to, the use of a split core mounted around a current carrier, and hence calibration coefficients are provided based on test, measurements and/or calculations respective of the devices.
|Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals|
The object of the present invention can be achieved by providing a method of transmitting broadcast signals including encoding data pipe, dp, data, wherein the encoding further includes forward error correction, fec, encoding the dp data, bit interleaving the fec encoded dp data and mapping the bit interleaved dp data onto constellations; building at least one signal frame by mapping the encoded dp data; and modulating data in the at least one built signal frame by an orthogonal frequency division multiplexing, ofdm, method and transmitting the broadcast signals having the modulated data, wherein each of the at least one signal frame includes at least one preamble having repeated at least one signaling information.. .
|Memory system and method of operation thereof|
A method of operating a memory system including a non-volatile memory device and a memory controller controlling the non-volatile memory device, includes reading data from a memory cell array in a unit of a page which includes a plurality of sectors; performing error correction decoding on the read data in a unit of a sector of the page; selecting at least one target sector which includes at least one uncorrectable error and selecting at least one pass sector wherein all errors of the pass sector are correctable by the error correction decoding; inhibiting precharging of bit-lines connected to the at least one pass sector while precharging target bit lines connected to the at least one target sector; and performing a read retry operation for data in the at least one target sector.. .
|Rate matching and scrambling techniques for control signaling|
Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes an input padding module configured to provide padded bits having padding bits added to payload bits for one or more control channels, and a scrambling module configured to apply a masking sequence to one or more of the padded bits to generate scrambled bits.
|Apparatus for transmitting broadcasting signal, apparatus for receiving broadcasting signal, and method for transmitting/receiving broadcasting signal through apparatus for transmitting/receiving broadcasting signal|
A transmitter and method of processing broadcast data are discussed. In one embodiment, the method includes forward error correction (fec) encoding physical layer pipe (plp) data at a first code rate; fec encoding first signaling data at a second code rate; fec encoding second signaling data at a third code rate; time interleaving the fec-encoded plp data; frequency interleaving the time-interleaved plp data by a pair of consecutive cells; and modulating the frequency-interleaved plp data, the fec-encoded first signaling data, and the fec-encoded second signaling data by an orthogonal frequency division multiplexing (ofdm) method, wherein the first signaling data include fec type information of the second signaling data and wherein the second signaling data include fec type information and the first code rate used by the plp data..
|Simultaneous data transfer and error control to reduce latency and improve throughput to a host|
The disclosed embodiments provide a system that transfers data from a storage device to a host. The system includes a communication mechanism that receives a request to read a set of blocks from the host.
|Memory testing with selective use of an error correction code decoder|
A method includes directing an access of a memory location of a memory device to an error correction code (ecc) decoder in response to receiving a test activation request indicating the memory location. The method also includes writing a test pattern to the memory location and reading a value from the memory location.
|Method and apparatus for correcting error in speech recognition system|
A method of correcting errors in a speech recognition system includes a process of searching a speech recognition error-answer pair db based on a sound model for a first candidate answer group for a speech recognition error, a process of searching a word relationship information db for a second candidate answer group for the speech recognition error, a process of searching a user error correction information db for a third candidate answer group for the speech recognition error, a process of searching a domain articulation pattern db and a proper noun db for a fourth candidate answer group for the speech recognition error, and a process of aligning candidate answers within each of the retrieved candidate answer groups and displaying the aligned candidate answers.. .
|Method and apparatus for data transmission using multiple transmit antennas|
A method and apparatus for increasing the data rate and providing antenna diversity using multiple transmit antennas utilize a set of bits of a digital signal to generate a codeword. Delay elements may be provided in antenna output channels, or, with suitable code construction, delay may be omitted.
|Apparatus and method for fast tag hit with double error correction and triple error detection|
A method is described that includes reading a cache tag and the cache tag's corresponding ecc from storage circuitry of a cache. The method also includes generating an ecc for a search tag.
|Efficient cache search and error detection|
A first codeword may be constructed from a cache tag in a cache and an error correction code corresponding to the cache tag. A second codeword may be constructed from a search tag and an error correction code corresponding to the search tag.
|Dtv transmitting system and receiving system and method of processing broadcast signal|
A television transmitting system includes an encoder, a data randomizing and expanding unit, a group formatter, a deinterleaver, and a packet formatter. The encoder codes enhanced data for error correction, permutes the coded data, and further codes the permuted data for error detection.
|Nonvolatile memory devices with age-based variability of read operations and methods of operating same|
Integrated circuit memory systems and methods include comparing a number of erase cycles of a memory block corresponding to a read request to a first value and reading data stored in the memory block according to a first read condition corresponding to a first reliability improvement operation when the number of erase cycles of the memory block is less than the first value. An error of the data read according to the first read condition may be corrected using an error correction code (ecc) when the error of the data read according to the first read condition is correctable..
|Error correcting device, method for monitoring an error correcting device and data processing system|
An error correcting device is provided that has an input connectable to receive one or more data units, an error detection module arranged to identify a presence of one or more errors in a received data unit of the one or more data units and to provide an error detection signal for the received data unit, an error correction module arranged to perform an error correction processing on the received data unit and provide a corrected data unit, and a correction evaluation module arranged to perform a comparison of the received data unit with the corrected data unit and to generate a correction error signal depending on a result of the comparison and the error detection signal.. .
|Method and system for operating a communication circuit configurable to support one or more data rates|
A method and system for operating a communication circuit that is configurable to support one or more communication standards on a single device. The communication circuit includes a transmitting device that comprises a pcs module operating at a first data rate, and a second pcs module operating at a second data rate.
|Forward error correction with configurable latency|
A method of performing forward error correction with configurable latency, where a configurable latency algorithm evaluates a target bit error rate (ber) against an actual ber and adjusts the size of a configurable buffer such that the target ber may be achieved when utilizing the smallest buffer size possible. When errors are corrected without the utilization of each of the configurable buffer locations, the algorithm reduces the size of the buffer by y buffer locations; the algorithm may continue to successively reduce the size of said buffer until the minimum number of buffer locations are utilized to achieve the target ber.
|Efficient correction of normalizer shift amount errors in fused multiply add operations|
A method for correcting a shift error in a fused multiply add operation. The method comprises adjusting a normalized floating-point number before performing a shift error correction to produce an adjusted normalized floating-point number, and correcting a shift error in the adjusted normalized floating-point number.
|Systems and methods for implementing soft-decision reed-solomon decoding to improve cable modem and cable gateway performance|
A system and method are provided for implementing a soft reed-solomon (rs) decoding scheme, technique or algorithm to improve physical layer performance in cable modems and cable gateways. At 1024-qam, a receiver is provided in which a signal to noise ratio is reduced by at least about 1 db relaxing design considerations and specifications for other components in the system including for the tuner.
|Optical information reproducing apparatus and optical information reproducing method|
A method of calculating a reliability effective in a decoding process of hologram. An optical information reproducing apparatus that reproduces information with the use of the holography includes an image acquisition unit that reproduces two-dimensional data from a hologram disc, an image equalization unit that makes the two-dimensional data equal to target data having a target pr characteristic, a soft output decoding unit that decodes output data of the image equalization unit on the basis of the pr characteristic, and outputs a decoded result having a reliability, and an error correction unit that conducts an error correction of the data on the basis of the decoded result..
|Semiconductor memory device having faulty cells|
In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories..
|Multi-level cell memory device and method of operating multi-level cell memory device|
A read method of a multi-level cell memory device includes receiving a first read command, and reading first and second hard decision data by performing first and second hard decision read operations using a first hard decision read voltage and a second hard decision read voltage, respectively, the second hard decision read voltage being higher than the first hard decision read voltage. The method further includes selecting one of the first and second hard decision read voltages, reading first soft decision data by performing a first soft decision read operation using a plurality of soft decision read voltages having voltage levels which are different from that of the selected one of the first and second hard decision read voltages, and providing the first soft decision data to a memory controller for first error correction code (ecc) decoding..
|Variable rate coding for forward and reverse link|
A technique for encoding a signal used in a digital communication system in which individual traffic channel data rates may be adapted to specific channel conditions. In particular, a forward error correction coding rate is adapted for individual channels while at the same time maintaining a fixed block size independent of the fec coding rate.
|Method of arranging data in a non-volatile memory and a memory control system thereof|
A method of arranging data in a non-volatile memory and an associated memory control system are disclosed. A data area is divided into a plurality of valid data divisions, each having a link header followed by associated data and error correction code (ecc).
|Error detection and correction apparatus and method|
Embodiments of apparatus and methods for error detection and correction are described. A codeword may have a data portion and associated check bits.
|Method, system and apparatus for providing access to error correction information|
Techniques and mechanisms to facilitate data error detection by a memory controller. In an embodiment, the memory controller calculates, for each of a plurality of data blocks, a respective result based on a first metadata value and data of that data block, where the first metadata value describes a characteristic which is common to each of the plurality of data blocks.
|Techniques for error correction of encoded data|
Examples are disclosed for techniques for error correction of encoded data. In some examples, error correction code (ecc) information for the ecc encoded data may be received that indicates the ecc encoded data includes one or more errors.
|Error recovery within integrated circuit|
An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.. .
|Error correction and recovery in chained memory architectures|
Electronic apparatus, systems, and methods to construct and operate the electronic apparatus and/or systems include a memory unit configured to receive data flow from two directions. The memory unit can be configured serially in a chain with other memory units.
|Virtual tape using a logical data container|
A virtual tape is constructed using a logical data container to aid in emulating a virtual tape by providing tape functionality, reducing seek time and improving recovery time in case of a failure. For example, the logical data container may comprise a global header followed by one or more data block groups.
|Fine step blended modulation communications|
A communication device is configured to perform symbol mapping of bits to generate modulation symbols using one or more modulations. The device may employ a blended modulation composed of bit labels or symbols having different numbers of bits per symbol and different modulations.
|Image receiving device and image receiving method|
An image transmission device compresses and transmits image data to be sent and cannot correct errors occurring on the transmission path when image data to be transmitted is larger than a currently prescribed image size. In an image receiving device which receives compressed image data, data to be inputted is inputted by switching between first periods, during which the amount of data transmitted per prescribed time interval is a first data transmission amount, and second periods, during which the amount of data transmitted per prescribed time interval is less than the first data transmission amount.
|Multilevel encoding with error correction|
Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a plurality of bits may be encoded into a plurality of memory cells by responding to bits of the plurality of bits by changing the logic levels of corresponding groups of memory cells of the plurality of memory cells.
|Error recovery for flash memory|
An indication of a page type which failed error correction decoding is received. A threshold to adjust is selected from a plurality of thresholds based at least in part on the page type.
|Memory controller, semiconductor storage device, and decoding method|
According to an embodiment, a memory interface that includes n number of channels and writes data subjected to an error correction encoding process having capable of correcting t symbols, n number of first error correction decoding units that perform an error correction decoding process of correcting s (s<t) symbols on read data, and a second error correction decoding units that perform an error correction decoding process of correcting t symbols on read data from which an error is detected after the error correction decoding process of correcting s symbols.. .
|Unmanned aerial vehicle angular reorientation|
A system comprising an unmanned aerial vehicle (uav) having wing elements and tail elements configured to roll to angularly orient the uav by rolling so as to align a longitudinal plane of the uav, in its late terminal phase, with a target. A method of uav body re-orientation comprising: (a) determining by a processor a boresight angle error correction value bases on distance between a target point and a boresight point of a body-fixed frame; and (b) effecting a uav maneuver comprising an angular role rate component translating the target point to a re-oriented target point in the body-fixed frame, to maintain the offset angle via the offset angle correction value..
|High-performance ecc decoder|
Methods for error correction code (ecc) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ecc. An error locator polynomial (elp) is generated based on the syndromes.
|Dtv transmitting system and method of processing broadcast data|
A dtv transmitting system includes an encoder, a randomizer, a block processor, a group formatter, a deinterleaver, and a packet formatter. The encoder codes enhanced data for error correction, permutes the coded data, and further codes the permuted data for error detection.
|Policy for read operations addressing on-the-fly decoding failure in non-volatile memory|
An apparatus includes a non-volatile memory and a controller. The controller is operatively coupled to the non-volatile memory and configured to perform read and write operations on the non-volatile memory using codewords as a unit of read access.
|Error correction code rate management for nonvolatile memory|
An apparatus having an interface and a circuit is shown. The interface is coupled to a memory that is nonvolatile.
|Stopping criteria for layered iterative error correction|
The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer.
|Method and apparatus for correcting speech recognition error|
Disclosed are a speech recognition error correction method and an apparatus thereof. The speech recognition error correction method includes determining a likelihood that a speech recognition result is erroneous, and if the likelihood that the speech recognition result is erroneous is higher than a predetermined standard, generating a parallel corpus according to whether the speech recognition result matches the correct answer corpus, generating a speech recognition model based on the parallel corpus, and correcting an erroneous speech recognition result based on the speech recognition model and the language model.
|Phase difference detector and rotation angle detection device including the same|
In a phase difference detector, a first phase difference computation unit computes a value of e(i)·c corresponding to one and the same given magnetic pole sensed by the two magnetic sensors with use of six output signals sampled at three different timings while the two magnetic sensors are sensing the given magnetic pole when a rotary body is rotating. E is an angular width error correction value, and c is a phase difference between two signals.
|Rotation angle detection device|
In a rotation angle detection device, when a condition that two sensors among three magnetic sensors sense one and the same magnetic pole for three consecutive sampling periods is satisfied, a rotation angle is computed based on output signals from the two sensors, sampled at three sampling timings. When the output signals sampled at the three sampling timings satisfy a prescribed requirement, an angular width error correction value corresponding to the magnetic pole sensed by the two sensors and amplitudes are computed, and stored in association with the magnetic pole.
|Setting a default read signal based on error correction|
The present disclosure includes apparatuses and methods related to setting a default read signal based on error correction. A number of methods can include reading a page of data from a group of memory cells with a first discrete read signal and error correcting at least one codeword of the page of data as read with the first discrete read signal.
|Automatic correction device of vehicle display system and method thereof|
An automatic correction device of a vehicle display system and method thereof, comprising following steps: firstly, transform an image of road in front into projection information, to calculate a coordinate model, then detect facial features of a driver, to calculate a face rotation angle and a facial features 3-d position of said driver, to estimate a position field of view for said driver looking to front. Then, said position field of view is substituted into an image overlap projection transformation formula, to generate an overlap error correction parameter.
|Forward error correction with parallel error detection for flash memories|
Methods, systems, and devices are described for forward error correction for flash memory. Encoded data from flash memory may be used to generate a number of data streams.
|Mram smart bit write algorithm with error correction parity bits|
Some aspects of the present disclosure relate a method. The method attempts to write an expected multi-bit word to a memory location in memory.
|Data storage device and method for processing error correction code thereof|
A data storage device includes a data storage medium, and an error correction code unit configured to process an error correction code for data to be stored in the data storage medium. The error correction code unit includes a storage block configured to store the data to be stored in the data storage medium, and an encoder configured to divide the data stored in the storage block into a plurality of data groups according to an address of the storage block, to encode the plurality of data groups, to encode a plurality of parity data groups that are generated by encoding the plurality of data groups, and to generate final parity data..
|Methods, solid state drive controllers and data storage devices having a runtime variable raid protection scheme|
A data storage device may comprise a flash controller and an array of flash memory devices coupled to the flash controller. The array may comprise a plurality of s-pages that may each comprise a plurality of f-pages.