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Error Correction patents



      
           
This page is updated frequently with new Error Correction-related patent applications. Subscribe to the Error Correction RSS feed to automatically get the update: related Error RSS feeds. RSS updates for this page: Error Correction RSS RSS


Staircase forward error correction coding

Data transmitter, data receiver, and frame synchronization method

Memory system

Date/App# patent app List of recent Error Correction-related patents
08/21/14
20140237326
 Method and apparatus for reading data from non-volatile memory patent thumbnailMethod and apparatus for reading data from non-volatile memory
Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array.
08/21/14
20140237325
 Staircase forward error correction coding patent thumbnailStaircase forward error correction coding
For example, is a valid codeword.. .
08/21/14
20140237323
 Data transmitter, data receiver, and frame synchronization method patent thumbnailData transmitter, data receiver, and frame synchronization method
Embodiments of the present invention provide a data transmitter, a data receiver, and a frame synchronization method. The data transmitter includes a coding module and a processing module.
08/21/14
20140237320
 Memory system patent thumbnailMemory system
A memory system includes a controlling unit that configured to control data transfer between the first and the second memory. The controlling unit executes copy processing for, after reading out data stored in a first page of the second memory to the first memory, writing the data in a second page of the second memory, determines, when executing the copy processing, whether the error correction processing for the data read out from the first page is successful, stores, when the error correction processing is successful, corrected data in the first memory and writes the corrected data in the second page, and reads out, when the error correction processing is unsuccessful, the data from the first page to the first memory and writes the data not subjected to the error correction processing in the second page..
08/21/14
20140233683
 Reduced state sequence estimation with soft decision outputs patent thumbnailReduced state sequence estimation with soft decision outputs
A receiver may be operable to receive an inter-symbol correlated (isc) signal, and generate a plurality of soft decisions as to information carried in the isc signal. The soft decisions may be generated using a reduced-state sequence estimation (rsse) process.
08/21/14
20140233483
 Method and device for transmitting frame patent thumbnailMethod and device for transmitting frame
Disclosed are a method and device for transmitting a frame. The method for transmitting a frame includes a step of generating a-mpdu (aggregate mac protocol data unit) and a step of transmitting a-mpdu.
08/21/14
20140233482
 Transmission device and transmission method patent thumbnailTransmission device and transmission method
A transmission device capable of reducing packet receiving errors and the number of retransmissions by improving error correction coding gain without increasing the amount of resources used in transmission. The transmission device (100) that transmits each bit of coded data constituted from systematic bits and parity bits in order for each transmission unit, and performs frequency puncturing to puncture, in units of symbols, data to be punctured in which each bit has been superimposed on a plurality of frequency domain symbols.
08/14/14
20140229997
 Satellite broadcasting and communication transmitting method and apparatus operable in broad signal to noise ratio (snr) environment patent thumbnailSatellite broadcasting and communication transmitting method and apparatus operable in broad signal to noise ratio (snr) environment
Provided is a technology applicable to a broad signal to noise ratio (snr) environment for a satellite communication and broadcasting service, including a mapper to modulate a forward error correction frame based on a predetermined constellation, a physical layer header processor to add a physical layer header to the modulated forward error correction frame, a physical layer frame spreader to spread a physical layer frame of the modulated forward error correction frame, and a physical layer scrambler to scramble the added physical layer header and the spread physical layer frame.. .
08/14/14
20140229805
 Llr computation device and error correction decoding device patent thumbnailLlr computation device and error correction decoding device
A two-reference-point-pair determining unit 101 determines two reference point pairs by selecting two transmission symbol points with their llr computation target bit being 0 and two transmission symbol points with their llr computation target bit being 1. An llr computation unit 113 assigns weights to the two llrs calculated for the two reference point pairs, respectively, followed by adding them, and further adds to the addition result a correction term that may be zero sometimes, thus computing llr for the two reference point pairs..
08/14/14
20140229799
 Statistical adaptive error correction for a flash memory patent thumbnailStatistical adaptive error correction for a flash memory
A method for implementing adaptive error correction in a memory, comprising the steps of (a) decoding a page of data read from a memory, (b) selecting one of a plurality of histograms based on a measured code word error rate of the decoded page and (c) applying an error correction code rate based on the selected histogram. The error correction code rate allows the memory to use a minimum number of error correction bits to provide reliable operation of the memory..
08/14/14
20140229796
Electronic control apparatus
In the electronic control apparatus according to the present invention, data after error correction is retained in a second storage area different from a first storage area where a data error is detected, data on the second storage area is used for control processing and data on the first storage area is also used for control processing continuously.. .
08/14/14
20140229795
Configurable coding system and method of multiple eccs
A configurable coding system and method of multiple error correcting codes (eccs) for a memory device or devices are disclosed. The system includes a first ecc codec that selectively performs different error corrections with different parameters; means for providing a selected parameter to the ecc codec for initializing the ecc codec; and a second ecc codec that corrects the selected error-prone parameter in order to provide an error-free parameter to the first ecc codec..
08/14/14
20140229793
Apparatus and method for controlling access to a memory device
An apparatus includes encoding circuitry to generate code words for storage in a memory device. Decoding circuitry is responsive to a read transaction to decode one or more code words read from the memory device in order to generate read data for outputting in response to the read transaction.
08/14/14
20140229786
Digital error correction
An error-correcting circuit comprises: a component arranged to generate a first output from a first input and a second input; an error detector arranged to generate an error flag indicative of whether or not it has detected an error in the first output, based on the first output, the first input and the second input; a correction generator suitable for generating a correcting output after a first time period beginning with a timing event, based on the first output, the first input and the second input; and an output generator arranged to generate an output of the error-correcting circuit after a second time period beginning with the timing event. If the error flag indicates that an error has been detected in the first output then the second time period may be longer than the first time period, otherwise the second time period may be not longer than the first time period.
08/14/14
20140229655
Storing error correction code (ecc) data in a multi-tier memory structure
Method and apparatus for managing data in a memory. In accordance with some embodiments, a data object is stored in a first non-volatile tier of a multi-tier memory structure.
08/14/14
20140226980
Low latency multiplexing for optical transport networks
Techniques for multiplexing and demultiplexing signals for optical transport networks are presented. A network component comprises a multiplexer component that multiplexes a plurality of signals having a first signal format to produce a multiplexed signal in accordance with a second signal format, while maintaining error correction code (ecc) of such signals and without decoding such signals and associated ecc.
08/14/14
20140226752
Satellite broadcasting and communication transmitting apparatus and method for broadband satellite and communication service
Provided is a satellite broadcasting and communication transmitting apparatus and method for a broadband satellite broadcasting and communication service, including a forward error correction (fec) encoder to generate an fec frame, a bit mapping framer to perform bit mapping on the generated fec frame, and a predistorter to predistort the bit mapped frame.. .
08/14/14
20140226731
Digital television system
A digital television system performing modulation/demodulation by vsb (vestigial side band) is provided. The invention includes a vsb transmitter including an additional error correction encoder designed such that a signal mapping of a tcm encoder is considered, a multiplexer (mux), a tcm encoder operating in correspondence with state transition processes of the additional error correction encoder, and a signal transmission part including an rf converter.
08/07/14
20140223267
Radix-4 viterbi forward error correction decoding
A method for forward error correction decoding. The method generally includes steps (a) to (d).
08/07/14
20140223265
Network system configured for resolving forward error correction during a link training sequence
One embodiment provides a method for resolving a forward error correction (fec) protocol. The method includes requesting, by a network node element during an auto-negotiation period between the node element and a link partner, to resolve at least one fec mode during a link training period; wherein the auto-negotiation period and the link training period are defined by an ethernet communications protocol and the auto-negotiation period occurs before the link training period; determining, by the network node element, at least one channel quality parameter of at least one channel of a communication link between the network node element and the link partner; and determining, by the network node element during the link training period, whether to enable at least one fec mode for use by the network node element based on, at least in part, the at least one channel quality parameter..
08/07/14
20140223257
Semiconducotr memory device including non-volatile memory cell array
A semiconductor memory device that may correct error data using an error correction circuit is disclosed. The semiconductor memory device may include a dram cell array, a parity generator, a nonvolatile memory cell array and an error correction circuit.
08/07/14
20140223256
Error detection and correction unit, error detection and correction method, information processor, and program
An error detection and correction unit includes: a first-code error detection section configured to detect whether or not each of a plurality of first code words in a second code word has an error, the second code word generated by encoding the plurality of first code words in chains and being a code word containing a plurality of partial data; and a second-code error correction section configured to correct the error in one partial data containing the first code word in which the error is detected of the plurality of partial data in the second code word, based on adjacent partial data adjacent to the one partial data.. .
08/07/14
20140223228
Memory system and error correction method
Disclosed is an error correcting method which includes detecting an error of meta data having a seed used to randomize user data; correcting the error of the meta data when the error is detected from the meta data; receiving the user data based upon seed confirmation information associated with an error existence of the seed or an error correction result of the seed; detecting an error of the user data; and correcting the error of the user data when the error is detected from the user data.. .
08/07/14
20140223224
Systems and methods for error correction in quantum computation
The effects of decoherence and/or noise in adiabatic quantum computation and quantum annealing are reduced by implementing replica coding schemes. Multiple instances of the same problem are mapped to respective subsets of the qubits and coupling devices of a quantum processor.
08/07/14
20140222420
Data processing method that selectively performs error correction operation in response to determination based on characteristic of packets corresponding to same set of speech data, and associated data processing apparatus
A data processing method for performing data processing on wireless received data and an associated data processing apparatus are provided, where the data processing method is applied to an electronic device. The data processing method includes the steps of: wirelessly receiving a plurality of packets corresponding to a same set of speech data from another electronic device; and selectively performing error correction operation on at least one of the plurality of packets to obtain the set of speech data, wherein whether to perform the error correction operation is determined according to at least one characteristic of the plurality of packets.
08/07/14
20140218172
Rfid systems with low complexity implementation and pallet coding error correction
Systems and methods for decoding data transmitted by rfid tags are disclosed. One embodiment of the invention includes an analyzer and equalizer configured to filter an input signal, an estimation block configured to obtain a baseband representation of the modulated data signal by mixing the filtered input signal with the carrier wave, and a coherent detector configured to perform phase and timing recovery on the modulated data signal in the presence of noise and to determine a sequence of data symbols..
07/31/14
20140215293
Transmission apparatus and transmission method
An encoding method and encoder of a time-varying ldpc-cc with high error correction performance are provided. In an encoding method of performing low density parity check convolutional coding (ldpc-cc) of a time varying period of q using a parity check polynomial of a coding rate of (n−1)/n (where n is an integer equal to or greater than 2), the time varying period of q is a prime number greater than 3, the method receiving an information sequence as input and encoding the information sequence using equation 1 as a g-th (g=0, 1, .
07/31/14
20140215289
Providing memory protection using a modified error correction code
Data and a corresponding initial error correction code is written to a first portion of a memory device. Based on an error in the first data and the initial error correction code, the initial error correction code is modified..
07/31/14
20140214401
Method and device for error correction model training and text error correction
A computer-implemented method is performed at a device having one or more processors and memory storing programs executed by the one or more processors. The method comprises: selecting a target word in a target sentence; from the target sentence, acquiring a first sequence of words that precede the target word and a second sequence of words that succeed the target word; from a sentence database, searching and acquiring a group of words, each of which separates the first sequence of words from the second sequence of words in a sentence; creating a candidate sentence for each of the candidate words by replacing the target word in the target sentence with each of the candidate words; determining the fittest sentence among the candidate sentences according to a linguistic model; and suggesting the candidate word within the fittest sentence as a correction..
07/31/14
20140214354
System and method of detection and analysis for semiconductor condition prediction
The invention described here enables in-operation, low-cost, non-invasive measurement of component performance and condition for assessing device longevity prediction, resilience and reliability. The non-invasive component measurements to be performed and subsequently evaluated are based on at least a set of physically unclonable functions and other measurements which can be error corrected, and the error correction factor and other measurements provides insight to the device condition.
07/24/14
20140208182
Controller, information processing system, method of controlling controller, and program
A controller includes: a low-level error correction section configured to execute low-level error correction in which an error in a code word is corrected with use of a predetermined decoding algorithm; and a high-level soft-decision error correction section configured to execute high-level soft-decision error correction in which the error in the code word is corrected with use of a high-level algorithm when the error correction by the low-level error correction section has failed, the high-level algorithm being a soft-decision decoding algorithm having higher error correction capability than error correction capability of the predetermined decoding algorithm.. .
07/24/14
20140208146
Time protocol latency correction based on forward error correction status
One embodiment provides a method for time protocol latency correction based on forward error correction (fec) status. The method includes determining, by a network node element, if a forward error correction (fec) decoding mode is enabled or disabled for a packet received from a link partner in communication with the network node element.
07/24/14
20140205022
Method and apparatus for transporting an 8b/10b coded video stream across a 64b/66b coded link
A video transport system is provided for transporting as 8b/10b coded video stream across a 64b/66b coded link, wherein forward error correction is provided without the overhead of the prior art. The system also provides a system with the ability to recover 64b/66b encoded blocks that have corrupt sync bits..
07/24/14
20140204437
Dynamic aperture holographic multiplexing
Systems and methods for dynamic aperture holographic multiplexing are disclosed. One example process may include recording a set of holograms in a recording medium by varying both the reference beam angular aperture and the signal beam angular aperture.
07/17/14
20140201604
Methods and systems for 2-dimensional forward error correction coding
A communication system and a method are disclosed. The communication system includes an encoder configured to encode source data and output an encoded frame including a plurality of rows and a plurality of columns.
07/17/14
20140201603
Systems, methods, apparatus, and computer program products for providing forward error correction with low latency
Systems, methods, apparatus, and computer program products for providing forward error correction with low latency to live streams in networks are provided. One example method includes receiving source data at a first rate, outputting the source data at a rate less than the first rate, collecting the source data in a buffer, fec decoding the source data, thereby generating decoded data; and outputting the decoded data at a rate equal to the first rate, either after collecting the source data in the buffer for a predetermined time duration or after collecting a predetermined amount of the source data in the buffer..
07/17/14
20140201599
Error protection for integrated circuits in an insensitive direction
A method for providing error detection, or error detection combined with error correction, to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding an error control mechanism to the array of storage cells in the insensitive direction. The insensitive direction is a direction perpendicular to a width of a gate conductor of the storage cells..
07/17/14
20140201597
Error correction with extended cam
A memory system includes a memory and a content addressable memory (cam). The memory includes a plurality of address locations, wherein each address location configured to store data and one or more error correction bits corresponding to the data.
07/17/14
20140201596
Adaptation of analog memory cell read thresholds using partial ecc syndromes
A method includes storing data that is encoded with an error correction code (ecc) in a group of analog memory cells. The memory cells in the group are read using multiple sets of read thresholds.
07/17/14
20140201589
Shared error protection for register banks
A method for adding error detection, or error detection combined with error correction, to a plurality of register banks includes grouping the plurality of register banks into an array. The method also includes adding a first error control mechanism to the array in a first direction and adding a second error control mechanism to the array in a second direction.
07/17/14
20140200843
Apparatus and methods thereof for error correction in split core current transformers
Apparatus and methods are provided for electrical parameter measurements at points of interest, such as circuit breakers, machines, and the like. The devices which comprise of components that may require corrections, such as the errors induced by, but not limited to, the use of a split core mounted around a current carrier, and hence calibration coefficients are provided based on test, measurements and/or calculations respective of the devices.
07/17/14
20140198874
Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals
The object of the present invention can be achieved by providing a method of transmitting broadcast signals including encoding data pipe, dp, data, wherein the encoding further includes forward error correction, fec, encoding the dp data, bit interleaving the fec encoded dp data and mapping the bit interleaved dp data onto constellations; building at least one signal frame by mapping the encoded dp data; and modulating data in the at least one built signal frame by an orthogonal frequency division multiplexing, ofdm, method and transmitting the broadcast signals having the modulated data, wherein each of the at least one signal frame includes at least one preamble having repeated at least one signaling information.. .
07/17/14
20140198573
Memory system and method of operation thereof
A method of operating a memory system including a non-volatile memory device and a memory controller controlling the non-volatile memory device, includes reading data from a memory cell array in a unit of a page which includes a plurality of sectors; performing error correction decoding on the read data in a unit of a sector of the page; selecting at least one target sector which includes at least one uncorrectable error and selecting at least one pass sector wherein all errors of the pass sector are correctable by the error correction decoding; inhibiting precharging of bit-lines connected to the at least one pass sector while precharging target bit lines connected to the at least one target sector; and performing a read retry operation for data in the at least one target sector.. .
07/10/14
20140195880
Rate matching and scrambling techniques for control signaling
Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes an input padding module configured to provide padded bits having padding bits added to payload bits for one or more control channels, and a scrambling module configured to apply a masking sequence to one or more of the padded bits to generate scrambled bits.
07/10/14
20140195879
Apparatus for transmitting broadcasting signal, apparatus for receiving broadcasting signal, and method for transmitting/receiving broadcasting signal through apparatus for transmitting/receiving broadcasting signal
A transmitter and method of processing broadcast data are discussed. In one embodiment, the method includes forward error correction (fec) encoding physical layer pipe (plp) data at a first code rate; fec encoding first signaling data at a second code rate; fec encoding second signaling data at a third code rate; time interleaving the fec-encoded plp data; frequency interleaving the time-interleaved plp data by a pair of consecutive cells; and modulating the frequency-interleaved plp data, the fec-encoded first signaling data, and the fec-encoded second signaling data by an orthogonal frequency division multiplexing (ofdm) method, wherein the first signaling data include fec type information of the second signaling data and wherein the second signaling data include fec type information and the first code rate used by the plp data..
07/10/14
20140195872
Simultaneous data transfer and error control to reduce latency and improve throughput to a host
The disclosed embodiments provide a system that transfers data from a storage device to a host. The system includes a communication mechanism that receives a request to read a set of blocks from the host.
07/10/14
20140195867
Memory testing with selective use of an error correction code decoder
A method includes directing an access of a memory location of a memory device to an error correction code (ecc) decoder in response to receiving a test activation request indicating the memory location. The method also includes writing a test pattern to the memory location and reading a value from the memory location.
07/10/14
20140195226
Method and apparatus for correcting error in speech recognition system
A method of correcting errors in a speech recognition system includes a process of searching a speech recognition error-answer pair db based on a sound model for a first candidate answer group for a speech recognition error, a process of searching a word relationship information db for a second candidate answer group for the speech recognition error, a process of searching a user error correction information db for a third candidate answer group for the speech recognition error, a process of searching a domain articulation pattern db and a proper noun db for a fourth candidate answer group for the speech recognition error, and a process of aligning candidate answers within each of the retrieved candidate answer groups and displaying the aligned candidate answers.. .
07/10/14
20140192920
Method and apparatus for data transmission using multiple transmit antennas
A method and apparatus for increasing the data rate and providing antenna diversity using multiple transmit antennas utilize a set of bits of a digital signal to generate a codeword. Delay elements may be provided in antenna output channels, or, with suitable code construction, delay may be omitted.
07/03/14
20140189473
Apparatus and method for fast tag hit with double error correction and triple error detection
A method is described that includes reading a cache tag and the cache tag's corresponding ecc from storage circuitry of a cache. The method also includes generating an ecc for a search tag.
07/03/14
20140189472
Efficient cache search and error detection
A first codeword may be constructed from a cache tag in a cache and an error correction code corresponding to the cache tag. A second codeword may be constructed from a search tag and an error correction code corresponding to the search tag.
07/03/14
20140189471
Dtv transmitting system and receiving system and method of processing broadcast signal
A television transmitting system includes an encoder, a data randomizing and expanding unit, a group formatter, a deinterleaver, and a packet formatter. The encoder codes enhanced data for error correction, permutes the coded data, and further codes the permuted data for error detection.
07/03/14
20140189469
Nonvolatile memory devices with age-based variability of read operations and methods of operating same
Integrated circuit memory systems and methods include comparing a number of erase cycles of a memory block corresponding to a read request to a first value and reading data stored in the memory block according to a first read condition corresponding to a first reliability improvement operation when the number of erase cycles of the memory block is less than the first value. An error of the data read according to the first read condition may be corrected using an error correction code (ecc) when the error of the data read according to the first read condition is correctable..
07/03/14
20140189462
Error correcting device, method for monitoring an error correcting device and data processing system
An error correcting device is provided that has an input connectable to receive one or more data units, an error detection module arranged to identify a presence of one or more errors in a received data unit of the one or more data units and to provide an error detection signal for the received data unit, an error correction module arranged to perform an error correction processing on the received data unit and provide a corrected data unit, and a correction evaluation module arranged to perform a comparison of the received data unit with the corrected data unit and to generate a correction error signal depending on a result of the comparison and the error detection signal.. .
07/03/14
20140189459
Method and system for operating a communication circuit configurable to support one or more data rates
A method and system for operating a communication circuit that is configurable to support one or more communication standards on a single device. The communication circuit includes a transmitting device that comprises a pcs module operating at a first data rate, and a second pcs module operating at a second data rate.
07/03/14
20140189446
Forward error correction with configurable latency
A method of performing forward error correction with configurable latency, where a configurable latency algorithm evaluates a target bit error rate (ber) against an actual ber and adjusts the size of a configurable buffer such that the target ber may be achieved when utilizing the smallest buffer size possible. When errors are corrected without the utilization of each of the configurable buffer locations, the algorithm reduces the size of the buffer by y buffer locations; the algorithm may continue to successively reduce the size of said buffer until the minimum number of buffer locations are utilized to achieve the target ber.


Popular terms: [SEARCH]

Error Correction topics: Error Correction, Memory Device, Volatile Memory, Memory Cell, Semiconductor, Semiconductor Memory, Forward Error Correction, Flash Memory, Memory Cells, Data Storage, Viterbi Algorithm, Provisioning, Data Packet, Multimedia, Allocation

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