FreshPatents.com Logo
Enter keywords:  

Track companies' patents here: Public Companies RSS Feeds | RSS Feed Home Page
Popular terms

[SEARCH]

Enable Signal topics
Enable Signal
Control Unit
Electronic Device
Integrated Circuit
Semiconductor
Output Enable
Liquid Crystal
Liquid Crystal Display
Data Transfer
Buffer Circuit
Esd Protection Circuit
Protection Circuit
Electrostatic Discharge
Esd Protection
Programmable Memory

Follow us on Twitter
twitter icon@FreshPatents

Web & Computing
Cloud Computing
Ecommerce
Search patents
Smartphone patents
Social Media patents
Video patents
Website patents
Web Server
Android patents
Copyright patents
Database patents
Programming patents
Wearable Computing
Webcam patents

Web Companies
Apple patents
Google patents
Adobe patents
Ebay patents
Oracle patents
Yahoo patents

[SEARCH]

Enable Signal patents



      
           
This page is updated frequently with new Enable Signal-related patent applications. Subscribe to the Enable Signal RSS feed to automatically get the update: related Enable RSS feeds. RSS updates for this page: Enable Signal RSS RSS


Signal generating circuit, optical signal transmitting apparatus, signal receiving circuit, method for establishing…

Nippon Telegraph And Telephone

Signal generating circuit, optical signal transmitting apparatus, signal receiving circuit, method for establishing…

Signal generating circuit, optical signal transmitting apparatus, signal receiving circuit, method for establishing…

Nippon Telegraph And Telephone

Signal generating circuit, optical signal transmitting apparatus, signal receiving circuit, method for establishing…

Signal generating circuit, optical signal transmitting apparatus, signal receiving circuit, method for establishing…

Samsung Electronics

Display apparatus, power supply control apparatus and method for controlling thereof

Date/App# patent app List of recent Enable Signal-related patents
03/26/15
20150085566
 Input trigger independent low leakage memory circuit patent thumbnailnew patent Input trigger independent low leakage memory circuit
Wordline-driver biasing and column-based source-biasing circuitry facilitate reduced current leakage, for example, in soc device sram circuits in a manner that is independent of the read/write/standby operating mode, and without an external trigger. Wordline-driver-biasing circuitry turns off (i.e., decouples from system power) wordline-drivers that are connected to unselected wordlines during read/write operations using one of a decoder-enable signal, which is generated in response to row address values, or based on the activation of a self-timing internal clock, which is generated by the memory circuit when it is activated (i.e., switched from standby to read/write mode).
Synopsys, Inc.
03/19/15
20150078765
 Signal generating circuit, optical signal transmitting apparatus, signal receiving circuit,  establishing optical signal synchronization, and optical signal synchronization system patent thumbnailSignal generating circuit, optical signal transmitting apparatus, signal receiving circuit, establishing optical signal synchronization, and optical signal synchronization system
To enable signal position detection, frequency offset compensation, clock offset compensation, and chromatic dispersion amount estimation in a communication system based on coherent detection using an optical signal, even on a signal having a great offset in an arrival time depending on a frequency due to chromatic dispersion. An optical signal transmitting apparatus generates specific frequency band signals having power concentrated on two or more specific frequencies and transmits a signal including the specific frequency band signals.
Nippon Telegraph And Telephone Corporation
03/19/15
20150078762
 Signal generating circuit, optical signal transmitting apparatus, signal receiving circuit,  establishing optical signal synchronization, and optical signal synchronization system patent thumbnailSignal generating circuit, optical signal transmitting apparatus, signal receiving circuit, establishing optical signal synchronization, and optical signal synchronization system
To enable signal position detection, frequency offset compensation, clock offset compensation, and chromatic dispersion amount estimation in a communication system based on coherent detection using an optical signal, even on a signal having a great offset in an arrival time depending on a frequency due to chromatic dispersion. An optical signal transmitting apparatus generates specific frequency band signals having power concentrated on two or more specific frequencies and transmits a signal including the specific frequency band signals.
Nippon Telegraph And Telephone Corporation
03/19/15
20150077410
 Display apparatus, power supply control  controlling thereof patent thumbnailDisplay apparatus, power supply control controlling thereof
A display apparatus is provided. The display apparatus includes an interface configured to receive a data enable signal and a data signal, a power supply configured to supply power to an internal component, and a controller configured to determine whether to supply power to the internal component based on whether the data enable signal is received from an external apparatus through the interface, and configured to control the power supply to supply the power to the internal component based on the determination..
Samsung Electronics Co., Ltd.
03/19/15
20150077187
 Dynamic error vector magnitude duty cycle correction patent thumbnailDynamic error vector magnitude duty cycle correction
Aspects of this disclosure relate to dynamic error vector magnitude (devm) compensation. In one embodiment, an apparatus includes an amplifier, a low pass filter, and a bias circuit.
Skyworks Solutions, Inc.
03/12/15
20150074331
 Nonvolatile memory package and nonvolatile memory chip patent thumbnailNonvolatile memory package and nonvolatile memory chip
A nonvolatile memory package of an embodiment includes: a data terminal configured to receive a write command for a data; a first ce terminal; a second ce terminal; a ce selection terminal; and a selector coupled to the first ce terminal and the second ce terminal. The selector outputs one of a first chip-enable signal and a second chip-enable signal based on a ce selection signal.
Kabushiki Kaisha Toshiba
03/12/15
20150070976
 Semiconductor device patent thumbnailSemiconductor device
There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an sram memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation.
Renesas Electronics Corporation
03/12/15
20150070335
 Pixel selection control method, driving circuit, display apparatus and electronic instrument patent thumbnailPixel selection control method, driving circuit, display apparatus and electronic instrument
A pixel selection control method, driving circuit, display apparatus and electronic instrument are disclosed. A driving circuit includes a logic circuit configured to receive a reference signal associated with a line of pixels.
Sony Corporation
03/12/15
20150070334
 Pixel selection control method, driving circuit, display apparatus and electronic instrument patent thumbnailPixel selection control method, driving circuit, display apparatus and electronic instrument
A pixel selection control method, driving circuit, display apparatus and electronic instrument are disclosed. A driving circuit includes a logic circuit configured to receive a reference signal associated with a line of pixels.
Sony Corporation
03/12/15
20150070068
 Internal voltage generator and  generating internal voltage patent thumbnailInternal voltage generator and generating internal voltage
An internal voltage generator includes an internal voltage control unit suitable for generate an enable signal based on a voltage level of an internal voltage, a clock control unit suitable for generate a control clock having a restricted toggling period based on the enable signal and a clock while controlling the toggling number of the control clock, and an internal voltage generation unit suitable for generate the internal voltage based on the control clock.. .
Sk Hynix Inc.
03/05/15
20150067423

A q-gating cell architecture to satiate the launch-off-shift (los) testing and an algorithm to identify best q-gating candidates


A method for creating an architecture to support q-gating for launch-off-shift (los) scan testing using a plurality of flip-flops is provided. The method may include applying a common clock signal to each clock input of the plurality of flip-flops and applying a gated scan enable signal to each scan enable input of the plurality of flip-flops.
International Business Machines Corporation
03/05/15
20150063051

Low power protection circuit


The present invention provides the low power protection circuit including a first voltage detector, a pulse generating circuit, a sr latch, and an output logic operation circuit. The low power protection circuit is adapted for a dynamic random access memory (dram) with dual operating voltages.
Nanya Technology Corporation
03/05/15
20150063044

Strobe signal generation device and memory apparatus using the same


A strobe signal generation device includes an enable signal generating section, a buffering section and a strobe signal driving section. The enable signal generation section generates a division enable signal in response a strobe signal.
Sk Hynix Inc.
03/05/15
20150062979

Constant voltage constant current control circuits and methods with improved load regulation


The present invention discloses cvcc circuits and methods with improved load regulation for an smps. In one embodiment, the cvcc can include: a voltage feedback circuit to generate an output voltage feedback signal; a current feedback circuit to generate an output current feedback signal; a control signal generating circuit that receives the output voltage feedback signal and the output current feedback signal, and generates a constant voltage/constant current control signal; a first enable signal generating circuit that compares a first reference voltage and the constant voltage/constant current control signal to generate a first enable signal; and a pwm controller that generates a pwm control signal based on the constant voltage/constant current control signal to control a main switch of the flyback smps..
Silergy Semiconductor Technology (hangzhou) Ltd
03/05/15
20150062212

Element substrate, printhead, and printing apparatus


An element substrate capable of suppressing occurrence of electromagnetic noise upon driving printing elements on an element substrate with long wiring lengths, preventing an operation error, and printing a high-quality image is provided. In the element substrate, plural element substrates each including printing elements are arrayed in an arrayed direction of the printing elements.
Canon Kabushiki Kaisha
03/05/15
20150061734

Interface circuit


According to one embodiment, a first pull-down transistor, a mode switching circuit, and a leak-cut circuit are provided. The first pull-down transistor pulls down an input/output terminal.
Kabushiki Kaisha Toshiba
03/05/15
20150061710

Semiconductor apparatus and test method


A test driver selection unit configured to enable a plurality of test driver selection signals in response to a test pulse and a test clock, and a plurality of drivers configured to receive the plurality of test driver selection signals, wherein each of the plurality of drivers is configured to output an output signal to a data bump in response to a test driver selection signal, data, and an output enable signal, and to receive a first driving voltage and a second driving voltage.. .
Sk Hynix Inc.
02/26/15
20150058690

Scan test circuit with scan clock


A scan test circuit includes: a pulse generator, for generating differential pulses according to a system clock signal; a functional path, including: a d-type latch clocked by the differential pulses; a test path, including: a scan latch clocked by a test clock signal; and a tri-state inverter. When a test enable signal is enabled, the generation of the differential pulses is disabled..
Mediatek Singapore Pte. Ltd.
02/26/15
20150058685

Method and system of testing semiconductor memory


A method of testing a semiconductor memory includes generating a logical value of a test pattern through an algorithm pattern generator included in a field programmable gate array. The generated logical value is programmed in a dut under the control of a dq signal responding to a dq enable signal that is generated from automatic test equipment and is then transferred to the field programmable gate array.
Samsung Electronics Co., Ltd.
02/26/15
20150055426

Novel sense amplifier scheme


A sense amplifier circuit comprising a pair of cross-coupled inverters and a data line charging circuit is disclosed. The cross-coupled inverters comprise a first inverter and a second inverter.
Taiwan Semiconductor Manufacturing Company Limited
02/26/15
20150055422

Semiconductor memory apparatus


A semiconductor memory apparatus includes a driving current control block configured to sense a resistance value of a dummy memory element, and generates a write driver control signal; and a write driving block configured to provide a driving voltage to a memory cell array in response to a write driver enable signal and the write driver control signal.. .
Sk Hynix Inc.
02/26/15
20150055415

Controller


According to one embodiment, controller includes a phase comparator that receives a data strobe signal outputted from a memory in response to a read enable signal, and a delayed data strobe signal formed by applying a delay to the data strobe signal, and outputs a result of comparison between phases of two signals. The controller also includes a duty control unit that corrects a duty of the read enable signal outputted to the memory based upon the comparison result of the phase comparator..
Kabushiki Kaisha Toshiba
02/26/15
20150055390

Content addressable memory


The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each cam cell of a cam memory array via a search line pair.
Renesas Electronics Corporation
02/26/15
20150054718

Pixel circuit and display device using the same


Exemplary embodiments of the present invention relates to a pixel circuit for displaying an image of uniform luminance. The pixel circuit comprising an organic light emitting diode (oled), an rs trigger comprising a first terminal connected to a scan line, a second terminal connected to an enable line, and a third terminal connected to a data line, the rs trigger configured to generate an output signal according to an enable signal, a data signal, and a scan signal respectively received via the enable line, the data line, and the scan line, and a driving transistor comprising a first electrode connected to a first power source, a second electrode connected to an anode of the oled, and a gate electrode connected to an output terminal of the rs trigger, the driver transistor configured to control a current flowing through the oled in response to the output signal of the rs trigger..
Samsung Display Co., Ltd.
02/19/15
20150052317

Systems, devices, memory controllers, and methods for memory initialization


Systems, devices, memory controllers, and methods for initializing memory are described. Initializing memory can include configuring memory devices in parallel.
Micron Technology, Inc.
02/19/15
20150048894

Delay line ring oscillation apparatus


The delay line degradation protection architecture as build-in ring oscillation apparatus includes a two gates logical circuit, a buffer, a clock input buffer and a delay lock loop circuit. The two gates logical circuit receives a clock enable signal, specific mode signal, and delayed clock output signal.
Nanya Technology Corporation
02/19/15
20150048876

Semiconductor circuit


Provided is a semiconductor circuit. The semiconductor circuit includes: an input node configured to receive an enable signal, a sense enable signal, and a clock signal; and a clock gating circuit configured to output an enable clock signal corresponding to the clock signal while a signal level of the enable signal is at a first level regardless of a signal level of the sense enable signal, when the semiconductor circuit is in a high-voltage mode, and output an enable clock signal corresponding to the clock signal while a signal level of at least one of the enable signal and the sense enable signal is at the first level, when the semiconductor circuit is in a low-voltage mode..
Samsung Electronics Co., Ltd.
02/12/15
20150043616

Circuits and methods for pulse radio receivers


Circuits and methods comprising: a radio frequency amplifier that powers off in response to an enable signal; a demodulator that outputs an rz signal; an all-digital clock and data recovery circuit comprising: a phase detector that includes a tri-state phase frequency detector for use when in an acquisition mode and a hogge phase detector for use when in a communication mode, that receives the rz signal, and that outputs a phase detector output from the tri-state phase frequency detector when in the acquisition mode and from the hogge phase detector when in the communication mode, a loop filter that receives the phase detector output from the phase detector and produces a loop filter output that is the sum of a proportional path of the loop filter and an integral path of the loop filter, and a numerical controlled oscillator that receives the loop filter output and produces the enable signal.. .
02/12/15
20150043289

Semiconductor memory device


A semiconductor memory device includes a pad configured to receive a first write data from outside of the semiconductor memory device, and a write circuit configured to generate a plurality of second write data which are to be written in memory cells of all banks to be tested in response to a test mode signal, data strobe signals, a write enable signal, and the first write data transferred through the pad.. .
Sk Hynix Inc.
02/12/15
20150043285

Interfaces and die packages, and appartuses including the same


A memory device includes a memory die package including a plurality of memory dies, an interface device including an interface circuit, and a memory controller configured to control the interface with control data received from at least one of the plurality of memory dies. The interface device of the memory device is configured to divide and multiplex an io channel between the memory die package and the memory controller into more than one channel using the control data receive from the at least one of the plurality of memory dies.
Micron Technology, Inc.
02/12/15
20150042388

Semiconductor memory apparatus


A semiconductor memory apparatus includes an enable signal generation unit configured to be inputted with a plurality of clocks which have different phases, and generate a plurality of enable signals; and a plurality of sampling units configured to output input data as sampling data in response to respective pairs of clocks of the plurality of clocks and respective ones of the plurality of enable signals.. .
Sk Hynix Inc.
02/05/15
20150039956

Test mux flip-flop cell for reduced scan shift and functional switching power consumption


A new flip-flop cell that is more efficient in scan chain configuration includes a multiplexer, storage element (e.g., a flip-flop), an inverter, and multiple logic gates. The flip-flop cell is configured to receive both a test signal and a data input signal and select one of the two to pass to the storage element based on a scan enable signal that indicates either a capture mode or a scan shift mode.
Stmicroelectronics Asia Pacific Pte. Ltd.
02/05/15
20150036783

Device and generating input control signals of a serialized compressed scan circuit


A device and a method for generating input control signals of a serialized compressed scan circuit are provided. A control signal generating device receives a test clock signal from a clock input port and a state enable signal from a state enable bus, and correspondingly generates a shift enable signal, a capture enable signal and a strobe signal.
Industrial Technology Research Institute
01/29/15
20150033360

Method and securing configuration scan chains of a programmable device


Scan chain circuitry on an integrated circuit device includes a plurality of memory elements, and a plurality of control elements. Each of the control elements is located between respective ones of the plurality of memory elements for controllably connecting the plurality of memory elements into a scan chain.
Altera Corporation
01/29/15
20150029372

Image sensor and controlling the same


Provided is an image sensor including a sensor array including a plurality of pixels arranged in rows and columns. The image sensor may include a ramp signal generator which may generate a ramp signal.
Samsung Electronics Co., Ltd.
01/29/15
20150028190

Counter circuit, analog-to-digital converter, and image sensor including the same and correlated double sampling


A counter circuit includes a first counter and a second counter. The first counter is configured to count a first counter clock signal which toggles with a first frequency to generate upper (n−m)-bit signals of n-bit counter output signals, in response to a first counting enable signal based on a first comparison signal during a coarse counting interval.
01/22/15
20150023144

Method and system for measuring noise of a magnetic head


A method for measuring noise of a magnetic head includes setting a plurality of threshold values, applying bias current or voltage to a read element of the magnetic head, applying an external transverse magnetic field to the magnetic head, amplifying output signal from the read element to produce an amplified signal, filtering the amplified signal to produce a filtered signal, generating an enable signal for each threshold value in a predetermined time window by a counting control means with input signals which include the filtered signal and the threshold value, measuring the cumulative time duration of each enable signal, making an amplitude-duration distribution according to the cumulative time durations and the threshold values, calculating a plurality of parameters according to the amplitude-duration distribution and analyzing the parameters with a plurality of predetermined criteria to determine the defects of the magnetic head. Accordingly, the invention also discloses a system for measuring noise of a magnetic head..
Sae Magnetics (h.k.) Ltd.
01/22/15
20150022428

Shift register circuit


A shift register circuit for driving an oled display panel is provided. The shift register circuit includes a plurality of circuit stages connected in series.
Au Optronics Corp.
01/22/15
20150022235

Semiconductor device


The disclosed invention provides a semiconductor device capable of suitably controlling the level of an enable signal to resolve nbti in a pmos transistor. An input node receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby.
Renesas Electronics Corporation
01/15/15
20150019607

Interpolation filter based on time assignment algorithm


Disclosed is an interpolation filter based on time assignment algorithm. An interpolation filter comprises an enable signal generating part generating enable signals for operation of the interpolation filter, an input value generating part generating input values, a first calculating part generating a first output value based on a first enable signal and a first input value, a second calculating part generating a second output value based on a second enable signal and a second input value, and an output value selecting part selecting a final output value among the first output value and the second output value.
Electronics And Telecommunications Research Institute
01/15/15
20150016196

Data input circuit


A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal clock during a burst period from substantially a time when the pulse of the shifting signal is generated.
Sk Hynix Inc.
01/15/15
20150015566

Driving apparatus of display


A driving apparatus of a display is disclosed. The driving apparatus includes a digital-to-analog converter (dac) circuit, an output buffer circuit and a pre-charge circuit.
Novatek Microelectronics Corp.
01/15/15
20150015310

Clock delay detecting circuit and semiconductor apparatus using the same


Provided is a clock delay detecting circuit and semiconductor apparatus using the same that is capable of generating a period signal whose period is a delay time of a clock, dividing the period signal, and counting the divided period signal. The clock delay detection circuit comprises a period signal generating unit configured to generate a counting control signal, a period signal dividing unit configured to generate a counting enable signal by dividing the counting control signal, and a counting unit configured to generate a delay information signal by counting the counting enable signal with a clock, wherein the counting control signal has a period with a predetermined time..
Sk Hynix Inc.
01/15/15
20150014779

Switch supporting voltages greater than supply


Devices for isolating an input from an output are disclosed. For example, a device includes a first p-type metal oxide semiconductor transistor and a first circuit.
Xilinx, Inc.
01/08/15
20150012791

Parallel test device and method


A parallel test device and method are disclosed, which relates to a technology for performing a multi-bit parallel test by compressing data. The parallel test device includes: a pad unit through which data input/output (i/o) operations are achieved; a plurality of input buffers configured to activate write data received from the pad unit in response to a buffer enable signal, and output the write data to a global input/output (gio) line; a plurality of output drivers configured to activate read data received from the global i/o (gio) line in response to a strobe delay signal, and output the read data to the pad unit; and a test controller configured to activate the buffer enable signal and the strobe delay signal during a test mode in a manner that the read data received from the plurality of output drivers is applied to the plurality of input buffers such that the read data is operated as the write data..
Sk Hynix Inc.
01/01/15
20150003122

Power converter for reducing standby power consumption


There is provided a power converter for reducing standby power consumption. The power converter includes a rectifier configured to rectify ac power into dc power, a transformer configured to output power by converting a voltage of dc power rectified by the rectifier, a pwm control module configured to control an output power by switching a power switching device connected to the transformer, a first external switch configured to provide a disable signal, a first capacitor that is connected in parallel to one side of the first external switch, a second external switch configured to provide an enable signal, and a second capacitor that is connected in parallel to one side of the second external switch..
Magnachip Semiconductor, Ltd.
01/01/15
20150002495

System and providing a multi-mode embedded display


An information handling system includes a display panel, a panel connector, and a source device. The display panel displays images at different resolutions.
Dell Products, Lp
01/01/15
20150002052

Automatic input impedence control


The present disclosure is directed to an input impedance control circuit. In one embodiment, the automatic input impedance control circuit includes a circuit controller that comprises a module for calculating an impedance and a control logic module, wherein the control logic module provides a current enable signal and a current control output signal, a driver in communication with the circuit controller for receiving the current enable signal and the current control output signal, an input voltage sensing circuit in communication with the module for calculating the impedance and the control logic module and an input current sensing circuit in communication with the module for calculating the impedance..
Dialight Corporation
12/25/14
20140375627

Display device and driving method thereof


A display device and driving method thereof are disclosed. In one aspect, the display device includes a display panel displaying a still image and a moving image and a signal control unit controlling signals for driving the display panel and controlling a frequency of the display panel based on a low frequency enable signal.
Samsung Display Co., Ltd.
12/25/14
20140375626

Semiconductor device, display device, and signal loading method


The present invention provides a drive ic, a display device and a loading method that enable signals of different differential formats to be loaded without resulting in circuit redundancy. Namely, a drive ic includes an input section, a holding section, a selection section, and an output section.
Lapis Semiconductor Co., Ltd.
12/25/14
20140375620

Display apparatus and source driver thereof


A display apparatus and a source driver thereof are disclosed. The source driver includes a temperature sensor and a power switch.
Novatek Microelectronics Corp.
12/25/14
20140375360

Source driver with reduced number of latch devices


A source driver with reduced number of latch devices includes a master latch device and at least one slave latch device. The master latch device has a first transmission gate, a first inverter, a second inverter, a first enable gate, and a second enable gate.
Orise Technology Co., Ltd.
12/25/14
20140374923

Semiconductor apparatus and semiconductor system


Provided is a semiconductor apparatus including a plurality of semiconductor chips coupled through an electrical coupling unit. Each of the semiconductor chips includes: a chip id signal generation unit configured to generate a chip id signal; and a chip enable signal generation unit configured to receive a clock enable signal in response to the chip id signal, wherein one of the semiconductor chips shares the received clock enable signal as a transfer clock enable signal with the other semiconductor chips, and the chip enable signal generation unit detects whether or not an error occurs in the chip id signals of the plurality of semiconductor chips, selects any one of the transfer clock enable signal and the clock enable signal applied, and outputs the selected signal as a chip enable signal..
Sk Hynix Inc.
12/18/14
20140372648

Multi master arbitration scheme in a system on chip


A multi master system on chip (soc) includes a plurality of masters comprising a first master and a second master, each configured to generate a request. A next state generator in the multi master soc is configured to generate a next state of a round robin pointer in response to the request and a current state of the round robin pointer.
Texas Instruments Incorporated
12/18/14
20140369106

Semiconductor device with fuse array and operating method thereof


A semiconductor device includes a fuse array for storing normal fuse data and pattern data through a programming operation, a boot-up control unit suitable for generating an enable signal for enabling an output of the pattern data, and a pattern detection unit suitable for detecting a pattern of the pattern data in response to the enable signal, and generating a detection signal. The fuse array outputs the normal fuse data in response to the detection signal..
Sk Hynix Inc.
12/18/14
20140368480

Thin film transistor array substrate and driving method therefor as well as liquid crystal display


A thin film transistor array substrate, a driving method therefore, and a liquid crystal display are disclosed. The thin film transistor array substrate includes at least a sub-pixel region formed by a gate line and a data line intersected with each other, wherein, each sub-pixel comprises a first transistor (21) of which the gate is connected with a gate line and the drain is connected with a data line and a first storage capacitor (23) of which one end is connected with the source of the first transistor (21) and the other end is connected with an output of a reference voltage, the sub-pixel further comprises a second storage capacitor (24) and a second transistor (25), wherein one end of the second storage capacitor (24) is connected with the source of the first transistor (21), and the other end of the second storage capacitor (24) is connected with the drain of the second transistor (25); the source of the second transistor (25) is connected with the output of the reference voltage, and the gate of the second transistor (25) is connected with an output of an enable signal.
Boe Technology Group Co., Ltd.
12/18/14
20140368241

Clock control device


A clock control device is disclosed, which relates to a technology for reducing the amount of current consumption when a semiconductor device operates at a high speed. The clock control device includes: a chip-select-signal control block configured to generate a chip-select-control signal by latching a chip select signal, and output a fast chip select signal according to the chip-select-control signal; and a clock control block configured to drive a clock signal in response to the fast chip select signal when a command clock enable signal is activated, thereby generating a clock control signal, wherein the chip-select-signal control block latches the chip-select-control signal, and controls the chip-select-control signal to be toggled after the command clock enable signal is transitioned..
Sk Hynix Inc.
12/18/14
20140367551

Double data rate counter, and analog-digital converting appratus and cmos image sensor using the same


A double data rate (ddr) counter includes a clock selection unit suitable for selectively inverting a first counting clock based on a control signal and for outputting a second counting clock, a first latch stage suitable for latching the second counting clock based on a counting enable signal and for outputting the least significant bit (lsb) of the ddr counter, a determination unit suitable for generating the control signal based on the last bit state of the lsb in a reset counting period, and a second latch stage suitable for receiving the lsb as a clock input to generate a higher bit of the lsb at least in a main counting period.. .
Sk Hynix Inc.
12/11/14
20140362654

Redundancy evaluation circuit for semiconductor device


A redundancy evaluation circuit has (m+1) fuse boxes and a comparator, wherein the m fuse box output a fuse status address signal and the other one fuse box outputs a comparator enable signal. Each fuse box has a common stage circuit and k redundant cells.
12/11/14
20140361830

Envelope tracker with variable boosted supply voltage


Techniques for efficiently generating a variable boosted supply voltage for an amplifier and/or other circuits are disclosed. In an exemplary design, an apparatus includes an amplifier, a boost converter, and a boost controller.
12/11/14
20140361610

Voltage regulator, operation method thereof, voltage regulating system, and mobile vehicle


A voltage regulator, an operation method thereof, and a voltage regulating system, and a mobile vehicle are provided. The voltage regulator coupled to an alternator and a battery includes a voltage detection unit which is coupled to the alternator and a startup assisting unit.
12/11/14
20140361608

Redundant power supply circuit, power over ethernet system, and method


A redundant power supply circuit includes a port detection circuit, a fixed state detection circuit, a voltage conversion circuit, and a control circuit. The port detection circuit detects and outputs a plurality of ready signals according to a plurality of power signals of a number of poe ports.
12/04/14
20140359388

Core circuit test architecture


A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths.
12/04/14
20140359336

Server and power chip detecting method


A power chip detecting device, applied in a server, includes a power chip, a power sequence control module, a base management controller, a gpio module, and a signal detecting module. The power sequence control module sends an initial power enable signal to the power chip after the server is switched on, and the power sequence control module receives an initial power good signal from the power chip after the power chip receives the initial power enable signal.


Popular terms: [SEARCH]

Enable Signal topics: Enable Signal, Control Unit, Electronic Device, Integrated Circuit, Semiconductor, Output Enable, Liquid Crystal, Liquid Crystal Display, Data Transfer, Buffer Circuit, Esd Protection Circuit, Protection Circuit, Electrostatic Discharge, Esd Protection, Programmable Memory

Follow us on Twitter
twitter icon@FreshPatents

###

This listing is a sample listing of patent applications related to Enable Signal for is only meant as a recent sample of applications filed, not a comprehensive history. There may be associated servicemarks and trademarks related to these patents. Please check with patent attorney if you need further assistance or plan to use for business purposes. This patent data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Enable Signal with additional patents listed. Browse our RSS directory or Search for other possible listings.
     SHARE
  
         











0.3349

3476

2 - 1 - 71