|| List of recent Enable Signal-related patents
| Domain crossing circuit of semiconductor apparatus|
A domain crossing circuit of a semiconductor apparatus includes a delay-locked loop block configured to generate a delay-locked loop clock signal in response to a clock signal and a clock enable signal; a clock enable block configured to generate the clock enable signal in response to the clock signal and a read command signal; and a command pass block configured to perform primary latency control according to the clock signal and secondary latency control according to the delay-locked loop clock signal, for the read command signal generated in response to a strobe signal, and generate a latency signal.. .
| Video signal transmission device, video signal reception device, and video signal transmission system|
A video transmission device 10 has: a packer 11 which receives a video signal, a sync signal, and a data-enable signal, and generates a plurality of packet signals by packetizing the video signal and the sync signal based on the data-enable signal and according to the number of bytes of a packet corresponding to the number of gradation bits of the video signal; an encode unit 15 which generates a plurality of encoded packet signals by encoding the plurality of packet signals; and a serializer 14 which generates a serial packet signal by parallel-serial converting the plurality of encoded packet signals. The packer 11 generates a control signal including a pulse with a pulse width corresponding to the number of bytes of the packet, and the encode unit 15 subjects a portion of the packet signals corresponding to the pulse in the control signal from the packer, to an encode process which is different from a process for the other portion..
| Display device that switches light emission states multiple times during one field period|
A scan driving circuit includes a shift register unit and a logic circuit unit. The start of a start pulse of an output signal stp+1 of a p+1′th shift register is situated between the start and end of a start pulse of the output signal stp of a p′th shift register, and one each of a first enable signal through a q′th enable signal exist in sequence between the start of the start pulse of the output signal stp and the start of the start pulse of the output signal stp+1.
| Latch circuit of display apparatus, display apparatus, and electronic equipment|
A latch circuit for outputting data for m pixels present in one line on a display panel in a time-division manner for each pixel, in order to drive each pixel from among the m pixels based on n-bit data, includes m×n 1-bit latch circuits in which n 1-bit latch circuits are arranged in the column direction y and m 1-bit latch circuits are arranged in the row direction x, each circuit latching 1-bit data. Each 1-bit latch circuit includes a data latch unit circuit that latches data corresponding to any one bit of the n bits at different timings for each row, a line latch unit circuit that simultaneously latches data from the data latch unit circuit in each row, and an output enable element that outputs data from the line latch unit circuit based on an enable signal for selecting any one column..
| Controlled power boost for envelope tracker|
An envelope-tracking (et) power supply may include a boost control pin. The boost control pin receives a boost enable signal that activates or enables a supplemental power supply in the et power supply.
|System and method for strengthening of a circuit element to reduce an integrated circuit's power consumption|
A system and method enable strengthening of flip-flops (ffs) in an integrated circuit (ic) for the purpose of reducing power consumption. This is achieved by using stability condition (stc) and observability don't-care (odc) techniques.
|Reducing power consumption during idle state|
Methods and apparatus relating to power consumption reduction during idle state(s) are described. In one embodiment, logic transfers control of a power state of a device to one or more general purpose input output signals.
|Fast turn on system for a synthesized source signal|
A fast turn on compensation system for a synthesized signal source includes a synthesized signal source coupled to a power supply and configured to generate a phase stable radio frequency (rf) output signal. A mute amplifier is coupled to the synthesized signal source and the power supply.
|Negative charge pump regulation|
A negative charge pump is responsive to a pump enable signal. A voltage controlled current source provides a current.
|Circuits and methods for dqs autogating|
In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second buffer.
|Load-selective input voltage sensor|
A power converter controller includes a switch driver circuit coupled to generate a drive signal to control switching of a power switch to control a transfer of energy from an input of the power converter to an output of the power converter. An input sense circuit is coupled to receive an input sense signal representative of the input of a power converter.
|Ac voltage sensor with low power consumption|
A power converter controller includes an input sense circuit to receive an input sense signal representative of an input of a power converter. A zero-crossing detector is coupled to the input sense circuit to be responsive to the input sense signal falling below a first zero-crossing threshold and rising above a second zero-crossing threshold to determine zero-crossing intervals.
|Switched mode power converter controller with ramp time modulation|
A controller for use in a power converter includes a drive circuit coupled to generate a drive signal to control switching of a power switch to control a transfer of energy from a power converter input to a power converter output. The controller also includes an input for receiving an enable signal including enable events responsive to the power converter output.
|Digital-to-time converter and calibration of digital-to-time converter|
A digital-to-time converter (dtc) comprises a gate controller configured to generate a gate enable signal based on first and second digital values so that the gate enable signal has a first enable period and a second enable period for each pair of a first digital value and a second digital value. A gate conditionally passes a main clock signal to a gate output in response to the gate enable signal, the gate thus providing a gated signal at a gate output.
|Data-retained power-gating circuit and devices including the same|
A power-gating circuit and devices including the same are provided. The power-gating circuit includes a flip-flop configured to receive a first power supply voltage and a gated clock signal to operate and a switch circuit connected between a first power supply voltage source configured to supply the first power supply voltage and a second power supply voltage source configured to supply a second power supply voltage.
|Integrated clock gater (icg) using clock cascode complimentary switch logic|
Inventive aspects include an integrated clock gater (icg) circuit having clocked complimentary voltage switched logic (cicg) that delivers high performance while maintaining low power consumption characteristics. The cicg circuit provides a small enable setup time and a small clock-to-enabled-clock delay.
|Cds circuit and analog-digital converter using dithering, and image sensor having same|
A correlated double sampling circuit includes a first input terminal receiving a ramp signal having first and second ramp sections, a second input terminal receiving a pixel signal, and a comparing circuit comparing the ramp signal with the pixel signal to generate an output signal, wherein the comparing circuit changes a point in time at which the output signal logically transitions during the first ramp section and the second ramp section in response to an applied dithering enable signal.. .
|Timing synchronization circuit with loop counter|
An apparatus for synchronizing an output dock signal with an input clock signal includes a first timing synchronization circuit, control logic, and a counter. The first timing synchronization circuit is operable to generate a delay to synchronize a reference clock signal representative of the input clock signal with a feedback dock signal representative of the output clock signal responsive a strobe signal.
|Memory controller for strobe-based memory systems|
An integrated circuit (ic) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal.
|Method for operating a network system|
The invention relates to a method for operating a network system (2) having at least one client device (4.1, 4.2), at least one management device (16) and at least one printing device (14), comprising: provision of a first order from the client device (4.1, 4.2) for execution by the at least one printing device (14), storage of the order in a memory device (10.1, 10.2) of the client device (4.1, 4.2), transmission of an order request from the client device (4.1, 4.2) to the management device (16), wherein the order of execution of orders is managed by the management device (16), transmission of requests from the client device (4.1, 4.2) to the management device (16) at first prescribable intervals of time to determine whether the printing device (14) is available for executing the order from the client device (4.1, 4.2), and transmission of an enable signal from the management device (16) to the client device (4.1, 4.2) in response to the request from the client device (4.1, 4.2) when the printing device (14) is available for executing the order from the client device (4.1, 4.2).. .
|Display interface that compresses/decompresses image data, method of operating same, and device including same|
A source driver integrated circuit (ic) includes a logic circuit configured to receive a transmission data packet including data, a compression code indicating compression or non-compression of the data, and a clock signal, to interpret the compression code, and to generate a sleep mode enable signal based on an interpretation result, and a clock signal recovery circuit configured to enable one of a voltage-controlled delay line and a voltage-controller oscillator in response to the sleep mode enable signal.. .
|Electronic device, indication electronic device and data transmission method|
The present invention provides an electronic device including a display, an input detection module and a processor. The input detection module detects an operation on the display executed by an indication electronic device, and generates a first operation signal corresponding to location information of the operation.
|Clock signal generator module, integrated circuit, electronic device and method therefor|
A clock signal generator module arranged to generate at least one clock signal for at least one functional module is described. The clock signal generator module comprises a first clock source component associated with at least one functional module, at least one further clock source component associated with the at least one functional module, and at least one management unit arranged to controllably enable signal generation by the first and at least one further clock source components in accordance with at least one operating characteristic of the at least one functional module associated therewith..
|Method and apparatus for battery control|
Generally, a system and a method for controlling a battery to power a load disable battery discharge if a battery voltage is less than a low voltage. Disabling battery discharge inhibits current flow from the battery to the load.
|Data transfer operation completion detection circuit and semiconductor memory device provided therewith|
A data transfer operation completion detection circuit including a first counter for performing a shifting operation in response to the generation of a read initiation signal, a second counter for performing a shifting operation in response to the generation of a burst completion signal, and an sr latch circuit for generating a read enable signal in response to the burst completion signal being generated when the count value of the first counter matches the count value of the second counter. The completion of a read operation or another data transfer operation is thus detected based on a read initiation signal reception history; therefore, it is possible to detect whether all read operations are complete at a given time even if a new read command is received while a read operation or the like is in progress..
|Asynchronous fifo buffer for memory access|
An asynchronous fifo buffer that provides data in response to requests to read a memory array is disclosed. The asynchronous fifo buffer provides the data output within a latency tolerance.
|Pulse generator circuit|
A pulse generator circuit is disclosed that is optimized for printed, solution-processed thin film transistor processing. In certain embodiments, the circuit comprises dual thin film transistors that operate as a diode and resistor, respectively.
|Nonvolatile memory device, read method for nonvolatile memory device, and memory system incorporating nonvolatile memory device|
A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read data after the strobe signal is toggled a predetermined number of times.. .
|Emulated current ramp for dc-dc converter|
A voltage converter (fig. 4) for a power supply circuit is disclosed.
|Interconnections for plural and hierarchical p1500 test wrappers|
A test architecture accesses ip core test wrappers within an ic using a link instruction register (lir). An ieee p1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper.
|Display circuitry with reduced pixel parasitic capacitor coupling|
A touch screen display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor (tft) layer.
|Baseband video data transmission device and reception device, and transceiver system|
In a transmission device (2): a controller (2a) performs a control of reading, from information regarding video specification, first information indicating whether a reception device is capable of intermittent reception of receiving a video signal at a timing that causes certain number of frames to be intermittent, and, when the reception device can perform intermittent reception, multiplexing, to the video signal during a blanking period of the video signal to be updated, an enable signal indicating the present video signal is to be enabled and second information indicating that transmission of the video signal will not resume unless the video signal is updated; and a transmitter (2d) transmits the video signal that is to be updated and then does not resume transmission of the video signal unless the video signal is updated.. .
|Led driving device, illuminator, and liquid crystal display device|
The present invention provides a light emitting diode (led) driving device as a semiconductor device, which comprises: a direct current/direct current (dc/dc) controller, for controlling an output segment that is used to generate an output voltage from an input voltage and supply the output voltage to an led; an output current driver, for generating an output current of the led; and an led short-circuit detection circuit, for monitoring a cathode voltage of the led to perform an led short-circuit detection, wherein the led short-circuit detection circuit controls whether an action is performed or not according to a short-circuit detection enable signal input from outside the led driving device.. .
|Pulsed current sensing|
A system and method are provided for sensing current. A current source is configured to generate a current and a pulsed sense enable signal is generated.
|Predictive current sensing|
A system and method are provided for estimating current. A current source is configured to generate a current and a pulsed sense enable signal is generated.
|Memory module and memory system comprising same|
A memory module comprises a plurality of semiconductor memory devices each comprising a mode register set (mrs) circuit configured to generate an enable signal corresponding to an error mode of the semiconductor memory device in response to an mrs command received from a command decoder, and an address buffer configured to store a predetermined address signal, to receive an address signal and corresponding data from an external device, and to compare the address signal received with the predetermined address signal in response to the enable signal. As a consequence of determining that the address signal received from the external device is the same as the predetermined address signal stored in the address buffer, data different from the corresponding data received from the external device is written to a memory cell corresponding to the predetermined address signal..
|Methods, apparatuses, and circuits for bimodal disable circuits|
Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles.
|Current-parking switching regulator downstream controller pre-driver|
A system and method are provided for generating non-overlapping enable signals. A peak voltage level is measured at an output of a current source that is configured to provide current to a voltage control mechanism.
|Apparatus and methods for biasing a power amplifier|
Apparatus and methods for biasing a power amplifier are disclosed. In one embodiment, a method of biasing a power amplifier includes shaping an enable signal using a time-dependent signal generator to generate a control current, amplifying the control current using a current amplifier to generate a correction current, and generating a bias current for a power amplifier using a primary biasing circuit.
|Margin free pvt tolerant fast self-timed sense amplifier reset circuit|
In described embodiments, a circuit for providing a margin free pvt tolerant fast self-timed sense amplifier reset includes a sense amplifier coupled between a complementary pair of first and second bitlines in a memory cell, a first and second pmos drivers connected to internal nodes of the sense amplifier, respectively, and outputting a first and second output signals, wherein the second output signal is inverted by an inverter to form an inverted output signal, a read detect block receiving the first and inverted output signals and generating a transition detect signal that is latched by a cross-coupled inverters and employed to generate a sense amplifier enable signal with a global sense amplifier enable signal, and a push-pull logic formed by a nmos and a pmos in series to generate an output of the circuit.. .
|Conversion circuit, image processing device, and conversion method|
A conversion circuit includes: a conversion section configured to convert each of analog pixel signals into digital pixel data; a timing acquisition section configured to acquire specified timing, in which the specified timing defines a display period during which display of each of the analog pixel signals is performed in a cycle of a synchronization signal; a timing setting section configured to set timing that defines an extension period that is longer than the display period, in which the timing is other than the specified timing; an enable signal generation section configured to generate an enable signal, in which the enable signal indicates the extension period as a period during which the digital pixel data is valid; and an output section configured to output the digital pixel data that is valid, in accordance with the enable signal.. .
|Power managed synchronizers for asynchronous input signals|
Clock-gated synchronizer circuitry includes a number of clock-gated synchronizers, with each clock-gated synchronizer configured to synchronize an asynchronous input signal into a clock domain. The circuitry also includes a clock gater coupled to a clock input of the plurality of clock-gated synchronizers and coupled to receive an input clock and an enable signal.
|Light emitting device power supply circuit, light emitting device control circuit and identifiable light emitting device circuit therefor and identification method thereof|
The present invention discloses a light emitting device power supply circuit, a light emitting device control circuit and an identifiable light emitting device circuit therefor, and an identification method thereof. The light emitting device control circuit includes an operation signal generation circuit and an identification circuit.
|Redundancy circuit and semiconductor memory device including the same|
A redundancy circuit includes a redundancy decoder, a fuse array, and a decoder. The redundancy decoder decodes a redundancy enable signal generated when an address of a defective cell matches an input address.
|On chip electrostatic discharge (esd) event monitoring|
An approach for monitoring electrostatic discharge (esd) event of an integrated circuit. The approach includes a canary device for exhibiting an impedance shift when affected by an esd pulse, wherein circuit drain of the canary device is connected to an input terminal of the circuit structure.
|Data bus synchronizer|
A data bus synchronizer includes a plurality of registers arranged in a cascade, configured to generate a synchronized output in response to sampling an asynchronous bus without an enable signal, where the plurality of registers receive a value on the asynchronous bus. A last register of the plurality of registers is configured to generate the synchronized output in response to a load enable signal.
|Method and system for coexistence of multiple collocated radios|
An apparatus may include a set of transceivers comprising three or more transceivers each operable to communicate via a wireless communications standard different from each other transceiver and a driver to output an enable signal when a first transceiver of the set of transceivers is active. The apparatus may also include a processor circuit and a real-time frame synchronization module operable on the processor circuit to receive a first frame synchronization input signal to delineate first receive and first transmit periods of a radio frame of a first transceiver of the set of transceivers, and to generate a frame synchronization signal to align receive and transmit periods of each of a multiplicity of additional transceivers of the set of transceivers to the respective first receive and first transmit periods of the first transceiver.
|Semiconductor integrated circuit and method of driving the same|
A semiconductor integrated circuit includes a fuse circuit comprising a fuse configured to generate a fuse state signal corresponding to a rupture state of the fuse in response to an enable signal, a fuse state decision unit configured to determine whether or not the fuse state signal is normal based on a test signal, and generate an output enable signal according to a determination result, and a driving unit configured to output the fuse state signal in response to the output enable signal.. .
A display device includes a data driver having i data output terminals (i being a natural number greater than 1) and outputting data voltages to the i data output terminals in accordance with a source output enable signal provided from a timing controller, an output controller connected between the i data output terminals and i data lines, and i garbage switches respectively connected to the i data lines and connecting the i data lines to a ground terminal at a power input timing when a power supply voltage is applied to the display device, and interrupting the connection between the i data lines and the ground terminal at a timing later than an output timing of a first source output enable signal provided from the timing controller after the power input timing.. .
|Low clock-power integrated clock gating cell|
In an integrated clock gating (icg) cell a latch is coupled to a nor gate. The nor gate receives an enable signal.
|Automatic input impedance control|
The present disclosure is directed to an input impedance control circuit. In one embodiment, the automatic input impedance control circuit includes a circuit controller that comprises a module for calculating an impedance and a control logic module, wherein the control logic module provides a current enable signal and a current control output signal, a driver in communication with the circuit controller for receiving the current enable signal and the current control output signal, an input voltage sensing circuit in communication with the module for calculating the impedance and the control logic module and an input current sensing circuit in communication with the module for calculating the impedance..
|Display device and method for processing frame thereof|
A display device and a method for processing frame are provided. The display device includes a display panel, a source driver, a gate driver, a timing controller and a frame processing module.
|Gate driving circuit, display module and display device|
Provided are a gate driving circuit, a display module and a display device belonging to the field of display technique and being designed for solving the problem of high power consumption of the display module in the prior art. The gate driving circuit is used for driving gates of tfts corresponding to gate lines connected thereto, and includes at least two stages of shift registers connected in cascade, wherein each stage of shift register includes a first output terminal and a second output terminal, the first output terminal is connected to an enable signal input terminal of a next stage of shift register so as to output a next stage enable signal to the next stage of shift register, and the second output terminal is connected to a corresponding gate line so as to apply a gate driving signal on the gates of tfts through the corresponding gate line..
|Scan flip-flop, method of operating the same, and device including the scan flip-flop|
A scan flip-flop may include a selector outputting a data signal or a scan input signal in response to a scan enable signal, and a flip-flop that latches an output signal of the selector or the data signal, based on a clock signal and a low voltage signal.. .
|Clock generation circuit and clock generation system using the same|
A clock generation circuit includes a counting code generation unit configured to generate counting codes corresponding to a frequency of an input clock when an enable signal is enabled; a control code generation unit configured to decode the counting codes and generate control codes; and a cycle changeable oscillation unit configured to determine a frequency of an output clock in response to the control codes.. .
|Memory array voltage source controller for retention and write assist|
A voltage source controller for a memory array includes an input coupled to a voltage source, an output coupled to one or more memory cells of a memory array, where the output is configured to provide a cell source voltage to the memory cells. The controller also includes a switch circuit configured to: receive a retention enable signal, a write assist enable signal, and a standard mode enable signal; and based on the retention enable signal, write assist enable signal, and standard mode enable signal, selectively set the cell source voltage for one or more of the memory cells to one of: a retention voltage, a write assist voltage, or a standard mode voltage, where the retention voltage and the write assist voltage are less than the standard mode voltage..
|Pulse generator and ferroelectric memory circuit|
A pulse generator circuit with ferroelectric memory element is disclosed that is optimized for printed, solution-processed thin film transistor processing. In certain embodiments, the circuit comprises dual thin film transistors that operate as a diode and resistor, respectively.
|Fuse repair device|
A fuse repair device may include a first fuse circuit configured to store a first portion out of a failed address, a second fuse circuit configured to store a multipurpose information or a second portion of the failed address, an enable control circuit configured to provide a first enable signal to enable the second fuse unit based on a first control signal, a switch control circuit configured to provide a second enable signal to enable the second fuse unit based on a second control signal, a repair control signal generation circuit configured to compare data stored in the first fuse circuit and the second fuse circuit with an input address, and generate a repair control signal based on the first enable signal and the second enable signal, and a multipurpose control signal generation circuit configured to generate a multipurpose control signal to control operations different from a repair operation.. .
|Data processing device and method|
A data processing device includes a clock converter, a data converter, ad an error detector. The clock converter is configured to receive a first clock signal, convert the first clock signal into a second clock signal, and output the second clock signal.
|Electronic device and reset circuit|
A reset circuit is connected to a processor chip to reset the processor chip. The reset circuit includes a control unit, a standby power, and a voltage converting unit.
|Methods and apparatus for improving backlight driver efficiency|
An electronic device may be provided with display circuitry that includes a display timing controller, a backlight driver, a light source, and other associated backlight structures. The backlight control circuitry may generate a control signal having an adjustable duty cycle to the backlight driver.
|High fill-factor image sensor architecture|
An image sensor architecture is implemented within an image sensor system. Image sensor pixels include pixel regions, and each pixel region includes a photosensor, a reset circuit, and a readout circuit.
|Semiconductor memory device, system having the same and method for generating reference voltage for operating the same|
A semiconductor memory device and a method for generating a reference voltage needed for operating the same are disclosed. The semiconductor memory device includes a first decoder configured to generate a default set signal in response to a reset signal and a clock enable signal, a second decoder configured to generate a reference voltage set signal in response, and a reference voltage provider configured to generate an internal reference voltage..
The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact.
|Scan test circuitry with control circuitry configured to support a debug mode of operation|
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains each having a plurality of scan cells.
|Nonvolatile memory and method of operating nonvolatile memory|
A nonvolatile memory includes multiple banks, control logic and multiple read and write (rw) circuits. Each bank includes multiple memory cells.