|| List of recent Enable Signal-related patents
|Redundancy circuit and semiconductor memory device including the same|
A redundancy circuit includes a redundancy decoder, a fuse array, and a decoder. The redundancy decoder decodes a redundancy enable signal generated when an address of a defective cell matches an input address.
|On chip electrostatic discharge (esd) event monitoring|
An approach for monitoring electrostatic discharge (esd) event of an integrated circuit. The approach includes a canary device for exhibiting an impedance shift when affected by an esd pulse, wherein circuit drain of the canary device is connected to an input terminal of the circuit structure.
|Data bus synchronizer|
A data bus synchronizer includes a plurality of registers arranged in a cascade, configured to generate a synchronized output in response to sampling an asynchronous bus without an enable signal, where the plurality of registers receive a value on the asynchronous bus. A last register of the plurality of registers is configured to generate the synchronized output in response to a load enable signal.
|Method and system for coexistence of multiple collocated radios|
An apparatus may include a set of transceivers comprising three or more transceivers each operable to communicate via a wireless communications standard different from each other transceiver and a driver to output an enable signal when a first transceiver of the set of transceivers is active. The apparatus may also include a processor circuit and a real-time frame synchronization module operable on the processor circuit to receive a first frame synchronization input signal to delineate first receive and first transmit periods of a radio frame of a first transceiver of the set of transceivers, and to generate a frame synchronization signal to align receive and transmit periods of each of a multiplicity of additional transceivers of the set of transceivers to the respective first receive and first transmit periods of the first transceiver.
|Semiconductor integrated circuit and method of driving the same|
A semiconductor integrated circuit includes a fuse circuit comprising a fuse configured to generate a fuse state signal corresponding to a rupture state of the fuse in response to an enable signal, a fuse state decision unit configured to determine whether or not the fuse state signal is normal based on a test signal, and generate an output enable signal according to a determination result, and a driving unit configured to output the fuse state signal in response to the output enable signal.. .
A display device includes a data driver having i data output terminals (i being a natural number greater than 1) and outputting data voltages to the i data output terminals in accordance with a source output enable signal provided from a timing controller, an output controller connected between the i data output terminals and i data lines, and i garbage switches respectively connected to the i data lines and connecting the i data lines to a ground terminal at a power input timing when a power supply voltage is applied to the display device, and interrupting the connection between the i data lines and the ground terminal at a timing later than an output timing of a first source output enable signal provided from the timing controller after the power input timing.. .
|Low clock-power integrated clock gating cell|
In an integrated clock gating (icg) cell a latch is coupled to a nor gate. The nor gate receives an enable signal.
|Automatic input impedance control|
The present disclosure is directed to an input impedance control circuit. In one embodiment, the automatic input impedance control circuit includes a circuit controller that comprises a module for calculating an impedance and a control logic module, wherein the control logic module provides a current enable signal and a current control output signal, a driver in communication with the circuit controller for receiving the current enable signal and the current control output signal, an input voltage sensing circuit in communication with the module for calculating the impedance and the control logic module and an input current sensing circuit in communication with the module for calculating the impedance..
|Display device and method for processing frame thereof|
A display device and a method for processing frame are provided. The display device includes a display panel, a source driver, a gate driver, a timing controller and a frame processing module.
|Gate driving circuit, display module and display device|
Provided are a gate driving circuit, a display module and a display device belonging to the field of display technique and being designed for solving the problem of high power consumption of the display module in the prior art. The gate driving circuit is used for driving gates of tfts corresponding to gate lines connected thereto, and includes at least two stages of shift registers connected in cascade, wherein each stage of shift register includes a first output terminal and a second output terminal, the first output terminal is connected to an enable signal input terminal of a next stage of shift register so as to output a next stage enable signal to the next stage of shift register, and the second output terminal is connected to a corresponding gate line so as to apply a gate driving signal on the gates of tfts through the corresponding gate line..
|Scan flip-flop, method of operating the same, and device including the scan flip-flop|
A scan flip-flop may include a selector outputting a data signal or a scan input signal in response to a scan enable signal, and a flip-flop that latches an output signal of the selector or the data signal, based on a clock signal and a low voltage signal.. .
|Clock generation circuit and clock generation system using the same|
A clock generation circuit includes a counting code generation unit configured to generate counting codes corresponding to a frequency of an input clock when an enable signal is enabled; a control code generation unit configured to decode the counting codes and generate control codes; and a cycle changeable oscillation unit configured to determine a frequency of an output clock in response to the control codes.. .
|Memory array voltage source controller for retention and write assist|
A voltage source controller for a memory array includes an input coupled to a voltage source, an output coupled to one or more memory cells of a memory array, where the output is configured to provide a cell source voltage to the memory cells. The controller also includes a switch circuit configured to: receive a retention enable signal, a write assist enable signal, and a standard mode enable signal; and based on the retention enable signal, write assist enable signal, and standard mode enable signal, selectively set the cell source voltage for one or more of the memory cells to one of: a retention voltage, a write assist voltage, or a standard mode voltage, where the retention voltage and the write assist voltage are less than the standard mode voltage..
|Pulse generator and ferroelectric memory circuit|
A pulse generator circuit with ferroelectric memory element is disclosed that is optimized for printed, solution-processed thin film transistor processing. In certain embodiments, the circuit comprises dual thin film transistors that operate as a diode and resistor, respectively.
|Fuse repair device|
A fuse repair device may include a first fuse circuit configured to store a first portion out of a failed address, a second fuse circuit configured to store a multipurpose information or a second portion of the failed address, an enable control circuit configured to provide a first enable signal to enable the second fuse unit based on a first control signal, a switch control circuit configured to provide a second enable signal to enable the second fuse unit based on a second control signal, a repair control signal generation circuit configured to compare data stored in the first fuse circuit and the second fuse circuit with an input address, and generate a repair control signal based on the first enable signal and the second enable signal, and a multipurpose control signal generation circuit configured to generate a multipurpose control signal to control operations different from a repair operation.. .
|Data processing device and method|
A data processing device includes a clock converter, a data converter, ad an error detector. The clock converter is configured to receive a first clock signal, convert the first clock signal into a second clock signal, and output the second clock signal.
|Electronic device and reset circuit|
A reset circuit is connected to a processor chip to reset the processor chip. The reset circuit includes a control unit, a standby power, and a voltage converting unit.
|Methods and apparatus for improving backlight driver efficiency|
An electronic device may be provided with display circuitry that includes a display timing controller, a backlight driver, a light source, and other associated backlight structures. The backlight control circuitry may generate a control signal having an adjustable duty cycle to the backlight driver.
|High fill-factor image sensor architecture|
An image sensor architecture is implemented within an image sensor system. Image sensor pixels include pixel regions, and each pixel region includes a photosensor, a reset circuit, and a readout circuit.
|Semiconductor memory device, system having the same and method for generating reference voltage for operating the same|
A semiconductor memory device and a method for generating a reference voltage needed for operating the same are disclosed. The semiconductor memory device includes a first decoder configured to generate a default set signal in response to a reset signal and a clock enable signal, a second decoder configured to generate a reference voltage set signal in response, and a reference voltage provider configured to generate an internal reference voltage..
The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact.
|Scan test circuitry with control circuitry configured to support a debug mode of operation|
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains each having a plurality of scan cells.
|Nonvolatile memory and method of operating nonvolatile memory|
A nonvolatile memory includes multiple banks, control logic and multiple read and write (rw) circuits. Each bank includes multiple memory cells.
|Memory interface circuitry with improved timing margins|
Integrated circuits may include memory interface circuitry that communicates with memory. The memory interface circuitry may include latch circuitry that receives a data strobe enable signal from the memory controller and latches the data strobe enable signal using a data strobe signal received from the memory.
|Semiconductor storage device and control method thereof|
According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals.
|Strobe acquisition and tracking|
A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal.
|Control device and light source device|
A control device adapted to control a first light-emitting diode and a second light-emitting diode, includes a first logic operation unit receiving a first enable signal and a second enable signal to generate a first logic signal, a second logic operation unit receiving the first and second enable signals to generate a second logic signal, a first adjustment unit generating a first adjustment signal according to the first logic signal, a second adjustment unit generating a second adjustment signal according to the second logic signal, a first control unit outputting a first control signal to the first light-emitting diode according to the first enable signal and the first adjustment signal, and a second control unit outputting a second control signal to the second light-emitting diode according to the second enable signal and the second adjustment signal. The first logic signal and the second logic signal are complementary..
|Energy management system|
The present invention relates to an energy management system comprising an energy storage, a control system and a power converter supplying power to a load. The energy storage is arranged in individual energy units and the power converter is provided with a switching system for controlling the voltage over the load.
|Data communication apparatus and control method|
A data communication apparatus includes a data generation unit, a control register, a memory, a memory address generation unit, a failure setting unit, and a transmission unit. The data generation unit generates data.
|Voltage generation circuit of semiconductor memory apparatus|
A voltage generation circuit of a semiconductor memory apparatus includes a plurality of pumping units configured to provide voltages to an output node; a sensing unit configured to sense a voltage level of the output node and generate a pumping enable signal; an oscillator configured to generate an oscillator signal in response to the pumping enable signal; and a control unit configured to selectively output the oscillator signal to the plurality of pumping units in response to an active signal, a power-up signal and a mode register set signal.. .
|Memory with output control|
An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device.
|Non-volatile memory device and method of operating|
A method of operating a non-volatile memory includes; during power-on, reading control information from an information block and lock information from an additional information block, then upon determining that a secure block should be locked, generating a lock enable signal that inhibits access to data stored in the secure block, and a read-only enable signal that prevents change in the data stored in the additional information block.. .
|Power line lowering for write assisted control scheme|
Some embodiments of the present disclosure relate to a memory array having a cell voltage generator configured to provide a cell voltage header to a plurality of memory cells. The cell voltage generator is connected to the memory cells by way of supply voltage line and controls a supply voltage of the memory cells.
|Three-dimension image format converter and three-dimension image format conversion method thereof|
A three-dimension (3d) image format converter and a 3d image format conversion method thereof are provided. The 3d image format converter includes an input circuit, a processing circuit and an output circuit.
|Display device and method of compensating for data charge deviation thereof|
A display device includes a display panel including data lines, a source driver positioned at one side of the display panel, and a timing controller which sequentially stores digital video data in a plurality of line memories, starts to generate an output data enable signal in conformity with a first writing start timing of a last line memory of the line memories, adjusts a pulse width of the output data enable signal of each horizontal pixel line based on a previously determined charge time graph, reads out the digital video data from the line memories in synchronization with rising edges of the output data enable signal, and generates a source output enable signal having the same pulse width each time each line memory finishes reading out the data.. .
|Motion detection circuit and motion detection method|
A motion detection method is adapted for an image display circuit including a motion detection circuit and an arbitration circuit. In this motion detection method, a number of motion quality observation windows are defined.
|High-precision led control circuit, method and led driver thereof|
In one embodiment, a light-emitting diode (led) driver can include: (i) a reference voltage control circuit configured to provide a reference voltage signal in response to an enable signal; (ii) a current control circuit configured to control an output current of the led driver in response to the reference voltage signal; and (iii) the led driver being configured to drive an led load when the enable signal is active.. .
|Platform and launch initiation system for secondary spacecraft for launch vehicle|
A platform and launch initiation control system for secondary spacecraft for a launch vehicle includes an aluminum honeycomb core sandwiched between top and bottom structural aluminum skins and strengthened by a spider-like stiffener. Spool inserts for engaging the secondary spacecraft are arranged on the platform.
|Flip-flop circuit having a reduced hold time requirement for a scan input|
A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels.
|Setting information storage circuit and integrated circuit chip including the same|
A setting information storage circuit includes first decoders configured to generate first input enable signals, respectively, in response to selection codes and a first set signal, first register sets configured to correspond to the first decoders, respectively, and to receive setting data when first input enable signals generated from the first decoders corresponding to the first register sets, respectively, are enabled, and store the received setting data, a second decoders configured to generate a second input enable signals, respectively, in response to the selection codes and a second set signal, and a second register sets configured to correspond to the second decoders, respectively, and to receive the setting data when second input enable signals generated from the second decoders corresponding to the second register sets, respectively, are enabled, and store the received setting data.. .
|Switched averaging error amplifier|
A signal averaging circuit includes a plurality of switched weighted current sources to generate a total amount of charge. The total amount of charge is representative of a weighted sum of a plurality of input signal samples during an active period of a read enable signal.
|Method and apparatus for digital control of a switching regulator|
An on/off controller device includes a control circuit to generate a control signal to switch a power switch between an on state and an off state to transfer energy from a primary side to a secondary side of a switched mode power supply. A comparator is coupled to generate an enable signal that enables and disables the switching of the power switch by the control circuit.
|Display device and method of operating the same|
A display device is provided which includes a display panel including a plurality of pixels connected with a plurality of gate lines and a plurality of data lines; a gate driving unit configured to drive the plurality of gate lines; a data driver configured to drive the plurality of data lines; and a timing controller configured to generate a plurality of control signals for controlling the gate driving unit and the data driver in response to externally provided clock signal and data signals. The timing controller converts the data signals into an image data signal, a horizontal synchronization signal, a vertical synchronization signal, and a data enable signal, a pulse width of each of the horizontal and vertical synchronization signals corresponding to an aspect ratio of the data signals or a size of a black image display area.
|Systems and methods for interfacing between hard logic and soft logic in a hybrid integrated device|
Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules.
|Core circuit test architecture|
A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths.
|Wordline tracking for boosted-wordline timing scheme|
Some aspects of the present disclosure a method. In this method, a wordline voltage is provided to a wordline, which is coupled to a plurality of memory cells.
An apparatus for processing signals, arranged on an integrated circuit, comprises at least one analog input port that receives an input signal from outside of the integrated circuit, and a detector that detects an operation state of the apparatus based on the input signal. The detector provides at least one digital control/enable signal, which is dependent on the operation state of the apparatus, to another apparatus arranged on the integrated circuit..
|Electronic wire bridge with safety circuit|
An electronic bridge system includes a first interface to couple to an electrical or electro-mechanical installation to receive system information from the installation, and a second interface to couple to a second component of the installation, wherein the second component is to be bypassed or interrupted by the bridge system. Further, the system includes a bridge circuit coupled to the second interface and having a control port, and a safety circuit coupled to the first interface and having an output coupled to the control port.
|Boost converter control for envelope tracking|
Techniques for controlling boost converter operation in an envelope tracking (et) system. In an aspect, an enable generation block is provided to generate an enable signal for a boost converter, wherein the enable signal is turned on in response to detecting that a sum of a first headroom voltage and an enable peak of a tracking supply voltage is greater than an amplifier supply voltage of the et system.
|Liquid crystal display device|
In a liquid crystal display device that performs two-line inversion driving, a difference of a write period of a substantial video signal between a pair of pixel rows scanned with the same polarity is compensated. An input signal pre-processing circuit 42 receives display data data and an original data enable signal dtmg, generates and inputs a data enable signal dtmg_r and display data data_r to a driver control signal generation block 40.
|Semiconductor memory device|
A semiconductor memory device includes a read circuit configured to sequentially output a plurality of compressed data corresponding to all banks which are to be tested in response to a plurality of bank addresses and a read enable signal during a test mode and a pad configured to transfer the compressed data which are sequentially outputted from the read circuit to an outside of the semiconductor memory device.. .
|Single-ended volatile memory access|
A memory includes an array of memory cells that form rows and columns. The rows include memory cell pairs.
|Drivers and driving methods for a led string, capable of providing led short protection or avoiding led flickering|
The disclosure regards to drivers and driving methods for a led string consisting of leds. The led string and a current switch are coupled in series between a power line and a ground line.
|Receiver in physical layer of mobile industry processor interface (mipi-phy)|
A receiver includes a control module, a data receiving circuit and a masking circuit. The control circuit generates an enable signal according to a pair of differential signals provided by a transmitter.
|Intermediate circuit and method for dram|
An intermediate circuit and method for hiding refresh confliction. The intermediate circuit includes: a first control circuit configured to generate a command output enable signal con, a data read enable signal drn and a refresh enable signal refn based on the second clock, wherein a ration of duration the signal con is in a first state to duration in a second state equals to clk2/(clk1-clk2), the signal refn has a state that is reverse to that of the signal con and is used to refresh the dram; a command buffer configured to store the access commands received from the user interface and output the stored access commands to the dram in response to the first state of the signal con; a data buffer configured to read data from the dram in response to the first state of the signal con and output the read data..
|Display panel driver circuit and overheat protection device thereof|
A display panel driver circuit includes multiple drivers adapted for cooperatively driving a display panel and each operable under a protection mode, and an overheat protection device including multiple protection circuits, each of which controls a respective one of the drivers to operate under the protection mode in response to receipt of an enable signal, an interface circuit which transmits the enable signal to each of the protection circuits in response to receipt of a warning signal, and multiple temperature detection circuits, each of which is able to detect a temperature associated with a respective one of the drivers, and outputs the warning signal to the interface circuit based on the temperature thus detected.. .
|Hybrid stylus for use in touch screen applications|
A touch screen system is configured to sense a proximate or actual touch made to a touch screen panel. In response thereto, an rf transmitter is actuated to emit rf energy.
|Multi-dimensional data registration integrated circuit for driving array-arrangement devices|
The multi-dimensional data registration integrated circuit for driving array-arrangement devices, comprising: a plurality of the i-th hierarchy sets, each of the i-th hierarchy sets is divided into a plurality of the (i+1)-th hierarchy sets; a i-th hierarchy address selection circuit, comprising a signal generation unit and a multiplexing unit, wherein the former generates an enable signal, the latter is connected to the signal generating unit and shifts the input data based on the enable signal and a second timing signal to further generate n bits of address signals, the i-th hierarchy address selection circuit is used to scan the plurality of the i-th hierarchy sets and select at least one of the i-th hierarchy sets to function; and a data supply circuit to follow a scan sequence of a j-th hierarchy address selection circuit and write a plurality of data into the selected j-th hierarchy sets.. .
|Computer system, power supply device and method thereof|
A computer system includes a first electronic device configured to be operated by utilizing a regular voltage, a second electronic device configured to be operated by utilizing the regular voltage, and a power supply device for providing the regular voltage. The power supply device includes a voltage regulator coupled to the first electronic device for transforming a supply voltage to output the regular voltage to the first electronic device, a control logic circuit for generating an enable signal according to a control signal, and a load switch circuit coupled to the control logic circuit, the voltage regulator and the second electronic device for outputting the regular voltage to the second electronic device according to the enable signal..
|Clock control device, semiconductor device including the same and clock control method|
A clock control device and method are provided. The clock control device includes a stable time controller which receives an operational condition and generates an expiration counting value based on the operational condition; a stable time counter which receives the expiration counting value and activates a clock gating enable signal after a count value of the stable time counter is equal to the expiration counting value; a clock gating cell which transmits a clock signal after receiving the clock gating enable signal; and an oscillator which generates an oscillator clock signal and transmits the oscillator clock signal to the clock gating cell and the stable time counter..
|One-time program cell array circuit and memory device including the same|
A one-time program cell array circuit includes a cell array configured to include a plurality of one-time program memory cells, and to program an inputted program data and output a stored program data as a read data, a code generation circuit configured to generate an error correction code to be programmed in the cell array based on the inputted program data during a program operation; and an error detection circuit configured to detect an error of the read data based on the error correction code and the read data that are outputted from the cell array during a read operation and to be enabled or disabled in response to a first enable signal. The concern caused by applying the error correction scheme to the one-time program cell array circuit may be resolved by controlling the enabling or disabling of an error correction scheme, while increasing reliability..
|Channel hot carrier tolerant tracking circuit for signal development on a memory sram|
An embodiment of the invention discloses an electronic device for reducing degradation in nmos circuits in a tracking circuit. A first multiplexer selects, based on n bits from a row address in a memory array, which tracking circuit from a group of 2n tracking circuits will be used to provide a signal develop time for a memory cell in the memory array using a dummy word line signal.
|Race free semi-dynamic d-type flip flop|
Some of the embodiments of the present disclosure provide a d-type flip-flop, comprising a first latch configured to generate a sample enable signal, based on logical states of an input signal, and generate a sampled signal, based on logical states of the input signal and the sample enable signal; and a second latch configured to generate an output signal responsively to the sampled signal. Other embodiments are also described and claimed..
|Electric bicycle driving apparatus|
An electric bicycle driving apparatus is disclosed. The apparatus includes a speed change mode operator to output a first speed change mode signal or second speed change mode signal, a controller to receive the first speed change mode signal or second speed change mode signal and output a first control signal corresponding to the first speed change mode signal or a second control signal corresponding to the second speed change mode signal, a motor driver to, when the first speed change mode signal is output, receive the first control signal and output a first motor driving signal to drive a motor in a first speed change mode, and, when the second speed change mode signal is output, receive the second control signal and output a second motor driving signal to drive the motor in a second speed change mode, and a relay to selectively receive a relay switching enable signal..
|Electric bicycle driving apparatus|
Disclosed is an electric-bicycle drying apparatus. The apparatus includes a speed-change mode operator to output a low-speed or high-speed mode signal, a controller to output a first or second control signal corresponding to the low-speed or high-speed mode signal, a first motor driver to output a first motor-driving signal to drive a motor in a low-speed mode in response to the low-speed mode signal, a second motor driver to output a second motor-driving signal to drive the motor in a high-speed mode in response to the high-speed mode signal, a motor-drive-load booster to boost load of the second motor-driving signal using battery power under control of the controller in response to the high-speed mode signal, and a motor speed-change switching unit to selectively receive a switching enable signal from the controller so as to be turned on to provide the second motor-driving signal having the boosted load to the motor..
|Reference cell circuit and method of producing a reference current|
The present invention discloses a reference cell circuit which is applied to a non-volatile memory. The reference cell circuit includes a reference cell array, a first current mirror circuit, and a second current mirror circuit.
|Communication method and radiographic imaging system and apparatus|
An x-ray imaging system includes an x-ray source for emitting x-rays. A radiation source driver drives the x-ray source.
|Semiconductor integrated circuit having differential signal transmission structure and method for driving the same|
A semiconductor integrated circuit includes an input data line pair, a sense amplifier configured to sense and amplify data loaded in the input data line pair and transmit the amplified data to an output data line pair, in response to a control signal, and a sense amplification controller configured to sense an amplification level of the output data line pair, limit an activation period of a sense amplification enable signal, and output the limited signal as the control signal.. .
A semiconductor apparatus includes: a sense amplifier unit enabled for a predetermined time during a read operation in response to a first read enable signal, enabled before a write operation in response to a second read enable signal, and disabled when the write operation is started, and a switch unit configured to connect a write driver and a memory unit during the write operation in response to a first select signal, connect the sense amplifier unit and the memory unit for the predetermined time during the read operation in response to a control signal, and disconnect the sense amplifier and the memory unit when the write operation is started.. .
|Read self-time technique with fine grained programmable logic delay element|
A sense amplifier enable signal delay circuit for the programmable control of the delay of the generation of a sense amplifier enable signal is described. Further, stacked transistors and a pulse-width control block, which are programmed by external test pins to control the delay of the generation of a sense amplifier enable signal are described.
Disclosed is a frequency synthesizer including first and second shift register circuits 3a and 3b each for outputting pll setting data on a rising edge of a load enable signal, first and second fractional modulators 4a and 4b each for generating dividing number control data on the basis of the pll setting data in synchronization with a reference signal, and first and second fractional pll synthesizers 5a and 5b each for generating a high frequency signal according to the pll setting data, the reference signal, and the dividing number control data. By controlling the timing of the load enable signal, the frequency synthesizer carries out phase control between the high frequency signals generated by the first and second fractional pll synthesizers 5a and 5b..
|Power voltage selection device|
A power voltage selection device includes a first power voltage and a second power voltage; a power selection unit having a first pmos transistor and a second pmos transistor, wherein the first power voltage is supplied to a source of the first pmos transistor, a gate of the first pmos transistor receives a first enable signal, the second power voltage is supplied to a source of the second pmos transistor, a gate of the second pmos transistor receives a second enable signal, and a body of the first pmos transistor is coupled to a body of the second pmos transistor; an output unit having a common node to which a drain of the first pmos transistor and a drain of the second pmos transistor are commonly coupled; and a body voltage control unit controlling to supply one of the first power voltage and the second power voltage to the bodies of the first pmos transistor and the second pmos transistor, wherein the one has a higher voltage level than the other.. .