|| List of recent Enable Signal-related patents
| Scan test circuit with scan clock|
A scan test circuit includes: a pulse generator, for generating differential pulses according to a system clock signal; a functional path, including: a d-type latch clocked by the differential pulses; a test path, including: a scan latch clocked by a test clock signal; and a tri-state inverter. When a test enable signal is enabled, the generation of the differential pulses is disabled..
Mediatek Singapore Pte. Ltd.
| Method and system of testing semiconductor memory|
A method of testing a semiconductor memory includes generating a logical value of a test pattern through an algorithm pattern generator included in a field programmable gate array. The generated logical value is programmed in a dut under the control of a dq signal responding to a dq enable signal that is generated from automatic test equipment and is then transferred to the field programmable gate array.
Samsung Electronics Co., Ltd.
| Novel sense amplifier scheme|
A sense amplifier circuit comprising a pair of cross-coupled inverters and a data line charging circuit is disclosed. The cross-coupled inverters comprise a first inverter and a second inverter.
Taiwan Semiconductor Manufacturing Company Limited
| Semiconductor memory apparatus|
A semiconductor memory apparatus includes a driving current control block configured to sense a resistance value of a dummy memory element, and generates a write driver control signal; and a write driving block configured to provide a driving voltage to a memory cell array in response to a write driver enable signal and the write driver control signal.. .
Sk Hynix Inc.
According to one embodiment, controller includes a phase comparator that receives a data strobe signal outputted from a memory in response to a read enable signal, and a delayed data strobe signal formed by applying a delay to the data strobe signal, and outputs a result of comparison between phases of two signals. The controller also includes a duty control unit that corrects a duty of the read enable signal outputted to the memory based upon the comparison result of the phase comparator..
Kabushiki Kaisha Toshiba
| Content addressable memory|
The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each cam cell of a cam memory array via a search line pair.
Renesas Electronics Corporation
| Pixel circuit and display device using the same|
Exemplary embodiments of the present invention relates to a pixel circuit for displaying an image of uniform luminance. The pixel circuit comprising an organic light emitting diode (oled), an rs trigger comprising a first terminal connected to a scan line, a second terminal connected to an enable line, and a third terminal connected to a data line, the rs trigger configured to generate an output signal according to an enable signal, a data signal, and a scan signal respectively received via the enable line, the data line, and the scan line, and a driving transistor comprising a first electrode connected to a first power source, a second electrode connected to an anode of the oled, and a gate electrode connected to an output terminal of the rs trigger, the driver transistor configured to control a current flowing through the oled in response to the output signal of the rs trigger..
Samsung Display Co., Ltd.
|Systems, devices, memory controllers, and methods for memory initialization|
Systems, devices, memory controllers, and methods for initializing memory are described. Initializing memory can include configuring memory devices in parallel.
Micron Technology, Inc.
|Delay line ring oscillation apparatus|
The delay line degradation protection architecture as build-in ring oscillation apparatus includes a two gates logical circuit, a buffer, a clock input buffer and a delay lock loop circuit. The two gates logical circuit receives a clock enable signal, specific mode signal, and delayed clock output signal.
Nanya Technology Corporation
Provided is a semiconductor circuit. The semiconductor circuit includes: an input node configured to receive an enable signal, a sense enable signal, and a clock signal; and a clock gating circuit configured to output an enable clock signal corresponding to the clock signal while a signal level of the enable signal is at a first level regardless of a signal level of the sense enable signal, when the semiconductor circuit is in a high-voltage mode, and output an enable clock signal corresponding to the clock signal while a signal level of at least one of the enable signal and the sense enable signal is at the first level, when the semiconductor circuit is in a low-voltage mode..
Samsung Electronics Co., Ltd.
Circuits and methods for pulse radio receivers
Circuits and methods comprising: a radio frequency amplifier that powers off in response to an enable signal; a demodulator that outputs an rz signal; an all-digital clock and data recovery circuit comprising: a phase detector that includes a tri-state phase frequency detector for use when in an acquisition mode and a hogge phase detector for use when in a communication mode, that receives the rz signal, and that outputs a phase detector output from the tri-state phase frequency detector when in the acquisition mode and from the hogge phase detector when in the communication mode, a loop filter that receives the phase detector output from the phase detector and produces a loop filter output that is the sum of a proportional path of the loop filter and an integral path of the loop filter, and a numerical controlled oscillator that receives the loop filter output and produces the enable signal.. .
Semiconductor memory device
A semiconductor memory device includes a pad configured to receive a first write data from outside of the semiconductor memory device, and a write circuit configured to generate a plurality of second write data which are to be written in memory cells of all banks to be tested in response to a test mode signal, data strobe signals, a write enable signal, and the first write data transferred through the pad.. .
Sk Hynix Inc.
Interfaces and die packages, and appartuses including the same
A memory device includes a memory die package including a plurality of memory dies, an interface device including an interface circuit, and a memory controller configured to control the interface with control data received from at least one of the plurality of memory dies. The interface device of the memory device is configured to divide and multiplex an io channel between the memory die package and the memory controller into more than one channel using the control data receive from the at least one of the plurality of memory dies.
Micron Technology, Inc.
Semiconductor memory apparatus
A semiconductor memory apparatus includes an enable signal generation unit configured to be inputted with a plurality of clocks which have different phases, and generate a plurality of enable signals; and a plurality of sampling units configured to output input data as sampling data in response to respective pairs of clocks of the plurality of clocks and respective ones of the plurality of enable signals.. .
Sk Hynix Inc.
Test mux flip-flop cell for reduced scan shift and functional switching power consumption
A new flip-flop cell that is more efficient in scan chain configuration includes a multiplexer, storage element (e.g., a flip-flop), an inverter, and multiple logic gates. The flip-flop cell is configured to receive both a test signal and a data input signal and select one of the two to pass to the storage element based on a scan enable signal that indicates either a capture mode or a scan shift mode.
Stmicroelectronics Asia Pacific Pte. Ltd.
Device and generating input control signals of a serialized compressed scan circuit
A device and a method for generating input control signals of a serialized compressed scan circuit are provided. A control signal generating device receives a test clock signal from a clock input port and a state enable signal from a state enable bus, and correspondingly generates a shift enable signal, a capture enable signal and a strobe signal.
Industrial Technology Research Institute
Method and securing configuration scan chains of a programmable device
Scan chain circuitry on an integrated circuit device includes a plurality of memory elements, and a plurality of control elements. Each of the control elements is located between respective ones of the plurality of memory elements for controllably connecting the plurality of memory elements into a scan chain.
Image sensor and controlling the same
Provided is an image sensor including a sensor array including a plurality of pixels arranged in rows and columns. The image sensor may include a ramp signal generator which may generate a ramp signal.
Samsung Electronics Co., Ltd.
Counter circuit, analog-to-digital converter, and image sensor including the same and correlated double sampling
A counter circuit includes a first counter and a second counter. The first counter is configured to count a first counter clock signal which toggles with a first frequency to generate upper (n−m)-bit signals of n-bit counter output signals, in response to a first counting enable signal based on a first comparison signal during a coarse counting interval.
Method and system for measuring noise of a magnetic head
A method for measuring noise of a magnetic head includes setting a plurality of threshold values, applying bias current or voltage to a read element of the magnetic head, applying an external transverse magnetic field to the magnetic head, amplifying output signal from the read element to produce an amplified signal, filtering the amplified signal to produce a filtered signal, generating an enable signal for each threshold value in a predetermined time window by a counting control means with input signals which include the filtered signal and the threshold value, measuring the cumulative time duration of each enable signal, making an amplitude-duration distribution according to the cumulative time durations and the threshold values, calculating a plurality of parameters according to the amplitude-duration distribution and analyzing the parameters with a plurality of predetermined criteria to determine the defects of the magnetic head. Accordingly, the invention also discloses a system for measuring noise of a magnetic head..
Sae Magnetics (h.k.) Ltd.
Shift register circuit
A shift register circuit for driving an oled display panel is provided. The shift register circuit includes a plurality of circuit stages connected in series.
Au Optronics Corp.
The disclosed invention provides a semiconductor device capable of suitably controlling the level of an enable signal to resolve nbti in a pmos transistor. An input node receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby.
Renesas Electronics Corporation
Interpolation filter based on time assignment algorithm
Disclosed is an interpolation filter based on time assignment algorithm. An interpolation filter comprises an enable signal generating part generating enable signals for operation of the interpolation filter, an input value generating part generating input values, a first calculating part generating a first output value based on a first enable signal and a first input value, a second calculating part generating a second output value based on a second enable signal and a second input value, and an output value selecting part selecting a final output value among the first output value and the second output value.
Electronics And Telecommunications Research Institute
Data input circuit
A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal clock during a burst period from substantially a time when the pulse of the shifting signal is generated.
Sk Hynix Inc.
Driving apparatus of display
A driving apparatus of a display is disclosed. The driving apparatus includes a digital-to-analog converter (dac) circuit, an output buffer circuit and a pre-charge circuit.
Novatek Microelectronics Corp.
Clock delay detecting circuit and semiconductor apparatus using the same
Provided is a clock delay detecting circuit and semiconductor apparatus using the same that is capable of generating a period signal whose period is a delay time of a clock, dividing the period signal, and counting the divided period signal. The clock delay detection circuit comprises a period signal generating unit configured to generate a counting control signal, a period signal dividing unit configured to generate a counting enable signal by dividing the counting control signal, and a counting unit configured to generate a delay information signal by counting the counting enable signal with a clock, wherein the counting control signal has a period with a predetermined time..
Sk Hynix Inc.
Switch supporting voltages greater than supply
Devices for isolating an input from an output are disclosed. For example, a device includes a first p-type metal oxide semiconductor transistor and a first circuit.
Parallel test device and method
A parallel test device and method are disclosed, which relates to a technology for performing a multi-bit parallel test by compressing data. The parallel test device includes: a pad unit through which data input/output (i/o) operations are achieved; a plurality of input buffers configured to activate write data received from the pad unit in response to a buffer enable signal, and output the write data to a global input/output (gio) line; a plurality of output drivers configured to activate read data received from the global i/o (gio) line in response to a strobe delay signal, and output the read data to the pad unit; and a test controller configured to activate the buffer enable signal and the strobe delay signal during a test mode in a manner that the read data received from the plurality of output drivers is applied to the plurality of input buffers such that the read data is operated as the write data..
Sk Hynix Inc.
Power converter for reducing standby power consumption
There is provided a power converter for reducing standby power consumption. The power converter includes a rectifier configured to rectify ac power into dc power, a transformer configured to output power by converting a voltage of dc power rectified by the rectifier, a pwm control module configured to control an output power by switching a power switching device connected to the transformer, a first external switch configured to provide a disable signal, a first capacitor that is connected in parallel to one side of the first external switch, a second external switch configured to provide an enable signal, and a second capacitor that is connected in parallel to one side of the second external switch..
Magnachip Semiconductor, Ltd.
System and providing a multi-mode embedded display
An information handling system includes a display panel, a panel connector, and a source device. The display panel displays images at different resolutions.
Dell Products, Lp
Automatic input impedence control
The present disclosure is directed to an input impedance control circuit. In one embodiment, the automatic input impedance control circuit includes a circuit controller that comprises a module for calculating an impedance and a control logic module, wherein the control logic module provides a current enable signal and a current control output signal, a driver in communication with the circuit controller for receiving the current enable signal and the current control output signal, an input voltage sensing circuit in communication with the module for calculating the impedance and the control logic module and an input current sensing circuit in communication with the module for calculating the impedance..
Display device and driving method thereof
A display device and driving method thereof are disclosed. In one aspect, the display device includes a display panel displaying a still image and a moving image and a signal control unit controlling signals for driving the display panel and controlling a frequency of the display panel based on a low frequency enable signal.
Samsung Display Co., Ltd.
Semiconductor device, display device, and signal loading method
The present invention provides a drive ic, a display device and a loading method that enable signals of different differential formats to be loaded without resulting in circuit redundancy. Namely, a drive ic includes an input section, a holding section, a selection section, and an output section.
Lapis Semiconductor Co., Ltd.
Display apparatus and source driver thereof
A display apparatus and a source driver thereof are disclosed. The source driver includes a temperature sensor and a power switch.
Novatek Microelectronics Corp.
Source driver with reduced number of latch devices
A source driver with reduced number of latch devices includes a master latch device and at least one slave latch device. The master latch device has a first transmission gate, a first inverter, a second inverter, a first enable gate, and a second enable gate.
Orise Technology Co., Ltd.
Semiconductor apparatus and semiconductor system
Provided is a semiconductor apparatus including a plurality of semiconductor chips coupled through an electrical coupling unit. Each of the semiconductor chips includes: a chip id signal generation unit configured to generate a chip id signal; and a chip enable signal generation unit configured to receive a clock enable signal in response to the chip id signal, wherein one of the semiconductor chips shares the received clock enable signal as a transfer clock enable signal with the other semiconductor chips, and the chip enable signal generation unit detects whether or not an error occurs in the chip id signals of the plurality of semiconductor chips, selects any one of the transfer clock enable signal and the clock enable signal applied, and outputs the selected signal as a chip enable signal..
Sk Hynix Inc.
Multi master arbitration scheme in a system on chip
A multi master system on chip (soc) includes a plurality of masters comprising a first master and a second master, each configured to generate a request. A next state generator in the multi master soc is configured to generate a next state of a round robin pointer in response to the request and a current state of the round robin pointer.
Texas Instruments Incorporated
Semiconductor device with fuse array and operating method thereof
A semiconductor device includes a fuse array for storing normal fuse data and pattern data through a programming operation, a boot-up control unit suitable for generating an enable signal for enabling an output of the pattern data, and a pattern detection unit suitable for detecting a pattern of the pattern data in response to the enable signal, and generating a detection signal. The fuse array outputs the normal fuse data in response to the detection signal..
Sk Hynix Inc.
Thin film transistor array substrate and driving method therefor as well as liquid crystal display
A thin film transistor array substrate, a driving method therefore, and a liquid crystal display are disclosed. The thin film transistor array substrate includes at least a sub-pixel region formed by a gate line and a data line intersected with each other, wherein, each sub-pixel comprises a first transistor (21) of which the gate is connected with a gate line and the drain is connected with a data line and a first storage capacitor (23) of which one end is connected with the source of the first transistor (21) and the other end is connected with an output of a reference voltage, the sub-pixel further comprises a second storage capacitor (24) and a second transistor (25), wherein one end of the second storage capacitor (24) is connected with the source of the first transistor (21), and the other end of the second storage capacitor (24) is connected with the drain of the second transistor (25); the source of the second transistor (25) is connected with the output of the reference voltage, and the gate of the second transistor (25) is connected with an output of an enable signal.
Boe Technology Group Co., Ltd.
Clock control device
A clock control device is disclosed, which relates to a technology for reducing the amount of current consumption when a semiconductor device operates at a high speed. The clock control device includes: a chip-select-signal control block configured to generate a chip-select-control signal by latching a chip select signal, and output a fast chip select signal according to the chip-select-control signal; and a clock control block configured to drive a clock signal in response to the fast chip select signal when a command clock enable signal is activated, thereby generating a clock control signal, wherein the chip-select-signal control block latches the chip-select-control signal, and controls the chip-select-control signal to be toggled after the command clock enable signal is transitioned..
Sk Hynix Inc.
Double data rate counter, and analog-digital converting appratus and cmos image sensor using the same
A double data rate (ddr) counter includes a clock selection unit suitable for selectively inverting a first counting clock based on a control signal and for outputting a second counting clock, a first latch stage suitable for latching the second counting clock based on a counting enable signal and for outputting the least significant bit (lsb) of the ddr counter, a determination unit suitable for generating the control signal based on the last bit state of the lsb in a reset counting period, and a second latch stage suitable for receiving the lsb as a clock input to generate a higher bit of the lsb at least in a main counting period.. .
Sk Hynix Inc.
Redundancy evaluation circuit for semiconductor device
A redundancy evaluation circuit has (m+1) fuse boxes and a comparator, wherein the m fuse box output a fuse status address signal and the other one fuse box outputs a comparator enable signal. Each fuse box has a common stage circuit and k redundant cells.
Envelope tracker with variable boosted supply voltage
Techniques for efficiently generating a variable boosted supply voltage for an amplifier and/or other circuits are disclosed. In an exemplary design, an apparatus includes an amplifier, a boost converter, and a boost controller.
Voltage regulator, operation method thereof, voltage regulating system, and mobile vehicle
A voltage regulator, an operation method thereof, and a voltage regulating system, and a mobile vehicle are provided. The voltage regulator coupled to an alternator and a battery includes a voltage detection unit which is coupled to the alternator and a startup assisting unit.
Redundant power supply circuit, power over ethernet system, and method
A redundant power supply circuit includes a port detection circuit, a fixed state detection circuit, a voltage conversion circuit, and a control circuit. The port detection circuit detects and outputs a plurality of ready signals according to a plurality of power signals of a number of poe ports.
Core circuit test architecture
A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths.
Server and power chip detecting method
A power chip detecting device, applied in a server, includes a power chip, a power sequence control module, a base management controller, a gpio module, and a signal detecting module. The power sequence control module sends an initial power enable signal to the power chip after the server is switched on, and the power sequence control module receives an initial power good signal from the power chip after the power chip receives the initial power enable signal.
The semiconductor device includes an internal clock generator, a shift signal generator and a first control signal generator. The internal clock generator generates a first internal clock signal and a second internal clock signal in response to an external clock signal.
I/o data retention device
An apparatus for controlling retention of data includes a logic circuit, a retention control cell circuit, and an i/o cell circuit. The logic circuit generates at least one retention enable signal before a chip enters a reduced power mode.
Nonvolatile memory device, read nonvolatile memory device, and memory system incorporating nonvolatile memory device
A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read data after the strobe signal is toggled a predetermined number of times.. .
Semiconductor devices and semiconductor systems including the same
Semiconductor devices are provided. The semiconductor device includes a control signal generator and a first data input unit.
Semiconductor device and semiconductor memory device
A semiconductor device includes a fuse array having a plurality of fuse sets suitable for outputting a plurality of fuse status signals having different levels according to whether fuses of the plurality of fuse sets are cut or not, a code counter suitable for counting selection codes in a preset order in response to an enable signal and an operation clock, and storage blocks suitable for receiving and storing the plurality of fuse status signals in a preset order in response to the selection codes.. .
An internal voltage generation circuit of a semiconductor apparatus includes: an active driver configured to output an internal voltage to an output node; a standby driver configured to output the internal voltage to the output node; and a voltage stabilizer connected to the output node. The voltage stabilizer starts a voltage stabilization operation of supplying or receiving electric charges to or from the output node when an active enable signal is disabled, and stops the voltage stabilization operation in a predetermined time after the active enable signal is enabled..
A lighting device includes a switch element coupled to a power source; a bridge current rectifying unit in communication with the switch element for converting alternating current received from the power source into direct current; a driving and light-emitting module in communication with the bridge current rectifying unit; and a counting and control unit in communication with the switch element and the driving and light-emitting module. The counting and control unit counts a switching number of the switch element, and selectively outputs one or both of a first enable signal and a second enable signal to the driving and light-emitting module to emit light of a selected feature according to the switching number of the switch element..
Method and optical transmission in a communication network
A manner of mitigating the self heating effect of a laser or other light source such as a laser in a network node of a communication network. A self-heating mitigation module is provided, the self-heating mitigation module includes one or both of a self-heating adjustment module to accelerate self heating at the beginning of a transmission and a sub-threshold lasing module that applies a sub-threshold current between transmissions.
Clock reproducing and timing method in a system having a plurality of devices
A system includes a memory controller and a plurality of semiconductor devices that are series-connected. Each of the devices has memory core for storing data.
A semiconductor apparatus includes: a command control unit configured to generate a read strobe signal, a write strobe signal, a read command, and a write command; a clock enable signal generation unit configured to generate a read clock enable signal in response to the read strobe signal and generate a write clock enable signal in response to the write strobe signal; a clock control unit configured to generate a first control clock signal and a second control clock signal in response to an internal clock signal, the read clock enable signal, and the write clock enable signal; and a latency shift unit configured to generate a first latency signal in response to a delayed read command and the first control clock signal and generate a second latency signal in response to a delayed write command and the second control clock signal.. .
Power controller with pulse skipping
A controller for a power converter includes a drive circuit coupled to generate a drive signal in response to an error signal representative of a load of the power converter. The drive circuit includes a pulse skipping circuit coupled to generate a blanking signal in response to the error signal.
Scanning signal line drive circuit and display device equipped with same
This liquid crystal display device allows outputs from rs-ff circuits (401 to 409) and switch circuits (411 to 419), which function as a shift register, to be provided as scanning signals that are selectively activated during odd and even scanning line selection periods, by simply changing the potential of an enable signal (en) (i.e., by simply providing an en signal line), which achieves interlacing drive that allows a reduction in the number of polarity inversions, thereby making it possible to reduce power consumption and a wiring area for control lines and achieve simple control which allows circuit simplification, resulting in a reduced frame area and a display panel which is compact as a whole.. .
I/o circuit with phase mixer for slew rate control
An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal.
Sleep mode circuit and a placing a circuit into sleep mode
A first circuit is configured to communicatively couple to a second circuit including an analog circuit and a digital circuit. The first circuit comprises a lock unit and a sleep unit.
Phase-rotating phase locked loop and controlling operation thereof
A phase-rotating phase locked loop (pll) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating pll, the first and second loops configured to activate in response to an enable signal. The pll may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code..
Adaptive interface for coupling fpga modules
A method for implementing an adaptive interface between at least one fpga with at least one fpga application and at least one i/o module, which are designed as the corresponding sender side or receiver side, for connection to the fpga, whereby a serial interface is formed between the at least one fpga and the at least one i/o module, comprising the steps of configuring a maximum number of registers to be transmitted for each fpga application, configuring a shared, fixed register width for all registers, setting an enable signal on the sender side for the registers to be transmitted out of the maximum number of registers to be transmitted, transmitting the enable signal from the sender side to the receiver side, and transmitting the registers, for which the enable signal is set, from the sender side to the receiver side.. .
Light source module, light source module driving circuit and driving method
The present invention discloses a light source module, a light source module driving circuit and a driving method. The driving circuit comprises: a power supply, which provides input voltage; a control signal generating circuit, which inputs the input voltage provided from the power supply and outputs an enable signal and a dimming signal; a driving chip, which is connected with the power supply and connected to the enable signal and the dimming signal output from the control signal generating circuit, driving the light source of the light source module according to the enable signal and the dimming signal.
Integrated circuit with toggle suppression logic
An integrated circuit with toggle suppression logic for built-in self-test is provided. The integrated includes a loading circuit configured to operate in a shift mode based on a first enable signal and a capture mode based on a second enable signal.
Voltage detection circuit
A voltage detection circuit includes a reference voltage and current supply configured to generate a reference voltage and a reference current; a switching element configured to shift from an off-state to an on-state when the reference voltage is higher than a predetermined threshold voltage; a current mirror circuit allowing a current corresponding to the reference current to flow through the switching element in the on-state; a capacitive element coupled in series to the current mirror circuit and charged with the current flowing through the switching element; and an inverter configured to output an enable signal activated based on a terminal voltage of the capacitive element.. .
A semiconductor device includes: a plurality of repair fuse circuits configured to each program a repair target address; and an enable signal generation circuit configured to generate at least one enable signal in response to a source signal and provide the enable signal to each of the repair fuse circuits in common. Since the semiconductor device may iteratively generate a rupture enable signal through a feedback scheme, the area occupied by a circuit, such as a shift register or a d flip-flop may be saved..
Apparatus and reading data from multi-bank memory circuits
The disclosure relates to an apparatus for reading data from a memory circuit that includes at least two memory banks. The apparatus includes a first multiplexer configured to generate data at a first output from a first selected one of a first set of bit lines of a first memory bank based on a select signal.
Semiconductor device, semiconductor system including the semiconductor device, and driving the semiconductor system
A semiconductor device includes a plurality of pads, a plurality of data input/output units connected with the plurality of pads and enabled in response to a plurality of enable signals, and a group programming unit suitable for grouping the plurality of pads into a number of pad groups in response to a mode register set (mrs) code and group information, and generating a number of groups of enable signals corresponding to the number of pad groups, wherein a number of groups of the data input/output units are sequentially enabled in response to respective groups of the enable signals.. .
Charging methods of detachable electronic devices
An electronic device includes a first battery, a first charging unit, a first voltage adjustment unit, a power detection module, and a first control module. The first charging unit charges the first battery according to a supply voltage and a first charging enable signal.
Input/output line driver circuit
Input/output (i/o) line driving circuits are provided. The circuit includes a first i/o line driver and a second i/o line driver.