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This page is updated frequently with new Enable Signal-related patent applications.




Date/App# patent app List of recent Enable Signal-related patents
08/18/16
20160241143 
 Quick-start high-voltage boost patent thumbnailQuick-start high-voltage boost
In one implementation, a voltage boost assembly including a boost converter having a capacitive element arranged at an output, and an inductive element connectable to an electrical supply. The voltage boost assembly also includes a sensor assembly provided to generate a quick-start enable signal in response to detecting that an electrical condition relative to an electrical output of the boost converter has breached a first threshold.
Skyworks Solutions, Inc.


08/18/16
20160235931 
 Ultrasound scanning apparatus, breathing machine, medical system and related method patent thumbnailUltrasound scanning apparatus, breathing machine, medical system and related method
An ultrasound scanning apparatus, a breathing machine, a medical system and a related method. The ultrasound scanning apparatus comprises an ultrasound scanning unit, an ultrasound controller for controlling the operation of the ultrasound scanning unit, detecting the operation state of the ultrasound scanning unit, generating a first enable signal when detecting that the operation state of the ultrasound scanning unit is transferred from an operating state to a nonoperating state and generating a second enable signal when detecting that the operation state of the ultrasound scanning unit is transferred from the nonoperating state to the operating state, and an enable output end for transmitting the first enable signal or the second enable signal to the breathing machine to control the running of the breathing machine..
Shenzhen Mindray Bio-medical Electronics Co., Ltd.


08/11/16
20160234007 
 Clock and data recovery circuit using digital frequency detection patent thumbnailClock and data recovery circuit using digital frequency detection
A clock and data recovery circuit is disclosed herein. The clock and data recovery circuit includes a phase detection unit, a charge pump, a loop filter, a voltage control oscillator, and a frequency detection unit.
Research & Business Foundation Sungkyunkwan Univer Sity


08/11/16
20160233981 
 Method of generating data patent thumbnailMethod of generating data
A method of generating data is provided. The method includes providing, by a peak comparator, a searcher enable signal and peak comparator output data based on result values that are generated by multiplying an input signal having a plurality of levels and a predetermined convolution pattern, providing by a start pattern searcher, a data determiner enable signal by comparing the peak comparator output data and a predetermined start pattern according to the searcher enable signal; and providing, by a data determiner, result data corresponding to the input signal based on the data determiner enable signal, the input signal and a predetermined filter mask pattern..
Samsung Electronics Co., Ltd.


08/11/16
20160232953 
 Strobe acquisition and tracking patent thumbnailStrobe acquisition and tracking
A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal.
Rambus Inc.


08/11/16
20160229298 
 Battery power integration apparatus and hev power system having the same patent thumbnailBattery power integration apparatus and hev power system having the same
A battery power integration apparatus includes a power converter, a battery control module, and a relay. The power converter has an input side and an output side, and the input side is connected to a high-voltage dc voltage.
Delta Electronics, Inc.


08/04/16
20160226476 
 Duty cycle detection circuit and duty cycle correction circuit including the same patent thumbnailDuty cycle detection circuit and duty cycle correction circuit including the same
A duty cycle detection circuit includes a reset unit suitable for resetting a first capacitor and a second capacitor based on a reset signal, a first charging/discharging unit suitable for charging the first capacitor while a clock is in a first level and discharging the first capacitor while the clock is in a second level, a second charging/discharging unit suitable for charging the second capacitor while the clock is in the second level and discharging the second capacitor while the clock is in the first level, and a differential amplifier suitable for amplifying a voltage difference between the first capacitor and the second capacitor based on an amplification enable signal and generating a detection signal as a result of the amplification.. .
Sk Hynix Inc.


07/28/16
20160217847 
 Memory system including plurality of dram devices operating selectively patent thumbnailMemory system including plurality of dram devices operating selectively
A memory system including a plurality of dynamic random access memory (dram) devices and a dram controller is provided. The plurality of dram devices includes one or more dram groups.
Samsung Electronics Co., Ltd.


07/28/16
20160217833 
 Sense amplifier and semiconductor device including the same patent thumbnailSense amplifier and semiconductor device including the same
A sense amplifier may include an amplifying section configured to amplify data of a segment line pair when an enable signal is activated and output amplified data to a local line pair, and including latches electrically coupled in a cross-coupled type. The sense amplifier may include a switching section configured to selectively electrically couple the segment line pair and the local line pair in response to an input/output switch signal..
Sk Hynix Inc.


07/28/16
20160217742 
 Display device that switches light emission states multiple times during one field period patent thumbnailDisplay device that switches light emission states multiple times during one field period
A scan driving circuit includes a shift register unit and a logic circuit unit. The start of a start pulse of an output signal stp+1 of a p+1'th shift register is situated between the start and end of a start pulse of the output signal stp of a p'th shift register, and one each of a first enable signal through a q'th enable signal exist in sequence between the start of the start pulse of the output signal stp and the start of the start pulse of the output signal stp+1.
Sony Corporation


07/28/16
20160216326 

Semiconductor apparatus and operating the same


A semiconductor apparatus includes a debugging processor that performs a debugging operation related to at least one selected intellectual property (ip) block from among a plurality of ip blocks. The debugging processor includes a debugging executing unit, a secure mode setting unit, and a debugging secure unit.
Samsung Electronics Co., Ltd.


07/21/16
20160211835 

Tunable delay circuit and operating method thereof


A tunable delay circuit includes a first multiplexer, a delay chain, and a second multiplexer. The first multiplexer selects an input signal or a feedback signal as a first output signal according to an enable signal.
Mediatek Singapore Pte. Ltd.


07/21/16
20160211026 

Memory with output control


An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device.
Conversant Intellectual Property Management Inc.


07/21/16
20160210937 

Scan line driver


A scan line driver is disclosed. In one aspect, the scan line driver includes a driving signal generation circuit, an output line driving circuit, and a carry transfer circuit.
Samsung Display Co., Ltd.


07/21/16
20160210892 

Display device and driving same


A picture-frame size of a display device including self light-emitting type display elements which are driven by a current is reduced over conventional devices. Transistors for controlling supply of a light-emission enable signal outputted from an emission driver to emission lines are provided between the emission driver and the emission lines.
Sharp Kabushiki Kaisha


07/14/16
20160205288 

Image processing device


An image processing unit receives at least a clock signal, a data enable signal, and an image signal, and outputs at least the clock signal, the data enable signal, and a processed image signal. The image processing unit includes an interface, an estimated vertical synchronizing signal generator, and an image signal processor.
Sharp Kabushiki Kaisha


07/14/16
20160204657 

Wireless power receiver and host control interface thereof


A wireless power receiver, configured to receive power from a wireless power outlet and to communicate with a host for providing electrical power thereto, is provided comprising a secondary inductive coil configured to receive power from a primary coil of the wireless power outlet, and a host control interface configured to facilitate communication between the wireless power receiver and the host. The host control interface comprises contacts, one or more information-carrying contacts configured to conduct at least one of a clock and a data signal between the wireless power receiver and the host, supply input and power supply ground contacts configured to cooperate to provide current between the wireless power receiver and the host, an interrupt-signal contact configured to carry an interrupt signal from the wireless power receiver and the host, and an enable-signal contact configured to carry an enable signal from the host to the wireless power receiver..
Powermat Technologies Ltd.


07/14/16
20160202771 

Control head-mounted information systems


A head-mounted information system is provided, the head-mounted information system comprising a frame configured to be mounted on a head of a user, a display unit coupled to the frame, a sensor unit coupled to the frame comprising one or more motion sensors, and, a processor unit coupled to the frame and connected to receive signals from the motion sensors. The processor unit comprises a processor and a memory accessible by the processor.
Intel Corporation


07/14/16
20160202723 

Method for calibrating a clock signal generator in a reduced power state


Various embodiments of a clock generator are disclosed. An example system may include a functional unit, and a clock generation unit configured to adjust a frequency of an output clock signal responsive to an assertion of an enable signal from the functional unit.
Apple Inc.


07/14/16
20160202713 

Circuit driving


A low dropout regulator includes a pre-regulation circuit, a sustaining circuit coupled to the pre-regulation circuit, and a pass element coupled to the sustaining circuit. The pre-regulation circuit is configured to generate a bias voltage.
Macronix International Co., Ltd.


07/07/16
20160197550 

Memory apparatus, charge pump circuit and voltage pumping method thereof


The invention provides a memory apparatus, a charge pump circuit, and a voltage pumping method thereof. The charge pump circuit including a plurality of delay units, a latch circuit, and a plurality of charge pump units.
Ememorey Technology Inc.


07/07/16
20160196881 

Repair information storage circuit and semiconductor apparatus including the same


A repair information storage circuit may include a fuse block, a controller, and a fuse latch array. The fuse block provides a boot-up enable signal and repair information.
Sk Hynix Inc.


07/07/16
20160196866 

Fast exit from dram self-refresh


Embodiments of the invention describe a dynamic random access memory (dram) device that may abort a self-refresh mode to improve the exit time from a dram low power state of self-refresh. During execution of a self-refresh mode, the dram device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the dram device.
Intel Corporation


07/07/16
20160196795 

Display device


A display device is capable of preventing damage to a driver integrated circuit (ic) when a malfunction occurs therein, the display device including a display panel including a gate line, a data line, a first dummy line, and a second dummy line; a first data driver integrated circuit connected to one side of the data line; a second data driver integrated circuit connected to another side of the data line; a first power supply configured to apply a part of first enable signals to the first data driver integrated circuit, and to apply a part of second enable signals to the second data driver integrated circuit through the second dummy line; and a second power supply configured to apply the rest of the second enable signals to the second data driver integrated circuit, and to apply the rest of the first enable signals to the first data driver integrated circuit through the first dummy line.. .
Samsung Display Co., Ltd.


07/07/16
20160193730 

Robot system and wiring robot system


In a robot system that is configured by a master controller and a slave controller, an input path of a safety input signal and an output path of an enable signal outputted from a safety monitoring unit within the master controller are wired to enable output outside of the master controller, an operating switch and the master controller are connected by a connection cable, the master controller and the slave controller are connected by a connection cable, a control unit of the slave controller is connected to the input path of the safety input signal, and a contact for power is connected to the output path of the enable signal.. .
Denso Wave Incorporated


06/30/16
20160191112 

Symbol interleave for wireless communications


A receiver includes a plurality of de-spreading correlators that are programmed to only correlate a specific portion of the full spreading code according to an interleave factor. Each correlator may be associated with a different symbol.

06/30/16
20160191066 

Method and apparatus to suppress digital noise spurs using multi-stage clock dithering


A clock dithering circuit that provides cancellation of digital noise spurs is disclosed. The clock dithering circuit includes a control unit that receives an input clock.

06/30/16
20160191028 

Low area enable flip-flop


The disclosure provides a flip-flop. The flip-flop includes a master latch.

06/30/16
20160189760 

Nonvolatile memory device, read nonvolatile memory device, and memory system incorporating nonvolatile memory device


A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read data after the strobe signal is toggled a predetermined number of times.. .

06/30/16
20160189582 

In-cell touch liquid crystal display apparatus


Disclosed is an in-cell touch liquid crystal display (lcd) apparatus comprising: an active area in which a plurality of pixels are provided; and a pad area in which an auto probe test pattern is disposed, wherein the auto probe test pattern comprises a common voltage enable signal line; a common voltage switching unit; a data enable signal line through which a data enable signal is applied; and a data switching unit that is coupled to the data enable signal line and configured to be turned on by the data enable signal and output a data voltage. The common voltage enable signal line and the data enable signal line are disposed separately from each other..

06/23/16
20160182902 

Silicon photomultipliers with internal calibration circuitry


A silicon photomultiplier includes a plurality of microcells providing a pulse output in response to an incident radiation, each microcell including circuitry configured to enable and disable the pulse output. Each microcell includes a cell disable switch.

06/23/16
20160182067 

All-digital-phase-locked-loop having a time-to-digital converter circuit with a dynamically adjustable offset delay


An all-digital-phase-locked-loop (adpll) includes a digitally controlled oscillator (dco) arranged to generate a dco output signal, and a feedback loop comprising a set of components for controlling the dco. The set of components comprise: a time-to-digital converter (tdc) arranged to generate a tdc output code indicative of the phase difference between the reference signal and the enable signal measured within the predetermined observation window; a subset of components arranged to generate the enable signal from the dco output signal; and an offset calibration system connected to the tdc output, which when activated is arranged to evaluate the difference between the first and second offset delay values by monitoring the tdc output code generated over a predetermined period of time, and to adjust the difference to position the predetermined observation window with respect to the reference signal..

06/23/16
20160182025 

Semiconductor device and semiconductor system including the same


A semiconductor device may include a control signal generation block configured to shift a level of a trimming signal and generate a selection control signal, and shift a level of a first enable signal and generate a driving control signal, when an internal voltage is raised to a level greater than a sensing reference voltage after an initialization period is ended. The semiconductor device may include an internal voltage generation block configured to select one of a plurality of trimming division voltages as a selected reference voltage in response to the selection control signal, and drive the internal voltage by comparing levels of the selected reference voltage and the internal voltage in response to the driving control signal..

06/23/16
20160182019 

Duty cycle detection circuit and method


A duty cycle detection circuit may include: a timing signal generation unit to generate a plurality of timing signal groups by selectively combining multi-phase clock signals according to an enable signal; and a detection unit to generate a duty detection signal by selectively combining signals of the plurality of timing signal groups according to the enable signal.. .

06/23/16
20160180919 

Multi-channel self refresh device


A multi-channel self refresh device may include period generation circuit configured to output a self refresh pulse signal having a predetermined time period in response to a refresh enable signal. The multi-channel self refresh device may include a channel region configured to activate a refresh signal in response to the self refresh pulse signal, when a self refresh command signal corresponding to a channel from among a plurality of self refresh command signals is activated..

06/23/16
20160180823 

Scanline driver chip and display device including the same


A scanline driver chip includes: a chip selection de-serializer configured to provide an output enable signal based on an enable signal, a clock signal, and serial chip selection data, the serial chip selection data being received in serial order; an address data de-serializer configured to provide parallel address data based on the enable signal, the clock signal, the output enable signal, and serial address data, the serial address data being received in serial order; and a decoder-level shifter configured to provide a scanline enable signal based on the parallel address data. A display device includes: a controller configured to provide an enable signal, a clock signal, serial chip selection data, and serial address data; a plurality of the scanline driver chips each configured to provide a scanline enable signal; and a pixel array configured to be driven based on the scanline enable signal..

06/23/16
20160180766 

Display panel and display device including the same


Display panels and display devices including the display panels are disclosed. In one aspect, a display panel includes a gate driver configured to output a scan line enable signal based on an enable signal and a control signal configured to be determined based on resolution of display data, a data driver configured to output the display data based on the control signal, and a pixel array including a plurality of pixels configured to be enabled by a scan line enable signal and display an image corresponding to the display data..

06/16/16
20160173077 

Method and a brown out detector


The disclosure provides a detector that includes a pre-charge circuit. The pre-charge circuit receives a supply voltage.
Texas Instruments Incorporated


06/16/16
20160172965 

Modulation circuit for enhanced load transient response


A circuit and method for providing improved load transient response in a dc-dc converter. A dcm modulator is incorporated into the converter controller to generate a dcm enable signal for the driver circuits for the converter.
Texas Instruments Incorporated


06/16/16
20160169966 

Integrated circuit with scan chain having dual-edge triggered scannable flip flops and operating thereof


An integrated circuit includes a scan chain, a clock divider circuit, and clock selection circuitry. The scan chain includes a plurality of dual edge flip flops, wherein each dual edge flip flop includes a data input, a scan input, a clock input, and data output.
Freescale Simiconductor, Inc.


06/09/16
20160164666 

Clock and data recovery circuit and system using the same


A clock and data recovery circuit may include a phase detection unit, a first filtering unit, a second filtering unit, and a phase interpolation unit. The phase detection unit compares a clock signal with data and generates a plurality of early phase detection signals and a plurality of late phase detection signals.
Sk Hynix Inc.


06/09/16
20160164501 

Semiconductor apparatus


A semiconductor apparatus includes a pipe input/output signal generation block configured to generate a plurality of pipe input signals and a plurality of pipe output signals according to a pipe enable signal, and be initialized according to an error detection signal; a pipe latch group including a plurality of pipe latches, each of the plurality of pipe latches being configured to receive and store an input signal according to a corresponding pipe input signal and output a stored signal as an output signal according to a corresponding pipe output signal; and an error detection block configured to generate the error detection signal according to a pipe end signal, the pipe enable signal, the plurality of pipe input signals and the plurality of pipe output signals.. .
Sk Hynix Inc.


06/09/16
20160163367 

Semiconductor memory apparatus


A semiconductor memory apparatus may include a decoding control block configured to generate a first decoding control signal and a second decoding control signal in response to a double enable signal and a first address. The semiconductor memory apparatus may include a decoding block configured to enable only one word line among a plurality of word lines or may simultaneously enable at least two word lines among the plurality of word lines, in response to the first and second decoding control signals and a second address..
Sk Hynix Inc.


06/09/16
20160162858 

Screening architectures enabling revocation and update


Methods, devices, systems and computer program products are provided to facilitate signaling of digital rights management (drm) information that is carried within a multimedia content as digital watermarks. The embedded watermarks enable signaling of a change in trustworthiness of particular drm technology, enable addition of new drm technologies to a trusted list of technologies, and facilitate revocation of obsolete or untrustworthy technologies.
Verance Corporation


06/09/16
20160162300 

Semiconductor device and driving the same


A semiconductor device includes an internal signal processing block suitable for generating an internal enable signal and an internal control signal that correspond to an external enable signal and an external control signal, and a monitoring unit suitable for outputting a monitoring signal that corresponds to a predetermined internal signal, based on the internal enable signal and the internal control signal, in an initial operation period.. .
Sk Hynix Inc.


06/02/16
20160157312 

Drivers and driving methods for a led string, capable of providing led short protection or avoiding led flickering


The disclosure regards to drivers and driving methods for a led string consisting of leds. The led string and a current switch are coupled in series between a power line and a ground line.
Leadtrend Technology Corporation


06/02/16
20160155403 

Liquid crystal display and test circuit thereof


A liquid crystal display and a test circuit thereof are provided. The test circuit has a plurality of signal pads, a first data distributor, a plurality of logic circuit units and n switches.
Au Optronics Corp.


05/26/16
20160149575 

Buffer circuit and operation method thereof


A buffer circuit includes an amplification unit suitable for sensing and amplifying an input signal and a reference voltage, a buffer enable unit suitable for enabling the amplification unit based on a buffer enable signal, and a buffer enable signal generation unit suitable for generating the buffer enable signal based on a first or second operation control signal, selected according to a high voltage detection signal.. .
Sk Hynix Inc.


05/26/16
20160148567 

Pixel selection control method, driving circuit, display apparatus and electronic instrument


A pixel selection control method, driving circuit, display apparatus and electronic instrument are disclosed. A driving circuit includes a logic circuit configured to receive a reference signal associated with a line of pixels.
Sony Corporation


05/19/16
20160142055 

Semiconductor device


A semiconductor device includes a first circuit applying an enable signal having a first logic level and a clock signal having the first logic level, supplying a first voltage to a first node and converting a voltage level of the first node into a second logic level different from the first logic level, and a second circuit applying an enable signal having the second logic level and a clock signal having the first logic level, supplying a second voltage to a second node different from the first node and converting a voltage level of the second node into the second logic level. The second circuit includes an operation circuit performing a nand operation on the logic level of the enable signal and the voltage level of the second node, and a switch turned on in response to an output of the operation circuit and supplying the second voltage to the second node..

05/19/16
20160141010 

Semiconductor memory apparatus and system including the same


A semiconductor memory apparatus includes a dbi calculation block, an inversion latch block, an inverted data selective output block, and a pipe latch block. The dbi calculation block performs a dbi calculation and outputs a dbi result signal based on a result of the dbi calculation.
Sk Hynix Inc.


05/19/16
20160141005 

Semiconductor integrated circuit and driving the same


Provided is a semiconductor integrated circuit including a plurality of memory chips stacked therein, each of the memory chips may include: a pumping enable signal control unit suitable for generating a pumping enable signal in response to a power-up signal or a trigger signal received from a first adjacent memory chip, delaying the pumping enable signal by a given time, and outputting the delayed pumping enable signal to a second adjacent memory chip; and a pumping unit suitable for generating a pumping voltage by performing a pumping operation in response to the pumping enable signal.. .
Sk Hynix Inc.


05/19/16
20160140903 

Scanline driver and display device including the same


A scanline driver includes a shift register circuit and an output buffer. The shift register circuit provides a register output signal and a plurality of signals based on a scan input signal and a plurality of clock signals.
Samsung Display Co., Ltd.


05/12/16
20160133309 

Circuits and methods for dqs autogating


In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second buffer.
Altera Corporation


05/12/16
20160132170 

Driving unit for touch electrode, driving circuit, touch panel and driving method


Provided are a driving unit for a touch electrode, a driving circuit, a touch panel and a driving method, wherein the driving unit comprises: a signal conversion unit configured to convert a signal input from the signal input terminal under the control of a clock signal and output the conversion result; a logic computation unit configured to perform a logic computation on the input signal and the touch enable signal and output the computation result; a buffer unit connected to an output terminal of the logic computation unit; and an output unit connected to an output terminal of the buffer unit and configured to output a touch scan signal to the touch driving electrode under the control of a signal output by the buffer unit. The driving circuit comprising multiple stages of driving unit described in the above can be directly integrated in the array substrate..
Boe Technology Group Co., Ltd.


05/12/16
20160129269 

Selectable boost converter and charge pump for compliance voltage generation in an implantable stimulator device


Compliance voltage generation circuitry for a medical device is disclosed. The circuitry in one embodiment comprises a boost converter and a charge pump, either of which is capable of generating an appropriate compliance voltage from the voltage of the battery in the device.
Boston Scientific Neuromodulation Corporation


05/05/16
20160124750 

Power-on method and related server device


A power-on method for a server device includes generating a stand-by power to a server module of the server device when a blade enable signal is asserted; asserting, by the server module, a power-on signal to a storage module of the server device; performing, by the storage module, a first boot-on process when the storage module receives the asserted power-on signal; transmitting, by the storage module, an asserted ready signal to the server module when the first boot-on process finishes; and performing, by the server module, a second boot-on process via a normal power when the server module receives the asserted ready signal.. .
Wistron Corporation


05/05/16
20160124029 

Detection circuit for an active discharge circuit of an x-capacitor, related active discharge circuit, integrated circuit and method


An active discharge circuit discharges an x. The detection circuit includes a sensor circuit that generates a sensor signal indicative of an ac oscillation voltage at the x capacitor.
Stmicroelectronics S.r.l.


05/05/16
20160123200 

Systems for regeneration of a gasoline particulate filter


A system includes a soot module, a coordinator module, a regeneration module, and actuator modules. The soot module determines a current amount of soot mass in a particulate filter of a gasoline engine, where the particulate filter is downstream from the gasoline engine and receives an exhaust gas from the gasoline engine.
Gm Global Technology Operations Llc


05/05/16
20160121604 

Element substrate, printhead, and printing apparatus


An element substrate capable of suppressing occurrence of electromagnetic noise upon driving printing elements on an element substrate with long wiring lengths, preventing an operation error, and printing a high-quality image is provided. In the element substrate, plural element substrates each including printing elements are arrayed in an arrayed direction of the printing elements.
Canon Kabushiki Kaisha


04/28/16
20160118983 

Calibration circuit and calibration apparatus including the same


A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.. .
Sk Hynix Inc.


04/28/16
20160118969 

Delay adjusting apparatus and operating apparatus including the same


A delay adjusting apparatus may include at least one selective delay element electrically coupled to an electrical path between an input terminal and an output terminal of the electrical path, and the at least one selective delay element configured to add a delay factor to the electrical path in response to an enable signal. The delay adjusting apparatus may include at least one fuse circuit configured to control electrical coupling of an e-fuse, in response to a program signal, and program the enable signal..
Sk Hynix Inc.


04/28/16
20160118094 

Semiconductor apparatus capable of self-tunning a timing margin


A semiconductor apparatus may include a delay-locked loop configured to generate a delay-locked clock signal through a delay locking operation of an internal clock signal and an external clock signal, and delay an internal read command by a delay time tuned in the delay locking operation and generate a delay-locked internal command. The semiconductor apparatus may include a tuning control block configured to generate the internal read command in response to a self-tuning enable signal generated by determining a delay locking completion time of the delay-locked loop.
Sk Hynix Inc.


04/28/16
20160118091 

Memory device and performing a write operation in a memory device


The present invention provides a technique for performing write operations within a memory device comprising an array of memory cells. Wordline driver circuitry is used to assert a wordline signal to activate an addressed memory cell in the array.
Arm Limited


04/28/16
20160118088 

Storage device including a plurality of nonvolatile memory chips


A storage device includes first and second nonvolatile memory groups that respectively include first and second nonvolatile memory chips, a memory controller connected to the first and second nonvolatile memory groups in common through input/output lines and at least one control line, and a group select circuit connected to the memory controller through the at least one control line and chip enable lines. The group select circuit is connected to the first and second nonvolatile memory groups through a plurality of first and second chip enable lines, respectively.
Samsung Electronics Co., Ltd.


04/28/16
20160117963 

Scan sense driver and display device including the same


A scan sense driver includes a scan driver and a sense driver. The scan line driver provides a scan line enable signal based on a plurality of clock signals, a global clock signal, and a scan input signal during a scan time interval.
Samsung Display Co., Ltd.


04/28/16
20160115933 

Starting battery for an internal combustion engine


A starting battery for use with an electric starting system includes a starter motor and a battery receiver. The starting battery includes a lithium-ion battery cell, two voltage output terminals, and an enable terminal.
Briggs & Stratton Corporation


04/21/16
20160111172 

Semiconductor device


A semiconductor device includes: a plurality of repair fuse circuits configured to each program a repair target address; and an enable signal generation circuit configured to generate at least one enable signal in response to a source signal and provide the enable signal to each of the repair fuse circuits in common. Since the semiconductor device may iteratively generate a rupture enable signal through a feedback scheme, the area occupied by a circuit, such as a shift register or a d flip-flop may be saved..

04/21/16
20160111135 

Input/output strobe pulse control circuit and semiconductor memory device including the same


An input/output strobe pulse control circuit includes a control signal generator suitable for generating first to third control signals in response to a column selection enable signal and a first input/output strobe pulse signal, a first latch suitable for generating a second input/output strobe pulse signal in response to the first and second control signals, wherein the second input/output strobe pulse signal is enabled at a failing edge of the column selection enable signal and disabled at a falling edge of the first input/output strobe pulse signal, and a second latch suitable for generating a selection control signal for selectively outputting the first input/output strobe pulse signal or the second input/output strobe pulse signal based on whether the first input/output strobe pulse signal is enabled within an enabling section of the column selection enable signal, in response to the second and third control signals.. .

04/21/16
20160109893 

Apparatus and controlling a power supply


Apparatuses and methods for controlling a power supply are provided. First power supply selecting circuit selects a higher voltage from usbin and acin to be first output voltage; first ldo decreases the first output voltage to second output voltage, and closes self-start circuit after receiving reference voltage; second power supply selecting circuit selects a higher voltage from second output voltage and vbat to be third output voltage; second ldo supplies the third output voltage as the first input voltage to reference circuit; reference circuit outputs the reference voltage according to first input voltage; second ldo closes self-start circuit after receiving the reference voltage; voltage detecting circuit supplies an enable signal to second ldo when determining that usbin or acin reaches a threshold voltage according to the reference voltage; and second ldo provides the first input voltage to reference circuit after receiving the enable signal..

04/21/16
20160109141 

Boiler control system and method


The invention provides a boiler control system based on delayed cycle control, in which the control is implemented by interrupting a heating device enable signal (such as a bms enable signal). This means the system can be used with electronic boilers without the boiler being aware (in terms of generating error codes) of the control taking place..

04/14/16
20160105177 

Clock buffers with pulse drive capability for power efficiency


A clock driver is provided. The clock driver includes a multi-stage delay cell having an input, a positive pulse driving branch, a negative pulse driving branch, and an output.

04/14/16
20160105168 

Chip and chip control method


Provided is a chip in which operation state information on a main logic unit operating in response to an enable signal is acquired, and determining whether a toggling condition of the main logic unit is satisfied based on the operation state information.. .

04/14/16
20160105100 

Charge pump system for reducing output ripple and peak current


A charge pump system includes a plurality of pump units, a control circuit, and a detection circuit. The plurality of pump units are used for generating a pump output voltage.

04/07/16
20160099743 

Apparatus and methods for biasing radio frequency switches


Apparatus and methods for radio frequency (rf) switches are provided herein. In certain implementations, an rf switching circuit includes an adaptive switch bias circuit that controls gate and/or channel voltages of one or more field effect transistor (fet) switches.
Analog Devices Global


03/31/16
20160094207 

Voltage generator with charge pump and related methods and apparatus


Aspects of this disclosure relate to voltage generators, such as negative voltage generators. In an embodiment, an apparatus includes a voltage generator, a level shifter, and a semiconductor-on-insulator radio frequency (rf) switch configured to receive a signal from the level shifter.
Skyworks Solutions, Inc.


03/31/16
20160093237 

Source driver and operating method thereof


A source driver circuit is provided which includes a plurality of digital multi-spread (hereinafter referred to as “dms”) blocks configured to generate dms signals for controlling an output timing of a data signal to be transmitted to a display panel from a plurality of clocks which are delayed as much as a reference period one another. Each dms block includes a plurality of sub blocks.
Samsung Electronics Co., Ltd.


03/31/16
20160091911 

Semiconductor apparatus


A semiconductor apparatus includes a control block that generates a first control signal, a second control signal, and a heating enable signal in response to an enable signal and a heating control signal, a temperature measurement block that generates a temperature code corresponding to temperature in response to the first and second control signals, a heater that generates heat while the heating enable signal is being enabled, a code latch block that stores the temperature code in response to the first and second control signals, and outputs a first code and a second code, a control code generation circuit that generates a signal by performing an operation on the first and second codes, and generates a control code by comparing the signal with a preset code, and a reference voltage generation circuit configured to change a voltage level of a reference voltage in response to the control code.. .
Sk Hynix Inc.


03/31/16
20160091563 

Scan flip-flop


A pull cell scan flip-flop includes a scan flip-flop and a pull cell. The pull cell is configured to receive a scan flip-flop output signal from the scan flip-flop, the scan flip-flop output signal having a scan flip-flop output value.
Taiwan Semiconductor Manufacturing Company Limited


03/24/16
20160087539 

Switched mode power converter controller with ramp time modulation


A controller for use in a power converter includes a drive circuit coupled to generate a drive signal to control switching of a power switch to control a transfer of energy from a power converter input to a power converter output. An input for receiving an enable signal including enable events is responsive to the power converter output.
Power Integrations, Inc.


03/17/16
20160079857 

Boost converter and related integrated circuit


A boost converter receives an input voltage and provides an output voltage and includes a power switch and a voltage control circuit configured to drive the power switch as a function of the output voltage. A voltage sensing circuit in the form of a voltage divider is coupled to sense the output voltage and provide a feedback voltage.
Stmicroelectronics S.r.l.


03/17/16
20160078839 

Image sticking elimination circuit and display device


An image sticking elimination circuit comprises signal module (11), switch control module (12) and switch module (13), the signal module (11) has input terminal connected to an enable signal and outputs first control signal according to the enable signal; the switch control module (12) receives the first control signal outputted from the signal module and outputs second control signal; the switch module (13) receives the second control signal outputted from the switch control module (12), and controls the connection or the disconnection between a first electrode (b) and a second electrode (c). By controlling the connection or disconnection of the circuits between the first electrode (b) and the second electrode (c) with the signal module (11), the switch control module (12) and the switch module (13), the charges at the two electrodes are neutralized rapidly by shorting out the first electrode (b) and the second electrode (c) when the display signal is off and the potentials at the two electrodes are equal to eliminate the phenomena of image sticking..
Boe Technology Group Co., Ltd.


03/17/16
20160078818 

Voltage providing circuit and display device including the same


A display device includes a data driver configured to generate a data signal based on a data voltage; a display panel configured to be driven based on a first power supply voltage and the data signal; a timing controller configured to control operations of the data driver and the display panel and configured to generate a ready signal indicating a power supply timing; a first voltage regulator configured to generate the first power supply voltage based on a first input voltage and a first enable signal; a second voltage regulator configured to generate the data voltage based on the first input voltage and a second enable signal; and a power sequence controller configured to generate the first enable signal based on the ready signal and the data voltage and configured to generate the second enable signal based on the ready signal and the first power supply voltage.. .
Samsung Display Co., Ltd.


03/10/16
20160072492 

Delay circuits and related systems and methods


Delay circuits, and related systems and methods are disclosed. In one aspect, a delay circuit is provided that uses logic to delay accurately an output enable signal to reduce or avoid data hazards within a slave device.
Qualcomm Incorporated


03/10/16
20160072479 

Semiconductor apparatus


A semiconductor apparatus includes a command decoding unit configured to decode an internal command, an internal clock and an internal clock enable signal, and generate an internal control signal; a clock enable signal control unit configured to receive a pre-clock enable signal and output one of the pre-clock enable signal and an enabled internal clock enable signal as the internal clock enable signal in response to a first test signal; an enable signal selection unit configured to output one of the pre-clock enable signal and a second to test signal as a counting enable signal in response to the first test signal; and a counting unit configured to perform a counting operation during an enable period of the counting enable signal, and output a counting code.. .
Sk Hynix Inc.


03/10/16
20160071615 

Semiconductor memory apparatus


A semiconductor memory apparatus includes an internal data generation block configured to generate test data in response to test signals, and output ones of normal data inputted from data input/output pads and the test data as internal data according to a test flag signal; a data storage region configured to receive and store the internal data, and output stored data as cell storage data; a latch block configured to receive and store the cell storage data in response to a data output enable signal, and output stored data as latch data; and a data comparison block configured to compare the test data and the latch data, and generate a test result signal.. .
Sk Hynix Inc.


03/10/16
20160071574 

Method and circuits for low latency initialization of static random access memory


A method and various circuit embodiments for low latency initialization of an sram are disclosed. In one embodiment, an ic includes an sram coupled to at least one functional circuit block.
Apple Inc.


03/10/16
20160070289 

Voltage generating circuit


A voltage generating circuit includes a voltage control circuit that includes an output section and a reference voltage terminal to which a reference voltage is supplied, and outputs a voltage to the output section which is controlled so as to be equal to a voltage of the reference voltage terminal, a first voltage dividing mos transistor having a first end connected to the output section, and a second voltage dividing mos transistor having a first end connected to a second end of the first voltage dividing mos transistor. The voltage generating circuit further includes an auxiliary circuit having a set terminal to which an enable signal is supplied.
Kabushiki Kaisha Toshiba


03/10/16
20160069959 

Semiconductor apparatus and test device therefor


A semiconductor apparatus includes a clock enable signal buffer unit configured to receive an input clock enable signal, and generate an output clock enable signal; a buffer control unit configured to generate a buffer enable signal in response to the output clock enable signal and a test enable signal; an input/output buffer unit configured to receive input patterns and generate output patterns; and a compression test unit configured to test the output patterns and the output clock enable signal according to the test enable signal.. .
Sk Hynix Inc.


03/03/16
20160064101 

Semiconductor device and semiconductor system including the same


A semiconductor system may include a first semiconductor device including a first pad group. The semiconductor system may include a second semiconductor device including a second pad group which is configured for input and output of signals from and to a third semiconductor device.
Sk Hynix Inc.


03/03/16
20160064048 

Asynchronous/synchronous interface


The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact.
Micron Technology, Inc.


03/03/16
20160062430 

Mitigation of power supply disturbance for wired-line transmitters


A wired-line transmitter may include architecture that provides control of the current profile during power-up and/or power-down of the transmitter. The current profile may include a sloped ramp up during power-up and/or a sloped ramp down during power-down.
Apple Inc.


02/25/16
20160056987 

Multi iq-path synchronization


Aspects of a wireless apparatus and a method for handling a modulated signal include a frequency generator that produces a clock signal, a first synchronization circuit that generates a first sync enable signal based on an even edge of the clock signal, a second synchronization circuit that generates a second sync enable signal based on an even edge of the clock signal, a first divider having a first initial operating condition that generates a first iq path based on the first sync enable signal, and a second divider having a second initial operating condition that generates a second iq path based on the second sync enable signal, wherein the first and second operating conditions are not equal when initially powered.. .
Qualcomm Incorporated


02/25/16
20160055899 

Fast exit from dram self-refresh


Embodiments of the invention describe a dynamic random access memory (dram) device that may abort a self-refresh mode to improve the exit time from a dram low power state of self-refresh. During execution of a self-refresh mode, the dram device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the dram device.
Intel Corporation


02/18/16
20160050403 

Image processing device and image processing method


An image processing device includes a plurality of mixer units, a plurality of scale processing units, and an enable signal processing unit. A mixer unit of the plurality of the plurality of mixer units selects one of an output of another mixer unit of the plurality of mixer units, and an output image of a scale processing unit of the plurality of scale processing units to generate a composite image..
Renesas Electronics Corporation


02/18/16
20160049930 

Integrated clock gater (icg) using clock cascode complimentary switch logic


Inventive aspects include an integrated clock gater (icg) circuit having clocked complimentary voltage switched logic (cicg) that delivers high performance while maintaining low power consumption characteristics. The cicg circuit provides a small enable setup time and a small clock-to-enabled-clock delay.

02/18/16
20160048182 

Micro-controller reset system and reset method thereof


A reset system comprises an enable circuit, a buck converter and a reset circuit. The enable circuit is connected to a system power source.
Inventec Corporation


02/18/16
20160047853 

Test system that performs simultaneous tests of multiple test units


A test system includes row decoder, column decoder, row test controller, and test circuit. The row decoder activates one of first through m-th row signals based on plurality of row input signals.
Samsung Electronics Co., Ltd.




Enable Signal topics: Enable Signal, Control Unit, Electronic Device, Integrated Circuit, Semiconductor, Output Enable, Liquid Crystal, Liquid Crystal Display, Data Transfer, Buffer Circuit, Esd Protection Circuit, Protection Circuit, Electrostatic Discharge, Esd Protection, Programmable Memory

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