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Date/App# patent app List of recent Enable Signal-related patents
02/04/16
20160036448 
 Electronic device and electronic system including the same patent thumbnailElectronic device and electronic system including the same
An electronic device includes a control logic portion suitable for generating a hold control signal based on a count enable signal, and a counting portion suitable for performing a counting operation while a latch operation stops during a counting section and performing the latch operation while the counting operation stops during a holding section based on the hold control signal and a counting clock signal.. .
Sk Hynix Inc.


02/04/16
20160036434 
 Semiconductor integrated circuit device patent thumbnailSemiconductor integrated circuit device
A semiconductor integrated circuit device includes a power domain area on a semiconductor substrate, that includes a circuit block for executing a predetermined function, a first power source line that receives an external power source voltage, a second power source line that is connected to the circuit block, a first power switch circuit in a peripheral area of the power domain area, that connects the first power source line and the second power source line in response to a first enable signal, and a second power switch circuit in the power domain area, that connects the first power source line and the second power source line in response to a second enable signal.. .
Kabushiki Kaisha Toshiba


02/04/16
20160036428 
 Fine-grained power gating in fpga interconnects patent thumbnailFine-grained power gating in fpga interconnects
Systems and methods for power gating in logic and/or computing circuitry in accordance with embodiments of the inventions are disclosed. In one embodiment, a multiplexer for fine-grain power gating includes a first supply voltage and a second supply voltage, a plurality of inputs, a plurality of selection inputs, a selection circuitry configured to select one of the plurality of inputs, where one of the plurality of inputs is the first supply voltage and one of the selection inputs is a power gating enable input, an output inverter stage including a pmos transistor and an nmos transistor, where at least one input to the inverter stage is provided to the gates of the pmos and nmos transistors and selection of the power gating enable signal applies the first supply voltage to the gate of the pmos transistor and places the pmos transistor in a cutoff mode of operation..
The Regents Of The University Of California


02/04/16
20160035399 
 Method and  asynchronous fifo circuit patent thumbnailMethod and asynchronous fifo circuit
The disclosure provides an asynchronous fifo circuit that includes a data memory which is coupled to a write data path and a read data path. The data memory receives a write clock and a read clock.
Texas Instruments Incorporated


01/21/16
20160020776 
 Phase-locked loop (pll) patent thumbnailPhase-locked loop (pll)
A phase-locked loop (pll) is provided. The pll comprises a dithering circuit that is configured to receive a second tuning signal, and dither the second tuning signal to generate a dither signal to decrease a magnitude of a spur of the pll.
Taiwan Semiconductor Manufacturing Company Limited


01/21/16
20160020687 
 Power module patent thumbnailPower module
A power module including: a power conversion unit including n switching-element pairs; and a control circuit. The control circuit receives n command signals, which correspond respectively to the n switching-element pairs, and a shared enable signal.
Mitsubishi Electric Corporation


01/21/16
20160019848 
 Timing controller and display device patent thumbnailTiming controller and display device
When applying exogenous noise with a synchronizing signal or a transmission clock period, influence by the applied noise is inhibited from appearing on a liquid crystal display, without increasing circuit size. There are included: a timing controller generating a control signal of a scanning line driving gate driver and a control signal of a signal line driving source driver based on an input signal to be a reference inputted from the outside; an enable signal generation unit including a noise detecting circuit for detecting various items of noise entering the input signal and outputs an enable signal for turning off or on the output of a gate driver control signal for a predetermined period based on output from the noise detecting circuit; and an image data output control circuit when detecting noise synchronized in a vertical period.
Nlt Technologies, Ltd.


01/07/16
20160006421 
 Frequency synthesiser circuit patent thumbnailFrequency synthesiser circuit
The invention relates to frequency synthesiser circuits, and in particular to frequency synthesiser circuits characterised by a small channel spacing. Embodiments disclosed include a frequency synthesiser circuit (100) for a radio receiver, the circuit comprising: a digitally controlled oscillator (118) configured to generate an output signal (128) with an output frequency on application of an oscillator enable signal (126); a delay module (160; 210) configured to delay an input reference signal (142) to generate a delayed reference signal (144; 244); and a duty cycle module (150) configured to modulate the oscillator enable signal based on a period of an input reference signal (142) and the delay of the delayed reference signal (144), such that a ratio between the output frequency and the frequency of the input reference signal (142) is a non-integer..
Nxp B.v.


01/07/16
20160006348 
 Charge pump apparatus patent thumbnailCharge pump apparatus
The invention provides a charge pump apparatus including a clock signal generator, a clock freezing circuit, a charge pump circuit, and a feedback circuit. The clock signal generator generates a clock signal.
Ememory Technology Inc.


01/07/16
20160005465 
 Content addressable memory patent thumbnailContent addressable memory
The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each cam cell of a cam memory array via a search line pair.
Renessas Electronics Corporation


01/07/16
20160005446 

Memory controller for strobe-based memory systems


An integrated circuit (ic) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal.
Rambus Inc.


01/07/16
20160003461 

Luminare having multiple sensors and independently-controllable light sources


A lighting device includes a first light source having a first light source switch and a first light element array, and a second light source having a second light source switch and a second light element array. The lighting device also includes a light sensor and a motion sensor.
International Development Llc


12/31/15
20150382418 

High-precision led control circuit, method and led driver thereof


In one embodiment, a light-emitting diode (led) driver can include: (i) a reference voltage control circuit configured to provide a reference voltage signal in response to an enable signal; (ii) a current control circuit configured to control an output current of the led driver in response to the reference voltage signal; and (iii) the led driver being configured to drive an led load when the enable signal is active.. .
Silergy Semiconductor Technology (hangzhou) Ltd


12/31/15
20150381197 

Driving voltage generator and digital to analog converter


A digital to analog converter is disclosed. The invention provides a digital to analog converter (dac) including a plurality of voltage transmitting switches and a selecting signal decoder.
Novatek Microelectronics Corp.


12/31/15
20150381158 

Device and clock signal loss detection


A device, comprises a first counter and a second counter, a control unit and a comparing unit. The first counter and the second counter are configured to alternately count a cycle number of a monitoring clock signal.
Montage Technology (shanghai) Co., Ltd.


12/31/15
20150380090 

Nonvolatile memories having data input/output switches and data storage devices and methods using the same


A nonvolatile memory includes a memory cell array including a plurality of memory cells, a pad configured to be connected to a data input/output line, and an input/output circuit configured to receive data to be programmed in the memory cell array and to transmit data read from the memory cell array. The nonvolatile memory further includes a switch configured to couple and decouple the pad and the input/output circuit responsive to a switch control signal and a control circuit configured to generate the switch control signal responsive to a chip enable signal.
Samsung Electronics Co., Ltd.


12/31/15
20150380068 

Semiconductor memory device and operating the same


A semiconductor memory device includes: an enable signal generation portion suitable for generating a data output enable signal activated at a predetermined first moment corresponding to column address strobe (cas) latency based on a read command, a strobe signal generation portion suitable for generating a data strobe signal which has a preamble section until the data output enable signal is activated from a predetermined second moment ahead of the first moment based on the read command and toggles based on a source clock during an activated section of the data output enable signal, and a data output portion suitable for outputting internal data in synchronization with the data strobe signal during the activated section of the data output enable signal.. .
Sk Hynix Inc.


12/31/15
20150380067 

Memory controller


A system provides synchronous read data sampling between a memory and a memory controller, which includes an asynchronous fifo buffer and which outputs a clock and other control signals. An outbound control signal (e.g., read_enable) is used to time-stamp the beginning of a read access using a clock edge counter.
Freescale Semiconductor, Inc.


12/31/15
20150378427 

Apparatuses and methods of entering unselected memories into a different power mode during multi-memory operation


Disclosed are examples of apparatuses including memory devices and systems comprising memories sharing a common enable signal, wherein the memories may be put into different power modes. Example methods for setting the different power modes of the memories are disclosed.
Micron Technology, Inc.


12/31/15
20150378323 

Intelligent switching


An intelligent switching method and system. The method includes retrieving by a computer processor of an intelligent switching device, detection data indicating that an individual is located within a specified proximity of an apparatus.
International Business Machines Corporation


12/31/15
20150377966 

Monitoring circuit of semiconductor device


The monitoring circuit of a semiconductor device includes: a boot-up controller configured to generate a boot-up enable signal in response to a power-up signal and a boot-up command signal; a read-period generator configured to output a read-period signal in response to a boot-up read signal; and a monitoring unit configured to output the read-period signal to an external output terminal during activation of the boot-up enable signal to allow the read-period signal to be monitored.. .
Sk Hynix Inc.


12/31/15
20150374040 

Electronic cigarette


An electronic cigarette includes a control chip, the control chip includes: a driving module configured to output a current to drive the electronic cigarette to work; an open-circuit detecting module electrically connected to the driving module, and configured to sample and detect the current, and send out an open-circuit enable signal when a sampled current is less than a internal reference current; a short-circuit detecting module electrically connected to the driving module, and configured to sample and detect the current, and send out a short-circuit enable signal when the sampled current is greater than the internal reference current; and a control module electrically connected to the driving module, and configured to receive the open-circuit enable signal and the short-circuit enable signal, and send a shutdown signal to the driving module.. .
Shenzhen Smoore Technology Limited


12/24/15
20150372932 

Method and checking data frame length


A method and apparatus for checking a data frame length relate to an ethernet passive optical network in the communication field. The method includes: during reception of an ethernet frame, when determining through analysis that a received ethernet frame is a data frame, extracting frame length information and frame indication information in the data frame, and calculating a frame length mantissa according to the frame length information; writing the data frame into a small cache for storage according to the frame indication information, and counting write enable signals used for controlling writing of a data frame by using a base-n counter, so as to obtain a count value of the write enable signal; and comparing the frame length mantissa with the count value, and if a comparison result is consistent, then a data frame length being successfully checked, and writing the frame length information into the small cache for storage..
Zte Corporation


12/24/15
20150372477 

Apparatus for transmitting power and control method thereof


Disclosed are an apparatus for transmitting power and a control method thereof. The apparatus includes a first main relay electrically controlling connection between a positive (+) terminal of a high voltage power source and a positive (+) terminal of a high voltage load, a second main relay electrically controlling connection between a negative (−) terminal of the high voltage power source and a negative (−) terminal of the high voltage load, a semiconductor switch connected in parallel to the first main relay, a reverse current preventer interposed between the semiconductor switch and the high voltage power source and preventing reverse current to the high voltage power source, a drive state measurer measuring a drive state of a power relay assembly, and a relay controller supplying or shutting off power to the high voltage load by operating the first and second main relays and the semiconductor switch in response to a relay enable signal from a battery controller and shutting off the power to the high voltage load upon determining that the drive state of the power relay assembly measured through the drive state measurer is abnormal or upon determining based on a vehicle state received from the battery controller that a vehicle is in an emergency state..
Kyungshin Co., Ltd.


12/17/15
20150365080 

System and a pulse generator


According to an embodiment, a method of generating a clock pulse includes receiving a leading edge at a clock input at a time when an enable signal is active, generating an edge at a clock output based on the received leading edge at the clock input, latching a logic value corresponding to the edge at the clock output, preventing changes at the clock input from affecting the latched logic value after the logic value is latched, resetting the latched logic value after a first delay time, and maintaining the reset logic value until a second edge is received at the clock input. The second edge at the clock input matches the leading edge at the clock input..
Stmicroelectronics International N.v.


12/17/15
20150365076 

Clock buffers with pulse drive capability for power efficiency


A clock driver and corresponding method are provided. The clock driver includes a multi-stage delay cell having logic circuitry and a plurality of serially connected delay elements.
International Business Machines Corporation


12/17/15
20150364174 

Word line driver circuit and resistance variable memory apparatus having the same


A world line driver circuit according to an embodiment includes a driving unit configured to output a sub word line driving signal in response to a word line select signal and a main word line driving signal, a transmission unit configured to transmit the sub word line driving signal to a word line in response to a first enable signal, and a precharge unit configured to precharge a potential of the word line.. .
Sk Hynix Inc.


12/17/15
20150362987 

Power mode management of processor context


A system having multiple power mode types, for example, includes a power manager that is responsive to a selection of a suspend power mode type for maintaining processor context information in volatile memory while the processor is in the selected suspend mode. A status register is arranged to retain the status of the context information in the volatile memory while the processor is in the selected suspend power mode.
Texas Instruments Deutschland Gmbh


12/17/15
20150362945 

Internal voltage generation circuit of semiconductor apparatus


An internal voltage generation circuit may include a first internal voltage generation block configured for receiving a first external voltage and for generating an internal voltage with a voltage level corresponding to a voltage level of a first reference voltage; and a second internal voltage generation block configured for receiving a second external voltage, generate the internal voltage with a voltage level corresponding to a voltage level of a second reference voltage, compare voltage levels of the second reference voltage and the internal voltage, and generate a comparison signal, wherein only one of the first and second internal voltage generation blocks is activated and the other is deactivated, in response to an enable signal, and the second internal voltage generation block disables the comparison signal to a voltage level of the first external voltage when the first internal voltage generation block is activated.. .
Sk Hynix Inc.


12/03/15
20150349730 

Apparatus and methods power amplifier biasing


Apparatus and methods for biasing a power amplifier are disclosed. In one embodiment, a method of biasing a power amplifier includes shaping an enable signal using a time-dependent signal generator to generate a control current, amplifying the control current using a current amplifier to generate a correction current, and generating a bias current for a power amplifier using a primary biasing circuit.
Skyworks Solutions, Inc.


12/03/15
20150348941 

Stack package and reduction of standby current


The stack package includes: a plurality of chips each stacked with a plurality of layers; and a plurality of pads respectively formed on the plurality of chips. Each chip includes: a ground path unit configured to form a current path between a pad and a ground stage; a selection unit configured to selectively control a connection path electrically coupled to the pad according to a chip enable signal; and a controller configured to selectively control a connection between the selection unit and the ground path unit according to a control signal..
Sk Hynix Inc.


12/03/15
20150348479 

Method of driving light source, light source apparatus and display apparatus having the light source apparatus


A method of driving a light source includes outputting a light source driving signal and outputting a delayed driving signal. The light source driving signal drives a light source based on image data.
Samsung Display Co., Ltd.


12/03/15
20150348472 

Display panel drivers


This disclosure provides systems, methods and apparatus for providing voltages to an arrangement of display modules in a display. In one aspect, a group including multiple rows of display modules may be provided a reset signal at the same time.
Qualcomm Mems Technologies, Inc.


12/03/15
20150347896 

Electronic comparison systems


An electronic comparison system includes input stages that successively provide bits of code words. One-shots connected to respective stages successively provide a first bit value until receiving a bit having a non-preferred value concurrently with an enable signal, and then provide a second, different bit value.
Purdue Research Foundation


11/26/15
20150339963 

Current slope control method and appartus for power driver circuit application


A low side driver includes a first transistor coupled in series with a second transistor at a low side voltage node for a load. A capacitance is configured to store a voltage and a voltage buffer circuit has an input coupled to receive the voltage stored by the capacitance and an output coupled to drive a control node of the second transistor with the stored voltage.
Stmicroelectronics (shenzhen) R&d Co. Ltd


11/19/15
20150334622 

Apparatus and method to perform lte/wlan handoff by keeping lte attached or in suspended state


Systems and methods are disclosed to provide offloading procedures that reduce signaling load. Specifically, embodiments of the present disclosure provide offloading techniques that enable signaling overhead caused by attachment procedures to be avoided when user equipment (ue) reconnects to a cellular network after offloading data to a wireless local area network (wlan).
Broadcom Corporation


11/19/15
20150333511 

Energy lockout in response to a planar catastrophic fault


A computer planar includes an enable signal line for providing an enable signal to an external power supply, wherein the external power supply will not turn on unless the enable signal is active high. During normal operation, an auxiliary power source maintains an active high enable signal on the enable signal line, which includes a fuse.
International Business Machines Corporation


11/19/15
20150331434 

Method and apparatus to minimize switching noise disburbance


A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit.
Telefonaktiebolaget L M Ericsson (publ)


11/19/15
20150331044 

Scan flip-flop circuit with los scan enable signal


A scan flip-flop for generating an output signal based on a first input signal, a clock signal, a test input signal, a launch on shift (los) signal, a test enable signal, and a reset signal includes a logic circuit, a multiplexer and a flip-flop circuit. The logic circuit receives an inverted clock signal, the test enable signal, a intermediate test enable signal, and the los signal, and generates an intermediate output signal that is an inherent los scan enable signal.
Freescale Semiconductor, Inc.


11/12/15
20150326226 

Load switch for controlling electrical coupling between power supply and load


Circuits and methods for controlling electrical coupling by a load switch are disclosed. In an embodiment, the load switch includes a pass element, level-shift circuit and low-resistance active path.
Texas Instruments Incorporated


11/12/15
20150326008 

Fault protection circuit


A fault detection circuit for use with a power converter includes an initiate fault check circuit coupled to generate an enable signal in response to a first sense signal coupled to be received from an output socket. A threshold detection circuit is coupled to generate a threshold detection output signal in response to a second sense signal coupled to be received from the power converter and a second reference signal.
Power Integrations, Inc.


11/12/15
20150323960 

Method for asynchronous gating of signals between clock domains


An apparatus for synchronizing a signal from a first clock domain into a second clock domain is disclosed. The apparatus may include circuitry, a synchronization circuit, and a clock gate circuit.
Apple Inc.


11/12/15
20150323579 

Duty cycle detector and semiconductor integrated circuit apparatus including the same


A duty cycle detector may include a rising clock detection unit enabled in response to a first control signal; a falling clock detection unit enabled in response to a second control signal with a different activation timing from the first control signal; and a comparison unit configured to compare an output signal of the rising clock detection unit to an output signal of the falling clock detection unit in response to a comparison enable signal, and output a duty cycle detection signal.. .
Sk Hynix Inc.


11/05/15
20150318857 

Synchronised logic circuit


Consistent with an example embodiment, the disclosed includes a synchronised logic circuit comprising: an input module; an output module; a decision logic module connected between the input and output modules and configured to provide a next output state to the output module dependent on a current input state provided from the input and output modules; a clock module connected to the input and output modules and configured to provide a clock signal for synchronising operation of the input and output modules; and an input detection module connected to the input module and configured to provide an enable signal to the clock module on detection of a change in an input provided to the input module, wherein the clock module is configured to provide a clock signal to the input and output modules on receiving the enable signal from the input detection circuit.. .
Nxp B.v.


10/22/15
20150303900 

Isolation circuit


An isolation circuit includes a first multiplexer, a d flip-flop, a second multiplexer, an or gate, and an and gate. The first multiplexer selects a data signal or a scan-in signal as a first element output signal according to a scan enable signal.
Via Technologies, Inc.


10/15/15
20150296579 

Light emitting diode driving circuit, display device, lighting device, and liquid crystal display device


As a result of being provided with an enable signal generating unit that supplies, to an led driver, an enable signal that is dependent on a low state period of a pwm signal, it is possible to realize a light emitting diode driver circuit that can suppress a booster circuit starting up suddenly and an excess current flowing in a power source in the case where the pwm signal enters a high state (on state) after having been held in a low state (off state) for a prescribed period or longer.. .

10/15/15
20150296160 

Linear image sensor and driving method therefor


A logical gate circuit (5) and four stages of flip flips (4a-4d) are assigned to each pixel (1). A controller (7) inputs four phase identification signals into the logical gate circuit (5) and also inputs a start signal str into a shift register (4) synchronously with the four mutually different phases defined by the phase identification signals.

10/15/15
20150295500 

Sampling for dimmer edge detection in power converter


A controller and a method for controlling a power converter includes a sample block coupled to generate a first, second, and third sample by sampling an input sense signal that is representative of an input voltage of the power converter. An enable signal is asserted when a first difference between the first sample and the second sample exceeds a first threshold.

10/08/15
20150288278 

Charge pump regulator with small ripple output signal and associated control method


A charge pump regulator includes a charge pump circuit, a voltage divider, a mode determining circuit, a frequency divider, and a selecting circuit. The charge pump circuit receives an oscillation signal and generates an output signal.

10/08/15
20150287447 

Semiconductor devices and semiconductor systems including the same


Semiconductor devices are provided. The semiconductor device includes a control signal generator and a first data input unit.

10/08/15
20150287364 

Pixel circuit and display device using the same


A pixel circuit includes four transistors, two capacitors and a light emitting element. A gate of first transistor receives a scan signal and a source/drain thereof receives a display data.

10/08/15
20150285858 

Test mode entry interlock


An integrated circuit haying normal and special operating modes includes a mode entry interlock (201) which is enabled by an initialization command and an externally supplied voltage at a first i/o terminal (204) to detect a conflict at the i/o terminal for reducing the likelihood of inadvertent entry into the special operating mode. The mode entry interlock also includes a second i/o terminal (212) for receiving a disassociated software command to enter into the special operating mode, and mode control logic (210, 216) for evaluating the received software command against any detected conflict at the i/o terminal to generate a special operating mode enable signal in response to receiving the first and second input signals only when the detected logic state conflicts with the first logic state..

10/01/15
20150280721 

Clock delay detecting circuit and semiconductor apparatus using the same


Provided is a clock delay detecting circuit and semiconductor apparatus using the same that is capable of generating a period signal whose period is a delay time of a clock, dividing the period signal, and counting the divided period signal. The clock delay detection circuit comprises a period signal generating unit configured to generate a counting control signal, a period signal dividing unit configured to generate a counting enable signal by dividing the counting control signal, and a counting unit configured to generate a delay information signal by counting the counting enable signal with a clock, wherein the counting control signal has a period with a predetermined time..
Sk Hynix Inc.


10/01/15
20150275909 

Control device and control method


A control device, applied to a fan, including a first temperature sensing circuit, a second temperature sensing circuit and a driving circuit. The first temperature sensing circuit is arranged to output an enable signal when the temperature is higher than a first threshold temperature.
Accton Technology Corporation


09/24/15
20150270995 

Receiver of semiconductor apparatus and semiconductor system including the same


A receiver of a semiconductor apparatus includes a first buffer unit configured to buffer a first positive input signal and a first negative input signal having a phase opposite the phase of the first positive input signal and to output the buffered first positive input signal as a first positive transmission signal and to output the buffered first negative input signal as a first negative transmission signal in response to a first enable signal, a second buffer unit configured to buffer a second positive input signal and a second negative input signal having a phase opposite the phase of the second positive input signal and to output the buffered second positive input signal as a second positive transmission signal and to output the buffered second negative input signal as a second negative transmission signal in response to a second enable signal, is and an output unit configured to invert one of the first and second positive transmission signals and to output the inverted one of the first and second positive transmission signals as a positive output signal, and to invert one of the first and second negative transmission signals and to output the inverted one of the first and second negative transmission signals as a negative output signal.. .
Sk Hynix Inc.


09/24/15
20150270775 

Fast startup charge pump


A charge pump is designed to be capable of quick start up. When the enable signal of the charge pump is arrived, the pump capacitor and the load capacitor of the charge pump can be charged in a short time, referred to as a pre-charging stage.
Smarter Microelectronics (guang Zhou) Co., Ltd


09/24/15
20150269378 

Use of a physical unclonable function for checking authentication


In order to check authentication using a physical unclonable function, an authenticator includes a physical unclonable function (puf) and an authentication checking function. A challenge response pair provides challenge information and a response for the authenticator.
Siemens Aktiengesellschaft


09/17/15
20150263769 

Single-input multiple-output power amplifier


An rf amplifier, including: an input rf chain configured to receive and process an input rf signal including a plurality of frequency bands within a first band group and output a first signal; and a plurality of output rf chains coupled to the input rf chain, each output rf chain of the plurality of output rf chains configured to process the first signal within at least one band of the plurality of frequency bands of the first band group, wherein each output rf chain includes a bias circuit configured to receive an enable signal to enable the processing of the first signal within the at least one band and output an output rf signal within the at least one band.. .
Qualcomm Incorporated


09/17/15
20150262665 

Memory device


According to one embodiment, a memory controller sends a periodic control signal from a first terminal on a non-volatile memory side to the non-volatile memory, and the control signal includes a data strobe signal, a write enable signal, and a read enable signal.. .
Kabushiki Kaisha Toshiba


09/17/15
20150262655 

Negative bitline boost scheme for sram write-assist


A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element.
Taiwan Semiconductor Manufacturing Co., Ltd.


09/17/15
20150262646 

Semiconductor device


A semiconductor device may include a write control block configured to generate a plurality of write enable signals for controlling a write operation, and a write delay block configured to apply delay times to a plurality of write data which are transmitted through a write global input/output line. The semiconductor device may also include a plurality of banks configured to operate in response to the plurality of write enable signals and receive the plurality of write data, wherein the plurality of write data have different delay times according to physical positions of the plurality of banks..
Sk Hynix Inc.


09/10/15
20150256914 

System and a transducer system with wakeup detection


According to embodiments described herein, a circuit includes an interface circuit configured to be coupled to a transducer and a detection circuit. The interface circuit is configured to provide a digital output signal to a signal input terminal of a processing circuit.
Infineon Technologies Ag


09/10/15
20150256820 

Shutter glass and control controlling the same


The present invention provides a shutter glasses and a system and method for controlling the shutter glasses. The system includes: a receiver for receiving a 3d_enable signal and a stv signal; a timer for timing from the moment when the 3d_enable signal is in high level, and retiming once the stv signal triggered by a positive source is detected; and a resetter for resetting left and right shutter control signals at the moment when the stv signal is triggered by a positive source if the time started by the timer until the sw signal triggered by a positive source comes is longer than a set time, so that openings of left and right shutters of the shutter glasses synchronize with the left and right image signals.
Shenzhen China Star Optoelectronics Technology Co., Ltd.


09/10/15
20150254390 

Shared channel masks in on-product test compression system


A semiconductor chip includes a first mask logic. The first mask logic includes a first mask and a second mask that mask a respective first scan channel output and a second scan channel output.
International Business Machines Corporation


09/10/15
20150254387 

Shared channel masks in on-product test compression system


A semiconductor chip includes a first mask logic. The first mask logic includes a first mask and a second mask that mask a respective first scan channel output and a second scan channel output.
International Business Machines Corporation


09/03/15
20150248928 

Boost system for dual-port sram


A boost system for dual-port sram includes a comparator and a boost circuit. The comparator is configured to compare a first row address of a first port and a second row address of a second port, and output a first enable signal.
Taiwan Semiconductor Manufacturing Company Ltd.


08/27/15
20150243455 

Control circuit of switch device


The invention provides a control circuit of a switch device. A single output pin of the control unit outputs an enable signal to control terminals of two switch units to control an on-state of the two switch units, and adjust a current size of a control current of the on-state of the switch device.
Fsp Technology Inc.


08/27/15
20150243208 

Organic light emitting display device and driving method thereof


An organic light emitting display includes: a data driver configured to supply a data signal to data lines, corresponding to a data enable signal during a driving period in which an image is displayed; and a timing controller configured to supply data and the data enable signal to the data driver, wherein a first data enable signal having a first period and a second data enable signal having a second period differing from the first period are included in the data enable signal supplied during one frame period.. .
Samsung Display Co., Ltd.


08/27/15
20150242331 

Controlling access to a memory


A memory protection device for controlling access to a memory and a method of controlling access to a memory are disclosed. A memory status value held by latch circuitry in the memory protection device determines whether the memory is an enabled or a disabled state.
Arm Limited


08/27/15
20150241513 

Core circuit test architecture


A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths.
Texas Instruments Incorporated


08/20/15
20150235684 

Semiconductor apparatus


A semiconductor apparatus includes: a command control unit configured to decode external signals and generate a read strobe signal or a write strobe signal; a clock enable signal generation unit configured to activate one of a read clock enable signal and a write clock enable signal in response to the read strobe signal or the write strobe signal; and a clock control unit configured to generate a first control clock signal and a second clock control signal in response to an internal clock signal, the read clock enable signal, and the write to clock enable signal.. .
Sk Hynix Inc.


08/13/15
20150229222 

Power supply an electrical appliance


A power supply apparatus includes a power supply circuit and a power-on circuit. The power-on circuit detects a remotely transmitted control signal and causes a transition of the power supply circuit to a turned on state.
Stmicroelectronics S.r.l.


08/13/15
20150228421 

Safety door switch apparatus


An apparatus generates a machine operation enable signal as a function of a closed position of a movable safety access door of a safety guard for a work cell. A pivotal plate carries a handle and a switch receiver.
Toyota Motor Engineering & Manufacturing North America, Inc.


08/13/15
20150228318 

Nonvolatile memory device, read nonvolatile memory device, and memory system incorporating nonvolatile memory device


A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read data after the strobe signal is toggled a predetermined number of times.. .
Samsung Electronics Co., Ltd.


08/13/15
20150228313 

Semiconductor memory device


A semiconductor memory device includes: a burst start signal generation unit configured to generate a first burst start signal by delaying a write pulse by a first period, generate a second burst start signal by delaying the write pulse by a second period, and selectively transmit the first or second burst start signal as a select burst start signal in response to a test signal; an input control signal generation unit configured to generate an input control signal in response to the first burst start signal; and a write command generation unit configured to generate a write driver enable signal in response to the select burst start signal.. .
Sk Hynix Inc.


08/13/15
20150228311 

Semiconductor memory apparatus, and reference voltage control circuit and internal voltage generation circuit therefor


An internal voltage control circuit according to an embodiment may include a source power supply selection unit configured to receive a first internal power supply voltage and a second internal power supply voltage and selecting the first internal power supply voltage and the second internal power supply voltage as a source voltage in response to a test mode enable signal, a first reference voltage generation unit configured to receive the source voltage from the source power supply selection unit, and configured to generate a to first low reference voltage and a first high reference voltage. The reference voltage control circuit may also include a second reference voltage generation unit configured to receive the first internal power supply voltage and configured to generate a second low reference voltage and a second high reference voltage..
Sk Hynix Inc.


08/13/15
20150227417 

Semiconductor memory apparatus and operating method thereof


A semiconductor memory apparatus may include an error check and correction circuit block configured to receive a plurality of cell data, and output error-checked data and error data discrimination signals after receiving an error check enable signal; and a data bus inversion circuit block configured to receive the plurality of cell data, and output the plurality of cell data by inverting or non-inverting the cell data after receiving a read data bus inversion enable signal, the error check enable signal and the error data discrimination signals.. .
Sk Hynix Inc.


08/06/15
20150221360 

Semiconductor memory device


A semiconductor memory device includes a memory cell array configured to include a plurality of word lines, a dock enable buffer configured to receive a clock enable signal, a plurality of command buffers configured to receive a plurality of commands, a refresh control unit configured to sequentially activate the plurality of word lines in a self-refresh mode, a command decoder configured to decode the clock enable signal and the plurality of commands, and to allow the refresh control unit to enter the self-refresh mode or exit from the self-refresh mode, and a buffer control unit configured to disable the plurality of command buffers when the clock enable signal is deactivated, and to enable the plurality of command buffers when the refresh control unit exits from the self-refresh mode.. .
Sk Hynix Inc.


08/06/15
20150221256 

Display device that switches light emission states multiple times during one field period


A scan driving circuit includes a shift register unit and a logic circuit unit. The start of a start pulse of an output signal stp+1 of a p+1′th shift register is situated between the start and end of a start pulse of the output signal stp of a p′th shift register, and one each of a first enable signal through a q′th enable signal exist in sequence between the start of the start pulse of the output signal stp and the start of the start pulse of the output signal stp+1.
Sony Corporation


08/06/15
20150220672 

Method and modelling power consumption of integrated circuit


A method of modeling power consumption of an integrated circuit and an apparatus for supporting the same are provided. The method of modeling power consumption of an integrated circuit includes: grasping information about a clock gating enable signal of the integrated circuit; determining a modeling level using a change rate of the number of the clock enable signal; and extracting a power state according to the modeling level and the number of the clock gating enable signal and modeling power consumption in the power state.
Samsung Electronics Co., Ltd. A Corporation


07/23/15
20150207462 

Wide common mode range sense amplifier


A device for comparing voltage levels of a pair of input signals is presented. The device may include a pre-amp circuit and a differential amplifier.
Apple Inc.


07/23/15
20150207413 

Hybrid power supply architecture


A hybrid power supply architecture including a microcontroller, a linear regulator, a first current sensing unit, a second current sensing unit, a switching regulator, a pwm controller and a hybrid output stage is disclosed. The linear and switching regulators respectively perform linear and switching regulation according to a first enable signal and a second enable signal generated by the microcontroller to generate a linear output power and a switching output power.
Celestica Technology Consultancy (shanghai) Co., Ltd.


07/23/15
20150206578 

Area-efficient, high-speed, dynamic-circuit-based sensing scheme for dual-rail sram memories


In one embodiment, a self-timed, dual-rail sram includes a self-timing circuit having a logic gate that is powered by voltage vdd and configured to receive a fire-sense-amplifier timing signal and to produce a vdd-domain sense-amplifier-enable signal soelv. The self-timing circuit includes an inverting level-shifter having complementary n-type and p-type transistors connected in series between voltage vdda and ground.
Lsi Corporation


07/23/15
20150206556 

Sense amplifiers and memory devices having the same


In a sense amplifier, a switching transistor is configured to apply a ground voltage to a ground node in response to a sense enable signal. A first detection circuit is configured to output a first detection signal to the first detection node based on a mode signal and a voltage of a bit-line.
Samsung Electronics Co., Ltd.


07/23/15
20150206502 

Display device and driving the same


A display device includes a display panel including data lines and scan lines coupled, a data driver configured to supply data voltages to the data lines based on digital video data, a scan driver configured to supply scan signals to the scan lines, a timing controller configured to select one of a normal mode and a self-refresh mode based on a panel self-refresh enable signal, where the data and scan drivers are driven by a first frame frequency in the normal mode and by a second frame frequency lower than the first frame frequency in the self-refresh mode, and a power supply source configured to supply driving voltages to the data and scan drivers and the timing controller and to transmits a direct current power voltage to an outside thereof, where a transmission of the direct current power voltage is blocked during a blank period in the self-refresh mode.. .
Samsung Display Co., Ltd.


07/23/15
20150206499 

Display device and driving method thereof


A display device includes: a plurality of pixels; a scan driver configured to apply a scan signal to a plurality of scan lines connected to the plurality of pixels; a data driver configured to apply a gray voltage to a plurality of data lines connected to the plurality of pixels; a signal controller configured to transmit a scan control signal for controlling operating of the scan driver to the scan driver, and configured to transmit a data control signal for controlling operating of the data driver to the data driver; a power supply configured to supply a power voltage for generation of the scan signal to the scan driver; and a short detector configured to detect a voltage level of the power voltage and generate an enable signal in response to the detection.. .
Samsung Display Co., Ltd.


07/23/15
20150206492 

Display device and driving method thereof


A display device including pixels; a data driver configured to apply a data signal to data lines connected to the pixels; and a signal controller configured to receive an image signal, a data enable signal, and a main clock signal, and to transmit an image data signal and an output signal that instructs transmitting of the data signal to the data driver. The signal controller is configured to detect electrostatic discharge (esd) noise using the main clock signal and to mask the output signal when the image signal is distorted as a result of the esd noise..
Samsung Display Co., Ltd


07/23/15
20150205338 

Power management system comprising static protecting circuit and related operation


A power management system comprises a power converter comprising a power stage and configured to detect an abnormal static state of the power stage, to generate a protection signal in response to the detection of the abnormal static state of the power stage, and to stabilize a direct current (dc) power supply voltage in response to an enable signal to generate a dc output voltage, and a main control circuit configured to generate the enable signal for the power converter based on the protection signal received from the power converter.. .
Samsung Electronics Co., Ltd.


07/16/15
20150200669 

Clock gating circuit for reducing dynamic power


A clock-gating circuit is disclosed that may reduce unnecessary power consumption associated with clock distribution networks. For some embodiments, the clock-gating circuit includes a latch control circuit, a storage latch, and a logic gate.
Qualcomm Incorporated


07/09/15
20150195013 

Wireless power receiver and host control interface thereof


A wireless power receiver, configured to receive power from a wireless power outlet and to communicate with a host for providing electrical power thereto, is provided comprising a secondary inductive coil configured to receive power from a primary coil of the wireless power outlet, and a host control interface configured to facilitate communication between the wireless power receiver and the host. The host control interface comprises contacts, one or more information-carrying contacts configured to conduct at least one of a clock and a data signal between the wireless power receiver and the host, supply input and power supply ground contacts configured to cooperate to provide current between the wireless power receiver and the host, an interrupt-signal contact configured to carry an interrupt signal from the wireless power receiver and the host, and an enable-signal contact configured to carry an enable signal from the host to the wireless power receiver..
Powermat Technologies Ltd.


07/09/15
20150194876 

Wirelessly activated power supply for an electronic device


A power supply includes a power supply circuit and a power-on circuit controlling transitioning of the power supply circuit to a turned-on state. The power-on circuit includes a code driver, a controller coupled to the power supply circuit and code driver, and a transducer to detect a wireless control signal and generate an enable signal based thereupon.
Stmicroelectronics S.r.l.


07/09/15
20150194110 

Liquid crystal display and driving the same


A liquid crystal display includes: a display panel including data lines, scan lines and a plurality of pixels connected to the data lines and the scan lines; a scan driver configured to supply scan signals to the scan lines; a data driver configured to supply data voltages to the data lines; and a timing controller configured to control operation timings of the scan driver and the data driver, where the timing controller is configured to output a plurality of scan output enable signals to the scan driver, and the scan driver is configured to supply odd scan signals to odd scan lines based on a first scan output enable signal of the scan output enable signals and to supply even scan signals to even scan lines based on a second scan output enable signal of the scan output enable signals.. .
Samsung Display Co., Ltd.


07/09/15
20150193564 

System and using clock chain signals of an on-chip clock controller to control cross-domain paths


An on-chip clock controller configured to control cross-domain paths using clock chain signals is disclosed. The on-chip clock controller includes a clock bits module configured to receive a clock chain signal and to output an enable signal based upon the clock chain signal.
Lsi Corporation


07/02/15
20150189716 

Led backlight driving circuit and liquid crystal device


A led backlight driving circuit is disclosed. The led backlight driving circuit includes a boost circuit for converting an input voltage to an output voltage for a led unit, a driving ic for controlling the boost circuit such that the boost circuit converts the input voltage to the output voltage for the led unit, a discharging module for releasing charges stored within the boost circuit after the driving circuit is turned off, and a detecting module for detecting a voltage at an output end of the boost circuit and then for generating enable signals for controlling the operations of the driving ic.
Shenzhen China Star Optoelectronics Technology Co., Ltd.


07/02/15
20150189706 

Led power supply with small dimming ratio control and control method thereof


A led driving control circuit for controlling a power switch in a led power supply includes: a feedback circuit coupled to a led load and generating a feedback signal indicative of an output voltage of the led power supply; an enabling circuit generating an enable signal according to the feedback signal, a first reference signal and a pwm dimming signal, wherein when the feedback signal is higher than the first reference signal, the enable signal synchronizes with the pwm dimming signal, and when the feedback signal is lower than the first reference signal, the duty cycle of the enable signal is higher than the duty cycle of the pwm dimming signal; and a feedback loop control circuit generating a control signal for controlling the power switch according to the feedback signal only when the enable signal is in an active state.. .
Chengdu Monolithic Power Systems Co., Ltd.




Enable Signal topics: Enable Signal, Control Unit, Electronic Device, Integrated Circuit, Semiconductor, Output Enable, Liquid Crystal, Liquid Crystal Display, Data Transfer, Buffer Circuit, Esd Protection Circuit, Protection Circuit, Electrostatic Discharge, Esd Protection, Programmable Memory

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