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This page is updated frequently with new Enable Signal-related patent applications. Subscribe to the Enable Signal RSS feed to automatically get the update: related Enable RSS feeds. RSS updates for this page: Enable Signal RSS RSS


Synchronous on-chip clock controllers

Stmicroelectronics International N.v.

Synchronous on-chip clock controllers

Date/App# patent app List of recent Enable Signal-related patents
05/21/15
20150138893
 High voltage switch, nonvolatile memory device comprising same, and related  operation patent thumbnailnew patent High voltage switch, nonvolatile memory device comprising same, and related operation
A high voltage switch operates in response to a first drive voltage and a second drive voltage higher than the first drive voltage. The high voltage switch comprises a pmos transistor transmitting the second drive voltage to an output terminal according to a voltage applied to its gate, a first depletion mode transistor providing the second drive voltage to the pmos transistor according to an output signal fed back from the output terminal, a second depletion mode transistor receiving the second drive voltage through one end and providing a switching voltage to another end according to a switching control signal, and a level shifter providing the switching voltage to a gate of the pmos transistor according to an enable signal and a reverse enable signal..
Samsung Electronics Co., Ltd.
05/21/15
20150137862
 Synchronous on-chip clock controllers patent thumbnailnew patent Synchronous on-chip clock controllers
A semiconductor chip includes on-chip clock controllers (occs) capable of synchronizing multiple clock signals on the device. Each occ controller receives a scan enable signal and a unique clock signal that is generated from one or more clock generators.
Stmicroelectronics International N.v.
05/14/15
20150131683
 Receiver with signal arrival detection capability patent thumbnailReceiver with signal arrival detection capability
A receiver includes first, second, and third signal processors and a controller. The first signal processor provides a first signal in response to detecting a first attribute of a received signal.
05/14/15
20150131364
 Negative bitline boost scheme for sram write-assist patent thumbnailNegative bitline boost scheme for sram write-assist
A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element.
05/14/15
20150130862
 Display driver, display system and microcomputer patent thumbnailDisplay driver, display system and microcomputer
Low power consumption is realized focusing on the refresh interval of a low leakage display panel. Display systems and microcomputers are described herein.
05/07/15
20150127914
 Semiconductor memory device, memory system and  operating the same patent thumbnailSemiconductor memory device, memory system and operating the same
A memory system including a plurality of memory chips is provided. The memory system includes a first memory chip and a second memory chip that share a data bus and become active by a chip enable signal, and a controller transmitting multi chip select commands to the first and second memory chips.
Sk Hynix Inc.
05/07/15
20150124546
 Voltage regulator and  controlling bias current patent thumbnailVoltage regulator and controlling bias current
A voltage regulator includes: a comparator configured to compare a feedback voltage with a reference voltage to output an enable signal and operate based on a bias current; a pass transistor turned on according to the enable signal and configured to output an external power voltage as an output voltage; a voltage distribution circuit configured to distribute and output the output voltage to an input terminal of the comparator; and a bias current control unit configured to control an amount of the bias current supplied to the comparator based on the output voltage.. .
Sk Hynix Inc.
05/07/15
20150124531
 Ias voltage generator for reference cell and bias voltage providing method therefor patent thumbnailIas voltage generator for reference cell and bias voltage providing method therefor
A bias voltage generator and generating method for a reference cell are provided. The bias voltage generator includes a data read detector, a cut-off signal generator and an output stage circuit.
Winbond Electronics Corp.
05/07/15
20150124529
 Semiconductor device,  operating the same, and semiconductor system including the same patent thumbnailSemiconductor device, operating the same, and semiconductor system including the same
A semiconductor device includes a page buffer configured to read data out of a memory cell array in response to a bias enable signal, and a control logic configured to generate the bias enable signal and a bias precharge signal that are used to control the memory cell array. The control logic activates the bias enable signal and the precharge signal before a ready/busy signal activating a read operation of the memory cell array is enabled..
Sk Hynix Inc.
04/30/15
20150121172
 Computer memory access patent thumbnailComputer memory access
A computer memory access method includes: receiving external data with a prefetching length; determining that the external data includes a masked data portion; at the time of a write enable signal being triggered, writing an unmasked data portion of the external data into a data storage unit of a computer memory by a writing unit; triggering a read enable signal at the time of the write enable signal being triggered and reading the unmasked data portion from the data storage unit by a reading unit while reading a third data portion corresponding to the masked data portion from the data storage unit; merging the unmasked data portion and the third data portion to a merged data and generating parity bits from the merged data by an error correction code encoding circuit; and writing the parity bits into a parity bit storage unit of the computer memory.. .
Xi'an Sinochip Semiconductors Co., Ltd.
04/30/15
20150121109

Voltage regulator and semiconductor memory device including the same


One example embodiment, a voltage regulator includes a regulating unit configured to generate a cell array operating voltage based on a power supply voltage and a reference voltage, a power switch control unit configured to generate a power switch control signal based on a sensing enable signal, and a power switch unit configured to compensate for a drop in the cell array operating voltage based on the power supply voltage and the power switch control signal, the cell array operating voltage dropping when the sensing enable signal is activated.. .
Samsung Electronics Co., Ltd.
04/30/15
20150117121

Semiconductor memory apparatus and data storage and power consumption


A semiconductor memory apparatus includes a write driver configured to transfer input data to a data storage region. The semiconductor memory apparatus may also include a sense amplifier configured to sense and amplify the data stored in the data storage region and output output data.
Sk Hynix Inc.
04/30/15
20150117080

Multi-chip package and memory system


A multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal, a second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal. The first memory chip and the second memory chip each include a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation..
Kabushiki Kaisha Toshiba
04/23/15
20150113236

Memory controller


A memory controller includes an digitally programmable delay unit having a selectable delay time receiving a read-enable signal and outputting a delayed read-enable signal. The delay time is selected in response to an externally applied delay-control signal.
Samsung Electronics Co., Ltd.
04/23/15
20150110057

Mobile communications terminal, and controlling radio frequency power amplifier thereof


The present invention discloses a mobile communications terminal. The mobile communications terminal includes a signal processing module and a radio frequency power amplifier, where the signal processing module outputs, to a radio frequency signal input end of the radio frequency power amplifier, a radio frequency signal corresponding to one group of data packets, and synchronously outputs an enable signal to an enable signal input end of the radio frequency power amplifier; and the signal processing module periodically stops outputting the enable signal to the enable signal input end within first predetermined duration, and outputs, to the radio frequency signal input end, a radio frequency signal corresponding to at least one piece of pilot data and synchronously outputs the enable signal to the enable signal input end within second predetermined duration..
Huawei Device Co., Ltd.
04/23/15
20150109841

Semiconductor device and operating the same


A semiconductor device comprises a memory block having a content addressable memory (cam) cell array storing data for internal operation conditions, and a memory cell array. The semiconductor device also comprises a page buffer to program data in the memory block or read the data programmed in the memory block; a control logic to activate a reset enable signal for initializing the page buffer during a reset operation and output the activated reset enable signal; and a power-supply controller to output a reset control signal for initializing the page buffer when the reset enable signal is activated, and provide a page buffer power-supply signal to the page buffer.
Sk Hynix Inc.
04/16/15
20150103757

Wireless transmission device and connecting device


An exemplary embodiment of the present disclosure illustrates a wireless transmission device. The wireless transmission device includes a processor, a remote module, and a transmission module.
Lite-on Electronics (guangzhou) Limited
04/16/15
20150102793

Synchronous rectification control method and control circuit and switching voltage regulator


In one embodiment, a synchronous rectification control method can include: (i) setting or updating a count value when a rectification switch is turned on; (ii) generating an off enable signal after a delay time corresponding to the count value has elapsed; (iii) turning off the rectification switch based on the off enable signal, and comparing a drain-source voltage of the rectification switch against a reference voltage; and (iv) generating a comparison signal for updating the count value based on the drain-source voltage and the reference voltage.. .
Silergy Semiconductor Technology (hangzhou) Ltd
04/02/15
20150095733

Method and testing surface mounted devices


An apparatus comprising a plurality of devices connected in series with one another, each of the devices comprising a test enable pin for receiving a test enable signal that indicates enablement of a test mode, and a test output pin for outputting a test output signal in the test mode, and a controller coupled to the devices and comprising an additional test output pin for outputting a test channel output signal, wherein a failure of at least one of the test output signals and the test channel output signal indicates the existence of one or more potential defects associated with the plurality of devices and the controller.. .
Conversant Intellectual Property Management Inc.
04/02/15
20150092503

Method and apparatus for memory command input and control


Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state.
Micron Technology, Inc.
04/02/15
20150092502

Circuit to generate a sense amplifier enable signal


A circuit includes a tracking bit line, a tracking unit connected to the tracking bit line and a detection unit. The tracking unit is configured to receive a first control signal and configured to selectively charge or discharge a voltage on the tracking bit line in response to the first control signal.
Taiwan Semiconductor Manufacturing Company, Ltd.
04/02/15
20150092475

Pseudo retention till access mode enabled memory


A memory configurable to be used in an rta mode includes an input latch configured to receive an input address bus and to generate a latched address bus that corresponds to a memory location. An address flop is configured to save the latched address and to generate a flopped address.
Texas Instruments Incorporated
03/26/15
20150085566

Input trigger independent low leakage memory circuit


Wordline-driver biasing and column-based source-biasing circuitry facilitate reduced current leakage, for example, in soc device sram circuits in a manner that is independent of the read/write/standby operating mode, and without an external trigger. Wordline-driver-biasing circuitry turns off (i.e., decouples from system power) wordline-drivers that are connected to unselected wordlines during read/write operations using one of a decoder-enable signal, which is generated in response to row address values, or based on the activation of a self-timing internal clock, which is generated by the memory circuit when it is activated (i.e., switched from standby to read/write mode).
Synopsys, Inc.
03/19/15
20150078765

Signal generating circuit, optical signal transmitting apparatus, signal receiving circuit, establishing optical signal synchronization, and optical signal synchronization system


To enable signal position detection, frequency offset compensation, clock offset compensation, and chromatic dispersion amount estimation in a communication system based on coherent detection using an optical signal, even on a signal having a great offset in an arrival time depending on a frequency due to chromatic dispersion. An optical signal transmitting apparatus generates specific frequency band signals having power concentrated on two or more specific frequencies and transmits a signal including the specific frequency band signals.
Nippon Telegraph And Telephone Corporation
03/19/15
20150078762

Signal generating circuit, optical signal transmitting apparatus, signal receiving circuit, establishing optical signal synchronization, and optical signal synchronization system


To enable signal position detection, frequency offset compensation, clock offset compensation, and chromatic dispersion amount estimation in a communication system based on coherent detection using an optical signal, even on a signal having a great offset in an arrival time depending on a frequency due to chromatic dispersion. An optical signal transmitting apparatus generates specific frequency band signals having power concentrated on two or more specific frequencies and transmits a signal including the specific frequency band signals.
Nippon Telegraph And Telephone Corporation
03/19/15
20150077410

Display apparatus, power supply control controlling thereof


A display apparatus is provided. The display apparatus includes an interface configured to receive a data enable signal and a data signal, a power supply configured to supply power to an internal component, and a controller configured to determine whether to supply power to the internal component based on whether the data enable signal is received from an external apparatus through the interface, and configured to control the power supply to supply the power to the internal component based on the determination..
Samsung Electronics Co., Ltd.
03/19/15
20150077187

Dynamic error vector magnitude duty cycle correction


Aspects of this disclosure relate to dynamic error vector magnitude (devm) compensation. In one embodiment, an apparatus includes an amplifier, a low pass filter, and a bias circuit.
Skyworks Solutions, Inc.
03/12/15
20150074331

Nonvolatile memory package and nonvolatile memory chip


A nonvolatile memory package of an embodiment includes: a data terminal configured to receive a write command for a data; a first ce terminal; a second ce terminal; a ce selection terminal; and a selector coupled to the first ce terminal and the second ce terminal. The selector outputs one of a first chip-enable signal and a second chip-enable signal based on a ce selection signal.
Kabushiki Kaisha Toshiba
03/12/15
20150070976

Semiconductor device


There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an sram memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation.
Renesas Electronics Corporation
03/12/15
20150070335

Pixel selection control method, driving circuit, display apparatus and electronic instrument


A pixel selection control method, driving circuit, display apparatus and electronic instrument are disclosed. A driving circuit includes a logic circuit configured to receive a reference signal associated with a line of pixels.
Sony Corporation
03/12/15
20150070334

Pixel selection control method, driving circuit, display apparatus and electronic instrument


A pixel selection control method, driving circuit, display apparatus and electronic instrument are disclosed. A driving circuit includes a logic circuit configured to receive a reference signal associated with a line of pixels.
Sony Corporation
03/12/15
20150070068

Internal voltage generator and generating internal voltage


An internal voltage generator includes an internal voltage control unit suitable for generate an enable signal based on a voltage level of an internal voltage, a clock control unit suitable for generate a control clock having a restricted toggling period based on the enable signal and a clock while controlling the toggling number of the control clock, and an internal voltage generation unit suitable for generate the internal voltage based on the control clock.. .
Sk Hynix Inc.
03/05/15
20150067423

A q-gating cell architecture to satiate the launch-off-shift (los) testing and an algorithm to identify best q-gating candidates


A method for creating an architecture to support q-gating for launch-off-shift (los) scan testing using a plurality of flip-flops is provided. The method may include applying a common clock signal to each clock input of the plurality of flip-flops and applying a gated scan enable signal to each scan enable input of the plurality of flip-flops.
International Business Machines Corporation
03/05/15
20150063051

Low power protection circuit


The present invention provides the low power protection circuit including a first voltage detector, a pulse generating circuit, a sr latch, and an output logic operation circuit. The low power protection circuit is adapted for a dynamic random access memory (dram) with dual operating voltages.
Nanya Technology Corporation
03/05/15
20150063044

Strobe signal generation device and memory apparatus using the same


A strobe signal generation device includes an enable signal generating section, a buffering section and a strobe signal driving section. The enable signal generation section generates a division enable signal in response a strobe signal.
Sk Hynix Inc.
03/05/15
20150062979

Constant voltage constant current control circuits and methods with improved load regulation


The present invention discloses cvcc circuits and methods with improved load regulation for an smps. In one embodiment, the cvcc can include: a voltage feedback circuit to generate an output voltage feedback signal; a current feedback circuit to generate an output current feedback signal; a control signal generating circuit that receives the output voltage feedback signal and the output current feedback signal, and generates a constant voltage/constant current control signal; a first enable signal generating circuit that compares a first reference voltage and the constant voltage/constant current control signal to generate a first enable signal; and a pwm controller that generates a pwm control signal based on the constant voltage/constant current control signal to control a main switch of the flyback smps..
Silergy Semiconductor Technology (hangzhou) Ltd
03/05/15
20150062212

Element substrate, printhead, and printing apparatus


An element substrate capable of suppressing occurrence of electromagnetic noise upon driving printing elements on an element substrate with long wiring lengths, preventing an operation error, and printing a high-quality image is provided. In the element substrate, plural element substrates each including printing elements are arrayed in an arrayed direction of the printing elements.
Canon Kabushiki Kaisha
03/05/15
20150061734

Interface circuit


According to one embodiment, a first pull-down transistor, a mode switching circuit, and a leak-cut circuit are provided. The first pull-down transistor pulls down an input/output terminal.
Kabushiki Kaisha Toshiba
03/05/15
20150061710

Semiconductor apparatus and test method


A test driver selection unit configured to enable a plurality of test driver selection signals in response to a test pulse and a test clock, and a plurality of drivers configured to receive the plurality of test driver selection signals, wherein each of the plurality of drivers is configured to output an output signal to a data bump in response to a test driver selection signal, data, and an output enable signal, and to receive a first driving voltage and a second driving voltage.. .
Sk Hynix Inc.
02/26/15
20150058690

Scan test circuit with scan clock


A scan test circuit includes: a pulse generator, for generating differential pulses according to a system clock signal; a functional path, including: a d-type latch clocked by the differential pulses; a test path, including: a scan latch clocked by a test clock signal; and a tri-state inverter. When a test enable signal is enabled, the generation of the differential pulses is disabled..
Mediatek Singapore Pte. Ltd.
02/26/15
20150058685

Method and system of testing semiconductor memory


A method of testing a semiconductor memory includes generating a logical value of a test pattern through an algorithm pattern generator included in a field programmable gate array. The generated logical value is programmed in a dut under the control of a dq signal responding to a dq enable signal that is generated from automatic test equipment and is then transferred to the field programmable gate array.
Samsung Electronics Co., Ltd.
02/26/15
20150055426

Novel sense amplifier scheme


A sense amplifier circuit comprising a pair of cross-coupled inverters and a data line charging circuit is disclosed. The cross-coupled inverters comprise a first inverter and a second inverter.
Taiwan Semiconductor Manufacturing Company Limited
02/26/15
20150055422

Semiconductor memory apparatus


A semiconductor memory apparatus includes a driving current control block configured to sense a resistance value of a dummy memory element, and generates a write driver control signal; and a write driving block configured to provide a driving voltage to a memory cell array in response to a write driver enable signal and the write driver control signal.. .
Sk Hynix Inc.
02/26/15
20150055415

Controller


According to one embodiment, controller includes a phase comparator that receives a data strobe signal outputted from a memory in response to a read enable signal, and a delayed data strobe signal formed by applying a delay to the data strobe signal, and outputs a result of comparison between phases of two signals. The controller also includes a duty control unit that corrects a duty of the read enable signal outputted to the memory based upon the comparison result of the phase comparator..
Kabushiki Kaisha Toshiba
02/26/15
20150055390

Content addressable memory


The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each cam cell of a cam memory array via a search line pair.
Renesas Electronics Corporation
02/26/15
20150054718

Pixel circuit and display device using the same


Exemplary embodiments of the present invention relates to a pixel circuit for displaying an image of uniform luminance. The pixel circuit comprising an organic light emitting diode (oled), an rs trigger comprising a first terminal connected to a scan line, a second terminal connected to an enable line, and a third terminal connected to a data line, the rs trigger configured to generate an output signal according to an enable signal, a data signal, and a scan signal respectively received via the enable line, the data line, and the scan line, and a driving transistor comprising a first electrode connected to a first power source, a second electrode connected to an anode of the oled, and a gate electrode connected to an output terminal of the rs trigger, the driver transistor configured to control a current flowing through the oled in response to the output signal of the rs trigger..
Samsung Display Co., Ltd.
02/19/15
20150052317

Systems, devices, memory controllers, and methods for memory initialization


Systems, devices, memory controllers, and methods for initializing memory are described. Initializing memory can include configuring memory devices in parallel.
Micron Technology, Inc.
02/19/15
20150048894

Delay line ring oscillation apparatus


The delay line degradation protection architecture as build-in ring oscillation apparatus includes a two gates logical circuit, a buffer, a clock input buffer and a delay lock loop circuit. The two gates logical circuit receives a clock enable signal, specific mode signal, and delayed clock output signal.
Nanya Technology Corporation
02/19/15
20150048876

Semiconductor circuit


Provided is a semiconductor circuit. The semiconductor circuit includes: an input node configured to receive an enable signal, a sense enable signal, and a clock signal; and a clock gating circuit configured to output an enable clock signal corresponding to the clock signal while a signal level of the enable signal is at a first level regardless of a signal level of the sense enable signal, when the semiconductor circuit is in a high-voltage mode, and output an enable clock signal corresponding to the clock signal while a signal level of at least one of the enable signal and the sense enable signal is at the first level, when the semiconductor circuit is in a low-voltage mode..
Samsung Electronics Co., Ltd.
02/12/15
20150043616

Circuits and methods for pulse radio receivers


Circuits and methods comprising: a radio frequency amplifier that powers off in response to an enable signal; a demodulator that outputs an rz signal; an all-digital clock and data recovery circuit comprising: a phase detector that includes a tri-state phase frequency detector for use when in an acquisition mode and a hogge phase detector for use when in a communication mode, that receives the rz signal, and that outputs a phase detector output from the tri-state phase frequency detector when in the acquisition mode and from the hogge phase detector when in the communication mode, a loop filter that receives the phase detector output from the phase detector and produces a loop filter output that is the sum of a proportional path of the loop filter and an integral path of the loop filter, and a numerical controlled oscillator that receives the loop filter output and produces the enable signal.. .
02/12/15
20150043289

Semiconductor memory device


A semiconductor memory device includes a pad configured to receive a first write data from outside of the semiconductor memory device, and a write circuit configured to generate a plurality of second write data which are to be written in memory cells of all banks to be tested in response to a test mode signal, data strobe signals, a write enable signal, and the first write data transferred through the pad.. .
Sk Hynix Inc.
02/12/15
20150043285

Interfaces and die packages, and appartuses including the same


A memory device includes a memory die package including a plurality of memory dies, an interface device including an interface circuit, and a memory controller configured to control the interface with control data received from at least one of the plurality of memory dies. The interface device of the memory device is configured to divide and multiplex an io channel between the memory die package and the memory controller into more than one channel using the control data receive from the at least one of the plurality of memory dies.
Micron Technology, Inc.
02/12/15
20150042388

Semiconductor memory apparatus


A semiconductor memory apparatus includes an enable signal generation unit configured to be inputted with a plurality of clocks which have different phases, and generate a plurality of enable signals; and a plurality of sampling units configured to output input data as sampling data in response to respective pairs of clocks of the plurality of clocks and respective ones of the plurality of enable signals.. .
Sk Hynix Inc.
02/05/15
20150039956

Test mux flip-flop cell for reduced scan shift and functional switching power consumption


A new flip-flop cell that is more efficient in scan chain configuration includes a multiplexer, storage element (e.g., a flip-flop), an inverter, and multiple logic gates. The flip-flop cell is configured to receive both a test signal and a data input signal and select one of the two to pass to the storage element based on a scan enable signal that indicates either a capture mode or a scan shift mode.
Stmicroelectronics Asia Pacific Pte. Ltd.
02/05/15
20150036783

Device and generating input control signals of a serialized compressed scan circuit


A device and a method for generating input control signals of a serialized compressed scan circuit are provided. A control signal generating device receives a test clock signal from a clock input port and a state enable signal from a state enable bus, and correspondingly generates a shift enable signal, a capture enable signal and a strobe signal.
Industrial Technology Research Institute
01/29/15
20150033360

Method and securing configuration scan chains of a programmable device


Scan chain circuitry on an integrated circuit device includes a plurality of memory elements, and a plurality of control elements. Each of the control elements is located between respective ones of the plurality of memory elements for controllably connecting the plurality of memory elements into a scan chain.
Altera Corporation
01/29/15
20150029372

Image sensor and controlling the same


Provided is an image sensor including a sensor array including a plurality of pixels arranged in rows and columns. The image sensor may include a ramp signal generator which may generate a ramp signal.
Samsung Electronics Co., Ltd.
01/29/15
20150028190

Counter circuit, analog-to-digital converter, and image sensor including the same and correlated double sampling


A counter circuit includes a first counter and a second counter. The first counter is configured to count a first counter clock signal which toggles with a first frequency to generate upper (n−m)-bit signals of n-bit counter output signals, in response to a first counting enable signal based on a first comparison signal during a coarse counting interval.
01/22/15
20150023144

Method and system for measuring noise of a magnetic head


A method for measuring noise of a magnetic head includes setting a plurality of threshold values, applying bias current or voltage to a read element of the magnetic head, applying an external transverse magnetic field to the magnetic head, amplifying output signal from the read element to produce an amplified signal, filtering the amplified signal to produce a filtered signal, generating an enable signal for each threshold value in a predetermined time window by a counting control means with input signals which include the filtered signal and the threshold value, measuring the cumulative time duration of each enable signal, making an amplitude-duration distribution according to the cumulative time durations and the threshold values, calculating a plurality of parameters according to the amplitude-duration distribution and analyzing the parameters with a plurality of predetermined criteria to determine the defects of the magnetic head. Accordingly, the invention also discloses a system for measuring noise of a magnetic head..
Sae Magnetics (h.k.) Ltd.
01/22/15
20150022428

Shift register circuit


A shift register circuit for driving an oled display panel is provided. The shift register circuit includes a plurality of circuit stages connected in series.
Au Optronics Corp.
01/22/15
20150022235

Semiconductor device


The disclosed invention provides a semiconductor device capable of suitably controlling the level of an enable signal to resolve nbti in a pmos transistor. An input node receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby.
Renesas Electronics Corporation
01/15/15
20150019607

Interpolation filter based on time assignment algorithm


Disclosed is an interpolation filter based on time assignment algorithm. An interpolation filter comprises an enable signal generating part generating enable signals for operation of the interpolation filter, an input value generating part generating input values, a first calculating part generating a first output value based on a first enable signal and a first input value, a second calculating part generating a second output value based on a second enable signal and a second input value, and an output value selecting part selecting a final output value among the first output value and the second output value.
Electronics And Telecommunications Research Institute
01/15/15
20150016196

Data input circuit


A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal clock during a burst period from substantially a time when the pulse of the shifting signal is generated.
Sk Hynix Inc.
01/15/15
20150015566

Driving apparatus of display


A driving apparatus of a display is disclosed. The driving apparatus includes a digital-to-analog converter (dac) circuit, an output buffer circuit and a pre-charge circuit.
Novatek Microelectronics Corp.
01/15/15
20150015310

Clock delay detecting circuit and semiconductor apparatus using the same


Provided is a clock delay detecting circuit and semiconductor apparatus using the same that is capable of generating a period signal whose period is a delay time of a clock, dividing the period signal, and counting the divided period signal. The clock delay detection circuit comprises a period signal generating unit configured to generate a counting control signal, a period signal dividing unit configured to generate a counting enable signal by dividing the counting control signal, and a counting unit configured to generate a delay information signal by counting the counting enable signal with a clock, wherein the counting control signal has a period with a predetermined time..
Sk Hynix Inc.


Popular terms: [SEARCH]

Enable Signal topics: Enable Signal, Control Unit, Electronic Device, Integrated Circuit, Semiconductor, Output Enable, Liquid Crystal, Liquid Crystal Display, Data Transfer, Buffer Circuit, Esd Protection Circuit, Protection Circuit, Electrostatic Discharge, Esd Protection, Programmable Memory

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