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This page is updated frequently with new Enable Signal-related patent applications.




Date/App# patent app List of recent Enable Signal-related patents
04/07/16
20160099743 
 Apparatus and methods for biasing radio frequency switches patent thumbnailApparatus and methods for biasing radio frequency switches
Apparatus and methods for radio frequency (rf) switches are provided herein. In certain implementations, an rf switching circuit includes an adaptive switch bias circuit that controls gate and/or channel voltages of one or more field effect transistor (fet) switches.
Analog Devices Global


03/31/16
20160094207 
 Voltage generator with charge pump and related methods and apparatus patent thumbnailVoltage generator with charge pump and related methods and apparatus
Aspects of this disclosure relate to voltage generators, such as negative voltage generators. In an embodiment, an apparatus includes a voltage generator, a level shifter, and a semiconductor-on-insulator radio frequency (rf) switch configured to receive a signal from the level shifter.
Skyworks Solutions, Inc.


03/31/16
20160093237 
 Source driver and operating method thereof patent thumbnailSource driver and operating method thereof
A source driver circuit is provided which includes a plurality of digital multi-spread (hereinafter referred to as “dms”) blocks configured to generate dms signals for controlling an output timing of a data signal to be transmitted to a display panel from a plurality of clocks which are delayed as much as a reference period one another. Each dms block includes a plurality of sub blocks.
Samsung Electronics Co., Ltd.


03/31/16
20160091911 
 Semiconductor apparatus patent thumbnailSemiconductor apparatus
A semiconductor apparatus includes a control block that generates a first control signal, a second control signal, and a heating enable signal in response to an enable signal and a heating control signal, a temperature measurement block that generates a temperature code corresponding to temperature in response to the first and second control signals, a heater that generates heat while the heating enable signal is being enabled, a code latch block that stores the temperature code in response to the first and second control signals, and outputs a first code and a second code, a control code generation circuit that generates a signal by performing an operation on the first and second codes, and generates a control code by comparing the signal with a preset code, and a reference voltage generation circuit configured to change a voltage level of a reference voltage in response to the control code.. .
Sk Hynix Inc.


03/31/16
20160091563 
 Scan flip-flop patent thumbnailScan flip-flop
A pull cell scan flip-flop includes a scan flip-flop and a pull cell. The pull cell is configured to receive a scan flip-flop output signal from the scan flip-flop, the scan flip-flop output signal having a scan flip-flop output value.
Taiwan Semiconductor Manufacturing Company Limited


03/24/16
20160087539 
 Switched mode power converter controller with ramp time modulation patent thumbnailSwitched mode power converter controller with ramp time modulation
A controller for use in a power converter includes a drive circuit coupled to generate a drive signal to control switching of a power switch to control a transfer of energy from a power converter input to a power converter output. An input for receiving an enable signal including enable events is responsive to the power converter output.
Power Integrations, Inc.


03/17/16
20160079857 
 Boost converter and related integrated circuit patent thumbnailBoost converter and related integrated circuit
A boost converter receives an input voltage and provides an output voltage and includes a power switch and a voltage control circuit configured to drive the power switch as a function of the output voltage. A voltage sensing circuit in the form of a voltage divider is coupled to sense the output voltage and provide a feedback voltage.
Stmicroelectronics S.r.l.


03/17/16
20160078839 
 Image sticking elimination circuit and display device patent thumbnailImage sticking elimination circuit and display device
An image sticking elimination circuit comprises signal module (11), switch control module (12) and switch module (13), the signal module (11) has input terminal connected to an enable signal and outputs first control signal according to the enable signal; the switch control module (12) receives the first control signal outputted from the signal module and outputs second control signal; the switch module (13) receives the second control signal outputted from the switch control module (12), and controls the connection or the disconnection between a first electrode (b) and a second electrode (c). By controlling the connection or disconnection of the circuits between the first electrode (b) and the second electrode (c) with the signal module (11), the switch control module (12) and the switch module (13), the charges at the two electrodes are neutralized rapidly by shorting out the first electrode (b) and the second electrode (c) when the display signal is off and the potentials at the two electrodes are equal to eliminate the phenomena of image sticking..
Boe Technology Group Co., Ltd.


03/17/16
20160078818 
 Voltage providing circuit and display device including the same patent thumbnailVoltage providing circuit and display device including the same
A display device includes a data driver configured to generate a data signal based on a data voltage; a display panel configured to be driven based on a first power supply voltage and the data signal; a timing controller configured to control operations of the data driver and the display panel and configured to generate a ready signal indicating a power supply timing; a first voltage regulator configured to generate the first power supply voltage based on a first input voltage and a first enable signal; a second voltage regulator configured to generate the data voltage based on the first input voltage and a second enable signal; and a power sequence controller configured to generate the first enable signal based on the ready signal and the data voltage and configured to generate the second enable signal based on the ready signal and the first power supply voltage.. .
Samsung Display Co., Ltd.


03/10/16
20160072492 
 Delay circuits and related systems and methods patent thumbnailDelay circuits and related systems and methods
Delay circuits, and related systems and methods are disclosed. In one aspect, a delay circuit is provided that uses logic to delay accurately an output enable signal to reduce or avoid data hazards within a slave device.
Qualcomm Incorporated


03/10/16
20160072479 

Semiconductor apparatus


A semiconductor apparatus includes a command decoding unit configured to decode an internal command, an internal clock and an internal clock enable signal, and generate an internal control signal; a clock enable signal control unit configured to receive a pre-clock enable signal and output one of the pre-clock enable signal and an enabled internal clock enable signal as the internal clock enable signal in response to a first test signal; an enable signal selection unit configured to output one of the pre-clock enable signal and a second to test signal as a counting enable signal in response to the first test signal; and a counting unit configured to perform a counting operation during an enable period of the counting enable signal, and output a counting code.. .
Sk Hynix Inc.


03/10/16
20160071615 

Semiconductor memory apparatus


A semiconductor memory apparatus includes an internal data generation block configured to generate test data in response to test signals, and output ones of normal data inputted from data input/output pads and the test data as internal data according to a test flag signal; a data storage region configured to receive and store the internal data, and output stored data as cell storage data; a latch block configured to receive and store the cell storage data in response to a data output enable signal, and output stored data as latch data; and a data comparison block configured to compare the test data and the latch data, and generate a test result signal.. .
Sk Hynix Inc.


03/10/16
20160071574 

Method and circuits for low latency initialization of static random access memory


A method and various circuit embodiments for low latency initialization of an sram are disclosed. In one embodiment, an ic includes an sram coupled to at least one functional circuit block.
Apple Inc.


03/10/16
20160070289 

Voltage generating circuit


A voltage generating circuit includes a voltage control circuit that includes an output section and a reference voltage terminal to which a reference voltage is supplied, and outputs a voltage to the output section which is controlled so as to be equal to a voltage of the reference voltage terminal, a first voltage dividing mos transistor having a first end connected to the output section, and a second voltage dividing mos transistor having a first end connected to a second end of the first voltage dividing mos transistor. The voltage generating circuit further includes an auxiliary circuit having a set terminal to which an enable signal is supplied.
Kabushiki Kaisha Toshiba


03/10/16
20160069959 

Semiconductor apparatus and test device therefor


A semiconductor apparatus includes a clock enable signal buffer unit configured to receive an input clock enable signal, and generate an output clock enable signal; a buffer control unit configured to generate a buffer enable signal in response to the output clock enable signal and a test enable signal; an input/output buffer unit configured to receive input patterns and generate output patterns; and a compression test unit configured to test the output patterns and the output clock enable signal according to the test enable signal.. .
Sk Hynix Inc.


03/03/16
20160064101 

Semiconductor device and semiconductor system including the same


A semiconductor system may include a first semiconductor device including a first pad group. The semiconductor system may include a second semiconductor device including a second pad group which is configured for input and output of signals from and to a third semiconductor device.
Sk Hynix Inc.


03/03/16
20160064048 

Asynchronous/synchronous interface


The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact.
Micron Technology, Inc.


03/03/16
20160062430 

Mitigation of power supply disturbance for wired-line transmitters


A wired-line transmitter may include architecture that provides control of the current profile during power-up and/or power-down of the transmitter. The current profile may include a sloped ramp up during power-up and/or a sloped ramp down during power-down.
Apple Inc.


02/25/16
20160056987 

Multi iq-path synchronization


Aspects of a wireless apparatus and a method for handling a modulated signal include a frequency generator that produces a clock signal, a first synchronization circuit that generates a first sync enable signal based on an even edge of the clock signal, a second synchronization circuit that generates a second sync enable signal based on an even edge of the clock signal, a first divider having a first initial operating condition that generates a first iq path based on the first sync enable signal, and a second divider having a second initial operating condition that generates a second iq path based on the second sync enable signal, wherein the first and second operating conditions are not equal when initially powered.. .
Qualcomm Incorporated


02/25/16
20160055899 

Fast exit from dram self-refresh


Embodiments of the invention describe a dynamic random access memory (dram) device that may abort a self-refresh mode to improve the exit time from a dram low power state of self-refresh. During execution of a self-refresh mode, the dram device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the dram device.
Intel Corporation


02/18/16
20160050403 

Image processing device and image processing method


An image processing device includes a plurality of mixer units, a plurality of scale processing units, and an enable signal processing unit. A mixer unit of the plurality of the plurality of mixer units selects one of an output of another mixer unit of the plurality of mixer units, and an output image of a scale processing unit of the plurality of scale processing units to generate a composite image..
Renesas Electronics Corporation


02/18/16
20160049930 

Integrated clock gater (icg) using clock cascode complimentary switch logic


Inventive aspects include an integrated clock gater (icg) circuit having clocked complimentary voltage switched logic (cicg) that delivers high performance while maintaining low power consumption characteristics. The cicg circuit provides a small enable setup time and a small clock-to-enabled-clock delay.

02/18/16
20160048182 

Micro-controller reset system and reset method thereof


A reset system comprises an enable circuit, a buck converter and a reset circuit. The enable circuit is connected to a system power source.
Inventec Corporation


02/18/16
20160047853 

Test system that performs simultaneous tests of multiple test units


A test system includes row decoder, column decoder, row test controller, and test circuit. The row decoder activates one of first through m-th row signals based on plurality of row input signals.
Samsung Electronics Co., Ltd.


02/11/16
20160043725 

Double data rate counter, and analog-to-digital converter and cmos image sensor using the same


A double data rate (ddr) counter includes an input clock control portion suitable for generating a first clock corresponding to a state of a input clock based on a counter enable signal, and an lsb control portion suitable for holding a least significant bit based on the counter enable signal and successively performing a counting operation on the first clock in multiple sections.. .
Sk Hynix Inc.


02/11/16
20160043723 

Semiconductor apparatus


A semiconductor apparatus may include an operation signal input selection block configured to output one of either a first operation signal or a second operation signal, as a select signal, in response to an operation select signal. The semiconductor apparatus may include a target code selection block configured to output one of either a first target code or a second target code, as a select code, in response to the operation select signal.
Sk Hynix Inc.


02/11/16
20160043710 

Apparatus and methods for controlling radio frequency switches


Apparatus and methods for controlling radio frequency (rf) switches are disclosed. Provided herein are apparatus and methods for controlling rf switches.
Skyworks Solutions, Inc.


02/11/16
20160042775 

Semiconductor memory device for conducting monitoring operation to verify read and write operations


A semiconductor memory device includes, in part, a first data i/o block and a second data i/o block. During a write operation, the first data i/o block transmits input data supplied through a first pad to a first global i/o line, and further generates a write internal signal.
Sk Hynix Inc.


02/11/16
20160042774 

Semiconductor memory device for conducting monitoring operation to verify read and write operations


A semiconductor memory device includes, in part, a first data i/o block and a second data i/o block. During a write operation, the first data i/o block transmits input data supplied through a first pad to a first global i/o line, and further generates a write internal signal.
Sk Hynix Inc.


02/04/16
20160036448 

Electronic device and electronic system including the same


An electronic device includes a control logic portion suitable for generating a hold control signal based on a count enable signal, and a counting portion suitable for performing a counting operation while a latch operation stops during a counting section and performing the latch operation while the counting operation stops during a holding section based on the hold control signal and a counting clock signal.. .
Sk Hynix Inc.


02/04/16
20160036434 

Semiconductor integrated circuit device


A semiconductor integrated circuit device includes a power domain area on a semiconductor substrate, that includes a circuit block for executing a predetermined function, a first power source line that receives an external power source voltage, a second power source line that is connected to the circuit block, a first power switch circuit in a peripheral area of the power domain area, that connects the first power source line and the second power source line in response to a first enable signal, and a second power switch circuit in the power domain area, that connects the first power source line and the second power source line in response to a second enable signal.. .
Kabushiki Kaisha Toshiba


02/04/16
20160036428 

Fine-grained power gating in fpga interconnects


Systems and methods for power gating in logic and/or computing circuitry in accordance with embodiments of the inventions are disclosed. In one embodiment, a multiplexer for fine-grain power gating includes a first supply voltage and a second supply voltage, a plurality of inputs, a plurality of selection inputs, a selection circuitry configured to select one of the plurality of inputs, where one of the plurality of inputs is the first supply voltage and one of the selection inputs is a power gating enable input, an output inverter stage including a pmos transistor and an nmos transistor, where at least one input to the inverter stage is provided to the gates of the pmos and nmos transistors and selection of the power gating enable signal applies the first supply voltage to the gate of the pmos transistor and places the pmos transistor in a cutoff mode of operation..
The Regents Of The University Of California


02/04/16
20160035399 

Method and asynchronous fifo circuit


The disclosure provides an asynchronous fifo circuit that includes a data memory which is coupled to a write data path and a read data path. The data memory receives a write clock and a read clock.
Texas Instruments Incorporated


01/21/16
20160020776 

Phase-locked loop (pll)


A phase-locked loop (pll) is provided. The pll comprises a dithering circuit that is configured to receive a second tuning signal, and dither the second tuning signal to generate a dither signal to decrease a magnitude of a spur of the pll.
Taiwan Semiconductor Manufacturing Company Limited


01/21/16
20160020687 

Power module


A power module including: a power conversion unit including n switching-element pairs; and a control circuit. The control circuit receives n command signals, which correspond respectively to the n switching-element pairs, and a shared enable signal.
Mitsubishi Electric Corporation


01/21/16
20160019848 

Timing controller and display device


When applying exogenous noise with a synchronizing signal or a transmission clock period, influence by the applied noise is inhibited from appearing on a liquid crystal display, without increasing circuit size. There are included: a timing controller generating a control signal of a scanning line driving gate driver and a control signal of a signal line driving source driver based on an input signal to be a reference inputted from the outside; an enable signal generation unit including a noise detecting circuit for detecting various items of noise entering the input signal and outputs an enable signal for turning off or on the output of a gate driver control signal for a predetermined period based on output from the noise detecting circuit; and an image data output control circuit when detecting noise synchronized in a vertical period.
Nlt Technologies, Ltd.


01/07/16
20160006421 

Frequency synthesiser circuit


The invention relates to frequency synthesiser circuits, and in particular to frequency synthesiser circuits characterised by a small channel spacing. Embodiments disclosed include a frequency synthesiser circuit (100) for a radio receiver, the circuit comprising: a digitally controlled oscillator (118) configured to generate an output signal (128) with an output frequency on application of an oscillator enable signal (126); a delay module (160; 210) configured to delay an input reference signal (142) to generate a delayed reference signal (144; 244); and a duty cycle module (150) configured to modulate the oscillator enable signal based on a period of an input reference signal (142) and the delay of the delayed reference signal (144), such that a ratio between the output frequency and the frequency of the input reference signal (142) is a non-integer..
Nxp B.v.


01/07/16
20160006348 

Charge pump apparatus


The invention provides a charge pump apparatus including a clock signal generator, a clock freezing circuit, a charge pump circuit, and a feedback circuit. The clock signal generator generates a clock signal.
Ememory Technology Inc.


01/07/16
20160005465 

Content addressable memory


The present invention provides a content addressable memory capable of higher frequency operation than conventional. When a search enable signal supplied from a search control circuit is asserted, each of search line drivers transfers search data to each cam cell of a cam memory array via a search line pair.
Renessas Electronics Corporation


01/07/16
20160005446 

Memory controller for strobe-based memory systems


An integrated circuit (ic) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal.
Rambus Inc.


01/07/16
20160003461 

Luminare having multiple sensors and independently-controllable light sources


A lighting device includes a first light source having a first light source switch and a first light element array, and a second light source having a second light source switch and a second light element array. The lighting device also includes a light sensor and a motion sensor.
International Development Llc


12/31/15
20150382418 

High-precision led control circuit, method and led driver thereof


In one embodiment, a light-emitting diode (led) driver can include: (i) a reference voltage control circuit configured to provide a reference voltage signal in response to an enable signal; (ii) a current control circuit configured to control an output current of the led driver in response to the reference voltage signal; and (iii) the led driver being configured to drive an led load when the enable signal is active.. .
Silergy Semiconductor Technology (hangzhou) Ltd


12/31/15
20150381197 

Driving voltage generator and digital to analog converter


A digital to analog converter is disclosed. The invention provides a digital to analog converter (dac) including a plurality of voltage transmitting switches and a selecting signal decoder.
Novatek Microelectronics Corp.


12/31/15
20150381158 

Device and clock signal loss detection


A device, comprises a first counter and a second counter, a control unit and a comparing unit. The first counter and the second counter are configured to alternately count a cycle number of a monitoring clock signal.
Montage Technology (shanghai) Co., Ltd.


12/31/15
20150380090 

Nonvolatile memories having data input/output switches and data storage devices and methods using the same


A nonvolatile memory includes a memory cell array including a plurality of memory cells, a pad configured to be connected to a data input/output line, and an input/output circuit configured to receive data to be programmed in the memory cell array and to transmit data read from the memory cell array. The nonvolatile memory further includes a switch configured to couple and decouple the pad and the input/output circuit responsive to a switch control signal and a control circuit configured to generate the switch control signal responsive to a chip enable signal.
Samsung Electronics Co., Ltd.


12/31/15
20150380068 

Semiconductor memory device and operating the same


A semiconductor memory device includes: an enable signal generation portion suitable for generating a data output enable signal activated at a predetermined first moment corresponding to column address strobe (cas) latency based on a read command, a strobe signal generation portion suitable for generating a data strobe signal which has a preamble section until the data output enable signal is activated from a predetermined second moment ahead of the first moment based on the read command and toggles based on a source clock during an activated section of the data output enable signal, and a data output portion suitable for outputting internal data in synchronization with the data strobe signal during the activated section of the data output enable signal.. .
Sk Hynix Inc.


12/31/15
20150380067 

Memory controller


A system provides synchronous read data sampling between a memory and a memory controller, which includes an asynchronous fifo buffer and which outputs a clock and other control signals. An outbound control signal (e.g., read_enable) is used to time-stamp the beginning of a read access using a clock edge counter.
Freescale Semiconductor, Inc.


12/31/15
20150378427 

Apparatuses and methods of entering unselected memories into a different power mode during multi-memory operation


Disclosed are examples of apparatuses including memory devices and systems comprising memories sharing a common enable signal, wherein the memories may be put into different power modes. Example methods for setting the different power modes of the memories are disclosed.
Micron Technology, Inc.


12/31/15
20150378323 

Intelligent switching


An intelligent switching method and system. The method includes retrieving by a computer processor of an intelligent switching device, detection data indicating that an individual is located within a specified proximity of an apparatus.
International Business Machines Corporation


12/31/15
20150377966 

Monitoring circuit of semiconductor device


The monitoring circuit of a semiconductor device includes: a boot-up controller configured to generate a boot-up enable signal in response to a power-up signal and a boot-up command signal; a read-period generator configured to output a read-period signal in response to a boot-up read signal; and a monitoring unit configured to output the read-period signal to an external output terminal during activation of the boot-up enable signal to allow the read-period signal to be monitored.. .
Sk Hynix Inc.


12/31/15
20150374040 

Electronic cigarette


An electronic cigarette includes a control chip, the control chip includes: a driving module configured to output a current to drive the electronic cigarette to work; an open-circuit detecting module electrically connected to the driving module, and configured to sample and detect the current, and send out an open-circuit enable signal when a sampled current is less than a internal reference current; a short-circuit detecting module electrically connected to the driving module, and configured to sample and detect the current, and send out a short-circuit enable signal when the sampled current is greater than the internal reference current; and a control module electrically connected to the driving module, and configured to receive the open-circuit enable signal and the short-circuit enable signal, and send a shutdown signal to the driving module.. .
Shenzhen Smoore Technology Limited


12/24/15
20150372932 

Method and checking data frame length


A method and apparatus for checking a data frame length relate to an ethernet passive optical network in the communication field. The method includes: during reception of an ethernet frame, when determining through analysis that a received ethernet frame is a data frame, extracting frame length information and frame indication information in the data frame, and calculating a frame length mantissa according to the frame length information; writing the data frame into a small cache for storage according to the frame indication information, and counting write enable signals used for controlling writing of a data frame by using a base-n counter, so as to obtain a count value of the write enable signal; and comparing the frame length mantissa with the count value, and if a comparison result is consistent, then a data frame length being successfully checked, and writing the frame length information into the small cache for storage..
Zte Corporation


12/24/15
20150372477 

Apparatus for transmitting power and control method thereof


Disclosed are an apparatus for transmitting power and a control method thereof. The apparatus includes a first main relay electrically controlling connection between a positive (+) terminal of a high voltage power source and a positive (+) terminal of a high voltage load, a second main relay electrically controlling connection between a negative (−) terminal of the high voltage power source and a negative (−) terminal of the high voltage load, a semiconductor switch connected in parallel to the first main relay, a reverse current preventer interposed between the semiconductor switch and the high voltage power source and preventing reverse current to the high voltage power source, a drive state measurer measuring a drive state of a power relay assembly, and a relay controller supplying or shutting off power to the high voltage load by operating the first and second main relays and the semiconductor switch in response to a relay enable signal from a battery controller and shutting off the power to the high voltage load upon determining that the drive state of the power relay assembly measured through the drive state measurer is abnormal or upon determining based on a vehicle state received from the battery controller that a vehicle is in an emergency state..
Kyungshin Co., Ltd.


12/17/15
20150365080 

System and a pulse generator


According to an embodiment, a method of generating a clock pulse includes receiving a leading edge at a clock input at a time when an enable signal is active, generating an edge at a clock output based on the received leading edge at the clock input, latching a logic value corresponding to the edge at the clock output, preventing changes at the clock input from affecting the latched logic value after the logic value is latched, resetting the latched logic value after a first delay time, and maintaining the reset logic value until a second edge is received at the clock input. The second edge at the clock input matches the leading edge at the clock input..
Stmicroelectronics International N.v.


12/17/15
20150365076 

Clock buffers with pulse drive capability for power efficiency


A clock driver and corresponding method are provided. The clock driver includes a multi-stage delay cell having logic circuitry and a plurality of serially connected delay elements.
International Business Machines Corporation


12/17/15
20150364174 

Word line driver circuit and resistance variable memory apparatus having the same


A world line driver circuit according to an embodiment includes a driving unit configured to output a sub word line driving signal in response to a word line select signal and a main word line driving signal, a transmission unit configured to transmit the sub word line driving signal to a word line in response to a first enable signal, and a precharge unit configured to precharge a potential of the word line.. .
Sk Hynix Inc.


12/17/15
20150362987 

Power mode management of processor context


A system having multiple power mode types, for example, includes a power manager that is responsive to a selection of a suspend power mode type for maintaining processor context information in volatile memory while the processor is in the selected suspend mode. A status register is arranged to retain the status of the context information in the volatile memory while the processor is in the selected suspend power mode.
Texas Instruments Deutschland Gmbh


12/17/15
20150362945 

Internal voltage generation circuit of semiconductor apparatus


An internal voltage generation circuit may include a first internal voltage generation block configured for receiving a first external voltage and for generating an internal voltage with a voltage level corresponding to a voltage level of a first reference voltage; and a second internal voltage generation block configured for receiving a second external voltage, generate the internal voltage with a voltage level corresponding to a voltage level of a second reference voltage, compare voltage levels of the second reference voltage and the internal voltage, and generate a comparison signal, wherein only one of the first and second internal voltage generation blocks is activated and the other is deactivated, in response to an enable signal, and the second internal voltage generation block disables the comparison signal to a voltage level of the first external voltage when the first internal voltage generation block is activated.. .
Sk Hynix Inc.


12/03/15
20150349730 

Apparatus and methods power amplifier biasing


Apparatus and methods for biasing a power amplifier are disclosed. In one embodiment, a method of biasing a power amplifier includes shaping an enable signal using a time-dependent signal generator to generate a control current, amplifying the control current using a current amplifier to generate a correction current, and generating a bias current for a power amplifier using a primary biasing circuit.
Skyworks Solutions, Inc.


12/03/15
20150348941 

Stack package and reduction of standby current


The stack package includes: a plurality of chips each stacked with a plurality of layers; and a plurality of pads respectively formed on the plurality of chips. Each chip includes: a ground path unit configured to form a current path between a pad and a ground stage; a selection unit configured to selectively control a connection path electrically coupled to the pad according to a chip enable signal; and a controller configured to selectively control a connection between the selection unit and the ground path unit according to a control signal..
Sk Hynix Inc.


12/03/15
20150348479 

Method of driving light source, light source apparatus and display apparatus having the light source apparatus


A method of driving a light source includes outputting a light source driving signal and outputting a delayed driving signal. The light source driving signal drives a light source based on image data.
Samsung Display Co., Ltd.


12/03/15
20150348472 

Display panel drivers


This disclosure provides systems, methods and apparatus for providing voltages to an arrangement of display modules in a display. In one aspect, a group including multiple rows of display modules may be provided a reset signal at the same time.
Qualcomm Mems Technologies, Inc.


12/03/15
20150347896 

Electronic comparison systems


An electronic comparison system includes input stages that successively provide bits of code words. One-shots connected to respective stages successively provide a first bit value until receiving a bit having a non-preferred value concurrently with an enable signal, and then provide a second, different bit value.
Purdue Research Foundation


11/26/15
20150339963 

Current slope control method and appartus for power driver circuit application


A low side driver includes a first transistor coupled in series with a second transistor at a low side voltage node for a load. A capacitance is configured to store a voltage and a voltage buffer circuit has an input coupled to receive the voltage stored by the capacitance and an output coupled to drive a control node of the second transistor with the stored voltage.
Stmicroelectronics (shenzhen) R&d Co. Ltd


11/19/15
20150334622 

Apparatus and method to perform lte/wlan handoff by keeping lte attached or in suspended state


Systems and methods are disclosed to provide offloading procedures that reduce signaling load. Specifically, embodiments of the present disclosure provide offloading techniques that enable signaling overhead caused by attachment procedures to be avoided when user equipment (ue) reconnects to a cellular network after offloading data to a wireless local area network (wlan).
Broadcom Corporation


11/19/15
20150333511 

Energy lockout in response to a planar catastrophic fault


A computer planar includes an enable signal line for providing an enable signal to an external power supply, wherein the external power supply will not turn on unless the enable signal is active high. During normal operation, an auxiliary power source maintains an active high enable signal on the enable signal line, which includes a fuse.
International Business Machines Corporation


11/19/15
20150331434 

Method and apparatus to minimize switching noise disburbance


A power management circuit generates a reference voltage and distributes it to a plurality of independently-enabled regulator voltage reference circuits, each of which generates a predetermined voltage for a voltage regulator. Separate enable signals and enable pre-charge signals are distributed to each regulator voltage reference circuit.
Telefonaktiebolaget L M Ericsson (publ)


11/19/15
20150331044 

Scan flip-flop circuit with los scan enable signal


A scan flip-flop for generating an output signal based on a first input signal, a clock signal, a test input signal, a launch on shift (los) signal, a test enable signal, and a reset signal includes a logic circuit, a multiplexer and a flip-flop circuit. The logic circuit receives an inverted clock signal, the test enable signal, a intermediate test enable signal, and the los signal, and generates an intermediate output signal that is an inherent los scan enable signal.
Freescale Semiconductor, Inc.


11/12/15
20150326226 

Load switch for controlling electrical coupling between power supply and load


Circuits and methods for controlling electrical coupling by a load switch are disclosed. In an embodiment, the load switch includes a pass element, level-shift circuit and low-resistance active path.
Texas Instruments Incorporated


11/12/15
20150326008 

Fault protection circuit


A fault detection circuit for use with a power converter includes an initiate fault check circuit coupled to generate an enable signal in response to a first sense signal coupled to be received from an output socket. A threshold detection circuit is coupled to generate a threshold detection output signal in response to a second sense signal coupled to be received from the power converter and a second reference signal.
Power Integrations, Inc.


11/12/15
20150323960 

Method for asynchronous gating of signals between clock domains


An apparatus for synchronizing a signal from a first clock domain into a second clock domain is disclosed. The apparatus may include circuitry, a synchronization circuit, and a clock gate circuit.
Apple Inc.


11/12/15
20150323579 

Duty cycle detector and semiconductor integrated circuit apparatus including the same


A duty cycle detector may include a rising clock detection unit enabled in response to a first control signal; a falling clock detection unit enabled in response to a second control signal with a different activation timing from the first control signal; and a comparison unit configured to compare an output signal of the rising clock detection unit to an output signal of the falling clock detection unit in response to a comparison enable signal, and output a duty cycle detection signal.. .
Sk Hynix Inc.


11/05/15
20150318857 

Synchronised logic circuit


Consistent with an example embodiment, the disclosed includes a synchronised logic circuit comprising: an input module; an output module; a decision logic module connected between the input and output modules and configured to provide a next output state to the output module dependent on a current input state provided from the input and output modules; a clock module connected to the input and output modules and configured to provide a clock signal for synchronising operation of the input and output modules; and an input detection module connected to the input module and configured to provide an enable signal to the clock module on detection of a change in an input provided to the input module, wherein the clock module is configured to provide a clock signal to the input and output modules on receiving the enable signal from the input detection circuit.. .
Nxp B.v.


10/22/15
20150303900 

Isolation circuit


An isolation circuit includes a first multiplexer, a d flip-flop, a second multiplexer, an or gate, and an and gate. The first multiplexer selects a data signal or a scan-in signal as a first element output signal according to a scan enable signal.
Via Technologies, Inc.


10/15/15
20150296579 

Light emitting diode driving circuit, display device, lighting device, and liquid crystal display device


As a result of being provided with an enable signal generating unit that supplies, to an led driver, an enable signal that is dependent on a low state period of a pwm signal, it is possible to realize a light emitting diode driver circuit that can suppress a booster circuit starting up suddenly and an excess current flowing in a power source in the case where the pwm signal enters a high state (on state) after having been held in a low state (off state) for a prescribed period or longer.. .

10/15/15
20150296160 

Linear image sensor and driving method therefor


A logical gate circuit (5) and four stages of flip flips (4a-4d) are assigned to each pixel (1). A controller (7) inputs four phase identification signals into the logical gate circuit (5) and also inputs a start signal str into a shift register (4) synchronously with the four mutually different phases defined by the phase identification signals.

10/15/15
20150295500 

Sampling for dimmer edge detection in power converter


A controller and a method for controlling a power converter includes a sample block coupled to generate a first, second, and third sample by sampling an input sense signal that is representative of an input voltage of the power converter. An enable signal is asserted when a first difference between the first sample and the second sample exceeds a first threshold.

10/08/15
20150288278 

Charge pump regulator with small ripple output signal and associated control method


A charge pump regulator includes a charge pump circuit, a voltage divider, a mode determining circuit, a frequency divider, and a selecting circuit. The charge pump circuit receives an oscillation signal and generates an output signal.

10/08/15
20150287447 

Semiconductor devices and semiconductor systems including the same


Semiconductor devices are provided. The semiconductor device includes a control signal generator and a first data input unit.

10/08/15
20150287364 

Pixel circuit and display device using the same


A pixel circuit includes four transistors, two capacitors and a light emitting element. A gate of first transistor receives a scan signal and a source/drain thereof receives a display data.

10/08/15
20150285858 

Test mode entry interlock


An integrated circuit haying normal and special operating modes includes a mode entry interlock (201) which is enabled by an initialization command and an externally supplied voltage at a first i/o terminal (204) to detect a conflict at the i/o terminal for reducing the likelihood of inadvertent entry into the special operating mode. The mode entry interlock also includes a second i/o terminal (212) for receiving a disassociated software command to enter into the special operating mode, and mode control logic (210, 216) for evaluating the received software command against any detected conflict at the i/o terminal to generate a special operating mode enable signal in response to receiving the first and second input signals only when the detected logic state conflicts with the first logic state..

10/01/15
20150280721 

Clock delay detecting circuit and semiconductor apparatus using the same


Provided is a clock delay detecting circuit and semiconductor apparatus using the same that is capable of generating a period signal whose period is a delay time of a clock, dividing the period signal, and counting the divided period signal. The clock delay detection circuit comprises a period signal generating unit configured to generate a counting control signal, a period signal dividing unit configured to generate a counting enable signal by dividing the counting control signal, and a counting unit configured to generate a delay information signal by counting the counting enable signal with a clock, wherein the counting control signal has a period with a predetermined time..
Sk Hynix Inc.


10/01/15
20150275909 

Control device and control method


A control device, applied to a fan, including a first temperature sensing circuit, a second temperature sensing circuit and a driving circuit. The first temperature sensing circuit is arranged to output an enable signal when the temperature is higher than a first threshold temperature.
Accton Technology Corporation


09/24/15
20150270995 

Receiver of semiconductor apparatus and semiconductor system including the same


A receiver of a semiconductor apparatus includes a first buffer unit configured to buffer a first positive input signal and a first negative input signal having a phase opposite the phase of the first positive input signal and to output the buffered first positive input signal as a first positive transmission signal and to output the buffered first negative input signal as a first negative transmission signal in response to a first enable signal, a second buffer unit configured to buffer a second positive input signal and a second negative input signal having a phase opposite the phase of the second positive input signal and to output the buffered second positive input signal as a second positive transmission signal and to output the buffered second negative input signal as a second negative transmission signal in response to a second enable signal, is and an output unit configured to invert one of the first and second positive transmission signals and to output the inverted one of the first and second positive transmission signals as a positive output signal, and to invert one of the first and second negative transmission signals and to output the inverted one of the first and second negative transmission signals as a negative output signal.. .
Sk Hynix Inc.


09/24/15
20150270775 

Fast startup charge pump


A charge pump is designed to be capable of quick start up. When the enable signal of the charge pump is arrived, the pump capacitor and the load capacitor of the charge pump can be charged in a short time, referred to as a pre-charging stage.
Smarter Microelectronics (guang Zhou) Co., Ltd


09/24/15
20150269378 

Use of a physical unclonable function for checking authentication


In order to check authentication using a physical unclonable function, an authenticator includes a physical unclonable function (puf) and an authentication checking function. A challenge response pair provides challenge information and a response for the authenticator.
Siemens Aktiengesellschaft


09/17/15
20150263769 

Single-input multiple-output power amplifier


An rf amplifier, including: an input rf chain configured to receive and process an input rf signal including a plurality of frequency bands within a first band group and output a first signal; and a plurality of output rf chains coupled to the input rf chain, each output rf chain of the plurality of output rf chains configured to process the first signal within at least one band of the plurality of frequency bands of the first band group, wherein each output rf chain includes a bias circuit configured to receive an enable signal to enable the processing of the first signal within the at least one band and output an output rf signal within the at least one band.. .
Qualcomm Incorporated


09/17/15
20150262665 

Memory device


According to one embodiment, a memory controller sends a periodic control signal from a first terminal on a non-volatile memory side to the non-volatile memory, and the control signal includes a data strobe signal, a write enable signal, and a read enable signal.. .
Kabushiki Kaisha Toshiba


09/17/15
20150262655 

Negative bitline boost scheme for sram write-assist


A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element.
Taiwan Semiconductor Manufacturing Co., Ltd.


09/17/15
20150262646 

Semiconductor device


A semiconductor device may include a write control block configured to generate a plurality of write enable signals for controlling a write operation, and a write delay block configured to apply delay times to a plurality of write data which are transmitted through a write global input/output line. The semiconductor device may also include a plurality of banks configured to operate in response to the plurality of write enable signals and receive the plurality of write data, wherein the plurality of write data have different delay times according to physical positions of the plurality of banks..
Sk Hynix Inc.


09/10/15
20150256914 

System and a transducer system with wakeup detection


According to embodiments described herein, a circuit includes an interface circuit configured to be coupled to a transducer and a detection circuit. The interface circuit is configured to provide a digital output signal to a signal input terminal of a processing circuit.
Infineon Technologies Ag


09/10/15
20150256820 

Shutter glass and control controlling the same


The present invention provides a shutter glasses and a system and method for controlling the shutter glasses. The system includes: a receiver for receiving a 3d_enable signal and a stv signal; a timer for timing from the moment when the 3d_enable signal is in high level, and retiming once the stv signal triggered by a positive source is detected; and a resetter for resetting left and right shutter control signals at the moment when the stv signal is triggered by a positive source if the time started by the timer until the sw signal triggered by a positive source comes is longer than a set time, so that openings of left and right shutters of the shutter glasses synchronize with the left and right image signals.
Shenzhen China Star Optoelectronics Technology Co., Ltd.


09/10/15
20150254390 

Shared channel masks in on-product test compression system


A semiconductor chip includes a first mask logic. The first mask logic includes a first mask and a second mask that mask a respective first scan channel output and a second scan channel output.
International Business Machines Corporation


09/10/15
20150254387 

Shared channel masks in on-product test compression system


A semiconductor chip includes a first mask logic. The first mask logic includes a first mask and a second mask that mask a respective first scan channel output and a second scan channel output.
International Business Machines Corporation


09/03/15
20150248928 

Boost system for dual-port sram


A boost system for dual-port sram includes a comparator and a boost circuit. The comparator is configured to compare a first row address of a first port and a second row address of a second port, and output a first enable signal.
Taiwan Semiconductor Manufacturing Company Ltd.


08/27/15
20150243455 

Control circuit of switch device


The invention provides a control circuit of a switch device. A single output pin of the control unit outputs an enable signal to control terminals of two switch units to control an on-state of the two switch units, and adjust a current size of a control current of the on-state of the switch device.
Fsp Technology Inc.


08/27/15
20150243208 

Organic light emitting display device and driving method thereof


An organic light emitting display includes: a data driver configured to supply a data signal to data lines, corresponding to a data enable signal during a driving period in which an image is displayed; and a timing controller configured to supply data and the data enable signal to the data driver, wherein a first data enable signal having a first period and a second data enable signal having a second period differing from the first period are included in the data enable signal supplied during one frame period.. .
Samsung Display Co., Ltd.


08/27/15
20150242331 

Controlling access to a memory


A memory protection device for controlling access to a memory and a method of controlling access to a memory are disclosed. A memory status value held by latch circuitry in the memory protection device determines whether the memory is an enabled or a disabled state.
Arm Limited


08/27/15
20150241513 

Core circuit test architecture


A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths.
Texas Instruments Incorporated


08/20/15
20150235684 

Semiconductor apparatus


A semiconductor apparatus includes: a command control unit configured to decode external signals and generate a read strobe signal or a write strobe signal; a clock enable signal generation unit configured to activate one of a read clock enable signal and a write clock enable signal in response to the read strobe signal or the write strobe signal; and a clock control unit configured to generate a first control clock signal and a second clock control signal in response to an internal clock signal, the read clock enable signal, and the write to clock enable signal.. .
Sk Hynix Inc.


08/13/15
20150229222 

Power supply an electrical appliance


A power supply apparatus includes a power supply circuit and a power-on circuit. The power-on circuit detects a remotely transmitted control signal and causes a transition of the power supply circuit to a turned on state.
Stmicroelectronics S.r.l.




Enable Signal topics: Enable Signal, Control Unit, Electronic Device, Integrated Circuit, Semiconductor, Output Enable, Liquid Crystal, Liquid Crystal Display, Data Transfer, Buffer Circuit, Esd Protection Circuit, Protection Circuit, Electrostatic Discharge, Esd Protection, Programmable Memory

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