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 Multi-mode led illumination system patent thumbnailnew patent Multi-mode led illumination system
This application discloses a lighting emitting diode (led) illumination system that operates at least in a boost mode and a bypass mode. The led illumination system includes a plurality of leds and bypass elements.
Google Inc


 Differential circuit and image sensing device including the same patent thumbnailnew patent Differential circuit and image sensing device including the same
A differential circuit includes a differential selection block suitable for generating differential selection signals corresponding to differential input signals in response to an enable signal and a differential loading block suitable for loading differential output signals corresponding to the differential input signals on differential lines in response to the differential selection signals.. .
Sk Hynix Inc.


 Reception circuit,  adjusting timing in reception circuit, and semiconductor device patent thumbnailnew patent Reception circuit, adjusting timing in reception circuit, and semiconductor device
A reception circuit includes a control signal generation circuit that generates a first enable signal based on a strobe signal and a second enable signal based on a core clock signal and a pointer control signal. A pattern data generation circuit generates determination pattern data from the first enable signal.
Socionext Inc.


 Charging circuit interrupt devices with self-test and methods thereof patent thumbnailCharging circuit interrupt devices with self-test and methods thereof
A charging circuit interrupting device for applying an input voltage provided by first and second input power lines of a power system to first and second output power lines of an output system includes a current-detecting unit, a self-test device, and a controller. The current-detecting unit executes a leakage-detection function and generates a leakage signal when the current difference between the first and second power lines is detected.
Delta Electronics, Inc.


 Voltage generator, semiconductor memory device having the same, and  operating semiconductor memory device patent thumbnailVoltage generator, semiconductor memory device having the same, and operating semiconductor memory device
A voltage generator that includes an operation mode determination circuit suitable for determining an active mode or a standby mode based on a chip enable signal to activate an active mode signal or a standby mode signal according to a result of the determination; and a bulk voltage generation circuit outputting a bulk voltage having an internal power voltage when the active mode signal is activated, and outputting the bulk voltage having an external power voltage when the standby mode signal is activated.. .
Sk Hynix Inc.


 Low power input gating patent thumbnailLow power input gating
Various implementations described herein are directed to an integrated circuit for implementing low power input gating. In one implementation, the integrated circuit may include a chip enable device configured to receive and use a clock input signal to toggle a control input of memory based on a chip enable signal.
Arm Limited


 Scan flip-flop circuit with dedicated clocks patent thumbnailScan flip-flop circuit with dedicated clocks
In one form, a scan flip-flop includes a clock gating cell and a dedicated clock flip-flop. The clock gating cell provides an input clock input signal as a scan clock signal when a scan shift enable signal is active, and provides the input clock signal as a data clock signal when the scan shift enable signal is inactive.
Advanced Micro Devices, Inc.


 System for a transducer system with wakeup detection patent thumbnailSystem for a transducer system with wakeup detection
According to embodiments described herein, a circuit includes an interface circuit configured to be coupled to a transducer and a detection circuit. The interface circuit is configured to provide a digital output signal to a signal input terminal of a processing circuit.
Infineon Technologies Ag


 Method and system for safely switching off an electrical load patent thumbnailMethod and system for safely switching off an electrical load
A method and system for safely switching off an electrical load in a system comprising a multi-channel control unit, a single-channel data transmission path and an output unit having a first processing unit, a second processing unit and safe outputs. The method comprises receiving and evaluating an input signal by the multi-channel control unit and generating an enable signal based on the evaluation; transmitting the enable signal to the output unit via the single-channel data transmission path; receiving the enable signal by the first processing unit and generating an output signal based on the enable signal; providing at least one part of the enable signal from the first processing unit to the second processing unit for evaluation therewith; generating a dynamic clock signal by the second processing unit based on the enable signal; and controlling the safe outputs based on the output signal and the dynamic clock signal..
Pilz Gmbh & Co. Kg


 Semiconductor memory apparatus patent thumbnailSemiconductor memory apparatus
A semiconductor memory apparatus may include a decoding unit configured to enable one of a plurality of sub word line driver enable signals by decoding a plurality of addresses while the decoding unit operates in a normal mode, and enables specific sub word line driver enable signals among the plurality of sub word line driver enable signals regardless of the plurality of addresses while the decoding unit is operating in a test mode. The semiconductor memory apparatus may include a sub word line driver group configured to include a plurality of sub word line drivers, the plurality of sub word line drivers configured for activation in response to the plurality of sub word line driver enable signals.
Sk Hynix Inc.


Semiconductor storage device and control method thereof

According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals.
Kabushiki Kaisha Toshiba

Semiconductor device

There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an sram memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation.
Renesas Electronics Corporation

Memory subsystem and computer system

A method including estimating an access request frequency from a cpu to a memory subsystem by counting a number of cpu access requests and a number of requests other than cpu access requests, wherein the cpu is connected to the memory subsystem via a system bus, and the memory subsystem includes a memory controller connected to the system bus, and a ddr memory, including the estimated access request frequency with a predetermined threshold value stored in a register, generating a clock gate signal to decimate an operating clock of the memory controller in response to a result of comparing the estimated access request frequency with the predetermined threshold value, generating a dummy cycle signal to delay the timing of signal data output from the memory controller to the system bus, and generating a clock enable signal to decimate an operating clock of the ddr memory.. .
International Business Machines Corporation

Parallel test device and method

A parallel test device and method are disclosed, which relates to a technology for performing a multi-bit parallel test by compressing data. The parallel test device includes: a pad unit through which data input/output (i/o) operations are achieved; a plurality of input buffers configured to activate write data received from the pad unit in response to a buffer enable signal, and output the write data to a global input/output (gio) line; a plurality of output drivers configured to activate read data received from the global i/o (gio) line in response to a strobe delay signal, and output the read data to the pad unit; and a test controller configured to activate the buffer enable signal and the strobe delay signal during a test mode in a manner that the read data received from the plurality of output drivers is applied to the plurality of input buffers such that the read data is operated as the write data..
Sk Hynix Inc.

Extensible configurable fpga storage structure and fpga device

An extensible configurable fpga storage structure and an fpga device, where the fpga storage structure includes: a plurality of local storage units, a controller and two clock buffers, where the two clock buffers are separately used for providing different clock signals for two clock input ports of the controller; the controller is used for receiving a write address signal input externally, and driven by the clock signals, generating a plurality of enable signals and write address decoding signals to be output to the plurality of local storage units; and each of the local storage units includes a local memory and a multiplexer used for providing input data for the local memory; and, based on a configuration mode of each local storage unit, generates output data in the corresponding configuration mode according to the enable signals, input write address decoding signals or read address signals, and the input data.. .
Capital Microelectronics Co., Ltd.

Closed-loop brain stimulation generating stimulation voltage thereof

A closed-loop brain stimulation apparatus and a method for generating a stimulation voltage thereof are provided. The closed-loop brain stimulation apparatus includes a brain signal receiving apparatus, a controller and a stimulation voltage generator.
National Tsing Hua University

Phase-rotating phase locked loop and controlling operation thereof

A phase-rotating phase locked loop (pll) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating pll, the first and second loops configured to activate in response to an enable signal. The pll may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code..
Samsung Electronics Co., Ltd.

Circuits and methods for performance optimization of sram memory

In described examples, a memory controller circuit controls accesses to an sram circuit. Precharge mode control circuitry outputs: a burst mode enable signal to the sram circuit indicating that a series of sram cells along a selected row of sram cells will be accessed; a precharge first mode signal to the sram circuit indicating that a first access along the selected row will occur; and a precharge last mode signal to the sram circuit indicating that a last access along the selected row will occur.
Texas Instruments Incorporated

Compensation circuit, amoled structure and display device

The present invention relates to the field of display apparatus, more specifically, to a compensation circuit, an amoled structure and a display device. Said circuit comprises a plurality of pixel units, each for the plurality of pixel units includes at least one light emitter, and each of said pixel units comprises: an anode initialization signal interface, a cst initialization port, a data control port and an enable signal control port.
Everdisplay Optronics (shanghai) Limited

Display control device and display apparatus

A short delay time from imaging of an imaging element to displaying on a view finder is realized using a simple circuit configuration. An evf controller includes a serial i/f that receives a command including the number of valid lines of one frame, a counter that counts the number of lines of which an image signal becomes valid, a data input unit that inputs a valid image signal based on a data enable signal, a data output unit that outputs the input valid image signal to an evf, and a timing generation unit that compares a count value of the counter with the number of valid lines, detects an end of the input of the valid image signal in the frame based on a comparison result, and then starts a process for preparation for a next frame..
Seiko Epson Corporation

Method for authenticating a driver in a motor vehicle

The invention relates to a method for authenticating a driver (2) in a motor vehicle (1), having a detection device (10) which is arranged in the motor vehicle (1) and has the purpose of detecting actual data (50) of the driver (2) which is transmitted during the authentication to a checking device (20) which is arranged in an external station (3) outside the motor vehicle (1), wherein the checking device (20) compares the actual data (50) with setpoint data (60), and when the actual data (50) corresponds to the setpoint data (60) an enable signal (70) is transmitted from the external station (3) to the motor vehicle (1), as a result of which a starting process of the motor vehicle (1) for the driver (2) is made possible.. .
Huf HÜlsbeck & FÜrst Gmbh & Co. Kg

Phase-locked loop with lower power charge pump

Described is a phase-locked loop with lower power charge pump. The phase-locked loop comprises: a phase frequency detector to compare a reference clock and a feedback clock and generate a pulse based on the comparison, a charge pump to provide a charge signal corresponding to the pulse, a bias generator to provide biasing for the charge pump, wherein the bias generator is operable to receive a bias enable signal from the phase frequency detector and the bias generator is disabled when the bias enable signal is not asserted, a loop filter coupled to the output of the charge pump to provide a control signal responsive to the charge signal, and a voltage-controlled oscillator (vco), wherein the oscillating frequency of the vco is controlled by the control signal..
Intel Corporation

Data driver and driving the data driver

A data driver includes shift registers, sampling latches, holding latches, and a data sensing unit. The shift registers generate sampling pulses by shifting a source start pulse in response to a source sampling clock.
Samsung Display Co., Ltd.

Input voltage sensor responsive to load conditions

An ac-dc power converter controller includes a switch driver circuit coupled to generate a drive signal to control switching of a power switch to control a transfer of energy from an input of the power converter to an output of the power converter. An input sense circuit is coupled to receive an input sense signal representative of the input of a power converter.
Power Integrations, Inc.

Input/output buffer circuit

An input/output (i/o) buffer circuit includes an i/o unit and a protection circuit. The i/o unit selectively receives and outputs signals based on an enable signal.
Nuvoton Technology Corporation

Semiconductor apparatus

A semiconductor apparatus may include: a data storage group including first to eight data storage areas; a first channel select pad configured to transmit a first channel select signal to the first and third data storage areas; a second channel select pad configured to transmit a second channel select signal to the second and fourth data storage areas; a third channel select pad configured to transmit the first channel select signal to the sixth and eighth data storage areas; a fourth channel select pad configured to transmit the second channel select signal to the fifth and seventh data storage areas; a first clock enable pad configured to transmit a first clock enable signal to the first and third data storage areas; a second clock enable pad configured to transmit a second clock enable signal to the second and fourth data storage areas; a third clock enable pad configured to transmit the first clock enable signal to the fifth and seventh data storage areas; and a fourth clock enable pad configured to transmit the second clock enable signal to the sixth and eighth data storage areas.. .
Sk Hynix Inc.

Data compensation device and display device including the same

A data compensation device includes a current calculator which calculates an average current of each of blocks included in a pixel array based on an input data, a data enable signal, a horizontal synchronization signal and a vertical synchronization signal, a voltage drop info provider which provides a bus voltage drop information of predetermined bus points and an array voltage drop information of predetermined array points, the bus points being included in a power supply bus wiring which is connected to the pixel array, the array points being included in the pixel array, a data compensation circuit configured to provide a compensation data corresponding to the input data based on the average current, the bus voltage drop information and the array voltage drop information, and an adder configured to provide a compensation result data by adding the input data and the compensation data.. .
Samsung Display Co., Ltd.

Control circuits for generating output enable signals, and related systems and methods

Control circuits for generating output enable signals are disclosed. In one aspect, a control circuit is provided that employs combinatorial logic to generate an output enable signal that meets timing constraints using a standard clock signal, a feedback clock signal based on the standard clock signal, and a single data rate (sdr) data output stream.
Qualcomm Incorporated

Led driving device, illuminator, and liquid crystal display device

The present invention provides a light emitting diode (led) driving device as a semiconductor device, which comprises: a direct current/direct current (dc/dc) controller, for controlling an output segment that is used to generate an output voltage from an input voltage and supply the output voltage to an led; an output current driver, for generating an output current of the led; and an led short-circuit detection circuit, for monitoring a cathode voltage of the led to perform an led short-circuit detection, wherein the led short-circuit detection circuit controls whether an action is performed or not according to a short-circuit detection enable signal input from outside the led driving device.. .
Rohm Co., Ltd.

Area-delay-power efficient multibit flip-flop

A multi-bit flip-flop (mbff) includes a plurality of 1-bit flip-flops, each having an input data selection circuit that receives a data signal and a scan data signal. The mbff also includes a local signal generation circuit that receives a global clock signal and a global scan enable signal, and in response, provides local control signals, wherein each of the local control signals is generated in response to both the global clock signal and the global scan enable signal.
Synopsys, Inc.

Integrated circuit

An integrated circuit includes a first signal generation unit suitable for generating a first enable signal which is activated during an initial setting period; a second signal generation unit suitable for generating a second enable signal which is activated in response to a command for performing a preset operation, after the initial setting period; and a temperature code generation unit suitable for generating temperature codes in response to activation of the first and second enable signals.. .
Sk Hynix Inc.

Transmission gate circuit

A transmission gate circuit includes a pass gate and a control circuit and provides high voltage protection to a flash memory in a characterization mode and a low resistive path with true open-drain functionality in a normal mode. A native nmosfet in series with the pass gate provides overvoltage protection for additional circuitry.
Freescale Semiconductor, Inc.

Semiconductor memory apparatus

A semiconductor memory apparatus includes a driving current control block configured to sense a resistance value of a dummy memory element, and generates a write driver control signal; and a write driving block configured to provide a driving voltage to a memory cell array in response to a write driver enable signal and the write driver control signal.. .
Sk Hynix Inc.

Power management driver and display device having the same

A power management driver includes a boost converter, a plurality of regulators, a sequence controller, and an operation controller. The boost converter converts an input voltage to a source drive voltage for drive a source driver based on a drive enable signal.
Samsung Display Co., Ltd.

Double half latch for clock gating

A double half latch circuit includes a first stage coupled to receive a local input enable signal on an input of a second logic gate, and a complement of the clock signal on an input of a third logic gate, and further includes a fourth logic gate coupled to generate an intermediate enable signal based on states of the local input enable signal the complement of the clock signal. A second stage includes a fifth logic gate coupled to receive the complement of the clock signal, and a sixth logic gate coupled to receive the intermediate enable signal, and is configured to generate the output enable signal.
Oracle International Corporation

Method and system for defining slot addresses

A method and system for assigning slot addresses to modules in an industrial control system is disclosed. The modules are set up in a daisy chain topology.
Rockwell Automation Technologies, Inc.

Analog switch having reduced gate-induced drain leakage

In an example, an apparatus includes an analog switch having an n-type metal oxide semiconductor (nmos) circuit in parallel with a p-type metal oxide semiconductor (pmos) circuit between a switch input and a switch output. The analog switch is responsive to an enable signal that determines switch state thereof.
Xilinx, Inc.

Semiconductor memory apparatus and operating method thereof

A semiconductor memory apparatus may include: a memory area; and a controller including a register configured to store parameter setting data, and to provide the parameter setting data to the memory area based on a data transmission enable signal enabled according to a parameter setting command or parameter get command.. .
Sk Hynix Inc.

Organic light-emitting diode display with pulse-width-modulated brightness control

A display may have an array of pixels arranged in rows and columns. Display driver circuitry may load data into the pixels via data lines that extend along the columns.
Apple Inc.

Interconnections for plural and hierarchical p1500 test wrappers

A test architecture accesses ip core test wrappers within an ic using a link instruction register (lir). An ieee p1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper.
Texas Instruments Incorporated

Input/output buffer circuit

An input/output (i/o) buffer circuit includes an i/o unit, a first register and a second register. The i/o unit selectively transmits digital signals and analog signals according to a enable signal, and selectively receives signals and outputs signals at an i/o terminal according to a second enable signal.
Nuvoton Technology Corporation

Array substrate, driving method thereof and display device

Disclosed are an array substrate, a driving method thereof, and a display device. The array substrate comprises a scan driving unit (10) located in a peripheral area and configured to input an enable signal to one terminal of at least one driving control line (vdd) in a display area so as to drive an oled device to emit light.
Boe Technology Group Co., Ltd.

Pre-charge driver for light emitting devices (leds)

An led driver includes a current driver receiving a reference voltage providing a charging current for driving channel output(s) of an led panel. A pre-charge circuit includes a voltage selector having a first and second select input, a control input receiving a pre-charge voltage select signal based on a next on/off state that is after a current sub-period, and a voltage selector output for switchably outputting a higher voltage level (v_h) when the next state is off and a lower level (v_l) when the next state on.
Texas Instruments Incorporated

Semiconductor device

A semiconductor device of one embodiment includes semiconductor chips. While the semiconductor device is receiving a power supply and a chip enable signal which is negated, all external terminals of the semiconductor chips are at the same logic level..
Kabushiki Kaisha Toshiba

Chemical controller system and method

A chemical controller for an aquatic application comprising at least one output relay. The chemical controller further includes a current detection circuit configured to detect current on an output of the at least one output relay and a current fault detection device configured to output a current fault signal indicative of the occurrence of a current fault condition.
Pentair Water Pool And Spa, Inc.

Control virtual navigation

The disclosure is related to a control system for virtual navigation, and a method. The system includes a central control unit used for managing the peripheral devices of the system, and a control device is provided.
Staging Design Inc.

Semiconductor device

Provided is a semiconductor device, including: an enable generating circuit (10) for generating an enable signal, being a pulse train in synchronization with a clock signal, and supplying the enable signal to a protection target circuit (30); and a first abnormality detecting circuit (20) for detecting an abnormality of clock timing due to introduction of a spike into the clock signal based on comparison between the clock signal and the enable signal generated by the enable generating circuit. Thus, a semiconductor device capable of detecting a local clock abnormality is obtained..
Mitsubishi Electric Corporation

Injection locked frequency divider capable of adjusting oscillation frequency

An injection locked frequency divider is disclosed. The injection-locked frequency divider includes a sub-harmonic injection-locked oscillator, a reference clock divider, a counter, and a variable load resistor control unit.
Research & Business Foundation Sungkyunkwan University

Analog to digital converter compatible with image sensor readout

A time to digital converter (tdc) includes a synchronizer configured to receive a stop signal and a master clock signal, wherein the synchronizer is configured to generate a clock stop signal and a counter enable signal. The tdc further includes a coarse counter configured to receive the master clock signal and the counter enable signal, wherein the coarse counter is configured to generate a most significant bits (msb) signal based on the counter enable signal and the master clock signal.
Taiwan Semiconductor Manufacturing Company, Ltd.

Quick-start high-voltage boost

In one implementation, a voltage boost assembly including a boost converter having a capacitive element arranged at an output, and an inductive element connectable to an electrical supply. The voltage boost assembly also includes a sensor assembly provided to generate a quick-start enable signal in response to detecting that an electrical condition relative to an electrical output of the boost converter has breached a first threshold.
Skyworks Solutions, Inc.

Ultrasound scanning apparatus, breathing machine, medical system and related method

An ultrasound scanning apparatus, a breathing machine, a medical system and a related method. The ultrasound scanning apparatus comprises an ultrasound scanning unit, an ultrasound controller for controlling the operation of the ultrasound scanning unit, detecting the operation state of the ultrasound scanning unit, generating a first enable signal when detecting that the operation state of the ultrasound scanning unit is transferred from an operating state to a nonoperating state and generating a second enable signal when detecting that the operation state of the ultrasound scanning unit is transferred from the nonoperating state to the operating state, and an enable output end for transmitting the first enable signal or the second enable signal to the breathing machine to control the running of the breathing machine..
Shenzhen Mindray Bio-medical Electronics Co., Ltd.



Enable Signal topics:
  • Enable Signal
  • Control Unit
  • Electronic Device
  • Integrated Circuit
  • Semiconductor
  • Output Enable
  • Liquid Crystal
  • Liquid Crystal Display
  • Data Transfer
  • Buffer Circuit
  • Esd Protection Circuit
  • Protection Circuit
  • Electrostatic Discharge
  • Esd Protection
  • Programmable Memory


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