|| List of recent Enable Signal-related patents
|Interpolation filter based on time assignment algorithm|
Disclosed is an interpolation filter based on time assignment algorithm. An interpolation filter comprises an enable signal generating part generating enable signals for operation of the interpolation filter, an input value generating part generating input values, a first calculating part generating a first output value based on a first enable signal and a first input value, a second calculating part generating a second output value based on a second enable signal and a second input value, and an output value selecting part selecting a final output value among the first output value and the second output value.
Electronics And Telecommunications Research Institute
|Data input circuit|
A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal clock during a burst period from substantially a time when the pulse of the shifting signal is generated.
Sk Hynix Inc.
|Driving apparatus of display|
A driving apparatus of a display is disclosed. The driving apparatus includes a digital-to-analog converter (dac) circuit, an output buffer circuit and a pre-charge circuit.
Novatek Microelectronics Corp.
|Clock delay detecting circuit and semiconductor apparatus using the same|
Provided is a clock delay detecting circuit and semiconductor apparatus using the same that is capable of generating a period signal whose period is a delay time of a clock, dividing the period signal, and counting the divided period signal. The clock delay detection circuit comprises a period signal generating unit configured to generate a counting control signal, a period signal dividing unit configured to generate a counting enable signal by dividing the counting control signal, and a counting unit configured to generate a delay information signal by counting the counting enable signal with a clock, wherein the counting control signal has a period with a predetermined time..
Sk Hynix Inc.
|Switch supporting voltages greater than supply|
Devices for isolating an input from an output are disclosed. For example, a device includes a first p-type metal oxide semiconductor transistor and a first circuit.
|Parallel test device and method|
A parallel test device and method are disclosed, which relates to a technology for performing a multi-bit parallel test by compressing data. The parallel test device includes: a pad unit through which data input/output (i/o) operations are achieved; a plurality of input buffers configured to activate write data received from the pad unit in response to a buffer enable signal, and output the write data to a global input/output (gio) line; a plurality of output drivers configured to activate read data received from the global i/o (gio) line in response to a strobe delay signal, and output the read data to the pad unit; and a test controller configured to activate the buffer enable signal and the strobe delay signal during a test mode in a manner that the read data received from the plurality of output drivers is applied to the plurality of input buffers such that the read data is operated as the write data..
Sk Hynix Inc.
|Power converter for reducing standby power consumption|
There is provided a power converter for reducing standby power consumption. The power converter includes a rectifier configured to rectify ac power into dc power, a transformer configured to output power by converting a voltage of dc power rectified by the rectifier, a pwm control module configured to control an output power by switching a power switching device connected to the transformer, a first external switch configured to provide a disable signal, a first capacitor that is connected in parallel to one side of the first external switch, a second external switch configured to provide an enable signal, and a second capacitor that is connected in parallel to one side of the second external switch..
Magnachip Semiconductor, Ltd.
|System and providing a multi-mode embedded display|
An information handling system includes a display panel, a panel connector, and a source device. The display panel displays images at different resolutions.
Dell Products, Lp
|Automatic input impedence control|
The present disclosure is directed to an input impedance control circuit. In one embodiment, the automatic input impedance control circuit includes a circuit controller that comprises a module for calculating an impedance and a control logic module, wherein the control logic module provides a current enable signal and a current control output signal, a driver in communication with the circuit controller for receiving the current enable signal and the current control output signal, an input voltage sensing circuit in communication with the module for calculating the impedance and the control logic module and an input current sensing circuit in communication with the module for calculating the impedance..
|Display device and driving method thereof|
A display device and driving method thereof are disclosed. In one aspect, the display device includes a display panel displaying a still image and a moving image and a signal control unit controlling signals for driving the display panel and controlling a frequency of the display panel based on a low frequency enable signal.
Samsung Display Co., Ltd.
Semiconductor device, display device, and signal loading method
The present invention provides a drive ic, a display device and a loading method that enable signals of different differential formats to be loaded without resulting in circuit redundancy. Namely, a drive ic includes an input section, a holding section, a selection section, and an output section.
Lapis Semiconductor Co., Ltd.
Display apparatus and source driver thereof
A display apparatus and a source driver thereof are disclosed. The source driver includes a temperature sensor and a power switch.
Novatek Microelectronics Corp.
Source driver with reduced number of latch devices
A source driver with reduced number of latch devices includes a master latch device and at least one slave latch device. The master latch device has a first transmission gate, a first inverter, a second inverter, a first enable gate, and a second enable gate.
Orise Technology Co., Ltd.
Semiconductor apparatus and semiconductor system
Provided is a semiconductor apparatus including a plurality of semiconductor chips coupled through an electrical coupling unit. Each of the semiconductor chips includes: a chip id signal generation unit configured to generate a chip id signal; and a chip enable signal generation unit configured to receive a clock enable signal in response to the chip id signal, wherein one of the semiconductor chips shares the received clock enable signal as a transfer clock enable signal with the other semiconductor chips, and the chip enable signal generation unit detects whether or not an error occurs in the chip id signals of the plurality of semiconductor chips, selects any one of the transfer clock enable signal and the clock enable signal applied, and outputs the selected signal as a chip enable signal..
Sk Hynix Inc.
Multi master arbitration scheme in a system on chip
A multi master system on chip (soc) includes a plurality of masters comprising a first master and a second master, each configured to generate a request. A next state generator in the multi master soc is configured to generate a next state of a round robin pointer in response to the request and a current state of the round robin pointer.
Texas Instruments Incorporated
Semiconductor device with fuse array and operating method thereof
A semiconductor device includes a fuse array for storing normal fuse data and pattern data through a programming operation, a boot-up control unit suitable for generating an enable signal for enabling an output of the pattern data, and a pattern detection unit suitable for detecting a pattern of the pattern data in response to the enable signal, and generating a detection signal. The fuse array outputs the normal fuse data in response to the detection signal..
Sk Hynix Inc.
Thin film transistor array substrate and driving method therefor as well as liquid crystal display
A thin film transistor array substrate, a driving method therefore, and a liquid crystal display are disclosed. The thin film transistor array substrate includes at least a sub-pixel region formed by a gate line and a data line intersected with each other, wherein, each sub-pixel comprises a first transistor (21) of which the gate is connected with a gate line and the drain is connected with a data line and a first storage capacitor (23) of which one end is connected with the source of the first transistor (21) and the other end is connected with an output of a reference voltage, the sub-pixel further comprises a second storage capacitor (24) and a second transistor (25), wherein one end of the second storage capacitor (24) is connected with the source of the first transistor (21), and the other end of the second storage capacitor (24) is connected with the drain of the second transistor (25); the source of the second transistor (25) is connected with the output of the reference voltage, and the gate of the second transistor (25) is connected with an output of an enable signal.
Boe Technology Group Co., Ltd.
Clock control device
A clock control device is disclosed, which relates to a technology for reducing the amount of current consumption when a semiconductor device operates at a high speed. The clock control device includes: a chip-select-signal control block configured to generate a chip-select-control signal by latching a chip select signal, and output a fast chip select signal according to the chip-select-control signal; and a clock control block configured to drive a clock signal in response to the fast chip select signal when a command clock enable signal is activated, thereby generating a clock control signal, wherein the chip-select-signal control block latches the chip-select-control signal, and controls the chip-select-control signal to be toggled after the command clock enable signal is transitioned..
Sk Hynix Inc.
Double data rate counter, and analog-digital converting appratus and cmos image sensor using the same
A double data rate (ddr) counter includes a clock selection unit suitable for selectively inverting a first counting clock based on a control signal and for outputting a second counting clock, a first latch stage suitable for latching the second counting clock based on a counting enable signal and for outputting the least significant bit (lsb) of the ddr counter, a determination unit suitable for generating the control signal based on the last bit state of the lsb in a reset counting period, and a second latch stage suitable for receiving the lsb as a clock input to generate a higher bit of the lsb at least in a main counting period.. .
Sk Hynix Inc.
Redundancy evaluation circuit for semiconductor device
A redundancy evaluation circuit has (m+1) fuse boxes and a comparator, wherein the m fuse box output a fuse status address signal and the other one fuse box outputs a comparator enable signal. Each fuse box has a common stage circuit and k redundant cells.
Envelope tracker with variable boosted supply voltage
Techniques for efficiently generating a variable boosted supply voltage for an amplifier and/or other circuits are disclosed. In an exemplary design, an apparatus includes an amplifier, a boost converter, and a boost controller.
Voltage regulator, operation method thereof, voltage regulating system, and mobile vehicle
A voltage regulator, an operation method thereof, and a voltage regulating system, and a mobile vehicle are provided. The voltage regulator coupled to an alternator and a battery includes a voltage detection unit which is coupled to the alternator and a startup assisting unit.
Redundant power supply circuit, power over ethernet system, and method
A redundant power supply circuit includes a port detection circuit, a fixed state detection circuit, a voltage conversion circuit, and a control circuit. The port detection circuit detects and outputs a plurality of ready signals according to a plurality of power signals of a number of poe ports.
Core circuit test architecture
A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths.
Server and power chip detecting method
A power chip detecting device, applied in a server, includes a power chip, a power sequence control module, a base management controller, a gpio module, and a signal detecting module. The power sequence control module sends an initial power enable signal to the power chip after the server is switched on, and the power sequence control module receives an initial power good signal from the power chip after the power chip receives the initial power enable signal.
The semiconductor device includes an internal clock generator, a shift signal generator and a first control signal generator. The internal clock generator generates a first internal clock signal and a second internal clock signal in response to an external clock signal.
I/o data retention device
An apparatus for controlling retention of data includes a logic circuit, a retention control cell circuit, and an i/o cell circuit. The logic circuit generates at least one retention enable signal before a chip enters a reduced power mode.
Nonvolatile memory device, read nonvolatile memory device, and memory system incorporating nonvolatile memory device
A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read data after the strobe signal is toggled a predetermined number of times.. .
Semiconductor devices and semiconductor systems including the same
Semiconductor devices are provided. The semiconductor device includes a control signal generator and a first data input unit.
Semiconductor device and semiconductor memory device
A semiconductor device includes a fuse array having a plurality of fuse sets suitable for outputting a plurality of fuse status signals having different levels according to whether fuses of the plurality of fuse sets are cut or not, a code counter suitable for counting selection codes in a preset order in response to an enable signal and an operation clock, and storage blocks suitable for receiving and storing the plurality of fuse status signals in a preset order in response to the selection codes.. .
An internal voltage generation circuit of a semiconductor apparatus includes: an active driver configured to output an internal voltage to an output node; a standby driver configured to output the internal voltage to the output node; and a voltage stabilizer connected to the output node. The voltage stabilizer starts a voltage stabilization operation of supplying or receiving electric charges to or from the output node when an active enable signal is disabled, and stops the voltage stabilization operation in a predetermined time after the active enable signal is enabled..
A lighting device includes a switch element coupled to a power source; a bridge current rectifying unit in communication with the switch element for converting alternating current received from the power source into direct current; a driving and light-emitting module in communication with the bridge current rectifying unit; and a counting and control unit in communication with the switch element and the driving and light-emitting module. The counting and control unit counts a switching number of the switch element, and selectively outputs one or both of a first enable signal and a second enable signal to the driving and light-emitting module to emit light of a selected feature according to the switching number of the switch element..
Method and optical transmission in a communication network
A manner of mitigating the self heating effect of a laser or other light source such as a laser in a network node of a communication network. A self-heating mitigation module is provided, the self-heating mitigation module includes one or both of a self-heating adjustment module to accelerate self heating at the beginning of a transmission and a sub-threshold lasing module that applies a sub-threshold current between transmissions.
Clock reproducing and timing method in a system having a plurality of devices
A system includes a memory controller and a plurality of semiconductor devices that are series-connected. Each of the devices has memory core for storing data.
A semiconductor apparatus includes: a command control unit configured to generate a read strobe signal, a write strobe signal, a read command, and a write command; a clock enable signal generation unit configured to generate a read clock enable signal in response to the read strobe signal and generate a write clock enable signal in response to the write strobe signal; a clock control unit configured to generate a first control clock signal and a second control clock signal in response to an internal clock signal, the read clock enable signal, and the write clock enable signal; and a latency shift unit configured to generate a first latency signal in response to a delayed read command and the first control clock signal and generate a second latency signal in response to a delayed write command and the second control clock signal.. .
Power controller with pulse skipping
A controller for a power converter includes a drive circuit coupled to generate a drive signal in response to an error signal representative of a load of the power converter. The drive circuit includes a pulse skipping circuit coupled to generate a blanking signal in response to the error signal.
Scanning signal line drive circuit and display device equipped with same
This liquid crystal display device allows outputs from rs-ff circuits (401 to 409) and switch circuits (411 to 419), which function as a shift register, to be provided as scanning signals that are selectively activated during odd and even scanning line selection periods, by simply changing the potential of an enable signal (en) (i.e., by simply providing an en signal line), which achieves interlacing drive that allows a reduction in the number of polarity inversions, thereby making it possible to reduce power consumption and a wiring area for control lines and achieve simple control which allows circuit simplification, resulting in a reduced frame area and a display panel which is compact as a whole.. .
I/o circuit with phase mixer for slew rate control
An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal.
Sleep mode circuit and a placing a circuit into sleep mode
A first circuit is configured to communicatively couple to a second circuit including an analog circuit and a digital circuit. The first circuit comprises a lock unit and a sleep unit.
Phase-rotating phase locked loop and controlling operation thereof
A phase-rotating phase locked loop (pll) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating pll, the first and second loops configured to activate in response to an enable signal. The pll may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code..
Adaptive interface for coupling fpga modules
A method for implementing an adaptive interface between at least one fpga with at least one fpga application and at least one i/o module, which are designed as the corresponding sender side or receiver side, for connection to the fpga, whereby a serial interface is formed between the at least one fpga and the at least one i/o module, comprising the steps of configuring a maximum number of registers to be transmitted for each fpga application, configuring a shared, fixed register width for all registers, setting an enable signal on the sender side for the registers to be transmitted out of the maximum number of registers to be transmitted, transmitting the enable signal from the sender side to the receiver side, and transmitting the registers, for which the enable signal is set, from the sender side to the receiver side.. .
Light source module, light source module driving circuit and driving method
The present invention discloses a light source module, a light source module driving circuit and a driving method. The driving circuit comprises: a power supply, which provides input voltage; a control signal generating circuit, which inputs the input voltage provided from the power supply and outputs an enable signal and a dimming signal; a driving chip, which is connected with the power supply and connected to the enable signal and the dimming signal output from the control signal generating circuit, driving the light source of the light source module according to the enable signal and the dimming signal.
Integrated circuit with toggle suppression logic
An integrated circuit with toggle suppression logic for built-in self-test is provided. The integrated includes a loading circuit configured to operate in a shift mode based on a first enable signal and a capture mode based on a second enable signal.
Voltage detection circuit
A voltage detection circuit includes a reference voltage and current supply configured to generate a reference voltage and a reference current; a switching element configured to shift from an off-state to an on-state when the reference voltage is higher than a predetermined threshold voltage; a current mirror circuit allowing a current corresponding to the reference current to flow through the switching element in the on-state; a capacitive element coupled in series to the current mirror circuit and charged with the current flowing through the switching element; and an inverter configured to output an enable signal activated based on a terminal voltage of the capacitive element.. .
A semiconductor device includes: a plurality of repair fuse circuits configured to each program a repair target address; and an enable signal generation circuit configured to generate at least one enable signal in response to a source signal and provide the enable signal to each of the repair fuse circuits in common. Since the semiconductor device may iteratively generate a rupture enable signal through a feedback scheme, the area occupied by a circuit, such as a shift register or a d flip-flop may be saved..
Apparatus and reading data from multi-bank memory circuits
The disclosure relates to an apparatus for reading data from a memory circuit that includes at least two memory banks. The apparatus includes a first multiplexer configured to generate data at a first output from a first selected one of a first set of bit lines of a first memory bank based on a select signal.
Semiconductor device, semiconductor system including the semiconductor device, and driving the semiconductor system
A semiconductor device includes a plurality of pads, a plurality of data input/output units connected with the plurality of pads and enabled in response to a plurality of enable signals, and a group programming unit suitable for grouping the plurality of pads into a number of pad groups in response to a mode register set (mrs) code and group information, and generating a number of groups of enable signals corresponding to the number of pad groups, wherein a number of groups of the data input/output units are sequentially enabled in response to respective groups of the enable signals.. .
Charging methods of detachable electronic devices
An electronic device includes a first battery, a first charging unit, a first voltage adjustment unit, a power detection module, and a first control module. The first charging unit charges the first battery according to a supply voltage and a first charging enable signal.
Input/output line driver circuit
Input/output (i/o) line driving circuits are provided. The circuit includes a first i/o line driver and a second i/o line driver.
Method for displaying electronic program guide, electronic device, and computer readable medium
A method for displaying an electronic program guide (epg), an electronic device, and a computer readable medium are provided. After a guide enable signal is received, a program database is searched according to a current channel to obtain a current category corresponding to the current channel.
Method and estimating motion
Provided are a motion estimation method and a motion estimation apparatus. The motion estimation apparatus includes a first register storing information on whether to detect first detection positions, a second register storing information on distances and number information of valid distance information, a controller receiving a command, a shifter, in response to the shift-enable signal, shifting and outputting reference data in a detection region of a reference frame and outputting the received reference data as it is, a selector, in response to the selection signal, selecting and outputting a part of output data of the shifter or outputting the whole output data, a process element (pe) array receiving current data of a current frame, and a comparator generating operation results for respective block sizes using operation results of the plurality of the pegs..
Driving control circuit of display device
The present invention aims to provide a driving control circuit of a display device, which includes a plurality of data driving circuits each having a timing controller merged with a source driver. The data driving circuits are configured to synchronize data of the respective data driving circuits and compensate for a difference between a data enable signal and a gate output enable signal, when an abnormal display signal is received..
Comparator and clock signal generation circuit
A comparator used in a clock signal generation circuit has first and second input transistors coupled to input signals of the comparator. First and second hysteresis transistors are coupled between the input transistors and an output stage of the comparator, and apply hysteresis to a comparison of the input signals.
Low power clock gating circuit
A clock gating circuit for generating a clock enable signal with respect to a clock input signal and a logic enable signal includes: a first plurality of transistors for receiving at least the logic enable signal and generating a first output; a second plurality of transistor for receiving at least the first output and generating a second output; a third plurality of transistors for receiving at least the second output and an inverted second output; and an and gate circuit, for receiving the second output and generating the clock enable signal when the logic enable signal is at logic 1. One transistor of the first plurality of transistors, the second plurality of transistors and the third plurality of transistors, respectively, receives the clock input signal at its gate..
Domain crossing circuit of semiconductor apparatus
A domain crossing circuit of a semiconductor apparatus includes a delay-locked loop block configured to generate a delay-locked loop clock signal in response to a clock signal and a clock enable signal; a clock enable block configured to generate the clock enable signal in response to the clock signal and a read command signal; and a command pass block configured to perform primary latency control according to the clock signal and secondary latency control according to the delay-locked loop clock signal, for the read command signal generated in response to a strobe signal, and generate a latency signal.. .
Video signal transmission device, video signal reception device, and video signal transmission system
A video transmission device 10 has: a packer 11 which receives a video signal, a sync signal, and a data-enable signal, and generates a plurality of packet signals by packetizing the video signal and the sync signal based on the data-enable signal and according to the number of bytes of a packet corresponding to the number of gradation bits of the video signal; an encode unit 15 which generates a plurality of encoded packet signals by encoding the plurality of packet signals; and a serializer 14 which generates a serial packet signal by parallel-serial converting the plurality of encoded packet signals. The packer 11 generates a control signal including a pulse with a pulse width corresponding to the number of bytes of the packet, and the encode unit 15 subjects a portion of the packet signals corresponding to the pulse in the control signal from the packer, to an encode process which is different from a process for the other portion..
Display device that switches light emission states multiple times during one field period
A scan driving circuit includes a shift register unit and a logic circuit unit. The start of a start pulse of an output signal stp+1 of a p+1′th shift register is situated between the start and end of a start pulse of the output signal stp of a p′th shift register, and one each of a first enable signal through a q′th enable signal exist in sequence between the start of the start pulse of the output signal stp and the start of the start pulse of the output signal stp+1.
Latch circuit of display apparatus, display apparatus, and electronic equipment
A latch circuit for outputting data for m pixels present in one line on a display panel in a time-division manner for each pixel, in order to drive each pixel from among the m pixels based on n-bit data, includes m×n 1-bit latch circuits in which n 1-bit latch circuits are arranged in the column direction y and m 1-bit latch circuits are arranged in the row direction x, each circuit latching 1-bit data. Each 1-bit latch circuit includes a data latch unit circuit that latches data corresponding to any one bit of the n bits at different timings for each row, a line latch unit circuit that simultaneously latches data from the data latch unit circuit in each row, and an output enable element that outputs data from the line latch unit circuit based on an enable signal for selecting any one column..
Controlled power boost for envelope tracker
An envelope-tracking (et) power supply may include a boost control pin. The boost control pin receives a boost enable signal that activates or enables a supplemental power supply in the et power supply.
System and strengthening of a circuit element to reduce an integrated circuit's power consumption
A system and method enable strengthening of flip-flops (ffs) in an integrated circuit (ic) for the purpose of reducing power consumption. This is achieved by using stability condition (stc) and observability don't-care (odc) techniques.
Reducing power consumption during idle state
Methods and apparatus relating to power consumption reduction during idle state(s) are described. In one embodiment, logic transfers control of a power state of a device to one or more general purpose input output signals.
Fast turn on system for a synthesized source signal
A fast turn on compensation system for a synthesized signal source includes a synthesized signal source coupled to a power supply and configured to generate a phase stable radio frequency (rf) output signal. A mute amplifier is coupled to the synthesized signal source and the power supply.
Negative charge pump regulation
A negative charge pump is responsive to a pump enable signal. A voltage controlled current source provides a current.
Circuits and methods for dqs autogating
In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second buffer.
Load-selective input voltage sensor
A power converter controller includes a switch driver circuit coupled to generate a drive signal to control switching of a power switch to control a transfer of energy from an input of the power converter to an output of the power converter. An input sense circuit is coupled to receive an input sense signal representative of the input of a power converter.
Ac voltage sensor with low power consumption
A power converter controller includes an input sense circuit to receive an input sense signal representative of an input of a power converter. A zero-crossing detector is coupled to the input sense circuit to be responsive to the input sense signal falling below a first zero-crossing threshold and rising above a second zero-crossing threshold to determine zero-crossing intervals.
Switched mode power converter controller with ramp time modulation
A controller for use in a power converter includes a drive circuit coupled to generate a drive signal to control switching of a power switch to control a transfer of energy from a power converter input to a power converter output. The controller also includes an input for receiving an enable signal including enable events responsive to the power converter output.