|| List of recent Enable Signal-related patents
|Timing synchronization circuit with loop counter|
An apparatus for synchronizing an output dock signal with an input clock signal includes a first timing synchronization circuit, control logic, and a counter. The first timing synchronization circuit is operable to generate a delay to synchronize a reference clock signal representative of the input clock signal with a feedback dock signal representative of the output clock signal responsive a strobe signal.
|Memory controller for strobe-based memory systems|
An integrated circuit (ic) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal.
|Method for operating a network system|
The invention relates to a method for operating a network system (2) having at least one client device (4.1, 4.2), at least one management device (16) and at least one printing device (14), comprising: provision of a first order from the client device (4.1, 4.2) for execution by the at least one printing device (14), storage of the order in a memory device (10.1, 10.2) of the client device (4.1, 4.2), transmission of an order request from the client device (4.1, 4.2) to the management device (16), wherein the order of execution of orders is managed by the management device (16), transmission of requests from the client device (4.1, 4.2) to the management device (16) at first prescribable intervals of time to determine whether the printing device (14) is available for executing the order from the client device (4.1, 4.2), and transmission of an enable signal from the management device (16) to the client device (4.1, 4.2) in response to the request from the client device (4.1, 4.2) when the printing device (14) is available for executing the order from the client device (4.1, 4.2).. .
|Display interface that compresses/decompresses image data, method of operating same, and device including same|
A source driver integrated circuit (ic) includes a logic circuit configured to receive a transmission data packet including data, a compression code indicating compression or non-compression of the data, and a clock signal, to interpret the compression code, and to generate a sleep mode enable signal based on an interpretation result, and a clock signal recovery circuit configured to enable one of a voltage-controlled delay line and a voltage-controller oscillator in response to the sleep mode enable signal.. .
|Electronic device, indication electronic device and data transmission method|
The present invention provides an electronic device including a display, an input detection module and a processor. The input detection module detects an operation on the display executed by an indication electronic device, and generates a first operation signal corresponding to location information of the operation.
|Clock signal generator module, integrated circuit, electronic device and method therefor|
A clock signal generator module arranged to generate at least one clock signal for at least one functional module is described. The clock signal generator module comprises a first clock source component associated with at least one functional module, at least one further clock source component associated with the at least one functional module, and at least one management unit arranged to controllably enable signal generation by the first and at least one further clock source components in accordance with at least one operating characteristic of the at least one functional module associated therewith..
|Method and apparatus for battery control|
Generally, a system and a method for controlling a battery to power a load disable battery discharge if a battery voltage is less than a low voltage. Disabling battery discharge inhibits current flow from the battery to the load.
|Data transfer operation completion detection circuit and semiconductor memory device provided therewith|
A data transfer operation completion detection circuit including a first counter for performing a shifting operation in response to the generation of a read initiation signal, a second counter for performing a shifting operation in response to the generation of a burst completion signal, and an sr latch circuit for generating a read enable signal in response to the burst completion signal being generated when the count value of the first counter matches the count value of the second counter. The completion of a read operation or another data transfer operation is thus detected based on a read initiation signal reception history; therefore, it is possible to detect whether all read operations are complete at a given time even if a new read command is received while a read operation or the like is in progress..
|Asynchronous fifo buffer for memory access|
An asynchronous fifo buffer that provides data in response to requests to read a memory array is disclosed. The asynchronous fifo buffer provides the data output within a latency tolerance.
|Pulse generator circuit|
A pulse generator circuit is disclosed that is optimized for printed, solution-processed thin film transistor processing. In certain embodiments, the circuit comprises dual thin film transistors that operate as a diode and resistor, respectively.
|Nonvolatile memory device, read method for nonvolatile memory device, and memory system incorporating nonvolatile memory device|
A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read data after the strobe signal is toggled a predetermined number of times.. .
|Emulated current ramp for dc-dc converter|
A voltage converter (fig. 4) for a power supply circuit is disclosed.
|Interconnections for plural and hierarchical p1500 test wrappers|
A test architecture accesses ip core test wrappers within an ic using a link instruction register (lir). An ieee p1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper.
|Display circuitry with reduced pixel parasitic capacitor coupling|
A touch screen display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor (tft) layer.
|Baseband video data transmission device and reception device, and transceiver system|
In a transmission device (2): a controller (2a) performs a control of reading, from information regarding video specification, first information indicating whether a reception device is capable of intermittent reception of receiving a video signal at a timing that causes certain number of frames to be intermittent, and, when the reception device can perform intermittent reception, multiplexing, to the video signal during a blanking period of the video signal to be updated, an enable signal indicating the present video signal is to be enabled and second information indicating that transmission of the video signal will not resume unless the video signal is updated; and a transmitter (2d) transmits the video signal that is to be updated and then does not resume transmission of the video signal unless the video signal is updated.. .
|Led driving device, illuminator, and liquid crystal display device|
The present invention provides a light emitting diode (led) driving device as a semiconductor device, which comprises: a direct current/direct current (dc/dc) controller, for controlling an output segment that is used to generate an output voltage from an input voltage and supply the output voltage to an led; an output current driver, for generating an output current of the led; and an led short-circuit detection circuit, for monitoring a cathode voltage of the led to perform an led short-circuit detection, wherein the led short-circuit detection circuit controls whether an action is performed or not according to a short-circuit detection enable signal input from outside the led driving device.. .
|Pulsed current sensing|
A system and method are provided for sensing current. A current source is configured to generate a current and a pulsed sense enable signal is generated.
|Predictive current sensing|
A system and method are provided for estimating current. A current source is configured to generate a current and a pulsed sense enable signal is generated.
|Memory module and memory system comprising same|
A memory module comprises a plurality of semiconductor memory devices each comprising a mode register set (mrs) circuit configured to generate an enable signal corresponding to an error mode of the semiconductor memory device in response to an mrs command received from a command decoder, and an address buffer configured to store a predetermined address signal, to receive an address signal and corresponding data from an external device, and to compare the address signal received with the predetermined address signal in response to the enable signal. As a consequence of determining that the address signal received from the external device is the same as the predetermined address signal stored in the address buffer, data different from the corresponding data received from the external device is written to a memory cell corresponding to the predetermined address signal..
|Methods, apparatuses, and circuits for bimodal disable circuits|
Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles.
|Current-parking switching regulator downstream controller pre-driver|
A system and method are provided for generating non-overlapping enable signals. A peak voltage level is measured at an output of a current source that is configured to provide current to a voltage control mechanism.
|Apparatus and methods for biasing a power amplifier|
Apparatus and methods for biasing a power amplifier are disclosed. In one embodiment, a method of biasing a power amplifier includes shaping an enable signal using a time-dependent signal generator to generate a control current, amplifying the control current using a current amplifier to generate a correction current, and generating a bias current for a power amplifier using a primary biasing circuit.
|Margin free pvt tolerant fast self-timed sense amplifier reset circuit|
In described embodiments, a circuit for providing a margin free pvt tolerant fast self-timed sense amplifier reset includes a sense amplifier coupled between a complementary pair of first and second bitlines in a memory cell, a first and second pmos drivers connected to internal nodes of the sense amplifier, respectively, and outputting a first and second output signals, wherein the second output signal is inverted by an inverter to form an inverted output signal, a read detect block receiving the first and inverted output signals and generating a transition detect signal that is latched by a cross-coupled inverters and employed to generate a sense amplifier enable signal with a global sense amplifier enable signal, and a push-pull logic formed by a nmos and a pmos in series to generate an output of the circuit.. .
|Conversion circuit, image processing device, and conversion method|
A conversion circuit includes: a conversion section configured to convert each of analog pixel signals into digital pixel data; a timing acquisition section configured to acquire specified timing, in which the specified timing defines a display period during which display of each of the analog pixel signals is performed in a cycle of a synchronization signal; a timing setting section configured to set timing that defines an extension period that is longer than the display period, in which the timing is other than the specified timing; an enable signal generation section configured to generate an enable signal, in which the enable signal indicates the extension period as a period during which the digital pixel data is valid; and an output section configured to output the digital pixel data that is valid, in accordance with the enable signal.. .
|Power managed synchronizers for asynchronous input signals|
Clock-gated synchronizer circuitry includes a number of clock-gated synchronizers, with each clock-gated synchronizer configured to synchronize an asynchronous input signal into a clock domain. The circuitry also includes a clock gater coupled to a clock input of the plurality of clock-gated synchronizers and coupled to receive an input clock and an enable signal.
|Light emitting device power supply circuit, light emitting device control circuit and identifiable light emitting device circuit therefor and identification method thereof|
The present invention discloses a light emitting device power supply circuit, a light emitting device control circuit and an identifiable light emitting device circuit therefor, and an identification method thereof. The light emitting device control circuit includes an operation signal generation circuit and an identification circuit.
|Redundancy circuit and semiconductor memory device including the same|
A redundancy circuit includes a redundancy decoder, a fuse array, and a decoder. The redundancy decoder decodes a redundancy enable signal generated when an address of a defective cell matches an input address.
|On chip electrostatic discharge (esd) event monitoring|
An approach for monitoring electrostatic discharge (esd) event of an integrated circuit. The approach includes a canary device for exhibiting an impedance shift when affected by an esd pulse, wherein circuit drain of the canary device is connected to an input terminal of the circuit structure.
|Data bus synchronizer|
A data bus synchronizer includes a plurality of registers arranged in a cascade, configured to generate a synchronized output in response to sampling an asynchronous bus without an enable signal, where the plurality of registers receive a value on the asynchronous bus. A last register of the plurality of registers is configured to generate the synchronized output in response to a load enable signal.
|Method and system for coexistence of multiple collocated radios|
An apparatus may include a set of transceivers comprising three or more transceivers each operable to communicate via a wireless communications standard different from each other transceiver and a driver to output an enable signal when a first transceiver of the set of transceivers is active. The apparatus may also include a processor circuit and a real-time frame synchronization module operable on the processor circuit to receive a first frame synchronization input signal to delineate first receive and first transmit periods of a radio frame of a first transceiver of the set of transceivers, and to generate a frame synchronization signal to align receive and transmit periods of each of a multiplicity of additional transceivers of the set of transceivers to the respective first receive and first transmit periods of the first transceiver.
|Semiconductor integrated circuit and method of driving the same|
A semiconductor integrated circuit includes a fuse circuit comprising a fuse configured to generate a fuse state signal corresponding to a rupture state of the fuse in response to an enable signal, a fuse state decision unit configured to determine whether or not the fuse state signal is normal based on a test signal, and generate an output enable signal according to a determination result, and a driving unit configured to output the fuse state signal in response to the output enable signal.. .
A display device includes a data driver having i data output terminals (i being a natural number greater than 1) and outputting data voltages to the i data output terminals in accordance with a source output enable signal provided from a timing controller, an output controller connected between the i data output terminals and i data lines, and i garbage switches respectively connected to the i data lines and connecting the i data lines to a ground terminal at a power input timing when a power supply voltage is applied to the display device, and interrupting the connection between the i data lines and the ground terminal at a timing later than an output timing of a first source output enable signal provided from the timing controller after the power input timing.. .
|Low clock-power integrated clock gating cell|
In an integrated clock gating (icg) cell a latch is coupled to a nor gate. The nor gate receives an enable signal.
|Automatic input impedance control|
The present disclosure is directed to an input impedance control circuit. In one embodiment, the automatic input impedance control circuit includes a circuit controller that comprises a module for calculating an impedance and a control logic module, wherein the control logic module provides a current enable signal and a current control output signal, a driver in communication with the circuit controller for receiving the current enable signal and the current control output signal, an input voltage sensing circuit in communication with the module for calculating the impedance and the control logic module and an input current sensing circuit in communication with the module for calculating the impedance..
|Display device and method for processing frame thereof|
A display device and a method for processing frame are provided. The display device includes a display panel, a source driver, a gate driver, a timing controller and a frame processing module.
|Gate driving circuit, display module and display device|
Provided are a gate driving circuit, a display module and a display device belonging to the field of display technique and being designed for solving the problem of high power consumption of the display module in the prior art. The gate driving circuit is used for driving gates of tfts corresponding to gate lines connected thereto, and includes at least two stages of shift registers connected in cascade, wherein each stage of shift register includes a first output terminal and a second output terminal, the first output terminal is connected to an enable signal input terminal of a next stage of shift register so as to output a next stage enable signal to the next stage of shift register, and the second output terminal is connected to a corresponding gate line so as to apply a gate driving signal on the gates of tfts through the corresponding gate line..
|Scan flip-flop, method of operating the same, and device including the scan flip-flop|
A scan flip-flop may include a selector outputting a data signal or a scan input signal in response to a scan enable signal, and a flip-flop that latches an output signal of the selector or the data signal, based on a clock signal and a low voltage signal.. .
|Clock generation circuit and clock generation system using the same|
A clock generation circuit includes a counting code generation unit configured to generate counting codes corresponding to a frequency of an input clock when an enable signal is enabled; a control code generation unit configured to decode the counting codes and generate control codes; and a cycle changeable oscillation unit configured to determine a frequency of an output clock in response to the control codes.. .
|Memory array voltage source controller for retention and write assist|
A voltage source controller for a memory array includes an input coupled to a voltage source, an output coupled to one or more memory cells of a memory array, where the output is configured to provide a cell source voltage to the memory cells. The controller also includes a switch circuit configured to: receive a retention enable signal, a write assist enable signal, and a standard mode enable signal; and based on the retention enable signal, write assist enable signal, and standard mode enable signal, selectively set the cell source voltage for one or more of the memory cells to one of: a retention voltage, a write assist voltage, or a standard mode voltage, where the retention voltage and the write assist voltage are less than the standard mode voltage..
|Pulse generator and ferroelectric memory circuit|
A pulse generator circuit with ferroelectric memory element is disclosed that is optimized for printed, solution-processed thin film transistor processing. In certain embodiments, the circuit comprises dual thin film transistors that operate as a diode and resistor, respectively.
|Fuse repair device|
A fuse repair device may include a first fuse circuit configured to store a first portion out of a failed address, a second fuse circuit configured to store a multipurpose information or a second portion of the failed address, an enable control circuit configured to provide a first enable signal to enable the second fuse unit based on a first control signal, a switch control circuit configured to provide a second enable signal to enable the second fuse unit based on a second control signal, a repair control signal generation circuit configured to compare data stored in the first fuse circuit and the second fuse circuit with an input address, and generate a repair control signal based on the first enable signal and the second enable signal, and a multipurpose control signal generation circuit configured to generate a multipurpose control signal to control operations different from a repair operation.. .
|Data processing device and method|
A data processing device includes a clock converter, a data converter, ad an error detector. The clock converter is configured to receive a first clock signal, convert the first clock signal into a second clock signal, and output the second clock signal.
|Electronic device and reset circuit|
A reset circuit is connected to a processor chip to reset the processor chip. The reset circuit includes a control unit, a standby power, and a voltage converting unit.
|Methods and apparatus for improving backlight driver efficiency|
An electronic device may be provided with display circuitry that includes a display timing controller, a backlight driver, a light source, and other associated backlight structures. The backlight control circuitry may generate a control signal having an adjustable duty cycle to the backlight driver.
|High fill-factor image sensor architecture|
An image sensor architecture is implemented within an image sensor system. Image sensor pixels include pixel regions, and each pixel region includes a photosensor, a reset circuit, and a readout circuit.
|Semiconductor memory device, system having the same and method for generating reference voltage for operating the same|
A semiconductor memory device and a method for generating a reference voltage needed for operating the same are disclosed. The semiconductor memory device includes a first decoder configured to generate a default set signal in response to a reset signal and a clock enable signal, a second decoder configured to generate a reference voltage set signal in response, and a reference voltage provider configured to generate an internal reference voltage..
The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact.
|Scan test circuitry with control circuitry configured to support a debug mode of operation|
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains each having a plurality of scan cells.
|Nonvolatile memory and method of operating nonvolatile memory|
A nonvolatile memory includes multiple banks, control logic and multiple read and write (rw) circuits. Each bank includes multiple memory cells.
|Memory interface circuitry with improved timing margins|
Integrated circuits may include memory interface circuitry that communicates with memory. The memory interface circuitry may include latch circuitry that receives a data strobe enable signal from the memory controller and latches the data strobe enable signal using a data strobe signal received from the memory.
|Semiconductor storage device and control method thereof|
According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals.
|Strobe acquisition and tracking|
A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal.
|Control device and light source device|
A control device adapted to control a first light-emitting diode and a second light-emitting diode, includes a first logic operation unit receiving a first enable signal and a second enable signal to generate a first logic signal, a second logic operation unit receiving the first and second enable signals to generate a second logic signal, a first adjustment unit generating a first adjustment signal according to the first logic signal, a second adjustment unit generating a second adjustment signal according to the second logic signal, a first control unit outputting a first control signal to the first light-emitting diode according to the first enable signal and the first adjustment signal, and a second control unit outputting a second control signal to the second light-emitting diode according to the second enable signal and the second adjustment signal. The first logic signal and the second logic signal are complementary..
|Energy management system|
The present invention relates to an energy management system comprising an energy storage, a control system and a power converter supplying power to a load. The energy storage is arranged in individual energy units and the power converter is provided with a switching system for controlling the voltage over the load.
|Data communication apparatus and control method|
A data communication apparatus includes a data generation unit, a control register, a memory, a memory address generation unit, a failure setting unit, and a transmission unit. The data generation unit generates data.
|Voltage generation circuit of semiconductor memory apparatus|
A voltage generation circuit of a semiconductor memory apparatus includes a plurality of pumping units configured to provide voltages to an output node; a sensing unit configured to sense a voltage level of the output node and generate a pumping enable signal; an oscillator configured to generate an oscillator signal in response to the pumping enable signal; and a control unit configured to selectively output the oscillator signal to the plurality of pumping units in response to an active signal, a power-up signal and a mode register set signal.. .
|Memory with output control|
An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device.
|Non-volatile memory device and method of operating|
A method of operating a non-volatile memory includes; during power-on, reading control information from an information block and lock information from an additional information block, then upon determining that a secure block should be locked, generating a lock enable signal that inhibits access to data stored in the secure block, and a read-only enable signal that prevents change in the data stored in the additional information block.. .
|Power line lowering for write assisted control scheme|
Some embodiments of the present disclosure relate to a memory array having a cell voltage generator configured to provide a cell voltage header to a plurality of memory cells. The cell voltage generator is connected to the memory cells by way of supply voltage line and controls a supply voltage of the memory cells.
|Three-dimension image format converter and three-dimension image format conversion method thereof|
A three-dimension (3d) image format converter and a 3d image format conversion method thereof are provided. The 3d image format converter includes an input circuit, a processing circuit and an output circuit.
|Display device and method of compensating for data charge deviation thereof|
A display device includes a display panel including data lines, a source driver positioned at one side of the display panel, and a timing controller which sequentially stores digital video data in a plurality of line memories, starts to generate an output data enable signal in conformity with a first writing start timing of a last line memory of the line memories, adjusts a pulse width of the output data enable signal of each horizontal pixel line based on a previously determined charge time graph, reads out the digital video data from the line memories in synchronization with rising edges of the output data enable signal, and generates a source output enable signal having the same pulse width each time each line memory finishes reading out the data.. .
|Motion detection circuit and motion detection method|
A motion detection method is adapted for an image display circuit including a motion detection circuit and an arbitration circuit. In this motion detection method, a number of motion quality observation windows are defined.
|High-precision led control circuit, method and led driver thereof|
In one embodiment, a light-emitting diode (led) driver can include: (i) a reference voltage control circuit configured to provide a reference voltage signal in response to an enable signal; (ii) a current control circuit configured to control an output current of the led driver in response to the reference voltage signal; and (iii) the led driver being configured to drive an led load when the enable signal is active.. .
|Platform and launch initiation system for secondary spacecraft for launch vehicle|
A platform and launch initiation control system for secondary spacecraft for a launch vehicle includes an aluminum honeycomb core sandwiched between top and bottom structural aluminum skins and strengthened by a spider-like stiffener. Spool inserts for engaging the secondary spacecraft are arranged on the platform.
|Flip-flop circuit having a reduced hold time requirement for a scan input|
A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels.
|Setting information storage circuit and integrated circuit chip including the same|
A setting information storage circuit includes first decoders configured to generate first input enable signals, respectively, in response to selection codes and a first set signal, first register sets configured to correspond to the first decoders, respectively, and to receive setting data when first input enable signals generated from the first decoders corresponding to the first register sets, respectively, are enabled, and store the received setting data, a second decoders configured to generate a second input enable signals, respectively, in response to the selection codes and a second set signal, and a second register sets configured to correspond to the second decoders, respectively, and to receive the setting data when second input enable signals generated from the second decoders corresponding to the second register sets, respectively, are enabled, and store the received setting data.. .
|Switched averaging error amplifier|
A signal averaging circuit includes a plurality of switched weighted current sources to generate a total amount of charge. The total amount of charge is representative of a weighted sum of a plurality of input signal samples during an active period of a read enable signal.
|Method and apparatus for digital control of a switching regulator|
An on/off controller device includes a control circuit to generate a control signal to switch a power switch between an on state and an off state to transfer energy from a primary side to a secondary side of a switched mode power supply. A comparator is coupled to generate an enable signal that enables and disables the switching of the power switch by the control circuit.
|Display device and method of operating the same|
A display device is provided which includes a display panel including a plurality of pixels connected with a plurality of gate lines and a plurality of data lines; a gate driving unit configured to drive the plurality of gate lines; a data driver configured to drive the plurality of data lines; and a timing controller configured to generate a plurality of control signals for controlling the gate driving unit and the data driver in response to externally provided clock signal and data signals. The timing controller converts the data signals into an image data signal, a horizontal synchronization signal, a vertical synchronization signal, and a data enable signal, a pulse width of each of the horizontal and vertical synchronization signals corresponding to an aspect ratio of the data signals or a size of a black image display area.
|Systems and methods for interfacing between hard logic and soft logic in a hybrid integrated device|
Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules.
|Core circuit test architecture|
A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths.