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 Demodulator for near field communication, near field communication device, and electronic device having the same patent thumbnailnew patent Demodulator for near field communication, near field communication device, and electronic device having the same
A demodulator for a near field communication (nfc) includes a first rectifier, a shifting rectifier, a field monitor and an edge detector. The first rectifier receives an antenna voltage through a first power terminal and a second power terminal, rectifies the antenna voltage and provides a first rectified signal to a first node.
Samsung Electronics Co., Ltd.


 Semiconductor device and  controlling the semiconductor device patent thumbnailnew patent Semiconductor device and controlling the semiconductor device
A semiconductor device includes: a clock synchronizing circuit that operates in synchronization with a clock; an enable signal generating circuit that generates an enable signal in an operation period during which the clock synchronizing circuit is operated; and a clock supplying circuit that supplies a clock to the clock synchronizing circuit or stop the supply of the clock according to the enable signal when a clock frequency is equal to or lower than a predetermined frequency, and supply a clock to the clock synchronizing circuit, irrespective of the enable signal, when the clock frequency is higher than the predetermined frequency.. .
Fujitsu Limited


 Power control device and method thereof patent thumbnailnew patent Power control device and method thereof
An embodiment relates to a power control device and a technology capable of stably supplying power when an electrical fuse boots up. The power control device includes a power supply unit, a power driving unit, and an electrical fuse unit.
Sk Hynix Inc.


 Semiconductor memory device and i/o control circuit therefor patent thumbnailnew patent Semiconductor memory device and i/o control circuit therefor
An i/o control circuit, includes a mode setting unit configured to generate a first mode signal, a second mode signal, a third mode signal, and a fourth mode signal in accordance with one of a plurality of i/o option modes, a first control signal generation unit configured to generate a first mode determination signal and a first control signal enable signal in response to the first i/o option signal and the first mode signal, and a second control signal generation unit configured to generate a second control signal enable signal, a third control signal enable signal, and a fourth control signal enable signal in response to a second i/o option signal, the first mode determination signal, the second mode signal, the third mode signal, and the fourth mode signal.. .
Sk Hynix Inc.


 Clock generation device and semiconductor device including the same patent thumbnailnew patent Clock generation device and semiconductor device including the same
A clock generation device and a semiconductor device including the same are disclosed, which may tune an internal clock to a desired frequency. The clock generation device may include an oscillator configured to tune an oscillation signal in response to a tuning signal, and adjust a period of an internal clock.
Sk Hynix Inc.


 Particle beam therapy device patent thumbnailParticle beam therapy device
A device controller controls an acceleration-related devices and an extraction-related devices of an accelerator for accelerating and extracting a particle beam, in such a way that the controller checks, at a time point when receiving a master clock pulse, that preparation for operating the acceleration-related devices is completed and then commands the acceleration-related devices to operate in accordance with an operation pattern corresponding to a prescribed energy of the particle beam, and commands the acceleration-related devices to operate in accordance with an extracting operation pattern when an extraction enable signal indicating that the particle beam reaches the prescribed energy is turned on and an extraction-related device setting-status signal indicating that completion of setting the extraction-related devices for the prescribed energy is on.. .
Mitsubishi Electric Corporation


 Inverter, in particular as part of a power generation network, and method patent thumbnailInverter, in particular as part of a power generation network, and method
An inverter for converting dc power of a generator into grid-conforming ac power includes an inverter bridge circuit and a scanning circuit configured to trace at least one part of a characteristic curve of the generator to determine an mpp power value (pmpp). The scanning circuit is configured, in the case of a derating to a derated power (pred), to trigger a tracing of the characteristic curve with provision of a first power profile deviating from the derated power (pred) if an enable signal is present at the inverter, and to indicate a start and an end of the tracing by outputting a start signal and an end signal, respectively.
Sma Solar Technology Ag


 A driving power supply  oled patent thumbnailA driving power supply oled
The present invention discloses a driving power supply apparatus for oled. Wherein it comprises a power board connecting to a motherboard and a oled screen, the motherboard comprises a standby circuit, a timing control module, a first and second transformer modules and a pfc circuit, the standby circuit connects to the timing control module and the motherboard, the timing control module connects to the pfc circuit, the motherboard and the first and second transformer modules, which connect to the motherboard and the pfc circuit.
Shenzhen Skyworth-rgb Electronic Co., Ltd


 On-die termination enable signal generator, semiconductor apparatus, and semiconductor system patent thumbnailOn-die termination enable signal generator, semiconductor apparatus, and semiconductor system
A semiconductor apparatus may include an on-die termination (odt) enable signal generator configured to enable an odt enable signal in response to a data strobe signal, or enable the odt enable signal in response to a command latch enable signal and an address latch enable signal. The semiconductor apparatus may include an odt circuit configured to perform an odt operation in response to the odt enable signal..
Sk Hynix Inc.


 Memory controller for strobe-based memory systems patent thumbnailMemory controller for strobe-based memory systems
An integrated circuit (ic) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal.
Rambus Inc.


Add-on device and server using the same

An add-on device includes an interface, an identification module, an enable module, and a function module. The identification module is used to output an identification signal.
Hon Hai Precision Industry Co., Ltd.

Integrated circuit and electronic apparatus including integrated circuit

An integrated circuit and an electronic apparatus including the same. The electronic apparatus includes a scan input processing circuit, a selection circuit and a scanning circuit.
Samsung Electronics Co., Ltd.

Voltage generator with charge pump and related methods and apparatus

Aspects of this disclosure relate to voltage generators, such as negative voltage generators. In certain configurations, a negative voltage generator includes a charge pump controllable by a clock signal and configured to provide a negative voltage at an output node, an oscillator configured to activate based on an enable signal and to provide the clock signal to the charge pump, a comparator configured to generate the enable signal based on comparing a feedback voltage with a reference value, a voltage divider electrically connected between a positive voltage node and the output node and configured to generate the feedback voltage at a feedback node, and a start-up capacitor electrically connected between the positive voltage node and the feedback node and configured to control a settling time of the feedback voltage..
Skyworks Solutions, Inc.

Envelope tracking power converter

A tracking power converter for a radio frequency power amplifier includes a boost converter circuit, a switching network circuit, a filter circuit, and a controller circuit. The boost converter circuit provides a boosted voltage in response to a battery voltage.
Adx Research, Inc.

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a first memory cell array including a first memory cell having a variable resistive element, a second memory cell array including a second memory cell having the variable resistive element, a reference signal generation circuit which generates a reference signal, a sense amplifier having a first input terminal and a second input terminal, and a read enable control circuit which generates a read enable signal in accordance with a command from outside and control switching between a single cell read mode and a twin cell read mode.. .
Kabushiki Kaisha Toshiba

Video signal transmission apparatus

The video signal transmission apparatus according to the present disclosure transmits a pixel clock, signals, and image data which all are supplied from a video signal source. The signals include a vertical synchronizing signal, a horizontal synchronizing signal, a data enable signal, and a field signal.
Panasonic Intellectual Property Management Co., Ltd.

Clock gating circuit that operates at high speed

A clock gating circuit includes a first precharge unit charging a first node based on a clock signal, a second precharge unit charging a second node based on the clock signal, a first discharge unit discharging the first node based on the clock signal, a second discharge unit discharging the second node based on the clock signal, a first cross-coupled maintain unit maintaining the first node at a charge state according to a voltage level of the second node, a second cross-coupled maintain unit maintaining the second node at a charge state according to a voltage level of the first node, and a control unit controlling the first and second discharge units to discharge the first node or the second node on the basis of a clock enable signal.. .
Samsung Electronics Co., Ltd.

Self repair device and method thereof

A self repair device may include: an electrical fuse array configured to store bit information of a failed address in a fuse; an electrical fuse controller configured to store a row address or column address corresponding to a failed bit when a failure occurs, generate a repair address by comparing a failed address inputted during a test to the address stored therein, output a rupture enable signal for controlling a rupture operation of the electrical fuse array, and output row fuse set data or column fuse set data in response to the failed address; and a row/column redundancy unit configured to perform a row redundancy or column redundancy operation in response to the row fuse set data or the column fuse set data applied from the electrical fuse array.. .
Sk Hynix Inc.

Sense amplifier driving device and semiconductor device including the same

An embodiment relates to a sense amplifier driving device for stabilizing bit line precharge power when a post-overdriving operation is performed. The sense amplifier driving device includes a power driving unit configured to supply a first pull-up voltage and a pull-down voltage to a pull-up power line and a pull-down power line during a post-overdriving period and a driving signal generation unit configured to generate a pull-up driving signal and a pull-down driving signal activated during the post-overdriving period in order to control the driving of the power driving unit.
Sk Hynix Inc.

Display device and driving the same

A display device includes a buffer connected to a data line of a display panel, a bias-mode verification unit which generates a bias-mode signal based on an nth image data signal and an mth image data signal (“m” is a natural number smaller than “n”) corresponding to the data line, a data selecting unit which selects one of a plurality of bias enable signals having different duty ratios from one another based on the bias-mode signal, a control signal generating unit which generates a switching control signal based on the bias enable signal selected by the data selecting unit, and a bias control unit which applies, to the buffer, at least one of a plurality of bias control signals having different levels from one another in an output period defined by the switching control signal.. .
Samsung Display Co., Ltd.

Scan driver, organic light emitting diode display device and display system including the same

A scan driver of an organic light emitting diode (oled) display device includes a plurality of sequentially-connected stages each connected to a plurality of pixels through a plurality of first-scan lines and a plurality of second-scan lines. Each stage of the sequentially-connected stages includes a common driver and a sub-driver unit.
Samsung Display Co., Ltd.

Input/output (i/o) line test device and controlling the same

An input/output (i/o) line test device and a method for controlling the same are disclosed, which may relate to a technology for testing a base die having no cell using various patterns. The i/o line test device may include an interface controller configured to perform signal transmission/reception between a pad and an input/output line (iol), and a signal transceiver configured to perform signal transmission/reception between the iol and a through silicon via (tsv).
Sk Hynix Inc.

Programming verification control circuit and control thereof

A programming verification control circuit is disclosed, including: a first decoder circuit for decoding a word line of a memory bit; a first drive circuit for receiving a first voltage and providing the first voltage to the word line of the memory bit based on a decoding result of the first decoder circuit; a second decoder circuit for decoding a control gate of the memory bit; a second drive circuit for receiving a second voltage and providing the second voltage to the control gate of the first memory bit based on a decoding result of the second decoder circuit; and a voltage equalizer for receiving the first voltage, the second voltage and a first enable signal and, in event of the first enable signal being valid, controlling the first voltage and the second voltage to be conducted. A method for controlling the programming verification control circuit is also disclosed..
Shanghai Huahong Grace Semiconductor Manufacturing Corporation

Display device with trace loss compensation function

A display device including a plurality of scan lines and a scan driver is provided. The scan driver is coupled to the scan lines each being coupled to a plurality of pixels.
Innolux Corporation

Multi-mode led illumination system

This application discloses a lighting emitting diode (led) illumination system that operates at least in a boost mode and a bypass mode. The led illumination system includes a plurality of leds and bypass elements.
Google Inc

Differential circuit and image sensing device including the same

A differential circuit includes a differential selection block suitable for generating differential selection signals corresponding to differential input signals in response to an enable signal and a differential loading block suitable for loading differential output signals corresponding to the differential input signals on differential lines in response to the differential selection signals.. .
Sk Hynix Inc.

Reception circuit, adjusting timing in reception circuit, and semiconductor device

A reception circuit includes a control signal generation circuit that generates a first enable signal based on a strobe signal and a second enable signal based on a core clock signal and a pointer control signal. A pattern data generation circuit generates determination pattern data from the first enable signal.
Socionext Inc.

Charging circuit interrupt devices with self-test and methods thereof

A charging circuit interrupting device for applying an input voltage provided by first and second input power lines of a power system to first and second output power lines of an output system includes a current-detecting unit, a self-test device, and a controller. The current-detecting unit executes a leakage-detection function and generates a leakage signal when the current difference between the first and second power lines is detected.
Delta Electronics, Inc.

Voltage generator, semiconductor memory device having the same, and operating semiconductor memory device

A voltage generator that includes an operation mode determination circuit suitable for determining an active mode or a standby mode based on a chip enable signal to activate an active mode signal or a standby mode signal according to a result of the determination; and a bulk voltage generation circuit outputting a bulk voltage having an internal power voltage when the active mode signal is activated, and outputting the bulk voltage having an external power voltage when the standby mode signal is activated.. .
Sk Hynix Inc.

Low power input gating

Various implementations described herein are directed to an integrated circuit for implementing low power input gating. In one implementation, the integrated circuit may include a chip enable device configured to receive and use a clock input signal to toggle a control input of memory based on a chip enable signal.
Arm Limited

Scan flip-flop circuit with dedicated clocks

In one form, a scan flip-flop includes a clock gating cell and a dedicated clock flip-flop. The clock gating cell provides an input clock input signal as a scan clock signal when a scan shift enable signal is active, and provides the input clock signal as a data clock signal when the scan shift enable signal is inactive.
Advanced Micro Devices, Inc.

System for a transducer system with wakeup detection

According to embodiments described herein, a circuit includes an interface circuit configured to be coupled to a transducer and a detection circuit. The interface circuit is configured to provide a digital output signal to a signal input terminal of a processing circuit.
Infineon Technologies Ag

Method and system for safely switching off an electrical load

A method and system for safely switching off an electrical load in a system comprising a multi-channel control unit, a single-channel data transmission path and an output unit having a first processing unit, a second processing unit and safe outputs. The method comprises receiving and evaluating an input signal by the multi-channel control unit and generating an enable signal based on the evaluation; transmitting the enable signal to the output unit via the single-channel data transmission path; receiving the enable signal by the first processing unit and generating an output signal based on the enable signal; providing at least one part of the enable signal from the first processing unit to the second processing unit for evaluation therewith; generating a dynamic clock signal by the second processing unit based on the enable signal; and controlling the safe outputs based on the output signal and the dynamic clock signal..
Pilz Gmbh & Co. Kg

Semiconductor memory apparatus

A semiconductor memory apparatus may include a decoding unit configured to enable one of a plurality of sub word line driver enable signals by decoding a plurality of addresses while the decoding unit operates in a normal mode, and enables specific sub word line driver enable signals among the plurality of sub word line driver enable signals regardless of the plurality of addresses while the decoding unit is operating in a test mode. The semiconductor memory apparatus may include a sub word line driver group configured to include a plurality of sub word line drivers, the plurality of sub word line drivers configured for activation in response to the plurality of sub word line driver enable signals.
Sk Hynix Inc.

Semiconductor storage device and control method thereof

According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals.
Kabushiki Kaisha Toshiba

Semiconductor device

There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an sram memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation.
Renesas Electronics Corporation

Memory subsystem and computer system

A method including estimating an access request frequency from a cpu to a memory subsystem by counting a number of cpu access requests and a number of requests other than cpu access requests, wherein the cpu is connected to the memory subsystem via a system bus, and the memory subsystem includes a memory controller connected to the system bus, and a ddr memory, including the estimated access request frequency with a predetermined threshold value stored in a register, generating a clock gate signal to decimate an operating clock of the memory controller in response to a result of comparing the estimated access request frequency with the predetermined threshold value, generating a dummy cycle signal to delay the timing of signal data output from the memory controller to the system bus, and generating a clock enable signal to decimate an operating clock of the ddr memory.. .
International Business Machines Corporation

Parallel test device and method

A parallel test device and method are disclosed, which relates to a technology for performing a multi-bit parallel test by compressing data. The parallel test device includes: a pad unit through which data input/output (i/o) operations are achieved; a plurality of input buffers configured to activate write data received from the pad unit in response to a buffer enable signal, and output the write data to a global input/output (gio) line; a plurality of output drivers configured to activate read data received from the global i/o (gio) line in response to a strobe delay signal, and output the read data to the pad unit; and a test controller configured to activate the buffer enable signal and the strobe delay signal during a test mode in a manner that the read data received from the plurality of output drivers is applied to the plurality of input buffers such that the read data is operated as the write data..
Sk Hynix Inc.

Extensible configurable fpga storage structure and fpga device

An extensible configurable fpga storage structure and an fpga device, where the fpga storage structure includes: a plurality of local storage units, a controller and two clock buffers, where the two clock buffers are separately used for providing different clock signals for two clock input ports of the controller; the controller is used for receiving a write address signal input externally, and driven by the clock signals, generating a plurality of enable signals and write address decoding signals to be output to the plurality of local storage units; and each of the local storage units includes a local memory and a multiplexer used for providing input data for the local memory; and, based on a configuration mode of each local storage unit, generates output data in the corresponding configuration mode according to the enable signals, input write address decoding signals or read address signals, and the input data.. .
Capital Microelectronics Co., Ltd.

Closed-loop brain stimulation generating stimulation voltage thereof

A closed-loop brain stimulation apparatus and a method for generating a stimulation voltage thereof are provided. The closed-loop brain stimulation apparatus includes a brain signal receiving apparatus, a controller and a stimulation voltage generator.
National Tsing Hua University

Phase-rotating phase locked loop and controlling operation thereof

A phase-rotating phase locked loop (pll) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating pll, the first and second loops configured to activate in response to an enable signal. The pll may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code..
Samsung Electronics Co., Ltd.

Circuits and methods for performance optimization of sram memory

In described examples, a memory controller circuit controls accesses to an sram circuit. Precharge mode control circuitry outputs: a burst mode enable signal to the sram circuit indicating that a series of sram cells along a selected row of sram cells will be accessed; a precharge first mode signal to the sram circuit indicating that a first access along the selected row will occur; and a precharge last mode signal to the sram circuit indicating that a last access along the selected row will occur.
Texas Instruments Incorporated

Compensation circuit, amoled structure and display device

The present invention relates to the field of display apparatus, more specifically, to a compensation circuit, an amoled structure and a display device. Said circuit comprises a plurality of pixel units, each for the plurality of pixel units includes at least one light emitter, and each of said pixel units comprises: an anode initialization signal interface, a cst initialization port, a data control port and an enable signal control port.
Everdisplay Optronics (shanghai) Limited

Display control device and display apparatus

A short delay time from imaging of an imaging element to displaying on a view finder is realized using a simple circuit configuration. An evf controller includes a serial i/f that receives a command including the number of valid lines of one frame, a counter that counts the number of lines of which an image signal becomes valid, a data input unit that inputs a valid image signal based on a data enable signal, a data output unit that outputs the input valid image signal to an evf, and a timing generation unit that compares a count value of the counter with the number of valid lines, detects an end of the input of the valid image signal in the frame based on a comparison result, and then starts a process for preparation for a next frame..
Seiko Epson Corporation

Method for authenticating a driver in a motor vehicle

The invention relates to a method for authenticating a driver (2) in a motor vehicle (1), having a detection device (10) which is arranged in the motor vehicle (1) and has the purpose of detecting actual data (50) of the driver (2) which is transmitted during the authentication to a checking device (20) which is arranged in an external station (3) outside the motor vehicle (1), wherein the checking device (20) compares the actual data (50) with setpoint data (60), and when the actual data (50) corresponds to the setpoint data (60) an enable signal (70) is transmitted from the external station (3) to the motor vehicle (1), as a result of which a starting process of the motor vehicle (1) for the driver (2) is made possible.. .
Huf HÜlsbeck & FÜrst Gmbh & Co. Kg

Phase-locked loop with lower power charge pump

Described is a phase-locked loop with lower power charge pump. The phase-locked loop comprises: a phase frequency detector to compare a reference clock and a feedback clock and generate a pulse based on the comparison, a charge pump to provide a charge signal corresponding to the pulse, a bias generator to provide biasing for the charge pump, wherein the bias generator is operable to receive a bias enable signal from the phase frequency detector and the bias generator is disabled when the bias enable signal is not asserted, a loop filter coupled to the output of the charge pump to provide a control signal responsive to the charge signal, and a voltage-controlled oscillator (vco), wherein the oscillating frequency of the vco is controlled by the control signal..
Intel Corporation

Data driver and driving the data driver

A data driver includes shift registers, sampling latches, holding latches, and a data sensing unit. The shift registers generate sampling pulses by shifting a source start pulse in response to a source sampling clock.
Samsung Display Co., Ltd.

Input voltage sensor responsive to load conditions

An ac-dc power converter controller includes a switch driver circuit coupled to generate a drive signal to control switching of a power switch to control a transfer of energy from an input of the power converter to an output of the power converter. An input sense circuit is coupled to receive an input sense signal representative of the input of a power converter.
Power Integrations, Inc.

Input/output buffer circuit

An input/output (i/o) buffer circuit includes an i/o unit and a protection circuit. The i/o unit selectively receives and outputs signals based on an enable signal.
Nuvoton Technology Corporation

Semiconductor apparatus

A semiconductor apparatus may include: a data storage group including first to eight data storage areas; a first channel select pad configured to transmit a first channel select signal to the first and third data storage areas; a second channel select pad configured to transmit a second channel select signal to the second and fourth data storage areas; a third channel select pad configured to transmit the first channel select signal to the sixth and eighth data storage areas; a fourth channel select pad configured to transmit the second channel select signal to the fifth and seventh data storage areas; a first clock enable pad configured to transmit a first clock enable signal to the first and third data storage areas; a second clock enable pad configured to transmit a second clock enable signal to the second and fourth data storage areas; a third clock enable pad configured to transmit the first clock enable signal to the fifth and seventh data storage areas; and a fourth clock enable pad configured to transmit the second clock enable signal to the sixth and eighth data storage areas.. .
Sk Hynix Inc.

Data compensation device and display device including the same

A data compensation device includes a current calculator which calculates an average current of each of blocks included in a pixel array based on an input data, a data enable signal, a horizontal synchronization signal and a vertical synchronization signal, a voltage drop info provider which provides a bus voltage drop information of predetermined bus points and an array voltage drop information of predetermined array points, the bus points being included in a power supply bus wiring which is connected to the pixel array, the array points being included in the pixel array, a data compensation circuit configured to provide a compensation data corresponding to the input data based on the average current, the bus voltage drop information and the array voltage drop information, and an adder configured to provide a compensation result data by adding the input data and the compensation data.. .
Samsung Display Co., Ltd.



Enable Signal topics:
  • Enable Signal
  • Control Unit
  • Electronic Device
  • Integrated Circuit
  • Semiconductor
  • Output Enable
  • Liquid Crystal
  • Liquid Crystal Display
  • Data Transfer
  • Buffer Circuit
  • Esd Protection Circuit
  • Protection Circuit
  • Electrostatic Discharge
  • Esd Protection
  • Programmable Memory


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