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Duc patents



      
           
This page is updated frequently with new Duc-related patent applications. Subscribe to the Duc RSS feed to automatically get the update: related Duc RSS feeds. RSS updates for this page: Duc RSS RSS


Semiconductor structures including fluidic microchannels for cooling and related methods

Soitec

Semiconductor structures including fluidic microchannels for cooling and related methods

Vertical channel-type 3d semiconductor memory device and method for manufacturing the same

Institute Of MicroelectronicsChinese Academy Of Sciences

Vertical channel-type 3d semiconductor memory device and method for manufacturing the same

Vertical channel-type 3d semiconductor memory device and method for manufacturing the same

Shenzhen China Star Optoelectronics Technology

Thin film transistor and method for manufacturing the same

Date/App# patent app List of recent Duc-related patents
06/25/15
20150181767
 Carrier module with bridging element for a semiconductor element patent thumbnailnew patent Carrier module with bridging element for a semiconductor element
Carrier module (1) for at least one semiconductor element (3) having a passively and/or actively cooled carrier (4) which has a positive carrier contact (5) and a negative carrier contact (6), with a device (2) for bridging the at least one semiconductor element (3) arranged on the carrier (4), comprising at least one first printed circuit board (7) with at least one bridging element (8), wherein at least one positive contact (9) which is electrically conductively connected to the positive carrier contact (5) and at least one negative contact (11) which is electrically conductively connected to the negative carrier contact (6) are provided on a first printed circuit board (7) and the bridging element (8) is electrically conductively connected to the positive contact (9) and to the negative contact (11) of the first printed circuit board (7), wherein the first printed circuit board (7) is thermally conductively and releasably connected to the carrier (4).. .
F.+s. Vermoegensverwaltungs Gmbh
06/25/15
20150181766
 Substrate and the method to fabricate thereof patent thumbnailnew patent Substrate and the method to fabricate thereof
The present invention discloses a substrate where the lateral surface of the substrate is formed to expose at least one portion of a via(s) for circuit connection. The substrate comprises a plurality of insulating layers; and a plurality of conductive layers separated by the plurality of insulating layers.
Cyntec Co., Ltd.
06/25/15
20150181739
 Electronic component module and an assembly including the same patent thumbnailnew patent Electronic component module and an assembly including the same
An electronic component module includes a board, a plurality of external terminals provided on a first surface of the board, and a first semiconductor chip provided on a region on the first surface surrounded by the plurality of external terminals. The first semiconductor chip more protrudes along a normal to the first surface than ends of the external terminals do..
Panasonic Corporation
06/25/15
20150181728
 Package for housing semiconductor element and semiconductor device patent thumbnailnew patent Package for housing semiconductor element and semiconductor device
A package for housing a semiconductor element includes a base body including a bottom plate section and a frame-shaped side wall section; and an input/output terminal provided so as to pass through the side wall section, the input/output terminal having a plate section on which line conductors are formed, and a vertical wall section which is fixed to the plate section so as to continue to the side wall section and so that the line conductors are sandwiched between the plate section and the vertical wall section and both ends of the line conductors are exposed from the vertical wall section. The vertical wall section has a thick section in a center portion of a side surface of the vertical wall section in a direction along the side wall section, the thick section having thick wall thickness, a lower end of the thick section being fixed to the plate section..
Kyocera Corporation
06/25/15
20150181725
 Thick film circuits with conductive components formed using different conductive elements and related methods patent thumbnailnew patent Thick film circuits with conductive components formed using different conductive elements and related methods
Disclosed herein are a variety of embodiments of thick film circuits with conductive components formed using different conductive elements and related methods for forming such circuits. One embodiment consistent with the present disclosure includes a multi-level thick film circuit formed on a substrate and having a first layer disposed on the substrate.
Gm Global Technology Operations Llc
06/25/15
20150181723
 Method of producing an electronic circuit with protection of the conductive layer patent thumbnailnew patent Method of producing an electronic circuit with protection of the conductive layer
The invention concerns a method of producing a circuit including the step consisting of connecting, to a bottom wall of a cavity, an electronic component with or without an intermediate wired link, the method including a step prior to an etching step which consists of depositing a layer of protective material on a conductive layer in the bottom of the cavity, said material being a liquid material capable of hardening and, once hardened, resistant to the etching solution.. .
Linxens Holding
06/25/15
20150181715
 Method for manufacturing touch panel patent thumbnailnew patent Method for manufacturing touch panel
A method for manufacturing a touch panel includes the following procedures. A first conductive layer and a shielding layer surrounding the first conductive layer are formed on a base plate.
Hon Hai Precision Industry Co., Ltd.
06/25/15
20150181712
 Semiconductor component with chip for the high-frequency range patent thumbnailnew patent Semiconductor component with chip for the high-frequency range
The invention relates to a semiconductor component with a chip, especially with a high-frequency switching circuit. The semiconductor component further comprises a metal body on the chip and a supplementary circuit board.
Rohde & Schwarz Gmbh & Co. Kg
06/25/15
20150181711
 Wiring substrate and light emitting device patent thumbnailnew patent Wiring substrate and light emitting device
Discoloration is suppressed in a wiring substrate including a conductive member including silver. A wiring substrate includes a ceramic layer and a conductive member including a conductive layer disposed on an upper surface of the ceramic layer.
Nichia Corporation
06/25/15
20150181708
 Semiconductor package module patent thumbnailnew patent Semiconductor package module
There is provided a semiconductor package module including: a substrate having one or more connection terminals formed thereon; first electronic components mounted on a first surface of the substrate; second electronic components mounted on a second surface of the substrate; and third electronic components formed on the substrate and including connection electrodes connecting the one or more connection terminals and external terminals to each other.. .
Samsung Electro-mechanics Co., Ltd.
06/25/15
20150181703
new patent

Wiring substrate and semiconductor device


A wiring substrate includes first and second wiring structures. The first wiring structure includes a core substrate, first and second insulation layers formed from a thermosetting insulative resin respectively including first and second reinforcement materials, and a via wire formed in the first insulation layer.
Shinko Electric Industries Co., Ltd.
06/25/15
20150181700
new patent

Stretchable and foldable electronic devices


Disclosed herein are stretchable, foldable and optionally printable, processes for making devices and devices such as semiconductors, electronic circuits and components thereof that are capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Strain isolation layers provide good strain isolation to functional device layers.
Northwestern University
06/25/15
20150181683
new patent

Electrostatic chuck including declamping electrode and declamping


A semiconductor wafer processing apparatus for processing semiconductor wafers comprises a semiconductor wafer processing chamber in which a semiconductor wafer is processed, a process gas source in fluid communication with the processing chamber adapted to supply process gas into the processing chamber, a vacuum source adapted to exhaust process gas and byproducts of the processing from the processing chamber, and an electrostatic chuck assembly. The electrostatic chuck assembly comprises a support surface in a layer of ceramic material on which the semiconductor wafer is supported during processing of the wafer in the chamber, at least one electrostatic clamping electrode embedded in the layer of ceramic material, the at least one electrostatic clamping electrode operable to apply an electrostatic clamping force to the wafer on the support surface when an electrostatic clamping voltage is applied to the clamping electrode, and at least one declamping electrode embedded in the layer of ceramic material above the at least one electrostatic clamping electrode operable to provide a path for draining any residual charge between the wafer and the support surface when the electrostatic clamping voltage is no longer applied to the clamping electrode..
Lam Research Corporation
06/25/15
20150181631
new patent

Establishing wireless communication via proximity detection


The present disclosure relates to computer-implemented systems and methods for wireless communication via proximity detection. The method may include determining, by a computer via a plurality of induction coils in a proximity transponder, a magnetic field emitted from a base station.
06/25/15
20150181352
new patent

Biasing circuitry for mems transducers


Circuitry for biasing a mems transducer and associated signal processing circuitry. A reference voltage generator is configured to generate a reference voltage at a reference voltage node.
Cirrus Logic International (uk) Limited
06/25/15
20150181348
new patent

Micro-electro-mechanical transducer having an optimized non-flat surface


A capacitive micromachined ultrasound transducer (cmut) and fabrication method of the same are provided. The cmut has a substrate, a curved membrane disposed on top of the substrate, and a flexible membrane disposed on top of the curved membrane.
Kolo Technologies, Inc.
06/25/15
20150181344
new patent

Electroacoustic transducer and manufacturing method thereof


An electroacoustic transducer comprises flexible strips and a shell, wherein the shell is formed of a first sub shell which is fixedly bonded to a second sub shell, the first sub shell is provided with a bonding surface for being bonded to the second sub shell, the flexible strip is bent to form a bent portion at the bonding surface; the second sub shell is provided with a dodging structure for dodging the bent portion. Its manufacturing method comprises: performing injection molding on the first sub shell from the bonding portions of the elastic strips; performing injection molding on the second sub shell; fixedly bonding the first sub shell with the second sub shell, wherein the flexible strip is bent to form the bent portion from the bonding surface at the end part of the first sub shell..
Goertek Inc.
06/25/15
20150181339
new patent

Enhancing the reproduction of multiple audio channels


This invention relates to the field of multichannel audio. More particularly, the invention relates to a method for the provision of audio channels suitable for application to loudspeakers located above conventional front loudspeakers..
Dolby Laboratories, Inc.
06/25/15
20150181334
new patent

Temperature measurement apparatus and protection sound signal converting device


An audio signal output from a tone generator is fed into a coil provided in a transducer for vibrating a sound board, so that a sound signal is generated by the vibration of the sound board. A predetermined dc voltage supplied by a constant voltage source circuit is superimposed on the audio signal by an adding circuit, so that the superimposed signal is fed into the coil.
Yamaha Corporation
06/25/15
20150181176
new patent

Dive computer incorporating stored dive site information


Dive computers in accordance with embodiments of the invention are disclosed that store information concerning a dive site. The stored information can be accessed during the dive to provide information concerning such things as points of interest and/or hazards.
Pelagic Pressure Systems
06/25/15
20150181138
new patent

Solid-state imaging element and camera system


A solid-state imaging element that includes a plurality of semiconductor layers stacked, a plurality of stack-connecting parts for electrically connecting the plurality of semiconductor layers, a pixel array part in which pixel cells that include a photoelectric conversion part and a signal output part are arrayed in a two-dimensional shape, and an output signal line through which signals from the signal output part of the pixel cells are propagated, in which the plurality of semiconductor layers includes at least a first semiconductor layer and a second semiconductor layer, and, in the first semiconductor layer, the plurality of pixel cells are arrayed in a two-dimensional shape, the signal output part of a pixel group formed with the plurality of pixel cells shares an output signal line wired from the stack-connecting parts, and the output signal line has a separation part which can separate each output signal line.. .
Sony Corporation
06/25/15
20150180974
new patent

Methods for transporting digital media


A networked system is provided for transporting digital media packets, such as audio and video. The network includes network devices interconnected to send and receive packets.
Audinate Pty Limited
06/25/15
20150180916
new patent

Portable sharing content thereof


Disclosed are a portable apparatus and a method for sharing content thereof, in which the method of sharing contents in a portable apparatus includes receiving user interaction with a document targeted for photographing through a camera of the portable apparatus; and sharing a content corresponding to the document with at least one remote device so as to correspond to the user interaction with the document. With this, the user interaction with the contents of the portable apparatus input through the camera and the document targeted for photographing is shared with the remote device, thereby efficiently supporting education focused on students..
Samsung Electronics Co., Ltd.
06/25/15
20150180784
new patent

Bus system and computer program


A bus system (100) for a semiconductor circuit transmits data on a networked bus between a first node and at least one second node via a relay device (250) arranged on the bus. The bus system (100) includes a first bus of a low delay and a second bus of a high delay.
Panasonic Intellectual Property Management Co., Ltd.
06/25/15
20150180704
new patent

Semiconductor chip and transmission/reception system including the same


A transmission/reception system includes first to nth channels, where n is an integer equal to or greater than 3; a transmission chip suitable for transmitting first to (n−1)th signals through the first to (n−1)th channels and transmitting a correction signal generated by using the first to (n−1)th signals to the nth channel; and a reception chip suitable for receiving signals of the first to nth channels and generating restored signals of the first to nth channels by using the first to nth channels.. .
Sk Hynix Inc.
06/25/15
20150180593
new patent

Antenna tuning unit


A system, apparatus, and method directed to impedance matching an antenna with a transmitter for non-directional radio beacons. The apparatus includes an l-type impedance network comprising non-capacitive elements and at least one variable inductor on each branch of the impedance network.
Southern Avionics Co.
06/25/15
20150180564
new patent

Systems and methods for signal frequency division in wireless communication systems


A system may include at least one antenna for receiving a first receive signal having a first signal diversity property and a second receive signal having a second signal diversity property. A first signal path may include a first frequency converter for downconverting the first receive signal to a first intermediate frequency signal having a first intermediate frequency.
Aviat U.s., Inc.
06/25/15
20150180542
new patent

Smart nfc antenna matching network system having multiple antennas and user device including the same


At least one example embodiment provides a near field communication (nfc) antenna matching network system connected to an nfc transceiver. The nfc antenna matching network system includes a matching circuit connected to first and second antenna terminals and to the nfc transceiver.
Samsung Electronics Co., Ltd.
06/25/15
20150180535
new patent

Semiconductor device and serial data transmission line system


A semiconductor device and a serial data transmission line system have a reception circuit and an adaptive equalizer circuit. A supply source of a power supply supplied with the reception circuit is selected based on correction intensity of the correction value calculated by the adaptive equalizer circuit.
Renesas Electronics Corporation
06/25/15
20150180477
new patent

Port spreading


A semiconductor die having: a logic unit having a plurality of inputs/outputs; a plurality of pads whereby electrical connections can be made to the die; and a multiplexer arranged between the inputs/outputs and the pads, the multiplexer being operable in a first mode in which it maps a first number of the inputs/outputs to a first number of the pads with a first mean spacing between those pads, and a second mode in which it maps a second number of the inputs/outputs to a first number of the pads with a second mean spacing between those pads, wherein the first number is larger than the second number and the first spacing is smaller than the second spacing.. .
Cambridge Silicon Radio Limited
06/25/15
20150180468
new patent

Balancing currents of power semiconductors


An exemplary method and arrangement for balancing currents of power semiconductors. The arrangement including multiple power semiconductor units and a central control unit.
Abb Oy
06/25/15
20150180466
new patent

Switching circuit and semiconductor module


A switching circuit includes first to (n+1)th input/output terminals and first to nth field-effect transistors (fets), for an integer n of two or more. When one of a source end and a drain end is referred to as a first end and another one is referred to as a second end, the first input/output terminal is electrically connected to the first ends of all of the first to nth fets.
Murata Manufacturing Co., Ltd.
06/25/15
20150180463
new patent

Monitoring for power semiconductor switch


An exemplary power semiconductor switch is configured to be controlled on the basis of a gate voltage signal driven by a gate driver unit. The device includes a measuring component for generating a saturation voltage signal on the basis of a voltage over the power semiconductor switch, and an auxiliary switch connected between a saturation voltage signal line carrying the saturation voltage signal and an output of the gate driver unit driving the gate voltage signal.
Abb Oy
06/25/15
20150180453
new patent

Insulated gate semiconductor element drive device


A drive circuit includes a constant current circuit which supplies a constant current to the gate of an igbt and on-operates the igbt; a discharge circuit which grounds the gate of the igbt and off-operates the igbt; and a switch circuit which operates one of the constant current circuit or discharge circuit in accordance with a control signal and turns on or off the igbt. In particular, the drive circuit includes a current detection circuit which detects a current flowing through the igbt when the igbt is turned on; and a current regulation circuit which feeds the current detected by the current detection circuit back to the constant current circuit and controls an output current of the constant current circuit in accordance with the turn-on characteristics of the igbt..
Fuji Electric Co., Ltd.
06/25/15
20150180449
new patent

Vibrating device and manufacturing method therfor


A vibrating device having vibrating arms connected to a supporter. The vibrating arms have an n-type si layer which is a degenerated semiconductor and an exciter provided on the n-type si layer.
Murata Manufacturing Co., Ltd.
06/25/15
20150180444
new patent

Heating body, vibration device, electronic apparatus, and moving object


An ic for heating includes a semiconductor, substrate on which a diffusion layer is formed; a first pad that applies a power source voltage to the diffusion layer; and a second pad that applies a ground voltage to the diffusion layer. A semiconductor substrate includes slits such that the slits intersect a virtual straight line connecting the pads when the semiconductor substrate is seen in a plan view..
Seiko Epson Corporation
06/25/15
20150180443
new patent

Heating body, resonation device, electronic apparatus, and moving object


An ic for heating includes a semiconductor substrate on which a diffusion layer is formed; a first pad and a first via that apply a power voltage to the diffusion layer; and a second pad and a second via that apply a ground voltage to the diffusion layer. The vias overlap with an area on which the diffusion layer is formed in a plan view, the first pad overlaps with the first via in a plan view, and the second pad overlaps with the second via in a plan view.
Seiko Epson Corporation
06/25/15
20150180441
new patent

Microwave switch and manufacturing microwave switch


Provided is a microwave switch including at least one semiconductor device connected to a transmission line and grounded in parallel, and at least one inductor connected in series to the transmission line. When the semiconductor device is shorted, the inductor may perform impedance matching through an interaction with the semiconductor device..
Electronics And Telecommunications Research Institute
06/25/15
20150180425
new patent

Temperature stabilized circuitry


This disclosure relates to temperature stabilization of at least a portion of an amplifier, such as a logarithmic amplifier, and/or a band gap reference circuit. In one aspect, one or more stages of an amplifier, a heater, and a temperature sensor are included in a semiconductor material and surrounded by thermally insulating sidewalls..
Analog Devices Technology
06/25/15
20150180398
new patent

Induction motor flux and torque control


An induction motor controller is provided. The induction motor controller includes a first module that derives a commanded stator voltage vector, in a rotor flux reference frame, via a rotor flux regulator loop and a torque regulator loop, which process at least partially in the rotor flux reference frame.
Atieva, Inc.
06/25/15
20150180370
new patent

Micro-electro-mechanical transducer having an optimized non-flat surface


A capacitive micromachined ultrasound transducer (cmut) is provided. The cmut has a first layer having a first electrode and a second layer having a second electrode opposing the first electrode to define a gap width therebetween.
Kolo Technologies, Inc.
06/25/15
20150180350
new patent

Resonant bidirectional converter, uninterruptible power supply apparatus, and control method


The present invention provides a resonant bidirectional converter, an uninterruptible power supply apparatus, and a control method. The resonant bidirectional converter includes: a filter capacitor, three primary side bridge arms, a resonant cavity, three transformers, and three secondary side bridge arms, where two ends of each of the primary side bridge arms are separately connected to two ends of a bus capacitor, each of the primary side bridge arms includes two semiconductor switch that are serially connected in a same direction, and any connection point located between the two semiconductor switch of the primary side bridge arm that are serially connected in the same direction is a first connection point..
Huawei Technologies Co., Ltd.
06/25/15
20150180239
new patent

Power supply circuit


There is a problem in the prior semiconductor devices that energy recovery efficiency is low. According to one embodiment of the present invention, a power supply circuit includes an alternating-current signal synthesis unit including a plurality of alternating-current coupling elements having primary sides to which respective input alternating-current signals are input and secondary sides connected in series with each other, and a control circuit that outputs an input selection signal specifying a combination of the input alternating-current signals to be synthesized.
Renesas Electronics Corporation
06/25/15
20150180227
new patent

Semiconductor element drive device


A semiconductor element drive device includes a drive circuit which drives a semiconductor element configuring a power conversion device; an alarm generation circuit which generates alarm signals with pulse widths corresponding to protection factors in accordance with the outputs of detection circuits which detect information necessary for the operation of protecting the semiconductor element; an output circuit which externally outputs the alarm signals at a predetermined level; a protection cancellation circuit which generates a protection cancellation signal over a fixed period in accordance with the inverting output of a drive stop signal generation circuit, which stops the drive of the semiconductor element by the drive circuit in accordance with the outputs of the detection circuits, and with the output of the alarm generation circuit; and an output control circuit which changes the signal output level of the output circuit in accordance with the protection cancellation signal.. .
Fuji Electric Co., Ltd.
06/25/15
20150180210
new patent

Semiconductor arrangement and formation thereof


A semiconductor arrangement and a method of forming the same are described. A semiconductor arrangement includes a first layer including a first optical transceiver and a second layer including a second optical transceiver.
Taiwan Semiconductor Manufacturing Company Limited
06/25/15
20150180203
new patent

Semiconductor optical element, semiconductor laser element, and manufacturing semiconductor optical element and semiconductor laser element, and manufacturing semiconductor laser module and semiconductor element


A semiconductor optical element includes a semiconductor layer portion that includes an optical waveguide layer. The semiconductor layer portion contains a first impurity having a function of suppressing atomic vacancy diffusion and a second impurity having a function of promoting atomic vacancy diffusion, between a topmost surface of the semiconductor layer portion and the optical waveguide layer.
Furukawa Electric Co., Ltd.
06/25/15
20150180202
new patent

Solid-state lighting device


A solid-state lighting device includes light source, light emitting, light receiving and light guiding sections, and a protection circuit. The light source section has a semiconductor laser including a light emitting layer and a driving circuit.
Toshiba Lighting & Technology Corporation
06/25/15
20150180200
new patent

Light source drive circuit, optical scanning apparatus, semiconductor drive circuit, and image forming apparatus


A light source drive circuit which drives a light source is disclosed, including a drive current generating unit which generates a drive current, the driving current including a predetermined current for obtaining a predetermined light amount from the light source; and first and second overshoot currents which are applied to the predetermined current in synchronization thereto; and a control unit which sets, to the drive current generating unit, a value of the first overshoot current to a fixed value, and a value of the second overshoot current in accordance with a light amount output from the light source.. .
06/25/15
20150180198
new patent

Method for manufacturing semiconductor laser element


A method for manufacturing a semiconductor laser element includes forming an etching end point detection layer on part of a substrate, forming an substrate exposed portion and forming a lower cladding layer, an active layer, and an upper cladding layer on the etching end point detection layer and on the exposed portion, forming an insulating film pattern at a distance corresponding to a clearance region, from directly above a boundary between the substrate exposed portion and the etching end point detection layer, etching the upper clad layer, the active layer, and the lower cladding layer using the insulating film pattern as a mask and stopping etching at a time when the etching end point detection layer is exposed or after a predetermined time duration after the time.. .
Mitsubishi Electric Corporation
06/25/15
20150180177
new patent

Compensation network using an orthogonal compensation network


In one embodiment, the present invention is a communication connector, comprising a compensation circuit for providing a compensating signal to approximately cancel an offending signal over a range of frequency, the compensation circuit including a capacitive coupling with a first magnitude growing at a first rate over the range of frequency and a mutual inductive coupling with a second magnitude growing at a second rate over the range of frequency, the second rate being greater than the first rate (e.g., the second rate approximately double the first rate).. .
Panduit Corp.
06/25/15
20150180108
new patent

Passive microelectronic components, capable of allowing a radio-frequency or hyper-frequency signal to travel in a single direction


A passive radiofrequency microelectronic components for an integrated circuit which includes a dielectric substrate and at least one metal conductive layer positioned on said substrate. The conductive layer including at least one first metal conductive portion and a second metal conductive portion separated by an insulation.
Thales
06/25/15
20150180013
new patent

High voltage battery for vehicles


A high voltage battery for vehicles is provided and includes an electrode tab that is divided into a first part disposed substantially adjacent to a battery cell and a second part disposed substantially adjacent to a terminal. A first part extension extends from the first part and is fixed to a lower pouch and a second part extension extends from the second part and is fixed to an upper pouch.
Hyundai Motor Company
06/25/15
20150179980
new patent

Luminescence element, lighting device including the same, and manufacturing the same


A luminescence element includes a substrate, a first electrode layer located on the substrate, a second electrode layer located above the first electrode layer and arranged to oppose the first electrode layer, and an emitting layer between the first electrode layer and the second electrode layer. The second electrode layer includes a light-transmitting conductive layer that contains a conductive polymer and a cured resin in which constituent molecules are crosslinked with one another..
Panasonic Intellectual Property Management Co., Ltd.
06/25/15
20150179973
new patent

Electro-optic component and manufacturing the same


A foil comprises a substrate carrying an electrically conductive structure. The electrically conductive structure is embedded in a barrier layer structure having a first inorganic layer, a second inorganic layer and an organic layer between said inorganic layers, and the organic layer is partitioned by the electrically conductive structure into organic layer portions.
Koninklijke Philips N.v.
06/25/15
20150179972
new patent

Electrode contacts


A device structure providing contact to conductive layers via a deep trench structure is disclosed. The device includes a first dielectric layer including a first opening.
Ignis Innovation Inc.
06/25/15
20150179969
new patent

Organic electroluminescent device having conductive layers in a cathode layer and an electron transporting layer having a letal complex


An organic electroluminescent device including an anode layer, an organic functional layer and a cathode layer is provided. The organic functional layer is disposed between the anode layer and the cathode layer.
Au Optronics Corporation
06/25/15
20150179963
new patent

Organic electroluminescent device and producing the same


An organic electroluminescent device of the present invention comprising comprises, as stacked on a baseplate, at least, a first conductive layer, a charge injection and transport layer, a light-emitting layer, and a second conductive layer, wherein (1) the charge injection and transport layer includes a charge injection layer in contact with the first conductive layer, (2) the charge injection and transport layer has a thickness ranging from 130 to 1000 nm, (3) the charge injection layer contains a crosslinked aromatic amine polymer, and the baseplate is a glass baseplate, and the minimum value of a waviness tangent for the surface of the glass baseplate towards the first conductive layer is equal to or more than 4.00×10−6, or a maximum value of the waviness tangent is equal to or more than 22×10−6.. .
Mitsubishi Chemical Corporation
06/25/15
20150179957
new patent

Nickel complexes for flexible transistors and inverters


The ligands and counter-cations are selected to optimize properties, such as molecular alignment, film morphology, and molecular packaging. Described herein, the ligands can be 2,3-pyrazinedithiol (l1), 1,2-benzenedithol (l2) or 2,3-quinoxalinedithol (l3) and the counter-cations can be diquat (2,2′-ebpy) or methyl viologen (4,4′-mbpy).
06/25/15
20150179954
new patent

Substituted terrylene and quaterrylene derivates and use as semiconductors thereof


Disclosed are terrylene and quaterrylene derivates of general formula (i) and the use thereof as organic semiconductor materials.. .
Max-planck-gesellschaft Zur Foerderung Der Wissenschaften E.v.
06/25/15
20150179947
new patent

Method for preparing a photovoltaic thin film having a heterojunction


The present invention relates to a method for preparing a photovoltaic thin film having a heterojunction by depositing a composition, including a first organic electron-donor semiconductor cp and a second organic electron-acceptor semiconductor cn, onto a substrate and then carrying out phase segregation, including: a step (e1) of preparing a first mixture m1 including the organic semiconductors cn and cp within a solvent medium; and then a step (e2) of adding an additive, having at least one n3 function, to the said mixture.. .
Universite Montpellier 2, Sciences Et Techniques
06/25/15
20150179930
new patent

Schottky barriers for resistive random access memory cells


Provided are resistive random access memory (reram) cells having schottky barriers and methods of fabricating such reram cells. Specifically, a reram cell includes two schottky barriers, one barrier limiting an electrical current through the variable resistance layer in one direction and the other barrier limiting a current in the opposite direction.
Intermolecular Inc.
06/25/15
20150179929
new patent

Phase-change memory device and fabrication method thereof


A phase-change memory device and a method of fabricating the same are provided. The phase-change memory device includes a semiconductor substrate in which a word line is arranged, a diode line disposed over the word line and extending parallel to the word line, a phase-change line pattern disposed over the diode line, and a projection disposed between the diode line and the phase-change line pattern and protruding from the diode line.
Sk Hynix Inc.
06/25/15
20150179908
new patent

Substrate for semiconductor device, semiconductor device having the substrate, and manufacturing method thereof


A substrate for a semiconductor device is provided. The substrate includes a first metal line, a second metal line, a metal support part, a first insulating part, and a second insulating part.
Research & Business Foundation Sungkyunkwan University
06/25/15
20150179907
new patent

Semiconductor light emitting device


A semiconductor light emitting device includes a semiconductor layer including a light emitting layer, a p-side electrode provided on a second surface of the semiconductor layer, and an n-side electrode provided on the semiconductor layer to be separated from the p-side electrode. The p-side electrode includes a plurality of contact metal selectively provided on the semiconductor layer in contact with the second surface, a transparent film provided on the semiconductor layer in contact with the second surface between the plurality of contact metal, and a reflective metal provided on the contact metal and on the transparent film in contact with the contact metal, the reflective metal including silver.
Kabushiki Kaisha Toshiba
06/25/15
20150179904
new patent

Micro-led array with filters


An integrated led device is provided. The led device includes a substrate.
University College Cork, National University Of Ireland
06/25/15
20150179900
new patent

Semiconductor nanoparticle-based materials


In various embodiments, the present invention relates to a plurality of coated primary particles, each primary particle including a primary matrix material and containing a population of semiconductor nanoparticles, wherein each primary particle is provided with a separate layer of a surface coating material. Various methods of preparing such particles are described.
Nanoco Technologies Ltd.
06/25/15
20150179893
new patent

Semiconductor light-emitting device preventing metal migration


A semiconductor light-emitting device is configured to prevent or reduce metal migration. The device includes: an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer; a reflecting layer disposed over the p-type semiconductor layer and containing a metal that tends to migrate; a well ring structure at the p-type semiconductor layer and substantially surrounding the reflecting layer to prevent the metal from migrating towards a side wall of the device; and a metal coating layer over the reflecting layer and extending towards the well ring structure to form an ohmic contact with the p-type semiconductor of the entire well ring structure.
Xiamen Sanan Optoelectronics Technology Co., Ltd.
06/25/15
20150179890
new patent

Semiconductor light emitting element


A semiconductor light emitting element includes a first conductive type semiconductor layer, a light emitting layer, and a second conductive type semiconductor layer disposed in this order. The semiconductor light emitting element includes first and second electrodes, a first insulating film and a translucent electrode.
Nichia Corporation
06/25/15
20150179889
new patent

Light-emitting device with reflecting electrode


An electrode structure for effectively improving the stability of a semiconductor led includes a reflecting layer capable of current spreading. In such an electrode structure, the current injects from the side surface of the reflecting layer to form a certain potential gradient over the contact surface between the electrode and the led contact surface, thereby inhibiting the metal ion of the reflecting layer from migration due to electric field during usage, thereby improving device stability.
Xiamen Sanan Optoelectronics Technology Co., Ltd.
06/25/15
20150179888
new patent

Semiconductor light emitting structure and semiconductor package structure


A semiconductor light emitting structure includes an epitaxial structure, an n-type electrode pad, a p-type electrode pad and an insulation layer. The n-type electrode pad and the p-type electrode pad are disposed on the epitaxial structure apart, wherein the p-type electrode pad has a first upper surface.
Genesis Photonics Inc.
06/25/15
20150179886
new patent

Diode having vertical structure


A light emitting diode includes a conductive layer, an n-gan layer on the conductive layer, an active layer on the n-can layer, a p-gan layer on the active layer, and a p-electrode on the p-gan layer. The conductive layer is an n-electrode..
Lg Innotek Co., Ltd.
06/25/15
20150179884
new patent

Light emitting device and light emitting apparatus having the same


A light emitting device is provided a transmissive substrate; a first pattern portion including a protrusions; a second pattern portion including a concaves having a width smaller than a width of each protrusion; a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer, under the transmissive substrate; a first electrode under the first conductive semiconductor layer; a reflective electrode layer under the second conductive semiconductor layer; a second electrode under the reflective electrode layer; a first connection electrode under the first electrode; a second connection electrode under the second electrode; and an insulating support member around the first electrode and the first connection electrode and around the second electrode and the second connection electrode. A transmissive resin layer is on the transmissive substrate and an insulating layer is between the insulating support member and the reflective electrode layer..
Lg Innotek Co., Ltd.
06/25/15
20150179883
new patent

Method of manufacturing a semiconductor device and a semiconductor device


A method of manufacturing a semiconductor device and the device resulted thereof is disclosed. In one aspect, the device has a heterogeneous layer stack of one or more iii-v type materials, at least one transmission layer of the layer stack having a roughened or textured surface for enhancement of light transmission.
Imec
06/25/15
20150179882
new patent

Light emitting device and light emitting device package having the same


Disclosed is a light emitting device. The light emitting device includes a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer and a light extraction structure formed on the first conductivity-type semiconductor layer, and the light extraction structure includes a plurality of cylinders and a void is formed in each cylinder..
Lg Innotek Co., Ltd.
06/25/15
20150179881
new patent

Nitride led structure with double graded electron blocking layer


A group iii nitride-based light emitting device includes an n-type semiconductor layer; a first p-type semiconductor layer; an active region; and an electron blocking region comprising algainn located between the active region and the first p-type semiconductor layer, and including at least an upgraded layer and a downgraded layer. An aluminium composition of the upgraded layer of the electron blocking region increases from an active region side to a first p-type semiconductor layer side of the electron blocking region, and an aluminium composition of the downgraded layer of the electron blocking region decreases from the active region side to the first p-type semiconductor layer side of the electron blocking region.
Sharp Kabushiki Kaisha
06/25/15
20150179880
new patent

Nitride semiconductor structure


A nitride light emitting diode structure including a first type doped semiconductor layer, a second type doped semiconductor layer, a light emitting layer, a first metal pad, a second metal pad and a magnetic film is disclosed. The magnetic film disposed between the first metal pad and the first type doped semiconductor layer includes a zinc oxide (zno) layer doped with cobalt (co).
Industrial Technology Research Institute
06/25/15
20150179879
new patent

Light emitting diode with improved light extraction efficiency


Disclosed is a light emitting diode (led) having improved light extraction efficiency. The led includes a light emitting structure positioned on a substrate and having a first semiconductor layer, an active layer and a second semiconductor layer.
Seoul Viosys Co., Ltd.
06/25/15
20150179878
new patent

Light emitting device


The disclosed light emitting device includes an intermediate layer interposed between the light emitting semiconductor structure and the substrate. The light emitting semiconductor structure includes a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, wherein the active layer has a multi quantum well structure including at least one period of a pair structure of a quantum barrier layer including alxga(1-x)n (0<x<1) and a quantum well layer including alyga(1-y)n(0<x<y<1), and at least one of the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer includes algan.
Lg Innotek Co., Ltd.
06/25/15
20150179875
new patent

Template for growing semiconductor, separating growth substrate and fabricating light emitting device using the same


A template for growing a semiconductor, a method of separating a growth substrate and a method of fabricating a light emitting device using the same are disclosed. The template for growing a semiconductor includes a growth substrate including a nitride substrate; a seed layer disposed on the growth substrate and including at least one trench; and a growth stop layer disposed on a bottom surface of the trench, wherein the trench includes an upper trench and a lower trench, and the upper trench has a smaller width than the lower trench..
Seoul Viosys Co., Ltd.
06/25/15
20150179874
new patent

Light emitting diode structure


A light emitting diode (led) structure includes a substrate, a n-type semiconductor layer, a light emitting layer and a p-type semiconductor layer. The n-type semiconductor layer is disposed on the substrate.
Genesis Photonics Inc.
06/25/15
20150179864
new patent

Cmos integrated the fabrication of thermopile pixel with umbrella absorber on semiconductor substrate


A method of manufacturing a pixel structure having an umbrella absorber is disclosed. The method includes providing a substrate with a membrane on a first surface of the substrate.
Excelitas Technologies Singapore Pte. Ltd.
06/25/15
20150179861
new patent

Etching of infrared sensor membrane


The invention relates to an infrared thermal sensor comprising a substrate having a cavity, a cavity bottom wall formed by a continuous substrate surface. The sensor comprises a membrane adapted for receiving heat from incident infrared radiation, a beam suspending the membrane, and a thermocouple.
Melexis Technologies Nv
06/25/15
20150179859
new patent

Solar cell with reduced absorber thickness and reduced back surface recombination


Manufacture for an improved stacked-layered thin film solar cell. Solar cell has reduced absorber thickness and an improved back contact for copper indium gallium selenide solar cells.
International Business Machines Corporation
06/25/15
20150179858
new patent

Solar cell and manufacturing method thereof


A solar cell includes a crystalline silicon semiconductor substrate, an intrinsic amorphous silicon semiconductor layer, an amorphous silicon semiconductor layer and a transparent conductive layer. The crystalline silicon semiconductor substrate possesses a first doped type and a trench is formed thereon to form an enclosed area to define a first electrode region in the enclosed area and a second electrode region out of the enclosed area.
Neo Solar Power Corp.
06/25/15
20150179857
new patent

Semiconductor epitaxial structures and semiconductor optoelectronic devices comprising the same


An optoelectronic device comprises a substrate; a converting structure for converting energy between light and electric current over the substrate; and a semiconductor buffer layer combination between the substrate and the converting structure, the semiconductor buffer layer combination comprising multiple first semiconductor layers and multiple second semiconductor layers alternately stacked, wherein each of the multiple first semiconductor layers comprises a first element, each of the multiple second semiconductor layers comprises a second element different from the first element, and the composition ratio of the first element gradually increases or decreases with an increase of the distance between the first semiconductor layers and the substrate.. .
Epistar Corporation
06/25/15
20150179845
new patent

Solid-state imaging device, light detecting device, and electronic apparatus


A solid-state imaging device includes a multi-quantum wells (mqw) structure which combines and uses a non-group iv lattice matching-based compound semiconductor with an absolute value of a mismatch ratio of less than 1% on a silicon substrate so as to have sensitivity to at least infrared light.. .
Sony Corporation
06/25/15
20150179843
new patent

Photovoltaic device


A photovoltaic device includes a photovoltaic portion having light-receiving surface that receives light, the photovoltaic portion including a nano-structure. The nano-structure includes one or more first regions and one or more second regions.
Panasonic Corporation
06/25/15
20150179842
new patent

Rectifier and terahertz detector using the same


Disclosed is a rectifier capable of performing a high speed rectifying operation, and includes: a first semiconductor layer; a second semiconductor layer; and a third semiconductor layer, in which the first semiconductor layer and the third semiconductor layer are formed of semiconductor layers having the same type, and the second semiconductor layer is formed between the first semiconductor layer and the third semiconductor layer, is formed of a semiconductor layer having a different type from that of the first semiconductor layer and the third semiconductor layer, and is formed in graded doped state.. .
Electronics And Telecommunications Research Institute
06/25/15
20150179840
new patent

Light receiving/emitting element, solar cell, optical sensor, light emitting diode, and surface emitting laser element technical field


A light receiving/emitting element 11 includes: a light receiving/emitting layer 21 in which a plurality of compound semiconductor layers are stacked; and an electrode 30 having a first surface 30a and a second surface 30b and made of a transparent conductive material, in which the second surface faces the first surface 30a, and the electrode is in contact, at the first surface 30a, with the light receiving/emitting layer 21. The transparent conductive material contains an additive made of one or more metals, or a compound thereof, selected from the group consisting of molybdenum, tungsten, chromium, ruthenium, titanium, nickel, zinc, iron, and copper, and concentration of the additive contained in the transparent conductive material near an interface to the first surface 30a of the electrode 30 is higher than concentration of the additive contained in the transparent conductive material near the second surface 30b of the electrode 30..
Suzhou Institute Of Nano-tech And Nano-bionics, Chinese Academy Of Sciences
06/25/15
20150179839
new patent

Contact layers for photovoltaic devices


Solar cells and methods for forming a back contact layer for a solar cell are disclosed. The methods comprise depositing a first layer comprising a conductor on a substrate, depositing a second layer on the first layer, the second layer comprising between about 1 nm and about 25 nm of a metal chalcogenide, and forming a third layer operable as an absorber layer on the second layer.
Intermolecular Inc.
06/25/15
20150179837
new patent

Solar cell and manufacturing the same


A solar cell is discussed. The solar cell includes a semiconductor substrate of a first conductive type, an emitter region of a second conductive type opposite the first conductive type, which is positioned at a front surface of the semiconductor substrate, a front passivation part positioned on a front surface of the emitter region, a front electrode part which passes through the front passivation part and is electrically connected to the emitter region, a back passivation part positioned on a back surface of the semiconductor substrate, and a back electrode part which passes through the back passivation part and is electrically connected to the semiconductor substrate.
Lg Electronics Inc.
06/25/15
20150179836
new patent

Metallization of solar cells


Approaches for the metallization of solar cells and the resulting solar cells are described. In an example, a method of fabricating a solar cell involves forming a barrier layer on a semiconductor region disposed in or above a substrate.
06/25/15
20150179835
new patent

Solar cell


A solar cell includes an opto-electrical conversion structure, a first electrically-conductive structure, and a second electrically-conductive structure. The opto-electrical conversion structure has a light receiving surface and a back surface opposite to the light receiving surface.
Au Optronics Corporation
06/25/15
20150179831
new patent

Semiconductor structure and manufacturing method thereof


A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface.
Xintec Inc.
06/25/15
20150179829
new patent

Composition for forming passivation layer, semiconductor substrate with passivation layer, producing semiconductor substrate with passivation layer, photovoltaic cell element, producing photovoltaic cell element and photovoltaic cell


The composition for forming a passivation layer includes an organic aluminum compound represented by formula (i) and an organic compound represented by formula (ii). In formula (i), each r1 independently represents an alkyl group having from 1 to 8 carbon atoms.
Hitachi Chemical Company, Ltd.
06/25/15
20150179826
new patent

Diode device and manufacturing the same


A diode device may include: a first semiconductor area having a first conductivity type; a second semiconductor area having a second conductivity type, provided on the first semiconductor area and having a uniform impurity density; a trench provided to pass through the second semiconductor area to contact the first semiconductor area; and a first metal layer provided on surfaces of the trench and the second semiconductor area.. .
Samsung Electro-mechanics Co., Ltd.
06/25/15
20150179825
new patent

Diode device and manufacturing the same


A diode device may include a first conductivity type first semiconductor region, a second conductivity type second semiconductor region partially formed inside an upper portion of the first semiconductor region, and second conductivity type third semiconductor regions partially formed inside the upper portion of the first semiconductor region, formed on sides of the second semiconductor region, and having an impurity concentration higher than that of the second semiconductor region.. .
Samsung Electro-mechanics Co., Ltd.
06/25/15
20150179823
new patent

Electrode structure for nitride semiconductor device, production method therefor, and nitride semiconductor field-effect transistor


According to an electrode structure of an embodiment of the invention, an ohmic electrode is provided from recess to a surface of an insulating film without being in contact with the surface of the nitride semiconductor multilayer body, so that the insulating film covers the surface of the algan barrier layer. Accordingly, during the formation process of the ohmic electrode by dry etching, the surface of the nitride semiconductor multilayer body can be protected by the insulating film..
Sharp Kabushiki Kaisha
06/25/15
20150179822
new patent

Semiconductor device capable of reducing influences of adjacent word lines or adjacent transistors and fabricating method thereof


A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate.
Nanya Technology Corp.
06/25/15
20150179818
new patent

Method of manufacturing nonvolatile semiconductor storage device and nonvolatile semiconductor storage device


A method of nonvolatile semiconductor storage device including forming a tunnel insulating film so as to contact a semiconductor substrate; forming a charge trap layer above the tunnel insulating film including a trap layer configured to trap charge and a block layer configured to block penetration of electrons; forming a control electrode so as to contact the charge trap layer; anisotropically etching the control electrode to expose a sidewall of the control electrode; depositing a deposit so as to be attached to a surface of the sidewall of the control electrode exposed by the etching; and anisotropically etching the charge trap layer using the deposit as a mask so that the charge trap layer projects in a gate-length direction from a lower end of the sidewall of the control electrode and a sidewall of the charge trap layer is exposed.. .
Kabushiki Kaisha Toshiba
06/25/15
20150179817
new patent

Gate formation memory by planarization


Semiconductor devices and methods of producing the devices are disclosed. The devices are formed by forming a gate structure on a substrate.
Spansion Llc
06/25/15
20150179813
new patent

Semiconductor device


It is an object to provide a method of manufacturing a crystalline silicon device and a semiconductor device in which formation of cracks in a substrate, a base protective film, and a crystalline silicon film can be suppressed. First, a layer including a semiconductor film is formed over a substrate, and is heated.
Semiconductor Energy Laboratory Co., Ltd.
06/25/15
20150179812
new patent

Thin film transistor and display device using the same


There is provided a bottom gate channel etched thin film transistor that can suppress initial vth depletion and a vth shift. A thin film transistor is formed, including a gate electrode interconnection disposed on a substrate, a gate insulating film, an oxide semiconductor layer to be a channel layer, a stacked film of a source electrode interconnection and a first hard mask layer, a stacked film of a drain electrode interconnection and a second hard mask layer, and a protective insulating film..
Japan Display Inc.
06/25/15
20150179811
new patent

Thin film transistor and manufacturing the same, and display unit and electronic apparatus


There are provided a thin film transistor having a simple structure that allows reduction in leakage current at the time of gate negative bias, and a method of manufacturing the thin film transistor, and a display unit and an electronic apparatus. The thin film transistor includes: a gate electrode; a semiconductor film including a channel region that faces the gate electrode; and an insulating film provided at least at a position near an end portion on the gate electrode side of side walls of the semiconductor film..
Sony Corporation
06/25/15
20150179810
new patent

Semiconductor device


A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved. The semiconductor device includes an oxide semiconductor film over an insulating surface, an antioxidant film over the insulating surface and the oxide semiconductor film, a pair of electrodes in contact with the antioxidant film, a gate insulating film over the pair of electrodes, and a gate electrode which is over the gate insulating film and overlaps with the oxide semiconductor film.
Semiconductor Energy Laboratory Co., Ltd.
06/25/15
20150179809
new patent

Thin film transistor and manufacturing the same, array substrate and display device


A thin film transistor and method for manufacturing the same, an array substrate and a display device are disclosed. The thin film transistor comprises a substrate; a gate electrode, a source electrode, a drain electrode and a semiconductor layer formed on the substrate; a gate insulating layer between the gate electrode and the semiconductor layer or between the gate electrode and the source and drain electrodes; an etching stop layer between the semiconductor layer and the source and drain electrodes having a source contact hole and a drain contact hole therein; and a source buffer layer between the source electrode and the semiconductor layer and a drain buffer layer between the drain electrode and the semiconductor layer.
Boe Technology Group Co., Ltd.
06/25/15
20150179806
new patent

Semiconductor device


A semiconductor device includes a first transistor which includes a first gate electrode below its oxide semiconductor layer and a second gate electrode above its oxide semiconductor layer, and a second transistor which includes a first gate electrode above its oxide semiconductor layer and a second gate electrode below its oxide semiconductor layer and is provided so as to at least partly overlap with the first transistor. In the semiconductor device, a conductive film serving as the second gate electrode of the first transistor and the second gate electrode of the second transistor is shared between the first transistor and the second transistor.
Semiconductor Energy Laboratory Co., Ltd.
06/25/15
20150179805
new patent

Oxide semiconductor film and semiconductor device


An oxide semiconductor film which has more stable electric conductivity is provided. The oxide semiconductor film comprises a crystalline region.
Semiconductor Energy Laboratory Co., Ltd.
06/25/15
20150179804
new patent

Semiconductor device


The semiconductor device includes a transistor including an oxide semiconductor film having a channel formation region, a gate insulating film, and a gate electrode layer. In the transistor, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the thickness of the gate insulating film is large (equivalent oxide thickness which is obtained by converting into a thickness of silicon oxide containing nitrogen is 5 nm or more and 50 nm or less, preferably 10 nm or more and 40 nm or less).
Semiconductor Energy Laboratory Co., Ltd.
06/25/15
20150179803
new patent

Semiconductor device


To provide a transistor having a high on-state current. A semiconductor device includes a first insulator containing excess oxygen, a first oxide semiconductor over the first insulator, a second oxide semiconductor over the first oxide semiconductor, a first conductor and a second conductor which are over the second oxide semiconductor and are separated from each other, a third oxide semiconductor in contact with side surfaces of the first oxide semiconductor, a top surface and side surfaces of the second oxide semiconductor, a top surface of the first conductor, and a top surface of the second conductor, a second insulator over the third oxide semiconductor, and a third conductor facing a top surface and side surfaces of the second oxide semiconductor with the second insulator and the third oxide semiconductor therebetween.
Semiconductor Energy Laboratory Co., Ltd.
06/25/15
20150179802
new patent

Thin film transistor, display substrate having the same and manufacturing a display substrate


A thin film transistor includes a gate electrode, an active pattern over the gate electrode and including an oxide semiconductor, an etch-stop layer covering the active pattern, a source electrode on the etch-stop layer, a drain electrode on the etch-stop layer and spaced from the source electrode, and an active protection pattern between the etch-stop layer and the active pattern and electrically coupled to the source electrode and the drain electrode.. .
Samsung Display Co., Ltd.
06/25/15
20150179801
new patent

Thin film transistor and manufacturing the same


The present disclosure provides a thin film transistor and a method of manufacturing the same. The transistor includes:a substrate; a gate electrode, a source electrode, and a drain electrode; and an oxide semiconductor layer; wherein, the oxide semiconductor includes a source region and a drain region which electrically contact with the source electrode and the drain electrode respectively, and a channel region for providing a conductive channel between the source electrode and the drain electrode, wherein, a gate isolation layer is arranged between the oxide semiconductor layer and the gate region electrically contacting with the gate electrode, and an oxide semiconductor protective layer is arranged on the oxide semiconductor layer.
Shenzhen China Star Optoelectronics Technology Co. Ltd.
06/25/15
20150179799
new patent

Semiconductor device and fabricating the same


A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region.
Samsung Electronics Co., Ltd.
06/25/15
20150179798
new patent

Conformal thin film deposition of electropositive metal alloy films


The present disclosure relates to a method of forming a semiconductor. The method includes heating a substrate in a reaction chamber, supplying to the reaction chamber a first constituent including a metal borohydride wherein the metal borohydride includes at least one of: an alkaline earth metal, a transition metal, or a combination thereof; supplying to the reaction chamber a main-group hydride constituent; and depositing a metal compound on the substrate, wherein the metal compound comprises a) at least one of an alkaline earth metal a transition metal or a combination thereof, b) boron and c) optionally the main group alloying element..
06/25/15
20150179797
new patent

Semiconductor structure and manufacturing the same


The present invention discloses a semiconductor device, which comprises a substrate, a gate stack structure on the substrate, a channel region in the substrate under the gate stack structure, and source and drain regions at both sides of the channel region, wherein there is a stressed layer under and at both sides of the channel region, in which the source and drain regions are formed. According to the semiconductor device and the method for manufacturing the same of the present invention, a stressed layer is formed at both sides of and under the channel region made of a silicon-based material so as to act on the channel region, thereby effectively increasing the carrier mobility of the channel region and improving the device performance..
06/25/15
20150179796
new patent

Germanium profile for channel strain


The present disclosure relates to a transistor device having a strained source/drain region comprising a strained inducing material having a discontinuous germanium concentration profile. In some embodiments, the transistor device has a gate structure disposed onto a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.
06/25/15
20150179795
new patent

Semiconductor devices including multilayer source/drain stressors and methods of manufacturing the same


A semiconductor device including source drain stressors and methods of manufacturing the same are provided. The methods may include forming a recess region in the substrate at a side of a gate pattern, and an inner surface of the recess region may include a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes.
Samsung Electronics Co., Ltd.
06/25/15
20150179794
new patent

Semiconductor device and manufacturing the same


Disclosed are a semiconductor device and a method of manufacturing a semiconductor device. The device may include an n− type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate, a p type epitaxial layer disposed on the n− type epitaxial layer, an n+ region disposed on the p type epitaxial layer, a trench passing through the p type epitaxial layer and the n+ region and disposed on the n− type epitaxial layer, a p+ region disposed on the n− type epitaxial layer and separated from the trench, a gate insulating layer positioned in the trench, a gate electrode positioned on the gate insulating layer, an oxide layer positioned on the gate electrode, a source electrode positioned on the n+ region, the oxide layer, and the p+ region, and a drain electrode positioned on a second surface of the n+ type silicon carbide substrate, in which channels are positioned on both sides of the trench..
Hyundai Motor Company
06/25/15
20150179791
new patent

Silicon carbide semiconductor device and manufacturing same


This silicon carbide semiconductor device includes: a substrate with a principal surface; a silicon carbide layer which is arranged on a side of the principal surface of the substrate and which includes a first impurity region of a first conductivity type; a trench which is arranged in the silicon carbide layer and which has a bottom located in the first impurity region; a trench bottom impurity layer which is arranged in the trench to contact with at least a portion of the bottom of the trench and which is a silicon carbide epitaxial layer of a second conductivity type; a gate insulating film which covers a side surface of the trench and the trench bottom impurity layer; and a gate electrode which is arranged over at least a portion of the gate insulating film that is located inside the trench.. .
Panasonic Corporation
06/25/15
20150179787
new patent

Group iii-v semiconductor transistor and manufacturing the same


Provided are group iii-v semiconductor transistors and methods of manufacturing the same. The method includes forming a group iii-v semiconductor channel layer on a substrate, forming a gate insulating layer covering the group iii-v semiconductor channel layer, and forming a protection layer including sulfur between the group iii-v semiconductor channel layer and the gate insulating layer by annealing the substrate under a sulfur atmosphere..
Industry-university Cooperation Foundation Hanyang University Erica Campus
06/25/15
20150179784
new patent

Semiconductor device having schottky junction between substrate and drain electrode


A semiconductor device includes a semiconductor substrate that is made of a semiconductor material with a wider band gap than silicon, a field effect transistor, including a front surface element structure, provided on a front surface of the substrate, and a drain electrode having surface contact with the substrate so as to form a schottky junction between the semiconductor substrate and the drain electrode.. .
Fuji Electric Co., Ltd.
06/25/15
20150179781
new patent

Strained semiconductor nanowire


At least one semiconductor nanowire laterally abutted by a pair of semiconductor pad portions is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor nanowire such that the at least one semiconductor nanowire is suspended.
International Business Machines Corporation
06/25/15
20150179780
new patent

Nitride semiconductor device and manufacturing the same


Disclosed are an npn-type bipolar transistor as a nitride semiconductor device having good characteristics, and a method of manufacturing the same. A so-called pn epitaxial substrate has a structure wherein an n-type collector layer and a p-type base layer of a three-layer structure are provided over a substrate.
Hitachi Metals, Ltd.
06/25/15
20150179779
new patent

Semiconductor structure and forming the same


A semiconductor structure and a method for forming same are provided. The semiconductor structure includes a bipolar transistor.
United Microelectronics Corp.
06/25/15
20150179778
new patent

Soi lateral bipolar transistors having surrounding extrinsic base portions


Lateral soi bipolar transistor structures are provided including an intrinsic base semiconductor material portion in which all surfaces of the intrinsic base not forming an interface with either a collector semiconductor material portion or an emitter semiconductor material portion, contain an extrinsic base semiconductor material portion. Each extrinsic base semiconductor material portion is of the same conductivity type as that of the intrinsic base semiconductor material portion, yet each extrinsic base semiconductor material portion has a higher dopant concentration than the intrinsic base semiconductor material portion.
International Business Machines Corporation
06/25/15
20150179777
new patent

Semiconductor device and manufacturing semiconductor device


An object is to provide a highly reliable semiconductor device having stable electric characteristics by using an oxide semiconductor film having stable electric characteristics. Another object is to provide a semiconductor device having higher mobility by using an oxide semiconductor film having high crystallinity.
Semiconductor Energy Laboratory Co., Ltd.
06/25/15
20150179776
new patent

Semiconductor device and manufacturing thereof


An insulating layer is provided with a projecting structural body, and a channel formation region of an oxide semiconductor layer is provided in contact with the projecting structural body, whereby the channel formation region is extended in a three dimensional direction (a direction perpendicular to a substrate). Thus, it is possible to miniaturize a transistor and to extend an effective channel length of the transistor.
Semiconductor Energy Laboratory Co., Ltd.
06/25/15
20150179775
new patent

Method for manufacturing semiconductor device and semiconductor device


An object is to provide a semiconductor device in which defects are reduced and miniaturization is achieved while favorable characteristics are maintained. A semiconductor layer is formed; a first conductive layer is formed over the semiconductor layer; the first conductive layer is etched with use of a first resist mask to form a second conductive layer having a recessed portion; the first resist mask is reduced in size to form a second resist mask; the second conductive layer is etched with use of the second resist mask to form source and drain electrodes each having a projecting portion with a tapered shape at the peripheries; a gate insulating layer is formed over the source and drain electrodes to be in contact with part of the semiconductor layer; and a gate electrode is formed in a portion over the gate insulating layer and overlapping with the semiconductor layer..
Semiconductor Energy Laboratory Co., Ltd.
06/25/15
20150179774
new patent

Method for manufacturing semiconductor device


The semiconductor device is manufactured by the following method. A first oxide semiconductor film is formed over a first gate electrode and a first insulating film, oxygen is added to the first oxide semiconductor film, and then a second oxide semiconductor film is formed over the first oxide semiconductor film.
Semiconductor Energy Laboratory Co., Ltd.
06/25/15
20150179772
new patent

Method and system for a gallium nitride self-aligned vertical mesfet


A semiconductor structure includes a iii-nitride substrate and a drift region coupled to the iii-nitride substrate along a growth direction. The semiconductor substrate also includes a channel region coupled to the drift region.
Avogy, Inc.
06/25/15
20150179770
new patent

Method for fabricating semiconductor device with loop-shaped fin


A fabrication method of a semiconductor device includes the following steps. First, sacrificial patterns are formed on a substrate and a space is formed on the sidewalls of each sacrificial pattern.
United Microelectronics Corp.
06/25/15
20150179769
new patent

Fin density control of multigate devices through sidewall image transfer processes


Methods and structures for fabricating fins for multigate devices are disclosed. In accordance with one method, a plurality of sidewalls are formed in or on a plurality of mandrels over a semiconductor substrate such that each of the mandrels includes a first sidewall composed of a first material and a second sidewall composed of a second material that is different from the first material.
International Business Machines Corporation
06/25/15
20150179768
new patent

Fin structure of semiconductor device


The disclosure relates to a fin field effect transistor (finfet). An exemplary finfet comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising an upper portion comprising a first semiconductor material having a first lattice constant, wherein the upper portion comprises a first substantially vertical portion having a first width and a second substantially vertical portion having a second width less than the first width over the first substantially vertical portion; and a lower portion comprising a second semiconductor material having a second lattice constant less than the first lattice constant, wherein a top surface of the lower portion has a third width less than the first width; and a gate structure covering the second substantially vertical portion..
Taiwan Semiconductor Manufacturing Company, Ltd.
06/25/15
20150179767
new patent

Method of making a finfet device


A method for fabricating a fin field-effect transistor (finfet) device includes forming a first dielectric layer over a substrate and then etching the first dielectric layer and the substrate to form a first fin and a second fin. A second dielectric layer is formed along sidewalls of the first fin and the second fin.
Taiwan Semiconductor Manufacturing Company, Ltd.
06/25/15
20150179765
new patent

Semiconductor device and fabrication method thereof


An mosfet includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a body region where an inversion layer is formed at a region in contact with the gate oxide film by application of voltage to the gate electrode.
Sumitomo Electric Industries, Ltd.
06/25/15
20150179764
new patent

Semiconductor device and manufacturing same


A semiconductor device includes first to fourth semiconductor layers, a gate electrode, a field plate electrode, an insulating film, first and second main electrodes, and an insulating section. The second semiconductor layer has the first conductivity type and is provided on the first semiconductor layer.
Kabushiki Kaisha Toshiba
06/25/15
20150179763
new patent

Semiconductor device and fabricating the same


A semiconductor device has an fet of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate.
Renesas Electronics Corporation
06/25/15
20150179762
new patent

Power semiconductor device having gate electrode coupling portions for etchant control


A general insulated gate power semiconductor active element with many gate electrodes arranged in parallel has a laminated structure including a barrier metal film and a thick aluminum electrode film formed over the gate electrodes via an interlayer insulating film. When the aluminum electrode film is embedded in between the gate electrodes in parallel, voids may be generated with the electrodes.
Renesas Electronics Corporation
06/25/15
20150179761
new patent

Methods of manufacturing semiconductor devices


Methods of forming semiconductor devices are disclosed. In some embodiments, a first trench and a second trench are formed in a substrate, and dopants of a first conductivity type are implanted along sidewalls and a bottom of the first trench and the second trench.
Taiwan Semiconductor Manufacturing Company, Ltd.
06/25/15
20150179760
new patent

Strained asymmetric source/drain


The present disclosure provides a semiconductor device and methods of making wherein the semiconductor device has strained asymmetric source and drain regions. A method of fabricating the semiconductor device includes receiving a substrate and forming a poly gate stack on the substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.
06/25/15
20150179759
new patent

Semiconductor device and manufacturing semiconductor device


A semiconductor device includes an electron transit layer formed on a substrate; an electron supply layer formed on the electron transit layer; a doping layer formed on the electron supply layer, the doping layer being formed with a nitride semiconductor in which an impurity element to become p-type and c are doped; a p-type layer formed on the doping layer, the p-type layer being formed with a nitride semiconductor in which the impurity element to become p-type is doped; a gate electrode formed on the p-type layer; and a source electrode and a drain electrode formed on the doping layer or the electron supply layer. The p-type layer is formed in an area immediately below the gate electrode, and a density of the c doped in the doping layer is greater than or equal to 1×107 cm−3 and less than or equal to 1×1019 cm−3..
Transphorm Japan, Inc.
06/25/15
20150179758
new patent

Semiconductor device and manufacturing the same


A main cell and a sense cell are formed in a first and second region of a semiconductor substrate respectively. A base layer is formed on a drift layer in the first and second regions.
Mitsubishi Electric Corporation
06/25/15
20150179754
new patent

Manufacturing semiconductor structure


A semiconductor structure includes a substrate, a first well having a first conductive type, a second well having a second conductive type, a body region, a first doped region, a second doped region, a third doped region and a field plate. The first and second wells are formed in the substrate.
Macronix International Co., Ltd.
06/25/15
20150179753
new patent

Novel e-fuse design for high-k metal-gate technology


E-fuses are used in integrated circuits in order to permit real-time dynamic reprogramming of the circuit after manufacturing. An e-fuse is hereby proposed wherein the metal element adapted to be blown upon passage of a current is not comprised of a silicide layer but is rather a metal layer above which a semiconductor layer is formed.
Globalfoundries Inc.
06/25/15
20150179752
new patent

Method and contact structure for coupling a doped body region to a trench electrode of a semiconductor device


A semiconductor body has a first surface, a second opposing surface, an edge, an active device region, and an edge termination region. A trench extends from the first surface into the semiconductor body in the edge termination region and includes sidewalls and an insulated electrode.
Infineon Technologies Austria Ag
06/25/15
20150179751
new patent

Ohmic contact to semiconductor layer


A perforating ohmic contact to a semiconductor layer in a semiconductor structure is provided. The perforating ohmic contact can include a set of perforating elements, which can include a set of metal protrusions laterally penetrating the semiconductor layer(s).
Sensor Electronic Technology, Inc.
06/25/15
20150179750
new patent

Dual oxide trench gate power mosfet using oxide filled trench


A method for forming a dual oxide thickness trench gate structure for a power mosfet includes providing a semiconductor substrate; forming a first trench on a top surface of the substrate; forming a first oxide layer in the first trench where the first oxide layer has a first depth from the bottom of the first trench; forming a dielectric spacer along the sidewall of the first trench and on the first oxide layer; etching the first oxide layer exposed by the dielectric spacer to a second depth from the bottom of the first trench using the dielectric spacer as a mask where the second depth is lower than the first depth; removing the dielectric spacer; and forming a second oxide layer along the sidewall of the first trench above the first oxide layer where the second oxide layer has a thickness thinner than the thickness of the first oxide layer.. .
Alpha And Omega Semiconductor Incorporated
06/25/15
20150179749
new patent

Non-volatile memory cell with self aligned floating and erase gates, and making same


A memory device, and method of making the same, in which a trench is formed into a substrate of semiconductor material. The source region is formed under the trench, and the channel region between the source and drain regions includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate.
Silicon Storage Technology, Inc
06/25/15
20150179748
new patent

Method for fabricating semiconductor device


A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.. .
United Microelectronics Corp.
06/25/15
20150179747
new patent

Semiconductor device


A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a source electrode layer and a drain electrode layer which are electrically connected to an oxide semiconductor layer, a gate insulating film over the oxide semiconductor layer; the source electrode layer, and the drain electrode layer; and a gate electrode layer that overlaps with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer with the gate insulating film positioned therebetween.
Semiconductor Energy Laboratory Co., Ltd.
06/25/15
20150179746
new patent

Semiconductor device, semiconductor substrate, manufacturing semiconductor device, and manufacturing semiconductor substrate


A second epitaxial layer is grown epitaxially over a first epitaxial layer. The first epitaxial layer includes an epitaxially grown layer and a defect layer.
Renesas Electronics Corporation
06/25/15
20150179745
new patent

Reduction of edge effects from aspect ratio trapping


A device includes a crystalline material within an area confined by an insulator. In one embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an art technique.
Taiwan Semiconductor Manufacturing Company, Ltd.
06/25/15
20150179743
new patent

Graphene as a ge surface passivation layer to control metal-semiconductor junction resistivity


In some embodiments, a “channel last” device architecture is implemented wherein an amorphous carbon layer is formed between the channel and the source and drain layers. Subsequent heating of the structure allows the metal materials in the source and drain layers to convert the amorphous carbon materials into graphene.
Intermolecular, Inc.
06/25/15
20150179742
new patent

Active regions with compatible dielectric layers


A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material.
06/25/15
20150179741
new patent

Semiconductor device


A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of aln, a 2 μm-thick undoped gan layer, and 20 nm-thick undoped algan having an al composition ratio of 20% are epitaxially grown in this order on, for example, a substrate made of silicon, and a source electrode and a drain electrode are formed so as to be in ohmic contact with the undoped algan layer.
Panasonic Intellectual Property Management Co., Ltd.
06/25/15
20150179739
new patent

Integration of ge-containing fins and compound semiconductor fins


A stack of a germanium-containing layer and a dielectric cap layer is formed on an insulator layer. The stack is patterned to form germanium-containing semiconductor fins and germanium-containing mandrel structures with dielectric cap structures thereupon.
International Business Machines Corporation
06/25/15
20150179737
new patent

Method for producing a semiconductor device having a beveled edge termination


A method for producing a semiconductor device includes forming a trench that defines a closed loop in a semiconductor body and extends from a first surface into the semiconductor body. The trench has at least one sidewall that is beveled relative to a vertical direction of the semiconductor body.
Infineon Technologies Austria Ag
06/25/15
20150179736
new patent

Semiconductor device with device separation structures


A semiconductor device includes a first gate electrode structure, a second gate electrode structure, a device separation structure, and cell separation structures. The first gate electrode structure is buried in a semiconductor portion in a first cell array at a distance to a first surface of the semiconductor portion.
Infineon Technologies Dresden Gmbh
06/25/15
20150179735
new patent

Semiconductor device and associated method


The invention relates to a semiconductor device and an associated method for fabricating the semiconductor device. The device comprises: a substrate having a contact surface and a back surface separated by a total distance; a vertical device formed in the substrate and having first and second terminals on the contact surface; an isolation trench extending the total distance through the substrate between the contact surface and the back surface to electrically isolate the vertical device; and a terminal separation trench extending from the contact surface into the substrate and arranged to separate and define an electrical conduction path between the first and second terminals of the vertical device..
Nxp B.v.
06/25/15
20150179733
new patent

Schottky diode with buried layer in gan materials


A semiconductor structure includes a iii-nitride substrate characterized by a first conductivity type and having a first side and a second side opposing the first side, a iii-nitride epitaxial layer of the first conductivity type coupled to the first side of the iii-nitride substrate, and a plurality of iii-nitride epitaxial structures of a second conductivity type coupled to the iii-nitride epitaxial layer. The semiconductor structure further includes a iii-nitride epitaxial formation of the first conductivity type coupled to the plurality of iii-nitride epitaxial structures, and a metallic structure forming a schottky contact with the iii-nitride epitaxial formation and coupled to at least one of the plurality of iii-nitride epitaxial structures..
Avogy, Inc.
06/25/15
20150179732
new patent

Area efficient field effect device


A novel semiconductor transistor is presented. The semiconductor structure has a gate region forming a channel with repetitive patterns in the direction perpendicular to the current flow, so that the portion of its channel that is not strictly planar contributes to a significant reduction of the silicon area occupied by the device.
Eta Semiconductor.inc
06/25/15
20150179724
new patent

Organic light emitting diode display device and fabricating the same


An organic light emitting diode display device comprises a driving thin film transistor including a first semiconductor layer, a gate insulating layer formed on the first semiconductor layer. The device further includes a storage capacitor including a first capacitor electrode electrically coupled to a drain electrode of the driving thin film transistor, a buffer layer formed on the first capacitor electrode, a second semiconductor layer formed on the buffer layer, and a second capacitor electrode formed on the second semiconductor layer and electrically coupled to a gate electrode of the driving thin film transistor.
Lg Display Co., Ltd.
06/25/15
20150179722
new patent

Organic light emitting display device


An organic light emitting display device includes: a curved organic light emitting display panel. The organic light emitting display panel includes a flexible substrate, a thin film transistor layer including a semiconductor layer, and an organic light emission layer including an organic light emitting material.
Samsung Display Co., Ltd.
06/25/15
20150179707
new patent

Transistor, display, and electric apparatus


A transistor includes: a gate electrode; a semiconductor layer facing the gate electrode with an insulating layer in between; a pair of source-drain electrodes electrically connected to the semiconductor layer; and a contact layer provided in a moving path of carriers between each of the pair of source-drain electrodes and the semiconductor layer, the contact layer having end surfaces covered with the source-drain electrode.. .
Sony Corporation
06/25/15
20150179705
new patent

Three-dimensional resistive memory array


A method for manufacturing a three-dimensional resistive memory array is disclosed. The method comprises forming a repetitive sequence comprising an isolating layer, a semiconductor layer, a gate insulating layer, and a conductive layer.
Imec
06/25/15
20150179704
new patent

Semiconductor memory device


A semiconductor memory device according to an embodiment described below comprises: first lines arranged in a first direction perpendicular to a main surface of a substrate and extending in a second direction crossing the first direction; second lines arranged in the second direction, extending in the first direction, and intersecting the first lines; memory cells disposed at intersections of the first lines and the second lines; and an interlayer insulating film provided between the second lines. The interlayer insulating film has an air gap extending continuously in the first direction so as to intersect at least some of the first lines aligned along the first direction.
Kabushiki Kaisha Toshiba
06/25/15
20150179702
new patent

Ac light emitting diode and fabricating the same


The present invention relates to a light emitting device, including a plurality of light guide portions, a reflection prevention substance disposed on an inclined surface of each light guide portion of the plurality of light guide portions, and a plurality light emitting regions. Each light emitting region includes a first-type semiconductor layer, a second-type semiconductor layer, and an active layer disposed between the first-type semiconductor layer and the second-type semiconductor layer.
Seoul Viosys Co., Ltd.
06/25/15
20150179700
new patent

Solid-state image pickup apparatus, image pickup system including solid-state image pickup apparatus, and manufacturing solid-state image pickup apparatus


A method for manufacturing a solid-state image pickup device is provided. The image pickup apparatus includes a photoelectric conversion portion disposed on the semiconductor substrate, a first insulating film over the photoelectric conversion portion, functioning as an antireflection film, a second insulating film on the first insulating film, disposed corresponding to the photoelectric conversion portion, and a waveguide having a clad and a core whose bottom is disposed on the second insulating film.
Canon Kabushiki Kaisha
06/25/15
20150179699
new patent

Imaging apparatus, imaging system and manufacturing imaging apparatus


One embodiment provides an imaging apparatus including a photoelectric conversion unit; and a junction type field effect transistor configured to output a signal based on a carrier generated by the photoelectric conversion unit. The junction type field effect transistor includes a semiconductor region of a first conductivity type that forms a channel and a gate region of a second conductivity type.
Canon Kabushiki Kaisha
06/25/15
20150179697
new patent

Semiconductor integrated circuit, electronic device, solid-state imaging apparatus, and imaging apparatus


A semiconductor integrated circuit includes a first semiconductor substrate in which a part of an analog circuit is formed between the analog circuit and a digital circuit which subjects an analog output signal output from the analog circuit to digital conversion; a second semiconductor substrate in which the remaining part of the analog circuit and the digital circuit are formed; and a substrate connection portion which connects the first and second semiconductor substrates to each other. The substrate connection portion transmits an analog signal which is generated by a part of the analog circuit of the first semiconductor substrate to the second semiconductor substrate..
Sony Corporation
06/25/15
20150179696
new patent

Photodetector circuit and semiconductor device


To provide a photodetector circuit capable of obtaining signals in different periods without being affected by characteristics of a photoelectric conversion element. The photodetector circuit has n signal output circuits (n is a natural number of 2 or more) connected to the photoelectric conversion element.
Semiconductor Energy Laboratory Co., Ltd.
06/25/15
20150179693
new patent

Solid-state image sensor, producing the same, and electronic apparatus


A solid-state image sensor includes a pixel formed, upon forming a structure where a photoelectric conversion layer is laminated on a wiring layer constituting a pixel circuit, by forming at least the photoelectric conversion layer and a wiring layer bonding layer on a different substrate from a semiconductor substrate in which the wiring layer is formed, and by bonding the wiring layer bonding film of the different substrate and the wiring layer of the semiconductor substrate together.. .
Sony Corporation
06/25/15
20150179690
new patent

Mechanisms for forming image sensor device


Embodiments of mechanisms for forming an image sensor device are provided. The image sensor device includes a semiconductor substrate and an isolation structure in the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.
06/25/15
20150179688
new patent

Imaging apparatus, imaging system and manufacturing imaging apparatus


One embodiment according to the present disclosure is an imaging apparatus including pixels. The pixel includes a junction type field effect transistor (jfet) provided in a semiconductor substrate.
Canon Kabushiki Kaisha
06/25/15
20150179687
new patent

Array substrate of liquid crystal display device and fabricating the same


An array substrate of a liquid crystal display device and a method of fabricating the array substrate. A gate electrode of a thin film transistor of the array substrate is formed.
Lg Display Co., Ltd.
06/25/15
20150179686
new patent

Method of manufacturing a tft-lcd array substrate


A thin film transistor liquid crystal display (tft-lcd) array substrate comprises a gate line, a data line, a pixel electrode and a thin film transistor. The pixel electrode and the thin film transistor are formed in a pixel region defined by intersecting of the gate line and the data line, and the thin film transistor comprises a gate electrode, a semiconductor layer, a source electrode and a drain electrode.
Beijing Boe Optoelectronics Technology Co., Ltd.
06/25/15
20150179684
new patent

High productivity combinatorial material screening for stable, high-mobility non-silicon thin film transistors


Methods for hpc techniques are applied to the processing of site-isolated regions (sir) on a substrate to form at least a portion of a tft device used in display applications. The processing may be applied to at least one of gate dielectric deposition, gate dielectric patterning, metal-based semiconductor deposition, metal-based patterning, etch stop deposition, etch stop patterning, source/drain deposition, or source/drain patterning.
Intermolecular, Inc.
06/25/15
20150179683
new patent

High productivity combinatorial material screening for metal oxide films


Methods for hpc techniques are applied to the processing of site-isolated regions (sir) on a substrate to form at least a portion of a tft device used in display applications. The processing may be applied to at least one of gate dielectric deposition, gate dielectric patterning, metal-based semiconductor (e.g.
Intermolecular, Inc.
06/25/15
20150179682
new patent

Semiconductor device and manufacturing the same


It is an object to obtain a liquid crystal display device in which a contact defect is reduced, increase in contact resistance is suppressed, and an opening ratio is high. The present invention relates to a liquid crystal display device having a substrate; a thin film transistor provided over the substrate, which includes a gate wiring, a gate insulating film, an island-shaped semiconductor film, a source region, and a drain region; a source wiring which is provided over the substrate and is connected to the source region; a drain electrode which is provided over the substrate and is connected to the drain region; an auxiliary capacitor provided over the substrate; a pixel electrode connected to the drain electrode; and a protective film fanned so as to cover the thin film transistor and the source wiring, where the protective film has an opening, and the auxiliary capacitor is formed in the area where the opening is formed..
Semiconductor Energy Laboratory Co., Ltd.
06/25/15
20150179681
new patent

Semiconductor device, manufacturing the same, display unit, and electronic apparatus


A semiconductor device includes: a transistor having an oxide semiconductor film; and a retention capacitor having a first conductive film and a second conductive film, the first conductive film containing an oxide material and being in contact with the oxide semiconductor film, and the second conductive film facing the first conductive film with an insulating film in between.. .
Sony Corporation
06/25/15
20150179680
new patent

Display device, semiconductor device, and manufacturing display device


A display device according to the present disclosure includes: a transistor section that includes a gate insulating film, a semiconductor layer, and a gate electrode layer, the semiconductor layer being laminated on the gate insulating film, the gate electrode film being laminated on an opposite side to the semiconductor layer of the gate insulating film; a first capacitor section that includes a first metal film and a second metal film, the first metal film being disposed at a same level as wiring layers that are electrically connected to the semiconductor layer and is disposed over the transistor section, the second metal film being disposed over the first metal film with a first interlayer insulating film in between; and a display element that is configured to be controlled by the transistor section.. .
Sony Corporation
06/25/15
20150179676
new patent

Display device


With an increase in the definition of a display device, the number of pixels is increased, and thus the numbers of gate lines and signal lines are increased. Due to the increase in the numbers of gate lines and signal lines, it is difficult to mount an ic chip having a driver circuit for driving the gate and signal lines by bonding or the like, which causes an increase in manufacturing costs.
Semiconductor Energy Laboratory Co., Ltd.
06/25/15
20150179675
new patent

Display device and manufacturing the same


An object is to provide a display device with excellent display characteristics, where a pixel circuit and a driver circuit provided over one substrate are formed using transistors which have different structures corresponding to characteristics of the respective circuits. The driver circuit portion includes a driver circuit transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using a metal film, and a channel layer is formed using an oxide semiconductor.
Semiconductor Energy Laboratory Co., Ltd.
06/25/15
20150179673
new patent

Semiconductor device and manufacturing method thereof


When vc inspection for a teg is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a contact plug, so that reliability of a semiconductor device is improved. An element structure of an sram is formed on an soi substrate in a chip region.
Renesas Electronics Corporation
06/25/15
20150179672
new patent

Thin film transistor and manufacturing the same, array substrate, and electronic apparatus


A thin film transistor and a method for manufacturing the same, an array substrate including the thin film transistor, and an electronic apparatus including the thin film transistor or provided with the array substrate. The thin film transistor includes: a gate electrode, a gate insulating layer, an active layer, and a source electrode and a drain electrode, the active layer is formed of a mixture including a semiconductor nano-material and a photoresist material.
Boe Technology Group Co., Ltd.
06/25/15
20150179669
new patent

Method of manufacturing array substrate, array substrate and display device


A method of manufacturing an array substrate, an array substrate and a display device are provided. The method of manufacturing the array substrate includes: forming a pattern of a gate metal layer including a gate line and a gate electrode and preserving photoresist at a position on the pattern of the gate metal layer corresponding to a gate lead hole; sequentially forming a gate insulating thin film, a semiconductor thin film and a source/drain metal thin film; removing the photoresist preserved at the position on the pattern of the gate metal layer corresponding to the gate lead hole, and forming the gate lead hole; forming a pattern of a source/drain metal layer including a source electrode, a drain electrode and a data line and a semiconductor layer; and forming a pattern including a pixel electrode layer and a channel..
Boe Technology Group Co., Ltd.
06/25/15
20150179664
new patent

Heterogeneous semiconductor material integration techniques


Techniques are disclosed for heteroepitaxial growth of a layer of lattice-mismatched semiconductor material on an initial substrate, and transfer of a defect-free portion of that layer to a handle wafer or other suitable substrate for integration. In accordance with some embodiments, transfer may result in the presence of island-like oxide structures on the handle wafer/substrate, each having a defect-free island of the lattice-mismatched semiconductor material embedded within its upper surface.
06/25/15
20150179663
new patent

Multi-level contact to a 3d memory array and making


A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region.
Sandisk Technologies Inc.
06/25/15
20150179662
new patent

Cobalt-containing conductive layers for control gate electrodes in a memory structure


A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess.
Sandisk Technologies Inc.
06/25/15
20150179661
new patent

Vertical channel-type 3d semiconductor memory device and manufacturing the same


A vertical channel-type 3d semiconductor memory device and a method for manufacturing the same are disclosed. In one aspect, the device includes a multi-layer film formed by depositing alternating layers of insulation and an electrode material on a substrate.
Institute Of Microelectronics, Chinese Academy Of Sciences
06/25/15
20150179660
new patent

Three dimensional nand device with channel located on three sides of lower select gate and making thereof


A select gate transistor for a nand device includes a select gate electrode having a first side, a second side, and top and a bottom, a semiconductor channel located adjacent to the first side, the second side and the bottom of the select gate electrode, and a gate insulating layer located between the channel and the first side, the second side and the bottom of the select gate electrode.. .
Sandisk Technologies, Inc.
06/25/15
20150179659
new patent

Multilevel contact to a 3d memory array and making thereof


A multi-level device includes at least one device region and at least one contact region. The contact region has a stack of alternating plurality of electrically conductive layers and plurality of electrically insulating layers located over a substrate.
Sandisk 3d Llc
06/25/15
20150179658
new patent

Semiconductor memory devices and manufacturing methods thereof


A semiconductor memory device and a manufacturing method of the semiconductor memory device are provided. The semiconductor memory device can include a substrate in which a cell area and a peripheral area are defined, a first gate insulating layer on the peripheral area, and a poly gate layer on the first gate insulating layer to form a combined stack, wherein the combined stack of the first gate insulating layer and the first poly gate layer is absent from the cell area..
Samsung Electronics Co., Ltd.
06/25/15
20150179657
new patent

Semiconductor storage device


A semiconductor storage device is provided with a semiconductor channel region; a first insulating layer including an oxide film disposed in contact with the semiconductor channel region, an yttrium oxide containing film disposed on the oxide film, and a hafnium oxide film having an orthorhombic phase iii structure disposed on the yttrium oxide containing film; and a control electrode disposed on the first insulating layer.. .
Kabushiki Kaisha Toshiba
06/25/15
20150179656
new patent

Ct-nor differential bitline sensing architecture


Providing for a non-volatile semiconductor memory architecture that achieves high read performance is described herein. In one aspect, an array of memory transistors arranged electrically in serial is configured to control a gate voltage of a pass transistor.
Spansion Llc
06/25/15
20150179652
new patent

Patterned structure of semiconductor device


A patterned structure of a semiconductor device includes a substrate, at least a first patterned structure, and at least a second patterned structure. The first patterned structure is a single-layered structure, and the second patterned structure is a multi-layered structure.
United Microelectronics Corp.
06/25/15
20150179651
new patent

Semiconductor device and manufacturing the same


A semiconductor device includes a bit line structure on a substrate, the bit line structure having a polysilicon layer pattern doped with impurities, and a metal layer pattern on the polysilicon layer pattern, a first spacer surrounding and contacting a sidewall of the bit line structure, the first spacer having a constant thickness, and a capacitor contact structure on the substrate, an air gap being defined between the capacitor contact structure and the first spacer.. .
Samsung Electronics Co., Ltd.
06/25/15
20150179649
new patent

Thyristor-based memory cells, devices and systems including the same and methods for forming the same


Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4f2, and methods for forming the same are provided. The thyristor-based memory cells each include a thyristor having vertically superposed regions of alternating dopant types, and a control gate.
Micron Technology, Inc.
06/25/15
20150179648
new patent

Multi-layer semiconductor structures for fabricating inverter chains


Systems and methods are provided for fabricating a semiconductor structure including an inverter chain. An example semiconductor structure includes a first device layer, a second device layer, and one or more inter-layer connection structures.
Taiwan Semiconductor Manufacturing Company Limited
06/25/15
20150179646
new patent

Flip-flop layout architecture implementation for semiconductor device


A semiconductor device includes a substrate including pmosfet and nmosfet regions. First and second gate electrodes are provided on the pmosfet region, and third and fourth gate electrodes are provided on the nmosfet region.
Samsung Electronics Co., Ltd.
06/25/15
20150179645
new patent

Semiconductor device with epitaxial structures


A semiconductor device includes at least two fin-shaped structures, a gate structure, at least two epitaxial structures and a cap. The fin-shaped structures are disposed on a substrate and are covered by the gate structure.
United Microelectronics Corp.
06/25/15
20150179644
new patent

Finfet integrated circuits and methods for their fabrication


Fin field effect transistor integrated circuits and methods for producing the same are provided. A fin field effect transistor integrated circuit includes a plurality of fins extending from a semiconductor substrate.
Globalfoundries, Inc.
06/25/15
20150179643
new patent

Semiconductor component with transistor


One aspect relates to a semiconductor component with a semiconductor body, a first main contact pad, a second main contact pad, a normally-on first transistor monolithically integrated in the semiconductor body and a normally-off second transistor monolithically integrated in the semiconductor body. The first transistor is a high electron mobility transistor having a first gate electrode and a first load path controllable via a first gate electrode, and the second transistor has a second gate electrode and a second load path controllable via the second gate electrode.
Infineon Technologies Austria Ag
06/25/15
20150179642
new patent

Method of manufacturing semiconductor device


A method of manufacturing a semiconductor device comprises forming an interlayer insulating film on a semiconductor substrate, the interlayer insulating film including a trench, forming a work function metal layer in the trench, forming an insulating film on the work function metal layer, forming a sacrificial film on the insulating film and filling the trench, forming a sacrificial film pattern with a top surface disposed in the trench by etching the sacrificial film, forming an insulating film pattern by selectively etching a portion of the insulating film which is formed higher than the sacrificial film pattern, and forming a work function metal pattern with a top surface disposed in the trench by selectively etching a portion of the work function metal layer which is formed higher than the insulating film pattern.. .
Samsung Electronics Co., Ltd.
06/25/15
20150179641
new patent

Semiconductor memory device and fabricating the same


A semiconductor memory device including a substrate, a first element isolation film pattern, and a second element isolation film pattern. The substrate includes a first region and a second region.
Samsung Electronics Co., Ltd.
06/25/15
20150179640
new patent

Common fabrication of different semiconductor devices with different threshold voltages


A multi-device semiconductor structure including a p-type logic device, a p-type memory device, a n-type logic device and a n-type memory device are provided on a bulk silicon substrate. Each of these devices includes a dielectric layer and either a n-type or a p-type work function layer disposed over the dielectric layer.
Globalfoundries Inc.
06/25/15
20150179639
new patent

Semiconductor structures including fluidic microchannels for cooling and related methods


Semiconductor structures are fabricated that include a semiconductor material bonded to a substrate with a layer of dielectric material between the semiconductor material and the substrate. At least one fluidic microchannel extends in a lateral direction through the layer of dielectric material between the semiconductor material and the substrate.
Soitec
06/25/15
20150179638
new patent

Method for manufacturing semiconductor device


A method for manufacturing a semiconductor device suppresses loss of vacuum in a chamber of an ion implanter, sag of a resist mask pattern for ion implantation, and producing a resist residue after ashing. First ion implanting process implants n-type impurity to form n+ impurity layer on the whole back surface of n− semiconductor wafer.
Fuji Electric Co., Ltd.
06/25/15
20150179637
new patent

Semiconductor devices


A semiconductor device includes a first doping region extending from a main surface of a semiconductor substrate into the semiconductor substrate. Further, the semiconductor device includes a second doping region arranged adjacent to the first doping region.
Infineon Technologies Ag
06/25/15
20150179636
new patent

Semiconductor device


A semiconductor device includes at least one field effect transistor structure, which is formed on a semiconductor substrate. The field effect transistor structure includes a drift region, a body region, a source region and a gate.
Infineon Technologies Ag
06/25/15
20150179635
new patent

Semiconductor device, light-emitting device, and electronic device


An object is to prevent an operation defect and to reduce an influence of fluctuation in threshold voltage of a field-effect transistor. A field-effect transistor, a switch, and a capacitor are provided.
Semiconductor Energy Laboratory Co., Ltd.
06/25/15
20150179634
new patent

Integrated semiconductor device


An integrated semiconductor device having a stabilization function includes a substrate layer, an insulating layer, ground plane layer formed between the substrate layer and the insulating layer and a signal plane layer formed on a surface of the insulating layer facing away from the substrate layer. An n-port, e.g.
Sony Corporation
06/25/15
20150179632
new patent

Semiconductor device comprising an e-fuse and a fet


A method of forming a semiconductor device including the steps of forming an electrically programmable fuse (e-fuse) on an isolation region and a transistor on an active region of a wafer, wherein forming the transistor includes forming a dummy gate above a substrate, removing the dummy gate and forming a metal gate in place of the dummy gate, and forming the e-fuse includes forming a metal-containing layer above the isolation region, forming a semiconductor layer on the metal-containing layer during the process of forming the dummy gate and of the same material as the dummy gate, forming a hard mask layer on the semiconductor layer formed on the metal-containing layer, and forming contact openings in the hard mask layer and semiconductor layer during the process of removing the dummy gate.. .
Globalfoundries Inc.
06/25/15
20150179631
new patent

Semiconductor device and fabricating the same


Provided is a semiconductor device including a deep doped region of a first conductivity type, a well region of a second conductivity type, a base region of the first conductivity type, an insulated gate bipolar transistor (igbt) and a metal oxide semiconductor (mos). The well region is disposed in the deep doped region.
Macronix International Co., Ltd.
06/25/15
20150179629
new patent

Semiconductor structure for electrostatic discharge protection


A semiconductor structure includes a p well formed on a p type substrate; a first n type electrode area formed on a central region of the p well; a first insulating area formed on the p well and surrounding the first n type electrode area; a second n type electrode area formed on the p well and surrounding the first insulating area; a second insulating area formed on the p well and surrounding the second n type electrode area; and a p type electrode area formed on the p well and surrounding the second insulating area; wherein periphery outlines of the first n type electrode area and the second n type electrode area are both 8k sided polygons or circles, and k is a positive integer.. .
Advanced Analog Technology, Inc.
06/25/15
20150179628
new patent

Semiconductor structure for electrostatic discharge protection


A semiconductor structure is arranged on an integrated circuit, the integrated circuit includes a seal ring arranged at outer periphery of the integrated circuit, a metal ring arranged at an inner side of the seal ring and a power bus arranged at a side of the metal ring. The semiconductor structure includes a first p type electrode area, a second p type electrode area and a first n type electrode area.
Advanced Analog Technology, Inc.
06/25/15
20150179626
new patent

Method of making stacked multi-chip packaging structure


A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the metal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip.. .
Alpha And Omega Semiconductor Incorporated
06/25/15
20150179625
new patent

Method of fabricating semiconductor package


A method of fabricating a semiconductor package includes providing a wafer which includes an upper area having through silicon vias (tsvs) and a lower area not having the tsvs; mounting a semiconductor chip on the upper area of the wafer; forming a passivation layer to a predetermined thickness to cover the semiconductor chip; exposing the tsvs by removing the lower area of the wafer in a state where no support is attached to the wafer; and exposing a top surface of the semiconductor chip by partially removing the passivation layer.. .
Samsung Electronics Co., Ltd.
06/25/15
20150179623
new patent

Method for manufacturing semiconductor device


A semiconductor chip is conveyed onto a chip mounting region of a wiring board by means of a bonding jig to electrically couple the semiconductor chip and the wiring board to each other. The bonding jig for mounting the semiconductor chip on the wiring board is equipped with a retention portion for adsorbing and retaining a logic chip, a pressing portion for pressing against the back surface of the semiconductor chip, and a sealing portion to be firmly attached to the peripheral edge portion of the back surface of the semiconductor chip.
06/25/15
20150179621
new patent

Module


A low profile module is provided that has a high functionality achieved by increasing the component mounting density. In spite of achieving high functionality in a module 100 by respectively mounting components such as a semiconductor substrate 104 and chip components 105 on the two main surfaces 101a and 101b of a wiring substrate 101, the low-profile module 100 can be provided which has a high functionality as a result of increasing its component mounting density by forming a thickness ha of a first component layer 102 formed by mounting only the semiconductor substrate 104 face down on one main surface 101a of the wiring substrate 101 so as to be smaller than the thickness of a second component layer 103 formed by mounting a plurality of chip components 105 on the other main surface 101b of the wiring substrate 101..
Murata Manufacturing Co., Ltd.
06/25/15
20150179620
new patent

Semiconductor device


A semiconductor element is sandwiched between a lower and upper surface of a cooling body. A connection circuit and a communication device are provided on the lower surface of the cooling body.
Mitsubishi Electric Corporation
06/25/15
20150179616
new patent

Semiconductor device and forming build-up interconnect structures over a temporary substrate


A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer.
Stats Chippac, Ltd.
06/25/15
20150179615
new patent

Semiconductor device and manufacturing the same


To improve reliability of a semiconductor device. In a conductive material that electrically couples a cu pillar electrode and a lead, an alloy part comprised of an alloy of tin and copper is formed inside this conductive material.
06/25/15
20150179614
new patent

Semiconductor device and manufacturing semiconductor device


Provided is a semiconductor device, including: a first substrate that includes a first wiring; a second substrate that is disposed facing the first substrate and includes a second wiring, the second wiring being connected to the first wiring through a connection terminal, and the second substrate being smaller in area than the first substrate; a first resin layer that is filled in a gap between the first substrate and the second substrate and covers a region, on the first substrate, in an outer periphery of the second substrate; an organic film pattern that is provided on the first substrate and surrounds the first resin layer; and a second resin layer that covers the first substrate, the organic film pattern, the first resin layer, and the second substrate.. .
Sony Corporation
06/25/15
20150179610
new patent

Compliant dielectric layer for semiconductor device


Systems, apparatuses, and methods provided for semiconductor devices and integrated circuit (ic) packages that include compliant dielectric layers. In a through silicon via interposer or substrate, a compliant dielectric material may be added to a surface of silicon material body to form a compliant dielectric layer.
Broadcom Corporation
06/25/15
20150179608
new patent

Embedded packages having a connection joint group


An embedded package includes a first semiconductor chip embedded in a package substrate, a second semiconductor chip disposed over a first surface of the package substrate, and a group of external connection joints disposed on the first surface of the package substrate and between a sidewall of the second semiconductor chip and an edge of the embedded package. Related memory cards and related electronic systems are also provided..
Sk Hynix Inc.
06/25/15
20150179607
new patent

Semiconductor packaging structure and process


A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.
06/25/15
20150179606
new patent

Method of processing a semiconductor wafer


A method of processing a semiconductor wafer includes forming semiconductor dies in the semiconductor wafer, each die having an active region containing devices of an integrated circuit and an edge region surrounding the active region, adjacent ones of the dies being separated by a scribe line. The method further includes forming interconnect wiring over the active region of each semiconductor die in an interlayer dielectric, forming ancillary wiring over the edge region of each die in the interlayer dielectric, forming a passivation on the interlayer dielectric, forming bond pads over the interconnect wiring of each die, the bond pads of each die being in electrical connection with the interconnect wiring of that die, and forming additional bond pads over the ancillary wiring of each semiconductor die, the additional bond pads of each die being in electrical connection with the interconnect wiring of that die..
Infineon Technologies Ag
06/25/15
20150179601
new patent

Removal apparatuses for semiconductor chips


An apparatus for removing a semiconductor chip from a board may include: a laser configured to irradiate the board with a laser beam to heat bumps mounting the semiconductor chip on the board; a picker configured to separate the semiconductor chip from the board; a vacuum portion configured to provide a vacuum to the picker; and an intake. If solder pillars, that are residues of the bumps, are melted by the laser beam, the intake removes the solder pillars using the vacuum provided from the vacuum portion.
Samsung Electronics Co., Ltd.
06/25/15
20150179599
new patent

Die substrate assembly and method


A die comprising a body of semiconductor material, said body configured to receive a solder layer of gold containing alloy for use in die bonding said die to a substrate, wherein the die includes an interface layer on a surface of the body for receiving the solder layer, the interface layer having a plurality of sub-layers of different metals.. .
Nxp B.v.
06/25/15
20150179598
new patent

Flip-chip packaging structure


A flip-chip packaging structure is provided, which includes: a packaging substrate having a substrate body and a circuit layer formed on the substrate body, wherein the circuit layer has a plurality of conductive pads embedded in the substrate body and exposed from a surface of the substrate body; and a chip disposed on and electrically connected to the packaging substrate through a plurality of conductive elements, wherein the conductive elements and the exposed portions of the conductive pads have a width ratio in a range of 0.7 to 1.3, thereby improving the product yield and reliability.. .
Siliconware Precision Industries Co., Ltd
06/25/15
20150179597
new patent

Semiconductor package and fabrication method thereof


A semiconductor package is provided, which includes: a first electronic element; a plurality of conductive elements formed on the first electronic element; a second electronic element having a plurality of conductive bumps and disposed on the first electronic element through the conductive bumps, wherein the conductive bumps are correspondingly electrically connected to the conductive elements; and an underfill formed between the second electronic element and the first electronic element for encapsulating the conductive bumps and the conductive elements, wherein the underfill contains a plurality of conductive particles having a particle size between 0.1 and 1 um, a plurality of insulating particles having a particle size between 1 and 10 um and a polymer. The invention overcomes the conventional drawback of poor electrical connection between the second electronic element and the first electronic element through the conductive particles so as to enhance the electrical performance of the semiconductor package..
Siliconware Precision Industries Co., Ltd
06/25/15
20150179596
new patent

Semiconductor package


Disclosed herein is a semiconductor package capable of stably implementing an interlayer bonding of a stacked board, the semiconductor package includes: a lower package having a chip module mounted thereon so as to be connected to a circuit pattern; an upper package stacked on the lower package and having an electrical device mounted thereon; and a bump receiving a tip of a solder ball electrically connecting the lower package and the upper package and coupled to the solder ball.. .
Samsung Electro-mechanics Co., Ltd.
06/25/15
20150179589
new patent

Semiconductor package and semiconductor module


According to one embodiment, a semiconductor package includes: a first metal body on which a part of a waveguide structure is formed; a second metal body including a mounting area for a semiconductor device and disposed on the first metal body; a line substrate on which a signal transmission line configured to communicate a waveguide with the semiconductor device mounted on the mounting area is formed; and a lid body disposed at a position facing the first metal body, interposing the second metal body and the line substrate. The lid body is made of resin, on which a structure corresponding to another waveguide structure on an extension of the waveguide structure in the first metal body is formed.
Kabushiki Kaisha Toshiba
06/25/15
20150179588
new patent

Semiconductor packages having emi shielding layers, methods of fabricating the same, electronic systems including the same, and memory cards including the same


Semiconductor packages are provided. In some embodiments, the semiconductor package includes a substrate, a first ground line including a first internal ground line disposed along edges of the substrate and a plurality of first extended ground lines between the first internal ground line and sidewalls of the substrate, a chip on the substrate, a molding member disposed on the substrate to cover the chip, and an electromagnetic interference (emi) shielding layer covering the molding member, the emi shielding layer extending along the sidewalls of the substrate and contacting the end portions of the plurality of first extended ground lines.
Sk Hynix Inc.
06/25/15
20150179587
new patent

Semiconductor device and forming stress relief layer between die and interconnect structure


A semiconductor device is made by forming a first conductive layer over a sacrificial carrier. A conductive pillar is formed over the first conductive layer.
Stats Chippac, Ltd.
06/25/15
20150179584
new patent

Alignment mark arrangement, semiconductor workpiece, and aligning a wafer


In various embodiments, an alignment mark arrangement may include a plurality of alignment marks disposed next to each other in a row, wherein at least one of the following holds true: a first alignment mark of the plurality of alignment marks has a first width and a second alignment mark of the plurality of alignment marks has a second width that is different from the first width; a first pair of neighboring alignment marks of the plurality of alignment marks is arranged at a first pitch and a second pair of neighboring alignment marks of the plurality of alignment marks is arranged at a second pitch that is different from the first pitch.. .
Infineon Technologies Ag
06/25/15
20150179583
new patent

Semiconductor devices comprising edge doped graphene and methods of making the same


A method of forming an edge-doped graphene channel is described. The method involves selectively removing graphene from a graphene layer on a substrate in the presence of a dopant to form graphene channels.
Harper Laboratories, Llc
06/25/15
20150179581
new patent

Metal-containing films as dielectric capping barrier for advanced interconnects


A method is provided for forming an interconnect structure for use in semiconductor devices. The method starts with forming a low-k bulk dielectric layer on a substrate and then forming a trench in the low-k bulk dielectric layer.
Applied Materials, Inc.
06/25/15
20150179580
new patent

Hybrid interconnect structure and fabricating the same


A method for fabricating hybrid interconnect structure is disclosed. The method includes the steps of: providing a material layer; forming a through-silicon hole in the material layer; forming a patterned resist on the material layer, wherein the patterned resist comprises at least an opening for exposing the through-silicon hole; and forming a conductive layer to fill the through-silicon hole and the opening in the patterned resist..
United Microelectronics Corp.
06/25/15
20150179577
new patent

Multilevel contact to a 3d memory array and making thereof


A multi-level device includes at least one device region and at least one contact region. The contact region has a stack of alternating plurality of electrically conductive layers and plurality of electrically insulating layers located over a substrate.
Sandisk 3d Llc
06/25/15
20150179576
new patent

Locally raised epitaxy for improved contact by local silicon capping during trench silicide processings


A low resistance contact to a finfet source/drain can be achieved by forming a defect free surface on which to form such contact. The fins of a finfet can be exposed to epitaxial growth conditions to increase the bulk of semiconductive material in the source/drain.
International Business Machines Corporation
06/25/15
20150179574
new patent

Semiconductor device and fabricating the same


According to a method of fabricating a semiconductor device, a first mask pattern is used to etch first device isolation layers and active lines or form grooves, in which word lines will be provided. Thereafter, the active lines are etched in a self-alignment manner by using the first mask pattern as an etch mask.
Samsung Electronics Co., Ltd.
06/25/15
20150179573
new patent

Semiconductor device and manufacturing semiconductor device


A method for manufacturing semiconductor device is provided. The method includes the following operations: providing a first conductive portion, a second conductive portion and a third conductive portion over a substrate; forming a dielectric layer over the first conductive portion, the second conductive portion, and the third conductive portion; forming a high-resistance layer over the first conductive portion; forming an oxide layer over the high-resistance layer and the dielectric layer; patterning the dielectric layer and the oxide layer by using the high-resistance layer as a blocking layer to form a first recess to expose the second conductive portion and the third conductive portion and to prevent the first conductive portion from exposure; and forming a plug layer in the first recess to connect the second conductive portion and the third conductive portion..
Taiwan Semiconductor Manufacturing Company Limited
06/25/15
20150179572
new patent

Semiconductor device for transmitting electrical signals between two circuits


A semiconductor device sends and receives electrical signals. The semiconductor device includes a first substrate provided with a first circuit region containing a first circuit; a multi-level interconnect structure provided on the first substrate; a first inductor provided in the multi-level interconnect structure so as to include the first circuit region; and a second inductor provided in the multi-level interconnect structure so as to include the first circuit region, wherein one of the first inductor and the second inductor is connected to the first circuit and the other of the first inductor and the second inductor is connected to a second circuit..
Renesas Electronics Corporation
06/25/15
20150179571
new patent

Metal interconnect structures and fabrication method thereof


A method is provided for fabricating a metal interconnection structure. The method includes providing a semiconductor substrate having an active region and an isolation structure surrounding the active region; and forming a metal layer on a surface of the semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation
06/25/15
20150179570
new patent

Semiconductor device and forming fine pitch rdl over semiconductor die in fan-out package


A semiconductor device has a first conductive layer including a plurality of conductive traces. The first conductive layer is formed over a substrate.
Stats Chippac, Ltd.
06/25/15
20150179567
new patent

Using materials with different etch rates to fill trenches in semiconductor devices


An embodiment includes a metal interconnect structure, comprising: a dielectric layer on a substrate; an opening in the dielectric layer, wherein the opening has opening sidewalls and exposes a conductive region of at least one of the substrate and an additional interconnect structure; a first atomic layer deposition (ald) layer on the conductive region and the opening sidewalls; a second ald layer on a portion of the first ald layer, and a third ald layer within the opening and on the first ald layer. Other embodiments are described herein..
06/25/15
20150179566
new patent

Semiconductor devices with inner via


A semiconductor device includes a semiconductor substrate having an inactive area and a pair of active areas separated by the inactive area, a control terminal supported by the semiconductor substrate and extending across the pair of active areas and the inactive area to define a conduction path during operation between a first conduction region in each active area and a second conduction region in each active area, a conduction terminal supported by the semiconductor substrate and extending across the pair of active areas and the inactive area for electrical connection to each first conduction region, and a via extending through the semiconductor substrate, electrically connected to the conduction terminal, and positioned in the inactive area.. .
Freescale Semiconductor, Inc.
06/25/15
20150179565
new patent

Semiconductor device with advanced pad structure resistant to plasma damage and forming the same


A connective structure for bonding semiconductor devices and methods for forming the same are provided. The bonding structure includes an alpad structure, i.e., a thick aluminum-containing connective pad, and a substructure beneath the aluminum-containing pad that includes at least a pre-metal layer and a barrier layer.
Taiwan Semiconductor Manufacturing Co., Ltd.
06/25/15
20150179564
new patent

Semiconductor device and manufacturing the same


A semiconductor device includes a stacked structure having first conductive layers stacked stepwise and first insulating layers interposed between the first conductive layers, wherein undercuts are formed under the first conductive layers and each of the first conductive layers includes a first region covered by the first conductive layer and a second region extending from the first region, contact pads coupled to the second regions of the respective first conductive layers, and a liner layer formed on the contact pads and filling the undercuts.. .
Sk Hynix Inc.
06/25/15
20150179563
new patent

Semiconductor device


According to one embodiment, a semiconductor device includes a first conductive line and a second conductive line including a first extension region in which the first conductive line and the second conductive line extend in a first direction, and a bend region in which the first conductive line and the second conductive line bend with respect to the first direction, a first dummy pattern and a second dummy pattern arranged on extension regions beyond the bend region of the first conductive line and the second conductive line, respectively, in the first direction, a first contact pad and a second contact pad formed beyond the bend region in the first direction, and connected to the first conductive line and the second conductive line, respectively.. .
Sandisk Corporation
06/25/15
20150179562
new patent

Thickened stress relief and power distribution layer


An embodiment includes a semiconductor structure comprising: a frontend portion including a device layer; a backend portion including a bottom metal layer, a top metal layer, and intermediate metal layers between the bottom and top metal layers; wherein (a) the top metal layer includes a first thickness that is orthogonal to the horizontal plane in which the top metal layer lies, the bottom metal layer includes a second thickness; and the intermediate metal layers includes a third thickness; and (b) the first thickness is greater than or equal to a sum of the second and third thicknesses. Other embodiments are described herein..
06/25/15
20150179560
new patent

Wiring substrate and semiconductor device


A wiring substrate includes first and second wiring structures. The first wiring structure includes a core substrate, first and second insulation layers each formed from a thermosetting insulative resin including a reinforcement material, and a via wire formed in the first insulation layer.
Shinko Electric Industries Co., Ltd.
06/25/15
20150179558
new patent

Semiconductor devices having through-substrate via plugs and semiconductor packages including the same


Provided is a semiconductor package including a package substrate having lands, a first semiconductor device mounted on the package substrate and having a bottom surface on which first lines are disposed, and solder balls respectively electrically connected to the lands of the package substrate with the first lines of the first semiconductor device. The first semiconductor device includes a first substrate, and through-substrate via (tsv) plugs that vertically pass through the first substrate.
06/25/15
20150179557
new patent

Semiconductor chips having heat conductive layer with vias


A heat conductive layer is deposited on a first surface of a wafer of semiconductor chips. The heat conductive layer is etched to form vias that expose through-electrodes on the first surface of each semiconductor chip.
International Business Machines Corporation
06/25/15
20150179556
new patent

Semiconductor package and manufacturing the same


There are provided a semiconductor package and a method of manufacturing the same. The semiconductor package according to an exemplary embodiment of the present disclosure includes: a substrate having a first device mounted thereon; a first lead frame formed on the substrate; a second lead frame formed to be spaced apart from the substrate; a post formed on the substrate and formed between the first lead frame and the second lead frame; and a molding part formed to surround the substrate and formed to protrude portions of the first and second lead frames, wherein the post includes a body part bonded to the substrate and a protruding part protruded to an exterior of the molding part..
Samsung Electro-mechanics Co., Ltd.
06/25/15
20150179554
new patent

Semiconductor device


A semiconductor device is disclosed. The semiconductor device has a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead disposed around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package sealing the semiconductor chip, the island, the lead, and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof..
Rohm Co., Ltd.
06/25/15
20150179552
new patent

Semiconductor package and manufacturing method thereof


A semiconductor package according to an exemplary embodiment in the present disclosure may include: a substrate having at least one indented portion formed as a groove therein; at least one electronic device mounted on one surface of the substrate; a lead frame bonded to the substrate and electrically connected to the electronic device; and a molded portion sealing the lead frame and the electronic device and including at least one through hole extending the indented portion.. .
Samsung Electro-mechanics Co., Ltd.
06/25/15
20150179551
new patent

Semiconductor device


A semiconductor device including a semiconductor chip, a first electrode pad and second electrode pad included on one surface of the semiconductor chip, a first conductive post joined by a joining material to the first electrode pad, a plurality of second conductive posts joined by a joining material to the second electrode pad, and a printed substrate, disposed opposing the one surface of the semiconductor chip, on which is formed an electrical circuit to which the first conductive post and second conductive posts are connected. The second conductive posts on the side near the first conductive post are arrayed avoiding a short-circuit prevention region at a distance such that the joining material of the first conductive post and the joining material of the second conductive posts do not link..
Fuji Electric Co., Ltd.
06/25/15
20150179550
new patent

Wiring layout having differently shaped vias


A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value.
Taiwan Semiconductor Manufacturing Company, Ltd.
06/25/15
20150179549
new patent

Semiconductor device


A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to identify the defective through silicon via x, activating x−1 switch circuits to connect x−1 data circuits to through silicon vias 1 to x−1 in the group of n adjacent through silicon vias, activating n−x switch circuits to connect n−x data circuits to through silicon vias x+1 to n in the group of n adjacent through silicon vias, and activating a switch circuit to connect a data circuit to an auxiliary through silicon via which is adjacent through silicon via n in the group of n adjacent through silicon vias.. .
Ps4 Luxco S.a.r.l.
06/25/15
20150179548
new patent

Through silicon via in n+ epitaxy wafers with reduced parasitic capacitance


A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance..
International Business Machines Corporation
06/25/15
20150179547
new patent

Hybrid tsv and forming the same


A semiconductor chip includes a substrate and a semiconductor layer positioned above the substrate. A hybrid through-silicon via (“tsv”) extends continuously through at least the semiconductor layer and the substrate and includes a first tsv portion and a second tsv portion.
Globalfoundries Singapore Pte Ltd
06/25/15
20150179546
new patent

Semiconductor device, manufacturing semiconductor device, and electronic device


There is provided a semiconductor device including a first semiconductor base substrate, a second semiconductor base substrate that is bonded onto a first surface side of the first semiconductor base substrate, a through electrode that is formed to penetrate from a second surface side of the first semiconductor base substrate to a wiring layer on the second semiconductor base substrate, and an insulation layer that surrounds a circumference of the through electrode formed inside the first semiconductor base substrate.. .
Sony Corporation
06/25/15
20150179545
new patent

Semiconductor devices and methods of manufacturing the same


A semiconductor device includes a through electrode penetrating a substrate such that a first end portion of the through electrode protrudes from a first surface of the substrate, a passivation layer covering the first surface of the substrate and a sidewall of the first end portion of the through electrode, a bump having a lower portion penetrating the passivation layer and coupled to the first end portion of the through electrode, and a lower metal layer disposed between the bump and the first end portion of the through electrode. The lower metal layer extends onto a sidewall of the bump and has a concave shape..
Sk Hynix, Inc.
06/25/15
20150179544
new patent

Semiconductor device and wafer thinning involving edge trimming and cmp


A semiconductor device has a substrate including a plurality of conductive vias formed vertically and partially through the substrate. An encapsulant is deposited over a first surface of the substrate and around a peripheral region of the substrate.
Stats Chippac, Ltd.
06/25/15
20150179542
new patent

Embedded heat spreader with electrical properties


Embodiments of the invention relate to incorporating one or more antennas or inductor coils into a semi-conductor package. A heat spreader or metal sheet is embedded in the package and stamped or otherwise patterned into a spiral or serpentine form.
International Business Machines Corporation
06/25/15
20150179541
new patent

Semiconductor device structure and manufacturing the same


Embodiments of mechanisms for forming a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate having a first device region and a second device region.
Taiwan Semiconductor Manufacturing Co., Ltd.
06/25/15
20150179540
new patent

Semiconductor device


A semiconductor device includes a substrate having a first surface and a second surface. A semiconductor chip is disposed on the first surface of the substrate.
Kabushiki Kaisha Toshiba
06/25/15
20150179539
new patent

Laser welding method, laser welding jig, and semiconductor device


In a laser welding method, a gap between first and second members to be welded is made at most 300 μm by pressing the second member against the first member with claws that are pressing parts of a laser welding jig, and the second member to be welded at a place between the claws is irradiated by laser light to laser-weld the first member and the second member. In a semiconductor device, the gap between the first member and the second member at the portion of laser-welding is at most 300 μm..
Fuji Electric Co., Ltd.
06/25/15
20150179537
new patent

Semiconductor element, semiconductor device including the same, and manufacturing semiconductor element


To provide a semiconductor element that can have the high adhesion between a substrate made of an oxide or the like and a metal film, a semiconductor element includes a substrate made of an oxide, a semiconductor element structure provided on an upper surface of the substrate, and a metal film provided on a lower surface of the substrate, in which the metal film contains nanoparticles made of an oxide.. .
Nichia Corporation
06/25/15
20150179535
new patent

Semiconductor wafers employing a fixed-coordinate metrology scheme and methods for fabricating integrated circuits using the same


Semiconductor wafers employing a fixed coordinate metrology scheme and methods for fabricating integrated circuits using the same are disclosed. In an exemplary embodiment, a semiconductor wafer employing a fixed-coordinate metrology scheme includes an external scribe region in the form of a first rectangular ring, the first rectangular ring defining a first interior space inward from the external scribe region and an interior scribe region in the form of a second rectangular ring, disposed within the first interior space and immediately adjacent to the external scribe region at all points along its exterior perimeter, the second rectangular ring defining a second interior space inward from the interior scribe region, the second interior space being wholly within the first interior space.
Globalfoundries Singapore Pte. Ltd.
06/25/15
20150179534
new patent

Testing of semiconductor components and circuit layouts therefor


In one embodiment of the present invention, a method of forming a semiconductor device includes performing a test during the forming of the semiconductor device within and/or over a substrate. A first voltage is applied to a first node coupled to a component to be tested in the substrate and a test voltage at a pad coupled to the component to be tested through a second node.
Infineon Technologies Ag
06/25/15
20150179533
new patent

Semiconductor manufacturing apparatus and manufacturing semiconductor device


In one embodiment, a semiconductor manufacturing apparatus includes a support module configured to support a wafer which includes a substrate and a workpiece layer provided on the substrate and has a first face on a side of the workpiece layer and a second face on a side of the substrate, a chamber configured to contain the support module, and a microwave generator configured to generate a microwave. The apparatus further includes a waveguide provided on an upper face side or a lower face side of the chamber, and configured to irradiate the second face of the wafer with the microwave.
Kabushiki Kaisha Toshiba
06/25/15
20150179532
new patent

System and dark field inspection


The present disclosure provides a method for fabricating a semiconductor structure. The method comprises providing a substrate and a patterned layer formed on the substrate, one or more overlay marks being formed on the patterned layer; performing a pre-film-formation overlay inspection using a bright field (bf) inspection tool to receive a pre-film-formation data on the one or more overlay marks on the patterned layer; forming one or more layers on the patterned layer; performing a post-film-formation overlay inspection using a dark field (df) inspection tool to receive a post-film-formation data on the one or more overlay marks underlying the one or more layers; and determining whether the pre-film-formation data matches the post-film-formation data..
Taiwan Semiconductor Manufacturing Company, Ltd.
06/25/15
20150179529
new patent

Thermal analysis for tiered semiconductor structure


Among other things, one or more systems and techniques for analyzing a tiered semiconductor structure are provided. One or more segments are defined for the tiered semiconductor structure.
Taiwan Semiconductor Manufacturing Company Limited
06/25/15
20150179528
new patent

Method for manufacturing semiconductor device


A method for manufacturing a semiconductor device may include forming a gate structure that includes a dummy gate member on a substrate. The method may further include forming two first-type spacers such that the dummy gate member is positioned between the first-type spacers.
Semiconductor Manufacturing International (shanghai) Corporation
06/25/15
20150179527
new patent

Semiconductor device having varying p-top and n-grade regions


An improved semiconductor is provided whereby n-grade and the p-top layers are defined by a series of discretely placed n-type and p-type diffusion segments. Also provided are methods for fabricating such a semiconductor..
Macronix International Co., Ltd.
06/25/15
20150179526
new patent

Anti-fuse array of semiconductor device and forming the same


An anti-fuse array of a semiconductor device and a method for forming the same are disclosed. The anti-fuse array for a semiconductor device includes a first-type semiconductor substrate formed to define an active region by a device isolation region, a second-type impurity implantation region formed in the active region, a first-type channel region isolated from the semiconductor substrate by the second-type impurity implantation region, a gate electrode formed over the channel region, and a first metal contact formed over the second-type impurity implantation region..
Sk Hynix Inc.
06/25/15
20150179525
new patent

High voltage three-dimensional devices having dielectric liners


High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate.
06/25/15
20150179524
new patent

Fin-like field effect transistor (finfet) based, metal-semiconductor alloy fuse device and manufacturing same


A fuse device and method for fabricating the fuse device is disclosed. An exemplary fuse device includes a first contact and a second contact coupled with a metal-semiconductor alloy layer, wherein the metal-semiconductor alloy layer extends continuously between the first contact and the second contact.
Taiwan Semiconductor Manufacturing Company, Ltd.
06/25/15
20150179523
new patent

Laser lift off systems and methods


Laser lift off systems and methods may be used to provide monolithic laser lift off with minimal cracking by reducing the size of one or more beam spots in one or more dimensions to reduce plume pressure while maintaining sufficient energy to provide separation. By irradiating irradiation zones with various shapes and in various patterns, the laser lift off systems and methods use laser energy more efficiently, reduce cracking when separating layers, and improve productivity.
Ipg Photonics Corporation
06/25/15
20150179522
new patent

Methods and wafer level packaging


A semiconductor device includes a substrate, a bond pad above the substrate, a guard ring above the substrate, and an alignment mark above the substrate, between the bond pad and the guard ring. The device may include a passivation layer on the substrate, a polymer layer, a post-passivation interconnect (ppi) layer in contact with the bond pad, and a connector on the ppi layer, wherein the connector is between the bond pad and the guard ring, and the alignment mark is between the connector and the guard ring.
Taiwan Semiconductor Manufacturing Company, Ltd.
06/25/15
20150179520
new patent

Methods for fabrication of semiconductor structures using laser lift-off process, and related semiconductor structures


Methods of fabricating a semiconductor structure include bonding a carrier wafer over a substrate, removing at least a portion of the substrate, transmitting laser radiation through the carrier wafer and weakening a bond between the substrate and the carrier wafer, and separating the carrier wafer from the substrate. Other methods include forming circuits over a substrate, forming trenches in the substrate to define unsingulated semiconductor dies, bonding a carrier substrate over the unsingulated semiconductor dies, transmitting laser radiation through the carrier substrate and weakening a bond between the unsingulated semiconductor dies and the carrier substrate, and separating the carrier substrate from the unsingulated semiconductor dies.
Soitec
06/25/15
20150179519
new patent

Interconnection structures in a semiconductor device and methods of manufacturing the same


Methods of fabricating interconnection structures of a semiconductor device are provided. The method includes, inter alia: forming a first insulation layer on a semiconductor substrate, forming a mold layer having trenches on the first insulation layer, forming a sidewall protection layer including a first metal silicide layer on sidewalls of the trenches, forming second metal lines that fill the trenches, forming upper protection layers on the second metal lines, removing the mold layer after formation of the upper protection layers to provide gaps between second metal lines, and forming a second insulation layer in the gaps and on the upper protection layers.
Sk Hynix Inc.
06/25/15
20150179517
new patent

Semiconductor substrate and fabrication method thereof


A method for fabricating a semiconductor substrate is disclosed, which includes: forming a first dielectric layer on a substrate body; forming a plurality of first vias penetrating the first dielectric layer to expose portions of the substrate body; forming a second dielectric layer on the first dielectric layer and the exposed portions of the substrate body, wherein the second dielectric layer extends on walls of the first vias; etching the second dielectric layer to form a plurality of openings communicating with the first vias and form a plurality of second vias penetrating the second dielectric layer in the first vias so as to expose portions of the substrate body, leaving the second dielectric layer on the walls of the first vias; and forming a circuit layer in the openings, and forming a plurality of conductive vias in the second vias for electrically connecting the circuit layer and the substrate body.. .
Siliconware Precision Industries Co., Ltd.
06/25/15
20150179516
new patent

Integrated structure and fabricating the same


A method for fabricating integrated structure is disclosed. The method includes the steps of: providing a substrate; forming a through-silicon hole in the substrate; forming a patterned resist on the substrate, wherein the patterned resist comprises at least one opening corresponding to a redistribution layer (rdl) pattern and exposing the through-silicon hole and at least another opening corresponding to another redistribution layer (rdl) pattern and connecting to the at least one opening; and forming a conductive layer to fill the through-silicon hole, the at least one opening and the at least another opening in the patterned resist so as to form a through-silicon via, a through-silicon via rdl pattern and another rdl pattern in one structure..
United Microelectronics Corp.
06/25/15
20150179515
new patent

Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches


Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to an embodiment of the invention, a low capacitance interconnect structure comprises an interlayer dielectric (ild).
06/25/15
20150179514
new patent

Cluster system for eliminating barrier overhang


A cluster tool is disclosed that can increase throughput of a wafer fabrication process by facilitating removal of barrier overhang in contact holes of contact film stacks. Individual chambers of the cluster tool provide for deposition of barrier material onto a semiconductor structure, depositing over with an amorphous carbon film (acf), etching back the acf, and etching a corner region of the contact hole.
Macronix International Co., Ltd.
06/25/15
20150179507
new patent

Methods for processing a semiconductor device


According to one embodiment, a method for processing a semiconductor device is provided including forming a final metal layer forming a passivation layer over the final metal layer and structuring the passivation layer and the final metal layer to form a patterned metal layer and a patterned passivation layer, wherein the patterned metal layer includes a pad region covered by the patterned passivation layer.. .
Infineon Technologies Ag
06/25/15
20150179506
new patent

Method for producing sos substrates, and sos substrate


A method for producing sos substrates which can be incorporated into a semiconductor production line, and is capable of producing sos substrates which have few defects and no variation in defects, and in a highly reproducible manner, or in other words, a method for producing sos substrates by: forming an ion-injection region (3) by injecting ions from the surface of a silicon substrate (1); adhering the ion-injection surface of the silicon substrate (1) and the surface of a sapphire substrate (4) to one another directly or with an insulating film (2) interposed therebetween; and then obtaining an sos substrate (8) having a silicon layer (6) on the sapphire substrate (4), by detaching the silicon substrate in the ion-injection region (3). This method is characterized in that the orientation of the sapphire substrate (4) is a c-plane having an off-angle of 1 degree or less..
Shin-etsu Chemical Co., Ltd.
06/25/15
20150179505
new patent

Semiconductor structure with trl and handle wafer cavities


A method is disclosed. The method comprises fabricating a device layer on a top portion of a semiconductor wafer that comprises a substrate.
Silanna Semiconductor U.s.a., Inc.
06/25/15
20150179504
new patent

Handle substrates of composite substrates for semiconductors


A handle substrate 11 or 11a is formed of an insulating polycrystalline material, the handle substrate has a surface 15 having a microscopic central line average surface roughness ra of 5 nm or smaller, and height differences 3 are provided between exposed faces 2a of crystal grains 2 exposing to said surface 15.. .
Ngk Insulators, Ltd.
06/25/15
20150179500
new patent

Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region


A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions.
Intermolecular, Inc.
06/25/15
20150179497
new patent

Isolation structure and manufacturing method thereof for high-voltage device in a high-voltage bcd process


The invention provides an isolation structure and a manufacturing method thereof for a high-voltage device in a high-voltage bcd process, the isolation structure comprising: a semiconductor substrate having a first type of doping; an epitaxial layer having a second type of doping over the semiconductor substrate, wherein the first type of doping is opposite to the second type of doping; an isolation region having the first type of doping, wherein the isolation region extends through the epitaxial layer into the semiconductor substrate, and wherein the isolation region has a doping concentration on the same order as a doping concentration of the epitaxial layer; a field oxide layer over the isolation region. This invention effectively isolates the epitaxial island where the bcd high-voltage device is located, thereby increasing the breakdown voltage of the high-voltage device in the bcd process.
Hangzhou Silan Integrated Circuit Co., Ltd
06/25/15
20150179496
new patent

Semiconductor wafer transfer jig


The semiconductor wafer conveying tool which can realize the uniform heating to a surface of a semiconductor wafer when heating the semiconductor wafer is a semiconductor wafer conveying tool which holds the semiconductor wafer having a predetermined diameter to convey it wherein the tool is provided with a main body having an opening with a diameter which is larger than a diameter of the semiconductor wafer, and at least three supporting members each having a predetermined length, containing plural pins which are arranged corresponding to the diameter of the semiconductor wafer and being configured to be a holding mechanism for holding the semiconductor wafer concentrically at a projection position from an inner periphery portion of the main body around the opening, as shown in fig. 1..
Senju Metal Lndustry Co., Ltd.
06/25/15
20150179494
new patent

Method for producing semiconductor device


A method for producing a semiconductor device having a semiconductor element obtained by dividing a semiconductor wafer comprises a temporary securing step of arranging a temporary securing film between a support member and the semiconductor wafer so as to temporarily secure the support member and the semiconductor wafer to each other; a grinding step of grinding a surface on the side opposite from the temporary securing film of the semiconductor wafer temporarily secured to the support member, and a semiconductor wafer peeling step of peeling the temporary securing film from the ground semiconductor wafer, wherein a semiconductor wafer edge-trimmed on an outer peripheral part of a surface opposing the support member is used as the semiconductor wafer, and the temporary securing step arranges the temporary securing film on the inside of the edge-trimmed part.. .
Hitachi Chemical Company, Ltd.
06/25/15
20150179493
new patent

Methods and structures for processing semiconductor devices


Methods of forming semiconductor structures include providing a polymeric material over a carrier substrate, bonding another substrate to the polymeric material, and lowering a temperature of the polymeric material to below about 15° c. To separate the another substrate from the carrier substrate.
Micron Technology, Inc.
06/25/15
20150179488
new patent

Robot with integrated aligner


A robot with an integrated aligner is provided that allows for the alignment of a semiconductor wafer while the semiconductor wafer transits between multiple stations. The robot with an integrated aligner may contain a rotational wafer support configured to rotate and/or translate, one or multiple robotic arms, and a sensor.
Lam Research Corporation
06/25/15
20150179482
new patent

Producing encapsulating layer-covered semiconductor element and producing semiconductor device


A method for producing an encapsulating layer-covered semiconductor element includes a disposing step of disposing a semiconductor element on a support, an encapsulating step of embedding and encapsulating the semiconductor element by an encapsulating layer in an encapsulating sheet including a peeling layer and the encapsulating layer laminated below the peeling layer and made from a thermosetting resin before complete curing, and a heating step of heating and curing the encapsulating layer after the encapsulating step. The heating step includes a first heating step in which the encapsulating sheet is heated under a normal pressure at a first temperature, a peeling step in which the peeling layer is peeled from the encapsulating layer after the first heating step, and a second heating step in which the encapsulating layer is heated at a second temperature that is higher than the first temperature after the peeling step..
Nitto Denko Corporation
06/25/15
20150179481
new patent

Semiconductor device and making embedded wafer level chip scale packages


A semiconductor device includes a carrier and a plurality of semiconductor die disposed over the carrier. An encapsulant is deposited over the semiconductor die.
Stats Chippac, Ltd.
06/25/15
20150179480
new patent

Method of manufacturing semiconductor device


A method of manufacturing a semiconductor device, includes providing a lead frame including a frame portion, including a through hole penetrating the lead frame, a device forming portion surrounded by the frame portion in plan view, including a die pad, and a semiconductor chip mounted on the die pad; after the providing step, sealing the semiconductor chip with sealing resin by supplying the sealing resin to the device forming portion via a first region of the frame portion in which the through hole is formed in plan view, thereby forming a sealing body sealing the device forming portion and the first region of the frame portion; and after the sealing step, removing a first part of the sealing body located at the first region of the frame portion from the lead frame by inserting a pin into the through hole.. .
Renesas Electronics Corporation
06/25/15
20150179473
new patent

Dual wavelength annealing method and apparatus


Methods and apparatus for thermal processing of semiconductor substrates are described. A solid state radiant emitter is used to provide a field of thermal processing energy.
Applied Materials, Inc.
06/25/15
20150179471
new patent

Method of producing a semiconductor substrate product and etching liquid


A method of producing a semiconductor substrate product, having the steps of: providing an etching liquid containing water, a hydrofluoric acid compound, and a water-soluble polymer; and applying the etching liquid to a semiconductor substrate, the semiconductor substrate having a silicon layer and a silicon oxide layer, the silicon layer containing an impurity, and thereby selectively etching the silicon oxide layer.. .
Fujifilm Corporation
06/25/15
20150179470
new patent

Multi-selective polishing slurry composition and a semiconductor element production method using the same


Provided are a multi-selective polishing slurry composition and a semiconductor element production method using the same. A silicon film provided with element patterns is formed on the uppermost part of a substrate having a first region and a second region.
Industry-university Cooperation Foundation Hanyang University
06/25/15
20150179466
new patent

Method of manufacturing semiconductor device


Provided is a method of manufacturing a semiconductor device. The method includes providing an object to be processed including a multilayer film formed by alternately laminating a first film and a second film having different dielectric coefficients within a processing container of a plasma processing apparatus; and repeatedly performing a sequence including: supplying a first gas including o2 gas or n2 gas, and a rare gas into the processing container and exciting the first gas, supplying a second gas including a fluorocarbon gas or a fluorohydrocarbon gas into the processing container and exciting the second gas, and supplying a third gas including hbr gas, a fluorine-containing gas, and a fluorocarbon gas or a fluorohydrocarbon gas into the processing container and exciting the third gas, so that the multilayer film is etched through a mask..
Tokyo Electron Limited
06/25/15
20150179465
new patent

Ion beam etching system


The disclosed embodiments relate to methods and apparatus for removing material from a substrate. In various implementations, conductive material is removed from a sidewall of a previously etched feature such as a trench, hole or pillar on a semiconductor substrate.
Lam Research Corporation
06/25/15
20150179461
new patent

Method for depositing extremely low resistivity tungsten


Methods for depositing extremely low resistivity tungsten in semiconductor processing are disclosed herein. Methods involve annealing the substrate at various times during the tungsten deposition process to achieve uniform tungsten layers with substantially lower resistivity..
Lam Research Corporation
06/25/15
20150179457
new patent

Method for fabricating semiconductor device with paterned hard mask


A method for fabricating a semiconductor device includes the following steps. First, a first interlayer dielectric is formed on a substrate.
United Microelectronics Corp.
06/25/15
20150179454
new patent

Finfet device having a strained region


A method of fabricating a semiconductor device includes providing a substrate having a fin disposed thereon. A gate structure is formed on the fin.
Taiwan Semiconductor Manufacturing Company, Ltd.
06/25/15
20150179453
new patent

Defective p-n junction for backgated fully depleted silicon on insulator mosfet


Methods for semiconductor fabrication include forming a well in a semiconductor substrate. A pocket is formed within the well, the pocket having an opposite doping polarity as the well to provide a p-n junction between the well and the pocket.
Commissariat A L'energie Atomique Et Aux Energies Alternatives
06/25/15
20150179447
new patent

Flexible single-crystalline semiconductor device and fabrication methods thereof


Systems and methods herein relate to the fabrication of a single-crystal flexible semiconductor template that may be attached to a semiconductor device. The template fabricated comprises a plurality of single crystals grown by lateral epitaxial growth on a seed layer and bonded to a flexible substrate.
University Of Houston System
06/25/15
20150179441
new patent

Semiconductor device and manufacturing the same


A semiconductor device is disclosed in which proton implantation is performed a plurality of times to form a plurality of n-type buffer layers in an n-type drift layer at different depths from a rear surface of a substrate. The depth of the n-type buffer layer, which is provided at the deepest position from the rear surface of the substrate, from the rear surface of the substrate is more than 15 μm.
Fuji Electric Co., Ltd.
06/25/15
20150179439
new patent

Method for processing gate dielectric layer deposited on germanium-based or group iii-v compound-based substrate


The present invention discloses a method for processing a gate dielectric layer deposited on a germanium-based or group iii-v compound-based substrate, belonging to a semiconductor device field. The method comprises the steps of depositing a high-k gate dielectric layer on the germanium-based or group iii-v compound-based substrate, and then performing a plasma process to the high-k gate dielectric layer by using fluorine plasma, wherein during the plasma process, a guiding electric field is applied so that fluorine ions, when being accelerated to a surface of the gate dielectric layer, has an energy of 5-50 ev and the fluorine plasma drifts into the high-k gate dielectric layer, a ratio of a density of the fluorine ions in the high-k gate dielectric layer and a density of oxygen atoms in the high-k gate dielectric layer being 0.01-0.15:1.
Peking University
06/25/15
20150179432
new patent

Methods and systems for chemical mechanical polish and clean


The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor structure including a metal gate (mg) layer formed to fill in a trench between two adjacent interlayer dielectric (ild) regions; performing a chemical mechanical polishing (cmp) process using a cmp system to planarize the mg layer and the ild regions; and cleaning the planarized mg layer using a o3/diw solution including ozone gas (o3) dissolved in deionized water (diw).
Taiwan Semiconductor Manufacturing Company, Ltd.
06/25/15
20150179429
new patent

Method for treating surface of semiconductor layer, semiconductor substrate, making epitaxial substrate


A surface treatment method for a semiconductor layer includes growing a first layer on a substrate in a growth reactor, the first layer consisting of one of gallium nitride, aluminum gallium nitride and indium aluminium nitride; growing a second layer of gallium nitride on a surface of the first layer, the gallium nitride of the second gan layer having a composition ratio of gallium to nitrogen larger than 2; taking the substrate out of the growth reactor after growing the second layer; and removing the second layer after taking the substrate out of the growth reactor.. .
Sumitomo Electric Device Innovations, Inc.
06/25/15
20150179427
new patent

Method of manufacturing semiconductor device, and recording medium


A method of manufacturing a semiconductor device includes performing a cycle a predetermined number of times, the cycle including supplying a first precursor containing a specific element and a halogen group to form a first layer and supplying a second precursor containing the specific element and an amino group to modify the first layer into a second layer. A temperature of the substrate is set such that a ligand containing the amino group is separated from the specific element in the second precursor, the separated ligand reacts with the halogen group in the first layer to remove the halogen group from the first layer, the separated ligand is prevented from being bonded to the specific element in the first layer, and the specific element from which the ligand is separated in the second precursor is bonded to the specific element in the first layer..
Hitachi Kokusai Electric Inc.
06/25/15
20150179397
new patent

Microscopy support structures


Electron microscope support structures and methods of making and using same. The support structures are generally constructed using semiconductor materials and semiconductor manufacturing processes.
Protochips, Inc.
06/25/15
20150179306
new patent

Semi-solid unbalanced audio cable


The present disclosure describes implementations of audio cables including a conductor spirally wrapped in a non-conductive thread to centrally position the conductor within a channel comprising mostly air, reducing propagation delay and self-inductance compared to cables utilizing non-air dielectric materials that completely surround the conductor. A coaxial cable includes a first conductor having a first diameter, and a non-conductive thread spirally wrapped around the center conductor, the non-conductive thread having a second diameter.
Belden Inc.
06/25/15
20150179286
new patent

System in a package (sip)


A system in a package (sip) includes a first semiconductor die having a nonvolatile memory and trim/repair circuitry, and a second semiconductor die having a volatile memory and trim/repair circuitry. The first and the second semiconductor die are in a same package.
06/25/15
20150179283
new patent

Semiconductor devices and semiconductor systems including the same


Semiconductor device includes a first data input/output (i/o) portion suitable for storing data inputted thereto through a first pad in a first cell block in synchronization with a test data strobe signal or a first data strobe signal and suitable for outputting the data stored in the first cell block to the first pad, a second data i/o portion suitable for storing data inputted thereto through a second pad in a second cell block in synchronization with the test data strobe signal or a second data strobe signal and suitable for outputting the data stored in the second cell block to the second pad, and a connection portion suitable for electrically connecting the first and second pads to each other in a test mode. Related semiconductor systems are also provided..
Sk Hynix Inc.
06/25/15
20150179276
new patent

Extended fuse reprogrammability mechanism


An apparatus includes a semiconductor fuse array, disposed on a die, into which is programmed configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses and a second plurality of semiconductor fuses.
Via Alliance Semiconductor Co., Ltd.
06/25/15
20150179266
new patent

Semiconductor memory device and operating method thereof


A semiconductor memory device and an operating method thereof are set forth. The semiconductor memory device includes a memory cell array with a string.
Sk Hynix Inc.
06/25/15
20150179259
new patent

Electronic device and fabricating the same


An electronic device including a semiconductor memory is provided, wherein the semiconductor memory comprises: a substrate in which first to third regions are provided; first to third trenches formed in the first to third regions, respectively, and having a different line width from each other; and first to third device isolation layers formed in the first to third trenches, respectively, wherein the first device isolation layer includes a stack structure of a first insulation layer and a second insulation layer, the second device isolation layer includes the first insulation layer formed over a part of a bottom and one sidewall of the second trench, the second insulation layer having a stepped type and a third insulation layer which is formed over the second insulation layer, and the third device isolation layer includes a stack structure of the first to third insulation layers.. .
Sk Hynix Inc.
06/25/15
20150179250
new patent

Access signal adjustment circuits and methods for memory cells in a cross-point array


Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed beol directly on top of a feol substrate that includes data access circuitry. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements disposed among word lines and subsets of bit lines, and an access signal generator.
Unity Semiconductor Corporation
06/25/15
20150179249
new patent

Semiconductor devices and integrated circuits including the same


A first semiconductor device equalizes levels of a bit line and a complementary bit line of a high-order bit line pair in a first memory block using a first drive voltage signal whose level is controlled when a power-down mode or a self-refresh mode is activated according to a level combination of high-order command/address signals. A second semiconductor device equalizes levels of a bit line and a complementary bit line of a low-order bit line pair in a second memory block using a second drive voltage signal whose level is controlled when the power-down mode or the self-refresh mode is activated according to a level combination of low-order command/address signals..
Sk Hynix Inc.
06/25/15
20150179241
new patent

Semiconductor device


A semiconductor device may include a nonvolatile storage unit, a select signal generation unit suitable for generating a plurality of select signals using a clock, a plurality of storage units suitable for storing data transmitted from the nonvolatile storage unit in response to the plurality of select signals, respectively, and a clock blocking unit suitable for blocking the clock inputted to the select signal generation unit when the data transmitted from the nonvolatile storage unit is the same as the data stored in the plurality of storage units.. .
Sk Hynix Inc.
06/25/15
20150179240
new patent

Sharing resources in multi-dice stacks


Apparatus, systems, and methods for configuring a plurality of stacked semiconductor dice with unique identifiers and identifying a die in the stack using the unique identifier are provided. Additional apparatus and methods are disclosed..
Micron Technology, Inc.
06/25/15
20150179239
new patent

Semiconductor device


A semiconductor device includes a plurality of memory cell region regions with each memory cell region region having a plurality of normal memory cell regions, a dummy memory cell region disposed at one side of the plurality of normal memory cell regions, and another dummy memory cell region disposed at another side of the plurality of normal memory cell regions. The semiconductor device further includes a plurality of circuit regions, each including a control circuit to control a portion of the plurality of normal memory cell regions, the dummy memory cell region, and the other dummy memory cell region.
Sk Hynix Inc.
06/25/15
20150179234
new patent

Semiconductor system and power source chip


A semiconductor system includes a semiconductor package having first and second semiconductor chips and a controller configured to control the first and second semiconductor chips, and a power source chip that is connected to a control line of the semiconductor package, and is configured to supply to the first and second semiconductor chips and the controller, power having different voltage or current levels that correspond to a voltage level of the control line.. .
Kabushiki Kaisha Toshiba
06/25/15
20150179233
new patent

Semiconductor system and power source chip


A semiconductor system includes a semiconductor memory unit configured to store data, a controller configured to control the semiconductor memory unit and operable in one of first and second modes, and a power source unit configured to supply power of varying levels to the controller depending on whether the controller is operating in the first mode or the second mode.. .
Kabushiki Kaisha Toshiba
06/25/15
20150179231
new patent

Semiconductor memory apparatus


A semiconductor memory apparatus may include a program voltage generation block configured to generate a program voltage in response to program codes; a precharge voltage generation block configured to generate a precharge voltage in response to the program codes and addresses; and a main bit line configured to be applied with the program voltage and the precharge voltage.. .
Sk Hynix Inc.
06/25/15
20150179216
new patent

Contamination reduction head for media


A cleaning head for removing contaminants from a data storage media, the cleaning head having a cleaning surface comprising a self-assembled monolayer, with the cleaning surface leading a read/write transducer. The self-assembled monolayer is selected so as to have a terminal functional group that has a high affinity to the contaminant(s) desired to be attracted and/or removed..
Seagate Technology Llc
06/25/15
20150179209
new patent

Plasmonic transducer having two metal elements with a gap disposed therebetween


A plasmonic transducer includes at least two metal elements with a gap therebetween. The metal elements are elongated along a plasmon-enhanced, near-field radiation delivery axis.
Seagate Technology Llc
06/25/15
20150179208
new patent

Optical information reproducing device


An optical information reproducing device, takes advantage of holography and can precisely detect a well-known pattern disposed at a prescribed location within a page and is used for correcting position deviation, rotation deviation, and magnification deviation. The optical fiber reproducing device includes a detection unit that detects the position information of a marker as a well-known pattern from a page as a 2-dimensional reproduction signal from a hologram, a detection error position estimating unit that estimates presence/absence of detection error in the position information of the marker and estimates the position where the detection error occurs if there is detection error, a position correcting unit that corrects the marker position information of the detection error position specified by the detection error position estimating unit, and a signal detection unit that detects each signal from within the page based on the corrected marker position information..
Hitachi Consumer Electronics Co., Ltd.
06/25/15
20150179199
new patent

Optical devices including layers that wrap the near field transducer (nft)


A device having an air bearing surface (abs), the device including a near field transducer (nft), the nft having at least a portion thereof at the abs; a first wrap layer, the first wrap layer surrounding at least a portion of the nft, the first wrap layer having a thickness of not greater than about 30 nanometers (nm), and the first wrap layer being made of a material that has a refractive index (n) that is not greater than 2.0; a second wrap layer, the second wrap layer surrounding at least a portion of the first wrap layer, the second wrap layer having a thickness that is not greater than 100 nm, and the second wrap layer being made of a material that has a refractive index (n) that is at least about 1.9; and a top cladding layer surrounding at least a portion of the second wrap layer, the top cladding layer being made of a material that has a refractive index (n) that is not greater than 2.0.. .
Seagate Technology Llc
06/25/15
20150179194
new patent

Devices including at least one intermixing layer


Devices that include a near field transducer (nft), the nft including a peg having five surfaces, the peg including a first material, the first material including gold (au), silver (ag), aluminum (al), copper (cu), ruthenium (ru), rhodium (rh), iridium (ir), or combinations thereof; an overlying structure; and at least one intermixing layer, positioned between the peg and the overlying structure, the at least one intermixing layer positioned on at least one of the five surfaces of the peg, the intermixing layer including at least the first material and a second material.. .
Seagate Technology Llc
06/25/15
20150179191
new patent

Universal magnetic recording head chip


An apparatus according to one embodiment includes a magnetic head having, on one module thereof, an array of n first data transducers positioned towards a media facing surface of the module, and m second data transducers interleaved with the array of first transducers. Only some of the data transducers are coupled to pads.
International Business Machines Corporation
06/25/15
20150179177
new patent

Decoder, decoding method, and computer program product


According to an embodiment, a decoder searches a finite state transducer and outputs an output symbol string corresponding to a signal that is input or corresponding to a feature sequence of signal that is input. The decoder includes a token operating unit and a duplication eliminator.
Kabushiki Kaisha Toshiba
06/25/15
20150179140
new patent

Display device


A display device in which an image with a wide color reproduction range and bright red can be displayed is provided. The display device is a display device such as, for example, a liquid crystal display device, a cathode ray tube, an organic electroluminescent display device, a plasma display panel, and a field emission display.
Sharp Kabushiki Kaisha
06/25/15
20150179093
new patent

Color conversion apparatus and non-transitory computer readable medium


A conversion apparatus, includes: a target value setting unit that sets a target value for color reproduction at the time when output image data is displayed on a display device, the target value is set by using a first target value set based on a display characteristic of the display device and a second target value set by designating targets of hue and saturation with respect to a gray image; a conversion relation creation unit that creates a conversion relation based on the set target value; and an output image creation unit that performs color conversion processing on an input image data using the conversion relation to creates the output image data, in which the second target value is set to suppress variation of color representation.. .
Fuji Xerox Co., Ltd.
06/25/15
20150179047
new patent

System and detecting hand hygiene compliance


A device configured to be disposed on or proximate to a dispenser and to detect hand hygiene compliance is provided. The device includes a proximity detection device configured to detect a location and an identifier of a caregiver within a proximity of the device.
General Electric Company
06/25/15
20150179015
new patent

Vending machine advertising system


A system for displaying advertising to consumers includes: a display panel; a product dispenser configured to dispense a plurality of products; a computer system including a processor, memory, and a storage device, the computer system being configured to: display a plurality of advertisements on the display panel, the advertisements being stored on the storage device; receive a selection of a selected product from among the plurality of products; and control the product dispenser to dispense the selected product, wherein at least one of the plurality of advertisements is unrelated to the plurality of products.. .
Mclaren Llc


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