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 Magnetic field protecting and screening multi-layer textile construction patent thumbnailnew patent Magnetic field protecting and screening multi-layer textile construction
A laminated double-layer textile product comprises a square mesh ferromagnetic alloy metal filament or thread technical fabric layer coupled to a square mesh synthetic monofilament technical fabric layer by laminating to provide a diffused joining of said two layers, said laminating comprising a hot-melt laminating.. .
Saati S.p.a.


 Cover for an electronic module patent thumbnailnew patent Cover for an electronic module
A cover for an electronic module that has a housing holding a electrical component and a circuit board for operating the electrical component includes a cover plate having an interior surface and an exterior surface. The cover plate has a dielectric body.
Tyco Electronics Corporation


 Selective segment via plating process and structure patent thumbnailnew patent Selective segment via plating process and structure
A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is applied to a conductive layer of an inner core and then stripped off after an electroless plating process.
Multek Technologies Ltd.


 Selective segment via plating process and structure patent thumbnailnew patent Selective segment via plating process and structure
A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is plugged into an inner core through hole and then stripped off after an electroless plating process.
Multek Technologies Ltd.


 Transparent substrate including fine metal line and  manufacturing the same patent thumbnailnew patent Transparent substrate including fine metal line and manufacturing the same
The present disclosure relates to a transparent substrate including: a resin pattern layer including a plurality of grooves respectively including side surfaces and a bottom surface; and, a conductive layer formed within the grooves, wherein a line width of the conductive layer is 0.1 μm to 3 μm and an average height of the conductive layer is 5% to 50% of a maximum depth of each of the grooves, and a manufacturing method thereof, such that simplicity in a manufacturing process and a consecutive process are enabled, manufacturing costs are inexpensive, and a transparent substrate having superior electrical conductivity and transparency characteristics is manufactured.. .
Lg Chem, Ltd.


 Method of manufacturing a printed circuit and the corresponding printed circuit patent thumbnailnew patent Method of manufacturing a printed circuit and the corresponding printed circuit
The manufacturing method gives the possibility of manufacturing a printed circuit comprising an electrically insulating substrate and electrically conductive elements borne by the substrate. The manufacturing method comprises the manufacturing of the insulating substrate and of the conductive elements together by additive manufacturing..
Thales


 Printed circuit board structure patent thumbnailnew patent Printed circuit board structure
The invention relates to a printed circuit board structure with at least one dielectric insulating layer and at least one conductive layer, in which within the at least one insulating layer, a layer made of a dielectric thermally conductive material is provided that is located at least in the vicinity of, or in contact with, an inner conductor arrangement. Another thermally conductive layer, preferably an electrically conductive metal layer, can be provided in the immediate vicinity of, or in contact with, the layer made of a dielectric thermally conductive material.
At&s Austria Technologie & Systemtechnik Aktiengesellschaft


 Ground system for high voltage semiconductor valve patent thumbnailnew patent Ground system for high voltage semiconductor valve
A high voltage valve arrangement includes a high voltage valve unit; an external electric shield structure arranged at least partially around the high voltage modular valve unit and a grounding system. The grounding system includes a grounding system configured to be remotely extended from a retracted position to an extended position, whereby the extendable grounding device establishes electric connection with the external shield structure when it is extended from the retracted position..
Abb Technology Ltd


 Led power source current control device patent thumbnailnew patent Led power source current control device
The purpose of the present invention is to provide an led power source current control device having a high power factor and a low total harmonic distortion (thd) for supplying current to an led by a semiconductor chip which uses a current distribution scheme, not a switching scheme. To this end, the present invention provides an led power source current control device comprising: a current control device for controlling over-current to be output as a constant voltage when input voltage is input as an overvoltage; a rectification unit for outputting a rectified voltage by rectifying an ac voltage which is output from the current control device; a constant voltage output unit connected to the output end of the rectification unit to protect the led from the overvoltage and to output constant voltage or more; a current distribution unit for receiving the rectified voltage and dividing a current corresponding to the magnitude of the rectified voltage to output the current; and a connector connected to one or more leds to supply current, which is output from the constant voltage output unit and the current distribution unit, to the leds..
Hyunjoo Idc Co., Ltd.


 Light-emitting device patent thumbnailnew patent Light-emitting device
A light-emitting device includes an insulating carrier; a light-emitting array formed on the insulating carrier including a first light-emitting circuit having a first light-emitting unit, wherein the first light-emitting circuit is a one-way circuit, a second light-emitting circuit having a second light-emitting unit, wherein the second light-emitting circuit is a one-way circuit, a first conductive layer, a second conductive layer, and a third conductive layer, wherein the first light-emitting circuit is formed between the first conductive layer and the second conductive layer and connects with them electrically, the second light-emitting circuit is formed between the second conductive layer and the third conductive layer and connects with them electrically, wherein an area of the second conductive layer is greater or equal to 1.9×103 μm2.. .
Epistar Corporation


new patent

Microwave heating apparatus


A microwave heating apparatus comprises: a housing, arranged to define a cavity; a semiconductor rf generator, configured to provide at least one rf signal; and a plurality of rf antennas, arranged in a distributed way within the cavity and configured to radiate the at least one rf signal from the semiconductor rf generator, such that items received in the cavity are dielectrically heated by the radiation.. .
Wayv Technologies Limited


new patent

Temperature measurement system employing an electromagnetic transponder and separate impedance-changing parasitic antenna


Temperature measurement systems (20) include a temperature sensor (22) and an electronic signal interrogator (24). The temperature sensor (22) has a transponder (26) equipped with an antenna (28), and a separate parasitic antenna (32) with a temperature-sensitive transducer (34, 68-74, 78a-84a), while the interrogator (24) has a transmitter (42) and antenna (40).
Tsi Technologies Llc


new patent

Induction heating system


The present invention intends to run one induction heating apparatus using a three-phase ac power supply without use of a scott connection transformer while preventing an occurrence of a phase where no current flows. An induction heating system uses the three-phase ac power supply to run the induction heating apparatus including an induction heating coil, and has an intermediate apparatus including a coil that is wound on an iron core with an even number of turns, forming a closed magnetic circuit.
Tokuden Co., Ltd.


new patent

Power adjustment method, computer-readable recording medium and power adjustment apparatus


A power adjustment method includes: measuring output power that is obtained when input power to be amplified in a linear region is input to a power amplifier configured to amplify input power linearly in the linear region and amplify input power nonlinearly in a nonlinear region; deriving a straight line connecting a measurement point corresponding to the measured output power and a boundary point between the linear region and the nonlinear region in a coordinate plane representing input/output characteristics; acquiring information on an approximate equation that is stored in advance in correspondence with the measured output power, the approximate equation representing a relation between input power and output power in the nonlinear region; and storing information on the derived straight line and the acquired information on the approximate equation in a semiconductor integrated circuit provided at a preceding stage of the power amplifier.. .
Fujitsu Limited


new patent

Multifunction integrated hearing and communication with noise cancellation and feedback management


Systems, devices and methods for communication include an ear canal microphone configured for placement in the ear canal to detect high frequency sound localization cues. An external microphone positioned away from the ear canal can detect low frequency sound, such that feedback can be substantially reduced.
Earlens Corporation


new patent

Hearing device, particularly hearing aid


A hearing device, particularly a hearing aid, has a housing, a signal processing unit arranged in the housing, a first sound generator disposed in the housing, and a second sound generator. The first sound generator and the second sound generator are configured to convert an output signal from the signal processing unit into sound.
Sivantos Pte. Ltd.


new patent

Sound conductor for a hearing device, main unit of a hearing device and hearing device


A sound conductor for a hearing device, particularly for a hearing aid, includes a housing, at least one sound generator formed by a thermoacoustic transducer, a plurality of signal ports connected to the sound generator, and a securing device for reversible securing to a main unit of the hearing device to produce an electrical connection between at least one signal port and a signal output of the main unit. The housing has a sound channel formed therein to conduct sound generated by the sound generator in a direction of propagation to a sound output of the housing.
Sivantos Pte. Ltd.


new patent

Mems-based speaker implementation


A micro-electromechanical system (mems) device that comprises a substrate, support structures, functional elements and conductive paths that comprise conductive elements; wherein the functional elements are included in a plurality of functional layers, the plurality of functional layers are spaced apart from each other; wherein the support structures are configured to provide structural support to the plurality of functional layers; wherein each functional layer is coupled to a conducting interface via a conductive path that is associated with the functional layer; and wherein the support structures comprise lateral etch stop elements.. .
Dsp Group Ltd.


new patent

System and an acoustic transducer and environmental sensor package


According to an embodiment, a transducer package includes a circuit board including a port, a lid disposed over the port, an acoustic transducer disposed over the port and including a membrane, and an environmental transducer disposed at the circuit board in the port. The lid encloses a first region, and the membrane separates the port from the first region.
Infineon Technologies Ag


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new patent

Transducer system


A transducer system including a panel having one or more piezo-electric enabled foils and an arrangement of electric contacts coupled to the panel and configured to define a plurality of transducers thereon. Each transducer is associated with a respective region of the panel and with at least two electric contacts that are coupled to at least two zones at that respective region of the panel.
Noveto Systems Ltd.


new patent

Transducer components and structure thereof for improved audio output


Embodiments are provided for components configured for audio playback. According to certain aspects, a transducer includes dual voice coils disposed in a magnet section, whereby the magnet section generates an electromagnetic field that causes the dual voice coils to actuate in response to an applied audio signal.
Google Inc.


new patent

Magnetic shielding and communication coil


A magnetic coil is described. In an example, an apparatus comprises a layer of porous material and a magnetic coil.
Microsoft Technology Licensing, Llc


new patent

Sound masking apparatus and sound masking method


A sound masking apparatus includes a reproduction processor configured to detect periodicity in a masker sound and add a delay to the masker sound in accordance with a detection result of the periodicity. The sound masking apparatus can prevent an unbalanced sound pressure distribution of masker sounds within an acoustic space without causing discomfort to a listener..
Yamaha Corporation


new patent

Acoustic apparatus with side port


An apparatus includes a microphone and a gasket. The microphone includes a base having an inner surface and an outer surface.
Knowles Electronics, Llc


new patent

Sound system with improved adjustable directivity


The disclosure includes a sound system comprising at least one digital signal processor control module, acting on a signal to the high-frequency transducer and on a signal to a mid-frequency transducer so as to apply, in a common frequency range, at least one magnitude parameter as well as at least one phase parameter so as to produce a directivity along the same angular sector as a directivity produced by the orientable shutters.. .
L-acoustics


new patent

Vibration headphones


Vibration headphones of the present technology include a first housing including an electroacoustic transducer configured to output a sound wave that is generated based on an audio signal fed to a first channel (right channel) and a first vibration driver configured to vibrate by converting an audio signal into mechanical vibration, and a second housing including an electroacoustic transducer configured to output a sound wave that is generated based on an audio signal in a second channel (left channel) and a second vibration driver configured to vibrate by converting an audio signal into mechanical vibration. Resonant frequencies of the first and the second vibration drivers are set in such a way that, when both the first and the second vibration drivers vibrate, at least two resonant frequencies appear in the vibrations of the first and the second vibration drivers..
Panasonic Intellectual Property Management Co., Ltd.


new patent

Portable communication device with flow through acoustic transducer ports for water management


Communication device includes a housing with a two or more apertures defined therein to form a speaker grille. The apertures are arranged to form one or more aperture sets, each comprised of at least two apertures connected by a fluid channel defined on an internal face of the panel.
Harris Corporation


new patent

Apparatus and playback of audio-visual recordings


An imaging system comprising a panoramic visual image display, an associated directional sound playback device, and an associated motion reproduction device is disclosed. The imaging system conveys visual, sound and motion information related to a particular viewing direction to provide a realistic experience for the viewer.
360fly, Inc.


new patent

Image sensor and driving image sensor


Provided are an image sensor compensating for property degradation of a metal-oxide-semiconductor (mos) resulting from a threshold voltage shift that may occur when photodiodes and a mos circuit of configuring an amplifier are integrated on the same substrate, and a method for driving the image sensor.. .
Samsung Electronics Co., Ltd.


new patent

Electronic device, imaging device, image reproduction method, image reproduction program, recording medium with image reproduction program recorded thereupon, and image reproduction device


An electronic device includes: a communication unit that performs communication with an external device; and a control unit that issues a command to the external device via the communication unit, on the basis of at least one of capacity of the external device, and capacity of the electronic device.. .
Nikon Corporation


new patent

Noise-shaping crest factor reduction with polyphase transforming


Apparatus, system and method relates generally to data communication with noise-shaping crest factor reduction using polyphase transformation. In such a method, a composite signal is received by a delay and a waveform generator.
Xilinx, Inc.


new patent

Method and controlling smart home system


The present disclosure relates to a sensor network, machine type communication (mtc), machine-to-machine (m2m) communication, and internet of things technology. The present disclosure may be applied to intelligent services based on the above technologies, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services.
Samsung Electronics Co., Ltd.


new patent

One-to-many matching with application to efficient privacy-preserving re-identification


Authentication methods are disclosed for determining whether a person or object to be authenticated is a member of a set of authorized persons or objects. A query signature is acquired comprising a vector whose elements store values of an ordered set of features for the person or object to be authenticated.
Xerox Corporation


new patent

Tunable laser including parallel lasing cavities with a common output


A parallel cavity tunable laser generally includes a semiconductor laser body defining a plurality of parallel laser cavities with a common output. Each of the parallel laser cavities is configured to be driven independently to generate laser light at a wavelength within a different respective wavelength range.
Applied Optoelectronics, Inc.


new patent

Portable terminal


A portable terminal includes an antenna, a communication unit, an n-bit counter, and a gain change unit. The communication unit has two modes of an active mode in which the communication unit itself outputs carrier waves and a passive mode in which carrier waves output from another device are used, and is configured to attempt communication through electromagnetic induction by using the antenna with switching between the two modes being alternately made and to communicate without switching between the modes while communication is established.
Kyocera Corporation


new patent

Semiconductor device


A semiconductor device according to an embodiment comprises a first terminal receiving a high-frequency signal as an input and a second terminal outputting the high-frequency signal. A first switching part is provided on a path of the high-frequency signal between the first terminal and the second terminal.
Kabushiki Kaisha Toshiba


new patent

Transmitter circuit, semiconductor apparatus and data transmission method


The transmitter circuit according to one embodiment includes a pulse generating circuit generating a pulse signal based on edges of input data, a first output driver outputting, based on the pulse signal, a first output pulse signal according to one of the edges to a first end of an external insulating coupling element, a second output driver outputting, based on the pulse signal, a second output pulse signal according to other one of the edges to a second end of the insulating coupling element, and an output stop circuit stopping the first and second output pulse signals from being output for a prescribed period from when a power supply voltage is turned on.. .
Renesas Electronics Corporation


new patent

Semiconductor device


[problem] to provide an input receiver making it possible to obtain adequate gain with respect to a broad reference potential level. [solution] the present invention is provided with a differential circuit (110) and a current-supplying circuit (120).
Ps4 Luxco S.a.r.l.


new patent

Driver for normally on iii-nitride transistors to get normally-off functionality


A semiconductor device includes a depletion mode gan fet and an integrated driver/cascode ic. The integrated driver/cascode ic includes an enhancement mode cascoded nmos transistor which is connected in series to a source node of the gan fet.
Texas Instruments Incorporated


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new patent

Analog switch having reduced gate-induced drain leakage


In an example, an apparatus includes an analog switch having an n-type metal oxide semiconductor (nmos) circuit in parallel with a p-type metal oxide semiconductor (pmos) circuit between a switch input and a switch output. The analog switch is responsive to an enable signal that determines switch state thereof.
Xilinx, Inc.


new patent

Semiconductor switch


In an embodiment, semiconductor switch includes first switches switching conduction between input-output nodes and a common node. One of the first switches includes a plurality of first transistors connected in series between an input and output node and the common node.
Kabushiki Kaisha Toshiba


new patent

Semiconductor device


A semiconductor device includes a clock supplying unit that independently supplies clocks to a plurality of bus slaves and a plurality of bus masters. The number of waits in accordance with an operating frequency can be set for each bus slave such as a memory.

new patent

Dead time control


Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors.
Peregrine Semiconductor Corporation


new patent

Level shifter


Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors.
Peregrine Semiconductor Corporation


new patent

Elastic wave device


An elastic wave device includes a multilayer film provided on a support substrate and including a piezoelectric thin film and a layer other than the piezoelectric thin film, an interdigital transducer electrode provided on one surface of the piezoelectric thin film, and an external connection terminal electrically connected to the interdigital transducer electrode. In a plan view, the multilayer film is partially absent or omitted in a region outside a region where the interdigital transducer electrode is provided, and the elastic wave device further includes a first insulating layer provided on the support substrate in at least a portion of a region where the multilayer film is absent or omitted..
Murata Manufacturing Co., Ltd.


new patent

Narrowing audio filter transition band


An apparatus including a first audio filter; a first transducer connected to the first audio filter; and a first sound attenuator located relative to the first transducer to attenuate sound from the first transducer. The first audio filter includes a first transition frequency band.
Nokia Technologies Oy


new patent

Semiconductor integrated circuit device


A device includes an operational-amplifier including an amplifier-part amplifying signals and transmitting amplified signals to a first and a second nodes, and an output-part connected to the first and second nodes and outputting signals from a first and a second outputs. The device includes a first and a second chopper switches and a first and second phase-compensation capacity elements.
Kabushiki Kaisha Toshiba


new patent

Multi-mode integrated front end module


Systems and methods are disclosed for a multi-mode radiofrequency (rf) module comprising a semiconductor die and a power amplifier residing on the die. The power amplifier is configured to operate in a first rf mode corresponding to a first rf wireless technology standard and a second rf mode corresponding to a second rf wireless technology standard.
Skyworks Solutions, Inc.


new patent

Methods of auto tuning machine parameters and systems thereof


In one example embodiment, a method includes determining a first adjustment value for a slip frequency of a rotor in an induction motor, determining a second adjustment value for an inductance of the induction motor and tuning the slip frequency of the rotor and the inductance of the induction motor based on the first adjustment value and the second adjustment value, respectively.. .

new patent

Power generating device and an object for utilizing the power generating device


The present invention provides a power generating device, comprising a first shell, a sensor module, a second shell, a magnetic module and a cover. The sensor module is disposed in the first hollow portion.

new patent

Converter for converting energy to be recovered and electricity generator


A converter for converting a variation in energy to be recovered, the converter including: a transducer layer extending essentially parallel to a reference plane and configured to transform the variation in the energy to be recovered into a mechanical deformation, the transducer layer comprising: a plurality of first blocks made from a magnetostrictive or shape-memory material, the first blocks being delimited in relation to one another by side edges, and regions that do not contain the material of the first block, the regions being inserted between the side edges of the first blocks; and a piezoelectric layer secured to the transducer layer. Each of the first blocks has a preferential axis of deformation parallel to the reference plane..
Centre National De La Recherche Scientifique


new patent

Converter for converting a variation in energy to be recovered into a potential difference


A converter including a first transducer that can lengthen inside at least a first deformation zone and simultaneously shrink inside at least a different second deformation zone. Inner faces of second and third electromechanical transducers are secured respectively, with no degree of freedom, substantially to the first and second deformation zones of the layer of the first transducer.
Institut Polytechnique De Grenoble


new patent

Unit current transformer device and magnetic induction power supplying device for linearly controlling output power by using the same


The present invention relates to a unit current transformer device and a magnetic induction power supplying device, and particularly to a magnetic induction power supply unit capable of linearly adjusting output power according to the number of unit current transformer devices configured to have a specific resonance frequency. To this end, the unit current transformer device includes a current transformer inducing secondary current from primary current flowing through a line in a magnetic induction manner and having a resonant frequency double or greater than that of the primary current, and a converting unit converting an output of the current transformer to dc power..
Tera Energy System Solution Co. Ltd


new patent

Power converter


A power converter that can be made compact and lightweight is provided. The power converter includes a control circuit power supply, a power semiconductor module that includes power conversion elements, a control circuit board that operates with power from the control circuit power supply and controls the power conversion elements, and a capacitor connected to the power conversion elements.
Hitachi, Ltd.


new patent

High speed, efficient sic power module


A power converter module includes an active metal braze (amb) substrate, power converter circuitry, and a housing. The amb substrate includes an aluminum nitride base layer, a first conductive layer on a first surface of the aluminum nitride base layer, and a second conductive layer on a second surface of the aluminum nitride base layer opposite the first surface.
Cree, Inc.


new patent

Protection circuit for semiconductor switching element, and power conversion device


Upon turn-off of igbt, by suppressing variations in collector-emitter voltage between igbts connected in series, risk of breaking igbt due to overvoltage breakdown can be reduced. In protection circuit provided for each of the plurality of igbts 50 connected in series, between collector and emitter of igbt 50, avalanche elements d1˜d5, resistance r4 and avalanche element d6 are sequentially connected in series.
Meidensha Corporation


new patent

Linear induction generator using magnetic repulsion


An electrical generator, comprising: a stator having a coil and a lift magnet coupled by a lever to an induction magnet, the induction magnet moveable longitudinally within the coil, the lever configured to move the induction magnet a multiple of a distance that the lift magnet is moved; and, a rotor moveable with respect to the stator, the rotor having a rotor magnet, the rotor magnet and the lift magnet positioned with respective magnetic moments opposing; whereby movement of the rotor magnet toward the lift magnet causes the lift magnet to move away from the rotor magnet which in turn causes, by operation of the lever, the induction magnet to move within the coil to generate a first electromotive force therein.. .

new patent

Multiphase induction motor with flux weakening


An electrical induction motor may include a stator with a plurality of circumferentially spaced slots, and n windings installed in the slots and each configured to be connected between two current inputs from an inverter, with a phase angle difference between the two current inputs equal to h×180°/n, wherein h=a harmonic of a current drive waveform supplied by the inverter to the windings. Each of the n windings may be installed in the plurality of slots to form a top layer of winding and a bottom layer of winding, with a phase angle of the current flowing through the top layer of winding in each slot being aligned with a phase angle of current flowing through the bottom layer of winding at a first, higher harmonic, and out of alignment at a second, lower harmonic..
Caterpillar Inc.


new patent

Apparatus for transmitting data and energy between two objects moving relative to one another


The invention relates to an apparatus for the transmission of data and energy between two objects moving relative to one another about a common axis of rotation. The objects each comprise coils which are disposed opposite and are spaced apart axially with respect to the axis of rotation such that an energy transmission between the coils is possible by inductive coupling.
Sick Ag


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new patent

Semiconductor device, power source unit, and electrical device


A semiconductor device includes a first signal outputting portion; a second signal outputting portion; and a voltage outputting portion. The first signal outputting portion compares a first voltage output from a first power source and a second voltage output from a second power source, and to output a comparison result.
Lapis Semiconductor Co., Ltd.


new patent

Power supply system


A chip set is configured such that a first overcurrent signal that is output at the time when there is an overcurrent in a first semiconductor switch or a third semiconductor switch and a second overcurrent signal that is output at the time when there is an overcurrent in a second semiconductor switch or a fourth semiconductor switch are input to input ports of an arithmetic processing unit.. .
Toyota Jidosha Kabushiki Kaisha


new patent

Surface-emitting laser, surface-emitting laser array, laser apparatus, ignition device and internal combustion engine


A surface-emitting laser includes a plurality of semiconductor layers; an active layer; and spacer layers, between which the active layer is held. The active layer includes a first layer including aluminum gallium indium arsenide ((alxga1-x)yin1-yas, where x and y are greater than or equal to zero but less than one), and a second layer including aluminum gallium indium arsenide ((almga1-m)nin1-nas, where m and n are greater than or equal to zero but less than one, and at least one of m-x and n-y is not zero).
Ricoh Company, Ltd.


new patent

Surface emitting semiconductor laser device


There is provided a surface emitting semiconductor laser including: a substrate; and a semiconductor layer including: a first semiconductor multilayer film having plural sets of specific layers, a second semiconductor multilayer film having plural sets of specific layers, and an active layer provided between them, so as to constitute a resonator.. .
Fuji Xerox Co., Ltd.


new patent

Monolithic integrated photonics with lateral bipolar and bicmos


After forming a first trench extending through a top semiconductor layer and a buried insulator layer and into a handle substrate of a semiconductor-on-insulator (soi) substrate, a dielectric waveguide material stack including a lower dielectric cladding layer, a core layer and an upper dielectric cladding layer is formed within the first trench. Next, at least one lateral bipolar junction transistor (bjt), which can be a pnp bjt, an npn bjt or a pair of complementary pnp bjt and npn bjt, is formed in a remaining portion of the top semiconductor layer.
International Business Machines Corporation


new patent

Optical semiconductor device and manufacturing the same


A semiconductor light-emitting device according to one embodiment includes a substrate, a first light reflection structure provided in contact with the substrate, a buried layer surrounding the first light reflection structure, an optical semiconductor structure including an active layer, provided above the first light reflection structure, a second light reflection structure provided above the optical semiconductor structure, and a pair of electrodes which supply current to the optical semiconductor structure. The surface of the first light reflection structure and the surface of the buried layer are included in the same plane..
Kabushiki Kaisha Toshiba


new patent

Semiconductor laser element and manufacturing semiconductor laser element


A semiconductor laser element includes: a window region including a disordered portion formed by diffusion of a group-iii vacancy, the diffusion promoted by providing on the window region a promoting film that absorbs a predetermined atom; a non-window region including an active layer of a quantum well structure; and a difference equal to or larger than 50 mev between an energy band gap in the window region and an energy band gap in the non-window region.. .
Furukawa Electric Co., Ltd.


new patent

Optical transmitter emitting light with narrowed linewidth


An optical transmitter that narrows the linewidth of the output light is disclosed. The optical transmitter includes a wavelength tunable laser diode (ld) type of the csg-dr ld integrated with a semiconductor optical amplifier (soa) driven by the constant magnitude mode.
Sumitomo Electric Industries, Ltd.


new patent

Packaging structure and packaging tunable laser device, and tunable laser device


The present disclosure provides a packaging structure and a method of packaging an tunable laser device, and an tunable laser device. The packaging structure of the tunable laser device may include a to tube base and a to tube cap, wherein a first thermal sink is disposed on the to tube base, a semiconductor laser chip is disposed on a vertical side of the first thermal sink, an aspheric lens is disposed on the to tube cap, and the semiconductor laser chip is disposed on a central axis of the aspheric lens; and wherein the vertical side of the first thermal sink is a side of the first thermal sink perpendicular to the to tube base.
Hisense International Co., Ltd.


new patent

Press-fit pin for semiconductor packages and related methods


A press-fit pin for a semiconductor package includes a shaft terminating in a head. A pair of arms extends away from a center of the head.
Semiconductor Components Industries, Llc


new patent

Right angle coaxial cable and connector assembly and forming same


A method of induction soldering an inner conductor of a coaxial cable to an inner contact of a right angle coaxial connector includes: (a) providing a coaxial connector, the coaxial connector including an outer conductor body and an inner contact, the inner contact defining a mating axis, the inner contact further comprising a blind hole with an open end; (b) providing a coaxial cable, the coaxial cable including an inner conductor, a dielectric circumferentially surrounding the inner conductor, and an outer conductor circumferentially surrounding the dielectric; (c) inserting the coaxial cable into the coaxial connector such that an end of the inner conductor is positioned in the blind hole of the inner contact and perpendicular to the mating axis; and (d) heating the blind hole of the inner conductor to melt solder present in the blind hole to form a solder joint between the inner conductor and the inner contact.. .
Commscope Technologies Llc


new patent

Photoelectric conversion device and manufacturing method thereof


A photoelectric conversion device of an embodiment includes: a first photoelectric conversion part including a first transparent electrode, a first organic active layer, and a first counter electrode; and a second photoelectric conversion part including a second transparent electrode, a second organic active layer, and a second counter electrode, which are provided on a transparent substrate. A conductive layer is formed on a partial region, of the second transparent electrode, which is adjacent to the first transparent electrode.
Kabushiki Kaisha Toshiba


new patent

Hybrid organic/inorganic eutectic solar cell


A semiconductor assembly including substantially non-crystalline substrate having a predetermined softening point, a textured buffer layer deposited on said substrate, a polymer film deposited on said buffer layer, and an inorganic or silicon inorganic film deposited on said polymer film. The buffer layer, polymer film, and inorganic or silicon inorganic film are each deposited at a respective deposition temperature that is below the softening point of the substrate.
Solar-tectic Llc


new patent

Conjugated polymers


The invention relates to novel conjugated polymers containing one or more diindeno-thieno[3,2-b]thiophene based polycyclic repeating units, to methods for their preparation and educts or intermediates used therein, to polymer blends, mixtures and formulations containing them, to the use of the polymers, polymer blends, mixtures and formulations as organic semiconductors in organic electronic (oe) devices, especially in organic photovoltaic (opv) devices and organic photodetectors (opd), and to oe, opv and opd devices comprising these polymers, polymer blends, mixtures or formulations.. .
Merck Patent Gmbh


new patent

Organic semiconductor compound and manufacturing the same


An organic semiconductor compound and a method for manufacturing the same is provided. The method for manufacturing the organic semiconductor compound may include stirring a solated organic semiconductor and a solated organometallic precursor.
Soongsil University Research Consortium Techno-park


new patent

Semiconductor device


In a semiconductor device having a magnetic sensor configured to detect a direction of magnetism, stress applied by a magnetic flux concentrator that is a magnetic material is small. The magnetic sensor includes, in combination, hall elements arranged on a surface of a semiconductor substrate, and a magnetic flux concentrator formed of a magnetic material having the function of amplifying magnetism, the magnetic flux concentrator being arranged on the semiconductor substrate, for at least partly covering each of the hall elements.
Sii Semiconductor Corporation


new patent

Power generator


A power generator including a converter with an electromechnical transducer and a magnetostrictive layer to convert a variation of a magnetic field into a mechanical deformation exerted on the transducer. There is a magnetic field source including a group of several permanent magnets.
Institut Polytechnique De Grenoble


new patent

Methods for thick film thermoelectric device fabrication


Solid state thermoelectric energy conversion devices can provide electrical energy from heat flow, creating energy, or inversely, provide cooling through applying energy. Thick film methods are applied to fabricate thermoelectric device structures using microstructures formed through deposition and subsequent thermal processing conditions.
Berken Energy Llc


new patent

Method of manufacturing light emitting device with exposed wire end portions


A light emitting device is constituted with a semiconductor light emitting element on which a support member is disposed on one surface provided with a p-side electrode and an n-side electrode and a fluorescent material layer is disposed on the other surface which is an opposite side of the one surface. The support member includes a resin layer, an electrode for p-side external connection and an electrode for n-side external connection disposed exposed at a surface opposite side of a surface where the resin layer is in touch with a light emitting element, and internal wirings disposed in the resin layer and electrically connecting between a p-side electrode and the electrode for p-side external connection respectively.
Nichia Corporation


new patent

Semiconductor light emitting device


According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first metal pillar, a second metal pillar, and an insulating layer. The semiconductor layer includes a first surface, a second surface, and a light emitting layer.
Kabushiki Kaisha Toshiba


new patent

Light emitting device and manufacturing light emitting device


A light emitting device includes: a semiconductor light emitting element having a sapphire substrate and a semiconductor layer; a mounting board; and a light transmission member, wherein: the sapphire substrate is bonded to the light transmission member by an adhesive material; the semiconductor light emitting element is mounted on the mounting board in the form of a flip-chip; and a roughened peripheral edge part is formed in the sapphire substrate in the mounting board side.. .
Toyoda Gosei Co., Ltd.


new patent

Optoelectronic component, optoelectronic arrangement, producing an optical element, and producing an optoelectronic component


An optoelectronic component includes an optoelectronic semiconductor chip having a radiation-emitting face; and an optical element arranged over the radiation-emitting face, wherein the optical element includes a material in which light-scattering particles are embedded, and a concentration of the embedded light-scattering particles has a gradient forming an angle not equal to 90° with the radiation emission face.. .
Osram Opto Semiconductors Gmbh


new patent

Optoelectronic semiconductor chip and optoelectronic semiconductor component


An optoelectronic semiconductor chip has a non-rectangular, parallelogram-shaped top surface and an active zone, which is at a distance from the top surface and runs parallel to the top surface at least in places. The top surface includes a radiation exit surface, through which electromagnetic radiation generated during operation in the active zone emerges.
Osram Opto Semiconductors Gmbh


new patent

Light emitting diode for surface mount technology, manufacturing the same, and manufacturing light emitting diode module


A light emitting diode (led) includes a substrate, a first semiconductor layer disposed on the substrate, an active layer disposed on a portion of the first semiconductor layer, a second semiconductor layer disposed on the active layer, a reflection pattern disposed on a portion of the second semiconductor layer, and a first insulating layer including a first portion having a first thickness and a second portion having a second thickness different from the first thickness, in which the first portion is disposed on the reflection pattern or the first semiconductor layer and the second portion is disposed on the second semiconductor layer.. .
Seoul Viosys Co., Ltd.


new patent

Semiconductor light-emitting element


A semiconductor light-emitting element includes a substrate having a convex portion protruding therefrom. A first semiconductor layer having a first conductivity type is separated from the substrate in a first direction.
Kabushiki Kaisha Toshiba


new patent

Semiconductor light-emitting element


A semiconductor light-emitting element includes a first layer having a first conductivity. A second layer having a second conductivity is provided between the first layer and a substrate.
Kabushiki Kaisha Toshiba


new patent

Light emitting device and fabricating the same


A light emitting device, includes: a substrate, including a top surface, a bottom surface, a first side surface connecting the top surface and the bottom surface, a first group of deteriorated region, and a second group of deteriorated region; and a semiconductor stack formed on the top surface of the substrate, wherein the first side surface includes a first group of convex region and a first group of concave region, wherein the first group of convex region includes the first group of deteriorated region, and the first group of concave region includes the second group of deteriorated region.. .
Epistar Corporation


new patent

Optoelectronic semiconductor chip and producing optoelectronic semiconductor chips


An optoelectronic semiconductor chip (1) is provided which has a semiconductor body comprising a semiconductor layer sequence (2) with an active region (20) provided for generating and/or receiving radiation, a first semiconductor region (21) of a first conduction type, a second semiconductor region (22) of a second conduction type and a cover layer (25). The active region (20) is arranged between the first semiconductor region (21) and the second semiconductor region (22) and comprises a contact layer (210) on the side remote from the active region.
Osram Opto Semiconductors Gmbh


new patent

Ultraviolet light emitting devices and methods of fabrication


An ultraviolet light emitting semiconductor chip, its use in a led, and methods of its fabrication are disclosed. The semiconductor chip can include a buffer layer of alxga1-xn, where 0<x≦1 having a thickness from about 10 μm to about 3 mm and defining apertures in the thickness of the buffer layer formed due to lateral overgrowth of the buffer layer over a grooved basal substrate.
University Of South Carolina


new patent

Semiconductor light emitting element, manufacturing same, and light emitting device


According to one embodiment, semiconductor light emitting element includes: a substrate having a first surface and a second surface on an opposite side of the first surface; an insulating layer provided on the second surface of the substrate; a first metal layer provided on the insulating layer; a semiconductor light emitting unit provided on the first metal layer, the semiconductor light emitting unit including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer, the second semiconductor layer being electrically connected to the first metal layer; and a first electrode layer provided on the first surface of the substrate, the first electrode layer extending in the substrate and in the insulating layer, and the first electrode layer being electrically connected to the first metal layer.. .
Kabushiki Kaisha Toshiba


new patent

Semiconductor layer sequence and producing the same


A semiconductor layer sequence includes an n-conducting n-type side, a p-conducting p-type side, and an active zone between the sides, the active zone simultaneously generating a first radiation having a first wavelength and a second radiation having a second wavelength, the active zone including at least one radiation-active layer having a first material composition that generates the first radiation, the at least one radiation-active layer is oriented perpendicular to a growth direction of the semiconductor layer sequence, the active zone includes a multiplicity of radiation-active tubes having a second material composition and/or having a crystal structure that generates the second radiation, which crystal structure deviates from the at least one radiation-active layer, and the radiation-active tubes are oriented parallel to the growth direction, the radiation-active tubes having an average diameter of 5 nm to 100 nm and an average surface density of the radiation-active tubes of 108 1/cm2 to 1011 1/cm2.. .
Osram Opto Semiconductors Gmbh


new patent

Semiconductor structures having active regions comprising ingan and methods of forming such semiconductor structures


Semiconductor structures include an active region between a plurality of layers of ingan. The active region may be at least substantially comprised by ingan.
Soitec


new patent

Method for manufacturing heterostructures for middle infrared band, a heterostructure, and a light-emitting diode and a photodiode based thereon


The present invention relates to producing spontaneous radiation sources based on aiiibv semiconductor compounds in 2.6-4.7 μm spectral range, and to manufacturing photosensitive structures for 2.0-4.7 μm spectral range. In the first embodiment, the heterostructure comprises a substrate containing inas, a barrier layer containing insbp and arranged on the substrate, and an active layer containing inassbp and arranged on the barrier layer.
Limited Liability Company "led Microsensor Nt"


new patent

Semiconductor light emitting device


According to one embodiment, a semiconductor light emitting device includes a base body, first to sixth semiconductor layers, first to third conductive layers, a structure, and a first insulating layer. The first semiconductor layer and the structure are separated from the base body in a first direction.
Kabushiki Kaisha Toshiba


new patent

Method of manufacturing semiconductor chips


A method of manufacturing semiconductor chips includes: forming grooves on a front face side of a substrate; and forming grooves on a back face side of the substrate as defined herein, and in manufacturing conditions in which a variation range of a top section of the cutting member having a tapered tip end shape with no top face in the groove width direction changes from a range included in the groove on the front face side to a range away from the groove on the front face side as wear of the cutting member advances, the use of the cutting member is stopped before the variation range changes from the range included in the groove on the front face side to the range away from the groove on the front face side.. .
Fuji Xerox Co., Ltd.


new patent

Semiconductor light-emitting element and manufacturing method thereof


A semiconductor light-emitting element includes a substrate having a first side and a second side, a first semiconductor layer of a first conductivity type on the first side of the substrate, a second semiconductor layer of a second conductivity type between the substrate and the first semiconductor layer, a third semiconductor layer between the first semiconductor layer and the second semiconductor layer, and a metal layer between the substrate and the second semiconductor layer. The substrate has a first surface on the first side facing the metal layer and a second surface on the second side opposite to the first surface, and the second surface is convex..
Kabushiki Kaisha Toshiba


new patent

Insulated-gate photoconductive semiconductor switch


This present invention provides a novel photoconductive semiconductor switch (pcss) comprising: a semi-insulating substrate, an anode formed on the upper surface of said semi-insulating substrate, a first n-type doped layer formed on the lower surface of said semi-insulating substrate, a p-type doped layer formed on said first n-type doped layer, a second n-type doped layer formed on said p-type doped layer, a cathode formed on said second n-type doped layer, several recesses facing towards said first n-type doped layer and vertically extending into a part of said first n-type doped layer, an insulating layer formed on said second n-type doped layer and on the walls and the bottoms of said recesses, a gate electrode consisting of two parts, one part of the which formed on said insulating layer on the walls and the bottoms of recesses, and the other part of the which formed on a part of the insulating layer on the second n-type doped layer for electrically connecting the part of the gate electrode on the recesses, wherein the cathode and the gate electrode are electrically isolated.. .
The Board Of Trustees Of The University Of Illinois


new patent

Semiconductor photoreceiving device


According to one embodiment, a semiconductor photoreceiving device includes a substrate, a first structural layer provided on the substrate, in which light enters from the substrate side and in which a refractive index changes periodically, a semiconductor layer provided on the first structural layer and including an optical absorption layer, a reflective layer provided on the semiconductor layer, and a pair of electrodes configured to apply voltage to the optical absorption layer.. .
Kabushiki Kaisha Toshiba


new patent

Semiconductor photo-detecting device


An ultraviolet (uv) photo-detecting device, including: a substrate; a first nitride layer disposed on the substrate; a second nitride layer disposed between the first nitride layer and the substrate; a light absorption layer disposed on the first nitride layer; and a schottky junction layer disposed on the light absorption layer.. .
Seoul Viosys Co., Ltd.


new patent

Solar cell


Disclosed is a solar cell including a semiconductor substrate, a first conductive area disposed on one surface of the semiconductor substrate, the first conductive area being of a first conductive type, a second conductive area of a second conductive type opposite to the first conductive type, a first electrode connected to the first conductive area, and a second electrode connected to the second conductive area. At least one of the first conductive area and the second conductive area is formed of a metal compound layer..
Lg Electronics Inc.


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new patent

Partly-transparent thin-film solar module


The present invention concerns a method for the manufacture of a partially transparent thin-layer solar module in which the opaque layers (primarily the semiconductor layer and the back contact layer) comprise defined surface regions which lack the material of these layers. These surface regions which are free of material may be produced by not coating them during manufacture or by retroactively removing them from the surface regions..
Ctf Solar Gmbh


new patent

Solar cell


A solar cell including a first conductive type semiconductor substrate; a first intrinsic semiconductor layer on a front surface of the semiconductor substrate; a first conductive type first semiconductor layer on at least one surface of the first intrinsic semiconductor layer; a second conductive type second semiconductor layer on a back surface of the semiconductor substrate; a second intrinsic semiconductor layer between the second semiconductor layer and the semiconductor substrate; a first conductive type third semiconductor layer on the back surface of the semiconductor substrate, the third semiconductor layer being spaced apart from the second semiconductor layer; and a third intrinsic semiconductor layer between the third semiconductor layer and the semiconductor substrate.. .
Intellectual Keystone Technology Llc


new patent

Metallization of solar cells


Approaches for the metallization of solar cells and the resulting solar cells are described. In an example, a method of fabricating a solar cell involves forming a barrier layer on a semiconductor region disposed in or above a substrate.

new patent

Solar cell


Solar cell including a semiconductor substrate with a first and second side, a first contact structure disposed in the region of the first side of the semiconductor substrate and contacting the semiconductor substrate, a passivation layer with openings disposed on the second side of the semiconductor substrate, and a second contact structure disposed on the passivation layer, which locally contacts the semiconductor substrate through the openings of the passivation layer, wherein the first contact structure has a strip-shaped connection element and contact fingers connected to the connection element, and wherein the passivation layer has an openings-free region extending along the connection element in a region under the strip-shaped connection element of the first contact structure.. .
Solarworld Innovations Gmbh


new patent

Semiconductor device


According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, and a fourth semiconductor region. The first semiconductor region is provided between the first and second electrodes.
Kabushiki Kaisha Toshiba


new patent

Semiconductor device and manufacturing method thereof


A semiconductor device includes a sic substrate having first and second surfaces, p-type first sic areas on the first surface of the sic substrate, an n-type second sic area between the first sic areas and the second surface, a third sic area having an n-type dopant concentration higher than that of the second sic area, on the second surface of the sic substrate, a first electrode on the first surface and electrically connected to the first sic areas, and a second electrode on the second surface and electrically connected to the third sic area. Where the area between the first sic areas and the second surface is a first area, and the area between a portion between adjacent first sic areas and the second surface is set as a second area, a z1/2 level density of the first area is higher than that of the second area..
Kabushiki Kaisha Toshiba


new patent

Zener diode having an adjustable low breakdown voltage


The present disclosure relates to a zener diode including a cathode region having a first conductivity type, formed on a surface of a semiconductor substrate having a second conductivity type. The zener diode includes an anode region having the second conductivity type, formed beneath the cathode region.
Stmicroelectronics (rousset) Sas


new patent

Nonvolatile semiconductor memory device


A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (a) provided just above the charge storage layer, a top layer (c) provided just below the control gate electrode, and a middle layer (b) provided between the bottom layer (a) and the top layer (c).
Kabushiki Kaisha Toshiba


new patent

Method for making a transistor in a stack of superimposed semiconductor layers


C) the portions are removed by selectively etching a second semi-conductor material made amorphous towards the first semi-conductor material (fig. 2l)..

new patent

Semiconductor device and manufacturing method thereof


An object is to achieve high electrical characteristics (a high on-state current value, an excellent s value, and the like) and a highly reliable semiconductor device. A high on-state current value is achieved, whereby a further reduction in channel width (w) is achieved.
Semiconductor Energy Laboratory Co., Ltd.


new patent

Method for producing thin film transistor


A method for producing a thin film transistor including an oxide semiconductor layer includes: depositing an oxide semiconductor film above a substrate by a sputtering method; and forming the oxide semiconductor layer into a predetermined shape by processing the oxide semiconductor film, wherein in the depositing of an oxide semiconductor film, a first oxide semiconductor film is deposited by using a first power density, and a second oxide semiconductor film is then deposited on the first oxide semiconductor film by using a second power density different from the first power density.. .
Joled Inc.


new patent

Thin film transistor, array substrate and display device


The present invention discloses a thin film transistor (tft), an array substrate comprising the tft and a display device comprising the array substrate. The tft comprises a gate, a source, a drain, and a semiconductor layer and an insulating layer which are both provided between the source, the drain and the gate, the insulating layer is made of inorganic insulating material, a modifying layer is provided between the insulating layer and the semiconductor layer and in an area corresponding to the insulating layer, and the modifying layer is made of organic aliphatic silane material.
Boe Technology Group Co., Ltd.


new patent

Semiconductor device


One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line.
Semiconductor Energy Laboratory Co., Ltd.


new patent

Semiconductor device and manufacturing method thereof


An object is to suppress conducting-mode failures of a transistor that uses an oxide semiconductor film and has a short channel length. A semiconductor device includes a gate electrode 304, a gate insulating film 306 formed over the gate electrode, an oxide semiconductor film 308 over the gate insulating film, and a source electrode 310a and a drain electrode 310b formed over the oxide semiconductor film.
Sharp Kabushiki Kaisha


new patent

Semiconductor device


A transistor with stable electrical characteristics. A semiconductor device that includes an oxide semiconductor, a first conductor, a first insulator, a second insulator, a third insulator, and a fourth insulator.
Semiconductor Energy Laboratory Co., Ltd.


new patent

Semiconductor device and manufacturing method thereof


A transistor with favorable electrical characteristics is provided. A minute transistor is provided.
Semiconductor Energy Laboratory Co., Ltd.


new patent

Semiconductor device, manufacturing the same, or display device including the same


To suppress a change in electrical characteristics and improve reliability in a transistor including an oxide semiconductor film. Provided is a semiconductor device including a transistor including a first gate electrode, a first insulating film over the first gate electrode, a first oxide semiconductor film over the first insulating film, a source electrode electrically connected to the first oxide semiconductor film, a drain electrode electrically connected to the first oxide semiconductor film, a second insulating film over the first oxide semiconductor film, a second oxide semiconductor film as a second gate electrode over the second insulating film, and a third insulating film over the second oxide semiconductor film.
Semiconductor Energy Laboratory Co., Ltd.


new patent

Semiconductor device and manufacturing the semiconductor device


A semiconductor device includes at least one first gate structure and at least one second gate structure on a semiconductor substrate. The at least one first gate structure has a flat upper surface extending in a first direction and a first width in a second direction perpendicular to the first direction.

new patent

Non-planar semiconductor device having hybrid geometry-based active region


Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-fet portion disposed above a fin-fet portion.
Intel Corporation


new patent

Semiconductor device including active fin


A semiconductor device includes first through fourth active fins, which extend alongside one another in a first direction; and a field insulating film that covers lower portions of the first through fourth active fins, the first and second active fins protrude from the field insulating film at a first height, the third active fin protrudes from the field insulating film at a second height different from the first height, and an interval between the first and second active fins is different from an interval between the third and fourth active fins.. .

new patent

Semiconductor device structure with raised source/drain having cap element


Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a source/drain structure adjacent to the gate stack.
Taiwan Semiconductor Manufacturing Co., Ltd


new patent

Method and structure of making enhanced utbb fdsoi devices


An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material.
Stmicroelectronics (crolles 2) Sas


new patent

Method and structure of making enhanced utbb fdsoi devices


An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material.
Stmicroelectronics (crolles 2) Sas


new patent

Vertical fin field-effect semiconductor device


A vertical finfet semiconductor device and a method of forming the same are disclosed. In one aspect, the semiconductor device includes a current-blocking structure formed over a semiconductor structure and a semiconductor fin formed on the current-blocking structure.
Globalfoundries Inc.


new patent

Semiconductor device


To provide a high-withstand-voltage lateral semiconductor device in which on-resistance or drain current density is uniform at an end portion and a center portion of the device in a gate width direction. A lateral n-type mos transistor 11 formed on an soi substrate includes a trench isolation structure 10b filled with an insulating film at an end portion of the transistor.
Hitachi Automotive Systems, Ltd.


new patent

Ldmos device and fabrication method thereof


The disclosed subject matter provides an ldmos device and fabrication method thereof. In an ldmos device, a drift region and a body region are formed in a substrate.
Semiconductor Manufacturing International (shanghai) Corporation


new patent

Methods of manufacturing trench semiconductor devices with edge termination structures


Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate.
Freescale Semiconductor, Inc.


new patent

Semiconductor device


A semiconductor device according to an embodiment includes a first active region and a second active region. The first active region includes a n-type first source region at a first surface of the sic substrate having the first surface and a second surface, a n-type first drain region, a first gate insulating film, a first gate electrode, a p-type second source region at the first surface and electrically connected to the first source region, a p-type second drain region, a second gate insulating film, and a second gate electrode electrically connected to the first gate electrode.
Kabushiki Kaisha Toshiba


new patent

Semiconductor device and manufacturing method thereof


A semiconductor device includes a substrate, a buffer layer and a device layer. The buffer layer is deposited on the substrate and comprises at least one gallium nitride (gan) epitaxy layer and at least one insertion layer deposited on the gan epitaxy layer, wherein the gan epitaxy layer adjacent to an interface between the gan epitaxy layer and the upper insertion layer is doped with a trapping electron element.
Hermes-epitek Corp.


new patent

Semiconductor component and producing a semiconductor component in a substrate having a crystallographic (100) orientation


A semiconductor component includes a substrate and a gallium nitride-containing first functional element which is implemented in the surface of the substrate. The substrate has a crystallographic (100) orientation..
Robert Bosch Gmbh


new patent

Insulated gate bipolar transistor and manufacturing same


An insulated gate bipolar transistor includes: a drift layer having a semiconductor substrate with n-type conductivity; a collector layer having p-type conductivity at a surface layer of the semiconductor substrate at a back surface side; and a field stop layer between the drift layer and the collector layer that has a higher impurity concentration than the drift layer. In a thickness direction of the semiconductor substrate, a lifetime control layer is arranged with a predetermined half value width by helium ion implantation; and the field stop layer is arranged with a predetermined half value width by hydrogen ion implantation.
Denso Corporation


new patent

Vertical-type semiconductor device


A buffer layer includes an n+-type first buffer region and an n+-type second buffer region. The first buffer region is provided at a first depth from a first main surface of a semiconductor layer and has an impurity concentration higher than an impurity concentration of a drift layer.
Toyota Jidosha Kabushiki Kaisha


new patent

Semiconductor device


According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a first electrode, a first insulating layer, and a second electrode. The first semiconductor region includes a first region and a second region.
Kabushiki Kaisha Toshiba


new patent

Forming low parasitic trim gate last mosfet


A method for making a fin mosfet with substantially reduced parasitic capacitance and/or resistance is provided. The fin mosfet includes: a patterned fin structure on a substrate, the substrate including a first semiconductor layer; an epitaxy layer covering the substrate and a first portion of the fin structure, the first portion of the fin structure being doped to be integrated with the epitaxy layer, wherein a source and drain region is formed in the epitaxy layer; a metal gate high-k structure covering a second portion of the fin structure; a nitride structure covering the metal gate high-k structure; an oxide spacer structure enclosing the metal gate high-k structure and the nitride structure; and a metal contact structure for the source and drain region..
International Business Machines Corporation


new patent

Method of using an ion implantation process to prevent a shorting issue of a semiconductor device


The present invention provides a manufacturing method of a semiconductor device, including providing a substrate, where a first dielectric layer is formed on the substrate, at least one gate is formed in the first dielectric layer, at least one hard mask is disposed on the top surface of the gate, and at least two spacers are disposed on two sides of the gate respectively. Next, a blanket implantation process is performed on the hard mask and the first dielectric layer, so as to form an ion rich region in the first dielectric layer, in the hard mask and in the spacer respectively.
United Microelectronics Corp.


new patent

Power mos transistor and manufacturing method therefor


The present invention discloses a power metal oxide semiconductor (mos) transistor, wherein a second u-shaped trench is formed below a first u-shaped trench, so that a field oxidation stress transition region can be extended, so a s to greatly reduce current leakage caused by the field oxidation stress and improve the reliability of the device; and a charge compensation region is provided in a drift region at the bottom of the second u-shaped trench, and a super-junction structure is formed between the charge compensation region and the drift region to improve the breakdown voltage of the power device. According to the present invention, the second u-shaped trench and the charge compensation region are formed by a self-aligning process, so that the technical process is simple, reliable and easy to control, and can reduce the manufacturing cost of the power mos transistor and improve its yield..
Su Zhou Oriental Semiconductor Co.,ltd


new patent

Method of forming epitaxial buffer layer for finfet source and drain junction leakage reduction


A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion.
Renesas Electronics Corporation


new patent

Semiconductor device and fabricating method thereof


A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, a source/drain regions adjacent to the pair of spacers in the substrate, an etch stop layer next to the gate structure and overlying the substrate, a contact plug extending into the source/drain region and partially overlapping the gate structure, a protective layer over the etch stop layer overlying the substrate and covering the etch stop layer next to the gate structure without the contact plug, and an interlayer dielectric layer over the protective layer.
Taiwan Semiconductor Manufacturing Co., Ltd.


new patent

Forming highly conductive source/drain contacts in iii-nitride transistors


In one embodiment, a method for fabricating a iii-nitride transistor on a iii-nitride semiconductor body is disclosed. The method comprises etching dielectric trenches in a field dielectric overlying gate, source, and drain regions of the iii-nitride semiconductor body, and thereafter forming a gate dielectric over the gate, source and drain regions.
Infineon Technologies Americas Corp.


new patent

Esd protection structure and fabrication thereof


An esd protection structure comprising a first semiconductor region of a first doping type, a second semiconductor region of the first doping type, a semiconductor structure of a second doping type opposite to the first doping type formed to provide lateral isolation between the first and second semiconductor regions of the first doping type, and a first contact region of the second doping type formed within a surface of the second semiconductor region. A thyristor structure is formed within the esd protection structure comprising the first contact region of the second doping type, the second semiconductor region of the first doping type, the semiconductor structure of the second doping type, and the first semiconductor region of the first doping type.
Freescale Semiconductor, Inc.


new patent

Method for fabricating semiconductor device having fin structure that includes dummy fins


A method for fabricating semiconductor device is disclosed. First, a substrate, and a sacrificial mandrel is formed on the substrate, in which the sacrificial mandrel includes a first side and a second side with the indentation.
United Microelectronics Corp.


new patent

Semiconductor device and fabricating method thereof


A semiconductor device includes a substrate, a first and second source/drain regions, and a gate stack. The first and second source/drain regions are disposed on the substrate.
Taiwan Semiconductor Manufacturing Company Ltd.


new patent

Conductive cap for metal-gate transistor


A semiconductor device includes a gate region, a conductive cap, and an interconnect. The gate region (e.g., a metal-gate transistor) includes a metal gate region and a high dielectric constant (high-k) gate dielectric region.
Qualcomm Incorporated


new patent

Semiconductor devices and structures and methods of formation


A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate.
Micron Technology, Inc.


new patent

Method for manufacturing a semiconductor device having a schottky contact


A semiconductor device includes an n-doped monocrystalline semiconductor substrate having a substrate surface, an amorphous n-doped semiconductor surface layer at the substrate surface of the n-doped monocrystalline semiconductor substrate, and a schottky-junction forming material in contact with the amorphous n-doped semiconductor surface layer. The schottky-junction forming material forms at least one schottky contact with the amorphous n-doped semiconductor surface layer..
Infineon Technologies Austria Ag


new patent

Process for producing, from an soi and in particular an fdsoi type substrate, transistors having gate oxides of different thicknesses, and corresponding integrated circuit


An integrated circuit includes a first zone for a first transistor and a second zone for a second transistor. The transistors are supported by a substrate of the silicon-on-insulator type that includes a semiconductor film on a buried insulating layer on a carrier substrate.
Stmicroelectronics (crolles 2) Sas


new patent

Semiconductor device


A semiconductor device includes a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type adjacent to the first semiconductor region in a first direction. A third semiconductor region of the first conductivity type is disposed on the second semiconductor region and separated from the first semiconductor region in the first direction by the second semiconductor region.
Kabushiki Kaisha Toshiba


new patent

Semiconductor device and fabricating the same


An semiconductor device is provided. A fin is disposed on a substrate, extending in a lengthwise direction.
Samsung Electronics Co., Ltd.


new patent

Semiconductor device


A semiconductor device according to an embodiment includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes an element region and a termination region provided around the element region.
Kabushiki Kaisha Toshiba


new patent

Zener diode having an adjustable breakdown voltage


The present disclosure relates to a zener diode including a zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the zener diode junction upon application of a second voltage to the second conducting region..
Stmicroelectronics (rousset) Sas


new patent

Semiconductor device, and manufacturing semiconductor device


A semiconductor device comprises: an n-type semiconductor substrate; a p-type anode region formed in the semiconductor substrate on its front surface side; an n-type field stop region formed in the semiconductor substrate on its rear surface side with protons as a donor; and an n-type cathode region formed in the semiconductor substrate to be closer to its rear surface than the field stop region is, wherein a concentration distribution of the donor in the field stop region in its depth direction has a first peak, and a second peak that is closer to the rear surface of the semiconductor substrate than the first peak is, and has a concentration lower than that of the first peak, and a carrier lifetime in at least a partial region between the anode region and the cathode region is longer than carrier lifetimes in the anode region.. .
Fuji Electric Co., Ltd.


new patent

Semiconductor-substrate manufacturing method and semiconductor-device manufacturing method in which germanium layer is heat-treated


A method of manufacturing a semiconductor substrate includes: heat-treating a germanium layer 30 with an oxygen concentration of 1×1016 cm−3 or greater in a reducing gas atmosphere at 700° c. Or greater.
Japan Science And Technology Agency


new patent

Semiconductor device


According to one embodiment, a semiconductor device includes: a first semiconductor region; a second semiconductor region on the first semiconductor region; a third semiconductor region on the second semiconductor region; an fourth insulating film on the second semiconductor region and the third semiconductor region; a first electrode under the first semiconductor region; a second electrode on the fourth insulating film; a plurality of first contact regions extending in a first direction from the first electrode toward the second electrode in the fourth insulating film, and the plurality of first contact regions electrically connecting the third semiconductor region to the second electrode; a plurality of second contact regions extending in the first direction in the fourth insulating film, and one of the plurality of second contact regions between adjacent ones of the first contact regions; and a third electrode in the second semiconductor region via a first insulating film.. .
Kabushiki Kaisha Toshiba


new patent

Semiconductor device


A semiconductor device according to an embodiment includes a cell region, a gate connection region, and a cell end region between the cell region and the gate connection region. The cell region includes, an n-type first sic region, a p-type second sic region, a n-type third sic region, a p-type fourth sic region, a gate insulating film, a gate electrode, a first electrode contacting with the first and fourth sic regions, a second electrode.
Kabushiki Kaisha Toshiba


new patent

Semiconductor device and manufacturing the same


A semiconductor device according to an embodiment includes a first-conductivity-type sic substrate, a first-conductivity-type sic layer provided on the sic substrate, having a first surface, and having a lower first-conductivity-type impurity concentration than the sic substrate, first second-conductivity-type sic regions provided in the first surface of the sic layer, second second-conductivity-type sic regions provided in the first sic regions and having a higher second-conductivity-type impurity concentration than the first sic region, silicide layers provided on the second sic regions and having a second surface, a difference between a distance from the sic substrate to the second surface and a distance from the sic substrate to the first surface being equal to or less than 0.2 μm, a first electrode provided to contact with the sic layer and the silicide layers, and a second electrode provided to contact with the sic substrate.. .
Kabushiki Kaisha Toshiba


new patent

Semiconductor device


A semiconductor device includes an sic substrate including a first surface and a second surface, the sic substrate having a first sic region of a first conductivity type at the first surface, and a second sic region of a second conductivity type between the first sic region and the second surface, an insulating film on the first surface around an element region of the semiconductor device and in contact with the first sic region, a first electrode on the insulating film and comprising a contact electrically connected to the first sic region, and a second electrode in contact with the second surface. A first conductivity type impurity concentration of the first sic region that is directly under a center portion of the contact is greater than a first conductivity type impurity concentration of the first sic region that is directly under a peripheral portion of the contact..
Kabushiki Kaisha Toshiba


new patent

Heterogeneous pocket for tunneling field effect transistors (tfets)


Embodiments of the disclosure described herein comprise a tunneling field effect transistor (tfet) having a drain region, a source region having a conductivity type opposite of the drain region, a channel region disposed between the source region and the drain region, a gate disposed over the channel region, and a heterogeneous pocket disposed near a junction of the source region and the channel region. The heterogeneous pocket comprises a semiconductor material different than the channel region, and comprises a tunneling barrier less than the bandgap in the channel region and forming a quantum well in the channel region to in crease a current through the tfet transistor when a voltage applied to the gate is above a threshold voltage..
Intel Corporation


new patent

Method of fabricating semiconductor structures on dissimilar substrates


Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate.
Intel Corporation


new patent

Asymmetric fet


After forming a first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region on recessed surfaces of a semiconductor portion that are not covered by a gate structure, at least one dielectric layer is formed to cover the first-side and the second-side epitaxial semiconductor regions and the gate structure. A second-side contact opening is formed within the at least one dielectric layer to expose an entirety of the second-side epitaxial semiconductor region.
International Business Machines Corporation


new patent

Semiconductor devices and methods of manufacture thereof


Semiconductor devices and methods of manufacture thereof are described. In an embodiment, a method of manufacturing a semiconductor device may include: patterning a substrate to have a first region and a second region extending from the first region of the substrate; depositing an isolation layer over a surface of the first region of the substrate; and epitaxially forming source/drain regions over the isolation layer and adjacent to sidewalls of the second region of the substrate..
National Chiao Tung University


new patent

Semiconductor device


According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of a second conductivity type, an insulating section, and a semiconductor section. The second semiconductor region is provided on the first semiconductor region.
Kabushiki Kaisha Toshiba


new patent

Semiconductor device formed with nanowire


A semiconductor device is provided. The semiconductor device includes a substrate; a first nanowire disposed over the substrate; a second nanowire disposed over the substrate; a first pad formed at first ends of the first and second nanowires, a second pad formed at second ends of the first and second nanowires, wherein the pads comprise different materials than the nanowires; and a gate surrounding at least a portion of each of the first and second nanowires..
United Microelectronics Corp.


new patent

Field effect transistors and methods of forming same


Semiconductor devices and methods of forming the same are provided. A template layer is formed on a substrate, the template layer having a recess therein.
Taiwan Semiconductor Manufacturing Company, Ltd.


new patent

Wire-last gate-all-around nanowire fet


A nanowire field effect transistor (fet) device includes a first source/drain region and a second source/drain region. Each of the first and second source/drain regions are formed on an upper surface of a bulk semiconductor substrate.
International Business Machines Corporation


new patent

Semiconductor device


According to an embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a first insulating layer, and a first insulating region. The second semiconductor region is provided on the first semiconductor region.
Kabushiki Kaisha Toshiba


new patent

Semiconductor device and fabricating the same


A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, a spacer layer and a dummy gate structure. The fin shaped structure is disposed on a substrate, wherein the fin shaped structure has a trench.
United Microelectronics Corp.


new patent

High-voltage transistor device


A semiconductor device is provided including a substrate, a buried oxide layer formed over the substrate, a semiconductor layer formed over the buried oxide layer, and a transistor device including a gate electrode, a gate insulation layer and a channel region, wherein the gate insulation layer comprises a part of the buried oxide layer.. .
Globalfoundries Inc.


new patent

Semiconductor device


A semiconductor device according to an embodiment includes a first semiconductor layer of a first conductivity type, second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a gate electrode, an insulating layer, and a first electrode. The first semiconductor layer includes first semiconductor regions.
Kabushiki Kaisha Toshiba


new patent

Semiconductor device


A semiconductor device includes: a semiconductor substrate; and a thin film resistor formed over an upper surface of the semiconductor substrate, the thin film resistor including first thin film resistor units and second thin film resistor units alternately connected in series, each of the first thin film resistor units having an elongated main portion and end portions that are connected to the elongated main portion, the end portions each forming a u-shape together with the elongated main portion in a plan view, and respectively overlapping with two of the second thin film resistor units that are adjacent to and connected to the first thin film resistor unit in series.. .
Fuji Electric Co., Ltd.


new patent

Memory device


According to one embodiment, a memory device includes a first conductive layer, a second conductive layer, a first insulating layer and a first layer. The first conductive layer includes a first metal capable of forming a compound with silicon.
Kabushiki Kaisha Toshiba


new patent

High thermal budget magnetic memory


Semiconductor devices and methods for forming a semiconductor device are disclosed. The method includes forming a storage unit of a magnetic memory cell.
Globalfoundries Singapore Pte. Ltd.


new patent

Semiconductor devices comprising magnetic memory cells


Memory cells are disclosed. Magnetic regions within the memory cells include an alternating structure of magnetic sub-regions and coupler sub-regions.
Micron Technology, Inc.


new patent

Formation of buried color filters in a back side illuminated image sensor with an ono-like structure


A semiconductor image sensor includes a substrate having a first side and a second side that is opposite the first side. An interconnect structure is disposed over the first side of the substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


new patent

Solid-state imaging device and manufacturing method therefor


A solid-state imaging device according to an embodiment includes a first semiconductor layer of a first conductivity type, a photodiode region in which a second semiconductor layer of a second conductivity type is formed in a surface of the first semiconductor layer, a first interlayer insulating film which is formed on the first semiconductor layer and on the photodiode region, a first fixed charge film which is formed on the first interlayer insulating film and has a charge of the second conductivity type, a second interlayer insulating film which is formed on or above the first fixed charge film, and a second fixed charge film which is formed on the second interlayer insulating film and has a charge of the second conductivity type.. .
Kabushiki Kaisha Toshiba


new patent

Composite grid structure to reduce cross talk in back side illumination image sensors


A semiconductor structure for back side illumination (bsi) pixel sensors is provided. Photodiodes are arranged within a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


new patent

Composite grid structure to reduce crosstalk in back side illumination image sensors


A semiconductor structure for back side illumination (bsi) pixel sensors is provided. Photodiodes are arranged within a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


new patent

Solid-state imaging device, manufacturing solid-state imaging device, and imaging apparatus


A solid-state imaging device includes, in a semiconductor substrate, a pixel portion provided with a photoelectric conversion portion, which photoelectrically converts incident light to obtain an electric signal and a peripheral circuit portion disposed on the periphery of the pixel portion, wherein a gate insulating film of amos transistor in the peripheral circuit portion is composed of a silicon oxynitride film, a gate insulating film of amos transistor in the pixel portion is composed of a silicon oxynitride film, and an oxide film is disposed just above the photoelectric conversion portion in the pixel portion.. .
Sony Corporation


new patent

Solid-state image sensor and electronic device


There is provided a solid-state image sensor including a semiconductor substrate in which a plurality of pixels are arranged, and a wiring layer stacked on the semiconductor substrate and formed in such a manner that a plurality of conductor layers having a plurality of wirings are buried in an insulation film. In the wiring layer, wirings connected to the pixels are formed of two conductor layers..
Sony Corporation


new patent

Solid-state imaging device and manufacturing method thereof


A solid-state imaging device includes a p-well, a gate insulating film, a gate electrode, a p+-type pinning layer that is located in the p-well so as to be outside the gate electrode and start from a first end portion of the gate electrode, a p−-type impurity region that is located in the p-well so as to extend under the gate electrode from a first end portion side and be in contact with the pinning layer, an n−-type impurity region that is located in the semiconductor layer under the p−-type impurity region and includes a portion that is under the pinning layer, and an n−-type impurity region that is in contact with the gate insulating film and the p−-type impurity region and is located so as to surround the n−-type impurity region in plan view.. .
Seiko Epson Corporation


new patent

Semiconductor device and manufacturing the same


A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.. .
Sony Corporation


new patent

Interconnect structure for stacked device and method


A stacked integrated circuit (ic) device and a method are disclosed. The stacked ic device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element.
Taiwan Semiconductor Manufacturing Company, Ltd.


new patent

Image sensor and manufacturing the same


Image sensor and method of manufacturing the same are provided. The image sensor includes a semiconductor substrate including a pixel area, a voltage connection area, and a pad area, a plurality of photoelectric conversion devices in the pixel area, an anti-reflective layer on a back side of the semiconductor substrate and on the plurality of photoelectric conversion devices, a device isolation structure between the plurality of photoelectric conversion devices, at least one voltage connection structure in the voltage connection area, and electrically connected to the device isolation structure, at least one voltage applying device electrically connected to the at least one voltage connection structure, an internal circuit including at least one conductive inner wire and at least one conductive inner via in an insulating layer, and a through via structure in the pad area..
Samsung Electronics Co., Ltd.


new patent

Photosensitive capacitor pixel for image sensor


An image sensor pixel, and image sensor, and a method of fabricating the same is disclosed. The image pixel includes a photosensitive capacitor and a transistor network.
Omnivision Technologies, Inc.


new patent

Array substrate, manufacturing the same, display device and electronic product


According to the method for manufacturing an array substrate of the present disclosure, when two non-adjacent conductive layers are electrically connected to each other through the via-holes, the insulating layers between the adjacent conductive layers may be etched by several etching processes so as to form the corresponding via-holes in the insulating layer, thereby to achieve the electrical connection between the non-adjacent conductive layers. Meanwhile, it is also able to achieve the electrical connection between the adjacent conductive layers through the via-holes in each etching process.
Beijing Boe Display Technology Co., Ltd.


new patent

Array substrate, manufacturing method thereof and display device


A method for manufacturing an array substrate, comprising forming a pattern of a gate electrode by one pattering process; forming a gate insulating layer on a substrate provided with the pattern of the gate electrode; forming first and second patterns thereon, in which the first pattern corresponds to a pattern of a semiconductor active layer and the second pattern corresponds to a source electrode and a drain electrode; forming a pattern layer including an opening area on the substrate provided with the second pattern, in which the opening area corresponds to a gap between the source electrode and the drain electrode, the minimum width thereof being greater than the width of the gap between the source electrode and the drain electrode, and at least forming a pattern of the source electrode and the drain electrode and a pixel electrode electrically connected with the drain electrode through the opening area.. .
Boe Technology Group Co., Ltd.


new patent

Active matrix substrate, display apparatus and manufacturing active matrix substrate


A gate electrode and a capacitance wiring are formed on the insulating substrate in the active matrix substrate, and an interlayer insulating film is formed to cover the insulating substrate. On the gate electrode and the capacitance wiring, contact holes ca and cb are formed.

new patent

Semiconductor device


Provided is a semiconductor device including a transistor having excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics) or a semiconductor device including a transistor with high reliability. In the channel width direction of a channel-etched transistor in which an oxide semiconductor film is between first and second gate electrodes, the first and second gate electrodes are connected to each other through an opening portion in first and second gate insulating films.
Semiconductor Energy Laboratory Co., Ltd.


new patent

Method for the formation of a finfet device having a partially dielectric isolated fin structure


A semiconductor material is patterned to define elongated fins insulated from an underlying substrate. A polysilicon semiconductor material is deposited over and in between the elongated fins, and is patterned to define elongated gates extending to perpendicularly cross over the elongated fins at a transistor channel.
Stmicroelectronics, Inc.


new patent

Semiconductor device and electronic device


To provide a semiconductor device with excellent electrical characteristics or a semiconductor device with stable electrical characteristics. A semiconductor device includes a first transistor, a second transistor, a first insulator, a second insulator, a first wiring, and a first plug.
Semiconductor Energy Laboratory Co., Ltd.


new patent

Semiconductor device


A semiconductor device includes a first pillar-shaped semiconductor layer, a first selection gate insulating film, a first selection gate, a first gate insulating film, a first contact electrode, a first bit line connected to an upper portion of the first pillar-shaped semiconductor layer and an upper portion of the first contact electrode, a second pillar-shaped semiconductor layer, a layer including a first charge storage layer, a first control gate, a layer including a second charge storage layer and formed above the first control gate, a second control gate, a second gate insulating film, a second contact electrode having an upper portion connected to an upper portion of the second pillar-shaped semiconductor layer, and a first lower internal line that connects a lower portion of the first pillar-shaped semiconductor layer and a lower portion of the second pillar-shaped semiconductor layer.. .
Unisantis Electronics Singapore Pte. Ltd.


new patent

Three-dimensional semiconductor memory device and fabricating the same


A semiconductor memory device includes a stack including gate electrodes sequentially stacked on a substrate, a vertical insulating structure penetrating the stack vertically with respect to the gate electrodes, a vertical channel portion disposed on an inner side surface of the vertical insulating structure, and a common source region formed in the substrate and spaced apart from the vertical channel portion. A bottom region of the vertical channel portion has a protruding surface in contact with a bottom region of the vertical insulating structure..

new patent

Semiconductor memory device and manufacturing the same


According to an embodiment, a semiconductor memory device comprises: a memory string comprising memory cells; and a contact electrically connected to one end of the memory string. The memory string comprises: control gate electrodes stacked above a first semiconductor layer; a second semiconductor layer having one end connected to the first semiconductor layer and having as its longitudinal direction a direction perpendicular to the first semiconductor layer, the second semiconductor layer facing the control gate electrodes; and a charge accumulation layer positioned between the control gate electrode and the second semiconductor layer.
Kabushiki Kaisha Toshiba


new patent

Method for manufacturing semiconductor memory device


According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a mask layer on the stacked body. The method includes forming a stopper film in a part of the mask layer.
Kabushiki Kaisha Toshiba


new patent

Semiconductor memory device


A semiconductor memory device according to an embodiment comprises: a memory cell array, the memory cell array including: a conductive layer, an inter-layer insulating layer, and a conductive line stacked on a semiconductor substrate in a stacking direction; first and second connecting lines that contact the semiconductor substrate and are electrically connected to the conductive line and that extend in the stacking direction; and a columnar body that penetrates the conductive layer and the inter-layer insulating layer in the stacking direction between the first and second connecting lines and that includes a first semiconductor layer, the semiconductor substrate having: a first impurity region to which a first impurity is added at a place of contact with the first connecting line; and a second impurity region to which a second impurity different from the first impurity is added at a place of contact with the second connecting line.. .
Kabushiki Kaisha Toshiba


new patent

Semiconductor memory device with first and second semicondutor films in first and second columnar bodies


A semiconductor memory device according to an embodiment comprises: conductive layers stacked in a vertical direction on a semiconductor substrate; and first and columnar bodies that extend in the vertical direction, the first and second columnar bodies each comprising: a first film; a second film disposed on the first film; and a semiconductor film, and the first film of the second columnar body having an upper end positioned higher than a first position lower than a first conductive layer and lower than a second position higher than the first conductive layer and a lower end positioned at or lower than the first position, and the second film of the second columnar body having an upper end positioned higher than the second position and a lower end positioned lower than the first position.. .
Kabushiki Kaisha Toshiba


new patent

Honeycomb cell structure three-dimensional non-volatile memory device


A monolithic three-dimensional memory device includes a plurality of memory stack structures arranged in a hexagonal lattice and located over a substrate. The hexagonal lattice structure is defined by hexagons each having a pair of sides that are parallel to a first horizontal direction and perpendicular to a second horizontal direction, the memory stack structures are located at vertices of the hexagonal lattice, and each memory stack structure includes vertically spaced memory elements and a vertical semiconductor channel.
Sandisk Technologies Inc.


new patent

Metallic etch stop layer in a three-dimensional memory structure


A dielectric liner, a bottom conductive layer, and a stack of alternating layers including insulator layers and spacer material layers are sequentially formed over a substrate. A memory opening extending through the stack can be formed by an anisotropic etch process that employs the bottom conductive layer as an etch stop layer.
Sandisk Technologies Inc.


new patent

Semiconductor device and manufacturing the same


The present invention discloses a semiconductor device and a method for manufacturing the same, and the semiconductor device includes: a first area in which a plurality of device elements are stacked, wherein adjacent ones of the plurality of device elements are spaced by an interlayer insulation layer, and each of the device elements includes a corresponding gate conductor; and a second area adjacent to the first area, wherein the interlayer insulation layer and the gate conductors extend from the first area to the second area, and there are electrically conductive vias in the second area through which the gate conductors and connected with wires, wherein there are also support posts in the second area to support the interlayer insulation layer and the gate conductors. The support posts provides a mechanical support for the floating layers in the process of manufacturing and also supports the gate conductors in the resulting device to thereby improve the yield ratio and reliability of the semiconductor device..

new patent

Split gate non-volatile memory cell with 3d finfet structure, and making same


A non-volatile memory cell including a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between.
Silicon Storage Technology, Inc.


new patent

Semiconductor memory device


A semiconductor memory device of the embodiments includes a first conductivity type semiconductor layer extending in a first direction and including a plurality of projecting regions on the surface thereof, a first insulating film provided on the projecting regions, a charge storage layer provided on the first insulating film, a second insulating film provided on the charge storage layer, and a control gate provided on the second insulating film.. .
Kabushiki Kaisha Toshiba


new patent

Salicided structure to integrate a flash memory device with a high k, metal gate logic device


An integrated circuit for an embedded flash memory device is provided. A semiconductor substrate includes a memory region and a logic region adjacent to the memory region.
Taiwan Semiconductor Manufacturing Co., Ltd.


new patent

Nonvolatile semiconductor memory device


A stacked body is disposed so as cover a periphery of a semiconductor columnar portion and includes a conductive layer and an inter-layer insulating layer stacked alternately in a stacking direction on a semiconductor substrate. An epitaxial layer is disposed on a surface of the semiconductor substrate and is electrically connected to a lower end of the semiconductor columnar portion.
Kabushiki Kaisha Toshiba


new patent

Semiconductor device including memory cell array and power supply region


A semiconductor device having an sram which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions..
Renesas Electronics Corporation


new patent

Semiconductor device and semiconductor memory device


According to one embodiment, a semiconductor device includes a first region having a first conductivity type in a semiconductor region; a second region having a second conductivity type in the semiconductor region; a gate electrode above a first part of the semiconductor region between the first region and the second region; a gate insulating layer between the first part and the gate electrode; a third region having the first conductivity type below the second region; and a fourth region across the second region and the third region and including a first impurity.. .
Kabushiki Kaisha Toshiba


new patent

Merged n/p type transistor


A semiconductor structure includes a semiconductor substrate, at least one first elongated region of n-type or p-type, and at least one other second elongated region of the other of n-type or p-type, the first and second elongated regions crossing such that the first elongated region and the second elongated region intersect at a common area, and a shared gate structure over each common area.. .
Globalfoundries Inc.


new patent

Semiconductor devices having bit lines and fabricating the same


Semiconductor devices and methods of forming the semiconductor devices are provided. The semiconductor devices may include a bit line provided to cross an active region of a substrate, isolation patterns provided on the substrate to face each other in a direction parallel to the bit line, a storage node contact provided between the isolation patterns to be in contact with a source/drain region provided in an upper portion of the active region, and a spacer provided between the bit line and the storage node contact.
Samsung Electronics Co., Ltd.


new patent

Finfet including tunable fin height and tunable fin width ratio


A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer.
Stmicroelectronics, Inc.


new patent

Dual strained cladding layers for semiconductor devices


Techniques and methods related to dual strained cladding layers for semiconductor devices, and systems incorporating such semiconductor devices.. .

new patent

Planar device on fin-based transistor architecture


Techniques are disclosed for forming a planar-like transistor device on a fin-based field-effect transistor (finfet) architecture during a finfet fabrication process flow. In some embodiments, the planar-like transistor can include, for example, a semiconductor layer which is grown to locally merge/bridge a plurality of adjacent fins of the finfet architecture and subsequently planarized to provide a high-quality planar surface on which the planar-like transistor can be formed.
Intel Corporation


new patent

Semiconductor devices having fin active regions


Semiconductor devices are providing including a first isolation region configured to define a first fin active region protruding from a substrate, first gate patterns on the first fin active region, and a first epitaxial region in the first fin active region between the first gate patterns. Sidewalls of the first epitaxial region have first inflection points so that an upper width of the first epitaxial region is greater than a lower width of the first epitaxial region..

new patent

Semiconductor devices including shallow trench isolation (sti) liners


Semiconductor devices including sti liners are provided. The semiconductor devices may include a sti trench that defines an active region in a substrate, a sti liner that extends conformally along side walls and a bottom surface of the sti trench, a device isolation film that is on the sti liner and fills up at least a part of the sti trench, a first gate structure that is disposed on the active region, and a second gate structure that is spaced apart from the first gate structure.
Samsung Electronics Co., Ltd.


new patent

Semiconductor device


A semiconductor device is provided. The semiconductor device may include a field insulating film on a substrate, a first fin type pattern which is formed on the substrate and protrudes upward from an upper surface of the field insulating film, and a gate electrode which intersects with the first fin type pattern on the field insulating film.

new patent

Semiconductor device and manufacturing method thereof


A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin.
Taiwan Semiconductor Manufacturing Co., Ltd.


new patent

Combination metal oxide semi-conductor field effect transistor (mosfet) and junction field effect transistor (jfet) operable for modulating current voltage response or mitigating electromagnetic or radiation interference effects by altering current flow through the mosfets semi-conductive channel region (scr)


Systems and methods for controlling current or mitigating electromagnetic or radiation interference effects using a combination of a metal-oxide semiconductor field effect transistor (mosfet) and junction field effect transistor (jfet) disposed perpendicularly and within a certain orientation to each other. An embodiment of the invention can be formed and operable for modulating current and/or voltage response or mitigating electromagnetic or radiation interference effects on the mosfet by controlling a semi-conductive channel region (scr) using an additional gate, e.g., jfet, disposed perpendicularly with respect to the mosfet configured to generate an electromagnetic field into the mosfet's semi-scr.
The United States Of America As Represented By The Secretary Of The Navy


new patent

Transistors patterned with electrostatic discharge protection and methods of fabrication


High-voltage semiconductor devices with electrostatic discharge (esd) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first s/d contacts and a plurality of second s/d contacts associated with the common gate(s).
Globalfoundries Inc.


new patent

Semiconductor device and testing the semiconductor device


A semiconductor device and a method for testing the semiconductor device are provided. The semiconductor device includes a diode (protection element) and a semiconductor element having a withstand voltage that is higher than that of the diode provided on one and the same first-conductive-type semiconductor substrate, the diode having a second-conductive-type first semiconductor region selectively provided in a front surface layer of the semiconductor substrate.
Fuji Electric Co., Ltd.


new patent

Esd protection structure and fabrication thereof


An esd protection structure formed within an isolation trench and comprising a first peripheral semiconductor region of a first doping type, a second semiconductor region of the first doping type, and a semiconductor structure of a second doping type opposite to the first doping type formed to provide lateral isolation between the semiconductor regions of the first doping type and isolation between the further semiconductor region of the first doping type and the isolation trench. The semiconductor structure of the second doping type is formed such that no semiconductor region of the second doping type is formed between a peripheral side of the first semiconductor region of the first doping type and a wall of the isolation trench, and no semiconductor region of the first doping type is in contact with the isolation trench other than the first semiconductor region of the first doping type..
Freescale Semiconductor, Inc.


new patent

Optoelectronics and cmos integration on goi substrate


A method of forming an optoelectronic device and a silicon device on a single chip. The method may include; forming a stack of layers on a substrate in a first and second region, the stack of layers include a semiconductor layer, a first insulator layer, a waveguide, a second insulator layer, and a device base layer; forming the device on the device base layer in the second region; forming a device insulator layer on the device and on the device base layer in the second region; and forming the optoelectronic device in the first region, the optoelectronic device has a bottom cladding layer, an active region, and a top cladding layer, wherein the bottom cladding layer is on the semiconductor layer, the active region is on the bottom cladding layer, and the top cladding layer is on the active region..
International Business Machines Corporation


new patent

Semiconductor package assembly


The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first semiconductor die.
Mediatek Inc.


new patent

Light-emitting device and display device


Disclosed herein is a light-emitting device including a plurality of first light-emitting elements mounted in a matrix form on a common wiring board. Each of the first light-emitting elements has a single crystal semiconductor multilayer structure and is a semiconductor element in the form of a chip that emits light in a given band of wavelengths.
Sony Corporation


new patent

Semiconductor light-emitting device and the manufacturing method thereof


A semiconductor light-emitting device that includes a substrate, at least one light-emitting unit arranged on the substrate, a phosphor layer at least covering an upper surface of the at least one light-emitting unit, and a reflective layer arranged on the substrate is provided. The reflective layer surrounds the at least one light-emitting unit.
Genesis Photonics Inc.


new patent

Flexible light emitting semiconductor device with large area conduit


A flexible polymeric dielectric layer (12) having first and second major surfaces, the first major surface having a conductive layer (20) thereon, the dielectric layer having at least one conduit (10) extending from the second major surface to the first major surface, the conduit having at least one lateral dimension of at least about one centimeter and being at least partially filled with conductive material (18), the conductive layer including at least one conductive feature (21) substantially aligned with the conduit (10), the conductive feature (21) supporting a plurality of light emitting semiconductor devices (22).. .
3m Innovative Properties Company


new patent

Cooling channels in 3dic stacks


An integrated circuit structure includes a die including a semiconductor substrate, dielectric layers over the semiconductor substrate, an interconnect structure including metal lines and vias in the dielectric layers, a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers, and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through..
Taiwan Semiconductor Manufacturing Company, Ltd.


new patent

Semiconductor device and manufacturing method thereof


A semiconductor device according to the present embodiment includes a semiconductor substrate, an insulating film and a conductive film. The insulating film is disposed on a first surface of the semiconductor substrate.
Kabushiki Kaisha Toshiba


new patent

Semiconductor device and manufacturing the same


A semiconductor device includes a wiring substrate, a first semiconductor chip provided on the wiring substrate, a supporting member provided on the wiring substrate in a region which does not overlap with the first semiconductor chip in a plan view when viewed from a direction perpendicular to the wiring substrate, a resin member provided on the first semiconductor chip, and a second semiconductor chip provided on the supporting member and the resin member. A method for manufacturing a semiconductor device includes providing a first semiconductor chip in a first region on a wiring substrate, providing a supporting member in a second region on the wiring substrate, providing a resin member in at least a portion on the first semiconductor chip, and providing a second semiconductor chip on the supporting member and the resin member..
Kabushiki Kaisha Toshiba


new patent

Edge structure for backgrinding asymmetrical bonded wafer


Semiconductor devices and methods of forming a semiconductor device are disclosed. The device includes a wafer with top and bottom surfaces.
Globalfoundries Singapore Pte. Ltd.


new patent

Semiconductor device and manufacturing method thereof


An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various electronic devices, and methods of making thereof, that comprise a permanently coupled carrier that enhances reliability of the electronic devices..
Amkor Technology, Inc.


new patent

Thermally enhanced package-on-package structure


A semiconductor package comprises a bottom package and a top package. The bottom package comprises at least one bottom-package semiconductor device.
Samsung Electronics Co., Ltd.


new patent

Semiconductor device and forming pop semiconductor device with rdl over top package


A pop semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate.
Stats Chippac, Ltd.


new patent

Power module


A power module is disclosed, including a power module substrate in which a circuit layer is arranged on one surface of an insulating layer; and a semiconductor element that is bonded onto the circuit layer, in which a copper layer composed of copper or a copper alloy is provided on a surface of the circuit layer to be bonded to the semiconductor element, a solder layer formed by using a solder material between the circuit layer and the semiconductor element is provided, an alloy layer containing sn as a main component, 0.5% by mass or more and 10% by mass or less of ni, and 30% by mass or more and 40% by mass or less of cu at an interface of the solder layer with the circuit layer is formed, and the coverage of the alloy layer at the interface is 85% or more.. .
Mitsubishi Materials Corporation


new patent

Semiconductor device and manufacturing method thereof


A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor substrate, a second metal layer located on the second semiconductor substrate, a third metal layer, a first alloy layer, and a second alloy layer. The third metal layer extends between the first metal layer and the second metal layer.
Kabushiki Kaisha Toshiba


new patent

Jog design in integrated circuits


A device includes an active region in a semiconductor substrate, a gate strip over and crossing the active region, and a jog over the active region and connected to the gate strip to form a continuous region. The jog is on a side of the gate strip.
Taiwan Semiconductor Manufacturing Company, Ltd.


new patent

Tunable composite interposer


A composite interposer can include a substrate element and a support element. The substrate element can have first and second opposite surfaces defining a thickness of 200 microns or less, and can have a plurality of contacts exposed at the first surface and electrically conductive structure extending through the thickness.
Invensas Corporation


new patent

Packaging devices and methods of manufacture thereof


Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming an interconnect wiring over a substrate, and forming conductive balls over portions of the interconnect wiring.
Taiwan Semiconductor Manufacturing Company, Ltd.


new patent

Semiconductor chip


A semiconductor chip includes: a body; holes disposed in a first surface of the body; and a warpage preventing member including filling members disposed in the holes.. .
Samsung Electro-mechanics Co., Ltd.


new patent

Semiconductor device and manufacturing semiconductor device


According to one embodiment, a semiconductor device includes: a semiconductor substrate; and an insulating film provided above the semiconductor substrate. The insulating film includes: a plurality of first particles having a periodic structure; a plurality of second particles provided between the plurality of first particles and having an average particle outline size smaller than an average particle outline size of the plurality of first particles; and a filler provided between at least one of the plurality of first particles and the plurality of second particles..
Kabushiki Kaisha Toshiba


new patent

Semiconductor package and mobile device using the same


According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip, and a conductive shielding layer covering the encapsulant and at least part of a side surface of the interposer board. The interposer board has plural vias through an insulating substrate.
Kabushiki Kaisha Toshiba


new patent

Wafer structure for electronic integrated circuit manufacturing


A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits.
Aeroflex Colorado Springs Inc.


new patent

Semiconductor package and semiconductor device including electromagnetic wave shield layer


A semiconductor package is provided with an electromagnetic wave shielding layer, and a conductive ground layer connected thereto. For example, in certain embodiments, the conductive ground layer is formed in a package substrate of the semiconductor package.
Samsung Electronics Co., Ltd.


new patent

Semiconductor device


A semiconductor device capable of achieving a reduction of noise is provided. For example, the semiconductor device includes a first region for forming a core circuit block crbk, a power-source voltage line lnvd1 disposed in the first region, a power-source voltage line lnvd2 disposed on the outside of the first region, and an on-chip capacitor cc.
Renesas Electronics Corporation


new patent

Semiconductor structure and fabrication method thereof


The disclosed subject matter provides a semiconductor structure and fabrication method thereof. In a semiconductor structure, a dielectric layer, a plurality of discrete gate structures, and a plurality of sidewall spacers are formed on a semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


new patent

Semiconductor device and manufacturing same


A semiconductor device includes a semiconductor layer, a first insulating film provided on the semiconductor layer, a second insulating film provided on the first insulating film and including a material different from a material of the first insulating film, a first interconnect extending in a first direction along a surface of the semiconductor layer on the second insulating film, a second interconnect disposed side by side with the first interconnect on the second insulating film, and a third insulating film covering the first interconnect and the second interconnect, the third insulating film including a first gap between the first interconnect and the second interconnect. An upper surface of the second insulating film directly below the first gap is located at a level equal to or below a lower end of the first interconnect and a lower end of the second interconnect..
Kabushiki Kaisha Toshiba


new patent

Semiconductor device


A semiconductor device includes a semiconductor chip, an electrically insulating element separated from the semiconductor chip by a space, and encapsulation material disposed in the space. The semiconductor chip includes a first face having a contact, and the electrically insulating element defines at least one through-hole.
Infineon Technologies Ag


new patent

Packaged semiconductor devices, methods of packaging semiconductor devices, and pop devices


Packaged semiconductor devices, methods of packaging semiconductor devices, and package-on-package (pop) devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming through-package vias (tpvs) over a carrier, and coupling a semiconductor device to the carrier.
Taiwan Semiconductor Manufacturing Company, Ltd.


new patent

Semiconductor device and wafer level package including such semiconductor device


An rdl structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.. .
Mediatek Inc.


new patent

Semiconductor device


According to one embodiment, a semiconductor device includes a substrate; a first interconnect portion provided on the substrate and including a plurality of interconnect layers separately stacked each other; a second interconnect portion provided separately from the first interconnect portion on the substrate and including the plurality of interconnect layers having a number of stacked layers same as a number of stacked layers of the first interconnect portion; a first pillar provided adjacent to the first interconnect portion and the second interconnect portion and extending in a stacking direction of the plurality of interconnect layers; and a plurality of conductive layers. The plurality of conductive layers is separately stacked each other, surrounding a side surface of the first pillar, and electrically connected to the first interconnect portion and the second interconnect portion..
Kabushiki Kaisha Toshiba


new patent

Mis (metal-insulator-semiconductor) contact structures for semiconductor devices


An mis contact structure comprises a layer of semiconductor material, a layer of insulating material having a contact opening formed therein, a layer of contact insulating material having substantially vertically oriented portions and a substantially horizontally oriented portion, the vertically oriented portions of the layer of contact insulating material contacting a portion, but not all, of the sidewalls of the contact opening and the horizontally oriented portion of the layer of contact insulating material contacting the semiconductor layer. A conductive material is positioned on the layer of contact insulating material within the contact opening, the conductive material layer having vertically oriented portions and a horizontally oriented portion and a conductive contact positioned in the contact opening that contacts the uppermost surfaces of the conductive material layer and the layer of contact insulating material..
International Business Machines Corporation


new patent

Power and ground routing of integrated circuit devices with improved ir drop and chip performance


An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (imd) layers and a plurality of first conductive layers embedded in respective said plurality of imd layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of imd layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal.. .
Mediatek Inc.


new patent

Semiconductor device with air gap and fabricating the same


A method for fabricating a semiconductor device includes preparing a substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the substrate in the memory cell region; forming a planar gate structure over the substrate in the peripheral circuit region; forming a bit line structure over the substrate in the memory cell region; forming a first air spacers over a sidewalls of the planar gate structure; and forming a second air spacers over a sidewalls of the bit line structure.. .
Sk Hynix Inc.


new patent

Semiconductor device structure and forming the same


A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first dielectric layer over the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


new patent

Semiconductor device structure and forming the same


A semiconductor device structure is provided. The semiconductor device structure includes a substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


new patent

Semiconductor device and manufacturing same


An object of the invention is to provide a semiconductor device having less cracking or peeling and a method of manufacturing the same. A fuse portion of a semiconductor device has bit lines electrically coupled to a sram memory cell.
Renesas Electronics Corporation


new patent

Methods of forming wiring structures in a semiconductor device


Methods of forming wiring structures and methods of manufacturing semiconductor devices include forming a lower structure on a substrate, forming an interlayer insulating film including an opening on the lower structure, forming a liner film on an inner surface of the opening, treating a surface of the liner film by an ion bombardment, and forming a first conductive film on the liner film. The first conductive film is formed to be at least partially filled in the opening through a reflow process.

new patent

Device manufacture and packaging method thereof


Some embodiments of the present disclosure provide a semiconductive device. The semiconductive device includes a first conductive layer and a second conductive layer above the first conductive layer.
Taiwan Semiconductor Manufacturing Company Ltd.


new patent

Semiconductor device


A semiconductor device which can achieve a reduction of emi noises is provided. For example, a first region which is used for forming a core circuit block crbk, a first power-source voltage line (lnvd1) in the first region, a first power-source voltage generating circuit (vreg), a first power source pad (pdvcl) outside the first region, a second power-source voltage line lnvd2 which connects the lnvd1 and the pdvcl, and an on-chip capacitor cc are provided.
Renesas Electronics Corporation


new patent

Semiconductor memory device


A semiconductor memory device according to an embodiment comprises: when three directions intersecting each other are assumed to be first through third directions, and two directions intersecting each other in a plane extending in the first and second directions are assumed to be fourth and fifth directions, a memory cell array including: a conductive layer stacked in the third direction above a semiconductor substrate and having a first region; and a first columnar body penetrating the first region of the conductive layer in the third direction and including a semiconductor film, the first columnar body having a cross-section along the first and second directions in which, at a first position which is a certain position in the third direction, a length in the fourth direction is shorter than a length in the fifth direction.. .
Kabushiki Kaisha Toshiba


new patent

Semiconductor device


According to one embodiment, a semiconductor device includes lower layer wirings formed on a semiconductor chip, a protection film arranged on the lower layer wirings, an upper layer wiring arranged on the protection film and across a plurality of lower layer wirings, and connected to the lower layer wirings, wherein the upper layer wiring is larger than the lower layer wirings in terms of wiring line width and wiring line thickness, and a stress relaxing portion configured to reduce a stress at an in-corner portion of the upper layer wiring on the protection film, as compared with a case where the in-corner portion is set in 90°.. .
Kabushiki Kaisha Toshiba


new patent

Semiconductor device and manufacturing semiconductor device


According to one embodiment, a semiconductor device includes an insulating layer provided on a semiconductor substrate, an opening provided on the insulating layer, a spacer film provided in a side wall of the opening in a stepped shape, and configured to have an etching resistance lower than that of the insulating layer, and a conductive body provided in the opening to be configured to cover the spacer film.. .
Kabushiki Kaisha Toshiba


new patent

Semiconductor device


A semiconductor device includes a first memory block and a second memory block in a cell region and a first transistor and a second transistor, respectively corresponding to the first and second memory blocks, in a pass transistor region located below the cell region, wherein each of the first and second transistors includes: a first gate electrode coupled to the first memory block and a second gate electrode coupled to the second memory block.. .
Sk Hynix Inc.


new patent

Semiconductor device and forming an embedded sop fan-out package


A semiconductor device includes a bga package including first bumps. A first semiconductor die is mounted to the bga package between the first bumps.
Stats Chippac Pte. Ltd.


new patent

Through electrode substrate and semiconductor device using through electrode substrate


A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.. .
Dai Nippon Printing Co., Ltd.


new patent

Wiring substrate and semiconductor device


The wiring substrate includes an insulation layer that includes a lower surface, an upper surface, and an intermediate surface located between the lower surface and the upper surface. A first wiring layer is formed on the lower surface of the insulation layer.
Shinko Electric Industries Co., Ltd.


new patent

Semiconductor assembly and method to form the same


A semiconductor assembly is disclosed where the semiconductor assembly includes a shell with an opening, an island that shuts the opening, and terminals. The island and the terminals are originally secured by and connected to an outer support, and formed by cutting or etching a metal plate constituting a lead frame.
Sumitomo Electric Device Innovations, Inc.


new patent

Semiconductor device and a manufacturing the same and a mounting structure of a semiconductor device


The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion..
Renesas Semiconductor Package & Test Solutions Co., Ltd.


new patent

Lead frame for mounting semiconductor element and manufacturing the same


A lead frame for mounting semiconductor element includes a protrusion that is horizontally projects from edges of the upper and lower surfaces of a semiconductor-mounting part or a terminal part of the lead frame and that is provided on a lateral side of at least one of the semiconductor-mounting part or the terminal part of the lead frame, wherein the top end of the protrusion is substantially flat or the profile of the cross section of the top end is arc-shaped, and the top end of the protrusion is thick.. .
Sh Materials Co., Ltd.


new patent

Semiconductor package for a lateral device and related methods


A semiconductor package. Implementations may include a lateral device that may include a lateral semiconductor device including one of interspersed and interdigitated source and drain regions and one or more gate regions, a single layer clip, and a leadframe.
Semiconductor Components Industries, Llc


new patent

Semiconductor device


A semiconductor device includes a mounting member that includes first and second regions. First peripheral portions are provided along at least a portion of an outer periphery of the first region.
Kabushiki Kaisha Toshiba


new patent

Semiconductor device and manufacturing semiconductor device


According to one embodiment, a semiconductor device includes a first conductor, a second conductor, and an envelope. The first conductor includes a first radiation surface.
Kabushiki Kaisha Toshiba


new patent

Semiconductor device


According to the present invention, a grease layer having a grease as a constituent material is provided in a filling region lying between a heat dissipation surface that is a bottom surface of a heat dissipation material of a semiconductor module and a surface of a cooler. Further, a seal material is formed on the surface of the cooler and covers the entire side surface region of the grease layer without any gap.
Mitsubishi Electric Corporation


new patent

Thermal spreader having inter-metal diffusion barrier layer


A heat spreader provided having: as ceramic substrate; and metallization layer structure disposed on at least one surface of the substrate. The metallization layer structure includes: a thick film layer disposed on the at least one surface of the substrate; a diffusion barrier layer on, and in direct contact with the thick film layer; and as heat conducting layer disposed on, and in direct contact with, the diffusion barrier layer.
Raytheon Company


new patent

Semiconductor device and forming stacked vias within interconnect structure for fo-wlcsp


A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier.
Stats Chippac Pte. Ltd.


new patent

Semiconductor device and forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package


A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die.
Stats Chippac Pte. Ltd.


new patent

Semiconductor device and method to minimize stress on stack via


A semiconductor device has a semiconductor die. A first insulating layer is disposed over the semiconductor die.
Stats Chippac Pte. Ltd.


new patent

Semiconductor module and resin case


A semiconductor module includes a base substrate, a semiconductor element provided on the front surface side of the base substrate, and a resin case bonded to the front surface of the base substrate and enclosing a region in which the semiconductor element is provided, wherein the resin case has a depressed portion formed in a height direction away from the base substrate in a bottom surface bonded to the base substrate, and a connection hole that connects the depressed portion and the exterior of the resin case.. .
Fuji Electric Co., Ltd.


new patent

System and dual-region singulation


A method for semiconductor fabrication includes forming a first array of semiconductor circuitry and a second array of semiconductor circuitry separated by a singulation region and a contact region. The method also includes forming a first array of process control monitoring structures within the singulation region of a substrate.
Infineon Technologies Austria Ag


new patent

Semiconductor device and forming build-up interconnect structures over carrier for testing at interim stages


A semiconductor device has a first interconnect structure formed over the carrier. A semiconductor die is disposed over the first interconnect structure after testing the first interconnect structure to be known good.
Stats Chippac Pte. Ltd.


new patent

Controlling azimuthal uniformity of etch process in plasma processing chamber


Apparatus, systems, and methods for controlling azimuthal uniformity of an etch process in a plasma processing chamber are provided. In one embodiment, a plasma processing apparatus can include a plasma processing chamber and an rf cage disposed above the plasma processing chamber.
Mattson Technology, Inc.


new patent

Non-destructive, wafer scale method to evaluate defect density in heterogeneous epitaxial layers


A semiconductor material stack of, from bottom to top, a first semiconductor material having a first lattice constant and a second semiconductor material having a second lattice constant that may or may not differ from the first lattice constant and is selected from an iii-v compound semiconductor and germanium is provided. The second semiconductor material of the semiconductor material stack is then scanned using an atomic force microscope (afm) operating in a tapping mode to provide an afm image of the second semiconductor material of the semiconductor material stack.
International Business Machines Corporation


new patent

Method and reducing radiation induced change in semiconductor structures


Embodiments of the present disclosure relate to an apparatus and a method for reducing the adverse effects of exposing portions of an integrated circuit (ic) device to various forms of radiation during one or more operations found within the ic formation processing sequence by controlling the environment surrounding and temperature of an ic device during one or more parts of the ic formation processing sequence. The provided energy may include the delivery of radiation to a surface of a formed or a partially formed ic device during a deposition, etching, inspection or post-processing process operation.
Applied Materials, Inc.


new patent

Low-cost soi finfet technology


A method of forming an soi fin using a porous semiconductor. The method may include forming a stack of semiconductor layers on a substrate, the stack includes a second semiconductor layer on a first semiconductor layer in a layered region; forming fins in the second semiconductor layer by etching a trench through an exposed portion of the of the second semiconductor layer; converting the first semiconductor layer into a porous semiconductor layer using a porousification process; and converting the porous semiconductor layer into an oxide layer..
International Business Machines Corporation


new patent

Semiconductor devices and methods of fabricating semiconductor devices


Semiconductor devices are provided. A semiconductor device includes a substrate including first through fourth areas.
Samsung Electronics Co., Ltd.


new patent

Semiconductor device and forming the same


The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor.
United Microelectronics Corp.


new patent

Semiconductor device and manufacturing method thereof


A semiconductor device includes a substrate that includes a first region and a second region adjacent to the first region. The first region has a thickness that is smaller than a thickness of the second region, and a nitride semiconductor layer is provided on the first region of the substrate..
Kabushiki Kaisha Toshiba


new patent

Structure and formation damascene structure


A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first conductive feature over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


new patent

Semiconductor device and manufacturing the same


According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a graphene film on a catalytic layer, removing a part of the graphene film to form an exposed side surface of the graphene film, introducing dopant into the graphene film from the exposed side surface, and forming a graphene interconnect by patterning the graphene film into which the dopant is introduced.. .
Kabushiki Kaisha Toshiba


new patent

Method for manufacturing semiconductor device


A method for manufacturing a semiconductor device is provided. The method comprises steps as follows.
United Microelectronics Corporation


new patent

Reliable contacts


Semiconductor device and method for forming a semiconductor device are presented. The method includes providing a substrate having a device component with a contact region.
Globalfoundries Singapore Pte. Ltd.


new patent

Method for producing semiconductor device


A semiconductor device is produced while keeping a short circuit margin between its interconnects. A method therefor includes a step in which when a multilayered resist is used to make an interconnect trench in an interlayer dielectric, a mixed gas including, as components thereof, at least cf4 gas, c3h2f4 gas and o2 gas is used to perform dry etching in order to form the multilayered resist..
Renesas Electronics Corporation


new patent

Manufacturing semiconductor device


In order to provide a semiconductor device with high reliability while manufacturing cost is being suppressed, dry etching for an insulating film is performed by using mixed gas containing at least cf4 gas and c3h2f4 gas as its components.. .
Renesas Electronics Corporation


new patent

Handle substrate for use in manufacture of semiconductor-on-insulator structure and manufacturing thereof


A method is provided for preparing a high resistivity silicon handle substrate for use in semiconductor-on-insulator structure. The handle substrate is prepared to comprise thermally stable charge carrier traps in the region of the substrate that will be at or near the buried oxide layer (box) of the final semiconductor-on-insulator structure.
Sunedison Semiconductor Limited (uen201334164h)


new patent

Cup-wash device, semiconductor apparatus, and cup cleaning method


A cup-wash device is provided. The cup-wash device includes a supporting disk and a base disposed on the supporting disk.
Taiwan Semiconductor Manufacturing Co., Ltd


new patent

Method and transfer of semiconductor devices


An apparatus includes a first frame to hold a wafer tape having a first side and a second side. A plurality of semiconductor device dies are disposed on the first side of the wafer tape.
Rohinni, Inc.


new patent

Method of manufacturing semiconductor device and semiconductor manufacturing apparatus


A method of manufacturing a semiconductor device uses a semiconductor manufacturing apparatus including a turn table allowing placement of at least first and second semiconductor substrates and being capable of moving positions of the first and the second semiconductor substrates by turning, a first film forming chamber, and a second film forming chamber. The first and the second film forming chambers are provided with an opening capable of loading and unloading the first and the second semiconductor substrates by lifting and lowering the first and the second semiconductor substrates placed on the turn table.
Kabushiki Kaisha Toshiba


new patent

Wafer pin chuck fabrication and repair


In a wafer chuck design featuring pins or “mesas” making up the support surface, engineering the pins to have an annular shape, or to contain holes or pits, minimizes sticking of the wafer, and improves wafer settling. In another aspect of the invention is a tool and method for imparting or restoring flatness and roughness to a surface, such as the support surface of a wafer chuck.
M Cubed Technologies, Inc.


new patent

Semiconductor manufacturing method and laminated body


A semiconductor manufacturing method according to a present embodiment includes forming a supporter on a second surface of a semiconductor substrate opposite to a first surface to be ground of the semiconductor substrate. The semiconductor manufacturing method includes thinning the thickness of the semiconductor substrate by grinding the first surface.
Kabushiki Kaisha Toshiba


new patent

Semiconductor manufacturing method and semiconductor manufacturing device


According to one embodiment, a semiconductor manufacturing method for a stacked body that includes a semiconductor substrate, a supporting substrate containing silicon, and a joining layer arranged between the semiconductor substrate and the supporting substrate to joint the semiconductor substrate and the supporting substrate, in which a surface of the semiconductor substrate opposite to the joining layer is to be ground, includes irradiating the stacked body with electromagnetic wave having energy of 0.11 to 0.14 ev from a side of the supporting substrate, and separating the semiconductor substrate from the supporting substrate.. .
Kabushiki Kaisha Toshiba


new patent

Method for transfer of semiconductor devices


A method of transferring semiconductor devices to a product substrate includes positioning a surface of the product substrate to face a first surface of a semiconductor wafer having the semiconductor devices thereon, and actuating a transfer mechanism to cause the transfer mechanism to engage a second surface of the semiconductor wafer. The second surface of the semiconductor wafer is opposite the first surface of the semiconductor wafer.
Rohinni, Inc.


new patent

Wafer transport method


A wafer transport method is provided. The wafer transport method includes loading an initial carrier containing a first wafer and a second wafer on a first semiconductor apparatus, and processing the first wafer by the first semiconductor apparatus, and loading the first wafer into a first carrier disposed on the first semiconductor apparatus.
Taiwan Semiconductor Manufacturing Co., Ltd.


new patent

Nitrogen oxide abatement in semiconductor fabrication


Embodiments enclosed herein relate to methods and apparatus for reducing nitrogen oxides (nox) produced during processing, such as during semiconductor fabrication processing. A processing system may include an abatement controller and an effluent abatement system, wherein the abatement controller controls the effluent abatement system to reduce nox production, while ensuring abatement of the effluent gases from the processing system.
Applied Materials, Inc.


new patent

Semiconductor device and manufacturing method thereof


An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of making electronic devices, and electronic devices made thereby, that utilize a film assist mold process..
Amkor Technology, Inc.


new patent

Thermally-enhanced provision of underfill to electronic devices


A method of feeding underfill material to fill a space between a semiconductor die and a substrate onto which the semiconductor die has been bonded, the method comprises positioning a stencil over the semiconductor die. The stencil has an elongated slot extending adjacent to an edge of the semiconductor die.
Asm Technology Singapore Pte Ltd


new patent

Lead frame structure, manufacturing lead frame structure, and semiconductor device


A lead frame structure includes a lead frame having a first surface, a second surface opposed to, and facing away from, the first surface, and a first through-hole extending through the lead frame from the first surface to the second surface, and a heat sink having a third surface contacting the second surface, a fourth surface opposed to, and facing away from, the third surface, and a second through-hole extending through the heat sink from the third surface to the fourth surface, and overlying the location of the first through-hole. The material of one of the heat sink and the lead frame extends through a through opening of the other of the heat sink and the lead frame and extends over a portion of the surface of the other of the heat sink and the lead frame on the second or fourth surfaces..
Kabushiki Kaisha Toshiba


new patent

Semiconductor device and manufacturing method thereof


A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide a method for manufacturing a semiconductor device, and a semiconductor device produced thereby, that comprises an interposer without through silicon vias..
Amkor Technology, Inc.


new patent

Semiconductor device, manufacturing the same and power converter


An object is to avoid an increase in contact resistance of an ohmic electrode by etching in a semiconductor device. There is provided a method of manufacturing a semiconductor device.
Toyoda Gosei Co., Ltd.


new patent

Semiconductor manufacturing method


A semiconductor manufacturing method in accordance with an embodiment includes feeding a first gas, which contains a component of a first film, to a reaction chamber, and forming a first film over a semiconductor substrate, which is accommodated in the reaction chamber, through plasma cvd. The semiconductor manufacturing method includes feeding a second gas to the reaction chamber after forming the first film, allowing the first gas in the reaction chamber to react on the second gas, and forming a second film, which has a composition different from that of the first film, over the surface of the first film.
Kabushiki Kaisha Toshiba


new patent

Method for thermal process in packaging assembly of semiconductor


A method for thermal process in packaging assembly of semiconductor is disclosed. The high-pressure overheated vapor is injected into the process chamber.

new patent

Method of manufacturing semiconductor device


In one embodiment, a method of manufacturing a semiconductor device includes forming a first silicon oxide film having a first carbon content above a substrate. The method further includes forming a second silicon oxide film having a second carbon content different from the first carbon content on the first silicon oxide film.
Kabushiki Kaisha Toshiba


new patent

Method of interfacial oxide layer formation in semiconductor device


A method of an interfacial oxide layer formation comprises a plurality of steps. The step (s1) is to remove a native oxide layer from a surface of a substrate; the step (s2) is to form an oxide layer on a surface of a substrate by piranha solution (spm); the step (s3) is to cleaning a surface of the oxide layer by standard clean 1 (sc1), and the step (s4) is to etch he oxide layer by a solution comprising diluted hydrogen fluoride (dhf) and ozonized pure water (dio3)..
United Microelectronics Corporation


new patent

Method for forming patterns with sharp jogs


The present disclosure provides a method for forming patterns in a semiconductor device. The method includes forming a main pattern on a substrate; forming a spacer on sidewalls of the main pattern; forming a cut pattern having an opening by a first lithography process; and performing a cut process to selectively remove portions of the spacer within the opening of the cut pattern while the main pattern remains unetched, thereby defining a circuit pattern by the main pattern and the spacer.
Taiwan Semiconductor Manufacturing Company, Ltd.


new patent

Method to improve finfet cut overlay


A patterned photoresist having an overlay tolerance of (x+y)/2 is formed over preselected hard mask portions or semiconductor fin portions, wherein x is a width of a semiconductor fin and y is a distance between a neighboring pair of semiconductor fins. Hard mask portions or semiconductor fin portions not protected by the patterned photoresist are then removed by an isotropic etching process.
International Business Machines Corporation


new patent

Atomic layer process chamber for 3d conformal processing


Embodiments described herein relate to methods for forming or treating material layers on semiconductor substrates. In one embodiment, a method for performing an atomic layer process includes delivering a species to a surface of a substrate at a first temperature, followed by spike annealing the surface of the substrate to a second temperature to cause a reaction between the species and the molecules on the surface of the substrate.
Applied Materials, Inc.


new patent

Silicide region of gate-all-around transistor


The disclosure relates to a semiconductor device and methods of forming same. A representative structure for a semiconductor device comprises a substrate; a nanowire structure protruding from the substrate having a channel region disposed between a source region and a drain region; a pair of silicide regions extending into opposite sides of the source region, wherein each of the pair of silicide regions comprise a vertical portion adjacent to the source region and a horizontal portion adjacent to the substrate; and a metal gate surrounding a portion the channel region..
Taiwan Semiconductor Manufacturing Company, Ltd.


new patent

Semiconductor structure and manufacturing method thereof


A semiconductor structure comprising a first layer, a metal layer and a second layer is disclosed. The first layer comprises a recessed surface.
Taiwan Semiconductor Manufacturing Company Ltd.


new patent

Method of forming a semiconductor structure


A method of forming a semiconductor device is disclosed. A substrate having a dielectric layer thereon is provided.
United Microelectronics Corp.


new patent

Semiconductor device and manufacturing process thereof


A semiconductor device is provided which includes a dielectric layer over a gate structure of the semiconductor device. The semiconductor device also includes a conductive interconnect configured to couple the gate structure with an i/o region over the conductive interconnect.
Taiwan Semiconductor Manufacturing Company Ltd.


new patent

Cut last self-aligned litho-etch patterning


The present disclosure relates to a method of performing a semiconductor fabrication process. In some embodiments, the method is performed by forming a spacer material within openings in a first masking layer overlying a second masking layer, and forming a reverse material over a part of the spacer material.
Taiwan Semiconductor Manufacturing Co., Ltd.


new patent

Self-aligned patterning process


Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a plurality of spacers over a first hard mask layer to form a first mask pattern, and forming a first photoresist over the plurality of spacers.
Taiwan Semiconductor Manufacturing Company, Ltd.


new patent

Substrate carrier for a reduced transmission of thermal energy


According to the present disclosure, a semiconductor substrate handling systems and substrate carrier is provided. The substrate carrier for holding a substrate to be processed and for transporting the substrate in or through a processing area with a transport device includes a main portion for holding the substrate; a first end portion adapted to be supported by the transport device; and at least one first intermediate portion connecting the main portion with the first end portion.
Applied Materials, Inc.


new patent

Semiconductor processing apparatus with protective coating including amorphous phase


Embodiments of the invention relate to compositions including a yttrium-based fluoride crystal phase, or a yttrium-based oxyfluoride crystal phase, or an oxyfluoride amorphous phase, or a combination of these materials. The compositions may be used to form a solid substrate for use as a semiconductor processing apparatus, or the compositions may be used to form a coating which is present upon a surface of substrates having a melting point which is higher than about 1600°, substrates such as aluminum oxide, aluminum nitride, quartz, silicon carbide and silicon nitride, by way of example..
Applied Materials, Inc.


new patent

Plasma etching of porous substrates


The disclosed technology generally relates to semiconductor fabrication, and more particularly to plasma etching of dielectric materials having pores. In one aspect, a method for etching a porous material in an environment includes contacting the porous material with an organic gas at a pressure and a temperature.
Katholieke Universiteit Leuven


new patent

Phase plate, fabricating same, and electron microscope


A phase plate capable of suppressing electrification and a method of fabricating the plate are provided. The phase plate is for use in an electron microscope and includes a phase control layer provided with a through-hole and at least one conductive layer covering and closing off the through-hole.
Jeol Ltd.


new patent

Systems and methods for energy saving contactor


A control circuit for an energy saving contactor including at least one power contact is provided. The control circuit includes a power supply unit, an energy storage circuit coupled to the power supply unit, a first transducer coupled to the power supply unit and configured to switch the at least one power contact from an open armature position to a closed armature position, a latch system configured to maintain the at least one power contact in the closed armature position, a second transducer coupled to the power supply unit and configured to disengage the latch system to cause the at least one power contact to switch from the closed armature position to the open armature position, and a controller configured to control electrical power supplied from the power supply to the first and second transducers to selectively activate the first and second transducers based on monitored input voltage conditions..
General Electric Company


new patent

Semiconductor memory device


A semiconductor memory device includes a block including a plurality of string units, each including a plurality of memory cells electrically connected in series, a bad string register in which information indicating which of the string units is a bad string is stored, and a control circuit. The control circuit controls an erase operation on the memory cells, the erase operation including a first erase operation followed by a first verify operation and as needed a subsequent erase operation followed by a subsequent verify operation.
Kabushiki Kaisha Toshiba


new patent

Semiconductor device


The trimming range of a reference current is extended larger than that of the related art. A semiconductor device includes a reference current generating circuit that generates a reference current.
Renesas Electronics Corporation


new patent

Semiconductor memory device


A semiconductor memory device includes memory cells, word lines that are electrically connected to gates of the memory cells, a source line that is electrically connected to one end of the memory cells, and a controller that executes a read operation over first, second, third, and fourth time periods. A first voltage is applied to a selected word line during the first and second time periods of the first operation, and a second voltage that is higher than the first voltage is applied to the selected word line during the third and fourth time periods of the second operation.
Kabushiki Kaisha Toshiba


new patent

Semiconductor memory device and data erasing method


A semiconductor memory device includes a memory cell array including a plurality of groups of memory cells above a substrate, the groups including a first group and a second group, each of the first and second groups including a first memory string and a second memory string, the first memory string including first memory cells that are disposed in a first layer, the second memory string including second memory cell that are disposed in a second layer above the first layer, and a controller configured to perform an erasing operation on the memory cells, the erasing operation including a verifying operation on the memory cells to determine on a layer by layer basis whether the memory cells failed to erase data stored therein.. .
Kabushiki Kaisha Toshiba


new patent

Semiconductor storage device


When writing reram cells, it is pursued to set the cells in a sufficiently high or low resistance state, while preventing excessive writing. Disclosed is a semiconductor storage device including memory cells, each including a variable resistance element, and control circuitry that executes an off writing process of applying off writing pulse to a memory cell to turn it into high resistance state and an on writing process of applying on writing pulse to turn it into low resistance state.
Renesas Electronics Corporation


new patent

Semiconductor integrated circuit


A semiconductor integrated circuit according to an embodiment includes a plurality of first wiring lines electrically connected to a plurality of input wiring lines; a plurality of second wiring lines electrically connected to a plurality of output wiring lines, the second wiring lines crossing the first wiring lines; and a plurality of cell arrays each of which includes memory elements disposed at intersection regions of a part of the first wiring lines and a part of the second wiring lines, each of the memory elements including a first terminal and a second terminal, the first terminal being electrically connected to one of the first wiring lines, the second terminal being electrically connected to one of the second wiring lines, and each of the second wiring lines being electrically connected to at most one of the cell arrays.. .
Kabushiki Kaisha Toshiba


new patent

Spin transistor memory


A spin transistor memory according to an embodiment includes: a first semiconductor region, a second semiconductor region, and a third semiconductor region, each being of a first conductivity type and disposed in a semiconductor layer; a first gate disposed above the semiconductor layer between the first semiconductor region and the second semiconductor region; a second gate disposed above the semiconductor layer between the second semiconductor region and the third semiconductor region; and a first ferromagnetic layer, a second ferromagnetic layer, and a third ferromagnetic layer disposed on the first semiconductor region, the second semiconductor region, and the third semiconductor region respectively.. .
Kabushiki Kaisha Toshiba


new patent

Semiconductor memory apparatus and operating method thereof


A semiconductor memory apparatus may include: a memory area; and a controller including a register configured to store parameter setting data, and to provide the parameter setting data to the memory area based on a data transmission enable signal enabled according to a parameter setting command or parameter get command.. .
Sk Hynix Inc.






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