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Duc patents



      

This page is updated frequently with new Duc-related patent applications.




Date/App# patent app List of recent Duc-related patents
06/23/16
20160183391 
 Methods and devices for miniaturization of high density wafer based electronic 3d multi-chip modules patent thumbnailMethods and devices for miniaturization of high density wafer based electronic 3d multi-chip modules
Techniques for constructing a multi-chip module semiconductor device are provided herein. The techniques include placing electronic modules on a first surface and a second surface, with electrical connections for the electronic modules being proximate to respectively mounted surfaces, disposing a mold material on one of the mounting surfaces to substantially surround corresponding electronic modules, orienting the mounting surface without the mold material disposed thereon, relative to the mounting surface with the mold material disposed thereon to cause the mold material to substantially surround each electronic module while maintaining a minimum distance between the electronic modules mounted on each mounting surface.

06/23/16
20160183376 
 Electronic packages with pre-defined via patterns and methods of making and using the same patent thumbnailElectronic packages with pre-defined via patterns and methods of making and using the same
An electronic package is provided. The electronic package includes a substrate and a plurality of vias defined by a corresponding plurality of pre-defined via patterns.

06/23/16
20160183371 
 Microvia structure of flexible circuit board and manufacturing method thereof patent thumbnailMicrovia structure of flexible circuit board and manufacturing method thereof
Disclosed urea microvia structure of a flexible circuit board and a manufacturing method thereof. A first through hole is formed in a first conductive layer of a flexible circuit board and a first exposed zone is defined.

06/23/16
20160183370 
 Zero-misalignment via-pad structures patent thumbnailZero-misalignment via-pad structures
A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure.

06/23/16
20160183330 
 Systems and methods for interchangeable induction heating systems patent thumbnailSystems and methods for interchangeable induction heating systems
An induction heating system includes interchangeable secondary induction heating assemblies and/or secondary induction heating coil flux concentrators that are specifically configured for the particular type of weld being created and/or the particular weld joint where the weld is created. For example, the secondary induction heating assemblies and/or secondary induction heating coil flux concentrators may have specific physical configurations (e.g., shapes, contours, etc.) and/or include specific materials (e.g., ferrites) that are well suited for the particular type of weld being created and/or the particular weld joint where the weld is created.

06/23/16
20160183116 
 Method and apparatus of positioning mobile terminal based on geomagnetism patent thumbnailMethod and apparatus of positioning mobile terminal based on geomagnetism
A method and an apparatus of positioning a mobile terminal based on geomagnetism. The mobile terminal has at least one magnetic force sensor.

06/23/16
20160183063 
 Terminal for contents sharing, an operating method thereof, and a vehicle information providing terminal patent thumbnailTerminal for contents sharing, an operating method thereof, and a vehicle information providing terminal
Provided is a terminal of providing a vehicle interface to a vehicle information providing terminal, the terminal including: a terminal information collection unit configured to collect terminal information of the other terminal capable of transceiving contents data; a wireless communication unit configured to receive a reproduction request of the contents data transmitted from the other terminal; a contents interface generator configured to generate a contents interface provided through the vehicle interface based on the terminal information and the contents data reproduction request; and a contents data relay unit configured to reproduce the contents data received from the other terminal through the contents interface to control the reproduced contents data to be provided to the vehicle information providing terminal.. .

06/23/16
20160183027 
 Method for processing of sound signals patent thumbnailMethod for processing of sound signals
A method for processing audio signals for creating a three dimensional sound environment comprises: receiving at least one input signal from at least one sound source; creating a simulated signal at least partly based on the received at least one input signal, the simulated signal representing a simulation of at least one input signal reflecting from the ground or a floor; and creating an output signal at least partly on the basis of the simulated signal and the at least one received input signal, the output signal comprising a plurality of audio channels; at least two channels of the audio channels of the output signal representing signals for sound transducers above a listener's ear level at a nominal listening position, and at least two channels of the audio channels of the output signal representing signals for sound transducers below a listener's ear level at a nominal listening position.. .

06/23/16
20160183025 
 System and  speech reinforcement patent thumbnailSystem and speech reinforcement
A system and method for speech reinforcement may determine the spatial location of an audio source and the spatial location of a listener. An audio signal generated by the audio source may be captured.

06/23/16
20160183024 
 Method and  providing virtual audio reproduction patent thumbnailMethod and providing virtual audio reproduction
A method, apparatus and computer program product are provided to permit audio signals to provide additional information to a user regarding the distance to the source of the audio signals, thereby increasing a user's situational awareness. In the context of a method, a distance and a direction from a user to an object are determined.

06/23/16
20160183022 

Location determination according to auditory tones


Systems, methods, and apparatus to calibrate sounds fields are disclosed. An example implementation involves causing, via a transducer of a network device, the network device to produce an auditory tone.

06/23/16
20160183017 

Transducer devices and methods for hearing


A device to transmit an audio signal to a user may comprise a mass, a piezoelectric transducer, and a support to support the mass and the piezoelectric transducer with the eardrum. The piezoelectric transducer can be configured to drive the support and the eardrum with a first force and the mass with a second force opposite the first force.

06/23/16
20160183012 

Hearing device adapted for estimating a current real ear to coupler difference


The application relates to a hearing device comprising an ite-part adapted for being located at or in an ear canal of a user, a configurable signal processing unit for processing an input signal, and a feedback estimation unit for providing a current estimate of an acoustic feedback path from an output transducer to an input transducer, a memory for storing frequency dependent reference estimates of the acoustic feedback path the real ear to coupler difference, when the ite-part is correctly mounted, an optional probe signal generator for generating a probe signal at least in a specific measurement mode, wherein the hearing device is configured to perform measurement of the current estimate of the acoustic feedback path. The hearing device further comprises a control unit operatively connected to said memory and to said signal processing unit, and configured to compare said current estimate of the acoustic feedback path with said reference estimate of the acoustic feedback path, and to provide a current feedback path difference measure, and to determine a current estimate of real ear to coupler difference from the current feedback path difference measure.

06/23/16
20160183007 

Acoustic galvanic isolation device


An acoustic galvanic isolation device includes a substrate capable of transmitting an acoustic wave. A first network of vibrating membrane electroacoustic transducers is arranged on a first surface of the substrate.

06/23/16
20160183006 

Piezoelectric speaker and electroacoustic transducer


A piezoelectric speaker has a piezoelectric element and vibration plate. The piezoelectric element has a base body with a mounting surface, as well as first and second terminals that are formed on the mounting surface with a distance between them.

06/23/16
20160182992 

Microspeaker acoustical resistance assembly


An electro-acoustic transducer is provided that comprises a diaphragm and a magnet assembly comprising a magnet and a back plate. The back plate comprises at least one first vent.

06/23/16
20160182939 

Mechanism for transference of media meta-data


The disclosed examples encompass a media sending device, a media receiving device or a method of sending and reproducing media. For example, a media sending device may store media content and a meta-data file which includes media customization information to facilitate reproduction of the media content and an identifier that identifies a type of the information in the meta-data file.

06/23/16
20160182938 

System for controlling electronic devices by means of voice commands, more specifically a remote control to control a plurality of electronic devices by means of voice commands


A remote control for generating output signals apt at controlling one or more electronic device, characterized in that said remote control includes a sound transducer, a speech recognition unit for recognizing voice commands, a memory for storing information relative to available content of said one or more electronic device and a control signal generating and receiving unit for generating control signals corresponding to said voice commands, for controlling said one or more electronic device.. .

06/23/16
20160182846 

Monolithically integrated rgb pixel array and z pixel array


An apparatus is described that includes first and second pixels arrays integrated on a same semiconductor chip. The first pixel array contains visible light pixels and no z pixels.

06/23/16
20160182574 

Method and supporting facility control of terminal


A method and an apparatus for supporting facility control of a terminal are provided. The method includes a sensor device receiving facility-related information from a remote control device of a facility to which the sensor device is attached, driving at least one sensor in accordance with the facility-related information, determining a kind of the facility based on a result of detecting through the at least one driven sensor, and transmitting a registration request for the facility of which the kind has been determined to a gateway.

06/23/16
20160182060 

Duty cycle detection circuit and semiconductor apparatus including the same


A duty cycle detection circuit may include a detection block configured to generate a duty detection signal by detecting a duty cycle of an input clock; and a current amount control block configured to control a current flowing through the detection block in response to the input clock, regardless of a variation in a frequency of the input clock.. .

06/23/16
20160182041 

Semiconductor device and semiconductor system


According to one embodiment, a semiconductor device includes: a voltage line to which a first voltage is applied; a first circuit configured to operate by using the first voltage; and a second circuit configured to control a connection between the voltage line and the first circuit. The second circuit includes: at least one first switch circuit configured to connect the first circuit and the voltage line based on a first control signal; and a second switch circuit including a plurality of switch sections configured to connect the first circuit and the voltage line based on a plurality of second control signals different from the first control signal..

06/23/16
20160182035 

Semiconductor device


A driver ic (integrated circuit) includes a power supply terminal; an output terminal to be coupled to a load element; a connection node on a current path between the power supply terminal and the output terminal; a substrate resistance, having one end coupled to the connection node; an output transistor including a gate, wherein the output transistor is coupled in series with the substrate resistance through the connection node; a resistance, having one end coupled to an other end of the substrate resistance; and a voltage detecting circuit configured to detect a voltage depending on a voltage between the one end of the substrate resistance and the other end of the substrate resistance, and to output an output signal, which is as an output of the voltage detecting circuit, to the gate of the output transistor.. .

06/23/16
20160182034 

Gate drive circuit and operating same


A gate drive circuit for applying a voltage to a gate of a semiconductor switching device is disclosed. The gate drive circuit includes a gate drive controller that provides voltage commands for operating the semiconductor switching device, a plurality of primary gate resistors coupled between the gate drive controller and the semiconductor switching device, one or more secondary gate resistors connected in parallel with the primary gate resistors, a primary transistor connected in series with each of the primary gate resistors, and a secondary transistor connected in series with each of the secondary gate resistors.

06/23/16
20160182032 

Semiconductor device


First and second external terminals are connected to high-voltage and low-voltage terminals, respectively, of a direct-current voltage source circuit in which first and second direct-current voltage sources are connected in series. A third external terminal is connected to a connecting point between the first and second direct-current voltage sources.

06/23/16
20160182031 

Semiconductor apparatus


A semiconductor apparatus includes a multiplication control block configured to generate a plurality of frequency control signals according to an input clock and a multiplication determination signal; and a clock output block configured to generate an output clock according to the input clock, the multiplication determination signal and the plurality of frequency control signals.. .

06/23/16
20160182029 

Strobe signal generation circuit and semiconductor apparatus using the same


A strobe signal generation circuit may include: a counter to generate a first source signal and a second source signal by counting an external strobe signal; a delay to generate a first delayed signal and a second delayed signal by delaying the first source signal and the second source signal by a preset time; and a combination unit to generate internal strobe signals by selectively combining the first source signal, the second source signal, the first delayed signal, and the second delayed signal.. .

06/23/16
20160182025 

Semiconductor device and semiconductor system including the same


A semiconductor device may include a control signal generation block configured to shift a level of a trimming signal and generate a selection control signal, and shift a level of a first enable signal and generate a driving control signal, when an internal voltage is raised to a level greater than a sensing reference voltage after an initialization period is ended. The semiconductor device may include an internal voltage generation block configured to select one of a plurality of trimming division voltages as a selected reference voltage in response to the selection control signal, and drive the internal voltage by comparing levels of the selected reference voltage and the internal voltage in response to the driving control signal..

06/23/16
20160181996 

Tube amplifier assembly having a power tube and a capacitor assembly


Tube amplifier assembly including a power tube that is configured to be coupled to a grounding deck and positioned within an opening of the grounding deck. The tube amplifier assembly also includes a tube adapter that is configured to be coupled to the grounding deck.

06/23/16
20160181993 

Sense amplifier and semiconductor memory device employing the same


The present disclosure herein relates to a sense amplifier and a semiconductor memory device employing the same. The sense amplifier includes an inverter including a pull-up transistor and a pull-down transistor, and a switching unit configured to change a connection relationship between the pull-up transistor and the pull-down transistor according to whether an input terminal of the inverter is precharged or a signal applied to the input terminal is sensed..

06/23/16
20160181992 

Magnetically coupled load modulation


A method, packaged semiconductor device, and system for controlling a secondary amplifier output current based on an input signal received from an amplifier input, converting electrical energy to magnetic energy at a secondary amplifier output inductor, coupling the magnetic energy from the secondary amplifier output inductor to a primary amplifier output inductor, converting the coupled magnetic energy to induced electrical energy at the primary amplifier output inductor, combining the induced electrical energy with output electrical energy from a primary amplifier gain element, and applying a combined electrical energy including the output electrical energy and the induced electrical energy to a primary amplifier load are provided.. .

06/23/16
20160181983 

Low power operational transconductance amplifier


A low power operational transconductance amplifier is disclosed. In an exemplary embodiment, an apparatus includes a transconductance stage configured to convert a first input voltage signal to first and second current signals and to convert a second input voltage signal to third and fourth current signals.

06/23/16
20160181964 

Partitioned motor drive subsea applications


A system includes an above-surface control unit and a subsea motor drive unit. The above-surface control unit includes a variable speed motor control circuit configured to generate at least one switch control signal and a first communications circuit configured to transmit the at least one switch control signal over a communications medium.

06/23/16
20160181953 

Drive control electric motor


The present invention relates to a drive control apparatus for an electric motor and a control method thereof. In the present invention, the generation of electric brake is suppressed while protecting a semiconductor relay from excessive surge voltage.

06/23/16
20160181948 

Three-level active neutral point converter


The invention relates to a active-neutral point clamped converter having at least one half-bridge circuit connected into a dc voltage circuit. Each half-bridge circuit has a high-potential-side input half-bridge and a low-potential-side input half-bridge in series.

06/23/16
20160181940 

Power conversion device


A power conversion device includes: a metal housing; a power semiconductor module that is contained in the metal housing and converts direct electric current to alternating electric current; a capacitor module that is contained in the metal housing and arranged side by side with the power semiconductor module, wherein the capacitor module smoothes the direct electric current supplied to the power semiconductor module; a substrate that has a drive circuit part mounted in a first region, the drive circuit part driving the power semiconductor module, and a control circuit part mounted in a second region, the control circuit part controlling the drive circuit part, wherein the substrate is disposed so as to cover over the metal housing; a base plate that extends in a space in which the second region of the substrate and the capacitor module oppose to each other, and that is electrically connected to the metal housing; and a first noise shielding member that extends in a direction along a boundary between the first region and the second region of the substrate, wherein the first noise shielding member separates the space from a space of the housing in which the power semiconductor module is disposed, and the first noise shielding member is electrically connected to the metal housing or a ground of the control circuit part.. .

06/23/16
20160181912 

Regulation for multi-phase voltage pump system


An approach of operating a voltage pump system for a semiconductor chip. The approach includes one or more voltage pumps receiving a pair of clock signal inputs.

06/23/16
20160181907 

Current balancing system for semiconductor elements in parallel


A circuit is for balancing currents flowing through a parallel assembly of semiconductor components of the same type. The circuit may include a respective regulation circuit for each semiconductor component.

06/23/16
20160181906 

Power converter with negative current capability and low quiescent current consumption


Dc-dc current mode switching power converters that have negative current capability are presented. The power converters comprise: an output node, a pass device connected to the output node of the power converter, the pass device being configured to operate in accordance with a pwm signal and to supply at least a portion of an output current of the power converter, a pwm comparator for generating the pwm signal for controlling operation of the pass device in accordance with a current conducted by the pass device and a difference between an output voltage of the power converter and a reference voltage.

06/23/16
20160181884 

Systems and methods for preventing electrical faults associated with motor leads


Systems and methods for protecting motor lead from debris and fluid contamination. In one embodiment, detachable, flexible lead wires within an esp motor are covered by protective sleeves that are sealed against the end connectors of the leads.

06/23/16
20160181875 

Method of and detecting coil alignment error in wireless inductive power transmission


A method for detecting induction coil alignment error in resonant induction wireless power apparatus includes an eddy current coil array superimposed upon the primary induction coil, a switching device for each eddy current coil, a voltage detector such as a low power rectifier connected to the secondary induction coil, an analog-to-digital converter, primary and secondary side micro-controllers, and, in a vehicle charging embodiment, a vehicle operator interface. During coil alignment, the primary side induction coil operates at low power.

06/23/16
20160181848 

Charging station, charging inductive charging


The present invention relates to a charging station for inductive charging of an electrical device having a rechargeable battery and a receiving induction coil. The charging station comprises: a housing comprising a plurality of panels forming an interior volume arranged to host the electrical device; a plurality of primary transmitting induction coils; and a controller arranged to excite the plurality of primary transmitting induction coils with charging current; wherein each of the plurality of primary transmitting induction coils is arranged at a separate panel of the housing..

06/23/16
20160181792 

Semiconductor device and current limiting method


A semiconductor device, including a main transistor configured to supply power from a power source to a load, and a current limiting device including a control transistor. The current limiting device is configured to detect that the current flowing from the main transistor is an overcurrent, and to limit the current upon determining that the current is equal to or greater than a current limit value, and an operating voltage of the control transistor is equal to or greater than a current limiting activation voltage.

06/23/16
20160181761 

Semiconductor light device and manufacturing the same


Provided is a semiconductor light device comprising a semiconductor substrate having a first conduction type; a first cladding layer having the first conduction type deposited above the semiconductor substrate; an active layer; a second cladding layer having a second conduction type; and a contact layer. The active layer includes a window portion that is disordered via diffusion of vacancies and a non-window portion having less disordering than the window portion, and the contact layer includes a first region and a second region that is below the first region and has greater affinity for hydrogen than the first region..

06/23/16
20160181760 

Semiconductor laser device and manufacturing method thereof, and submount manufacturing method


A semiconductor laser device can include an insulating single crystal sic having a first surface, a second surface, and micropipes having openings in the first surface and the second surface. A conductive base can be provided on a side of the first surface of the single crystal sic, and a semiconductor laser element can be provided on a side of the second surface of the single crystal sic.

06/23/16
20160181683 

Device for radio-frequency power coupling and using the device


A device and a method for utilizing the device for radio-frequency (rf) power coupling, particularly a power combiner and/or divider, includes a box shaped casing forming the outside conductor, and connectors for inputting and outputting rf-power, which are electrically connected to at least one center conductor, where the electrical connection between the connectors and the at least one center conductor is a direct electrical and mechanical connection.. .

06/23/16
20160181592 

Method for manufacturing transparent electrode film


Provided herein is a method for forming a transparent electrode film, the method comprising forming an electrode pattern by printing an electrode pattern on a release film using a metal ink composition; forming an insulating layer by applying a curable resin on the release film on which the electrode pattern has been formed; forming a substrate layer by laminating a substrate on the insulating layer; removing the release film; and forming a conductive layer by applying a conductive material on the electrode pattern from which the release film has been removed.. .

06/23/16
20160181562 

Organic light emitting display device


An organic light emitting display device comprises two emission portions between first and second electrodes, wherein at least one among the two emission portions includes two emitting layers, whereby efficiency and a color reproduction ratio may be improved.. .

06/23/16
20160181559 

Laminate and manufacturing method therefor


The present application relates to a laminate and a method for preparing the same. The present application provides a laminate, including: a substrate; a first layer provided on the substrate; a second layer which is provided on the first layer and has an overhang structure with a width which is larger than that of the first layer; a conductive layer which is provided on the substrate and the second layer, in which the conductive layer provided on the substrate is electrically shorted from the conductive layer provided on the second layer..

06/23/16
20160181556 

Semiconductor device, manufacturing the same, and electronic apparatus


A semiconductor device includes: a gate electrode; an organic semiconductor film forming a channel; and a pair of source-drain electrodes formed on the organic semiconductor film, the pair of source-drain electrodes each including a connection layer, a buffer layer, and a wiring layer that are laminated in order.. .

06/23/16
20160181534 

Polymers based on fused diketopyrrolopyrroles


The present invention relates to polymers comprising one or more (repeating) unit(s) of the formula (i), wherein y is a group of formula (ii); and their use as ir absorber, organic semiconductor in organic devices, especially in organic photovoltaics and photodiodes, or in a device containing a diode and/or an organic field effect transistor. The polymers according to the invention can have excellent solubility in organic solvents 10 and excellent film-forming properties.

06/23/16
20160181531 

Film-forming composition, film formed thereby, and manufacturing organic semiconductor element using same


This film-forming composition is suitably usable for the manufacturing of an organic semiconductor element because the composition can form a film on an organic semiconductor film; and the formed film has resistance to an etching solvent during the fine pattern processing of the organic semiconductor film by photolithography etc.. .

06/23/16
20160181522 

Electronic device and fabricating the same


An electronic device with improved variable resistance characteristics and a method for fabricating the same are provided. In an embodiment of the disclosed technology, a method for forming an electronic device with a semiconductor memory includes forming a crystalized doped layer over a substrate; forming a barrier layer over the doped layer; forming a metal layer over the barrier layer; and reacting the barrier layer with a portion of the metal layer.

06/23/16
20160181520 

Electronic device and fabricating the same


Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a substrate; a variable resistance element formed over the substrate; a top electrode formed over the variable resistance element; a barrier layer formed over the top electrode and including a groove; an interlayer dielectric layer formed over the substrate to have a layer structure in which the variable resistance element, the top electrode and the barrier layer are formed in the interlayer dielectric layer; and a metal wiring including a portion formed in the groove of the barrier layer..

06/23/16
20160181514 

Electronic device and fabricating the same


Disclosed are an electronic device comprising a semiconductor memory and a method for fabricating the same, which enable the characteristics of a variable resistance element to be improved. The electronic device includes a semiconductor memory.

06/23/16
20160181513 

Semiconductor structures and devices and methods of forming semiconductor structures and magnetic memory cells


A magnetic cell includes a magnetic region formed from a precursor magnetic material comprising a diffusive species and at least one other species. An amorphous region is proximate to the magnetic region and is formed from a precursor trap material comprising at least one attracter species having at least one trap site and a chemical affinity for the diffusive species.

06/23/16
20160181511 

Semiconductor devices and methods of fabricating the same


Provided are semiconductor devices and methods of fabricating the same. The semiconductor device may include lower wires, upper wires crossing the lower wires, select elements provided at intersections between the lower and upper wires, and memory elements provided between the select elements and the upper wires.

06/23/16
20160181510 

Semiconductor device and fabricating the same


A semiconductor device includes a magnetic tunnel junction (mtj) element, an electrode layer pattern formed over the mtj element, a protective layer for protecting the mtj element and the electrode layer pattern, wherein the protective layer is arranged to expose a first area of the electrode layer pattern, a first insulation layer formed over the protective layer and arranged to form a first hole exposing the first area of the electrode layer pattern, a second insulation layer formed over the first insulation layer and arranged to form a second hole over the first hole, wherein the second hole has a larger width than the first hole, and an overhang pattern protruding from a sidewall of the first hole and suitable for preventing the protective layer on a sidewall of the mtj element.. .

06/23/16
20160181498 

Enhanced power conversion efficiency from thermoelectric metamaterials


A thermoelectric metamaterial is provided, comprising a plurality of component materials selected from the group consisting of dielectrics, semiconductors, semimetals, and metals. The component materials are placed into contact with one another and arranged in a selected geometrical configuration adapted to achieve a thermal conductivity of the metamaterial that is different from the thermal conductivity of each of the component materials.

06/23/16
20160181491 

Optoelectronic semiconductor component


An optoelectronic semiconductor component including an optoelectronic semiconductor chip having a first surface, wherein the first surface is a radiation emission surface of the optoelectronic semiconductor chip, the semiconductor chip is embedded in a mold body, the first surface is elevated with respect to a top side of the mold body, and a reflective layer is arranged on the top side of the mold body.. .

06/23/16
20160181489 

Light emitting device and light emitting device package


A light emitting device includes a light emitting layer, a substrate that is transparent to an emission wavelength of the light emitting layer and positioned to receive an emission wavelength from the light emitting layer, a convex pattern including a collection of a plurality of convex portions discretely arranged on a front surface of the substrate with a first pitch, an n type nitride semiconductor layer located on the front surface of the substrate to cover the convex pattern and a p type nitride semiconductor layer located on the light emitting layer. The light emitting layer is located on the n type semiconductor layer.

06/23/16
20160181488 

Semiconductor light emitting device


A semiconductor light emitting device including a plurality of light emitting elements can be miniaturized while enabling to emit light with high luminance. The semiconductor light emitting device can include a mounting substrate, and a plurality of semiconductor light emitting elements mounted on the mounting substrate side by side, each of the semiconductor light emitting elements having a semiconductor structure layer that can include a first semiconductor layer of a first conductivity type, an active layer, and a second semiconductor layer of a second conductivity type opposite to the first conductivity type, which are layered in that order.

06/23/16
20160181487 

Photon extraction from nitride ultraviolet light-emitting devices


In various embodiments, a rigid lens is attached to a light-emitting semiconductor die via a layer of encapsulant having a thickness insufficient to prevent propagation of thermal expansion mismatch-induced strain between the rigid lens and the semiconductor die.. .

06/23/16
20160181481 

Method for producing a conversion lamina and conversion lamina


A method for producing at least one conversion lamina for a radiation-emitting semiconductor component is specified. A base material including a conversion substance contained therein is applied to a substrate by means of a double-layered stencil.

06/23/16
20160181478 

Semiconductor light emitting device and fabrication the semiconductor light emitting device


A semiconductor light emitting device which can control of current density and can optimize current density and in which a rise in luminosity is possible, and a fabrication method of the semiconductor light emitting device are provided. The semiconductor light emitting device including: a semiconductor substrate structure including a semiconductor substrate, a first metal layer placed on a first surface of the semiconductor substrate, and a second metal layer placed on a second surface of the semiconductor substrate; and a light emitting diode structure including a third metal layer placed on the semiconductor substrate structure, a current control layer placed on the third metal layer and composed of a transparent insulating film and a current control electrode, an epitaxial growth layer placed on the current control layer, and a surface electrode placed on the epitaxial growth layer, wherein the semiconductor substrate structure and the light emitting diode structure are bonded by using the first metal layer and the third metal layer..

06/23/16
20160181477 

Light emitting diode and fabricating the same


A light emitting diode includes an n-type semiconductor layer disposed on a substrate; a p-type semiconductor layer disposed on a portion of the n-type semiconductor layer; an active layer disposed between the n-type semiconductor layer and the p-type semiconductor layer and generating light through recombination of electrons and holes; an ohmic contact layer disposed on the p-type semiconductor layer and including an indium tin oxide (ito) layer doped with a metal, a transparent conductive layer disposed on the ohmic contact layer to a different thickness than the ohmic contact layer and including an undoped ito layer, and a reflective layer disposed on the transparent conductive layer and including an oxide layer. Accordingly, the light emitting diode exhibits excellent current-voltage characteristics through improvement in reliability and electrical conductivity of the ohmic contact layer while improving luminous efficacy through the reflective layer formed of an oxide..

06/23/16
20160181475 

Semiconductor light-emitting device


A semiconductor light-emitting device including a first type doped semiconductor layer, a second type doped semiconductor layer, a light-emitting layer, and a contact layer is provided. The light-emitting layer is disposed between the first type doped semiconductor layer and the second type doped semiconductor layer.

06/23/16
20160181474 

Optoelectronic devices incorporating single crystalline aluminum nitride substrate


The invention provides an optoelectronic device adapted to emit ultraviolet light, including an aluminum nitride single crystalline substrate, wherein the dislocation density of the substrate is less than about 105 cm−2 and the full width half maximum (fwhm) of the double axis rocking curve for the (002) and (102) crystallographic planes is less than about 200 arcsec; and an ultraviolet light-emitting diode structure overlying the aluminum nitride single crystalline substrate, the diode structure including a first electrode electrically connected to an n-type semiconductor layer and a second electrode electrically connected to a p-type semiconductor layer. In certain embodiments, the optoelectronic devices of the invention exhibit a reverse leakage current less than about 10−5 a/cm2 at −10 v and/or an l80 of at least about 5000 hours at an injection current density of 28 a/cm2..

06/23/16
20160181472 

Semiconductor light-emitting device


A semiconductor light-emitting device including an n-type semiconductor layer, a plurality of p-type semiconductor layers, a light-emitting layer, and a contact layer is provided. The light-emitting layer is disposed between the n-type semiconductor layer and the whole of the p-type semiconductor layers.

06/23/16
20160181471 

Optoelectronic semiconductor chip comprising a multi-quantum well comprising at least one high barrier layer


An optoelectronic semiconductor chip includes a p-type semiconductor region, an n-type semiconductor region, and an active layer embodied as a multi-quantum well structure arranged between the p-type semiconductor region and the n-type semiconductor region. The multi-quantum well structure includes a plurality of alternating quantum well layers and barrier layers.

06/23/16
20160181469 

Semiconductor light-emitting device and manufacturing method thereof


A semiconductor light-emitting device including a first n-type semiconductor layer, a p-type semiconductor layer, and a light-emitting layer is provided. The first n-type semiconductor layer contains aluminum, and the concentration of the n-type dopant thereof is greater than or equal to 5×1018 atoms/cm3.

06/23/16
20160181468 

Variable composition transparent conductive oxide layer and methods of forming thereof


Provided are light emitting diodes (leds) and methods of fabricating such leds. An led may include a transparent conductive oxide (tco) layer having a varying refractive index.

06/23/16
20160181466 

Solar cell, manufacturing method therefor, solar-cell module, and manufacturing method therefor


Provided is a solar cell including a photoelectric conversion section having a first principal surface and a second principal surface, and a collecting electrode formed on the first principal surface of photoelectric conversion section. The photoelectric conversion section includes a semiconductor-stacked portion including a semiconductor junction, a first electrode layer which is a transparent electrode layer formed on the first principal surface side of the semiconductor-stacked portion, and a second electrode layer formed on the second principal surface side of the semiconductor-stacked portion.

06/23/16
20160181463 

Methods of treating a semiconductor layer


Methods for treating a semiconductor layer including a semiconductor material are presented. A method includes contacting at least a portion of the semiconductor material with a passivating agent.

06/23/16
20160181461 

Manufacturing solar cell


Provided is a method for manufacturing a solar cell with improved output characteristics. A hydrogen radical treatment, in which ions are not used, is performed on at least one of the first and second semiconductor layers (11, 13)..

06/23/16
20160181454 

Solar cell module and manufacturing the same


A solar cell module and a method for manufacturing the same are discussed. The solar cell module includes a front transparent substrate and a back substrate positioned opposite each other, a plurality of solar cells positioned between the front transparent substrate and the back substrate, each solar cell including a semiconductor substrate and first and second electrodes, the first and second electrodes being separated from each other on a back surface of the semiconductor substrate and each extending in a first direction, a first conductive line connected to the first electrode included in the each solar cell through a conductive adhesive, a second conductive line connected to the second electrode included in the each solar cell through the conductive adhesive, a first encapsulant positioned between the solar cells and the front transparent substrate, and a second encapsulant positioned between the solar cells and the back substrate..

06/23/16
20160181453 

Photodetector cell and solar panel with dual metal contacts and related methods


A photodetector cell may include a substrate, and a first contact carried by the substrate and having a first work function value. The photodetector cell may include a second contact carried by the substrate and having a second work function value different from the first work function value, and a semiconductor wire carried by the substrate and having a third work function value between the first and second work function values.

06/23/16
20160181450 

Multi-layer sputtered metal seed for solar cell conductive contact


Multi-layer sputtered metal seed for solar cell conductive contacts and methods of forming solar cell conductive contacts are described. In an example, a solar cell includes a substrate.

06/23/16
20160181448 

Photodetector with surface plasmon resonance


Methods and structures for providing single-color or multi-color photo-detectors leveraging plasmon resonance for performance benefits. In one example, a radiation detector includes a semiconductor absorber layer having a first electrical conductivity type and an energy bandgap responsive to radiation in a first spectral region, a semiconductor collector layer coupled to the absorber layer and having a second electrical conductivity type, and a plasmonic resonator coupled to the collector layer and having a periodic structure including a plurality of features arranged in a regularly repeating pattern..

06/23/16
20160181447 

Laser beam shaping for foil-based metallization of solar cells


Approaches for foil-based metallization of solar cells and the resulting solar cells are described. For example, a method of fabricating a solar cell involves locating a metal foil above a plurality of alternating n-type and p-type semiconductor regions disposed in or above a substrate.

06/23/16
20160181445 

Silicon photonics integration method and structure


Approaches for silicon photonics integration are provided. A method includes: forming at least one encapsulating layer over and around a photodetector; thermally crystallizing the photodetector material after the forming the at least one encapsulating layer; and after the thermally crystallizing the photodetector material, forming a conformal sealing layer on the at least one encapsulating layer and over at least one device.

06/23/16
20160181442 

Semiconductor device and manufacturing same


A semiconductor device includes: a first conductive type semiconductor device; a first conductive type drift region formed by epitaxial growth on the semiconductor substrate; a plurality of first conductive type vertical implantation regions formed by multistage ion implantation in the drift region, the vertical implantation regions having a prescribed vertical implantation width and a prescribed drift region width; an anode electrode disposed on the front surface of the drift region opposite to the semiconductor substrate, the anode electrode being in schottky contact with the drift region and in ohmic contact with the first conductive type vertical implantation regions; and a cathode electrode disposed on the rear surface of the semiconductor substrate opposite to the drift region, the cathode electrode being in ohmic contact with the semiconductor substrate.. .

06/23/16
20160181441 

Semiconductor device and manufacturing a semiconductor device


A semiconductor device includes a semiconductor material having a bandgap larger than 2 ev and less than 10 ev, and a contact layer in contact with the semiconductor material. The contact layer includes a metal nitride.

06/23/16
20160181438 

Semiconductor device


A semiconductor device is provided with a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a third oxide semiconductor film in contact with a top surface of the insulating surface, a side surface of the first oxide semiconductor film, and side and top surfaces of the second oxide semiconductor film; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with the gate insulating film and faces the top and side surfaces a of the second oxide semiconductor film. A thickness of the first oxide semiconductor film is larger than a sum of a thickness of the third oxide semiconductor film and a thickness of the gate insulating film, and the difference is larger than or equal to 20 nm..

06/23/16
20160181434 

Semiconductor device and manufacturing semiconductor device


A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. An oxide semiconductor film which can have a first crystal structure by heat treatment and an oxide semiconductor film which can have a second crystal structure by heat treatment are formed so as to be stacked, and then heat treatment is performed; accordingly, crystal growth occurs with the use of an oxide semiconductor film having the second crystal structure as a seed, so that an oxide semiconductor film having the first crystal structure is formed.

06/23/16
20160181433 

Field effect transistor


An insulating film is provided over one surface of a first semiconductor layer including a first oxide semiconductor including indium as a main component, and a second semiconductor layer including an i-type second oxide semiconductor is provided in contact with the other surface. The energy difference between a vacuum level and a fermi level in the second oxide semiconductor is larger than that in the first oxide semiconductor.

06/23/16
20160181432 

Semiconductor device


Reducing hydrogen concentration in a channel formation region of an oxide semiconductor is important in stabilizing threshold voltage of a transistor including an oxide semiconductor and improving reliability. Hence, hydrogen is attracted from the oxide semiconductor and trapped in a region of an insulating film which overlaps with a source region and a drain region of the oxide semiconductor.

06/23/16
20160181431 

Manufacturing crystalline semiconductor film and semiconductor device


A change in electrical characteristics is inhibited in a semiconductor device using a transistor including an oxide semiconductor having crystallinity, and the reliability of the semiconductor device is improved. Further, a semiconductor device with low power consumption is provided.

06/23/16
20160181429 

Finfet with dual workfunction gate structure


A semiconductor device includes a substrate having a fin structure, the fin structure having a height in a substantially perpendicular direction to the substrate, and having consecutive upper and lower portions along the height, the lower portion being closer to the substrate than the upper portion. The semiconductor device further includes a gate structure wrapping around a portion of the fin structure, the gate structure having a gate dielectric layer disposed around the fin structure, and a gate electrode layer disposed over the gate dielectric layer.

06/23/16
20160181428 

Fin field effect transistors having conformal oxide layers and methods of forming same


An embodiment fin field-effect-transistor (finfet) includes a semiconductor fin comprising a channel region and a gate oxide on a sidewall and a top surface of the channel region. The gate oxide includes a thinnest portion having a first thickness and a thickest portion having a second thickness different than the first thickness.

06/23/16
20160181427 

Semiconductor device


A semiconductor device includes an isolation feature in a substrate. The semiconductor device further includes a first source/drain feature in the substrate, wherein a first side of the first source/drain feature contacts the isolation feature, and the first source/drain feature exposes a portion of the isolation feature below a top surface of the substrate.

06/23/16
20160181426 

Methods of forming epi semiconductor material in a trench formed above a semiconductor device and the resulting devices


A device includes a gate structure having an axial length that is positioned above an active region of a semiconductor substrate and includes a first gate structure portion positioned above the active region and second gate structure portions positioned above an isolation region formed in the semiconductor substrate. An etch stop layer is positioned on the gate structure and covers sidewall surfaces of the second gate structure portions but does not cover any sidewall surfaces of the first gate structure portion.

06/23/16
20160181425 

Method for manufacturing semiconductor device


There is provided a method for manufacturing a semiconductor device including a substrate including a plurality of active regions, a plurality of gate electrodes extending in a first direction to intersect a portion of the plurality of active regions, and including first and second gate electrodes disposed to be adjacent to each other in the first direction, a gate isolation portion disposed between the first and second gate electrodes. The gate isolation portion includes a first layer and second layers disposed on both ends of the first layer in a second direction perpendicular to the first direction..

06/23/16
20160181423 

Display panel


A display panel is provided, which includes a first substrate, a first insulating layer on the first substrate, a semiconductor layer on the first insulating layer, and a second insulating layer on the semiconductor layer and the first insulating layer. The second insulating layer has a surface in the vicinity of the first insulating layer.

06/23/16
20160181421 

Semiconductor devices and related fabrication methods


Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a body region of semiconductor material having a first conductivity type, a source region of semiconductor material having a second conductivity type within the body region, a junction isolation region of semiconductor material having the second conductivity type, a drain region of semiconductor material having the second conductivity type, and first and second drift regions of semiconductor material having the second conductivity type.

06/23/16
20160181419 

Semiconductor device


The present examples relate to a semiconductor device used in an electric device or high voltage device. The present examples improve rsp by minimizing drift region resistance by satisfying breakdown voltage by improving the structure of a drift region through which current flows in a semiconductor device to provide optimal results.

06/23/16
20160181418 

Semiconductor device and fabrication method thereof


A semiconductor device includes a well region of a first conductivity type, having a first depth, formed in a substrate. A source contact region of a second conductivity type is formed in the well region.

06/23/16
20160181417 

Transistor device with field-electrode


Disclosed is a transistor device. The transistor device includes a plurality of field structures which define a plurality of semiconductor mesa regions in a semiconductor body, and each of which comprises a field electrode and a field electrode dielectric; a plurality of gate structures in each semiconductor mesa region, wherein each gate structure comprises a gate electrode and a gate dielectric, and is arranged in a trench of the semiconductor mesa region; a plurality of body regions, a plurality of source regions, and a drift region.

06/23/16
20160181416 

Charge-compensation device


A charge-compensation semiconductor device includes a semiconductor body having a first surface, a lateral edge delimiting the semiconductor body in a horizontal direction substantially parallel to the first surface, an active area, a peripheral area arranged between the active area and the lateral edge, a drift region, first compensation regions forming respective first pn-junctions with the drift region, and second compensation regions extending from the first surface into the drift region and forming respective second pn-junctions with the drift region. The first compensation regions form in the active area a lattice comprising a first base vector having a first length.

06/23/16
20160181415 

Wide band gap semiconductor device


A semiconductor substrate having a main surface and made of a wide band gap semiconductor is provided, the semiconductor substrate including a device region formed in the semiconductor substrate, and a peripheral region formed to surround the device region. In the peripheral region, the semiconductor substrate includes a first semiconductor region having a first conductivity type, and a second semiconductor region formed on the first semiconductor region and having the main surface, the second semiconductor region having a second conductivity type different from the first conductivity type.

06/23/16
20160181414 

Semiconductor device including fin- fet and manufacturing method thereof


A semiconductor device includes a first fin structure for a first fin field effect transistor (fet). The first fin structure includes a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer.

06/23/16
20160181413 

Semiconductor device


A semiconductor device is provided with an n−-type drift layer, a n+-type diffusion well region provided on a surface part of the n−-type drift layer, a p-type channel well region, an n+-type diffusion well region, a gate insulating film, a gate electrode laminated on the gate insulating film, a drain trench, a field plate provided in the drain trench with a silicon oxide film and an insulating film interposed therebetween and a field plate electrode formed on the field plate. The field plate is tapered toward a base part of the drain trench.

06/23/16
20160181412 

Semiconductor devices and methods for fabricating the same


Provided are a semiconductor device configured to block a physical diffusion path by forming an oxide layer between barrier layers to prevent impurities from being diffused through the physical diffusion path between the barrier layers, and a method for fabricating the semiconductor device. The semiconductor device includes a gate insulation layer formed on a substrate, a first barrier layer formed on the gate insulation layer, an oxide layer formed on the first barrier layer, the oxide layer including an oxide formed by oxidizing a material included in the first barrier layer, a second barrier layer formed on the oxide layer, a gate electrode formed on the second barrier layer, and source/drains disposed at opposite sides of the gate electrode in the substrate..

06/23/16
20160181411 

Semiconductor device


A drain electrode is partially formed on a side surface of a drain pad. In this case, the drain electrode is integrated with the drain pad and extends from the side surface of the drain pad in a first direction (y direction).

06/23/16
20160181410 

Semiconductor device with low-conducting field-controlling element


A semiconductor device including a low conducting field-controlling element is provided. The device can include a semiconductor including an active region (e.g., a channel), and a set of contacts to the active region.

06/23/16
20160181409 

Bidirectional power switching with bipolar conduction and with two control terminals gated by two merged transistors


Power semiconductor devices, methods, and systems, in which additional switches are added on both surfaces of a two-sided power device with bidirectional conduction. The additional switches are preferably vertical trench mos transistors, and permit the emitter-base junction on either surface to be shunted easily..

06/23/16
20160181408 

Semiconductor device with stripe-shaped trench gate structures and gate connector structure


A semiconductor device includes a transistor cell with a stripe-shaped trench gate structure that extends from a first surface into a semiconductor body. A gate connector structure at a distance to the first surface is electrically connected to a gate electrode in the trench gate structure.

06/23/16
20160181406 

Semiconductor device and manufacturing the same


An object is to provide a semiconductor device including an oxynitride semiconductor whose carrier density is controlled. By introducing controlled nitrogen into an oxide semiconductor layer, a transistor in which an oxynitride semiconductor having desired carrier density and on characteristics is used for a channel can be manufactured.

06/23/16
20160181405 

Method for manufacturing semiconductor device


It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity.

06/23/16
20160181403 

Finfets and methods for forming the same


A finfet includes a semiconductor fin including an inner region, and a germanium-doped layer on a top surface and sidewall surfaces of the inner region. The germanium-doped layer has a higher germanium concentration than the inner region.

06/23/16
20160181402 

Method of manufacturing a semiconductor device with lateral fet cells and field plates


A method of manufacturing a semiconductor device includes providing dielectric stripe structures extending from a first surface into a semiconductor substrate between semiconductor fins. A first mask is provided that covers a first area including first stripe sections of the dielectric stripe structures and first fin sections of the semiconductor fins.

06/23/16
20160181399 

Methods for fabricating semiconductor devices


Methods of forming a semiconductor device are provided. The methods may include forming a gate structure on a substrate, forming a first sacrificial pattern and a second sacrificial pattern on opposing sides of the gate structure respectively and partially replacing the first sacrificial pattern with a first insulating pattern such that a portion of the first sacrificial pattern remains in the first insulating pattern and replacing the second sacrificial pattern with a second insulating pattern.

06/23/16
20160181398 

Composite dummy gate with conformal polysilicon layer for finfet device


A method includes providing a fin structure containing a semiconductor material. The method includes forming a gate dielectric layer over the fin structure, the gate dielectric layer being at least partially wrapped around the fin structure.

06/23/16
20160181397 

Method to improve reliability of high-k metal gate stacks


A method of fabricating a gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over an area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; annealing the replacement gate structure in an ambient atmosphere containing hydrogen; and depositing a gap fill layer.. .

06/23/16
20160181396 

Semiconductor structure and fabrication method thereof


A method for forming a semiconductor structure includes providing a semiconductor substrate having a metal gate structure formed on the semiconductor substrate; forming a first dielectric layer covering a side surface of the metal gate structure on the semiconductor substrate; forming a cap layer on the metal gate structure; etching a top portion of the first dielectric layer using the cap layer as an etching mask; forming a protective sidewall spacer on a side surface of the cap layer and a side surface of a portion of the first dielectric layer under the cap layer; forming a second dielectric layer to cover the cap layer, the protective sidewall spacer and a top surface of the etched first dielectric layer; forming at least a first through-hole in the second dielectric layer; and forming a first conductive via in the first through-hole.. .

06/23/16
20160181392 

Partial spacer for increasing self aligned contact process margins


A semiconductor structure is provided. The semiconductor includes a gate stack on a substrate.

06/23/16
20160181391 

Diode structures with controlled injection efficiency for fast switching


This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface.

06/23/16
20160181390 

Semiconductor devices having low contact resistance and low current leakage


The present disclosure is directed to a device and method for reducing the resistance of the middle of the line in a transistor. The transistor has electrical contacts formed above, and electrically connected to, the gate, drain and source.

06/23/16
20160181388 

Method for manufacturing a semiconductor device comprising a metal nitride layer and semiconductor device


A method of manufacturing a semiconductor device includes introducing nitrogen into a metal layer or into a metal nitride layer, the metal layer or metal nitride layer being formed in contact with a semiconductor material. A semiconductor device includes a semiconductor material and a metal nitride layer in contact with the semiconductor material.

06/23/16
20160181386 

Semiconductor device with an interconnect structure and forming the same


A semiconductor device structure and method for forming the semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate electrode formed on the substrate.

06/23/16
20160181385 

Semiconductor devices having buried contact structures and methods of manufacturing the same


Semiconductor devices are provided including a substrate defining a gate trench. A buried gate structure is provided in the gate trench and at least fills the gate trench.

06/23/16
20160181383 

Semiconductor device and manufacturing method thereof


The present invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, an epitaxial structure, and a recess.

06/23/16
20160181382 

Method for fabricating a transistor with a raised source-drain structure


A method for forming a transistor includes defining agate structure on a top surface of a first semiconductor layer of a silicon-on-insulator (soi) substrate. The gate structure includes an insulating cover.

06/23/16
20160181381 

Trench epitaxial growth for a finfet device having reduced capacitance


A finfet device includes a semiconductor fin, a gate electrode extending over a channel of the fin and sidewall spacers on each side of the gate electrode. A dielectric material is positioned on each side of a bottom portion of said fin, with an oxide material on each side of the fin overlying the dielectric material.

06/23/16
20160181380 

Semiconductor device metal-insulator-semiconductor contacts with interface layers and methods for forming the same


Embodiments provided herein describe systems and methods for forming semiconductor devices. A semiconductor substrate is provided.

06/23/16
20160181379 

Semiconductor device and manufacturing the same


A semiconductor device includes: a semiconductor substrate; a plurality of trench gate electrodes that have a stripe shape in plan view and are located in parallel with each other at an interval; a gate insulating film located on surfaces of the trench gate electrodes; a first impurity layer located in an upper layer portion of the semiconductor substrate; a second impurity layer that is selectively located in a surface of the first impurity layer and is in contact with the gate insulating film; an interlayer insulating film that is located so as to cover upper portions of the trench gate electrodes and an upper portion of the second impurity layer, projects on the semiconductor substrate, and has a stripe shape in plan view; and a planarized buried film of metal that is buried in portions between projecting portions of the interlayer insulating film on the semiconductor substrate.. .

06/23/16
20160181377 

Semiconductor device having dual work function gate structure, fabricating the same, memory cell having the same, and electronic device having the same


A semiconductor device includes a body including a first junction region; a pillar positioned over the body, and including a vertical channel region and a second junction region over the vertical channel region; a gate trench exposing side surfaces of the pillar; a gate dielectric layer covering the gate trench; and a gate electrode embedded in the gate trench, with the gate dielectric layer interposed therebetween. The gate electrode includes a first work function liner overlapping with the vertical channel region, and including an aluminum-containing metal nitride; a second work function liner overlapping with the second junction region, and including a silicon-containing non-metal material; and an air gap positioned between the second work function liner and the second junction region..

06/23/16
20160181376 

Silicon carbide semiconductor device and manufacturing a silicon carbide semiconductor device


An infrared ray absorbing film is selectively formed on a surface of a silicon carbide semiconductor substrate in a predetermined area. An aluminum film and a nickel film are sequentially formed in this order on the silicon carbide semiconductor substrate in an area excluding the predetermined area in which the infrared ray absorbing film is formed.

06/23/16
20160181375 

Silicon carbide semiconductor substrate, manufacturing silicon carbide semiconductor substrate, and manufacturing silicon carbide semiconductor device


A silicon carbide semiconductor substrate includes: a base substrate that has a main surface having an outer diameter of not less than 100 mm and that is made of single-crystal silicon carbide; and an epitaxial layer formed on the main surface. The silicon carbide semiconductor substrate has an amount of warpage of not less than −100 μm and not more than 100 μm when a substrate temperature is a room temperature and has an amount of warpage of not less than −1.5 mm and not more than 1.5 mm when the substrate temperature is 400° c..

06/23/16
20160181374 

Silicon carbide semiconductor device and manufacturing the same


A silicon carbide semiconductor device includes a silicon carbide substrate and a gate electrode. The silicon carbide substrate includes a first source region and a second source region, a first body region, a second body region, a first drift region, a second drift region, a third drift region, and a first connection region.

06/23/16
20160181373 

Silicon carbide semiconductor device and manufacturing the same


A silicon carbide semiconductor device includes a silicon carbide layer and a gate insulating layer. The silicon carbide layer has a main surface.

06/23/16
20160181372 

Silicon carbide semiconductor device and manufacturing same


A silicon carbide layer includes a drift region, a body region and a source region. The drift region constitutes a first main surface and has a first conductivity type.

06/23/16
20160181371 

Semiconductor device and manufacturing the same


The semiconductor device includes: a substrate, an n-type drift region formed on a main surface of the substrate; a p-type well region, an n-type drain region and an n-type source region each formed in the drift region to extend from a second main surface of the drift region opposite to the first main surface of the drift region in contact with the substrate in a direction perpendicular to the second main surface; a gate groove extending from the second main surface in the perpendicular direction and penetrating the source region and the well region in a direction parallel to the first main surface of the substrate; and a gate electrode formed on a surface of the gate groove with a gate insulating film interposed therebetween, wherein the drift region has a higher impurity concentration than the substrate, and the well region extends to the inside of the substrate.. .

06/23/16
20160181368 

Structures and devices including a tensile-stressed silicon arsenic layer and methods of forming same


Structures including a tensile-stressed silicon arsenic layer, devices including the structures, and methods of forming the devices and structures are disclosed. Exemplary tensile-stressed silicon arsenic layer have an arsenic doping level of greater than 5 e+20 arsenic atoms per cubic centimeter.

06/23/16
20160181366 

Field effect transistors including fin structures with different doped regions and semiconductor devices including the same


Field effect transistors are provided. According to the field effect transistor, a source region and a drain region are provided on a substrate and a fin portion is provided to protrude from the substrate.

06/23/16
20160181365 

Semiconductor devices having channel regions with non-uniform edge


A semiconductor device may include a drift region having a first conductivity type, a source region having the first conductivity type, and a well region having a second conductivity type disposed adjacent to the drift region and adjacent to the source region. The well region may include a channel region that has the second conductivity type disposed adjacent to the source region and proximal to a surface of the semiconductor device cell.

06/23/16
20160181362 

Silicide regions in vertical gate all around (vgaa) devices and methods of forming same


An embodiment semiconductor device includes a nanowire extending upwards from a semiconductor substrate, a source/drain region in the nanowire, and a channel region in the nanowire over the source/drain region. The source/drain region further extends into the semiconductor substrate past edges of the nanowire.

06/23/16
20160181361 

Semiconductor devices with cavities


A semiconductor device comprises a first semiconductor wafer including a cavity formed in the first semiconductor die. A second semiconductor die is bonded to the first semiconductor die over the cavity.

06/23/16
20160181360 

Semiconductor structure with etched fin structure and forming the same


A semiconductor structure and a method for forming the same are provided. The method includes forming a first fin structure and a second fin structure over a substrate and forming a first sidewall layer to cover the first fin structure and the second fin structure over the substrate.

06/23/16
20160181359 

Zig-zag trench structure to prevent aspect ratio trapping defect escape


A semiconductor structure including: trench-defining layer; an epitaxial layer; and a set of defect-blocking member(s). The trench-defining layer includes a trench surface which defines an elongated interior space called the “trench.” the epitaxial layer is grown epitaxially in the interior space of the trench.

06/23/16
20160181357 

Semiconductor device


In a semiconductor device, a p+ back gate region (pbg) is arranged in a main surface (si) between first and second portions (p1, p2) of an n+ source region (sr), and arranged on a side closer to an n+ drain region (dr) with respect to the n+ source region (sr). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained..

06/23/16
20160181356 

Semiconductor device


A semiconductor device includes a first conductivity type semiconductor layer that includes a wide bandgap semiconductor and a surface. A trench, including a side wall and a bottom wall, is formed in the semiconductor layer surface, and a schottky electrode is connected to the surface.

06/23/16
20160181355 

Schottky barrier diode and manufacturing the same


A schottky barrier diode provided herein includes: a semiconductor substrate; and an anode electrode being in contact with the semiconductor substrate. The semiconductor substrate includes: p-type contact regions being in contact with the anode electrode; and an n-type drift region being in contact with the anode electrode by schottky contact in a range where the p-type contact regions are not provided the p-type contact regions includes: a plurality of circular regions located so that the circular regions are arranged at intervals between an outer side and an inner side at a contact surface between the semiconductor substrate and the anode electrode; and an internal region located in an inner portion of the circular region located on an innermost side at the contact surface and connected to the circular region located on the innermost side at the contact surface..

06/23/16
20160181354 

Semiconductor device


A semiconductor device in which the concentration of an electric field is suppressed in a region overriding a drain region and a source region. A drain region is formed in a first region, a source region is formed in a second region.

06/23/16
20160181352 

Capacitor structure compatible with nanowire cmos


A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure.

06/23/16
20160181351 

Ultrahigh voltage resistor, semiconductor device, and the manufacturing method thereof


An example provides a semiconductor device including an insulator with a predetermined thickness between a well region of a semiconductor substrate and a resistor of polysilicon. The insulator has a structure that is able to withstand an ultrahigh voltage, and thereby allows the manufacture of a semiconductor device resistor that can bear an ultrahigh voltage without increasing the size of a semiconductor substrate and a semiconductor device including such a resistor.

06/23/16
20160181320 

Electronic device


An electronic device includes a memory device that includes a switching device having an improved switching property and reliability. The semiconductor memory includes a first carbon electrode; a second carbon electrode; a switching layer provided between the first carbon electrode and the second carbon electrode; a third carbon electrode; and a variable resistance layer including nitride and provided between the second carbon electrode and the third carbon electrode..

06/23/16
20160181319 

Resistance change memory


According to one embodiment, a resistance change memory includes a semiconductor layer having a first surface in a first direction and a second surface in a second direction crossing the first direction, extending in a third direction crossing the first and second directions, and having first and second portions, a gate electrode covering the first and second surfaces between the first and second portions, a first conductive line connected to the first portion, a resistance change element having first and second terminals, the first terminal connected to the second portion, a second conductive line connected to the second terminal, and a third conductive line connected to the gate electrode.. .

06/23/16
20160181318 

Electronic device and fabricating the same


An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.. .

06/23/16
20160181317 

Electronic device


This patent document provides an electronic device capable of improving the characteristics of a variable resistance element. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a variable resistance element capable of being included in the semiconductor memory, and including a fixed layer, a tunnel barrier layer, and a variable layer laminated therein, wherein the variable resistance element is capable of allowing a slope of a graph of a switching current density as a function of an external magnetic field to be proportional to the square of “h/hk” when the magnetization directions of the fixed layer and the variable layer are switched from a parallel state to an antiparallel state.

06/23/16
20160181316 

Electronic device and fabricating the same


Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a substrate; a plurality of variable resistance elements formed over the substrate and arranged as a matrix, spacer patterns formed over the substrate to surround the variable resistance elements in the matrix with a thickness sufficient to define contact holes between the variable resistance elements, and a source line contact buried in the contact hole..

06/23/16
20160181315 

Electronic device and fabricating the same


Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a substrate including a first region and a second region separated from the first region; an interlayer dielectric layer formed over the substrate including first and second regions; a first contact plug located over the first region and formed through the interlayer dielectric layer; a second contact plug located over the second region and formed through the interlayer dielectric layer, wherein the first and the second contact plugs having different structures in the first and second regions, respectively; and a variable resistance element formed over the interlayer dielectric layer over the first region so as to be in contact with the first contact plug..

06/23/16
20160181314 

Physical layout and structure of rgbz pixel cell unit for rgbz image sensor


An image sensor is described having a pixel cell unit. The pixel cell unit has first, second and third transfer gate transistor gates on a semiconductor surface respectively coupled between first, second and third visible light photodiode regions and a first capacitance region.

06/23/16
20160181313 

Method of producing semiconductor epitaxial wafer, semiconductor epitaxial wafer, and producing solid-state image sensing device


Provided is a semiconductor epitaxial wafer having metal contamination reduced by achieving higher gettering capability, a method of producing the semiconductor epitaxial wafer, and a method of producing a solid-state image sensing device using the semiconductor epitaxial wafer. The method of producing a semiconductor epitaxial wafer 100 includes a first step of irradiating a semiconductor wafer 10 containing at least one of carbon and nitrogen with cluster ions 16 thereby forming a modifying layer 18 formed from a constituent element of the cluster ions 16 contained as a solid solution, in a surface portion of the semiconductor wafer 10; and a second step of forming a first epitaxial layer 20 on the modifying layer 18 of the semiconductor wafer 10..

06/23/16
20160181312 

Method of producing semiconductor epitaxial wafer, semiconductor epitaxial wafer, and producing solid-state image sensing device


The method of producing a semiconductor epitaxial wafer, according to the present invention includes: a first step of irradiating a semiconductor wafer 10 with cluster ions 16 thereby forming a modifying layer 18 formed from a constituent element of the cluster ions 16 contained as a solid solution, in a surface portion 10a of the semiconductor wafer; a second step of performing heat treatment for crystallinity recovery on the semiconductor wafer 10 after the first step such that the haze level of the semiconductor wafer surface portion 10a is 0.20 ppm or less; and a third step of forming an epitaxial layer 20 on the modifying layer 18 of the semiconductor wafer after the second step.. .

06/23/16
20160181311 

Method of producing semiconductor epitaxial wafer, semiconductor epitaxial wafer, and producing solid-state image sensing device


The method of producing a semiconductor epitaxial wafer includes a first step of irradiating a surface portion 10a of a semiconductor wafer 10 with cluster ions 16 thereby forming a modifying layer 18 formed from carbon and a dopant element contained as a solid solution that are constituent elements of the cluster ions 16, in the surface portion 10a of the semiconductor wafer; and a second step of forming an epitaxial layer 20 on the modifying layer 18 of the semiconductor wafer, the epitaxial layer 20 having a dopant element concentration lower than the peak concentration of the dopant element in the modifying layer 18.. .

06/23/16
20160181306 

Semiconductor bump-bonded x-ray imaging device


A high pixel density intraoral x-ray imaging sensor includes a direct conversion, fully depleted silicon detector bump bonded to a readout cmos substrate by cu-pillar bump bonds.. .

06/23/16
20160181304 

Solid-state imaging device, manufacturing method thereof, and camera with alternatively arranged pixel combinations


A solid-state imaging device includes a semiconductor substrate; and a pixel unit having a plurality of pixels on the semiconductor substrate, wherein the pixel unit includes first pixel groups having two or more pixels and second pixel groups being different from the first pixel groups, wherein a portion of the pixels in the first pixel groups and a portion of the pixels in the second pixel groups share a floating diffusion element.. .

06/23/16
20160181303 

Semiconductor device and semiconductor-device manufacturing method


It is possible to reduce resistance variations of a member connecting a through-silicon via to a line and improve wiring reliability. A hole through which the through-silicon via is to be stretched is created and an over-etching process is carried out on a wiring layer including the line.

06/23/16
20160181302 

Semiconductor photomultiplier


The present disclosure relates to a semiconductor photomultiplier comprising a a substrate; an array of photosensitive elements formed on a first major surface of the substrate; a plurality of primary bus lines interconnecting the photosensitive elements; at least one segmented secondary bus line provided on a second major surface of the substrate which is operably coupled to one or more terminals; and multiple vertical interconnect access (via) extending through the substrate operably coulping the primary bus lines to the at least one segmented secondary bus line.. .

06/23/16
20160181301 

Semiconductor device and a manufacturing method thereof


A semiconductor device has a chip region including a back-side illumination type photoelectric conversion element, a mark-like appearance part, a pad electrode, and a coupling part. The mark-like appearance part includes an insulation film covering the entire side surface of a trench part formed in a semiconductor substrate.

06/23/16
20160181296 

Image sensor pixel for high dynamic range image sensor


An image sensor pixel includes a first photodiode and a second photodiode disposed in a semiconductor material. The first photodiode has a first doped region, a first lightly doped region, and a first highly doped region.

06/23/16
20160181293 

Semiconductor photomultiplier


The present disclosure relates to a semiconductor photomultiplier comprising a substrate; an array of photosensitive cells formed on the substrate that are operably coupled between an anode and a cathode. A set of primary bus lines are provided each being associated with a corresponding set of photosensitive cells.

06/23/16
20160181292 

Thin-film transistor, manufacturing the same, and manufacturing backplane for flat panel display


Provided are a thin-film transistor (tft), a method of manufacturing the same, and a method of manufacturing a backplane for a flat panel display (fpd). The method of manufacturing the tft according to an embodiment of the present invention includes forming a gate electrode on a substrate; forming an insulating layer on the substrate to cover the gate electrode; performing a plasma treatment on an upper surface of the insulating layer using a halogen gas; forming an oxide semiconductor layer on the insulating layer and positioned to correspond to the gate electrode; and forming source and drain electrodes on the insulating layer to contact and over portions of the oxide semiconductor layer..

06/23/16
20160181291 

Semiconductor device, display device, and manufacturing semiconductor device


A semiconductor device (100a) includes a first metal layer (12) including a gate electrode (12g); a gate insulating layer (14) formed on the first metal layer; an oxide semiconductor layer (16) formed on the gate insulating layer; a second metal layer (18) formed on the oxide semiconductor layer; an interlayer insulating layer (22) formed on the second metal layer; and a transparent electrode layer (te) including a transparent conductive layer (tc). The oxide semiconductor layer includes a first portion (16a) and a second portion (16b) extending while crossing an edge of the gate electrode.

06/23/16
20160181288 

Deformable electronic device and methods of providing and using deformable electronic device


Some embodiments include a method of providing an electronic device. The method includes: (i) providing a carrier substrate, (ii) providing a device substrate comprising a first side and a second side opposite the first side, the device substrate having a flexible substrate, (iii) coupling the first side of the device substrate to the carrier substrate; and (iv) after coupling the first side of the device substrate to the carrier substrate, providing two or more active sections over the second side of the device substrate, each active section of the two or more active sections being spatially separate from each other and having at least one semiconductor device.

06/23/16
20160181285 

Uniform junction formation in finfets


The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming an abrupt junction in the channel regions of high density technologies, such as tight pitch finfet devices, using recessed source-drain (s-d) regions and annealing techniques. In an embodiment, a faceted buffer layer, deposited before the s-d region is formed, may be used to control the profile and dopant concentration of the junction under the channel.

06/23/16
20160181284 

Thin film transistor array panel and manufacturing the panel


A thin film transistor array panel includes: a gate line disposed on a substrate and including a first connection member of a gate driver region and a gate electrode of a display area, a gate insulating layer disposed on the substrate and having a first contact hole exposing the first connection member, a semiconductor layer disposed on a region of the gate insulating layer, a data line disposed on the gate insulating layer and the semiconductor layer and including a drain electrode, a source electrode, and a second connection member connected to the first connection member through the first contact hole, a passivation layer disposed on the data line, the source electrode, the drain electrode, and the second connection member, and a pixel electrode disposed on the passivation layer and electrically connected to the drain electrode. A horizontal width of the first contact hole ranges from 1 to 2 μm..

06/23/16
20160181278 

Array substrate, manufacturing the same, and display device


The present disclosure relates to the field of liquid crystal display technology, and provides an array substrate, its manufacturing method and a display device. The array substrate includes data lines, gate lines, and a plurality of pixel units defined by the data lines and the gate lines.

06/23/16
20160181276 

Multi-orientation soi substrates for co-integration of different conductivity type semiconductor devices


A method of forming a semiconductor device that includes providing a base semiconductor substrate having a first orientation crystal plane, and forming an epitaxial oxide layer on the base semiconductor substrate. The epitaxial oxide layer has the first orientation crystal plane.

06/23/16
20160181275 

Nonvolatile memory device and fabricating the same


A nonvolatile memory device includes a substrate comprising a first word line formation area, a second word line formation area, and a support area interposed between the first and second word line formation areas; a first stacked structure disposed over the substrate of each of the first and second word line formation areas and having a plurality of interlayer dielectric layers and a plurality of conductive layers that are alternately stacked therein; a second stacked structure disposed over the substrate of the support area and having the plurality of interlayer dielectric layers and a plurality of spaces that are alternately stacked therein; a channel layer disposed in the first stacked structure; and a memory layer interposed between the channel layer and each of the plurality of conductive layers.. .

06/23/16
20160181274 

Semiconductor memory device


A method of manufacturing a semiconductor device includes forming a laminated structure including sacrificial layers and a select gate layer on a substrate, forming a penetration region penetrating the laminated structure, forming a select gate insulating layer on a sidewall of the select gate layer exposed by the penetration region, and forming an active pattern in the penetration region. The method also includes exposing a portion of the active pattern by removing the sacrificial layers and forming an information storage layer on the exposed portion of the active pattern..

06/23/16
20160181273 

Semiconductor device and manufacturing method thereof


Disclosed are a semiconductor device and a manufacturing method thereof. According to the semiconductor device and the manufacturing method thereof according to exemplary embodiments of the present invention, after the dopant source layer is uniformly deposited on a channel layer of the device with the 3-demensional vertical structure by the plasma-enhanced atomic layer deposition (peald) method, the deposited dopant source layer is heat-treated so that the dopants are diffused into the channel layer to function as charge carriers, thereby preventing the charges in the channel layer from being reduced.

06/23/16
20160181272 

Fabricating 3d nand memory having monolithic crystalline silicon vertical nand channel


Disclosed herein are techniques for fabricating 3d nand memory devices having a mono-crystalline silicon semiconductor vertical nand channel. Memory holes are formed in horizontal layers of material above a substrate.

06/23/16
20160181271 

Methods of fabricating memory device with spaced-apart semiconductor charge storage regions


Methods of fabricating semiconductor devices, such as monolithic three-dimensional nand memory string devices, include selectively forming semiconductor material charge storage regions over first material layers exposed on a sidewall of a front side opening extending through a stack comprising an alternating plurality of first and second material layers using a difference in incubation time for the semiconductor material on the first material relative to an incubation time for the semiconductor material on the second material of the stack. In other embodiments, a silicon layer is selectively deposited on silicon nitride on a surface having at least one first portion including silicon oxide and at least one second portion including silicon nitride using a difference in an incubation time for the silicon on silicon nitride relative to an incubation time for the silicon on silicon oxide..

06/23/16
20160181270 

Memory architecture of array with single gate memory devices


A vertical gate nonvolatile nand array includes a plurality of vertically stacked nand strings of nonvolatile memory cells, a plurality of word lines arranged orthogonally over the plurality of vertically stacked nand strings, and a plurality of vertical columns of conductive gate material electrically coupled to the plurality of word lines. The plurality of vertically stacked nand strings are with vertically stacked semiconductor strips having opposite sides including a first side and a second side.

06/23/16
20160181269 

Three dimensional stacked semiconductor structure and manufacturing the same


A 3d stacked semiconductor structure is provided, comprising a plurality of stacks vertically formed on a substrate and disposed parallel to each other, a dielectric layer formed on the stacks, a plurality of conductive plugs independently formed in the dielectric layer; and a metal-oxide-semiconductor (mos) layer formed on the dielectric layer. One of the stacks at least comprises a plurality of multi-layered pillars, and each of the multi-layered pillars comprises a plurality of insulating layers and a plurality of conductive layers arranged alternately.

06/23/16
20160181268 

Boundary scheme for embedded poly-sion cmos or nvm in hkmg cmos technology


The present disclosure relates to a structure and method for reducing cmp dishing in integrated circuits. In some embodiments, the structure has a semiconductor substrate with an embedded memory region and a periphery region.

06/23/16
20160181267 

Non-volatile memory cell, nand-type non-volatile memory, and manufacturing the same


A non-volatile memory cell, a nand-type non-volatile memory, and a method of manufacturing the same are provided. The method of manufacturing the non-volatile memory cell includes the following steps.

06/23/16
20160181265 

Memory cell having a vertical selection gate formed in an fdsoi substrate


A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate.

06/23/16
20160181261 

Method to prevent oxide damage and residue contamination for memory device


The present disclosure relates a method of forming an integrated circuit. In some embodiments, the method is performed by patterning a first masking layer over a substrate to have a first plurality of openings at a memory cell region and a second plurality of openings at a boundary region.

06/23/16
20160181259 

Vertical ferroelectric memory device and a manufacturing thereof


The disclosed technology generally relates to semiconductor devices, and more particularly to a ferroelectric memory device and a method of manufacturing and using the same. In one aspect, a vertical ferroelectric memory device includes a stack of horizontal layers formed on a semiconductor substrate, where the stack of layers includes a plurality gate electrode layers alternating with a plurality of insulating layers.

06/23/16
20160181258 

Methods of fabricating semiconductor devices


Methods of fabricating semiconductor devices include forming a first impurity region in a substrate by implanting a first impurity of a first conductivity type in a cell region and a peripheral region of the substrate to a first target depth from a top surface of the substrate; forming a second impurity region in the cell region and the peripheral region by implanting a second impurity of the first conductivity type into the cell region and the peripheral region to a second target depth that is smaller than the first depth from the top surface of the substrate; forming a cell transistor with a channel in the cell region, wherein the first impurity region forms the channel of the cell transistor; and forming a peripheral transistor with a channel in the peripheral region, wherein the second impurity region forms the channel of the peripheral transistor.. .

06/23/16
20160181257 

Stacked metal layers with different thicknesses


A semiconductor chip includes a plurality of stacked conductive layers. The plurality of stacked conductive layers includes a first conductive layer, a second conductive layer, and a third conductive layer.

06/23/16
20160181256 

Low-drive current finfet structure for improving circuit density of ratioed logic in sram devices


A method of fabricating an sram semiconductor device includes forming first and second finfets on an upper surface of a bulk substrate. The first finfet includes a first source/drain region containing first dopants, and the second finfet includes a second source/drain region containing second dopants.

06/23/16
20160181255 

Semiconductor integrated circuit device


In an image information chip or the like, a multi-port sram is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port.

06/23/16
20160181254 

Low-drive current finfet structure for improving circuit density of ratioed logic in sram devices


A method of fabricating an sram semiconductor device includes forming first and second finfets on an upper surface of a bulk substrate. The first finfet includes a first source/drain region containing first dopants, and the second finfet includes a second source/drain region containing second dopants.

06/23/16
20160181253 

Semiconductor structures with deep trench capacitor and methods of manufacture


An integrated finfet and deep trench capacitor structure and methods of manufacture are provided. The method includes forming deep trench capacitor structures in a silicon on insulator (soi) wafer.

06/23/16
20160181252 

Deep trench polysilicon fin first


After forming a recessed conductive material portion over a deep trench capacitor located in a lower portion of a deep trench embedded in a substrate, a hard mask layer is formed over a top semiconductor layer of the substrate and the recessed conductive material portion such that the hard mask layer completely fills the deep trench. Next, the hard mask layer, the top semiconductor layer and the recessed conductive material portion are patterned to form a laterally contacting pair of a semiconductor fin and a conductive strap structure over the deep trench capacitor as well as a dielectric cap embedded in the deep trench.

06/23/16
20160181251 

Semiconductor device


A semiconductor device includes a first memory cell including a first transistor and a first capacitor, the first transistor comprising a first gate electrode, a first source, and a first drain; a second memory cell including a second transistor and the first capacitor, the second transistor comprising a second gate electrode, a second source, and a second drain; a first word line coupled to the first gate electrode; and a second word line coupled to the second gate electrode. The first capacitor is electrically connected between the first and second transistors..

06/23/16
20160181250 

Finfet based zram with convex channel region


Embodiments of the present invention provide improved methods and structures for fabrication of capacitor-less dram devices, sometimes referred to as zram devices. A channel is formed in a fin-type field effect transistor (finfet) that is comprised of a finned channel portion and a convex channel portion.

06/23/16
20160181249 

Semiconductor structures with deep trench capacitor and methods of manufacture


An integrated finfet and deep trench capacitor structure and methods of manufacture are provided. The method includes forming a plurality of fin structures from a substrate material.

06/23/16
20160181248 

Cmos transistors including gate spacers of the same thickness


A dielectric material layer is deposited on gate structures of first and second semiconductor material portions. The dielectric material layer is anisotropically etched to form a first gate spacer on a first semiconductor material portion, while being protected above the second semiconductor material portion.

06/23/16
20160181247 

Field-isolated bulk finfet


Disclosed are isolation techniques for bulk finfets. A semiconductor device includes a semiconductor substrate with a fin structure on the semiconductor substrate.

06/23/16
20160181246 

Method of manufacturing semiconductor integrated circuit device


The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset sti insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.. .

06/23/16
20160181245 

Short channel effect suppression


A semiconductor device includes a semiconductor substrate having a first region and a second region. The first region includes a first set of fin structures, the first set of fin structures comprising a first set of epitaxial anti-punch-through features of a first conductivity type.

06/23/16
20160181244 

Short channel effect suppression


A method of fabricating a semiconductor device includes forming a plurality of isolation features on a semiconductor substrate, thereby defining a first set of semiconductor features, performing an etching process on the first set of semiconductor features such that larger semiconductor features are etched deeper than smaller semiconductor features, after the etching process, forming anti-punch-through features on surfaces of the exposed features of the first set of semiconductor features, forming a semiconductor layer over the anti-punch-through features, and forming transistors on the semiconductor layer of each of the features of the first set of semiconductor features. .

06/23/16
20160181243 

Methods of fabricating semiconductor devices including fin-shaped active regions


A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.. .

06/23/16
20160181240 

Semiconductor device and method


In an embodiment, a semiconductor device includes a silicon carbide layer comprising a lateral diode, and a group iii nitride based semiconductor device arranged on the silicon carbide layer.. .

06/23/16
20160181239 

Multi-layered integrated circuit with selective temperature coefficient of resistance


The integrated circuit described herein includes: a first resistor having a first trench in a dielectric layer, the first trench having a first width; a second resistor having a second trench in the dielectric layer, the second trench having a second width not equal to the first width; a trench in a dielectric layer; a first conductive layer having a first tcr and coating at least a portion of the first trench and the second trench; and a second conductive layer having a second tcr and coating at least a portion of the first conductive layer in each of the first trench and the second trench, wherein the second tcr is not equal to the first tcr, and wherein the tcr of the ic is selected based on a dimension of the trench, a thickness of the first conductive layer, and a thickness of the second conductive layer.. .

06/23/16
20160181235 

Integrated circuit having spare circuit cells


Aspects of the disclosure include an integrated circuit that includes a plurality of functional circuit cells and a plurality of inactive spare functional circuit cells. Ones of the functional circuit cells respectively includes a set of first electrically interconnected transistors that define a first logic component and a first power rail configured to carry a first supply voltage.

06/23/16
20160181232 

Semiconductor module and semiconductor device


A semiconductor module includes first and second semiconductor elements connected in series, an insulating substrate, first and second metal patterns formed on a first main surface and a second main surface of the insulating substrate, and first, second, and third electrode plates. A lower surface electrode and an upper surface electrode of the first semiconductor element are bonded to the first metal pattern and the first electrode plate, respectively.

06/23/16
20160181229 

Mounting structure of semiconductor device and manufacturing the same


A semiconductor-device mounting structure includes a first semiconductor device and a plate-shaped second semiconductor device connected to the first semiconductor device. The first semiconductor device includes a flexible board, an electronic component, and a sealing resin.

06/23/16
20160181228 

Semiconductor device and manufacturing same


A semiconductor device includes a first laminated body and a second laminated body. The first laminated body includes sequentially a first element, a first wiring layer, and a first connection layer that includes a first junction electrode, on a main surface of a first substrate.

06/23/16
20160181226 

Stacked semiconductor chip rgbz sensor


An apparatus is described that includes a first semiconductor chip having a first pixel array. The first pixel array has visible light sensitive pixels.

06/23/16
20160181225 

Corrosion-resistant copper bonds to aluminum


A method for fabricating a semiconductor device is disclosed. A packaged semiconductor device is provided having copper ball bonds attached to aluminum pads.

06/23/16
20160181224 

Method of manufacturing semiconductor device


A method of manufacturing a semiconductor device that includes: preparing a pair of substrates that respectively include a device structure on one primary surface or another primary surface thereof; stacking the substrates so that said one primary surfaces face each other, exposing said another surfaces to the outside, and fixing entire peripheral outer edges of the substrates that have been stacked to each other; and thereafter, plating said exposed another primary surfaces of the stacked and fixed substrates.. .

06/23/16
20160181223 

Bump structure having a side recess and semiconductor structure including the same


In some embodiments, the present invention relates to a method of integrated chip bonding. The method forms a conductive trace on a surface of a first work piece, and a conductive bump on a surface of a second work piece.

06/23/16
20160181221 

Semiconductor module


To provide a semiconductor module that has high reliability of electric connection by a solder and is inexpensive. A joint surface of an electrode jointing portion that is opposed to a surface to be jointed of a gate electrode of a bare-chip fet and a joint surface of a substrate jointing portion that is opposed to a surface to be jointed of another wiring pattern include an outgas releasing mechanism that makes outgas generated from a molten solder during solder jointing of a metal plate connector be released from solders interposed between the joint surfaces and the surfaces to be jointed..

06/23/16
20160181219 

Solder joint structure for ball grid array in wafer level package


A semiconductor device package and a method for forming the same using an improved solder joint structure are disclosure. The package includes solder joints having a thinner bottom portion than a top portion.

06/23/16
20160181214 

Stacked memory chip having reduced input-output load, memory module and memory system including the same


A stacked memory chip includes a chip input-output pad unit, a first semiconductor die and a second semiconductor die. The chip input-output pad unit includes a chip command-address pad unit, a lower chip data pad unit and an upper chip data pad unit that are to be connected to an external device.

06/23/16
20160181213 

Wafer structure and wafer dicing


The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls.

06/23/16
20160181211 

Die package with superposer substrate for passive components


A die package is described that includes a substrate to carry passive components. In one example, the package has a semiconductor die having active circuitry near a front side of the die and having a back side opposite the front side, and a component substrate near the back side of the die.

06/23/16
20160181210 

Semiconductor device and manufacturing semiconductor device


An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip, a groove formed in a periphery of a surface of the semiconductor chip being tapered toward a rear surface of the semiconductor chip, wherein the sealing resin layer is partly disposed in the groove.. .

06/23/16
20160181207 

Method of making an electromagnetic interference shield for semiconductor chip packages


An electromagnetic interference shield is described for semiconductor chip packages. In some embodiments, a mold compound is formed over a semiconductor die, the die being over a front side redistribution layer on a side opposite the mold compound, the redistribution layer extending past the die and the mold compound extending around the die to contact the redistribution layer.

06/23/16
20160181206 

Semiconductor package having a metal paint layer


Disclosed are devices and methods related to a conductive paint layer configured to provide radio-frequency (rf) shielding for a packaged semiconductor module. Such a module can include a packaging substrate, one or more rf components mounted on the packaging substrate, a ground plane disposed within the packaging substrate, and a plurality of rf-shielding wirebonds disposed on the packaging substrate and electrically connected to the ground plane.

06/23/16
20160181205 

Discrete component backward traceability and semiconductor device forward traceability


A system is disclosed for providing backward and forward traceability by a methodology which identifies discrete components (die, substrate and/or passives) that are included in a semiconductor device. The present technology further includes a system for generating a unique identifier and marking a semiconductor device with the unique identifier enabling the semiconductor device, and the discrete components within that device, to be tracked and traced through each process and test in the production of the semiconductor device..

06/23/16
20160181204 

Electronic device and fabricating the same


This patent document provides an electronic device including a semiconductor memory that can simplify a fabrication process and improve characteristics of a variable resistance element, and a method for fabricating the same. In one aspect, an electronic device including a semiconductor memory is provided, wherein the semiconductor memory includes: a substrate; a variable resistance element formed over the substrate and exhibiting different resistance states to store data; an interlayer insulating layer formed over the substrate to surround at least a portion of the variable resistance element; an upper electrode contact formed over the variable resistance element to penetrate a portion of the interlayer insulating layer and be in contact with the variable resistance element; and a metal wiring formed over the interlayer insulating layer, and configured to include a stacked structure of a tungsten layer and a barrier layer, wherein the barrier layer is in contact with the upper electrode contact and includes tungsten, boron and iridium..

06/23/16
20160181201 

Semiconductor package assembly with through silicon via interconnect


The invention provides a semiconductor package assembly with a tsv interconnect. The semiconductor package assembly includes a first semiconductor die mounted on a base.

06/23/16
20160181199 

Semiconductor device


According to one embodiment, an integrated circuit is formed on a semiconductor chip, a regulator supplies power to the integrated circuit via the power-supply wire, a first resistor is connected between the first pad electrode and the power-supply wire on the semiconductor chip, and a second resistor is connected between the second pad electrode and the power-supply wire on the semiconductor chip and has a resistance smaller than that of the first resistor.. .

06/23/16
20160181198 

Semiconductor devices having expanded recess for bit line contact


A semiconductor device includes a first device isolation region and a second device isolation region defining a first active region, a second active region, and a third active region in a substrate, a recess region exposing an upper surface of the first active region and upper surfaces of the first and second device isolation regions, and active buffer patterns on the second and third active regions. The first active region is located between the second and third active regions, the first device isolation region is located between the first and second active regions, the second device isolation region is located between the first and third active regions.

06/23/16
20160181197 

Reliable passivation layers for semiconductor devices


Device and method for forming a device are disclosed. A substrate which is prepared with a dielectric layer having a top metal level of the device is provided.

06/23/16
20160181196 

Preservation of fine pitch redistribution lines


An embodiment includes a semiconductor apparatus comprising: a redistribution layer (rdl) including a patterned rdl line having two rdl sidewalls, the rdl comprising a material selected from the group comprising cu and au; protective sidewalls directly contacting the two rdl sidewalls; a seed layer including the material; and a barrier layer; wherein (a) the rdl line has a rdl line width orthogonal to and extending between the two rdl sidewalls, and (b) the seed and barrier layers each include a width parallel to and wider than the rdl line width. Other embodiments are described herein..

06/23/16
20160181195 

Substrate strip and manufacturing semiconductor package using the same


A substrate includes a substrate body including a plurality of chip mounting regions and a peripheral region surrounding the plurality of chip mounting regions, each of the chip mounting regions including a conductive plane. The substrate further includes a conductive support structure located in the peripheral region, first conductive lines connected between the conductive planes of adjacent chip mounting regions, and second conductive lines connected between the conductive support structure and the conductive planes of chip mounting regions located adjacent the peripheral region..

06/23/16
20160181194 

Semiconductor device


The present invention is to provide a semiconductor device in which the generation of the eddy current in a metal flat plate is reduced, and the q value of the rf circuit of the semiconductor device is improved even using the metal flat plate as a support.. .

06/23/16
20160181191 

Substrate core via structure


By now it should be appreciated that there has been provided methods for making a packaged semiconductor device (and the resultant device) including a via layer that includes a top surface and a bottom surface; a plurality of vias within the via layer, wherein the plurality of vias extend from the bottom surface to the top surface; a first via of the plurality of vias extending from the bottom surface to the top surface at a first angle; and a second via of the plurality of vias extending from the bottom surface to the top surface at a second angle.. .

06/23/16
20160181190 

Semiconductor device and making the same


A semiconductor device includes a first electronic component mounted to an upper face of a plated interconnect layer, a second electronic component mounted to a lower face of the plated interconnect layer, a first resin part covering the first electronic component on an upper side of the plated interconnect layer, and a second resin part covering the second electronic component on a lower side of the plated interconnect layer, wherein the first and second electronic components at least partially face each other across the plated interconnect layer, wherein the plated interconnect layer includes a sloping portion disposed on a sloping boundary between the first and second resin parts, and wherein an end part of the sloping portion is bent to have a face thereof exposed from the second resin part, and a lower surface of the second resin part is flush with the face of the end part.. .

06/23/16
20160181187 

Semiconductor device and lead frame


A semiconductor device includes a lead frame having terminals, a semiconductor chip electrically coupled to the terminals, and a resin part configured to encapsulate the semiconductor chip such as to expose part of the terminals, wherein a given one of the terminals includes a first lead and a second lead welded together such that an upper face of the first lead is placed against a lower face of the second lead, wherein the lower face of the second lead extends further than the upper face of the first lead toward the semiconductor chip in a longitudinal direction of the terminal, and also extends further sideways than the upper face of the first lead in a transverse direction of the terminal, and wherein an area of the lower face of the second lead is covered with the resin part, the area extending further than the upper face of the first lead.. .

06/23/16
20160181186 

Semiconductor device and production method therefor


A semiconductor device includes a semiconductor chip, a lead arranged on a side portion of the semiconductor chip, and a wire, whose one end and another end are bonded to the semiconductor chip and the lead respectively, having a ball portion and a stitch portion wedged in side elevational view on the semiconductor chip and the lead respectively. An angle of approach of the wire to the lead is not less than 50°, and the length of the stitch portion is not less than 33 μm..

06/23/16
20160181185 

Semiconductor package structure


A semiconductor package structure includes a lead frame, a chip and a molding compound. The lead frame includes a tray pad and a plurality of leads.

06/23/16
20160181184 

Semiconductor device and its manufacturing method


The present invention makes it possible to improve the reliability of a semiconductor device. The semiconductor device has, over a semiconductor substrate, a pad electrode formed at the uppermost layer of a plurality of wiring layers, a surface protective film having an opening over the pad electrode, a redistribution line being formed over the surface protective film and having an upper surface and a side surface, a sidewall barrier film comprising an insulating film covering the side surface and exposing the upper surface of the redistribution line, and a cap metallic film covering the upper surface of the redistribution line.

06/23/16
20160181183 

Method for preventing die pad delamination


The invention is directed to a method for inhibiting or preventing delamination at the interface of the die attach/mold compound and the die pad of a semiconductor device and a semiconductor device formed by such method. The method includes providing a leadframe having a top surface; coating said top surface of said leadframe with first and second silane coating; heating said silane coatings to form a pourous layer having a porosity of at least 10%; applying a die to said pourous layer; securing said die to said pourous layer by a die attaching compound; and after the curing of die attach material and wire bonding, a mold compound is applied through molding..

06/23/16
20160181182 

Electronic device and methods of providing and using electronic device


Some embodiments include a method of providing an electronic device. The method can comprise: providing a first device substrate; providing one or more first active sections over a second side of the first device substrate at a first device portion of the first device substrate; and after providing the first active section(s) over the second side of the first device substrate at the first device portion, folding a first perimeter portion of the first device substrate toward the first device portion at a first side of the first device substrate so that a first edge portion remains to at least partially frame the first device portion.

06/23/16
20160181181 

Package structure and manufacturing same


A method for manufacturing a package structure carries out in following way. A flexible circuit board is provided.

06/23/16
20160181180 

Packaged semiconductor device having attached chips overhanging the assembly pad


A semiconductor device (200) comprising a semiconductor chip (201) has an electrically active side (201a) and an opposite electrically inactive side (201b); the active side bordered by an edge having a first length (202a), and the inactive side bordered by a parallel edge having a second length (202b) smaller than the first length; a substrate has an assembly pad (210) bordered by a linear edge having a third length (210a) equal to or smaller than the first length; the inactive chip side attached to the pad so that the edge of the first length is parallel to the edge of the third length; the active side of the attached chip forms an overhang over the pad, when the third length is smaller than the first length.. .

06/23/16
20160181176 

Semiconductor package


The present disclosure relates to a semiconductor package. In an embodiment, the semiconductor package includes a substrate, a semiconductor device, a thermal conductive element and a molding compound.

06/23/16
20160181174 

Integrated circuit cooling apparatus


A chip fabricated from a semiconductor material is disclosed, which may include active devices located below a first depth from the chip back side, and a structure to remove heat from the active devices to the chip back side. The structure may include thermally conductive partial vias (tcpvs), which may include a recess with a depth, from the chip back side towards the active devices less than the first depth.

06/23/16
20160181172 

Compositions and methods for semiconductor processing and devices formed therefrom


The present invention relates generally to the field of semiconductor devices, including solar cells, and compositions and methods for processing semiconductor devices, passivation of semiconductor surfaces, semiconductor etching and anti-reflective coatings for semiconductor devices.. .

06/23/16
20160181164 

Fin formation on an insulating layer


An approach to forming fins for a semiconductor device on a silicon-on-insulator wafer. The approach includes depositing a layer of mandrel material and etching the layer of mandrel material to form a mandrel.

06/23/16
20160181163 

Method and structure for metal gates


A semiconductor device having metal gates and methods of forming the same are disclosed. The method includes receiving a substrate, a dummy gate stack formed over the substrate, and a structure surrounding the dummy gate stack.

06/23/16
20160181162 

Gate-all-around fin device


A gate-all around fin double diffused metal oxide semiconductor (dmos) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate.

06/23/16
20160181161 

Sub-fin device isolation


A fin-based structure may include fins on a surface of a semiconductor substrate. Each of the fins may include a doped portion proximate to the surface of the semiconductor substrate.

06/23/16
20160181160 

Method for manufacturing silicon carbide semiconductor device


When a gate insulating film is formed on a silicon carbide substrate, the silicon carbide substrate is first oxidized with an oxidation reactant gas to form the gate insulating film on the surface of the silicon carbide substrate. The silicon carbide substrate on which the gate insulating film has been formed is nitrided with a nitriding reactant gas.

06/23/16
20160181159 

Method for fabricating semiconductor device


A method for fabricating a semiconductor device, including forming gate patterns over a substrate, forming conductive layer covering top and sidewalls of each gate pattern, forming a metal layer for a silicidation process over the conductive layer, and silicifying the conductive layer and the gate patterns using the metal layer.. .

06/23/16
20160181158 

Method and structure for a large-grain high-k dielectric


A method of forming a semiconductor device (100) includes depositing a metal oxide (104) over the substrate (102). The depositing includes combining a first metal and oxygen to form the metal oxide having grains and further adding a catalyst during the combining.

06/23/16
20160181154 

Semiconductor device with multi-layer metallization


One or more embodiments are related to a semiconductor device, comprising: a metallization layer comprising a plurality of portions, each of the portions having a different thickness. The metallization layer may be a final metal layer..

06/23/16
20160181152 

Semiconductor device metallization systems and methods


Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe.

06/23/16
20160181150 

Precursors of manganese and manganese-based compounds for copper diffusion barrier layers and methods of use


Semiconductor devices and methods of making semiconductor devices with a barrier layer comprising manganese nitride are described. Also described are semiconductor devices and methods of making same with a barrier layer comprising mn(n) and, optionally, an adhesion layer..

06/23/16
20160181149 

Semiconductor structure and fabrication method thereof


A method for forming a semiconductor structure is provided. The method includes providing a substrate; and forming an ultra-low-dielectric-constant (ulk) dielectric layer on a surface of the substrate.

06/23/16
20160181148 

Semiconductor device and manufacturing the same


In one embodiment, a semiconductor device includes a substrate, first and second interconnects provided on the substrate to be apart from each other, and third and fourth interconnects provided on the substrate to be apart from each other. The device further includes a first pad portion connected with the first or third interconnect, and a second pad portion connected with the second or fourth interconnect, and provided to be apart from the first pad portion.

06/23/16
20160181147 

Semiconductor device and manufacturing the same


A first misfet which is a semiconductor element is formed on an soi substrate. The soi substrate includes a supporting substrate which is a base, box layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an soi layer which is a semiconductor layer formed on the box layer.

06/23/16
20160181143 

Semiconductor device with air gap and fabricating the same


A method for fabricating a semiconductor device includes preparing a substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the substrate in the memory cell region; forming a planar gate structure over the substrate in the peripheral circuit region; forming a bit line structure over the substrate in the memory cell region; forming a first air spacers over a sidewalls of the planar gate structure; and forming a second air spacers over a sidewalls of the bit line structure.. .

06/23/16
20160181140 

Protective tape and manufacturing a semiconductor device using the same


A protective tape and a method for manufacturing a semiconductor device using the same capable of achieving excellent connection properties. The protective tape includes an adhesive layer, a thermoplastic resin layer and a backing material film in that order; a modulus ratio of a shear storage modulus of the adhesive layer to a shear storage modulus of the thermoplastic resin layer at an application temperature at which the protective tape is applied is 0.01 or less.

06/23/16
20160181138 

Method of manufacturing a semiconductor component and semiconductor component


Various embodiments provide method of manufacturing a semiconductor component, wherein the method comprises providing a layer stack comprising a carrier and a thinned wafer comprising a metallization layer on one side, wherein the thinned wafer is placed on a first side of the carrier; forming an encapsulation encapsulating the layer stack at least partially; and subsequently thinning the carrier from a second side of the carrier, wherein the second side is opposite to the first side of the carrier.. .

06/23/16
20160181130 

Internal plasma grid for semiconductor fabrication


The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers.

06/23/16
20160181128 

High-throughput semiconductor-processing apparatus equipped with multiple dual-chamber modules


A wafer-processing apparatus includes: multiple discrete units of reactors disposed on the same plane; a wafer-handling chamber having a polygonal shape having multiple sides corresponding to and being attached to the multiple discrete units, respectively, and one additional side for a load lock chamber; a load lock chamber attached to the one additional side of the wafer-handling chamber; multiple discrete gas boxes for controlling gases corresponding to and being connected to the multiple discrete units, respectively; and multiple discrete electric boxes for controlling electric systems corresponding to and being detachably connected to the multiple discrete units, respectively, wherein the gas boxes and the electric boxes are arranged alternately as viewed from above under the multiple discrete units, and the electric boxes can be pulled out outwardly without being disconnected from the corresponding units so that sides of the gas boxes are accessible.. .

06/23/16
20160181126 

Method for manufacturing multi-chip package


A multi-chip package structure is provided, including a substrate having a grounding structure; two semiconductor elements disposed on and electrically connected to the substrate; an encapsulant formed on the substrate and encapsulating semiconductor elements, wherein the encapsulant has a plurality of round holes formed between the semiconductor elements; and an electromagnetic shielding structure formed in each of the round holes and connected to the grounding structure to achieve electromagnetic shielding effects. A method for forming the multi-chip package is also provided..

06/23/16
20160181125 

Stacked semiconductor die assemblies with thermal spacers and associated systems and methods


Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a thermally conductive casing defining a cavity, a stack of first semiconductor dies within the cavity, and a second semiconductor die stacked relative to the stack of first dies and carried by a package substrate.

06/23/16
20160181124 

3d packages and methods for forming the same


Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure.

06/23/16
20160181118 

Plasma processing method


A plasma processing method capable of controlling an etching rate of a sin film and obtaining high selectivity to a sio2 film and si at the same time performs etch-back of a sin film as a processing object of a film structure including a sio2 film and the sin film or a si film and the sin film on a surface of a substrate placed in a processing chamber by using inductively couple plasma formed in the processing chamber by supplying process gas including chf3 or cf4 and o2 gas into the processing chamber inside a vacuum vessel and supplying rf power of 7-50 mhz to an induction coil surrounding an outer circumference of the processing chamber.. .

06/23/16
20160181117 

Integrated etch/clean for dielectric etch applications


The embodiments herein relate to methods and apparatus for etching a recessed feature in dielectric material. In various embodiments, a recessed feature is formed in two etching operations.

06/23/16
20160181109 

Semiconductor device manufacturing method


A semiconductor device manufacturing method includes forming a dielectric film on a semiconductor substrate; forming a resist pattern on the dielectric film; irradiating an ionized gas cluster to a region of the dielectric film where the resist pattern is not formed; and removing a part of the region of the dielectric film in a thickness direction thereof where the ionized gas cluster is irradiated by a wet etching. The dielectric film serves as a gate insulating film, and two regions having different thicknesses of the dielectric film are formed..

06/23/16
20160181108 

Doping of high-k dielectric oxide by wet chemical treatment


A method for fabricating a semiconductor device includes forming a first high-k (hk) dielectric layer over a substrate, performing a wet treatment process to the first hk dielectric layer. The wet treatment includes a dopant.

06/23/16
20160181106 

Phase change memory with diodes embedded in substrate


An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type..

06/23/16
20160181104 

Method for forming a semiconductor device and a semiconductor substrate


A method for forming a semiconductor device includes incorporating chalcogen dopant atoms into a semiconductor doping region of a semiconductor substrate of a semiconductor device. The method further includes incorporating heavy metal atoms into the semiconductor doping region..

06/23/16
20160181103 

Semiconductor device including small pitch patterns


A method is provided for fabricating small pitch patterns. The method includes providing a semiconductor substrate, and forming a target material layer having a first region and a second region on the semiconductor substrate.

06/23/16
20160181101 

Semiconductor device and manufacturing the same


A semiconductor device includes a plurality of line patterns including at least two continuous line repetition units having, as one of the line repetition unit, four line patterns continuously arranged in a first direction and having variable widths based on location. To form the plurality of line patterns including the at least two continuous line repetition units, a plurality of reference patterns are formed repeatedly at a uniform reference pitch on a feature layer.

06/23/16
20160181098 

Oxide semiconductor layer and production method therefor, oxide semiconductor precursor, oxide semiconductor layer, semiconductor element, and electronic device


The invention provides an oxide semiconductor layer that has less cracks and is excellent in electrical property and stability, as well as a semiconductor element and an electronic device each including the oxide semiconductor layer. The invention provides an exemplary method of producing an oxide semiconductor layer, and the method includes the precursor layer forming step of forming, on or above a substrate, a layered oxide semiconductor precursor including a compound of metal to be oxidized into an oxide semiconductor dispersed in a solution including a binder made of aliphatic polycarbonate, and the annealing step of heating the precursor layer at a first temperature achieving decomposition of 90 wt % or more of the binder, and then annealing the precursor layer at a temperature equal to or higher than a second temperature (denoted by x) that is higher than the first temperature, achieves bonding between the metal and oxygen, and has an exothermic peak value in differential thermal analysis (dta)..

06/23/16
20160181092 

Nitride spacer for protecting a fin-shaped field effect transistor (finfet) device


Approaches for protecting a semiconductor device (e.g., a fin field effect transistor device (finfet)) using a nitride spacer are provided. Specifically, a nitride spacer is formed over an oxide and a set of fins of the finfet device to mitigate damage during subsequent processing.

06/23/16
20160181087 

Particle removal with minimal etching of silicon-germanium


Particle-clean formulations and methods for semiconductor substrates use aqueous solutions of tetraethylammonium hydroxide (“teah,” c8h21no) with or without hydrogen peroxide (h2o2). The solution ph ranges from 8-12.5.

06/23/16
20160181018 

Multilayer film capacitor


A multilayer film capacitor having a composite stack disposed between two electrodes where the composite stack includes at least one thermoplastic conductive layer and at least one thermoplastic insulating layer. The total thickness of the conductive layers is at least 3 times the total thickness of the insulating layers.





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