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Duc patents



      
           
This page is updated frequently with new Duc-related patent applications. Subscribe to the Duc RSS feed to automatically get the update: related Duc RSS feeds. RSS updates for this page: Duc RSS RSS


Vertical conductive connections in semiconductor substrates

StmicroelectronicsS.r.l.

Vertical conductive connections in semiconductor substrates

Method for fabricating finfet on germanium or group iii-v semiconductor substrate

Peking University

Method for fabricating finfet on germanium or group iii-v semiconductor substrate

Method for fabricating finfet on germanium or group iii-v semiconductor substrate

Honeywell International

Ambient condition detector with processing of incoming audible commands followed by speech recognition

Date/App# patent app List of recent Duc-related patents
05/21/15
20150143324
 Semiconductor device design methods and conductive bump pattern enhancement methods patent thumbnailnew patent Semiconductor device design methods and conductive bump pattern enhancement methods
Semiconductor device design methods and conductive bump pattern enhancement methods are disclosed. In some embodiments, a method of designing a semiconductor device includes designing a conductive bump pattern design, and implementing a conductive bump pattern enhancement algorithm on the conductive bump pattern design to create an enhanced conductive bump pattern design.
Taiwan Semiconductor Manufacturing Company, Ltd.
05/21/15
20150143321
 Methods for cell phasing and placement in dynamic array architecture and implementation of the same patent thumbnailnew patent Methods for cell phasing and placement in dynamic array architecture and implementation of the same
A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates.
Tela Innovations, Inc.
05/21/15
20150143312
 Method of designing patterns of semiconductor devices patent thumbnailnew patent Method of designing patterns of semiconductor devices
A method of designing patterns of semiconductor devices includes forming a plurality of tiles having patterns on a wafer, measuring the patterns of the plurality of tiles, analyzing the measurements of the patterns and determining a tile having such a size that the measurements linearly vary according to a design size and pattern density, and modifying the pattern density of the determined tile.. .
Samsung Electronics Co., Ltd.
05/21/15
20150143311
 Method, system and computer program product for designing semiconductor device patent thumbnailnew patent Method, system and computer program product for designing semiconductor device
A method of designing a semiconductor device is performed by at least one processor. In the method, a first environment temperature for a first substrate is determined based on an operational temperature of a second substrate, the first and second substrates stacked one upon another in the semiconductor device.
Taiwan Semiconductor Manufacturing Company, Ltd.
05/21/15
20150143307
 Sequential clock gating using net activity and xor technique on semiconductor designs including already gated pipeline design patent thumbnailnew patent Sequential clock gating using net activity and xor technique on semiconductor designs including already gated pipeline design
The circuit design process requires ways to reduce the power consumption of large integrated circuits and system-on-chip designs. This is typically done by introducing a process of clock gating thereby enabling or disabling flip-flops associated with specific functional blocks within the circuit.
Atrenta, Inc.
05/21/15
20150143203
 Semiconductor device and  operating the same patent thumbnailnew patent Semiconductor device and operating the same
A semiconductor device includes a memory device suitable for outputting health monitoring data including information on a threshold voltage distribution, and outputting read data read from memory cells included in the memory device, and a controller suitable for receiving a predetermined quantity of the read data from the memory device based on the health monitoring data, and performing a decoding operation for an error correction by using the received read data.. .
Sk Hynix Inc.
05/21/15
20150143165
 Memory systems and methods of managing failed memory cells of semiconductor memories patent thumbnailnew patent Memory systems and methods of managing failed memory cells of semiconductor memories
A memory system includes a memory controller configured to replace a memory block including a failed memory cell with a unit cache block of a cache memory in response to detection of the failed memory cell in the memory block. The unit cache block is smaller than a minimum size of a memory cell array capable of being blocked by an operating system, and the unit cache block has substantially the same storage capacity as the memory block..
Samsung Electronics Co., Ltd.
05/21/15
20150143131
 Information processing device, information storage device, information processing system, information processing method, and program patent thumbnailnew patent Information processing device, information storage device, information processing system, information processing method, and program
According to a first aspect of the present disclosure, there is provided an information storage device including a storage unit that stores encrypted content, usage control information of the encrypted content, and a revocation list in which revocation information of a content reproduction device is recorded, and a data processing unit that determines whether content reproduction of an information processing device which performs decoding of the encrypted content is permitted. The data processing unit acquires an entry identifier which is designation information for a registration entry of the revocation list recorded in the usage control information, executes an identifier registration determination process for determining whether an identifier of the information processing device which performs decoding of the encrypted content is registered in the entry of the revocation list identified according to the acquired entry identifier, and determines whether a subkey which is a generation key for a title key applied to the decoding of the encrypted content is to be provided to the information processing device based on a result of the identifier registration determination process..
Sony Corporation
05/21/15
20150142924
 Method for providing contents and electronic device using the same patent thumbnailnew patent Method for providing contents and electronic device using the same
Disclosed is a method of providing a content of an electronic device. The method includes, when an audio streaming service is requested to a server, transmitting user information of an electronic device.
Samsung Electronics Co., Ltd.
05/21/15
20150142883
 Information processing apparatus, synchronization correction method and computer program patent thumbnailnew patent Information processing apparatus, synchronization correction method and computer program
An information processing apparatus is provided which includes a transmission unit for transmitting a query request for querying another device for a count value held by such other device, a reception unit for receiving a return of the count value from such other device, a correction unit for performing, at a predetermined period, correction processing for synchronizing sampling frequency with such other device based on the received count value, and a reproduction unit for reproducing content in synchronization with such other device based on the sampling frequency. The correction unit corrects by taking into account a round trip time between the transmission of the query request and the reception of the return and residual difference occurred at a previous correction time..
Sony Corporation
05/21/15
20150142833
new patent

System and obtaining metadata about content stored in a repository


At least one of the embodiments described herein relate generally to a method of obtaining metadata for content stored in a first repository. The method may be performed at a second repository, and may include the acts of identifying a content object stored in the first repository, the content object comprising learning content usable in an electronic educational system to provide electronic learning; identifying metadata for the content object stored in the first repository, the metadata associated with the learning content of the content object; retrieving the metadata associated with the learning content from the first repository; and storing a harvested content object corresponding to the content object, wherein the harvested content object includes the metadata associated with the learning content of the content object stored in the first repository..
Desire2learn Incorporated
05/21/15
20150142687
new patent

Student account data system


A student account data system is provided. The system includes one or more processors and a machine-readable mediums storing a set of instructions that, when executed by the processor cause it to execute operations including gathering student data from at least a first program, create a student profile from the student data, and award at least one achievement based on the student data.
V.p. Skyview, L.l.c.
05/21/15
20150142675
new patent

Electronic process validation


A system for electronic transaction processing, comprising a plurality of electronic documents, each having a plurality of elements, each element having one or more representation data field, one or more definition data field and one or more record data field, a consumer closing table providing access to a subset of the electronic documents and allowing a borrower that has been associated with the subset of the electronic documents to edit predetermined data fields and to view predetermined educational materials associated with one or more of the elements and a closing disclosure collaboration system configured to provide access to a closing disclosure document and to allow a settlement agent to edit predetermined data fields and to allow a lender to edit predetermined data fields.. .
Guardian Consumer Services, Inc.
05/21/15
20150142619
new patent

On-line product catalogue and ordering system, and the presentation of multimedia content


A method of presenting an on-line product catalogue and ordering system to a user, said method comprising providing a graphical user interface representing a virtual space through which users may navigate, said virtual space including representations representing products, through which a user may obtain product information and order a product on-line, and representations representing other users of the system, through which the user may identify such other users and communicate with a selected other user regarding the products on offer.. .
Outersonic Limited
05/21/15
20150142432
new patent

Ambient condition detector with processing of incoming audible commands followed by speech recognition


A monitoring system includes at least one detector having a housing which carries at least one ambient condition sensor. Control circuits carried by the housing are coupled to the sensor.
Honeywell International Inc.
05/21/15
20150142342
new patent

Method and device for sensing isotropic stress and providing a compensation for the piezo-hall effect


A method determines isotropic stress by means of a hall element which includes a plate-shaped area made of a doped semiconductor material and comprises four contacts contacting the plate-shaped area and forming corners of a quadrangle, two neighboring corners of the quadrangle defining an edge thereof. At least one van der pauw transresistance value in at least one van der pauw measurement set-up of the hall element is determined, wherein the four contacts of the hall element form contact pairs, a contact pair comprising two contacts defining neighbouring corners of the quadrangle.
Melexis Technologies Nv
05/21/15
20150142254
new patent

System and detecting and isolating faults in pressure sensing of flush air data system (fads)


A system and method for detecting and isolating faults in pressure ports (2) and pressure transducers (3) of a pressure sensing system are disclosed. The system comprises a set of pressure ports (2) flushed to a nose cap (1) of a space vehicle in crucifix form.
Indian Space Research Organisation
05/21/15
20150142162
new patent

Multi-protocol multi-client equipment server


A multi-client multi-protocol equipment server includes: a host interface that facilitates communication with a manufacturing execution system (mes); a plurality of client interfaces, wherein each client interface facilitates communication with a client based on a common equipment model (cem) for a semiconductor manufacturing tool; and a plurality of tool interfaces, wherein each tool interface facilitates communication with a semiconductor manufacturing tool, wherein at least one of the interfaces is a semi equipment communications standard/generic model for communications and control of manufacturing equipment (secs/gem) interface that is configured in a single xml file that defines attributes of the cem for the semiconductor manufacturing tool which uses the secs/gem interface, and wherein a computer executes the multi-client multi-protocol server.. .
Peer Intellectual Property Inc.
05/21/15
20150142148
new patent

Interactive sound reproducing


An audio system attachable to a computer includes a sound reproduction device for producing audible sound from audio signals. The sound reproduction device includes a radio tuner and a powered speaker.
Bose Corporation
05/21/15
20150142033
new patent

Ultrasonic surgical instrument with features for forming bubbles to enhance cavitation


An ultrasonic element comprises an ultrasonic transducer and a head or blade. The ultrasonic transducer is operable to convert electrical power into ultrasonic vibrations.
Ethicon Endo-surgery, Inc.
05/21/15
20150141876
new patent

Method for providing directional therapy to skeletal joints


An ultrasound therapy system and method is provided that provides directional, focused ultrasound to localized regions of tissue within body joints, such as spinal joints. An ultrasound emitter or transducer is delivered to a location within the body associated with the joint and heats the target region of tissue associated with the joint from the location.
The Regents Of The University Of California
05/21/15
20150141833
new patent

Catheter device implementing high frequency, contrast imaging ultrasound transducer, and associated method


An imaging catheter system is provided, including a hollow lumen having a distal portion, and a plurality of first transducer elements arranged in a first array configured to be received within the distal portion of the hollow lumen. Each of the first transducer elements include a micromachined piezocomposite, and the plurality of first transducer elements is configured to operate at an effective operational frequency of greater than about 30 mhz.
North Carolina State University
05/21/15
20150141825
new patent

Ultrasonic device and manufacturing method thereof, electronic equipment, and ultrasonic image device


An ultrasonic device includes a substrate, an acoustic adjustment layer, an acoustic lens and a structural member. The substrate has an element array including a plurality of thin film ultrasonic transducer elements arranged in an array form.
Seiko Epson Corporation
05/21/15
20150141803
new patent

Method and adjustable earpieces in an mri system


Apparatus and method for imaging a patient in an mri system. This includes a frame, and at least one assembly that includes an earpiece positioner connected to a reference position on the frame, a first lockable joint on the positioner; and an earpiece connected to a patient-proximal end of the positioner by a second joint, wherein the first earpiece is moveably positioned to a selected pitch angle, a selected yaw angle, and a selected one of a plurality of distances relative to the reference position on the frame.
Life Services Llc
05/21/15
20150141795
new patent

Breast scanning apparatus using photoacoustic ultrasonic wave


A breast scanning apparatus which uses photoacoustic ultrasonic waves is provided. The breast scanning apparatus includes a body which includes a first hole and a second hole which are horizontally parallel to each other; a first compression plate and a second compression plate, at least one of which is movable in a vertical direction with respect to the body; a first sliding plate and a second sliding plate, which are respectively installed on surfaces of the first compression plate and the second compression plate and are facing each other and are movable in a first direction; a first ultrasonic transducer array in the first compression plate and facing the first sliding plate; and a first laser head in the first compression plate, which is movable in a second direction which is perpendicular to the first direction..
Samsung Electronics Co., Ltd.
05/21/15
20150141791
new patent

Magnetic resonance safe electrode for biopotential measurements


An electrode patch (34) for use in biopotential measurements in a magnetic resonance (mr) environment includes: a plastic or polymer sheet (32); an electrically conductive trace (58) disposed on the plastic or polymer sheet, the electrically conductive trace having sheet resistance of one ohm/square or higher; and an electrode (30) disposed on the electrically conductive trace and configured for attachment to human skin. In some embodiments the electrically conductive trace is a carbon-based electrically conductive trace.
Koninklijke Philips N.v.
05/21/15
20150141788
new patent

Transducer assemblies for dry applications of tranducers


A transducer assembly including a support terminal and at least one probe extending from the support terminal is adapted to enable a transducer to penetrate and slide through patches of hair covering a subject area of a person. The probe includes at least one leg structure supporting a transducer disposed at the distal end of the leg structure for sensing or stimulating the state of a particular property of a selected subject area when the transducer is applied by the leg structure to the selected subject area.
Cognionics, Inc.
05/21/15
20150141737
new patent

Method and device for treating osteoarthritis noninvasively


Methods and devices are provided for oa treatment of an affected area or joint. In one embodiment, the method may involve identifying a treatment site of the joint, and providing at least one transducer module at the treatment site.
05/21/15
20150141623
new patent

Protein purification methods to reduce acidic species


The instant invention relates to the field of protein production and purification, and in particular to compositions and processes for controlling the amount of charge variants, aggregates, and fragments of a protein of interest, as well as host cell proteins, present in purified preparations by applying particular chromatography conditions during such protein purification.. .
Abbvie, Inc.
05/21/15
20150141607
new patent

Curable composition


Provided are a curable composition and its use. The curable composition having excellent processability, workability, heat resistance, and light resistance, and having no problem of discoloring despite using for a long time may be provided.
Lg Chem, Ltd.
05/21/15
20150141445
new patent

Tricyclic compounds having cytostatic and/or cytotoxic activity and methods of use thereof


The present invention provides tricyclic compounds having cytostatic and cytotoxic activity in a single molecule having receptor tyrosine kinase(s), dihydrofolate reductase, thymidylate synthase and/or dihydroorotate dehydrogenase inhibitory activity, which are useful as anti-angiogenic and anti-tumor agents. Also provided are methods of utilizing these inhibitors to treat tumor cells and other proliferative diseases and disorders..
Duquesne University Of The Holy Ghost
05/21/15
20150141429
new patent

Parp inhibitor compounds, compositions and methods of use


The present invention relates to tetraaza phenalen-3-one compounds which inhibit poly (adp-ribose) polymerase (parp) and are useful in the chemosensitization of cancer therapeutics. The induction of peripheral neuropathy is a common side-effect of many of the conventional and newer chemotherapies.
Eisai Inc.
05/21/15
20150141372
new patent

Substituted cycloalkenopyrazoles as bub1 inhibitors for the treatment of cancer


Compounds of formula (i), processes for their production and their use as bub1 kinase inhibitors for the treatment of hyperproliferative diseases and/or disorders responsive to induction of cell death.. .
Bayer Pharma Aktiengesellschaft
05/21/15
20150141355
new patent

Salacia compositions, methods of treatment by their administration, and methods of their preparation


A salacia composition described herein significantly reduces appetite, activates hormone sensitive lipase, and manages a healthy lipid profile through inhibition of hmg-coa reductase enzyme. Salacia compositions described herein include of at least 12% of polyphenols, 2% of mangiferin and 1% of 25,26-oxidofriedelane-1,3-dione by weight of the composition in the form of extract.
Omniactive Health Technologies (canada) Limited
05/21/15
20150141342
new patent

Blood borne mirna signature for the accurate diagnosis of pancreatic ductal adenocarcinoma


The differential expression of select mirna in plasma and bile among patients with pdac, chronic pancreatitis (cp), and controls were measured. Patients (n=215) with treatment-naïve pdac (n=77), cp with bile or pancreatic duct pathology (n=67), and controls (n=71) that had been prospectively enrolled in a pancreatobiliary disease biorepository at the time of endoscopic retrograde cholangiopancreatography (ercp) or endoscopic ultrasound (eus) were identified.
Indiana University Research And Technology Corp.
05/21/15
20150141289
new patent

Methods and compositions for identifying and validating modulators of cell fate


The invention provides for compositions and methods for identifying and validating modulators of cell fate, such as such as maintenance, cell specification, cell determination, induction of stem cell fate, cell differentiation, cell dedifferentiation, and cell trans-differentiation. The invention relates to reporter nucleic acid constructs, host cells comprising such constructs, and methods using such cells and constructs.
Chromocell Corporation
05/21/15
20150141237
new patent

Disordered molecular sieve supports for the selective catalytic reduction of nox


A catalyst for selective catalytic reduction of nox having one or more transition metals selected from cr, mn, fe, co, ce, ni, cu, zn, ga, mo, ru, rh, pd, ag, in, sn, re, ir, pt, and mixtures thereof supported on a support, wherein the support has a molecular sieve having at least one intergrowth phase having at least two different small-pore, three-dimensional framework structures.. .
Johnson Matthey Public Limited Company
05/21/15
20150140962
new patent

Secure witness or criminal participant location or position and time recording information apparatus, systems and method


An apparatus, system or method for use of encrypted or confidential location or position, time, and unique identifier information (lpti information) comprising mobile device encoded unique identifiers (uis), to register the presence of one or more persons in a retail or service store or outlet, vehicle, financial, educational, governmental, transportation, shipping, cargo, residential, vacation, travel, power generation or distribution, water or food supply or storage, or data storage location or position, for use in identifying potential suspects, conspirators, participants or witnesses for criminal, regulated, tort, or prohibited activity for use by law enforcement or a court, and which information is kept encrypted until authorized access is granted to law enforcement or a court by issuance or a warrant or other appropriate legal authorization.. .
Secure Sigint, Llc
05/21/15
20150140939
new patent

Wireless communication device


A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (rf) unit capable of performing a conversion between a radio frequency (rf) signal and a baseband signal, wherein the wireless communication signal is one of the rf signal and the baseband signal.
Mediatek Inc.
05/21/15
20150140927
new patent

Wireless communication module and portable electronic device using the same


Disclosure is one wireless communication module comprising an antenna unit sending or receiving signals and energy; a chip unit storing signals from the antenna unit and processing them with the energy from the antenna; a coupling unit including a first and a second coupling terminals realizing a method of electromagnetic induction, resonant magnetic induction, or photoinduction to send signals and energy to each other; and a first matching terminal electrically connected to the antenna unit and the first coupling terminal to make impedance matching between the antenna unit and the first coupling terminal and a second matching unit and a second matching unit electrically connected to the chip unit and the second coupling terminal to make impedance matching between the chip unit and the second coupling terminal. The present invention also discloses a portable electronic device using the stated wireless communication module..
Taiwan Name Plate Co., Ltd.
05/21/15
20150140835
new patent

Substrate processing apparatus, manufacturing semiconductor device, and recording medium


A substrate processing apparatus is disclosed. The substrate processing apparatus includes a process chamber configured to accommodate a substrate; a gas supply unit configured to supply a process gas into the process chamber; a lid member configured to block an end portion opening of the process chamber; an end portion heating unit installed around a side wall of an end portion of the process chamber; and a thermal conductor installed on a surface of the lid member in an inner side of the process chamber, and configured to be heated by the end portion heating unit..
Hitachi Kokusai Electric Inc.
05/21/15
20150140834
new patent

Al2o3 surface nucleation preparation with remote oxygen plasma


Methods and apparatus for processing using a plasma source for the treatment of semiconductor surfaces are disclosed. The apparatus includes an outer vacuum chamber enclosing a substrate support, a plasma source (either a direct plasma or a remote plasma), and an optional showerhead.
Intermolecular Inc.
05/21/15
20150140829
new patent

Method for semiconductor manufacturing


A method includes followings operations. A semiconductor substrate is provided.
Taiwan Semiconductor Manufacturing Company Ltd.
05/21/15
20150140827
new patent

Methods for barrier layer removal


Implementations described herein generally relate to semiconductor manufacturing and more particularly to methods for etching a low-k dielectric barrier layer disposed on a substrate using a non-carbon based approach. In one implementation, a method for etching a barrier low-k layer is provided.
Applied Materials, Inc.
05/21/15
20150140824
new patent

Jig, manufacturing method thereof, and flip chip bonding chips of ultrasound probe using jig


A jig includes a wafer including an accommodation groove configured to accommodate a capacitive micromachined ultrasonic transducer (cmut) when flip chip bonding is performed, and a separation groove formed in a bottom surface of the accommodation groove, the separation groove having a bottom surface that is spaced apart from thin films of the cmut that face the bottom surface of the separation groove when the cmut is seated on portions of the bottom surface of the accommodation groove.. .
Kyungpook National University Industry-academic Cooperation Foundation
05/21/15
20150140820
new patent

Cleaning agent for semiconductor substrates and processing semiconductor substrate surface


A cleaning agent is provided for a semiconductor substrate superior in corrosion resistance of a tungsten wiring or a tungsten alloy wiring, and superior in removal property of polishing fines (particle) such as silica or alumina, remaining at surface of the semiconductor substrate, in particular, at surface of a silicon oxide film such as a teos film, after a chemical mechanical polishing process; and a method for processing a semiconductor substrate surface. A cleaning agent for a semiconductor substrate is to be used in a post process of a chemical mechanical polishing process of the semiconductor substrate having a tungsten wiring or a tungsten alloy wiring, and a silicon oxide film, comprising (a) a phosphonic acid-based chelating agent, (b) a primary or secondary monoamine having at least one alkyl group or hydroxyalkyl group in a molecule and (c) water, wherein a ph is over 6 and below 7..
Wako Pure Chemical Industries, Ltd.
05/21/15
20150140819
new patent

Semiconductor process


A semiconductor process includes the following steps. A substrate having trenches with different sizes is provided.
United Microelectronics Corp.
05/21/15
20150140817
new patent

Apparatuses facilitating fluid flow into via holes, vents, and other openings communicating with surfaces of substrates of semiconductor device components


A method for removing material from surfaces of at least a portion of at least one recess or at least one aperture extending into a surface of a substrate includes pressurizing fluid so as to cause the fluid to flow into the at least one recess or the at least one aperture. The fluid may be pressurized by generating a pressure differential across the substrate, which causes the fluid to flow into or through the at least one aperture or recess.
Micron Technology, Inc.
05/21/15
20150140815
new patent

Via in substrate with deposited layer


An opening such as a small-diameter via is formed in a semiconductor substrate such as a monocrystalline silicon chip or wafer by a high etch rate process which leaves the opening with a rough interior surface. A smoothing layer such as a polysilicon layer is applied over the interior surfaces of the openings.
Invensas Corporation
05/21/15
20150140814
new patent

Alkaline pretreatment for electroplating


Prior to electrodeposition, a semiconductor wafer having one or more recessed features, such as through silicon vias (tsvs), is pretreated by contacting the wafer with a pre-wetting liquid comprising a buffer (such as a borate buffer) and having a ph of between about 7 and about 13. This pre-treatment is particularly useful for wafers having acid-sensitive nickel-containing seed layers, such as nib and nip.
Lam Research Corporation
05/21/15
20150140811
new patent

Spacer-damage-free etching


A method of patterning a semiconductor device is disclosed. A tri-layer photoresist is formed over a plurality of patterned features.
Taiwan Semiconductor Manufacturing Company, Ltd.
05/21/15
20150140808
new patent

Semiconductor device having buried bit lines and fabricating the same


A semiconductor device includes body lines, formed substantially perpendicular to a substrate, and having recessed sidewalls, buried bit lines, buried in the recessed sidewalls, and including a metal silicide, and a barrier layer interposed between each of the buried bit lines and the body lines corresponding thereto, and containing germanium.. .
Sk Hynix Inc.
05/21/15
20150140807
new patent

Vias in porous substrates


A microelectronic unit can include a substrate having front and rear surfaces and active semiconductor devices therein, the substrate having a plurality of openings arranged in a symmetric or asymmetric distribution across an area of the rear surface, first and second conductive vias connected to first and second pads exposed at the front surface, pluralities of first and second conductive interconnects extending within respective ones of the openings, and first and second conductive contacts exposed for interconnection with an external element. The plurality of first conductive interconnects can be separated from the plurality of second conductive interconnects by at least one of the plurality of openings, the at least one opening at least partially filled with an insulating material.
Tessera, Inc.
05/21/15
20150140806
new patent

Wafer-level die attach metallization


Embodiments of a semiconductor wafer having wafer-level die attach metallization on a back-side of the semiconductor wafer, resulting semiconductor dies, and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor wafer includes a semiconductor structure and a front-side metallization that includes front-side metallization elements for a number of semiconductor die areas.
Cree, Inc.
05/21/15
20150140804
new patent

Semiconductor device and manufacturing the same


A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes adjacent storage node contact plugs having different heights, and lower-electrode bowing profiles having different heights, such that a spatial margin between the lower electrodes is assured and a bridge fail is prevented, resulting in improved device operation characteristics.
Sk Hynix Inc.
05/21/15
20150140803
new patent

Methods of forming semiconductor structures


Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such methods may include filling a plurality of trenches in a substrate with a dielectric material and removing portions of the substrate between the dielectric material to form a plurality of openings.
Micron Technology, Inc.
05/21/15
20150140802
new patent

Semiconductor device and process for producing semiconductor device


A semiconductor device includes: a substrate in which a product region and scribe regions are defined; a 1st insulation film formed above the substrate; a metal film in the 1st insulation film, disposed within the scribe regions in such a manner as to surround the product region; a 2nd insulation film formed on the 1st insulation film and the metal film; a 1st groove disposed more inside than the metal film in such a manner as to surround the product region, and reaching from a top surface of the 2nd insulation film to a position deeper than a top surface of the metal film; and a 2nd groove disposed more outside than the metal film in such a manner as to surround the metal film, and reaching from the top surface of the 2nd insulation film to a position deeper than the top surface of the metal film.. .
Fujitsu Semiconductor Limited
05/21/15
20150140800
new patent

Method of fabricating semiconductor device


A method of fabricating a semiconductor device includes the following steps. At least a first gate stack layer and at least a second gate stack layer protruding from a conductive layer on a substrate are provided.
United Microelectronics Corp.
05/21/15
20150140799
new patent

Asymmetric spacers


A semiconductor device having asymmetric spacers and steps for forming the same are disclosed. The spacers have difference capacitances, with the spacer having a higher capacitance formed over a source region of the device and the spacer having a lower capacitance formed over a drain region of the device.
International Business Machines Corporation
05/21/15
20150140798
new patent

Semiconductor manufacturing method and equipment thereof


A semiconductor manufacturing equipment includes a buffer chamber, a load port, a first chamber, and a second chamber respectively connected with the buffer chamber at a different side. The semiconductor manufacturing equipment also has a third chamber in the buffer chamber, the third chamber configured for cooling a wafer, and a single blade robot in the buffer chamber.
Taiwan Semiconductor Manufacturing Company Ltd.
05/21/15
20150140796
new patent

Formation of contact/via hole with self-alignment


In a method for manufacturing a semiconductor device, a substrate is provided, and a dielectric layer is formed to cover the substrate. A recess portion is formed in the dielectric layer.
Taiwan Semiconductor Manufacturing Co., Ltd.
05/21/15
20150140795
new patent

Method for producing semiconductor thin films on foreign substrates


The invention relates to a method by means of which the average single crystal size, in particular the diameter of the single crystals, in a semiconductor thin film applied to a foreign substrate can be increased by an order of magnitude with respect to prior methods. The method is characterized in that a thin semiconductor film is applied to the foreign substrate in a first step.
05/21/15
20150140794
new patent

Polycrystallization method


According to one embodiment, provided is a polycrystallization method for polycrystallizing an amorphous semiconductor film that has a natural oxide film on the surface . The polycrystallization method includes a step of cleaning the natural oxide film while leaving the natural oxide film on the surface of the amorphous semiconductor film, and a step of polycrystallizing the amorphous semiconductor film in the state where the natural oxide film is left..
Japan Display Inc.
05/21/15
20150140793
new patent

Nanowire devices


A method of forming nanowire devices. The method includes forming a stressor layer circumferentially surrounding a semiconductor nanowire.
International Business Machines Corporation
05/21/15
20150140792
new patent

Method for depositing a group iii nitride semiconductor film


Conditioning a surface of the substrate by etching and providing a conditioned surface; holding the substrate away from a substrate facing surface of a heater by a predetermined distance; heating the substrate to a temperature by using the heater whilst the substrate is held away from the substrate facing surface of the heater, and depositing a group iii nitride semiconductor film onto the conditioned surface of the substrate by a physical vapour deposition method whilst the substrate is held away from the substrate facing surface of the heater and forming an epitaxial group iii nitride semiconductor film with n-face polarity on the conditioned surface of the substrate.. .
05/21/15
20150140791
new patent

Apparatus for producing metal chloride gas and producing metal chloride gas, and hydride vapor phase epitaxy, nitride semiconductor wafer, nitride semiconductor device, wafer for nitride semiconductor light emitting diode, manufacturing nitride semiconductor freestanidng substrate and nitride semiconductor crystal


There is provided an apparatus for producing metal chloride gas, comprising: a source vessel configured to store a metal source; a gas supply port configured to supply chlorine-containing gas into the source vessel; a gas exhaust port configured to discharge metal chloride-containing gas containing metal chloride gas produced by a reaction between the chlorine-containing gas and the metal source, to outside of the source vessel; and a partition plate configured to form a gas passage continued to the gas exhaust port from the gas supply port by dividing a space in an upper part of the metal source in the source vessel, wherein the gas passage is formed in one route from the gas supply port to the gas exhaust port, with a horizontal passage width of the gas passage set to 5 cm or less, with bent portions provided on the gas passage.. .
Hitachi Metals, Ltd.
05/21/15
20150140788
new patent

Apparatus and producing group iii nitride semiconductor device and producing semiconductor wafer


The production apparatus includes a shower head electrode, a susceptor for supporting a growth substrate, a first gas supply pipe, and a second gas supply pipe. The first gas supply pipe has at least one first gas exhaust outlet and supplies an organometallic gas containing group iii metal as a first gas, and the second gas supply pipe supplies a gas containing nitrogen gas as the second gas.
National University Corporation Nagoya University
05/21/15
20150140785
new patent

Method of manufacturing semiconductor device


A method of manufacturing a semiconductor device include preparing an initial substrate including an edge region and a central region in which circuit patterns are formed, forming a reforming region in the edge region of the initial substrate, grinding the initial substrate to form a substrate, and cutting the substrate to form a semiconductor chip including each of the circuit patterns. A crystal structure of the reforming region is different from that of the initial substrate..
Samsung Electronics Co., Ltd.
05/21/15
20150140783
new patent

Wafer dicing press and method and semiconductor wafer dicing system including the same


In a wafer dicing press for reducing time and cost for wafer dicing and for evenly applying a dicing pressure to a whole wafer, a wafer dicing press includes a support unit supporting a first side of a wafer; and a pressurization device applying a pressure, by dispersing the pressure, to a second side of the wafer so that a laser-scribed layer of the wafer operates as a division starting point. Accordingly, the wafer dicing press reduces laser radiation and pressure-application times for dividing a wafer into semiconductor devices.
05/21/15
20150140781
new patent

Semiconductor isolation structure and manufacture


A method of formation of an isolation structure for vertical semiconductor devices, the resulting isolation structure, and a memory device to prevent leakage among adjacent vertical semiconductor devices are described.. .
Micron Technology, Inc.
05/21/15
20150140777
new patent

Methods of selectively doping chalcogenide materials and methods of forming semiconductor devices


Methods of selectively forming a metal-doped chalcogenide material comprise exposing a chalcogenide material to a transition metal solution, and incorporating transition metal of the transition solution into the chalcogenide material without substantially incorporating the transition metal into an adjacent material. The chalcogenide material is not silver selenide.
Micron Technology, Inc.
05/21/15
20150140774
new patent

Method of fabricating semiconductor device


A method of fabricating a semiconductor device comprises forming a first etch stop layer over a first dielectric layer. The method also comprises forming a first trench in the first etch stop layer and the first dielectric layer.
Taiwan Semiconductor Manufacturing Company, Ltd.
05/21/15
20150140771
new patent

Method for fabricating a bipolar transistor having self-aligned emitter contact


A method of producing a semiconductor device, comprising a substrate layer made of a semiconductor material of a first conductivity type and having a first insulation region, and a vertical bipolar transistor having a first vertical portion of a collector made of monocrystalline semiconductor material of a second conductivity type and disposed in an opening of the first insulation region, a second insulation region lying partly on the first vertical portion of the collector and partly on the first insulation region and having an opening in the region of the collector, in which opening a second vertical portion of the collector made of monocrystalline material is disposed, the portion including an inner region of the second conductivity type, a base made of monocrystalline semiconductor material of the first conductivity type, a base connection region surrounding the base in the lateral direction, a t-shaped emitter made of semiconductor material of the second conductivity type and overlapping the base connection region, wherein the base connection region, aside from a seeding layer adjacent the substrate or a metallization layer adjacent a base contact, consists of a semiconductor material which differs in its chemical composition from the semiconductor material of the collector, the base and the emitter and in which the majority charge carriers of the first conductivity type have greater mobility compared thereto.. .
Ihp Gmbh - Innovations For High Performance Microelectronics/leibniz-institut Fur Innovative M
05/21/15
20150140769
new patent

Raised source/drain mos transistor and forming the transistor with an implant spacer and an epitaxial spacer


A raised source/drain mos transistor is formed in a process that utilizes a first sidewall spacer when implanting a semiconductor region to form the heavily-doped source region and the heavily-doped drain region of the transistor, and a second different sidewall spacer when epitaxially growing the raised source region and the raised drain region of the transistor.. .
Texas Instruments Incorporated
05/21/15
20150140768
new patent

Method of manufacturing semiconductor device


A performance of a semiconductor device is improved. A gate electrode is formed on an soi substrate via a gate insulating film, and a laminated film including an insulating film il2 and an insulating film il3 on the insulating film il2 is formed on the soi substrate so as to cover the gate electrode, and then, a sidewall spacer formed of the laminated film is formed on a side wall of the gate electrode by etching back the laminated film.
Renesas Electronics Corporation
05/21/15
20150140767
new patent

Process for manufacturing devices for power applications in integrated circuits


A mos transistor for power applications is formed in a substrate of semiconductor material by a method integrated in a process for manufacturing integrated circuits which uses an sti technique for forming insulating regions. The method includes the phases of forming an insulating element on a top surface of the substrate and forming a control electrode on a free surface of the insulating element.
Stmicroelectronics S.r.l.
05/21/15
20150140765
new patent

Method of fabricating a gate dielectric layer


A method of making a semiconductor device, the method includes forming an active region in a substrate. The method further includes forming a first gate structure over the active region, where the forming the first gate structure includes forming a first interfacial layer.
Taiwan Semiconductor Manufacturing Company, Ltd.
05/21/15
20150140764
new patent

Single poly plate low on resistance extended drain metal oxide semiconductor device


A semiconductor device, in particular, an extended drain metal oxide semiconductor (ed-mos) device, defined by a doped shallow drain implant in a drift region. For example, an extend drain n-channel metal oxide semiconductor (ed-nmos) device is defined by an n doped shallow drain (ndd) implant in the drift region.
Macronix International Co., Ltd.
05/21/15
20150140763
new patent

Contact structure of semiconductor device


The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ild) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer..
Taiwan Semiconductor Manufacturing Company, Ltd.
05/21/15
20150140762
new patent

Finfet with merge-free fins


A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions..
International Business Machines Corporation
05/21/15
20150140761
new patent

Device isolation in finfet cmos


Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage.
Renesas Electronics Corporation
05/21/15
20150140758
new patent

Method for fabricating finfet on germanium or group iii-v semiconductor substrate


The present invention provides a method for fabricating a finfet on a germanium or group iii-v semiconductor substrate. The process flow of the method mainly includes: forming a pattern structure for a source, a drain and a fine bar connecting the source and the drain; forming an oxide isolation layer; forming a gate structure, a source and a drain structure; and forming metal contacts and metal interconnections.
Peking University
05/21/15
20150140757
new patent

Methods of forming semiconductor devices including an embedded stressor, and related apparatuses


Methods of forming semiconductor devices are provided. A method of forming a semiconductor device includes forming preliminary trenches adjacent opposing sides of an active region.
Samsung Electronics Co., Ltd.
05/21/15
20150140755
new patent

Method for producing a semiconductor device with surrounding gate transistor


A method for producing a semiconductor device includes a first step of forming a fin-shaped silicon layer on a silicon substrate using a first resist and forming a first insulating film therearound; and a second step of forming a second insulating film around the fin-shaped silicon layer and etching the second insulating film so as to be left on a side wall of the fin-shaped silicon layer, depositing a third insulating film on the first and second insulating films and the fin-shaped silicon layer, depositing a polysilicon thereon, planarizing a surface thereof, and etching back the polysilicon to expose the third insulating film, forming a second resist, etching the second and third insulating films and then etching the fin-shaped silicon layer and the polysilicon, and removing the second insulating film to form a pillar-shaped silicon layer and a dummy gate formed of the polysilicon.. .
Unisantis Electronics Singapore Pte. Ltd.
05/21/15
20150140754
new patent

Semiconductor device, manufacturing the same, and power module


A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer portions of the n-type base layer and the p-type base layer, respectively, a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer, a gate electrode formed on the gate insulation film facing the p-type base layer across the gate insulation film, a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer, a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer and including first baryons converted to donors, a source electrode connected to the n-type source layer, and a drain electrode connected to the n-type drain layer.. .
Rohm Co., Ltd.
05/21/15
20150140752
new patent

Multiple-time programming memory cells and methods for forming the same


A method includes forming shallow trench isolation (sti) regions to separate a first active region and a second active region of a semiconductor substrate from each other, etching a portion of the sti regions that contacts a sidewall of the second active region to form a recess, and implanting a top surface layer and a side surface layer of the second active region to form an implantation region. The side surface layer of the second active region extends from the sidewall of the second active region into the second active region.
Taiwan Semiconductor Manufacturing Company, Ltd.
05/21/15
20150140750
new patent

Process for manufacturing integrated device incorporating low-voltage components and power components


An integrated device includes: a semiconductor body having a first, depressed, portion and second portions which project from the first portion; a sti structure, extending on the first portion of the semiconductor body, which delimits laterally the second portions and has a face adjacent to a surface of the first portion; low-voltage cmos components, housed in the second portions, in a first region of the semiconductor body; and a power component, in a second region of the semiconductor body. The power component has at least one conduction region, formed in the first portion of the semiconductor body, and a conduction contact, coupled to the conduction region and traversing the sti structure in a direction perpendicular to the surface of the first portion of the semiconductor body..
Stmicroelectronics S.r.l.
05/21/15
20150140749
new patent

Semiconductor device having reduced-damage active region and manufacturing the same


A semiconductor device according to example embodiments may include a substrate having an nmos area and a pmos area, isolation regions and well regions formed in the substrate, gate patterns formed on the substrate between the isolation regions, source/drain regions formed in the substrate between the gate patterns and the isolation regions, source/drain silicide regions formed in the source/drain regions, a tensile stress layer formed on the nmos area, and a compressive stress layer formed on the pmos area, wherein the tensile stress layer and compressive stress layer may overlap at a boundary region of the nmos area and the pmos area. The semiconductor devices according to example embodiments and methods of manufacturing the same may increase the stress effect on the active region while reducing or preventing surface damage to the active region..
Samsung Electronics Co., Ltd.
05/21/15
20150140747
new patent

Semiconductor device including transistor and manufacturing the same


A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a bulk epitaxial pattern disposed in a recess region formed in the semiconductor substrate at a side of the gate pattern, an insert epitaxial pattern disposed on the bulk epitaxial pattern, and a capping epitaxial pattern disposed on the insert epitaxial pattern. The bulk epitaxial pattern has an upper inclined surface that is a {111} crystal plane, and the insert epitaxial pattern includes a specific element that promotes the growth rate of the insert epitaxial pattern on the upper inclined surface..
Samsung Electronics Co., Ltd.
05/21/15
20150140742
new patent

Methods of forming gated devices


Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend primarily along a first direction.
Micron Technology, Inc.
05/21/15
20150140741
new patent

Fully isolated ligbt and methods for forming the same


A device includes a dielectric layer, and a heavily doped semiconductor layer over the dielectric layer. The heavily doped semiconductor layer is of a first conductivity type.
Taiwan Semiconductor Manufacturing Company, Ltd.
05/21/15
20150140740
new patent

Method of fabrication, device structure and submount comprising diamond on metal substrate for thermal dissipation


A method of fabrication, a device structure and a submount comprising high thermal conductivity (htc) diamond on a htc metal substrate, for thermal dissipation, are disclosed. The surface roughness of the diamond layer is controlled by depositing diamond on a sacrificial substrate, such as a polished silicon wafer, having a specific surface roughness.
Advanced Diamond Technologies, Inc.
05/21/15
20150140739
new patent

Discrete semiconductor device package and manufacturing method


Disclosed is a discrete semiconductor device package (100) comprising a semiconductor die (110) having a first surface and a second surface opposite said first surface carrying a contact (112); a conductive body (120) on said contact; an encapsulation material (130) laterally encapsulating said conductive body; and a capping member (140, 610) such as a solder cap, a further semiconductor die or a combination thereof in conductive contact with the solder portion, said solder cap extending over the encapsulation material. A further solder cap (150) may be provided over the first surface.
Nxp B.v.
05/21/15
20150140738
new patent

Circuit connecting material and semiconductor device manufacturing method using same


Provided are a circuit connecting material able to provide good bonding with an opposing electrode, and a semiconductor device manufacturing method using the same. The present invention uses a circuit connecting material, in which a first adhesive layer to be adhered to the semiconductor chip side, and a second adhesive layer having a lowest melting viscosity attainment temperature higher than that of the first adhesive layer are laminated.
Dexerials Corporation
05/21/15
20150140737
new patent

Wafer level semiconductor package and manufacturing methods thereof


A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface.
Advanced Semiconductor Engineering, Inc.
05/21/15
20150140736
new patent

Semiconductor device and forming wire bondable fan-out ewlb package


A semiconductor device has a first semiconductor die and a first encapsulant deposited over the first semiconductor die. An interconnect structure is formed over the first semiconductor die and first encapsulant.
Stats Chippac, Ltd.
05/21/15
20150140734
new patent

Semiconductor device


To provide a highly reliable semiconductor device which includes a transistor including an oxide semiconductor, in a semiconductor device including a staggered transistor having a bottom-gate structure provided over a glass substrate, a gate insulating film in which a first gate insulating film and a second gate insulating film, whose compositions are different from each other, are stacked in this order is provided over a gate electrode layer. Alternatively, in a staggered transistor having a bottom-gate structure, a protective insulating film is provided between a glass substrate and a gate electrode layer.
Semiconductor Energy Laboratory Co., Ltd.
05/21/15
20150140733
new patent

Method for manufacturing semiconductor device


To provide a semiconductor device including an oxide semiconductor which is capable of having stable electric characteristics and achieving high reliability, by a dehydration or dehydrogenation treatment performed on a base insulating layer provided in contact with an oxide semiconductor layer, the water and hydrogen contents of the base insulating layer can be decreased, and by an oxygen doping treatment subsequently performed, oxygen which can be eliminated together with the water and hydrogen is supplied to the base insulating layer. By formation of the oxide semiconductor layer in contact with the base insulating layer whose water and hydrogen contents are decreased and whose oxygen content is increased, oxygen can be supplied to the oxide semiconductor layer while entry of the water and hydrogen into the oxide semiconductor layer is suppressed..
Semiconductor Energy Laboratory Co., Ltd.
05/21/15
20150140732
new patent

Method for manufacturing semiconductor device


It is an object to drive a semiconductor device at high speed or to improve the reliability of the semiconductor device. In a method for manufacturing the semiconductor device, in which a gate electrode is formed over a substrate with an insulating property, a gate insulating film is formed over the gate electrode, and an oxide semiconductor film is formed over the gate insulating film, the gate insulating film is formed by deposition treatment using high-density plasma.
Semiconductor Energy Laboratory Co., Ltd.
05/21/15
20150140731
new patent

Method for manufacturing semiconductor device


To improve productivity of a transistor that includes an oxide semiconductor and has good electrical characteristics. In a top-gate transistor including a gate insulating film and a gate electrode over an oxide semiconductor film, a metal film is formed over the oxide semiconductor film, oxygen is added to the metal film to form a metal oxide film, and the metal oxide film is used as a gate insulating film.
Semiconductor Energy Laboratory Co., Ltd.
05/21/15
20150140730
new patent

Oxide semiconductor film, semiconductor device, and manufacturing semiconductor device


A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used. In a transistor using an oxide semiconductor film for an active layer, a microvoid is provided in a source region and a drain region adjacent to a channel region.
Semiconductor Energy Laboratory Co., Ltd.
05/21/15
20150140727
new patent

Method for forming conductive electrode patterns and manufacturing solar cells comprising the same


A method for forming conductive electrode patterns of a solar cell is provided. The method includes preparing a glass substrate and forming a transparent conductive oxide film (tco) on the glass substrate.
Hyundai Motor Company
05/21/15
20150140726
new patent

Method for manufacturing semiconductor device


A transparent conductive substrate (1) in which a transparent conductive film (12) is placed on a light-transmissive base plate (11) is brought into a reaction chamber of a plasma apparatus without being rinsed (step (a)) and the transparent conductive film (12) is treated with plasma using a ch4 gas and an h2 gas (step (b)). After step (b), semiconductor devices are deposited on the transparent conductive film (12) in series (steps (c) and (d)) and a semiconductor device (10) is manufactured (step (e))..
Sharp Kabushiki Kaisha
05/21/15
20150140721
new patent

Patterning of silicon oxide layers using pulsed laser ablation


Various laser processing schemes are disclosed for producing various types of hetero junction and homo-junction solar cells. The methods include base and emitter contact opening, selective doping, metal ablation, annealing to improve passivation, and selective emitter doping via laser heating of aluminum.
Solexel, Inc.
05/21/15
20150140719
new patent

Vertical conductive connections in semiconductor substrates


An embodiment of a die comprising: a semiconductor body including a front side, a back side, and a lateral surface; an electronic device, formed in said semiconductor body and including an active area facing the front side; a vertical conductive connection, extending through the semiconductor body and defining a conductive path between the front side and the back side of the semiconductor body; and a conductive contact, defining a conductive path on the front side of the semiconductor body, between the active area and the vertical conductive connection, wherein the vertical conductive connection is formed on the lateral surface of the die, outside the active area.. .
Stmicroelectronics, S.r.l.
05/21/15
20150140713
new patent

Peeling apparatus and manufacturing apparatus of semiconductor device


To eliminate electric discharge when an element formation layer including a semiconductor element is peeled from a substrate used for manufacturing the semiconductor element, a substrate over which an element formation layer and a peeling layer are formed and a film are made to go through a gap between pressurization rollers. The film is attached to the element formation layer between the pressurization rollers, bent along a curved surface of the pressurization roller on a side of the pressurization rollers, and collected.
Semiconductor Energy Laboratory Co., Ltd.
05/21/15
20150140711
new patent

Method of separating a wafer of semiconductor devices


A method according to embodiments of the invention includes providing a wafer comprising a semiconductor structure grown on a growth substrate. The semiconductor structure includes a light emitting layer disposed between an n-type region and a p-type region.
Koninklijke Philips N.v.
05/21/15
20150140707
new patent

Semiconductor light emitting device and manufacturing method thereof


A semiconductor light emitting device includes: a light emission structure in which a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer are sequentially stacked; a first electrode formed on the first conductive semiconductor layer; an insulating layer formed on the second conductive semiconductor layer and made of a transparent material; a reflection unit formed on the insulating layer and reflecting light emitted from the active layer; a second electrode formed on the reflection unit; and a transparent electrode formed on the second conductive semiconductor layer, the transparent electrode being in contact with the insulating layer and the second electrode.. .
Samsung Electronics Co., Ltd.
05/21/15
20150140702
new patent

Method for manufacturing semiconductor light emitting device


The method for manufacturing the semiconductor light emitting device includes steps of forming a plurality of semiconductor light emitting element regions on a substrate, forming a recess portion between the plurality of semiconductor light emitting element regions on a surface of the substrate, disposing a light reflective sealing resin on the substrate to cover the plurality of semiconductor light emitting element regions with the sealing resin and to fill the recess portion with a part of the sealing resin that covers the plurality of semiconductor light emitting element regions, removing the substrate, disposing a light transmissive resin on surfaces of the plurality of semiconductor light emitting element regions where the substrate has been removed, and dividing the plurality of semiconductor light emitting element regions into individual pieces, wherein the recess portion includes a first recess portion and one or more second recess portions shallower than the first recess portion.. .
Nichia Corporation
05/21/15
20150140699
new patent

Methods of forming oxide semiconductor devices and methods of manufacturing display devices having oxide semiconductor devices


A method of forming an oxide semiconductor device may be provided. In the method, a substrate comprising a first major surface and a second major surface that faces away from the first major surface may be provided.
Industry-academic Cooperation Foundation, Yonsei University
05/21/15
20150140695
new patent

Method and system for determining overlap process windows in semiconductors by inspection techniques


The formation of overlap areas in sophisticated semiconductor devices is a critical aspect which may not be efficiently evaluated on the basis of conventional measurement and design strategies. For this reason, the present disclosure provides measurement techniques and systems in which overlying device patterns are transformed into the same material layer, thereby forming a combined pattern which is accessible by well-established defect inspection techniques.
Globalfoundries Inc.
05/21/15
20150140693
new patent

Misalignment/alignment compensation method, semiconductor lithography system, and semiconductor patterning


A misalignment/alignment compensation method for a lithography process includes the steps of: obtaining misalignment data associated with an alignment mark disposed on a substrate; and obtaining a compensation parameter by performing asymmetry compensation calculation on at least one of a first directional component of the misalignment data, which is associated with a first direction, and a second directional component of the misalignment data, which is associated with a second direction.. .
05/21/15
20150140692
new patent

Advanced process control controlling width of spacer and dummy sidewall in semiconductor device


An advanced process control (apc) method for controlling a width of a spacer in a semiconductor device includes: providing a semiconductor substrate; providing a target width of a gate; forming the gate on the semiconductor substrate, in which the gate has a measured width; depositing a dielectric layer covering the gate, in which the dielectric layer has a measured thickness; providing a target width of the spacer; determining a trim time of the dielectric layer based on the target width of the gate, the measured width of the gate, the target width of the spacer, and the measured thickness of the dielectric layer; and performing a trimming process on the dielectric layer for the determined trim time to form the spacer.. .
Taiwan Semiconductor Manufacturing Co., Ltd.
05/21/15
20150140690
new patent

Etching semiconductor product


There is provided an etching method for a semiconductor product. The semiconductor product having, on a substrate, an sio2 layer, and an si layer with a free surface and directly stacked on the sio2 layer is prepared.
Tohoku University
05/21/15
20150140661
new patent

Method for producing pancreatic hormone-producing cell, pancreatic hormone-producing cell, and differentiation/induction promoter


The method for producing a pancreatic hormone-producing cell according to the present invention is characterized in that a specific differentiation/induction promoter is added to a culture medium in the process of differentiating/inducing of a pluripotent stem cell or a pancreatic tissue stem/progenitor cell into the pancreatic hormone-producing cell. The differentiation/induction promoter to be used is: a polypeptide which comprises an amino acid sequence encoded by dna comprising the nucleotide sequence represented by seq id no: 1 or a variant thereof; or a culture supernatant of a cell into which dna comprising the nucleotide sequence represented by seq id no: 1 or dna capable of hybridizing with dna comprising a nucleotide sequence complementary to the aforementioned dna under stringent conditions is integrated as a foreign gene..
Saitama Medical University
05/21/15
20150140641
new patent

Endoglucanase variants


The present invention relates to variant endoglucanases having improved thermoactivity, improved thermostability, and improved viscosity reduction activity over wild-type m. Thermophila endoglucanase..
Codexis, Inc.
05/21/15
20150140629
new patent

Alcoholic fermentation process in the presence of a high alcohol tolerant yeast and a maltotriose positive yeast


The invention relates to an alcoholic fermentation process in the presence of one or more high alcohol tolerant yeast and one or more maltotriose positive yeast. The process of the present invention can be a fermentation process for the production of ethanol, for the production of beer, for the production of wine and the like, in a preferred embodiment, the present invention relates to a process for the production of ethanol in the presence of distiller's yeast and baker's yeast..
Cargill, Incorporated
05/21/15
20150140624
new patent

Production of lactic acid from fermentations using mixed bacterial cultures


A method and system for producing lactic acid from biomass materials uses a mixed bacteria culture of at least one homofermentative lactic acid bacteria and at least one heterofermentative lactic acid bacteria in an integrated production system to increase the productivity and yield of lactic acid.. .
Jiangsu University
05/21/15
20150140607
new patent

Cho expression system


The present invention is within the field of industrial protein production. The inventors have designed and constructed a new expression system comprising an expression vector coding for a glutamine synthetase of human or dog origin, and a cho cell line.
Sanofi
05/21/15
20150140600
new patent

Mass spectrometry quantitation of p450 isoforms in hepatocytes


A method for screening a drug for cytochrome p450 (cyp) induction is provided and can include incubating the drug with a microsome-containing biological sample and then quantitating at least one cytochrome p450 isoform. The isoforms can be selected from 2b6, 3a4, 1a2, and 3a5 isoforms.
Dh Technologies Development Pte. Ltd.
05/21/15
20150140555
new patent

Method of identifying foetal erythroblast


There is provided a method for identifying at least one foetal erythroblast the method comprising: (a) detecting the expression of at least one foetal erythroblast specific marker selected from the group consisting of neutral amino acid transporter b (slc1a5), solute carrier family 3 (activators of dibasic and neutral amino acid transport) member 2 isoform a (slc3a2), splice isoform a of chloride channel protein 6, transferrin receptor protein 1, splice isoform 3 of protein gpr107 precursor, olfactory receptor 11h4, splice isoform 1 of protein c9orf5, cleft lip and palate transmembrane protein 1, bcg induced integral membrane protein bigm103, antibacterial protein fall-39 precursor, caax prenyl protease 1 homolog, splice isoform 2 of synaptophysin-like protein, vitamin k epoxide reductase complex subunit 1-like protein 1, splice isoform 1 of protein c20orf22 (abhd12), hypothetical protein dkfzp564k247 (hypoxia induced gene 1 protein) (ipi accession no. Ipi00295621), hypothetical protein dk-fzp586c1924 (ipi accession no.
National University Of Singapore
05/21/15
20150140542
new patent

Robotic game system for educational competitions


Robotic game system for education of the electrical, mechanical, design and strategic arts containing elements for robotic remote control and autonomous action in inter-team competitions with illustrative examples of said education materials and components.. .
Visualedge, Inc.
05/21/15
20150140541
new patent

Educational querying processing based on detected course enrollment and course-relevant query time


Techniques can construct a learner's educational context (e.g., course enrollments, subject-matter interests, and/or activity involvements) and tailor query processing using the educational context. For a given query, each concept in a set of concepts can be assigned a weight.
Pearson Education, Inc.
05/21/15
20150140540
new patent

Information processing system, information processing method, information processing apparatus, portable terminal, and control method and control program thereof


There is provided an information processing apparatus that readily supports to provide hardware resources for implementing ict education in the field of education. The information processing apparatus includes a device information receiver that receives, via a network, device information for identifying a device connected to a portable terminal, an education application selector that selects, based on the device information, an education application to be provided to the device, and an education application provider that provides the education application to the device via the network and the portable terminal..
Nec Corporation
05/21/15
20150140492
new patent

Conductive polymer composition, coated article having antistatic film formed from the composition, and patterning process using the composition


The present invention is a conductive polymer composition containing a π-conjugated conductive polymer, a polyanion, and a gemini surfactant. There can be provided a conductive polymer composition that has excellent antistatic performance and excellent application properties, does not adversely affect a resist, and can be suitably used in lithography using electron beam or the like..
Shin-etsu Chemical Co., Ltd.
05/21/15
20150140479
new patent

Method of processing a semiconductor wafer such as to make prototypes and related apparatus


A method of processing a semiconductor wafer may include providing a rotatably alignable photolithography mask that includes different mask images. Each mask image may be in a corresponding different mask sector.
Stmicroelectronics Pte Ltd
05/21/15
20150140188
new patent

Process for the continuous production of pasteurized dried minced meat, reconstituted in the form of thin slabs, and unit for carrying out said process


Transporting the meat strip to an output conveyor.. .
05/21/15
20150140171
new patent

Two-phase fermentation of staphylococcus increases nitrate reductase activity


The present invention is related to the field of reddening of food products. In particular the present invention relates to a two-phase fermentation method for boosting the nitrate reductase activity of staphylococcus strains with nitrate reductase activity comprising a first aerobic phase in the absence of nitrate and a second anaerobic or oxygen limited phase with continuous nitrate feeding and use of the staphylococcus strains for reddening of most products..
Chr. Hansen A/s
05/21/15
20150140116
new patent

Bone implant materials comprising cross-linked bioactive hydrogel matrices


The present invention is directed to a stabilized cross-linked hydrogel matrix comprising a first high molecular weight component and a second high molecular weight component that are covalently linked, and at least one stabilizing or enhancing agent, wherein the first high molecular weight component and the second high molecular weight component are each selected from the group consisting of polyglycans and polypeptides. This stabilized hydrogel matrix may be prepared as bioactive gels, pastes, slurries, cell attachment scaffolds for implantable medical devices, and casting or binding materials suitable for the construction of medical devices.
Pioneer Surgical Technology, Inc.
05/21/15
20150140061
new patent

Coated stent comprising an hmg-coa reductase inhibitor


Stents with coatings comprising a combination of a restenosis inhibitor comprising an hmg-coa reductase inhibitor and a carrier. Also provided are methods of coating stents with a combination of an hmg-coa reductase inhibitor and a carrier.
Covidien Lp


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