|| List of recent Duc-related patents
| Compositions, organisms, systems, and methods for expressing a gene product in plants|
The present disclosure relates, in some embodiments, to compositions, organisms, systems, and methods for expressing a gene product in a plant using a expression control sequence (ecs) operable in monocots and/or dicots. For example, (i) an isolated nucleic acid may comprise an ecs (e.g., a sugarcane bacilliform virus promoter) and, optionally, an exogenous nucleic acid (exna) operably linked to the ecs; (ii) an expression vector may comprise an ecs; an exna; and, optionally, a 3′ termination sequence, wherein the ecs has promoter activity sufficient to express the exna in at least one monocot and at least one dicot; (iii) a microorganism, plant cell, or plant may comprise an isolated nucleic acid; (iv) a method for constitutively expressing an exna in a plant (e.g., a monocot and/or a dicot) may comprise, contacting an expression vector with the cytosol of a cell of the plant, wherein the expression vector comprises the exna and an ecs operable to drive expression of the exna; and/or (v) a method of directing constitutive expression of a nucleic acid in a plant (e.g., a monocot and/or a dicot) may comprise transforming the plant with an expression nucleic acid comprising an ecs, an exna, and a 3′ termination sequence..
| Method and system for designing 3d semiconductor package|
A three-dimensional semiconductor package and method for making the same include providing a first package layout parameter for a plurality of first terminals included in a first package, a second package layout parameter for a plurality of second terminals included in a second package disposed above or below the first package, and a connection terminal layout parameter for a plurality of connection terminals electrically connecting the first package and the second package; providing a first wiring connection layout between the first and second terminals and the connection terminals by applying a first process to the first package, second package, and connection terminal layout parameters; and providing a second wiring connection layout between the first and second terminals and the connection terminals by applying a second process, which is different from the first process, to the first wiring connection layout.. .
| Dummy shoulder structure for line stress reduction|
Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate.
| System and method of testing through-silicon vias of a semiconductor die|
A method includes contacting a first group of through-silicon vias (tsvs) contacts with a multi-contact probe and applying a first voltage value to each of the first group of tsv contacts via the multi-contact probe, where the first group of tsv contacts corresponds to a first group of tsvs. The method also includes determining, based on a second voltage value detected at a particular tsv of the first group of tsvs, whether the particular tsv corresponds to a tsv test result..
| Semiconductor apparatus and method of operating the same|
A semiconductor apparatus includes a memory device configured to include a buffer memory block and a main memory block, and to correct data read from the buffer memory block based on error information, and to perform a program loop to store corrected data in the main memory block, and a memory controller configured to perform an error checking and correction (ecc) operation on the data and to output the error information obtained through the ecc operation to the memory device.. .
| Semiconductor device|
Supply of power to a plurality of circuits is controlled efficiently depending on usage conditions and the like of the circuits. An address monitoring circuit monitors whether a cache memory and an input/output interface are in an access state or not, and performs power gating in accordance with the state of the cache memory and the input/output interface.
| Semiconductor device and method of operating the same|
A method of operating a semiconductor device may comprise storing data in memory cells coupled to first word lines of memory blocks including the first word lines and second word lines located respectively between the first word lines, detecting a memory block, where data stored in the memory cells of the first word lines is invalidated, from the memory blocks, and storing data in memory cells coupled to the second word lines of the detected memory block.. .
| Method for parallel mining of temporal relations in large event file|
Disclosed herein is a method for parallel mining of temporal relations in a large event file using a mapreduce model. In the method for parallel mining of temporal relations in a large even file according to the present invention, an event file is sorted based on customer identification (id) and event time at which each event has occurred.
| Online reward point exchange method and system with price, redemption and transacted value discount scheduling|
An online reward exchange system and method of operation, which includes an exchange computer that interoperates via a computer network with user computers, reward point issuer computers, and merchant computers. The merchants' products may be purchased by a user by requesting an issuer(s) to redeem reward points in exchange for payment to the merchant for the product.
| Skills amelioration system|
Required certifications and education for each member of a group are automatically scanned. Current certifications and educational requirements are compared against the current job function, skills, and location for each member of the group, such as for each employee of a department of a company.
| Mobile assay facility and method of using same to procure and assay precious metals|
A self contained, mobile assay facility built in a modified armored truck is completely equipped to smelt and assay precious metals, particularly gold and silver. An induction furnace melts the metal that is then poured into an ingot.
| Text reproduction device, text reproduction method and computer program product|
According to an embodiment, a text reproduction device includes a setting unit, an acquiring unit, an estimating unit, and a modifying unit. The setting unit is configured to set a pause position delimiting text in response to input data that is input by the user during reproduction of speech data.
| Treatment device using nanotechnology|
The current invention discloses a treatment device having a heat source, a power source and a heat applicator. The power source includes at least one nanotech battery, ensuring superior properties such as prolonged electricity production and prompt recharging.
| Heating device using exothermic chemical reaction|
The current invention discloses a treatment device having a heat source, a power source, a heat applicator and a lighting mechanism. The power source includes at least one nanotech battery, ensuring superior properties such as prolonged electricity production and prompt recharging.
| Optmizing energy transmission in a leadless tissue stimulation system|
Method and systems for optimizing acoustic energy transmission in implantable devices are disclosed. Transducer elements transmit acoustic locator signals towards a receiver assembly, and the receiver responds with a location signal.
| Method and apparatus for controlling ultrasound system|
Provided are an ultrasound system and methods that deliver medication through skin by using multiple frequencies. The method to deliver medication through skin include irradiating the skin with ultrasound having a first frequency to cavitate a skin tissue; irradiating the skin with ultrasound having a second frequency, which is lower than the first frequency, to collapse the cavitated tissue; and delivering the medication through the collapsed tissue, wherein a single transducer is configured to produce the ultrasound having the first frequency and the ultrasound having the second frequency..
| Ring laser for use with imaging probe as a safe margin indicator|
A surgical imaging apparatus is disclosed, and includes an elongate body having a proximal portion and a distal portion and including at least one ultrasonic transducer. The surgical imaging apparatus also includes at least one light source being operatively coupled with the elongate body and configured to move relative to the elongate body.
| Ultrasonic probe and ultrasonic medical system adopting the same|
An ultrasonic probe and a medical system adopting the same. The ultrasonic probe includes at least one support plate having a first state of being folded and a second state of being unfolded.
| Probe with optoacoustic isolator|
An optoacoustic probe including an ultrasound transducer array, an acoustic lens and a light path separated from the transducer array by an isolator to mitigate light energy from the light path from reaching the transducer array. The isolator being formed from a mixture including a flexible carrier, a coloring and between 10% and 80% by volume micro-bubbles.
| Heating device using exothermic chemical reaction|
The current invention discloses a treatment device having a heat source, a power source, a heat applicator and a lighting mechanism. The power source includes at least one battery having superior properties such as prolonged electricity production and prompt recharging.
| Apparatus and method for spatially selective interventional neuroparticles|
An apparatus and method are provided for spatially-selective administration of actions by at least one device in the body using a transducer that is sensitive to a spatially-variant energy field imposed on the at least one device by a source external to a subject's body; and at least one component in the at least one device, wherein interaction of the transducer with the imposed spatially-variant energy field causes or enables at least one component in the at least one device to affect nearby tissues in the body.. .
| Methods for dissolution and instant neutralization of solid nitrocellulose propellants and plasticized military munitions|
Nitrocellulose propellants and plasticized military munitions, equipment, or contaminated soil are placed in a suitable container. A first option consists of adding a strong base to plasticized munitions in a container or militarization/demilitarization equipment or soil containing plasticized munitions or nitrocellulose propellant; adding an organic solvent; and then adding water to mixture.
| Vegetable oil extraction|
A method of extracting recovering oil from vegetable material in which oil bearing material is heated and subjected to sonication at least one frequency above 400 khz, removing a first yield of oil by decanting and subjecting the retained material to centrifugal separation to separate out a second yield of oil. Preferably the raw vegetable material is passed through a screw press and the obtained material is heated and subjected to the ultrasonic treatment and then allowed to settle for a predetermined period before decanting the oil layer.
| Compositions and methods for treating colon cancer|
Certain embodiments are directed to methods of treating a pathophysiological state or symptoms thereof resulting from aldose reductase-mediated signaling in a cytotoxic pathway using an aldose reductase specific inhibitor.. .
| Dual action inhibitors against histone deacetylases and 3-hydroxy-3-methylglutaryl coenzyme a reductase|
Disclosed herein are novel compounds of formula (i), and uses thereof. The compounds of formula (i) are inhibitors of histone deacetylases (hdacs) and 3-hydroxy-3-methylglutaryl coenzyme a (hmg-coa) reductase (hmgr).
| Chemiluminescence compact imaging scanner|
Systems, devices, and methods for accurately imaging chemiluminescence and other luminescence are disclosed. A compact, flat-bed scanner having a light-tight enclosure, one or more detector bars of linear charge-coupled device (ccd) or complementary metal oxide semiconductor (cmos) imaging chips, and high working numerical aperture (na) optics scans closely over a sample in one direction and then the opposite direction.
| Stable gene targets in breast cancer and use thereof for optimizing therapy|
A method for determining genes in breast cancer that are stable in copy number, expression and sequence in tumors from nearly all patients. Certain stable genes are targets of standard chemotherapy.
| Exhaust gas purification catalyst and method for producing it|
The purpose of the present invention is to provide an exhaust gas purification catalyst which can decrease a nox reduction temperature and comprises rhodium and gold. An exhaust gas purification catalyst which carries two-element microparticles each comprising rhodium and gold, said catalyst being characterized in that the rhodium and the gold are phase-separated from each other and the content ratio of the rhodium to the gold (i.e., rhodium:gold) is (30-99.9 at.
| Adductor and abductor exercise device|
An exercise device that enables a user to exercise the adductor and abductor muscles. The exercise device may include a base with at least one base channel and a slant board with at least one slant board channel.
| Polishing apparatus and method of polishing semiconductor wafer|
An aspect of the present embodiment, there is provided a polishing apparatus, including a stage configured to be placed a semiconductor wafer thereon and to be rotated with the semiconductor wafer, a first polishing unit configured to contact a polishing tape to one portion of the semiconductor wafer on the stage, a second polishing unit configured to contact to other portion of the semiconductor wafer, the other portion being different from the one portion, a feed unit configured to feeding the polishing tape, and a recovery unit configured to recovery the polishing tape.. .
| Method for polishing a semiconductor wafer|
A method for polishing at least one wafer composed of semiconductor material that has a front side and the rear side includes performing at least one first polishing step including simultaneously polishing both front and rear sides of the at least one wafer at a process temperature between an upper polishing plate and a lower polishing plate. Each of the upper polishing and lower polishing plates is covered with a polishing pad having an inner edge and an outer edge, a hardness of at least 80° shore a, a compressibility of less than 2.5%, and respective upper and lower surfaces that come into contact with the wafer being polished.
| Method for repairing white defect of liquid crystal display panel|
A method for repairing white defect of liquid crystal display panel includes: (1) providing a laser repairing platform and a liquid crystal display panel that contains a white defect to be repaired, wherein the white defect contained liquid crystal display panel comprises a substrate, a first insulation layer formed on the common wiring layer, a metal layer formed on the first insulation layer, a second insulation layer formed on the metal layer, and a transparent conductive layer formed on the second insulation layer; and (2) applying the laser repairing platform to carry out multi-spot welding on the common wiring layer, the metal layer, and the transparent conductive layer at a location corresponding to a white defect of the liquid crystal display panel so as to have the common wiring layer, the metal layer, and the transparent conductive layer electrically connected at sites corresponding to the multiple welding spots.. .
| Connector utilizing conductive polymers|
An improved electronic receptacle connector with portions thereof formed from an electrically conductive polymer is disclosed. A conductive polymer front face enables improved device aesthetics and can discharge electrostatic energy from a plug before it is mated with the connector.
| Coaxial connector plug and coaxial connector receptacle|
A coaxial connector plug and a coaxial connector receptacle that may be stably suctioned by a suction nozzle. A coaxial connector receptacle including a substantially cylindrical outer conductor and a center conductor surrounded by the outer conductor is mountable to a coaxial connector plug.
| Substrate processing apparatus, method of manufacturing semiconductor device, and non-transitory computer-readable recording medium|
Provided is a substrate processing apparatus including a reaction chamber configured to heat a substrate; a transfer chamber configured to transfer the heated substrate; a refrigerant flow path installed in the reaction chamber; a refrigerant flow path installed in the reaction chamber; a refrigerant supply unit installed in the refrigerant flow path; a refrigerant exhaust unit installed in the refrigerant flow path; a transfer chamber refrigerant supply unit installed in the transfer chamber; a transfer chamber refrigerant exhaust unit installed in the transfer chamber; a heat exchanger connected to the refrigerant exhaust pipe and the transfer chamber refrigerant exhaust unit; a turbine connected to the heat exchanger; a generator connected to the turbine; and a control unit configured to control the refrigerant supply unit and the transfer chamber refrigerant supply unit.. .
| Methods of forming a poruous insulator, and related methods of forming semiconductor device structures|
Semiconductor devices with porous insulative materials are disclosed. The porous insulative materials may include a consolidated material with voids dispersed therethrough.
| Manufacturing method of semiconductor device and semiconductor manufacturing apparatus|
A manufacturing method of a semiconductor device according to the present invention comprises cleaning a semiconductor substrate. A first chemical liquid for forming a water-repellent protection film and a second chemical liquid coating the first chemical liquid are supplied on a surface of the semiconductor substrate.
| Method of fabricating fin fet and method of fabricating device|
In fin fet fabrication, side walls of a semiconductor fin formed on a substrate have certain roughness. Using such fins having roughness may induce variations in characteristics between transistors due to their shapes or the like.
| Method for manufacturing a semiconductor device|
A method for manufacturing a semiconductor device includes forming an etch-target layer over a semiconductor substrate having a lower structure, forming a first mask pattern over the etch-target layer, forming a spacer material layer with a uniform thickness over the etch-target layer including the first mask pattern, forming a second mask pattern on an indented region of the space material layer, and etching the etch-target layer with the first mask pattern and the second mask pattern as an etch mask to form a fine pattern.. .
| Etchant and etching process|
A system and method for manufacturing semiconductor devices is provided. An embodiment comprises using an etchant to remove a portion of a substrate to form an opening with a 45° angle with a major surface of the substrate.
| Silicide formation in high-aspect ratio structures|
Embodiments of the present invention include methods of forming a silicide layer on a semiconductor substrate. In an exemplary embodiment, a metal layer may first be deposited above a semiconductor substrate using a chemical vapor deposition process with a metal amidinate precursor and then the semiconductor substrate may be annealed, causing the semiconductor substrate to react with the metal layer forming a metal-rich silicide layer on the semiconductor substrate.
| Method of forming a metal silicide layer|
A method for forming a metal silicide layer is disclosed. The method includes the steps of: forming a first metal layer with a thickness less than 10 nm on a silicon substrate; forming a second metal layer with a thickness more than 10 nm on the first metal layer; annealing the metal layers and the silicon substrate, so that a part of the second metal layer penetrates through the first metal layer, and both the part of the second metal layer penetrating through the first metal layer and a part of the first metal layer react with the silicon substrate to form the metal silicide layer, while the remaining part of the first and second metal layers form a third metal layer; and removing the third metal layer, so that the metal silicide layer can be formed in the semiconductor substrate..
| Method for manufacturing semiconductor device|
A method for manufacturing semiconductor device includes preparing a structure including a substrate, an insulating layer on the substrate and having a recess, a barrier film on the insulating layer, and a copper film on the barrier such that the copper film is filling the recess with the barrier between the insulating layer and copper film, removing the copper film down to interface with the barrier such that copper wiring is formed in the recess, etching the wiring such that surface of the wiring is recessed from surface of the insulating layer, and removing the barrier from the surface of the insulating layer such that the surface of the insulating layer is exposed. The etching includes positioning the structure removed down to the barrier in organic compound atmosphere having vacuum state, and irradiating oxygen gas cluster ion beam on the surface of the wiring to anisotropically etch the wiring..
| Method of manufacturing a semiconductor device|
A method of manufacturing a semiconductor device includes forming a plurality of conductive lines separated from one another in a first direction via a slender hole and extending in a second direction perpendicular to the first direction, forming a first insulation layer filling the slender hole between the plurality of conductive lines, forming a plurality of first isolated holes separated from one another between the plurality of conductive lines in the first direction and the second direction by patterning the first insulation layer, forming a liner layer in the first isolated holes, filling a second insulation layer having an etching selectivity with respect to the first insulation layer, in the first isolated holes on the liner layer and forming a plurality of second isolated holes between the conductive lines by removing the first insulation layer using the etching selectivity between the second insulation layer and the first insulation layer.. .
| Semiconductor constructions, methods of forming transistor gates, and methods of forming nand cell units|
Some embodiments include methods of forming charge storage transistor gates and standard fet gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. Fet and charge storage transistor gate stacks may be formed.
| Three dimensional fet devices having different device widths|
A method of manufacturing a three dimensional fet device structure includes: providing a substrate having a semiconductor layer on an insulator layer; forming three dimensional fins in the semiconductor layer; applying a masking material to a first fin while exposing a second fin; applying a hydrogen atmosphere to the substrate and exposed second fin, the hydrogen atmosphere causing the exposed second fin to reflow and change shape; removing the masking material from the first fin; and forming a gate to wrap around each of the first and second fins. The first and second fins are formed having a device width such that the first fin having a first device width and a second fin having a second device width with the first device width being different than the second device width..
| Method and system for junction termination in gan materials using conductivity modulation|
A semiconductor structure includes a gan substrate having a first surface and a second surface opposing the first surface. The gan substrate is characterized by a first conductivity type and a first dopant concentration.
| Method of laser separation of the epitaxial film or of the epitaxial film layer from the growth substrate of the epitaxial semiconductor structure (variations)|
The present invention proposes variations of the laser separation method allowing separating homoepitaxial films from the substrates made from the same crystalline material as the epitaxial film this new method of laser separation is based on using the selective doping of the substrate and epitaxial film with fine donor and acceptor impurities. In selective doping, concentration of free carries in the epitaxial film and substrate may essentially differ and this can lead to strong difference between the light absorption factors in the infrared region near the residual beams region where free carriers and phonon-plasmon interaction of the optical phonons with free carriers make an essential contribution to infrared absorption of the optical phonons.
| Methods of forming semiconductor structures including bodies of semiconductor material|
Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material.
| Method of making semiconductor device|
A method for fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, and a first region, a second region and a third region are defined thereon.
| Method for processing semiconductors using a combination of electron beam and optical lithography|
Forming an alignment mark on a semiconductor structure using an optical lithography to form a metal alignment mark on a substrate of the structure, using the formed metal alignment mark to form a first feature of a semiconductor device being formed on the substrate using optical lithography, and using the formed metal alignment mark to form a second, different feature for the semiconductor using electron beam lithography. In one embodiment, the first feature is an ohmic contact, the second feature is a schottky contact, the metal alignment mark is a refractory metal or a refractory metal compound having an atomic weight greater than 60 such as tan and the semiconductor device is a gan semiconductor device.
| Method of fabricating mos device|
Provided is a method of fabricating a mos device including the following steps. At least one gate structure is formed on a substrate, wherein the gate structure includes a gate conductive layer and a hard mask layer disposed on the gate conductive layer.
| Methods of fabricating semiconductor device using nitridation of isolation layers|
A method of forming a semiconductor device can include providing a plasma nitrided exposed top surface including an active region and an isolation region. The exposed top surface including the active region and the isolation region can be subjected to etching to form a deeper recess in the active region that in the isolation region and an unmerged epitaxial stress film can be grown in the deeper recess..
| Contact structure of semiconductor device|
A method of fabricating a semiconductor device comprises epitaxially-growing a strained material in a cavity of a substrate comprising a major surface and the cavity, the cavity being below the major surface. A lattice constant of the strained material is different from a lattice constant of the substrate.
| Finfet device and method of manufacturing same|
A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure including one or more fins disposed on the substrate.
| Self-aligned trench mosfet and method of manufacture|
A trench metal-oxide-semiconductor field effect transistor (mosfet), in accordance with one embodiment, includes a drain region, a plurality of gate regions disposed above the drain region, a plurality of gate insulator regions each disposed about a periphery of a respective one of the plurality of gate regions, a plurality of source regions disposed in recessed mesas between the plurality of gate insulator regions, a plurality of body regions disposed in recessed mesas between the plurality of gate insulator regions and between the plurality of source regions and the drain region. The mosfet also includes a plurality of body contact regions disposed in the each body region adjacent the plurality of source regions, a plurality of source/body contact spacers disposed between the plurality of gate insulator regions above the recessed mesas, a source/body contact disposed above the source/body contact spacers, and a plurality of source/body contact, plugs disposed between the source/body contact spacers and coupling the source/body contact to the plurality of body contact regions and the plurality of source regions..
| Chemical mechanical polish in the growth of semiconductor regions|
A method includes performing a first planarization step to remove portions of a semiconductor region over isolation regions. The first planarization step has a first selectivity, with the first selectivity being a ratio of a first removal rate of the semiconductor region to a second removal rate of the isolation regions.
| Electronic component, a semiconductor wafer and a method for producing an electronic component|
An electronic component includes a semiconductor substrate defined by a generally planar first face, a generally planar second face and side faces extending between the generally planar second face and the generally planar first face. The semiconductor substrate has a curved contour between the generally planar second face and the side faces..
| Method of fabricating a semiconductor device having a capping layer|
A method of semiconductor device fabrication includes forming a first dummy gate structure in a first region of a semiconductor substrate and forming a second dummy gate structure in a second region of the semiconductor substrate. A protective layer (e.g., oxide and/or silicon nitride hard mask) is formed on the second dummy gate structure.
| Method of forming a gated diode structure for eliminating rie damage from cap removal|
A method of fabricating a semiconductor structure provided with a plurality of gated-diodes having a silicided anode (p-doped region) and cathode (n-doped region) and a high-k gate stack made of non-silicided gate material, the gated-diodes being adjacent to fets, each of which having a silicided source, a silicided drain and a silicided hik gate stack. The semiconductor structure eliminates a cap removal rie in a gate first high-k metal gate flow from the region of the gated-diode.
| Method for manufacturing compound semiconductor device|
A compound semiconductor device includes: a compound semiconductor multilayer structure; a gate insulating film on the compound semiconductor multilayer structure; and a gate electrode, wherein the gate electrode includes a gate base portion on the gate insulating film and a gate umbrella portion, and a surface of the gate umbrella portion includes a schottky contact with the compound semiconductor multilayer structure.. .
| Method for manufacturing semiconductor device|
A semiconductor device includes: a semiconductor layer disposed above a substrate; an insulating film formed by oxidizing a portion of the semiconductor layer; and an electrode disposed on the insulating film, wherein the insulating film includes gallium oxide, or gallium oxide and indium oxide.. .
| Method of forming a semiconductor structure including a vertical nanowire|
A method comprises providing a semiconductor structure comprising a substrate and a nanowire above the substrate. The nanowire comprises a first semiconductor material and extends in a vertical direction of the substrate.
| Finfet device and method of manufacturing same|
A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate.
| Semiconductor device and manufacturing method thereof|
The reliability of a semiconductor device including a mosfet formed over an soi substrate is improved. A manufacturing method of the semiconductor device is simplified.
| Semiconductor device comprising a passive component of capacitors and process for fabrication|
A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside.
| Single layer bga substrate process|
The present disclosure provides semiconductor packaging techniques that form a substrate using metal and insulating materials. The substrate includes a first surface that is bonded to a semiconductor device and a second surface that is bonded to a printed circuit board.
| Method for producing a semiconductor module arrangement|
A method for producing a semiconductor module arrangement includes providing a semiconductor module and a printed circuit board. The semiconductor module has a circuit mount populated with a semiconductor chip, an adjustment device in a first relative position with respect to the circuit mount, and a plurality of electrical connections each of which has a free end.
| Semiconductor-encapsulating adhesive, semiconductor-encapsulating film-form adhesive, method for producing semiconductor device, and semiconductor device|
The present invention relates to a semiconductor-encapsulating adhesive, a semiconductor-encapsulating film-form adhesive, a method for producing a semiconductor device, and a semiconductor device. The present invention provides a semiconductor-encapsulating adhesive comprising (a) an epoxy resin, and (b) a compound formed of an organic acid reactive with an epoxy resin and a curing accelerator..
| Stacked microelectronic assembly with tsvs formed in stages and carrier above chip|
A microelectronic assembly is provided which includes a first element consisting essentially of at least one of semiconductor or inorganic dielectric material having a surface facing and attached to a major surface of a microelectronic element at which a plurality of conductive pads are exposed, the microelectronic element having active semiconductor devices therein. A first opening extends from an exposed surface of the first element towards the surface attached to the microelectronic element, and a second opening extends from the first opening to a first one of the conductive pads, wherein where the first and second openings meet, interior surfaces of the first and second openings extend at different angles relative to the major surface of the microelectronic element.
| Fabrication method of semiconductor package having electrical connecting structures|
A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability..
| Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods|
Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate.
| Semiconductor device and manufacturing method thereof|
In one embodiment, a semiconductor device includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first and second semiconductor chips are electrically connected via first bump connection parts.
| Methods and arrangements relating to semiconductor packages including multi-memory dies|
Embodiments provide a method comprising providing a multi-memory die that comprises multiple individual memory dies. Each of the individual memory dies is defined as an individual memory die within a wafer of semiconductor material during production of memory dies.
| Methods for fabricating a thin film transistor and an array substrate|
The present invention provides methods for fabricating a thin film transistor and an array substrate, which are applicable in the field of display device fabrication, and solve the problem of performing patterning process too many times during the fabrications of a thin film transistor and an array substrate. The method for fabricating a thin film transistor comprises: forming a gate layer on a substrate; forming a gate insulation layer on the substrate; forming an oxide semiconductor layer and a barrier layer and on the substrate; and forming a source-drain layer on the substrate, wherein, the step of forming the oxide semiconductor layer and the barrier layer comprises: sequentially forming an oxide semiconductor film a the barrier film; and forming the oxide semiconductor layer from the oxide semiconductor film and the barrier layer from the barrier film by performing a patterning process once..
| Method for manufacturing semiconductor device|
To reduce defects in an oxide semiconductor film in a semiconductor device. To improve electrical characteristics of and reliability in the semiconductor device including an oxide semiconductor film.
| Avalanche photodiodes and methods of fabricating the same|
Provided are an avalanche photodiode and a method of fabricating the same. The method of fabricating the avalanche photodiode includes sequentially forming a compound semiconductor absorption layer, a compound semiconductor grading layer, a charge sheet layer, a compound semiconductor amplification layer, a selective wet etch layer, and a p-type conductive layer on an n-type substrate through a metal organic chemical vapor deposition process..
| Methods of growing heteroepitaxial single crystal or large grained semiconductor films on glass substrates and devices thereon|
A method is disclosed for making semiconductor films from a eutectic alloy comprising a metal and a semiconductor. Through heterogeneous nucleation said film is deposited at a deposition temperature on relatively inexpensive buffered substrates, such as glass.
| Light emitting diode and method for fabricating the same|
The disclosed light emitting diode includes a substrate provided, at a surface thereof, with protrusions, a buffer layer formed over the entirety of the surface of the substrate, a first semiconductor layer formed over the buffer layer, an active layer formed on a portion of the first semiconductor layer, a second semiconductor layer formed over the active layer, a first electrode pad formed on another portion of the first semiconductor layer, except for the portion where the active layer is formed, and a second electrode pad formed on the second semiconductor layer. Each protrusion has a side surface inclined from the surface of the substrate at a first angle, and another side surface inclined from the surface of the substrate at a second angle different from the first angle..
| Semiconductor light emitting device and method of manufacturing the same|
There are provided a semiconductor light emitting device and a method of manufacturing the same. A method of manufacturing a plurality of light emitting nanostructures of a semiconductor light emitting device includes: forming a plurality of first conductivity type semiconductor cores on a first type semiconductor seed layer, each first conductivity type semiconductor core formed through an opening in an insulating film; forming an active layer on each first conductivity type semiconductor core; forming, using a mask pattern, a second conductivity type semiconductor layer on each active layer to cover the active layer, to form a plurality of light emitting nanostructures; and forming an electrode on the plurality of light emitting nanostructures..
| Optoelectronic semiconductor device and the manufacturing method thereof|
The present application provides a method of manufacturing an optoelectronic semiconductor device, comprising the steps of: providing a substrate; forming an optoelectronic system on the substrate; forming a barrier layer on the optoelectronic system; forming an electrode on the barrier layer; and annealing the optoelectronic semiconductor device; wherein the optoelectronic semiconductor device has a first forward voltage before the annealing step and has a second forward voltage after the annealing step, and a difference between the second forward voltage and the first forward voltage is smaller than 0.2 volt.. .
| Semiconductor test structures|
A method performed using a resistive device, where the resistive device includes a substrate with an active region separated from a gate electrode by a dielectric and electrical contacts along a longest dimension of the gate electrode, the method comprising, performing one or more processes to form the resistive device, measuring a resistance between the electrical contacts, and correlating the measured resistance with a variation in one or more of the processes.. .
| Semiconductor device manufacturing method|
To improve the performance of a semiconductor device, a semiconductor device manufacturing method includes an exposing process of performing pattern exposure of a resist film formed on a substrate by using euv light reflected from a front surface of an euv mask as a reflective mask. In this exposing process, the resist film is subjected to pattern exposure by repeating a process of irradiating the resist film with the euv light by changing a focal position of the euv light with which the resist film is irradiated, along a film thickness direction of the resist film.
| Etchant and etching process|
A system and method of etching a semiconductor device are provided. Etching solution is sampled and analyzed by a monitoring unit to determine a concentration of components within the etching solution, such as an oxidant concentration.
| Method of manufacturing and testing a chip package|
A method of producing and testing a chip package is described. The chip package to be produced includes a semiconductor chip containing an integrated circuit and a reinforcing structure attached to the semiconductor chip.
| Heat treatment apparatus and heat treatment method for heating substrate by irradiating substrate with flash of light|
A flash heating part in a heat treatment apparatus includes 30 built-in flash lamps, and irradiates a semiconductor wafer held by a holder in a chamber with a flash of light. Thirty switching elements are provided in a one-to-one correspondence with the 30 flash lamps.
| Semiconductor ferroelectric device, manufacturing method for the same, and electronic device|
A manufacturing method for a semiconductor device, the method including forming a thin film transistor by forming a polysilicon thin film on an insulating substrate, forming a gate electrode via a gate insulating film, and forming source/drain regions and a channel region by ion implantation in the polysilicon thin film by using the gate electrode as a mask, forming an interconnection layer on an interlayer dielectric film covering this thin film transistor and forming a first contact to be connected to the thin film transistor through the interlayer dielectric film, forming a silicon hydronitride film on the interlayer dielectric film so as to cover the interconnection layer, forming a lower electrode on this silicon hydronitride film and forming a second contact to be connected to the interconnection layer through the silicon hydronitride film, and forming a ferroelectric layer on the lower electrode.. .
| Transformer signal coupling for flip-chip integration|
Methods for transformer signal coupling and impedance matching for flip-chip circuit assemblies are presented. In one embodiment, a method for providing an inductive coupling between dies may include fabricating a first inductor on a first die using a passive process, fabricating a second inductor on a second die using a semiconductor process, and assembling each die so the first and second inductor are configured as a transformer.
| Stable indium-containing semiconductor nanocrystals|
Nanocrystals having an indium-based core and methods for making them and using them to construct core-shell nanocrystals are described. These core-shell nanocrystals are highly stable and provide higher quantum yields than known nanocrystals of similar composition, and they provide special advantages for certain applications because of their small size..
| Method for viscosity reduction in co-fermentation ethanol processes|
The present disclosure provides methods and compositions for reducing the viscosity of biomass process streams in an ethanol production process. The method comprises adding cellulase enzymes to a biomass feedstock that is fermented to produce ethanol, generating whole stillage and thin stillage streams from the post-fermentation biomass, and adding an additional enzyme or enzyme cocktail that reduces the viscosity of the whole stillage stream, thin stillage stream, concentrated thin stillage stream, and/or the syrup stream generated by evaporating the thin stillage..
| Genes encoding key catalyzing mechanisms for ethanol production from syngas fermentation|
Gene sequences of key acetogenic clostridial species were sequenced and isolated. Genes of interest were identified, and functionality was established.