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Duc patents



      

This page is updated frequently with new Duc-related patent applications.




Date/App# patent app List of recent Duc-related patents
07/14/16
20160205763 
 Wiring substrate and manufacturing method thereof patent thumbnailWiring substrate and manufacturing method thereof
Disclosed is wiring substrate, the wiring substrate including a substrate having a high thermal conductive layer, in which at least one of a front surface and a rear surface of the substrate is a mounting surface for a variety of components; a window section formed in the substrate; and a connection terminal extended from an inside surface portion of the window section and bending in a direction perpendicular to a surface of the substrate.. .
Yazaki Corporation


07/14/16
20160205737 
 Self-identifying solid-state transducer modules and associated systems and methods patent thumbnailSelf-identifying solid-state transducer modules and associated systems and methods
Self-identifying solid-state transducer (sst) modules and associated systems and methods are disclosed herein. In several embodiments, for example, an sst system can include a driver and at least one sst module electrically coupled to the driver.
Micron Technology, Inc.


07/14/16
20160205727 
 Microfluidic-based apparatus and method vaporization of liquids using magnetic induction patent thumbnailMicrofluidic-based apparatus and method vaporization of liquids using magnetic induction
Methods and apparatus for vaporizing liquid into the surrounding environment, including directing liquid from a liquid source to a vaporization port where the vaporization port has lateral dimensions varying from 10 um to 300 um, by magnetically inductive heating a liquid in the vaporization port with an at least one inductive heating element located in thermal communication to the vaporization port, and releasing vaporized liquid from the vaporization port into the surrounding environment so that fluid is transported through the depth of the structure.. .
Numerical Design, Inc.


07/14/16
20160205725 
 System and  monitoring temperatures of and controlling multiplexed heater array patent thumbnailSystem and monitoring temperatures of and controlling multiplexed heater array
A system for measuring temperatures of and controlling a multi-zone heating plate in a substrate support assembly used to support a semiconductor substrate in a semiconductor processing includes a current measurement device and switching arrangements. A first switching arrangement connects power return lines selectively to an electrical ground, a voltage supply or an electrically isolated terminal, independent of the other power return lines.
Lam Research Corporation


07/14/16
20160205538 
 Apparatus and  managing subscriber profile in wireless communication system patent thumbnailApparatus and managing subscriber profile in wireless communication system
The present disclosure relates to a communication method and system for converging a 5th-generation (5g) communication system for supporting higher data rates beyond a 4th-generation (4g) system with a technology for internet of things (iot). The present disclosure may be applied to intelligent services based on the 5g communication technology and the iot-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services.
Samsung Electronics Co., Ltd.


07/14/16
20160205484 
 Magnet arrangement for bone conduction hearing implant patent thumbnailMagnet arrangement for bone conduction hearing implant
An implantable magnetic transducer arrangement is described for a hearing implant in a recipient patient. An implant housing hermetically encapsulates an interior housing volume and is fixedly attached to skull bone beneath the skin of the patient.
Vibrant Med-el Hearing Technology Gmbh


07/14/16
20160205474 
 Method for operating an arrangement of sound transducers according to the wave field synthesis principle patent thumbnailMethod for operating an arrangement of sound transducers according to the wave field synthesis principle
A method and a device for operating an arrangement of sound transducers according to the wave-field synthesis principle. In order to supply an extended audience region with the same signal, the same signal content is generated by at least two virtual sound sources, which are arranged such that the wavefronts thereof are directed only onto a part audience area, rather than generating only a single beam extending over the entire audience area.
Advanced Acoustic Sf Gmbh


07/14/16
20160205470 
 Condenser microphone unit and condenser microphone patent thumbnailCondenser microphone unit and condenser microphone
A condenser microphone unit and a condenser microphone are provided that can prevent intrusion of rf current into the condenser microphone unit. The condenser microphone unit includes an electroacoustic transducer 30 including a diaphragm 32 and a fixed electrode 33 that constitute a capacitor; a printed circuit board 50 including an impedance converter 40 connected to the electroacoustic transducer 30; and a unit case 20 having bottomed tubular shape and an opening, the electroacoustic transducer 30 and the printed circuit board 50 being installed in the interior of the unit case 20, a hole being formed on the printed circuit board 50 across the thickness of the printed circuit board 50, a first filter element l being inserted into the hole 50h, the first filter element l being connected to the impedance converter 40..
Kabushiki Kaisha Audio-technica


07/14/16
20160205465 
 Speaker back cavity patent thumbnailSpeaker back cavity
An apparatus including a sound transducer; and a housing having the sound transducer connected thereto. The housing forms a substantially sealed air space back cavity acoustically coupled to the sound transducer.
Nokia Corporation


07/14/16
20160205441 
 Transmission method, reception method, transmission apparatus, and reception apparatus patent thumbnailTransmission method, reception method, transmission apparatus, and reception apparatus
A transmission method includes: generating one or more transfer frames that each store one or more streams used for content transfer; and transmitting the one or more generated frames through broadcast, each of the one or more streams storing one or more second transfer units, each of the one or more second transfer units storing one or more first transfer units, and each of the one or more first transfer units storing one or more internet protocol (ip) packets. In at least one stream among the one or more streams, each of the first transfer units positioned at a head contains reference clock information indicating time used for reproduction of the content..
Panasonic Intellectual Property Corporation Of America


07/14/16
20160205424 

Methods and local channel insertion in an all-digital content distribution network


Methods and apparatus for inserting local content of interest in an all digital content delivery network. In one embodiment, the content delivery network comprises a cable television or satellite network, and an rf channel thereof is separated or isolated from an incoming multiplex of all-digital content transmission.
Time Warner Cable Enterprises Llc


07/14/16
20160205377 

Real image camcorder, glass-free 3d display and processes for capturing and reproducing 3d media using parallel ray filters


Parallel rays capture by a real image camcorder and capture emission by a real image television are made by parallel rays filter formed by multiple leveled liquid crystals with windows to filter distinct parallel rays in a field of vision. The image processing with image parameters is electronically carried out or by means of a device that displaces said image and controls a real image projection distance forwards or backwards a real image television.

07/14/16
20160205195 

Method, apparatus, computer program and computer program product for transmitting data for use in a vehicle


A method is provided for transmitting data for use in a vehicle. The method involves a user request for the transmission and reproduction of desired data from a first source by way of a mobile radio link being taken as a basis for ascertaining whether the desired data are also provided by a second source independently of the mobile radio link.
Bayerische Motoren Werke Aktiengesellschaft


07/14/16
20160205103 

Method for controlling contents and electronic device thereof


The present disclosure relates to a sensor network, machine type communication (mtc), machine-to-machine (m2m) communication, and technology for internet of things (iot). The present disclosure may be applied to intelligent services based on the above technologies, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services.
Samsung Electronics Co., Ltd.


07/14/16
20160204872 

Method and generating optical polar return-to-zero amplitude modulation signal using reflective semiconductor optical amplifier and wavelength-division-multiplexed passive optical network system using the same


The present invention can operate a reflective semiconductor optical amplifier at ultrahigh speed using a polar return-to-zero (rz) modulation method, and operate a reflective semiconductor optical amplifier (rsoa) whose modulation bandwidth is limited at ultrahigh speed by generating signals vertically symmetrical using a newly suggested polar rz signal generator when generating an amplitude modulation signal at a transmission end. The present invention can overcome the problem that a modulation speed cannot be increased to 10 gb/s or above due to signal distortion by inter-symbol-interference when generating an ultrahigh speed amplitude modulation signal using an rsoa of low price having a very narrow modulation bandwidth in an rsoa-based optical network.
Korea Advanced Institute Of Science And Technology


07/14/16
20160204863 

Fiber-optic communication device and fiber-optic communication system


A fiber-optic communication device includes a modulator, a combiner and an electronic-to-optical transducer. The modulator is to modulate a number (n) of radio-frequency carriers respectively with a number (m) of digital stream signals respectively into a number (n) of modulated signals having different central frequencies.
Transystem Inc.


07/14/16
20160204823 

10gbe e-band radio with 8psk modulation


A millimeter wave radio link in which the transceivers have most of its components fabricated on a single chip or chipset of a small number of semiconductor chips. The chip or chipsets when mass produced is expected to make the price of millimeter wave radios comparable to many of the lower-priced microwave radios available today from low-cost foreign suppliers.
Trex Enterprises Corporation


07/14/16
20160204792 

Semiconductor device and semiconductor device operating method


A semiconductor device includes an analog-digital converter circuit. The analog-digital converter circuit includes a delay cell array that includes n-number (n is a natural number of 2 or more) of serially-coupled delay cells, receives a reference clock signal, and utilizes an analog input signal as the power supply voltage for delay cells in each stage, and an encoder that encodes the output signal of the delay cells in each stage of the delay cell array.
Renesas Electronics Corporation


07/14/16
20160204778 

Transmission channel for ultrasound applications


A transmission channel transmits high-voltage pulses and receives echos of the high-voltage pulses. The transmission channel includes a current generator circuit, which generates current-integrator drive currents.
Stmicroelectronics S.r.l.


07/14/16
20160204773 

System and anti-ambipolar heterojunctions from solution-processed semiconductors


Van der waals heterojunctions are extended to semiconducting p-type single-walled carbon nanotube (s-swcnt) and n-type film that can be solution-processed with high spatial uniformity at the wafer scale. The resulting large-area, low-voltage p-n heterojunctions can exhibit anti-ambipolar transfer characteristics with high on/off ratios.
Northwestern University


07/14/16
20160204762 

Acoustic wave device


The present invention relates to an acoustic wave device including: a substrate; an idt arranged on the substrate; a connection electrode arranged on the substrate and electrically connected to the idt; a side wall formed outside the idt to create a cavity including the idt on the substrate; a cover formed on a top of the side wall; a connection terminal penetrating the side wall or the cover or formed along an inner or outer peripheral surface of the side wall, and electrically connected to the connection electrode; and a conductive layer formed on a top of the cover not to be overlapped with the connection terminal, in which an area of the conductive layer is less than 50% of an area of the cover.. .
Wisol Co., Ltd.


07/14/16
20160204758 

Tunable diplexers in three-dimensional (3d) integrated circuits (ic) (3dic) and related components and methods


Tunable diplexers in three-dimensional (3d) integrated circuits (ic) (3dic) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer.
Qualcomm Incorporated


07/14/16
20160204741 

Semiconductor device


Disclosed is a semiconductor device. The semiconductor device includes a functional circuit having a resistor formed by a plurality of polysilicon resistors, and in which the property of the functional circuit can be adjusted by trimming the resistor, and in which the polysilicon resistors are coupled in series or in parallel to each other and arranged in a direction perpendicular to one side of the semiconductor device..
Renesas Electronics Corporation


07/14/16
20160204738 

System and dynamically biasing oscillators for optimum phase noise


Systems and methods for biasing frequency oscillators to minimize phase noise are disclosed. The system may comprise a tank circuit having an inductor, at least a first coupling capacitor and a second coupling capacitor.
Qualcomm Incorporated


07/14/16
20160204717 

Piezoelectirc energy harvesting system with frequency mismatch tolerance


An impedance matching circuit is provided for use with a piezotransducer that includes a parasitic capacitor comprising: an inductor coupled in parallel with the parasitic capacitor; a peak and valley detection circuit configured to detect output voltage waveform peaks and valleys; a first switch circuit configured to bias flip the output voltage waveform at a selectable first time relative to a detected peak and at a selectable first time relative to a detected valley; a second switch circuit configured to couple the inductor to the energy storage circuit at a selectable second time following each output voltage bias flip; an energy monitoring circuit to provide an indication of energy flow from the inductor to the energy storage circuit following each output voltage bias flip; and a maximum power point tracking (mppt) circuit configured to select the first time and the second time based at least in part upon the indicated energy flow.. .

07/14/16
20160204694 

Power supply device


According to one embodiment of the present invention, when a power supply device having first and second amplification units which share an energy storage element is used, it is possible to reduce voltage stress of a semiconductor device and to consistently maintain output voltage outputted to the first and second amplification units while individually adjusting the amplification rates of the first and second amplification units.. .
Lg Innotek Co., Ltd.


07/14/16
20160204675 

Power tool and circuit board


A power tool and a printed circuit board for use therewith. The power tool has an electric motor and a power source.
Nanjing Chervon Industry Co., Ltd.


07/14/16
20160204653 

Semiconductor device being capable of improving the breakdown characteristics


A semiconductor device, wherein the semiconductor device includes a high-voltage supply circuit suitable for supplying a high voltage; a discharge circuit suitable for discharging the high voltage; and an auxiliary-voltage supply circuit suitable for supplying a first auxiliary voltage, which varies according to an operation state of the high-voltage supply circuit, to a reference node of the discharge circuit.. .
Sk Hynix Inc.


07/14/16
20160204648 

In-vehicle charger


A si diode is used as a rectifying diode on a transformer secondary side of an isolated dc/dc converter, and a high-voltage schottky barrier diode made of a wide bandgap semiconductor is used as a free-wheeling diode arranged between a rectifier circuit and a smoothing reactor. Thus, there may be provided an in-vehicle charger capable of suppressing a diode recovery surge voltage with a circuit configuration that is simpler and suppressed in cost increase as compared to a case where a related-art synchronous rectifier circuit system is employed..
Mitsubishi Electric Corporation


07/14/16
20160204596 

Dc circuit breaker device


In a dc circuit breaker device, first and second semiconductor switches are connected in series on a main circuit line such that current-carrying directions of the switches are opposite to each other. A first diode is connected in anti-parallel with the first semiconductor switch, and a second diode is connected in anti-parallel with the second semiconductor switch.
Mitsubishi Electric Corporation


07/14/16
20160204581 

Ion generation apparatus and electrical equipment


An ion generation apparatus that can facilitate the separation of adhering materials from a discharge electrode and efficiently generate ions includes an induction electrode, and a discharge electrode for generating ions between the discharge electrode and the induction electrode. The discharge electrode has a plurality of filament-like conductors, and a joining portion to tie the bottoms of the conductors together.
Sharp Kabushiki Kaisha


07/14/16
20160204578 

Ring-modulated laser


An optical source is described. This optical source includes a semiconductor optical amplifier, with a semiconductor other than silicon, which provides a gain medium.
Oracle International Corporation


07/14/16
20160204572 

Energy integrating device for split semiconductor laser diodes


An energy integrating device for split semiconductor laser diodes includes: an installing holder, wherein the installing holder has a disc structure with a positioning hole at a center thereof, four module bases for mounting laser modules are symmetrically provided at one side of the disc structure, and the laser modules are embedded inside the module bases; a printed circuit board, connected to the laser modules through sleeves, is mounted at one side of the module bases, and a wire and a plug are mounted on the printed circuit board for connecting a power source; the laser modules are adjusted and positioned through fastening screws, and laser beams thereof are emitted through surface holes of the installing holder with the disc structure; the laser beams from the laser modules are focused onto one laser spot through a positive lens.. .
Elite Optoelectronucs Co., Ltd.


07/14/16
20160204502 

Radio-frequency transparent window


A patch for a device in an electronic housing including an aluminum layer having a threshold thickness, a non-conductive layer on a first side of the aluminum layer, and a radio-frequency (rf) transparent layer on a second side of the aluminum layer is provided. A method for manufacturing an antenna window including a patch as above is also provided, the method including determining a thickness of the aluminum layer adjacent to an anodized aluminum layer.
Apple Inc.


07/14/16
20160204494 

3d multilayer high frequency signal line


In one example, a manufacturing method is disclosed. There is being dispensed a first dielectric layer on a ground layer.
Microsoft Technology Licensing, Llc


07/14/16
20160204368 

Solar cell and solar cell module


According to one embodiment, a solar cell includes a substrate, a stacked body, and an optical layer. The substrate is light-transmissive.
Kabushiki Kaisha Toshiba


07/14/16
20160204351 

Light emitting diode


The disclosure relates to a light emitting diode. The light emitting diode includes a first semiconductor layer, an active layer, and a second semiconductor layer, a first electrode, a second electrode and a nanotube film.
Hon Hai Precision Industry Co., Ltd.


07/14/16
20160204350 

Polymyeric organic semiconductor compositions


The present invention relates to organic copolymers and organic semiconducting compositions comprising these materials, including layers and devices comprising such organic semiconductor compositions. The invention is also concerned with methods of preparing such organic semiconductor compositions and layers and uses thereof.
Smartkem Limited


07/14/16
20160204344 

Structure and formation memory device


Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first electrode over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


07/14/16
20160204327 

Compound semiconductors and their applications


Disclosed is a new compound semiconductor material which may be used for thermoelectric material or the like, and its applications. The compound semiconductor may be represented by chemical formula 1 below: chemical formula 1 bi1-xmxcu1-wtwoa-yq1ytebsez where, in chemical formula 1, m is at least one selected from the group consisting of ba, sr, ca, mg, cs, k, na, cd, hg, sn, pb, mn, ga, in, tl, as and sb, q1 is at least one selected from the group consisting of s, se, as and sb, t is at least one selected from the group consisting of transition metal elements, 0≦x<1, 0<w<1, 0.2<a<1.5, 0≦y<1.5, 0≦b<1.5 and 0≦z<1.5..
Lg Chem, Ltd.


07/14/16
20160204325 

Thermoelectric element, thermoelectric module comprising same, and heat conversion apparatus


The embodiments of the present invention relate to a thermoelectric element and a thermoelectric module, and may provide a thermoelectric element and a thermoelectric module having notably improved cooling capacity (qc) and rate of temperature change (at) to be provided by constructing the thermoelectric element by stacking unit members, each of which comprises a semiconductor layer on a substrate, thereby lowering thermal conductivity and raising electric conductivity.. .
Lg Innotek Co., Ltd.


07/14/16
20160204324 

Thermal management in electronic devices with yielding substrates


In accordance with certain embodiments, heat-dissipating elements are integrated with semiconductor dies and substrates in order to facilitate heat dissipation therefrom during operation.. .

07/14/16
20160204316 

Semiconductor optoelectronic device with an insulative protection layer and the manufacturing method thereof


The present disclosure is to provide an optoelectronic device. The optoelectronic device comprises a heat dispersion substrate; an insulative protection layer on the heat dispersion substrate, wherein the insulative protection layer comprises alingan series material; and an optoelectronic unit comprising an epitaxial structure comprising multiple layers on the insulative protection layer, wherein at least one layer of the epitaxial structure comprises iii-v group material devoid of nitride..
Epistar Corporation


07/14/16
20160204315 

Passivation for a semiconductor light emitting device


In embodiments of the invention, a passivation layer is disposed over a side of a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A material configured to adhere to an underfill is disposed over an etched surface of the semiconductor structure..
Lumileds Llc


07/14/16
20160204311 

Lighting device with plural fluorescent materials


Provided is a light-emitting device that has a high emission efficiency, excellent stability and temperature properties, and that generates light having a high color rendering property sufficient for practical use. This semiconductor light-emitting device comprises a semiconductor light-emitting element that emits blue light, a green phosphor that absorbs the blue light and emits green light, and an orange phosphor that absorbs the blue light and emits orange light, and is characterized in that the orange phosphor is an eu-activated α-sialon phosphor having an emission spectrum peak wavelength within a range of 595 to 620 nm..
Sharp Kabushiki Kaisha


07/14/16
20160204310 

Light-emitting device and the manufacturing method thereof


A method of manufacturing a light-emitting device comprises the steps of: providing a substrate; forming a mask block contacting the substrate and exposing a portion of the substrate; implanting an ion into the portion of the substrate to form an ion implantation region; and forming a semiconductor stack on the substrate such that multiple cavities are formed between the semiconductor stack and the ion implantation region; wherein the mask block comprises a material made of metal or oxide.. .
Epistar Corporation


07/14/16
20160204309 

Semiconductor light-emitting element and manufacturing the same


A step of forming, on a surface of a semiconductor structure layer, easily-to-be-etched portions arranged on the basis of crystal directions on the surface of the semiconductor structure layer and a step of subjecting the surface of the semiconductor structure layer to wet etching to form an uneven structure surface including a plurality of protrusions derived from a crystal structure of the semiconductor structure layer on the surface of the semiconductor structure layer are included.. .
Stanley Electric Co., Ltd.


07/14/16
20160204306 

Hybrid heterostructure light emitting devices


Light-emitting devices having a multiple quantum well (mqw) pin diode structure and methods of making and using the devices are provided. The devices are composed of multilayered semiconductor heterostructures.
Wisconsin Alumni Research Foundation


07/14/16
20160204305 

Semiconductor light emitting device and fabricating the same


A method of manufacturing a semiconductor light-emitting device, comprises the steps of providing a first substrate; providing multiple epitaxial units on the first substrate, wherein the plurality of epitaxial units comprises: multiple first epitaxial units, wherein each of the first epitaxial units has a first geometric shape and a first area; and multiple second epitaxial units, wherein each of the second epitaxial units has a second geometric shape and a second area; providing a second substrate with a surface; transferring the multiple second epitaxial units to the surface of the second substrate; and dividing the first substrate to form multiple first semiconductor light-emitting devices, wherein each of the first semiconductor light-emitting devices has the first epitaxial unit; wherein the first geometric shape is different from the second geometric shape, or the first area is different from the second area.. .
Epistar Corporation


07/14/16
20160204303 

Using an active solder to couple a metallic article to a photovoltaic cell


Methods include providing a metallic article that is configured to serve as an electrical conduit within a photovoltaic cell. The processes further include providing a semiconductor substrate that includes a coating at a top surface of the semiconductor substrate, where the coating is a dielectric anti-reflective coating, a transparent conductive oxide or an amorphous silicon.
Gtat Corporation


07/14/16
20160204300 

Solar cell and manufacturing the same


A solar cell and a method of manufacturing the same are disclosed. The solar cell includes a substrate of a first conductive type; an emitter layer of a second conductive type opposite the first conductive type on the substrate; a first electrode electrically connected to the emitter layer; a passivation layer on the substrate; a second electrode conductive layer on the passivation layer, the second electrode conductive layer including at least one second electrode electrically connected to the substrate through the passivation layer; and a second electrode current collector electrically connected to the second electrode conductive layer..
Lg Electronics Inc.


07/14/16
20160204291 

Solar cell having quantum well structure and manufacturing same


The present invention provides a practical solar cell having a multiple quantum well structure and a method for manufacturing the same, and the heterostructure solar cell is capable of reducing the transmission loss of solar light and the short wavelength loss of solar light by inserting a multi-layer quantum well structure between p- and n-type semiconductors, thereby obtaining a high-efficiency solar cell which can overcome the limitations of theoretical conversion efficiency and reducing manufacturing costs.. .
Cheongju University Industry & Academy Cooperation Foundation


07/14/16
20160204283 

Photovoltaic cell and fabricating the same


A photovoltaic cell device is disclosed. The device comprises: an active region having a plurality of spaced-apart elongated nanostructures aligned vertically with respect to an electrically conductive substrate, wherein each elongated nanostructure has at least one p-n junction characterized by a bandgap within the electromagnetic spectrum, and is coated by an electrically conductive layer being electrically isolated from the substrate..
Ramot At Tel-aviv University Ltd.


07/14/16
20160204282 

Multi-gate and complementary varactors in finfet process


A varactor includes at least one semiconductor fin, a first gate, and a second gate physically disconnected from the first gate. The first gate and the second gate form a first finfet and a second finfet, respectively, with the at least one semiconductor fin.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/14/16
20160204281 

Energy storage device with large charge separation


High density energy storage in semiconductor devices is provided. There are two main aspects of the present approach.
The Board Of Trustees Of The Leland Stanford Junior University


07/14/16
20160204280 

Lateral charge storage region formation for semiconductor wordline


Devices and methods for forming charge storage regions are disclosed. In one embodiment, a semiconductor device comprises a semiconductor layer having a trench, charge storage layers formed at both side surfaces of the trench, a wordline buried in the trench in contact with the charge storage layers, and source-drain regions formed in the semiconductor layer at both sides of the trench..
Cypress Semiconductor Corporation


07/14/16
20160204278 

Self-aligned metal oxide tft with reduced number of masks and with reduced power consumption


A method of fabricating mo tfts includes positioning opaque gate metal on a transparent substrate to define a gate area. Depositing gate dielectric material overlying the gate metal and a surrounding area, and depositing metal oxide semiconductor material thereon.

07/14/16
20160204277 

Semiconductor device including nanowire transistor


A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel region, a gate that surrounds at least a part of the channel region, and a gate dielectric film that is disposed between the channel region and the gate. A source/drain region that contacts one end of the at least one nanowire is formed in a semiconductor layer that extends from the substrate to the one end of the at least one nanowire.
Samsung Electronics Co., Ltd.


07/14/16
20160204275 

Semiconductor device


It is an object of the present invention to connect a wiring, an electrode, or the like formed with two incompatible films (an ito film and an aluminum film) without increasing the cross-sectional area of the wiring and to achieve lower power consumption even when the screen size becomes larger. The present invention provides a two-layer structure including an upper layer and a lower layer having a larger width than the upper layer.
Semiconductor Energy Laboratory Co., Ltd.


07/14/16
20160204271 

Semiconductor device and manufacturing the same


To manufacture a highly reliable semiconductor device by giving stable electric characteristics to a transistor. An oxide semiconductor film is deposited by a sputtering method with the use of a polycrystalline sputtering target.
Semiconductor Energy Laboratory Co., Ltd.


07/14/16
20160204270 

Semiconductor device and manufacturing method thereof


A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased..
Semiconductor Energy Laboratory Co., Ltd.


07/14/16
20160204269 

Semiconductor device and manufacturing the same


It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer.
Semiconductor Energy Laboratory Co., Ltd.


07/14/16
20160204268 

Method for manufacturing semiconductor device


A semiconductor device which is miniaturized while favorable characteristics thereof are maintained is provided. In addition, the miniaturized semiconductor device is provided with a high yield.
Semiconductor Energy Laboratory Co., Ltd.


07/14/16
20160204267 

Thin film transistor and manufacturing the same


Provided is a thin film transistor (tft) that includes a first electrode on a substrate separated from a second electrode, an oxide semiconductor pattern on the second electrode including a channel region, a third electrode on the oxide semiconductor pattern, a first insulating layer on the substrate including the third electrode including first contact holes exposing a part of the first electrode, a part of the second electrode, and a part of the third electrode, a gate electrode on the first insulating layer and corresponding to a part of the oxide semiconductor pattern, a second insulating layer on the substrate including the gate electrode including a second contact hole corresponding to the first contact hole that exposes a part of the second electrode, and a pixel electrode on the second insulating layer electrically connected to the second electrode through the first contact hole and the second contact hole.. .
Samsung Display Co., Ltd.


07/14/16
20160204266 

Thin film transistor array panel and manufacturing method thereof


A thin film transistor array panel and method of manufacturing. The thin film transistor array panel includes a substrate, a first gate electrode positioned on the substrate, a gate insulating layer positioned on the first gate, an oxide semiconductor positioned on the gate insulating layer and including a channel region, at least one etch stopper positioned on the oxide semiconductor, a second gate electrode, a source electrode and a drain electrode positioned on the at least one etch stopper, a passivation layer formed on the second gate electrode, the source electrode and the drain electrode; and a pixel electrode positioned on the passivation layer and connected to the drain electrode, in which the oxide semiconductor includes an n+ region formed in a portion exposed through the at least one etch stopper..
Samsung Display Co., Ltd.


07/14/16
20160204264 

Semiconductor devices having gate structures with skirt regions


Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes an active fin protruding upwardly from a substrate and extending in a first direction and a gate structure extending in a second direction intersecting to cross the active fin, where a first width of a lower portion of the gate structure that contacts the active fin is greater than a second width of the lower portion of the gate structure that is spaced apart from the active fin..

07/14/16
20160204263 

Improved cladding layer epitaxy via template engineering for heterogeneous integration on silicon


An apparatus including a semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the semiconductor body including a first material including a first band gap; and a plurality of nanowires including a second material including a second band gap different than the first band gap, the plurality of nanowires disposed in separate planes extending through the first material so that the first material surrounds each of the plurality of nanowires; and a gate stack disposed on the channel region. A method including forming a plurality of nanowires in separate planes above a substrate, each of the plurality of nanowires including a material including a first band gap; individually forming a cladding material around each of the plurality of nanowires, the cladding material including a second band gap; coalescing the cladding material; and disposing a gate stack on the cladding material..
Intel Corporation


07/14/16
20160204261 

Channel cladding last process flow for forming a channel region on a finfet device having a reduced size fin in the channel region


One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming a sacrificial gate structure around a portion of an initial fin, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure and removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove portions of the initial fin so as to thereby define a reduced size fin and recesses under the sidewall spacers, forming at least one replacement epi semiconductor cladding material around the reduced size fin in the replacement gate cavity and in the recesses under the sidewall spacers, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.. .
Globalfoundries Inc.


07/14/16
20160204260 

Structure and formation finfet device


Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a fin channel structure over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


07/14/16
20160204259 

High efficiency finfet diode


Disclosed are methods to form a finfet diode of high efficiency, designed to resolve the degradation problem with a conventional finfet diode arising from reduced active area, and a method of fabrication. The finfet diode has a doped substrate, two spaced-apart groups of semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/14/16
20160204258 

Semiconductor device and manufacturing the same


To improve performance of a semiconductor device. Over a semiconductor substrate, a gate electrode is formed via a first insulating film for a gate insulating film, and a second insulating film extends from over a side wall of the gate electrode to over the semiconductor substrate.
Renesas Electronics Corporation


07/14/16
20160204257 

Self-aligned contact process enabled by low temperature


Self-aligned contacts of a semiconductor device are fabricated by forming a metal gate structure on a portion of a semiconductor layer of a substrate. The metal gate structure contacts inner sidewalls of a gate spacer.
International Business Machines Corporation


07/14/16
20160204255 

Method of making a finfet, and finfet formed by the method


A method includes forming first and second fins of a finfet extending above a semiconductor substrate, with a shallow trench isolation (sti) region in between, and a distance between a top surface of the sti region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the sti region.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/14/16
20160204254 

Semiconductor device


A semiconductor device includes a hetero junction structure including an electron transport layer of gan and an electron supply layer of inx1aly1ga1-x1-y1n (0≦x1≦1, 0≦y1≦1, 0≦1−x1−y1<1), source and drain electrodes provided above an surface of the electron supply layer, a p-type layer of inx2aly2ga1-x2-y2n (0≦x2≦1, 0≦y2≦1, 0≦1−x2−y2≦1) provided above the surface of the electron supply layer and between the source electrode and the drain electrode, a gate electrode provided to be electrical contact with the p-type layer, and an insulation layer covering at least one of the surface of the electron supply layer exposed between the source electrode and the p-type layer and the surface of the electron supply layer exposed between the drain electrode and the p-type layer, wherein positive charges are fixed in at least a part of the insulation layer.. .
Toyota Jidosha Kabushiki Kaisha


07/14/16
20160204253 

Iii-v mosfet with strained channel and semi-insulating bottom barrier


Embodiments include a method for fabricating a semiconductor device and the resulting structure comprising forming a semi-insulating bottom barrier on a semiconductor substrate. A channel is formed on the bottom barrier.
International Business Machines Corporation


07/14/16
20160204252 

Semiconductor device


A plurality of unit misfet elements connected in parallel with each other to make up a power misfet are formed in an ldmosfet forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power misfet is formed in a driver circuit region on the main surface of the semiconductor substrate.
Renesas Electronics Corporation


07/14/16
20160204251 

Pillar-shaped semiconductor device and production method therefor


A sio2 layer is formed at a middle of a si pillar. An opening is formed in a gate insulating layer and a gate conductor layer in a peripheral portion that includes a side surface of the sio2 layer.
Unisantis Electronics Singapore Pte. Ltd.


07/14/16
20160204250 

New layout for ldmos


A layout structure, a semiconductor device and an electronic apparatus are provided. The layout structure includes at least one ldmos.
Semiconductor Manufacturing International (shanghai) Corporation


07/14/16
20160204249 

Mosfet having dual-gate cells with an integrated channel diode


A semiconductor device includes mosfet cells having a drift region of a first conductivity type. A first and second active area trench are in the drift region.
Texas Instruments Incorporated


07/14/16
20160204248 

Semiconductor device with vertical gate and manufacturing the same


A gate electrode is formed in a trench reaching a drain region so as to leave a concave portion on the top of the trench. A first insulating film is formed, which fills the concave portion and of which the thickness increases as the distance from an end of the trench increases on the substrate surface on both sides of the trench.
Panasonic Intellectual Property Management Co., Ltd.


07/14/16
20160204246 

Ge and iii-v channel semiconductor devices having maximized compliance and free surface relaxation


Ge and iii-v channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such ge and iii-v channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate.
Intel Corporation


07/14/16
20160204244 

Semiconductor device and making same


A semiconductor device and method of forming the same is described. In an example, a polysilicon layer is deposited on a substrate having at least one polysilicon ring.
Hewlett-packard Develoment Company, L.p.


07/14/16
20160204243 

Semiconductor device and a manufacturing a semiconductor device


The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region.
Renesas Electronics Corporation


07/14/16
20160204242 

Compound semiconductor device and manufacturing the same


An embodiment of a compound semiconductor device includes: a substrate; a nitride compound semiconductor stacked structure formed on or above the substrate; and a gate electrode, a source electrode and a drain electrode formed on or above the compound semiconductor stacked structure. A recess positioning between the gate electrode and the drain electrode in a plan view is formed at a surface of the compound semiconductor stacked structure..
Fujitsu Limited


07/14/16
20160204241 

Semiconductor device and manufacturing method thereof


A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor on a substrate, a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer, a gate trench formed in the second semiconductor layer or in the second and first semiconductor layers, a gate electrode formed at the gate trench, and a source electrode and a drain electrode formed on the second semiconductor layer. The gate trench has terminal parts of a bottom of the gate trench formed shallower than a center part of the bottom.
Fujitsu Limited


07/14/16
20160204240 

Power semiconductor device


A power semiconductor device is provided comprising: a collector electrode, a collector layer of a second conductivity type, a drift layer of a first conductivity type, a base layer of the second conductivity type, a first insulating layer having an opening, an emitter layer of the first conductivity type, the emitter layer contacts the base layer and separated from the drift layer by one of the first insulating layer or the base layer, a body layer of the second conductivity type arranged laterally to the emitter layer and separated from the base layer by the first insulating layer and the emitter layer, a source region of the first conductivity type separated from the emitter layer by the body layer, an emitter electrode contacted by the source region. The device further comprises a first layer of the second conductivity type contacting the emitter electrode and separated from the base layer, and a second layer of the first conductivity type arranged between the first layer and the base layer and separated from the emitter layer and the source region.
Abb Technology Ag


07/14/16
20160204238 

Igbt having deep gate trench


There are disclosed herein various implementations of an insulated-gate bipolar transistor (igbt) with buried depletion electrode. Such an igbt may include a collector at a bottom surface of a semiconductor substrate, a drift region having a first conductivity type situated over the collector, and a base layer having a second conductivity type opposite the first conductivity type situated over the drift region.
Infineon Technologies Americas Corp.


07/14/16
20160204237 

Semiconductor device


A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth p layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth p layers respectively have surface concentrations p(1) to p(4) that decrease in this order, bottom-end distances d(1) to d(4) that increase in this order, and distances b(1) to b(4) to the edge of the semiconductor substrate that increase in this order.
Mitsubishi Electric Corporation


07/14/16
20160204236 

Semiconductor device


A semiconductor device includes: a first conductivity-type collector region; a second conductivity-type field stop region disposed on the collector region; a second conductivity-type drift region, which is disposed on the field stop region and has an impurity concentration lower than the field stop region; a first conductivity-type base region disposed on the drift region; and a second conductivity-type emitter region disposed on the base region, wherein an impurity concentration gradient in a film thickness direction of the field stop region is larger in a region adjacent to the collector region than in a region adjacent to the drift region.. .
Sanken Electric Co., Ltd.


07/14/16
20160204235 

Bipolar transistor, semiconductor device, and bipolar transistor manufacturing method


Disconnection of a base line is suppressed even when a short-side direction of a collector layer is parallel to crystal orientation [011]. A bipolar transistor includes: a collector layer that has a long-side direction and a short-side direction in a plan view, in which the short-side direction is parallel to crystal orientation [011], a cross-section perpendicular to the short-side direction has an inverted mesa shape, and a cross-section perpendicular to the long-side direction has a forward mesa shape; a base layer that is formed on the collector layer; a base electrode that is formed on the base layer; and a base line that is connected to the base electrode and that is drawn out from an end in the short-side direction of the collector layer to the outside of the collector layer in a plan view..
Murata Manufacturing Co., Ltd.


07/14/16
20160204233 

Integrated circuit heat dissipation using nanostructures


An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device.
International Business Machines Corporation


07/14/16
20160204232 

Manufacturing the semiconductor device


The semiconductor device is manufactured through the following steps: after first heat treatment is performed on an oxide semiconductor film, the oxide semiconductor film is processed to form an oxide semiconductor layer; immediately after that, side walls of the oxide semiconductor layer are covered with an insulating oxide; and in second heat treatment, the side surfaces of the oxide semiconductor layer are prevented from being exposed to a vacuum and defects (oxygen deficiency) in the oxide semiconductor layer are reduced.. .
Semiconductor Energy Laboratory Co., Ltd.


07/14/16
20160204231 

Semiconductor device and manufacturing method thereof


A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film.
Semiconductor Energy Laboratory Co., Ltd.


07/14/16
20160204230 

Method for fabricating semiconductor device


A method for fabricating semiconductor device is disclosed. Preferably, two hard masks are utilized to define the width of the first gate (may serve for a control gate) and the width of the second gate (may serve for a select gate).
United Microelectronics Corp.


07/14/16
20160204228 

Method for forming a nanowire structure


Embodiments of the invention describe a method for forming a nanowire structure on a substrate. According to one embodiment, the method includes a) depositing a first semiconductor layer on the substrate, b) etching the first semiconductor layer to form a patterned first semiconductor layer, c) forming a dielectric layer across the patterned first semiconductor layer, and d) depositing a second semiconductor layer on the patterned first semiconductor layer and on the dielectric layer.
Tokyo Electron Limited


07/14/16
20160204224 

Tunnel field-effect transistor, manufacturing same, and switch element


A tunnel field-effect transistor (tfet) is configured by disposing a iii-v compound semiconductor nano wire on a (111) plane of a iv semiconductor substrate exhibiting p-type conductivity, and arbitrarily disposing electrodes of a source, drain and gate. Alternatively, the tunnel field-effect transistor is configured by disposing a iii-v compound semiconductor nano wire on a (111) plane of a iv semiconductor substrate exhibiting n-type conductivity, and arbitrarily disposing electrodes of a source, drain and gate.
Japan Science And Technology Agency


07/14/16
20160204223 

High voltage device fabricated using low-voltage processes


A method for fabricating a high-voltage transistor on a semiconductor substrate includes defining and forming shallow trench isolation regions for all of the transistors, defining and forming well regions for all of the transistors, forming a gate oxide layer in the well regions for all of the transistor, forming gates for all of the transistors over the gate oxide layer, implanting a dopant to form lightly-doped drain regions for all of the transistors, the lightly-doped drain regions for at least drains of the high-voltage transistors being spaced apart from an inner edge of the shallow trench isolation regions, forming gate spacers at sides of the gates of all of the transistors, and implanting a dopant to form sources and drains for all of the transistors, the drains of the high-voltage transistors being formed completely surrounded by the lightly-doped drain regions of the high-voltage transistors.. .
Microsemi Soc Corporation


07/14/16
20160204220 

Method for manufacturing silicon carbide semiconductor device


A method for manufacturing a silicon carbide semiconductor device includes steps of preparing a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, forming a groove portion in the first main surface of the silicon carbide substrate, and cutting the silicon carbide substrate at the groove portion. The step of forming the groove portion includes a step of thermally etching the silicon carbide substrate using chlorine.
Sumitomo Electric Industries, Ltd.


07/14/16
20160204219 

Semiconductor device comprising ferroelectric elements and fast high-k metal gate transistors


A semiconductor device comprises a first and second circuit element. The first circuit element comprises a first electrode structure including a first high-k dielectric layer, the first high-k dielectric layer having a first thickness and comprising hafnium.
Globalfoundries Inc.


07/14/16
20160204218 

Semiconductor structure comprising an aluminum gate electrode portion and the formation thereof


An illustrative method includes providing a semiconductor structure. The semiconductor structure includes an active region and an electrically insulating structure.
Globalfoundries Inc.


07/14/16
20160204217 

Devices with fully and partially silicided gate structures in gate first cmos technologies


A semiconductor product with certain devices having a first device with a fully silicided (fusi) gate and a second device with a partially silicided gate is disclosed. In one example, the first semiconductor device is recessed, resulting in a recessed first gate electrode material which is fully silicided during a subsequent silicidation process.
Globalfoundries Inc.


07/14/16
20160204215 

Semiconductor device and manufacturing method thereof


A fin fet semiconductor device includes a fin structure extending in a first direction and extending from an isolation insulating layer. The fin fet device also includes a gate stack including a gate electrode layer, a gate dielectric layer, side wall insulating layers disposed at both sides of the gate electrode layer, and interlayer dielectric layers disposed at both sides of the side wall insulating layers.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/14/16
20160204213 

Semiconductor device


A semiconductor device according to an embodiment switches high-frequency signals and includes a semiconductor layer of a first conductivity type. A first layer of a second conductivity type is provided in the semiconductor layer.
Kabushiki Kaisha Toshiba


07/14/16
20160204211 

Self-limiting silicide in highly scaled fin technology


A method of forming a metal semiconductor alloy on a fin structure that includes forming a semiconductor material layer of a polycrystalline crystal structure material or amorphous crystal structure material on a fin structure of a single crystal semiconductor material, and forming a metal including layer on the semiconductor material layer. Metal elements from the metal including layer may then b intermixed metal elements with the semiconductor material layer to provide a metal semiconductor alloy contact on the fin structure.
International Business Machines Corporation


07/14/16
20160204210 

Semiconductor device having field plate structures and gate electrode structures between the field plate structures


A semiconductor device includes a field effect transistor in a semiconductor substrate having a first surface. The field effect transistor includes a first field plate structure and a second field plate structure, each extending in a first direction parallel to the first surface, and gate electrode structures disposed over the first surface and extending in a second direction parallel to the first surface, the gate electrode structures being disposed between the first and the second field plate structures..
Infineon Technologies Austria Ag


07/14/16
20160204207 

Composite high-k metal gate stack for enhancement mode gan semiconductor devices


Enhancement mode gallium nitride (gan) semiconductor devices having a composite high-k metal gate stack and methods of fabricating such devices are described. In an example, a semiconductor device includes a gallium nitride (gan) channel region disposed above a substrate.
Intel Corporation


07/14/16
20160204206 

Silicon carbide semiconductor device and manufacturing same


A silicon carbide semiconductor device includes: a silicon carbide off substrate including a main surface having an off angle relative to a basal plane, the main surface being provided with a trench, the trench having a plurality of side walls and a bottom portion; a gate insulating film covering the side walls and the bottom portion; and a gate electrode provided on the gate insulating film, each of the side walls having an angle of more than 65° and not more than 80° relative to the basal plane in the trench, opening directions of the plurality of side walls being all at a silicon plane side or a carbon plane side.. .
Sumitomo Electric Industries, Ltd.


07/14/16
20160204205 

Source material for electronic device applications


Various embodiments include methods and apparatuses comprising methods for formation of and apparatuses including a source material for electronic devices. One such apparatus includes a vertical string of memory cells comprising a plurality of alternating levels of conductor and dielectric material, a semiconductor material extending through the plurality of alternating levels of conductor material and dielectric material, and a source material coupled to the semiconductor material.
Micron Technology, Inc.


07/14/16
20160204203 

Metal oxide semiconductor having epitaxial source drain regions and a manufacturing same using dummy gate process


A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.. .
Sony Corporation


07/14/16
20160204201 

Semiconductor devices having channels with retrograde doping profile


A device isolation region is formed, delimiting an active region in a substrate. A word line is formed, extending across the active region and the device isolation region and buried therein.

07/14/16
20160204200 

Semiconductor device with non-linear surface


A semiconductor device includes a first channel having a first linear surface and a first non-linear surface. The semiconductor device includes a first dielectric region surrounding the first channel.
Taiwan Semiconductor Manufacturing Company Limited


07/14/16
20160204199 

Mosfet structure and manufacturing method thereof


A mosfet structure and a method for manufacturing the same are disclosed. The method comprises: a.
Institute Of Microelectronics, Chinese Academy Of Sciences


07/14/16
20160204198 

High mobility transistors


An integrated circuit containing an n-channel finfet and a p-channel finfet has a dielectric layer over a silicon substrate. The fins of the finfets have semiconductor materials with higher mobilities than silicon.
Texas Instruments Incorporated


07/14/16
20160204197 

Semiconductor structure and manufacturing method thereof


The present invention provides a semiconductor structure, including a substrate, a shallow trench isolation (sti) disposed in the substrate, a plurality of first fin structures disposed in the substrate, where each first fin structure and the substrate have same material, and a plurality of second fin structures disposed in the sti, where each second fin structure and the sti have same material.. .
United Microelectronics Corp.


07/14/16
20160204196 

Self-formation of high-density arrays of nanostructures


A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer.
International Business Machines Corporation


07/14/16
20160204195 

Semiconductor structure with fin structure and wire structure and forming the same


A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a fin structure formed over the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


07/14/16
20160204194 

Method and structure for improving finfet with epitaxy source/drain


Isolation structures are formed to laterally surround a gate material block such that each sidewall of the gate material block abuts a corresponding sidewall of the isolation structures. Sidewalls of the gate material bock define ends of gate structures to be subsequently formed.
International Business Machines Corporation


07/14/16
20160204192 

Semiconductor device and manufacturing the semiconductor device


In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region.
Renesas Electronics Corporation


07/14/16
20160204188 

High breakdown voltage passive element and high breakdown voltage passive element manufacturing method


Warping of a semiconductor wafer occurring due to a difference in the thermal expansion rates of an insulating film and the semiconductor wafer is restricted. Therefore, processing failures and conveying failures in the manufacturing process, as well as cracking of the semiconductor wafer, are restricted.
Fuji Electric Co., Ltd.


07/14/16
20160204180 

Organic light emitting diode display device and fabricating the same


An organic light emitting diode display device comprises a driving thin film transistor including a first semiconductor layer, a gate insulating layer formed on the first semiconductor layer. The device further includes a storage capacitor including a first capacitor electrode electrically coupled to a drain electrode of the driving thin film transistor, a buffer layer formed on the first capacitor electrode, a second semiconductor layer formed on the buffer layer, and a second capacitor electrode formed on the second semiconductor layer and electrically coupled to a gate electrode of the driving thin film transistor.
Lg Display Co., Ltd.


07/14/16
20160204179 

Light emitting device and electronic apparatus


On a semiconductor substrate, a plurality of transistors that includes a drive transistor which controls a drive current according to a potential of a gate, a light emitting element that emits a light having a brightness corresponding to the drive current, and an element isolation portion that electrically isolates each transistor are formed. The element isolation portion has a structure in which an insulator fills inside of a groove formed on the semiconductor substrate..
Seiko Epson Corporation


07/14/16
20160204178 

Semiconductor device


Semiconductor elements deteriorate or are destroyed due to electrostatic discharge damage. The present invention provides a semiconductor device in which a protecting means is formed in each pixel.
Semiconductor Energy Laboratory Co., Ltd.


07/14/16
20160204177 

Display apparatus


A display apparatus including a pixel including a first thin-film transistor (tft) and a second tft connected to the first tft, the display apparatus includes a substrate, a semiconductor layer disposed on the substrate and including an active region of the first tft and an active region of the second tft, a first gate layer disposed on the semiconductor layer and including a gate of the first tft and a gate of the second tft, a second gate layer disposed on the first gate layer and including a connection node connecting the gate of the first tft to the active region of the second tft, and a line layer disposed on the second gate layer and configured to supply a driving voltage to the pixel.. .
Samsung Display Co., Ltd.


07/14/16
20160204163 

Variable resistance memory device and manufacturing the same


A variable resistance memory device includes a semiconductor substrate having a vertical transistor with a shunt gate that increases an area of a gate of the vertical transistor.. .
Sk Hynix Inc.


07/14/16
20160204158 

Complementary metal oxide semiconductor image sensor device and forming the same


The present invention relates to a cmos image sensor device and a method of forming the same. The cmos image sensor device includes a substrate, a deep trench isolation (dti), a photodiode, an electrode and an interface region.
United Microelectronics Corp.


07/14/16
20160204156 

Solid-state imaging device and electronic apparatus


There is provided a solid-state imaging device including: one or more photoelectric conversion elements provided on side of a first surface of a semiconductor substrate; a through electrode coupled to the one or more photoelectric conversion elements, and provided between the first surface and a second surface of the semiconductor substrate; and an amplifier transistor and a floating diffusion provided on the second surface of the semiconductor substrate, in which the one or more photoelectric conversion elements are coupled to a gate of the amplifier transistor and the floating diffusion via the through electrode.. .
Sony Corporation


07/14/16
20160204153 

Solid-state imaging apparatus, manufacturing method therefor, and electronic apparatus


A charge accumulation section that is formed on a first semiconductor substrate and accumulates photoelectrically converted charges, a charge-retaining section that is formed on a second semiconductor substrate and retains charges accumulated in the charge accumulation section, and a transfer transistor that is formed on the first semiconductor substrate and the second semiconductor substrate and transfers charges accumulated in the charge accumulation section to the charge-retaining section are provided. A bonding interface between the first semiconductor substrate and the second semiconductor substrate is formed in a channel of the transfer transistor..

07/14/16
20160204152 

Imaging device, imaging apparatus, production apparatus and method, and semiconductor device


There is provided an imaging device including a semiconductor having a light-receiving portion that performs photoelectric conversion of incident light, electrically conductive wirings, and a contact group including contacts that have different sizes and connect the semiconductor and the electrically conductive wirings.. .
C/o Sony Corporation


07/14/16
20160204150 

Image sensor


Example embodiments relate to an image sensor supporting a global shutter for minimizing image distortion. An example image sensor includes a semiconductor layer having a first surface and a second surface that are opposite to each other; a photosensitive device, which is formed in the semiconductor layer near the first surface and accumulates charges based on light incident via the second surface; a charge storage device, which is formed in the semiconductor layer near the first surface and temporarily stores charges accumulated by the photosensitive device; a first transmission transistor, which transmits charges accumulated by the photosensitive device to the charge storage device and includes a first gate formed on the first surface of the semiconductor layer; and a leakage photogenerated charge drain region, which is formed in the semiconductor layer near the second surface, is apart from the charge storage device, and is arranged above the charge storage device..

07/14/16
20160204149 

Semiconductor switching device separated by device isolation


A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.. .
Taiwan Semiconductor Manufacturing Company, Ltd.


07/14/16
20160204146 

Semiconductor structure and manufacturing method thereof


A semiconductor structure includes a semiconductive substrate includes a first side and a second side opposite to the first side, a radiation sensing device disposed in the semiconductive substrate, an interlayer dielectric (ild) disposed over the first side of the semiconductive substrate, and a conductive pad passing through the ild, disposed in the semiconductive substrate and configured to couple with an interconnect structure disposed over the ild, wherein a portion of the conductive pad is surrounded by the semiconductive substrate, and a step height is configured by a surface of the portion of the conductive pad and the second side of the semiconductive substrate.. .
Taiwan Semiconductor Manufacturing Company Ltd.


07/14/16
20160204145 

Image pickup element, manufacturing image pickup element, and electronic apparatus


An image pickup element includes: a semiconductor substrate including a photoelectric conversion section for each pixel; a pixel separation groove provided in the semiconductor substrate; and a fixed charge film provided on a light-receiving surface side of the semiconductor substrate, wherein the fixed charge film includes a first insulating film and a second insulating film, the first insulating film being provided contiguously from the light-receiving surface to a wall surface and a bottom surface of the pixel separation groove, and the second insulating film being provided on a part of the first insulating film, the part corresponding to at least the light-receiving surface.. .
Sony Corporation


07/14/16
20160204140 

Solid-state imaging element and electronic device


The solid-state imaging element includes a high-concentration diffusion layer configured to serve as a connection portion by which a wiring is connected to a semiconductor substrate, and a junction leak control film formed to cover a surface of the diffusion layer. Also, to connect the wiring to the diffusion layer, a width of an opening formed in an insulation film stacked on the semiconductor substrate is greater than a width of the diffusion layer.

07/14/16
20160204139 

Thin film transistor substrate and manufacturing same


A thin film transistor substrate includes: a gate electrode and a first electrode of a capacitor formed above a substrate so as to be arranged along a plane of the substrate; a gate insulating film formed on the gate electrode; a semiconductor layer formed on the gate insulating film; an insulating layer formed on the semiconductor layer and above the first electrode so as to expose portions of the semiconductor layer; a source electrode and a drain electrode formed above the insulating layer so as to be connected to the semiconductor layer at the exposed portions of the semiconductor layer; and a second electrode of the capacitor formed above the insulating layer, at a position opposite the first electrode, and the insulating layer above the gate electrode is thicker than the insulating layer above the first electrode.. .
Joled Inc.


07/14/16
20160204137 

Semiconductor device and manufacturing method thereof


A manufacturing method of a semiconductor device comprises the steps of: providing a transparent substrate; forming a gate electrode on the transparent substrate; forming a gate insulation layer covering the gate electrode; forming an oxide semiconductor layer on the gate insulation layer and at least partially over the gate electrode; forming an etching stop layer over the gate electrode and at least covering a part of the oxide semiconductor layer, wherein the etching stop layer includes an opening; forming an electrode layer at the opening and on a part of the etching stop layer; and applying a low-resistance treatment to a part of the oxide semiconductor layer uncovered by the etching stop layer and the electrode layer to form a pixel electrode.. .
Hannstar Display Corporation


07/14/16
20160204136 

Transistor and liquid crystal display device having the same


A transistor and a liquid crystal display device having the same are provided. The transistor includes a first gate electrode disposed on a base substrate; a gate insulating layer disposed on the first gate electrode; a semiconductor layer disposed on the gate insulating layer, and including a channel area; a source electrode and a drain electrode connected to both ends of the semiconductor layer; a passivation layer configured to cover the semiconductor layer, the source electrode, and the drain electrode; and a second gate electrode disposed on the passivation layer, and partially overlapping the channel area in a direction from the drain electrode toward the source electrode..
Samsung Display Co., Ltd


07/14/16
20160204135 

Thin film transistor array panel and manufacturing the same


A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a gate line disposed on a substrate and including a gate electrode; a gate insulating layer formed on the gate line; a first oxide semiconductor layer disposed on the gate insulating layer and formed of an oxide semiconductor; a data wiring layer disposed on the gate insulating layer and including data line intersecting with the gate line, a source electrode connected to the data line, and a drain electrode facing the drain electrode; and a second oxide semiconductor layer covering the source electrode and the drain electrode, wherein the data wiring layer includes copper or a copper alloy.. .
Samsung Display Co., Ltd.


07/14/16
20160204134 

An array substrate manufacturing method, an array substrate and a display panel


The present invention discloses an array substrate manufacturing method, an array substrate and a display panel, and the method comprises: forming a gate electrode and a first electrode which is transparent on the substrate; forming an isolated layer on the substrate, and covering the isolated layer on the gate electrode and the first electrode; forming a semiconductor layer on the isolated layer; forming a medium layer on the semiconductor layer, and providing a first via hole, a second via hole and a third via hole; forming a source electrode, a drain electrode, and a second electrode on the medium layer, the source electrode and the drain electrode are connected to the semiconductor layer respectively through the first via hole and the second via hole, and the second electrode is connected to the first electrode through the third via hole to form a storage capacitance; forming a third electrode which is transparent on the medium layer, and the third electrode is connected to the drain electrode to form a pixel electrode. An utilized amount of photomasks can be decreased, technical processes can be reduced and cost can be saved during the manufacturing procedures of the array substrate in the present invention by applying the aforemention method..
Shenzhen China Star Optoelectronics Technology Co. Ltd.


07/14/16
20160204132 

Finfet with reduced capacitance


A structure including a gate electrode above and perpendicular to a plurality of semiconductor fins, a pair of spacers disposed on opposing sides of the gate electrode, and a gap fill material above a semiconductor substrate, directly below the gate electrode, and between the plurality of fins, the gate electrode separates the gap fill material from each of the plurality of fins.. .
International Business Machines Corporation


07/14/16
20160204131 

Strain release in pfet regions


A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (ssoi) structure, the ssoi structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the ssoi structure, forming a gate structure over a portion of at least one fin in a nfet region, forming a gate structure over a portion of at least one fin in a pfet region, removing the gate structure over the portion of the at least one fin in the pfet region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pfet region, such that the new gate structure surrounds the portion on all four sides.. .
International Business Machines Corporation


07/14/16
20160204130 

Flat panel display device with oxide thin film transistor and fabricating the same


A flat panel display device with an oxide thin film transistor is disclosed which includes: a buffer film formed on a substrate; an oxide semiconductor layer which has a width of a first length and is formed on the buffer film; a gate insulation film which has a width of a second length and is formed on the oxide semiconductor layer; a gate electrode which has a width of a third length and is formed on the gate insulation film; an interlayer insulation film formed on the entire surface of the substrate provided with the gate electrode; source and drain electrodes formed on the interlayer insulation film and connected to the oxide semiconductor layer; a passivation film formed on the entire surface of the substrate provided with the source and drain electrode; and a pixel electrode formed on the passivation film and connected to the drain electrode. The first length is larger than the second length and the second length is larger than the third length..
Lg Display Co., Ltd.


07/14/16
20160204129 

Fdsoi - capacitor


A method of manufacturing a semiconductor device including a capacitor structure is provided, including the steps of providing an soi wafer comprising a substrate, a buried oxide (box) layer formed over the substrate and a semiconductor layer formed over the box layer, removing the semiconductor layer in a first region of the wafer to expose the box layer, forming a dielectric layer over the exposed box layer in the first region, and forming a conductive layer over the dielectric layer. Moreover, a semiconductor device including a capacitor formed on a wafer is provided, wherein the capacitor comprises a first capacitor electrode comprising a doped semiconductor substrate of the wafer, a capacitor insulator comprising an ultra-thin box layer of the wafer and a high-k dielectric layer formed on the ultra-thin box layer, and a second capacitor electrode comprising a conductive layer formed over the high-k dielectric layer..
Globalfoundries Inc.


07/14/16
20160204128 

Cointegration of bulk and soi semiconductor devices


A method of forming a semiconductor device structure includes providing a substrate with a semiconductor-on-insulator (soi) configuration, the soi substrate comprising a semiconductor layer formed on a buried oxide (box) layer which is disposed on a semiconductor bulk substrate, forming trench isolation structures delineating a first region and a second region within the soi substrate, removing the semiconductor layer and the box layer in the first region for exposing the semiconductor bulk substrate within the first region, forming a first semiconductor device with an electrode in and over the exposed semiconductor bulk substrate in the first region, forming a second semiconductor device in the second region, the second semiconductor device comprising a gate structure disposed over the semiconductor layer and the box layer in the second region, and performing a polishing process for defining a common height level to which the electrode and the gate structure substantially extend.. .
Globalfoundries Inc.


07/14/16
20160204126 

Thin-film transistor substrate and fabricating the same


A tft substrate includes: a substrate; a gate electrode above the substrate; an oxide semiconductor layer above the substrate; a gate insulating film between the gate electrode and the oxide semiconductor layer; a source electrode and a drain electrode which are connected to the oxide semiconductor layer; oxide films on the surface of the source electrode and the surface of the drain electrode, respectively; a first protective film covering the oxide films; a first interconnect layer connected to the source electrode and the drain electrode via respective first contact holes extending through the first protective film and the oxide films; wherein the source electrode and the drain electrode are each a laminated film including a cu film and a cu—mn alloy film formed on the cu film.. .
Joled Inc.


07/14/16
20160204125 

Thin film transistor array panel


A thin-film transistor array panel includes an insulation substrate, a gate line disposed on the insulation substrate, a gate insulating layer disposed on the gate line, a semiconductor layer disposed on the gate insulating layer, a data line disposed on the semiconductor layer and including a source electrode, a drain electrode disposed on the semiconductor layer and facing the source electrode, a first electrode disposed on the gate insulating layer, a first passivation layer disposed on the first electrode and including silicon nitride, a second passivation layer disposed on the first passivation and including silicon nitride, and a second electrode disposed on the passivation layer, in which a first ratio of nitrogen-hydrogen bonds to silicon-hydrogen bonds in the first passivation layer is different from a second ratio of nitrogen-hydrogen bonds to silicon-hydrogen bonds in the second passivation layer.. .
Samsung Display Co., Ltd.


07/14/16
20160204124 

Display panel


A display panel is provided. The display panel includes a substrate including a non-display region containing a thin film transistor, which includes a semiconductor layer; a first insulating layer; a first metal layer; a second insulating layer; a first and second via hole series disposed adjacent to the respective opposite sides of the first metal layer.
Innolux Corporation


07/14/16
20160204123 

Method of fabricating three-dimensional semiconductor devices, and three-dimensional semiconductor devices thereof


Present example embodiments relate generally to semiconductor devices and methods of fabricating a semiconductor device comprising providing a substrate and forming a plurality of layers over the substrate. The plurality of layers comprise alternating first composition material layers and second composition material layers.
Macronix International Co., Ltd.


07/14/16
20160204122 

Three-dimensional memory device containing plural select gate transistors having different characteristics and making thereof


A stack of material layers includes first material layers, second material layers located between a respective pair of an overlying first material layer and an underlying first material layer, and at least one temporary material layer located between a respective pair of an overlying first material layer and an underlying first material layer. After formation of a memory opening and a memory stack structure, at least one first backside recess is formed by removing the at least one temporary material layer and adjoining portions of a memory film.
Sandisk Technologies, Inc.


07/14/16
20160204119 

Semiconductor device


A semiconductor device may include: a plurality of source-side half channels positioned in a first region and arranged in first to 2nth rows, wherein n is an integer equal to or greater than 2; a plurality of first drain-side half channels positioned in a second region at one side of the first region and arranged in first to nth rows; a plurality of second drain-side half channels positioned in a third region at the other side of the first region and arranged in first to nth rows; a plurality of first pipe channels suitable for connecting the first to nth rows of source-side half channels to the first to nth rows of first drain-side half channels, respectively; and a plurality of second pipe channels suitable for connecting the (n+1)th to 2nth rows of source-side half channels to the first to nth rows of second drain-side half channels, respectively.. .
Sk Hynix Inc.


07/14/16
20160204118 

Techniques to avoid or limit implant punch through in split gate flash memory devices


Some embodiments of the present disclosure relate to a flash memory device. The flash memory device includes first and second individual source/drain (s/d) regions spaced apart within a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/14/16
20160204116 

Method for manufacturing a semiconductor device


The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate.
Renesas Electronics Corporation


07/14/16
20160204115 

Semiconductor device and fabricating the same


A semiconductor device includes stacked structure, openings passing through stacked structure, semiconductor patterns formed over inner walls of the openings, liner layers formed in the openings over the semiconductor patterns, and gap-fill insulating layers formed over the liner layers to fill the openings, wherein each of the gap-fill insulating layers seals an upper portion of the opening and includes at least one air gap.. .
Sk Hynix Inc.


07/14/16
20160204114 

Semiconductor device


A semiconductor device includes first and second well regions having a first conductivity type, and a third well region between the first and second well regions having a second conductivity type different from the first conductivity type. A first active region is in the first well region.
Samsung Electronics Co., Ltd.


07/14/16
20160204113 

Semiconductor device, related manufacturing method, and related electronic device


A semiconductor device may include a first inverter, a second inverter, a first access transistor, and a second access transistor. A drain electrode of the first access transistor or a source electrode of the first access transistor may be electrically connected to both an output terminal of the first inverter and an input terminal the second inverter.
Semiconductor Manufacturing International (shanghai) Corporation


07/14/16
20160204112 

Semiconductor device and fabricating the same


A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.. .

07/14/16
20160204109 

Semiconductor device and fabricating method thereof


A semiconductor device includes an interlayer insulating film formed on a substrate and including a trench, a gate insulating film formed in the trench, a work function adjusting film formed on the gate insulating film in the trench along sidewalls and a bottom surface of the trench, and including an inclined surface having an acute angle with respect to the sidewalls of the trench, and a metal gate pattern formed on the work function adjusting film in the trench to fill up the trench.. .

07/14/16
20160204108 

Cmos transistor, semiconductor device including the transistor, and semiconductor module including the device


Provided are a cmos transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The cmos transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate.

07/14/16
20160204107 

Semiconductor intergrated circuit and logic circuit


Disclosed herein is a driver circuit including first and second n-channel transistors connected together in series between first and second nodes. The first n-channel transistor is comprised of n fin transistor(s) having an identical gate length and an identical gate width where n is equal to or greater than one, and has its gate connected to a first input node.
Socionext Inc.


07/14/16
20160204106 

Semiconductor devices and methods of fabricating the same


A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a fin which comprises long sides and a first short side, a first trench which is immediately adjacent the first short side of the fin and has a first depth, a second trench which is immediately adjacent the first trench and has a second depth greater than the first depth, a first protrusion structure which protrudes from a bottom of the first trench and extends side by side with the first short side, and a gate which is formed on the first protrusion structure to extend side by side with the first short side..

07/14/16
20160204105 

Method and device for a finfet


A method of forming a semiconductor device includes providing a semiconductor substrate. The semiconductor substrate includes a plurality of fins formed thereon, a stress layer formed on the top surface of each of the fins, and a plurality of strip-shaped gate structures formed above the stress layers.
Semiconductor Manufacturing International (shanghai) Corporation


07/14/16
20160204104 

Semiconductor integrated circuit devices


A semiconductor integrated circuit device may include a standard cell region on a surface of a substrate and a first active region on the surface of the substrate in the standard cell region, wherein the first active region has a length in a first direction. A second active region may be on the surface of the substrate in the standard cell region, the second active region may have a length in the first direction, the length of the second active region may be greater than the length of the first active region, and an axis in a second direction may intersect centers of the first and second active regions so that the first and second active regions are symmetric about the axis in the second direction.

07/14/16
20160204103 

Semiconductor device structure


A semiconductor device structure having at least one thin-film resistor structure is provided. Through the metal plug(s) or metal wirings located on different layers, a plurality of stripe segments of the thin-film resistor structure is electrically connected to ensure the thin-film resistor structure with the predetermined resistance and less averting areas in the layout design..
United Microelectronics Corp.


07/14/16
20160204102 

Three-dimensional semiconductor device and manufacturing the same


A three-dimensional (3d) semiconductor device is provided, comprising a substrate having a staircase region comprising n steps, wherein n is an integer one or greater; a stack having multi-layers on the substrate, and the multi-layers comprising active layers alternating with insulating layers on the substrate, the stack comprising a plurality of sub-stacks formed on the substrate and the sub-stacks disposed in relation to the n steps to form respective contact regions; and a plurality of connectors formed in the respective contact regions, and the connectors extending downwardly to connect a bottom layer under the multi-layers.. .
Macronix International Co., Ltd.


07/14/16
20160204100 

Semiconductor device and formation method thereof


The present disclosure provides a semiconductor device and formation method thereof. A shallow trench isolation structure is formed in a semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


07/14/16
20160204099 

Semiconductor device and manufacturing the same


Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion.
Renesas Electronics Corporation


07/14/16
20160204097 

Semiconductor device having overload current carrying capability


A semiconductor device includes a semiconductor region having charge carriers of a first conductivity type, a transistor cell in the semiconductor region, and a semiconductor channel region in the transistor cell and having a first doping concentration of charge carriers of a second conductivity type. A semiconductor auxiliary region in the semiconductor region has a second doping concentration of charge carriers of the second conductivity type, which is at least 30% higher than the first doping concentration.
Infineon Technologies Ag


07/14/16
20160204095 

Semiconductor device


A first impurity diffusion region is provided within a semiconductor substrate, a second impurity diffusion region is provided within the first impurity diffusion region, a third impurity diffusion region is provided within the second impurity diffusion region, a first portion of a fourth impurity diffusion region is provided within the second impurity diffusion region so as to be spaced from the third impurity diffusion region, and a second portion of the fourth impurity diffusion region is provided in a third portion of the first impurity diffusion region on a side of a surface of the semiconductor substrate, a first contact is provided so as to be in contact with the second portion, the first contact and the third portion overlap in plan view, and a first power supply is connected to the third impurity diffusion region.. .
Seiko Epson Corporation


07/14/16
20160204093 

Fabrication semiconductor package


A fabrication method of a semiconductor package is disclosed, which includes the steps of: disposing a plurality of first semiconductor elements on an interposer; forming a first encapsulant on the interposer for encapsulating the first semiconductor elements; disposing a plurality of second semiconductor elements on the first semiconductor elements; forming a second encapsulant on the first semiconductor elements and the first encapsulant for encapsulating the second semiconductor elements; and thinning the interposer, thereby reducing the overall stack thickness and preventing warpage of the interposer.. .
Siliconware Precision Industries Co., Ltd.


07/14/16
20160204092 

Semiconductor device


The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed.
Renesas Electronics Corporation


07/14/16
20160204086 

Methods of manufacturing wide band gap semiconductor device and semiconductor module, and wide band gap semiconductor device and semiconductor module


A method of manufacturing a wide band gap semiconductor device includes the steps of preparing a wide band gap semiconductor substrate, separating the wide band gap semiconductor substrate into a plurality of first semiconductor chips (80), fixing the plurality of first semiconductor chips (80) on a fixation member (70), measuring a breakdown voltage of each of the first semiconductor chips (80) while immersing at least the first semiconductor chips (80) in inert liquid (91), and after the step of measuring a breakdown voltage of each of the first semiconductor chips (80), providing a plurality of second semiconductor chips each having each of the first semiconductor chips (80) fixed on the fixation member (70), by cutting the fixation member (70).. .
Sumitomo Electric Industries, Ltd.


07/14/16
20160204085 

Semiconductor system, device and structure


An integrated circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between at least a portion of the plurality of first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second transistors, the second layer overlying the at least one metal layer; and at least one conductive structure constructed to provide power to a portion of the second transistors, where the provide power is controlled by at least one of the transistors.. .
Monolithic 3d Inc.


07/14/16
20160204084 

Front-to-back bonding with through-substrate via (tsv)


Methods for forming a semiconductor device structure are provided. The method includes providing a first semiconductor wafer and a second semiconductor wafer.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/14/16
20160204083 

Integrated semiconductor device and wafer level fabricating the same


The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate, the second bond pad electrically connecting to the second electrical device; a second insulation layer over the second bond pad having a top surface, the second insulation layer being bonded toward the first bond pad of the first substrate; and a through-substrate-via (“tsv”) extending from a surface opposite to the first bond pad through the first substrate and through the top surface of the second insulation layer to the second bond pad..
Taiwan Semiconductor Manufacturing Company, Ltd.


07/14/16
20160204082 

Method of manufacturing semiconductor device


In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip..
Renesas Electronics Corporation


07/14/16
20160204081 

Semiconductor device and manufacturing the same


The present invention provides a semiconductor device with an improved yield ratio and reduced height and manufacturing cost; and a method of manufacturing the semiconductor device. According to an aspect of the present invention, there is provided a semiconductor device including a substrate, a semiconductor element that is flip-chip connected to the substrate, and a molding portion that seals the semiconductor element.
Cypress Semiconductor Corporation


07/14/16
20160204080 

Semiconductor packages and methods for fabricating the same


A semiconductor package comprising: a semiconductor chip; a connection pillar that is disposed adjacent to the semiconductor chip; a first heat dissipation layer disposed on the semiconductor chip; and a second heat dissipation layer disposed on the first heat dissipation layer, the second heat dissipation layer including a first protrusion extending beyond a perimeter of the semiconductor chip and extending towards the connection pillar.. .

07/14/16
20160204079 

Methods and apparatus of packaging with interposers


Methods and apparatus for forming a semiconductor device package on an interposer using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, where a micro-bump is used as a vertical connection between a die and the interposer, and a micro-bump line is used as a horizontal connection for signal transmission between different dies above the interposer.
Taiwan Semiconductor Manufacturing Company, Ltd.


07/14/16
20160204075 

Semiconductor chip and processing a semiconductor chip


Various embodiments provide a semiconductor chip, wherein the semiconductor chip comprises a first contact area and a second contact area both formed at a frontside of the semiconductor chip; a passivation layer arranged at the frontside between the first contact area and the second contact area; and a contact stack formed over the frontside of the semiconductor chip and comprising a plurality of layers, wherein at least one layer of the plurality of layers is removed from the passivation layer and boundary regions of the contact areas being adjacent to the passivation layer and wherein at least one another layer of the plurality of different layer is present in the boundary region of the contact areas adjoining the passivation layer.. .
Infineon Technologies Ag


07/14/16
20160204074 

Dicing power transistors


Some embodiments relate to a method of dicing a semiconductor wafer. The semiconductor wafer that includes a device structure that is formed within a device layer.
Taiwan Semiconductor Manufacturing Co., Ltd.


07/14/16
20160204073 

Semiconductor package and manufacturing the same


A semiconductor package includes a semiconductor chip mounted on a substrate, an insulating layer covering at least a portion of the semiconductor chip and including a thixotropic material or a hot melt material, and a shielding layer covering at least a portion of the semiconductor chip and the insulating layer. A method of manufacturing the semiconductor package includes forming an insulating layer and a shielding layer having a high aspect ratio by using a three-dimensional printer..
Samsung Electronics Co., Ltd.


07/14/16
20160204072 

Semiconductor apparatus and manufacturing same


According to the embodiments, a semiconductor device includes a substrate, a plurality of insulating layers, a lower shield plate, a semiconductor device, an upper shield plate, and a side shield member. A first contact portion is formed on the substrate.
Kabushiki Kaisha Toshiba


07/14/16
20160204071 

Semiconductor die and die cutting method


The present disclosure provides die cutting methods and semiconductor dies. A semiconductor substrate has a test region, isolation regions, and core regions.
Semiconductor Manufacturing International (shanghai) Corporation


07/14/16
20160204070 

Semiconductor device and manufacturing method thereof


A method for manufacturing a semiconductor device is provided. The method comprises the steps of: providing a transparent substrate having a visible region and an invisible region; forming a gate and at least an alignment mark coplanarly on the transparent substrate, wherein the gate is located in the visible region and the alignment mark is located in the invisible region; forming a gate insulation layer to cover the gate and cover the alignment mark; forming an oxide semiconductor layer on the gate insulation layer above the gate; and forming an etching stop layer above the gate and the alignment mark..
Hannstar Display (nanjing) Corporation


07/14/16
20160204069 

Semiconductor device with reduced via resistance


A semiconductor interconnect structure that has a first portion included in an upper interconnect level and a second portion included in a lower interconnect level. The semiconductor interconnect structure has a segment of dielectric capping material that is in contact with the bottom of the first portion, which separates, in part, the upper interconnect level from a lower interconnect level.
International Business Machines Corporation


07/14/16
20160204068 

Semiconductor device and semiconductor device manufacturing method


A method includes forming a multilayered film including a conductive layer mainly containing aluminum, and a barrier metal layer formed thereon, forming a hard mask layer on the barrier metal layer, patterning a resist on the hard mask layer, patterning the hard mask layer by dry-etching the hard mask layer with the patterned resist as a mask, cleaning a surface of the barrier metal layer with a cleaning solution after the patterning the hard mask layer, and dry-etching the multilayered film with the patterned hard mask layer as a mask after the cleaning the surface of the barrier metal layer. In the patterning the hard mask layer, dry etching is performed with a ratio of a flow rate of an oxidizing gas to a total flow rate of a process gas at less than 1% in a state in which the barrier metal layer is exposed to the process gas..
Canon Kabushiki Kaisha


07/14/16
20160204066 

Semiconductor device and fabrication method thereof


The present disclosure provides a semiconductor device and fabrication method thereof. A dielectric layer is formed on a first surface of a semiconductor substrate.
Semiconductor Manufacturing International (shanghai) Corporation


07/14/16
20160204061 

Chip package and fabrication method thereof


A chip package including a chip, a first though hole, a conductive structure, a first isolation layer, a second though hole and a first conductive layer. The first though hole is extended from a second surface to a first surface to expose a conductive pad, and the conductive structure is on the second surface and extended to the first though hole to contact the conductive pad.
Xintec Inc.


07/14/16
20160204058 

Semiconductor device


A power supply wiring structure of a semiconductor device including a semiconductor chip flip-chip mounted on a substrate decreases the characteristic impedance of internal wiring and thereby increases the noise reduction effect, while achieving low impedance during high frequency power supply operation. A semiconductor device has an inner power supply plate structure on a first insulating film on a protection film of a semiconductor chip, in an inner region of a plurality of peripheral electrode pads on a mounting surface of the semiconductor chip as viewed in plan, for supplying power to the semiconductor chip.
Noda Screen Co., Ltd.


07/14/16
20160204057 

Semiconductor device


A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin.
Renesas Electronics Corporation


07/14/16
20160204056 

Wiring board with interposer and dual wiring structures integrated together and making the same


A wiring board with integrated interposer and dual wiring structures is characterized in that an interposer and a first wiring structure are positioned within a through opening of a stiffener whereas a second wiring structure is disposed beyond the through opening of the stiffener. The mechanical robustness of the stiffener can prevent the wiring board from warping.
Bridge Semiconductor Corporation


07/14/16
20160204055 

Ic package


An ic package having a semiconductor body that includes a monolithically integrated circuit and at least two metallic contact surfaces. The integrated circuit being connected to the two electrical contact surfaces via printed conductors, and being disposed on a carrier substrate and connected to the carrier substrate in a force-fitting manner.
Micronas Gmbh


07/14/16
20160204053 

Semiconductor package


The invention provides a semiconductor package. The semiconductor package includes a lead frame including a die peddle.
Mediatek Inc.


07/14/16
20160204052 

Packaged semiconductor device having leadframe features preventing delamination


A semiconductor device has a leadframe with a first (401a) and a parallel second surface, and an assembly pad (410) bordered by two opposing sides, which include a plurality of through-holes (420) from the first to the second pad surface. Another pad side includes one or more elongated windows (421) between the pad surfaces.
Texas Instruments Incorporated


07/14/16
20160204050 

Semiconductor device, related manufacturing method, and related electronic device


A method for manufacturing a semiconductor device may include the following steps: preparing a first substrate; providing a first conductor, which is configured to electrically connect two elements associated with the first substrate; providing a second conductor on the first substrate, wherein the second conductor is electrically connected to the first conductor; preparing a second substrate; providing a third conductor, which is configured to electrically connect two elements associated with the second substrate; providing a fourth conductor on the second substrate, wherein the fourth conductor is electrically connected to the third conductor; providing a fifth conductor on the fourth conductor; and combining the fifth conductor with the second conductor through eutectic bonding.. .
Semiconductor Manufacturing International (shanghai) Corporation


07/14/16
20160204048 

Integrated circuit heat dissipation using nanostructures


An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device.
International Business Machines Corporation


07/14/16
20160204047 

Semiconductor device and manufacturing the same


A semiconductor device includes: a semiconductor element having a solder region and a non-solder region on a first face; a first metal member disposed on the first face of the semiconductor element; a second metal member disposed on a rear face of the semiconductor element; a first solder that connects the solder region of the semiconductor element and the first metal member; and a second solder that connects the rear face of the semiconductor element and the second metal member. At least the second solder provides a melt-bond.
Denso Corporation


07/14/16
20160204046 

Semiconductor device


A semiconductor device includes a semiconductor chip, a resin mold portion sealing a component in which the semiconductor chip is included, and a bonding layer disposed between the resin mold portion and the component. The bonding layer is made of an organic resin that is disposed at an obverse side of the component, and includes a first layer bonded to the component and a second layer bonded to the resin mold portion.
Denso Corporation


07/14/16
20160204043 

Methods for monitoring semiconductor fabrication processes using polarized light


The inventive concept provides apparatuses and methods for monitoring semiconductor fabrication processes in real time using polarized light. In some embodiments, the apparatus comprises a light source configured to generate light, a beam splitter configured to reflect the light toward the wafer being processed, an objective polarizer configured to polarize the light reflected toward the wafer and to allow light reflected by the wafer to pass therethrough, a blaze grating configured to separate light reflected by the wafer according to wavelength, an array detector configured to detect the separated light and an analyzer to analyze the three-dimensional profile of the structure/pattern being formed in the wafer..

07/14/16
20160204042 

Method for manufacturing semiconductor structure


A method includes followings operations. A substrate including a first surface and a second surface is provided.
Taiwan Semiconductor Manufacturing Company Ltd.


07/14/16
20160204041 

Method of inspecting semiconductor device and fabricating semiconductor device using the same


A method of inspecting a semiconductor device includes providing a substrate, on which a mold layer with a plurality of mold openings is provided, milling the mold layer in a direction inclined at a predetermined angle with respect to a direction normal to a top surface of the substrate, such that an inclined cutting surface exposing milled mold openings is formed, the milled mold openings including first milling openings along a first column extending in a first direction and having different heights, obtaining image data of the cutting surface, the image data including first contour images of the first milling openings, and obtaining a first process parameter, which represents an extent of bending of the mold openings according to a distance from a top surface of the substrate, using positions of center points of the first contour images.. .
Samsung Electronics Co., Ltd.


07/14/16
20160204040 

Manufacturing apparatus of semiconductor device and management manufacturing apparatus of semiconductor device


According to one embodiment, a management method of a manufacturing apparatus of a semiconductor device, the method includes measuring a weight of a pre-exposure substrate including a semiconductor substrate and a resist film provided on the semiconductor substrate, performing an exposure process for the resist film, measuring a weight of a post-exposure substrate including the semiconductor substrate and the resist film after the exposure process is performed, and acquiring a weight difference between the weight of the pre-exposure substrate and the weight of the post-exposure substrate.. .
Kabushiki Kaisha Toshiba


07/14/16
20160204039 

Temperature-controlled implanting of a diffusion-suppressing dopant in a semiconductor structure


Semiconductor structures and methods of fabrication are provided for, for instance, inhibiting diffusion of active dopant within a semiconductor material. A diffusion-suppressing dopant is implanted via, an implanting process under controlled temperature, into a semiconductor material of a semiconductor structure to define a diffusion-suppressed region within the semiconductor material.
Globalfoundries Inc.


07/14/16
20160204038 

Methods for fabricating integrated circuits with improved implantation processes


Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having an n-channel gate stack and a p-channel gate stack formed over a semiconductor substrate.
Globalfoundries, Inc.


07/14/16
20160204035 

Backside processed semiconductor device


A method of forming a semiconductor device includes: providing a first substrate, forming at least one transistor on a first surface of the first substrate; forming a first dielectric cap layer covering the first surface of the first substrate; forming a first interconnect structure on the first dielectric cap layer; providing a carrier substrate; bonding the carrier substrate to the first substrate through the first dielectric cap layer; and from a second surface of the first substrate opposite to the first surface, thinning the first substrate to a second depth.. .
Semiconductor Manufacturing International (shanghai) Corporation


07/14/16
20160204034 

Method of forming a semiconductor structure including a plurality of fins and an alignment/overlay mark


A method includes providing a semiconductor structure including a substrate that includes a material to be patterned. First and second mandrels are formed over the substrate using a common photolithography process that defines a position of the first mandrel relative to the substrate and a position of the second mandrel relative to the substrate.
Globalfoundries Inc.


07/14/16
20160204033 

Method for separating substrates and semiconductor chip


Disclosed is a method for separating a substrate (1) along a separation pattern (4), in which method a substrate (1) is provided and an auxiliary layer (3) is applied to the substrate, said layer covering the substrate at least along the separation pattern. The substrate comprising the auxiliary layer is irradiated, such that the material of the auxiliary layer penetrates the substrate along the separation pattern in the form of an impurity.
Osram Opto Semiconductors Gmbh


07/14/16
20160204032 

Method for dividing a composite into semiconductor chips, and semiconductor chip


The invention relates to a method for dividing a composite into a plurality of semiconductor chips along a dividing pattern. A composite, which comprises a substrate, a semiconductor layer sequence, and a functional layer, is provided.
Osram Opto Semiconductors Gmbh


07/14/16
20160204031 

Shielded coplanar line


In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line, including the steps of: forming active components and a set of front metallization levels; simultaneously etching from the rear surface of the substrate a through via hole and a trench crossing the substrate through at least 50% of its height; coating with a conductive material the walls and the bottom of the hole and of the trench; and filling the hole and the trench with an insulating filling material; and forming a coplanar line extending on the rear surface of the substrate, in front of the trench and parallel thereto, so that the lateral conductors of the coplanar line are electrically connected to the conductive material coating the walls of the trench.. .
Stmicroelectronics Sa


07/14/16
20160204030 

Methods of forming semiconductor device


A sacrificial layer is formed to cover the gate structures. The sacrificial layer is patterned to form a first opening in the sacrificial layer.
Samsung Electronics Co., Ltd.


07/14/16
20160204029 

Laminate and core shell formation of silicide nanowire


Methods and apparatus for forming a metal silicide as nanowires for back-end interconnection structures for semiconductor applications are provided. In one embodiment, the method includes forming a metal silicide stack comprising as plurality of metal silicide layers on a substrate by a chemical vapor deposition process or a physical vapor deposition process, thermal treating the metal silicide stack in a processing chamber, applying a microwave power in the processing chamber while thermal treating the metal silicide layer; and maintaining a substrate temperature less than 400 degrees celsius while thermal treating the metal silicide layer..
Applied Materials, Inc.


07/14/16
20160204027 

Direct deposition of nickel silicide nanowire


Methods for direct deposition of a metal silicide nanowire for back-end interconnection structures for semiconductor applications are provided. In one embodiment, the method includes positioning a substrate in a processing region of a process chamber, the substrate having a first surface comprising a non-dielectric material; and a dielectric layer formed on the first surface.
Applied Materials, Inc.


07/14/16
20160204025 

Transistor, semiconductor device and manufacturing the same


A semiconductor device including a central region, side regions located in both sides of the central region, and conductive layers including a first barrier pattern formed in the central region, a material pattern formed in the first barrier pattern and having an etch selectivity with respect to the first barrier pattern, and a second barrier pattern formed in the material pattern; and insulating layers alternately stacked with the conductive layers.. .
Sk Hynix Inc.


07/14/16
20160204023 

Manufacturing semiconductor substrate


A technique disclosed herein relates to a manufacturing method for a semiconductor substrate having the bonded interface with high bonding strength without forming an oxide layer at the bonded interface also for the substrate having surface that is hardly planarized. The manufacturing method for the semiconductor substrate may include an amorphous layer formation process in which a first amorphous layer is formed by modifying a surface of a support substrate and a second amorphous layer is formed by modifying a surface of a single-crystalline layer of a semiconductor.
National Institute Of Advanced Industrial Science And Technology


07/14/16
20160204022 

Semiconductor device structures with improved planarization uniformity, and related methods


Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a peripheral region. An array region may include memory cells coupled to conductive lines.
Micron Technology, Inc.


07/14/16
20160204010 

Method of manufacturing semiconductor device


A method of manufacturing a semiconductor device includes a step of vacuum packing a sawn wafer while being housed in a shipping case. The shipping case has the following structure.

07/14/16
20160204009 

Methods and systems to improve pedestal temperature control


A semiconductor processing system may include a substrate pedestal. The system may also include at least one fluid channel having a delivery portion configured to deliver a temperature controlled fluid to the substrate pedestal, and having a return portion configured to return the temperature controlled fluid from the substrate pedestal.
Applied Materials, Inc.


07/14/16
20160204004 

Wafer-scale package including power source


A medical device includes a first substrate, a second substrate, a control module, and an energy storage device. The first substrate includes at least one of a first semiconductor material and a first insulating material.
Medtronic, Inc.


07/14/16
20160204001 

Metal etchant compositions and methods of fabricating a semiconductor device using the same


The present inventive concepts provide metal etchant compositions and methods of fabricating a semiconductor device using the same. The metal etchant composition includes an organic peroxide in a range of about 0.1 wt % to about 20 wt %, an organic acid in a range of about 0.1 wt % to about 70 wt %, and an alcohol-based solvent in a range of about 10 wt % to about 99.8 wt %.

07/14/16
20160204000 

Method for manufacturing semiconductor device


A method for manufacturing a semiconductor device in accordance with the present invention includes the steps of preparing a semiconductor substrate, placing the semiconductor substrate on an electrostatic chuck, chucking the semiconductor substrate after raising a temperature of the electrostatic chuck to a first temperature, raising a temperature of the electrostatic chuck to a second temperature which is higher than the above-described first temperature in a state where the semiconductor substrate is chucked, and performing a treatment to the semiconductor substrate in a state where a temperature of the electrostatic chuck is maintained at the above-described second temperature.. .
Sumitomo Electric Industries, Ltd.






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