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Duc patents



      

This page is updated frequently with new Duc-related patent applications.




Date/App# patent app List of recent Duc-related patents
02/04/16
20160037654 
 Power converter patent thumbnailPower converter
An object of the invention is to further improve connection reliability of internal components of a power converter. According to the invention, there is provided a power converter including a power semiconductor module that converts dc current into ac current; a casing that forms a housing space for housing the power semiconductor module; an ac relay bus bar that is connected to an ac terminal of the power semiconductor module by weld connection; and an ac terminal block that is connected to an ac terminal of a motor, wherein the ac relay bus bar is supported by the casing through an insulating member, and the ac terminal block, is connected to the ac relay bus bar and supported by the casing..
Hitachi Automotive Systems, Ltd.


02/04/16
20160037647 
 Wiring board with built-in electronic component and  manufacturing the same patent thumbnailWiring board with built-in electronic component and manufacturing the same
A wiring board with a built-in electronic component includes a substrate having a cavity, an electronic component accommodated in the cavity, a conductive layer formed on the substrate and extending over the electronic component in the cavity, and a solder-resist layer formed on the conductive layer and having first and second openings such that the first openings are forming first pads including the conductive layer exposed by the first openings and that the second openings are forming second pads including the conductive layer exposed by the second openings. The second pads include portions of the conductive layer formed directly over the electronic component, respectively, and connected to the electronic component, the first pads include portions of the conductive layer formed on outer side with respect to the electronic component, respectively, and each second opening has an opening diameter which is formed smaller than an opening diameter of each first opening..
Ibiden Co., Ltd.


02/04/16
20160037646 
 Printed circuit board and  manufacturing the same patent thumbnailPrinted circuit board and manufacturing the same
The object of the present invention is to provide a printed circuit board formed with a cavity to mount a semiconductor chip.. .
Samsung Electro-mechanics Co., Ltd.


02/04/16
20160037644 
 Wiring board patent thumbnailWiring board
In the wiring board of the present invention, the land pattern for power supply, connected to the semiconductor element connection pad for power supply through a via conductor and arranged below the segment region, includes a strip-shaped continued portion in the position corresponding to the outer peripheral portion except the outer peripheral side of the mounting portion in the segment region, and the strip-shaped continued portion and the power supply plane arranged therebelow are connected through a via conductor.. .
Kyocera Circuit Solutions, Inc.


02/04/16
20160037643 
 Array resistor and semiconductor module patent thumbnailArray resistor and semiconductor module
A semiconductor module includes: a module board, a plurality of chips mounted on the module board, and a plurality of array resistors mounted on the module board, the plurality of array resistors including at least a first array resistor. The first array resistor may include a substrate comprising a top surface, a bottom surface opposite the top surface, and first to fourth side surfaces connecting the top surface to the bottom surface, the first and third side surfaces being opposite each other, and the second and fourth side surfaces being opposite each other; a plurality of first electrodes disposed on the first side surface of the substrate, each first electrode including at least a first portion on the first side surface of the substrate and a second portion on the bottom surface of the substrate; a plurality of second electrodes disposed on the third side surface of the substrate, each second electrode opposite a respective first electrode and including at least a first portion on the third side surface of the substrate and a second portion on the bottom surface of the substrate; for each pair of respective first and second electrodes opposite each other, a resistor disposed on the substrate between the respective first and second electrodes; and at least one third electrode disposed on the second side surface of the substrate, the third electrode including at least a first portion on the second side surface of the substrate and a second portion on the bottom surface of the substrate.
Samsung Electronics Co., Ltd.


02/04/16
20160037641 
 Electrical component patent thumbnailElectrical component
An electrical component having a first package part of a first plastic compound. The first package part has a first trench-shaped formation.
Micronas Gmbh


02/04/16
20160037633 
 Flexible electronic fiber-reinforced composite materials patent thumbnailFlexible electronic fiber-reinforced composite materials
The present disclosure describes multilayer fiber-reinforced electronic composite materials comprising at least one conductive layer and at least one laminate layer further comprising at least one reinforcing layer. In various embodiments, the conductive layer is a continuous metal layer, an etched-metal layer, a metal ground plane, a metal power plane, or an electronic circuitry layer.
Dsm Ip Assets B.v.


02/04/16
20160037632 
 Laminate, conductive pattern, and  producing laminate patent thumbnailLaminate, conductive pattern, and producing laminate
Provided is a laminate in which at least a layer including a support, a primer layer, a first conductive layer, an insulating layer, and a second conductive layer are laminated, wherein the insulating layer is formed by coating at least a portion of or entirety of a surface of the first conductive layer with a resin composition and drying the resin composition; and the second conductive layer includes a second plating seed layer formed by coating a portion of or entirety of a surface of the insulating layer with a fluid containing a conductive substance, and a second plating layer formed on a surface of the second plating seed layer. This laminate has high adhesion between layers and allows the high adhesion to be maintained even upon exposure to a high-temperature and high-humidity environment..
Dic Corporation


02/04/16
20160037605 
 Apparatus and  operating a luminaire patent thumbnailApparatus and operating a luminaire
An illumination system verifies whether one or more aspects of an output signal provided by a photosensitive transducer fall within a threshold of an expected value for the aspect. The aspect may include a sunrise time, a sunset time, a dawn time, a dusk time, a solar noon time, a solar midnight time, or similar.
Express Imaging Systems, Llc


02/04/16
20160037589 
 Induction cooktop patent thumbnailInduction cooktop
The present disclosure relates to an induction cooktop. The induction cooktop comprises a ceramic cooking surface in connection with a housing.
Whirlpool Corporation


02/04/16
20160037588 

Induction cooker hob and worktop arrangement


An induction cooker hob which includes a cooking plate configured for placing cookware to be heated on an upper side thereof. At least one induction heating element is attached to an averted lower side of the cooking plate.
Electrolux Appliances Aktiebolag


02/04/16
20160037587 

Oil diffusion pump and vacuum film formation device


Provided is an oil diffusion pump equipped with an oil vapor generator capable of eliminating the problems occurring when a heater wire is used as a heating source for an operating oil. The present invention is a vacuum pump for which an oil vapor generator (70) is arranged within a casing (51) and this oil vapor generator is operated to vaporize an operating oil (8), thereby producing oil vapor and this oil vapor is sprayed from a jet (53, 53a) to exhaust intake air.
Shincron Co., Ltd.


02/04/16
20160037586 

Induction heating apparatus


An induction heating apparatus includes a susceptor defining a reaction chamber. A housing is spaced from the susceptor opposite the reaction chamber and defines a port.
Hemlock Semiconductor Corporation


02/04/16
20160037585 

A assigning induction coils of an induction cooking hob and an induction cooking hob


An induction cooking hob and method for assigning induction coils of the hob, so that each coil corresponds with a unique number or identity. The method includes; setting a load onto the hob, so that the load covers only one of the coils, which is provided for a first unique number or first identity; activating a pot detection device for all coils of hob; identifying the coil covered by the load; assigning the first number or identity to the covered coil; storing the unique number or identity in conjunction with the covered induction coil; setting the load onto a further one of the coils, which is provided for a second unique number or second identity; repeating the steps c) to f) for the further coil and second number or identity; and repeating the steps b) to f) for all other coils and corresponding unique numbers or corresponding identities..
Electrolux Appliances Aktiebolag


02/04/16
20160037584 

Method of detecting cookware on an induction hob, induction hob and cooking appliance


A method of detecting cookware (3) on an induction hob (1) including a plurality of induction heating coils (2) each being adapted for heating, in the activated state, cookware (3) placed on the induction hob (1). With the method, detecting cookware (3) is based on signals generated by at least one active induction heating coil (4) through the action of parasitic electromagnetic coupling effects in at least one inactive induction heating coil (6)..
Electrolux Appliances Aktiebolag


02/04/16
20160037522 

Method and system for determining an interval of frequencies in a telecommunications network


A method allows determination of a frequency interval for the emission, by an item of user equipment, of a signal to be sent to a base station in a telecommunications network, the frequency interval being within a predetermined frequency band over which the base station works, the method including the determination of frequency interval, wherein the determination of the frequency interval is achieved from a table of references including maximum power reduction values for the emission of a signal by the item of user equipment so that the power of the signal emitted by the item of user equipment at a predetermined out-of-band frequency is less than a predetermined maximum power limit value.. .
Cassidian Sas


02/04/16
20160037280 

System and tools for enhanced 3d audio authoring and rendering


Improved tools for authoring and rendering audio reproduction data are provided. Some such authoring tools allow audio reproduction data to be generalized for a wide variety of reproduction environments.
Dolby Laboratories Licensing Corporation


02/04/16
20160037269 

Method and feedback suppression


A method and an apparatus reduce feedback in a hearing aid device. The method includes the step of acquiring a first feedback transfer function at a first point in time on a feedback path from a signal processing device via an electro-acoustic transducer, an acoustic signal path from the electro-acoustic transducer to an acousto-electric transducer and via the acousto-electric transducer back to the signal processing device.
Sivantos Pte.ltd


02/04/16
20160037234 

Reproduction apparatus, reproduction method, and program


Disclosed herein is a reproduction apparatus including: a reproduction control information acquisition block configured to acquire reproduction control information for controlling reproduction of content; a reproduction block configured to reproduce, in accordance with the acquired reproduction control information, the content that is distributed; and a control block configured to control an operation of an application program that is executed in operative connection with the content being reproduced in accordance with information associated with the application program and obtained from the acquired reproduction control information.. .
Sony Corporation


02/04/16
20160037209 

Video audio output device and system


According to one embodiment, video audio output device is connected to an electronic device and reproduces a predetermined content together with the electronic device. The video audio output device includes storage, first module, second module, and seamless reproduction controller.
Toshiba Lifestyle Products & Services Corporation


02/04/16
20160037150 

Stereoscopic video and audio recording method, stereoscopic video and audio reproducing method, stereoscopic video and audio recording apparatus, stereoscopic video and audio reproducing apparatus, and stereoscopic video and audio recording medium


The object of the present invention is to provide a stereoscopic video and audio recording method, a stereoscopic video and audio recording medium, a stereoscopic video and audio reproducing method, a stereoscopic video and audio recording apparatus, and a stereoscopic video and audio reproducing apparatus. An audio information storage region for three-dimensional video is arranged in advance, separately from audio information for ordinary two-dimensional video, in a media recording format for recording stereoscopic video and audio.
Mitsubishi Electric Corporation


02/04/16
20160037111 

Negative biased substrate for pixels in stacked image sensors


A pixel cell includes a photodiode disposed within a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. A transfer transistor is disposed within the first semiconductor chip and coupled to the photodiode to transfer the image charge from the photodiode.
Omnivision Technologies, Inc.


02/04/16
20160037098 

Image sensors including semiconductor channel patterns


The inventive concepts relate to image sensors. The image sensor includes a substrate including a floating diffusion region and a pixel circuit, an interlayer insulating layer on the substrate, a contact node and a first electrode on the interlayer insulating layer, a dielectric layer on a top surface of the first electrode, a channel semiconductor pattern on the dielectric layer and connected to the contact node, and a photoelectric conversion layer on the channel semiconductor pattern.
Samsung Electronics Co., Ltd.


02/04/16
20160036937 

Memory system allowing host to easily transmit and receive data


According to one embodiment, a memory system includes a non-volatile semiconductor memory device, a control unit, a memory as a work area, a wireless communication module, and an extension register. The control unit controls the non-volatile semiconductor memory device.
Kabushiki Kaisha Toshiba


02/04/16
20160036531 

Wavelength-reuse fiber-optic transmitters


A fiber-optic transmitter comprises a transmitter optical port, an optical circulator, a semiconductor optical amplifier, and a two-port modulation-averaging structure. The optical circulator has at least three ports, a first one of the three circulator ports being optically coupled to the transmitter optical port.

02/04/16
20160036495 

Proximity sensing using ehf signals


A system for sensing proximity using ehf signals may include a communication circuit configured to transmit via a transducer an em signal at an ehf frequency, and a proximity sensing circuit configured to sense a nearby transducer field-modifying object by detecting characteristics of a signal within the communication circuit. A system for determining distance using ehf signals may include a detecting circuit coupled to a transmitting communication circuit and a receiving communication circuit, both communication circuits being mounted on a first surface.
Keyssa, Inc.


02/04/16
20160036439 

Semiconductor integrated circuit device


According to one embodiment, a semiconductor integrated circuit device includes a first line to which a voltage is applied; a first circuit operating based on a data; a second circuit capable of retaining the data; a third circuit between the first line and the first circuit and capable of shutting off a supply of the voltage to the first circuit; and a fourth circuit including a resistor element, the resistor element connected between the first line and the second circuit. The fourth circuit supplies the voltage to the second circuit via the resistor element in a period in which the third circuit shut off the supply of the voltage to the first circuit..
Kabushiki Kaisha Toshiba


02/04/16
20160036435 

A gate drive circuit for a semiconductor switch


The present application is directed to drive arrangement for semiconductor switches and in particular to a method of driving the gate of a switch with pulses corresponding to turn-on and turn-off commands through separate turn-on and turn-off transformers. The application provides a fail safe reset feature, a more efficient turn-on circuit and an energy recovery circuit for recovering energy from the gate upon turn-off.
Eisergy Limited


02/04/16
20160036434 

Semiconductor integrated circuit device


A semiconductor integrated circuit device includes a power domain area on a semiconductor substrate, that includes a circuit block for executing a predetermined function, a first power source line that receives an external power source voltage, a second power source line that is connected to the circuit block, a first power switch circuit in a peripheral area of the power domain area, that connects the first power source line and the second power source line in response to a first enable signal, and a second power switch circuit in the power domain area, that connects the first power source line and the second power source line in response to a second enable signal.. .
Kabushiki Kaisha Toshiba


02/04/16
20160036430 

Intelligent gate drive unit


An intelligent gate drive unit and related method for controlling one or more semiconductor switches of one or more power modules, the intelligent gate drive unit comprises at least a gate driver and an analog measuring circuit, wherein the gate driver facilitates control of the one or more semiconductor switches and wherein the analog measuring circuit facilitates measuring the switch voltage when the one or more semiconductor switches are in a conducting mode.. .
Kk Wind Solutions A/s


02/04/16
20160036419 

Method and calibrating cmos inverter


A circuit and method for calibrating cmos (complementary metal-oxide semiconductor) inverters are provided. In a circuit, a first tunable cmos inverter, controlled by a control signal, receives a first voltage from a first circuit node and outputs a second voltage to a second circuit node.
Realtek Semiconductor Corp.


02/04/16
20160036418 

Transmission drive circuit and semiconductor integrated circuit device


Provided is a transmission drive circuit which can reduce distortions of a transmission signal and transmission noise, and is isolable from a signal line. A transmission drive circuit 700 includes a drive transistor 10 and an isolation diode 31 connected between a node n1 coupled to a signal line sl commonly used to propagate a transmission signal and a reception signal and a power source line hvp, and further includes an isolation diode 32 and a drive transistor 20 connected between the node n1 and a voltage line hvm.
Hitachi, Ltd.


02/04/16
20160036416 

Elastic wave device with integrated inductor


An elastic wave device includes an interdigital transducer (idt) electrode disposed on an upper surface of a piezoelectric substrate, a wiring electrode disposed on the upper surface of the piezoelectric substrate and connected to the idt electrode, and a first insulator layer disposed on the upper surface of the piezoelectric substrate. The first insulator layer seals the idt electrode and the wiring electrode and includes a first resin and a first filler.
Skyworks Panasonic Filter Solutions Japan Co., Ltd.


02/04/16
20160036412 

Ultrasonic device and probe as well as electronic apparatus and ultrasonic imaging apparatus


An acoustic matching layer is formed on individual ultrasonic transducer elements on a base. Electric conductors are arranged between adjacent ultrasonic transducer elements, the electric conductors being connected to electrodes of the ultrasonic transducer elements.
Seiko Epson Corporation


02/04/16
20160036406 

Integrated microelectromechanical system devices and methods for making the same


Integrated microelectromechanical system (“mems”) devices and methods for making the same. The integrated mems device comprises a substrate (200) with first electronic circuitry (206) formed thereon, as well as a mems filter device (100).
Harris Corporation


02/04/16
20160036397 

Semiconductor amplifier circuit


According to one embodiment, a semiconductor amplifier circuit includes: a first amplifier circuit including first and second p-type transistors; a second amplifier circuit including first and second n-type transistors; and first to seventh current mirror circuits. The first and second current mirror circuits are connected to drains of the first and second p-type transistors.
Kabushiki Kaisha Toshiba


02/04/16
20160036382 

Low power wide tuning range oscillator


A wide tuning range oscillator system uses multiple active cores with cross-coupled transistors and multiple tapped inductors having windings that can be connected to circuit nodes. These active cores are connected to a pair of symmetric tapping points and are switched on/off by biasing elements.
Texas Instruments Incorporated


02/04/16
20160036376 

Techniques for optimizing photo-voltaic power via inductive coupling


Techniques for optimizing power production from photo-voltaic systems using, e.g., inductive coupling, are provided. In one aspect, a method of optimizing photo-voltaic generated power from a string of photo-voltaic devices is provided.
International Business Machines Corporation


02/04/16
20160036343 

Semiconductor device


Converter output terminals of a converter are located adjacent to each other on a first side and an external terminal for external connection of a composite module is located adjacent to the converter output terminal. Ac input terminals of the converter are located on a second side.
Mitsubishi Electric Corporation


02/04/16
20160036342 

Power conversion device


Semiconductor switching elements are individually inserted between a plurality of power conversion units provided in parallel with each other through a dc link portion and a dc power supply unit for supplying dc power to each of the power conversion units to restrict the dc power supplied to the respective power conversion units. A control circuit monitors a short-circuit current occurring in each of the power conversion units and turns off the semiconductor switching element connected to the power conversion unit where the short-circuit current flows to stop the power supplied to the power conversion unit..
Fuji Electric Co., Ltd.


02/04/16
20160036331 

Semiconductor device and dc-to-dc converter


In general, according to one embodiment, a semiconductor device includes a device main body, a semiconductor substrate. The device main body includes a semiconductor substrate mounting part and a first conductor provided around the semiconductor substrate mounting part.
Kabushiki Kaisha Toshiba


02/04/16
20160036319 

Power factor correction circuit


A power factor correction circuit includes a rectifier that rectifies ac power supply voltage, a series circuit of an inductor and a semiconductor switch connected between the rectifier circuit output terminals, and a series circuit of a diode and a smoothing capacitor connected to both ends of the semiconductor switch, a load connected to both ends of the smoothing capacitor, so that the power factor on the input side of the rectifier circuit is corrected by the switching operation of the semiconductor switch. This power factor correction circuit includes a control circuit that controls the switching frequency of the semiconductor switch such that the switching frequency becomes maximum when the ripple of a current flowing through the inductor becomes maximum.
Fuji Electric Co., Ltd.


02/04/16
20160036316 

Insulated gate semiconductor device


An insulated gate semiconductor device includes an insulated gate semiconductor element, an output current detection unit, a voltage detection unit, and a heat generation amount suppression unit. The insulated gate semiconductor element on-operates by receiving a first gate voltage at a control terminal, and switches and outputs an input voltage to a load.
Fuji Electric Co., Ltd.


02/04/16
20160036315 

Drive circuit and semiconductor device


Malfunction can be reliably avoided even when a signal that drives a high side power device is not normally transmitted in a level shift circuit. In a drive circuit, a pulse generator circuit generates a set signal and reset signal that causes a high side power device to be turned on or off.
Fuji Electric Co., Ltd.


02/04/16
20160036219 

Esd state-controlled semiconductor-controlled rectifier


Circuits and methods of fabricating circuits that provide electrostatic discharge protection, as well as methods of protecting an integrated circuit from an electrostatic discharge event at an input/output pin. The protection circuit includes a silicon-controlled rectifier having a well and an anode in the well.
International Business Machines Corporation


02/04/16
20160036198 

Housing and producing a housing


A housing for an optoelectronic semiconductor component includes a housing body having a mounting plane and a leadframe with a first connection conductor and a second connection conductor. The housing body deforms the leadframe in some regions.
Osram Opto Semiconductors Gmbh


02/04/16
20160036197 

Nitride semiconductor light emitting device


A nitride semiconductor light emitting device includes a first coat film of aluminum nitride or aluminum oxynitride formed at a light emitting portion and a second coat film of aluminum oxide formed on the first coat film. The thickness of the second coat film is at least 80 nm and at most 1000 nm.
Sharp Kabushiki Kaisha


02/04/16
20160036166 

Communications connectors including low impedance transmission line segments that improve return loss and related methods


A communications connector includes a printed circuit board having a first internal conductive layer and first and second external conductive layers that are stacked with dielectric layers therebetween. The printed circuit board has input terminals, output terminals and signal current carrying conductive paths which electrically connect respective ones of the input and output terminals.
Commscope, Inc. Of North Carolina


02/04/16
20160036142 

Flexible connector and methods of manufacture


A flexible connector includes a flexible substrate having a plurality of conductive pads and a plurality of conductive polymer springfingers. Each conductive polymer springfinger extends between a first end and a second end.
Tyco Electronics Corporation


02/04/16
20160036118 

Hybrid radio frequency / inductive loop charger


Biometric monitoring devices, including various technologies that may be implemented in such devices, are discussed herein. Additionally, techniques, systems, and apparatuses are discussed herein for providing a hybrid antenna including an rf radiator and an electrically coupled inductive loop.
Fitbit, Inc.


02/04/16
20160036060 

Composite electrode for flow battery


A composite electrode adapted for use in a flow battery stack system has a carbon felt stratum forming a semi-porous reaction zone and a carbon foam stratum forming a porous flow path zone. The composite electrode is less compressible than prior art electrodes having similar conductivity and specific surface areas.
Concurrent Technologies Corporation


02/04/16
20160036034 

Method for injecting electrolyte


A method for injecting an electrolyte includes heating a case in which an electrode assembly is accommodated, and injecting an electrolyte into the case after the heating of the case. Here, the heating of the case may include heating the case through high-frequency induction heating using a coil.
Lg Chem, Ltd.


02/04/16
20160036005 

Display panel and display device


The present invention relates to the field of display technology, and particularly to a display panel and a display device comprising the display panel. The display panel comprises a substrate, which is divided into a plurality of sub-pixel areas, each of which comprises a thin film transistor and an organic light-emitting diode device provided above the thin film transistor, wherein, a pixel define layer and a conductive layer are provided above the thin film transistor and below the organic light-emitting diode device, the pixel define layer is used for defining a light-transmissive region and a non-light-transmissive region of the sub-pixel area, an upper surface of the conductive layer and an upper surface of the pixel define layer are in the same plane, and the conductive layer is electrically connected to a drain of the thin film transistor..
Boe Technology Group Co., Ltd.


02/04/16
20160035995 

Organic light emitting device and manufacturing method thereof


An organic light emitting device includes an anode, the anode including a conductive polymer, a fluorine-containing organic material, and metal nanoparticles, a cathode facing the anode, and an emission layer between the anode and the cathode.. .
Postech Academy-industry Foundation


02/04/16
20160035987 

Organic semiconducting blend


A blend for preparing a semiconducting layer an organic electronic device comprises a polymer, a first non-polymeric semiconductor, a second non-polymeric semiconductor and a third non-polymeric semiconductor. The blend enables higher concentration solutions of semiconductor and a broader solution processing window as compared to blends comprising one polymer and one non-polymeric semiconductor.
Cambridge Display Technology Limited


02/04/16
20160035984 

Organic thin film transistor, organic semiconductor thin film, and organic semiconductor material


An organic thin film transistor containing a compound represented by the following formula in a semiconductor active layer has a high carrier mobility and a small change in the threshold voltage after repeated driving. Z represents a substituent having a length of 3.7 Å or less, and at least one of r1 to r8 represents -l-r wherein l represents alkylene, etc., and r represents alkyl, etc..
Fujifilm Corporation


02/04/16
20160035981 

Organic semiconductor compound thin film, fabricating the same and electronic device using the same


Disclosed herein is an organic semiconductor compound thin film. The organic semiconductor compound thin film includes a conjugated organic material including an unshared electron pair-containing sulfur or nitrogen atom and exhibiting semiconductivity, and a polymeric organic acid bonded to the conjugated organic material through hydrogen bonding and protonation.
Gwangju Institute Of Science And Technology


02/04/16
20160035976 

Semiconductor memory device and manufacturing the same


Provided are a variable resistance semiconductor memory device which changes its resistance without being affected by an underlying layer and is suitable as a memory device of increased capacity, and a method of manufacturing the same. The semiconductor memory device in the present invention includes: a first contact plug formed inside a first contact hole penetrating through a first interlayer insulating layer; a lower electrode having a flat top surface and is thicker above the first interlayer insulating layer than above the first contact plug; a variable resistance layer; and an upper electrode.
Panasonic Intellectual Property Management Co., Ltd.


02/04/16
20160035972 

Electronic device comprising semiconductor memory using metal electrode and metal compound layer surrounding sidewall of the metal electrode


This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a lower electrode, a variable resistance element over the lower electrode, an upper electrode disposed over the variable resistance element and including metal, and a metal compound layer configured to surround a side of the upper electrode.
Sk Hynix Inc.


02/04/16
20160035958 

Manufacturing process of the thermoelectric conversion element


A manufacturing process of the thermoelectric conversion element is provided, wherein the system using semiconductor process technology to the construction of the thermoelectric conversion element nanoscale thermoelectric effect to increase, and the use of different type and surface state of the sample to increase the thermoelectric conversion element thermoelectric figure of merit. Through the use of a specific thickness of deposition of nanostructures on a nanoscale roughening of the substrate cannot affect the conductivity of thermoelectric materials under, and also can improve the seebeck coefficient and lower thermal conductivity in order o significantly enhance the thermoelectric figure of merit..
National Tsing Hua University


02/04/16
20160035951 

Optical semiconductor element mounting package, and optical semiconductor device using the same


An optical semiconductor element mounting package that has good adhesion between the resin molding and the lead electrodes and has excellent reliability is provided, as well as an optical semiconductor device using the package is also provided. The optical semiconductor element mounting package having a recessed part that serves as an optical semiconductor element mounting region, wherein the package is formed by integrating: a resin molding composed of a thermosetting light-reflecting resin composition, which forms at least the side faces of the recessed part; and at least a pair of positive and negative lead electrodes disposed opposite each other so as to form part of the bottom face of the recessed part, and there is no gap at a joint face between the resin molding and the lead electrodes..
Hitachi Chemical Company, Ltd.


02/04/16
20160035941 

High index dielectric film to increase extraction efficiency of nanowire leds


Various embodiments include semiconductor devices, such as nanowire leds, that include a plurality of first conductivity type semiconductor nanowire cores located over a support, a plurality of second conductivity type semiconductor shells extending over and around the respective nanowire cores, and a layer of a high index of refraction material over at least a portion of a surface of at least one of the nanowire cores and the shells, wherein the high index of refraction material has an index of refraction that is between about 1.4 and about 4.5. Light extraction efficiency may be improved..
Glo Ab


02/04/16
20160035939 

Semiconductor light emitting element, light emitting device, and manufacturing semiconductor light emitting element


A semiconductor light emitting element includes a stacked body, a first metal layer, and a second metal layer. The stacked body includes a first semiconductor layer, a second semiconductor layer, and a light emitting layer.
Kabushiki Kaisha Toshiba


02/04/16
20160035938 

Semiconductor light emitting device, nitride semiconductor layer, and forming nitride semiconductor layer


According to an embodiment, a semiconductor light emitting device includes a foundation layer, a first semiconductor layer, a light emitting layer, and a second semiconductor layer. The foundation layer has an unevenness having recesses, side portions, and protrusions.
Kabushiki Kaisha Toshiba


02/04/16
20160035936 

Patterned layer design for group iii nitride layer growth


A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group iii nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings.
Sensor Electronic Technology, Inc.


02/04/16
20160035935 

Ultraviolet light emitting device separated from growth substrate and fabricating the same


A uv light emitting device and a method for fabricating the same are disclosed. The method includes forming a first super-lattice layer including alxga(1-x)n on a substrate, forming a sacrificial layer including alzga(1-z)n on the first super-lattice layer, partially removing the sacrificial layer, forming an epitaxial layer on the sacrificial layer, and separating the substrate from the epitaxial layer, wherein the sacrificial layer includes voids, the substrate is separated from the epitaxial layer at the sacrificial layer, and forming an epitaxial layer includes forming an n-type semiconductor layer including n-type aluga(1-u)n (0<u≦z≦x<1).
Seoul Viosys Co., Ltd.


02/04/16
20160035934 

Nitride semiconductor structure and semiconductor light emitting device including the same


A nitride semiconductor structure and a semiconductor light emitting device are revealed. The semiconductor light emitting device includes a substrate disposed with a first type doped semiconductor layer and a second type doped semiconductor layer.
Genesis Photonics Inc.


02/04/16
20160035932 

Nano-structured light-emitting manufacturing the same


A nano-structured light-emitting device including a first semiconductor layer; a nano structure formed on the first semiconductor layer. The nano structure includes a nanocore, and an active layer and a second semiconductor layer that are formed on a surface of the nanocore, and of which the surface is planarized.
Samsung Electronics Co., Ltd.


02/04/16
20160035929 

Lateral single-photon avalanche diode and producing a lateral single-photon avalanche diode


The lateral single-photon avalanche diode comprises a semiconductor body comprising a semiconductor material of a first type of electric conductivity, a trench in the semiconductor body, and anode and cathode terminals. A junction region of the first type of electric conductivity is located near the sidewall of the trench, and the electric conductivity is higher in the junction region than at a farther distance from the sidewall.
Ams Ag


02/04/16
20160035928 

Photodiode


According to one embodiment, a photodiode includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, and a film. The second semiconductor layer is provided in the first semiconductor layer.
Kabushiki Kaisha Toshiba


02/04/16
20160035924 

Configurable backplane interconnecting led tiles


Relatively small, electrically isolated led tiles or pv tiles are fabricated having an anode electrode and a cathode electrode. The led tiles contain microscopic printed leds that are connected in parallel by two conductive layers sandwiching the leds.
Nthdegree Technologies Worldwide Inc.


02/04/16
20160035916 

Multifunctional nanostructured metal-rich metal oxides


A transparent conductive oxide (tco) material includes a metal-rich metal oxide having an average formula (m1, m2 . .
The Trustees Of Dartmouth College


02/04/16
20160035915 

Semiconductor substrate and producing the same, photovoltaic cell element, and photovoltaic cell


The semiconductor substrate of the present invention contains a semiconductor layer and an impurity diffusion layer containing at least one impurity atom selected from the group consisting of an n-type imparity atom and a p-type impurity atom and at least one metallic atom selected from the group consisting of k, na, li, ba, st, ca, mg, be, zn, pb, cd, v, sn, zr, mo, la, nb, ta, y, ti, ge, te, and lu.. .
Hitachi Chemical Company, Ltd.


02/04/16
20160035913 

Solid state detection devices, methods of making and methods of using


The present application is directed to a solid state device for detecting neutrons. The device includes a semiconductor substrate having pores.
Lgs Innovations Llc


02/04/16
20160035907 

Solar cell module


A solar cell module includes a plurality of solar cells each including a semiconductor substrate and first and second electrode parts each having a different polarity, a plurality of interconnectors for electrically connecting the plurality of solar cells, a conductive adhesive for electrically connecting each of the plurality of interconnectors to the corresponding electrode part of each of the plurality of solar cells, and at least one insulating adhesive portion for temporarily fixing the plurality of interconnectors to the corresponding electrode part. The at least one insulating adhesive portion includes an adhesive having adhesiveness to attach the interconnector to the corresponding electrode part at the room temperature..
Lg Electronics Inc.


02/04/16
20160035906 

Planar semiconductor esd device and making same


An esd device is provided for protecting a circuit from electrostatic discharge, and includes a planar diode having an anode and a cathode. The anode is electrically coupled to a signal path of the circuit, and the cathode is electrically coupled to a ground of the circuit.
Globalfoundries Inc.


02/04/16
20160035905 

Semiconductor devices


Provided are semiconductor devices. A semiconductor device includes a first well formed in a substrate; an element isolation layer formed on the first well; a second well formed in the first well on a first side of the element isolation layer; a third well formed in the second well, the third well has a higher concentration of impurities than the second well; a first electrode electrically connected to the third well; a fourth well formed in the first well on a second side of the element isolation layer; a fifth well formed in the fourth well, the fifth well has a different conductivity type from the fourth well; a second electrode electrically connected to the fifth well; and a sixth well overlapping the fourth well, the sixth well has a lower concentration of impurities than the fourth well..
Samsung Electronics Co., Ltd.


02/04/16
20160035903 

Thin-film transistor


Thin-film transistor includes column-shaped protrusion portion having a side surface and protruding from a main surface of the substrate, a gate insulating layer including a first layer and a second layer, at least part of the gate insulating layer being in a channel region extending along the side surface, a gate electrode in contact with the gate insulating layer, a source electrode and a drain electrode isolated from one another, at least part of one of the source electrode and the drain electrode overlap the protrusion portion and the other being in a region that does not overlap the protrusion portion or the one electrode, and a semiconductor layer in contact with at least part of the source electrode, at least part of the drain electrode, and at least part of the gate insulating layer in the channel region directly or with a functional layer interposed.. .
Sumitomo Chemical Company, Limited


02/04/16
20160035902 

Transistor and display device


It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material.
Semiconductor Energy Laboratory Co., Ltd.


02/04/16
20160035901 

Fabricating thin film transistor, thin film transistor and display panel


Embodiments of the invention provide a fabricating method a thin film transistor, a thin film transistor and a display panel, so as to improve carrier mobility in the polycrystalline silicon. The fabricating method a thin film transistor comprises following m1, depositing an inducing layer on a substrate; m2, etching a recess in the inducing layer by an etching process, the recess having an edge with a prescribed shape; m3, depositing an amorphous silicon layer in the recess having an edge with a prescribed shape, and inducing the amorphous silicon layer to form a polycrystalline silicon layer by crystallization method, polycrystalline silicon grains in the polycrystalline silicon layer arranging in a direction vertical to the edge of the recess by the limitation of the edge of the recess, and the polycrystalline silicone layer and the inducing layer together forming a semiconductor layer; and m4, forming a gate insulating layer, a gate, a passivation layer and a source and a drain connecting with the semiconductor layer sequentially on the semiconductor layer..
Beijing Boe Optoelectronics Technology Co., Ltd.


02/04/16
20160035900 

Thin film transistor substrate and display panel using the same


A thin film transistor includes a gate electrode, a semiconductor layer, a source electrode, a drain electrode, a first protective layer, and a second protective layer. The gate electrode is disposed on a substrate.
Innolux Corporation


02/04/16
20160035898 

Semiconductor device and manufacturing semiconductor device using metal oxide


A method of manufacturing a semiconductor device using a metal oxide includes forming a metal oxide layer on a substrate, forming an amorphous semiconductor layer on the metal oxide layer, and forming a polycrystalline semiconductor layer by crystallizing the amorphous semiconductor layer using the metal oxide layer.. .
Samsung Electronics Co., Ltd.


02/04/16
20160035897 

Semiconductor device


A transistor whose channel is formed in a semiconductor having dielectric anisotropy is provided. A transistor having a small subthreshold swing value is provided.
Semiconductor Energy Laboratory Co., Ltd.


02/04/16
20160035896 

Semiconductor device, manufacturing method thereof, and electronic device


A gate insulating film is formed over an oxide semiconductor film. A gate electrode is formed over the gate insulating film.
Semiconductor Energy Laboratory Co., Ltd.


02/04/16
20160035895 

Oxide semiconductor target, oxide semiconductor film and producing same, and thin film transistor


The invention provides an oxide semiconductor target including an oxide sintered body including zinc, tin, oxygen, and aluminum in a content ratio of from 0.005% by mass to 0.2% by mass with respect to the total mass of the oxide sintered body, in which the content ratio of silicon to the total mass of the oxide sintered body is less than 0.03% by mass.. .
Hitachi Metals, Ltd.


02/04/16
20160035893 

Pixel structure and manufacturing method thereof


A manufacturing method of a pixel structure is provided, which includes following steps. A gate and a gate insulating layer are formed on a substrate.
Chunghwa Picture Tubes, Ltd.


02/04/16
20160035891 

Stress in n-channel field effect transistors


A fin field-effect transistor (finfet) includes a gate stack on a surface of a semiconductor fin. The semiconductor fin may include a capping material and a stressor material.
Qualcomm Incorporated


02/04/16
20160035888 

Junction fet semiconductor device with dummy mask structures for improved dimension control and forming the same


A method for semiconductor devices on a substrate includes using gate structures which serve as active gate structures in a mosfet region, as dummy gate structures in a jfet region of the device. The dummy gate electrodes are used as masks and determine the spacing between gate regions and source/drain regions, the width of the gate regions, and the spacing between adjacent gate regions according to some embodiments, thereby forming an accurately dimensioned transistor channel..
Taiwan Semiconductor Manufacturing Co., Ltd.


02/04/16
20160035887 

Semiconductor device and multiple gate field effect transistor


The present invention provides a semiconductor device, which includes a substrate, a first gate electrode, a second gate electrode, a source region and a drain region, wherein the first gate electrode and the second gate electrode are embedded in the substrate respectively; the source region is formed in the substrate, and at least a portion of the source region is disposed between the first gate electrode and the second gate electrode; and the drain region is formed in the substrate, and at least a portion of the drain region is disposed between the first gate electrode and the second gate electrode.. .
Realtek Semiconductor Corp.


02/04/16
20160035886 

Semiconductor device and formation thereof


A semiconductor device and method of formation are provided. The semiconductor device includes a first active region adjacent a channel, the channel, and a second active region adjacent the channel.
Taiwan Semiconductor Manufacturing Company Limited


02/04/16
20160035885 

N-channel double diffusion mos transistor, and semiconductor composite device


A mos transistor includes a p-type semiconductor substrate, a p-type epitaxial layer, and an n-type buried layer provided in a boundary between the semiconductor substrate and the epitaxial layer. In a p-type body layer provided in a surface portion of the epitaxial layer, an n-type source layer is provided to define a double diffusion structure together with the p-type body layer.
Rohm Co., Ltd.


02/04/16
20160035884 

Semiconductor device and manufacturing the same


A semiconductor device includes a semiconductor substrate, and a p-well and an n-type drift region disposed in the semiconductor substrate. The p-well includes a lower well region and an upper well region disposed above the lower well region.
Semiconductor Manufacturing International (shanghai) Corporation


02/04/16
20160035883 

Reduction of degradation due to hot carrier injection


In a general aspect, a high-voltage metal-oxide-semiconductor (hvmos) device can include comprising a first gate dielectric layer disposed on a channel region of the hvmos device and a second gate dielectric layer disposed on at least a portion of a drift region of the hvmos device. The drift region can be disposed laterally adjacent to the channel region.
Fairchild Semiconductor Corporation


02/04/16
20160035882 

Multiple semiconductor device trenches per cell pitch


A semiconductor device includes a plurality of field plate trenches formed in a semiconductor substrate, a plurality of gate trenches formed in the semiconductor substrate and spaced apart from the field plate trenches, and a plurality of device cells having a cell pitch defined by a distance from one side of a field plate trench to the same side of an adjacent field plate trench. Each device cell includes a first doped region of a first conductivity type and a second doped region of a second conductivity type adjacent the first doped region in a part of the semiconductor substrate disposed between the adjacent field plate trenches that define the cell pitch.
Infineon Technologies Austria Ag


02/04/16
20160035881 

Semiconductor device and manufacturing the same


A super junction mosfet includes a parallel pn layer including a plurality of pn junctions and in which an n-type drift region and a p-type partition region interposed between the pn junctions are alternately arranged and contact each other, a mos gate structure on the surface of the parallel pn layer, and an n-type buffer layer in contact with an opposite main surface. The impurity concentration of the buffer layer is equal to or less than that of the n-type drift region.
Fuji Electric Co., Ltd.


02/04/16
20160035880 

Power mosfet, an igbt, and a power diode


Super-junction mosfets by trench fill system requires void-free filling epitaxial growth. This may require alignment of plane orientations of trenches in a given direction.
Renesas Electronics Corporation


02/04/16
20160035879 

Semiconductor device


In general, according to one embodiment, a semiconductor device includes, a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions, a fourth semiconductor region, a fifth semiconductor region, and a gate electrode. The third semiconductor region includes a first portion and a second portion.
Kabushiki Kaisha Toshiba


02/04/16
20160035878 

Finfet with dielectric isolation after gate module for improved source and drain region epitaxial growth


A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures.
International Business Machines Corporation


02/04/16
20160035877 

Finfet having highly doped source and drain regions


A method of forming a semiconductor device that includes forming an in-situ doped semiconductor material on a semiconductor substrate, and forming fin structures from the in-situ doped semiconductor material. A sacrificial channel portion of the fin structures may be removed, wherein a source region and a drain region portion of the fin structures of the in-situ doped semiconductor material remain.
International Business Machines Corporation


02/04/16
20160035876 

Fin end spacer for preventing merger of raised active regions


After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins.
International Business Machines Corporation


02/04/16
20160035875 

Fin end spacer for preventing merger of raised active regions


After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins.
International Business Machines Corporation


02/04/16
20160035874 

Finfet device


A fin-type field-effect transistor (finfet) device includes a plurality of fins formed over a substrate. The semiconductor device further includes a dielectric layer filled in a space between each fin and over a first portion of the plurality of fins and a dielectric trench formed in the dielectric layer.
Taiwan Semiconductor Manufacturing Company, Ltd.


02/04/16
20160035872 

Method for the formation of silicon and silicon-germanium fin structures for finfet devices


A substrate layer formed of a first semiconductor material includes adjacent first and second regions. Fin structures are formed from the substrate layer in both the first and second regions.
International Business Machines Corporation


02/04/16
20160035871 

Lateral/vertical semiconductor device


A lateral semiconductor device and/or design including a space-charge generating layer and a set of electrodes located on an opposite side of a device channel as contacts to the device channel is provided. The space-charge generating layer is configured to form a space-charge region to at least partially deplete the device channel in response to an operating voltage being applied to the contacts to the device channel..
Sensor Electronic Technology, Inc.


02/04/16
20160035869 

Semiconductor device


A semiconductor device formed on a substrate of a first conductivity type, including a base layer of a second conductivity disposed on a first face of the substrate, an anode layer with a higher dopant amount in a portion of the base layer, an igbt region formed on the base layer, a diode region formed on the anode layer, a trench extending from the top of the igbt and diode regions in to the substrate. The area occupied by the diode region is different from the area occupied by the igbt region, but they share collector and emitter electrodes.
Kabushiki Kaisha Toshiba


02/04/16
20160035868 

Semiconductor device and semiconductor device manufacturing method


A semiconductor device and manufacturing method achieve miniaturization, prevent rise in threshold voltage and on-state voltage, and prevent decrease in breakdown resistance. N+-type emitter region and p++-type contact region are repeatedly alternately disposed in a first direction in which a trench extends in stripe form in a mesa portion sandwiched between trench gates.
Fuji Electric Co., Ltd.


02/04/16
20160035867 

Reverse-conducting igbt


A reverse-conducting igbt includes a semiconductor body having a drift region arranged between first and second surfaces. The semiconductor body further includes first collector regions arranged at the second surface and in ohmic contact with a second electrode, backside emitter regions and in ohmic contact with the second electrode.
Infineon Technologies Ag


02/04/16
20160035866 

Semiconductor device and manufacturing method thereof


An object is to provide a thin film transistor using an oxide semiconductor layer, in which contact resistance between the oxide semiconductor layer and source and drain electrode layers is reduced and electric characteristics are stabilized. Another object is to provide a method for manufacturing the thin film transistor.
Semiconductor Energy Laboratory Co., Ltd.


02/04/16
20160035865 

Method of manufacturing semiconductor device


A first conductor is formed over a substrate. A first insulator is formed over the first conductor.
Semiconductor Energy Laboratory Co., Ltd.


02/04/16
20160035864 

Fin end spacer for preventing merger of raised active regions


After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins.
International Business Machines Corporation


02/04/16
20160035863 

Methods of forming stressed channel regions for a finfet semiconductor device and the resulting device


An illustrative method includes forming a finfet device above structure comprising a semiconductor substrate, a first epi semiconductor material and a second epi semiconductor material that includes forming an initial fin structure that comprises portions of the semiconductor substrate, the first epi material and the second epi material, recessing a layer of insulating material such that a portion, but not all, of the second epi material portion of the initial fin structure is exposed so as to define a final fin structure, forming a gate structure above and around the final fin structure, removing the first epi material of the initial fin structure and thereby define an under-fin cavity under the final fin structure and substantially filling the under-fin cavity with a stressed material.. .
International Business Machines Corporation


02/04/16
20160035862 

Field plate trench transistor and producing it


A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure.
Infineon Technologies Austria Ag


02/04/16
20160035861 

Methods of manufacturing semiconductor devices


In a method of manufacturing a semiconductor device, a dummy gate structure is formed on a substrate. A first spacer layer is formed on the substrate to cover the dummy gate structure.

02/04/16
20160035860 

Contact techniques and configurations for reducing parasitic resistance in nanowire transistors


Embodiments of the present disclosure provide contact techniques and configurations for reducing parasitic resistance in nanowire transistors. In one embodiment, an apparatus includes a semiconductor substrate, an isolation layer formed on the semiconductor substrate, a channel layer including nano-wire material formed on the isolation layer to provide a channel for a transistor, and a contact coupled with the channel layer, the contact being configured to surround, in at least one planar dimension, nanowire material of the channel layer and to provide a source terminal or drain terminal for the transistor..
Intel Corporation


02/04/16
20160035859 

Igbt and manufacturing the same


An igbt has an emitter region, a top body region that is formed below the emitter region, a floating region that is formed below the top body region, a bottom body region that is formed below the floating region, a trench, a gate insulating film that covers an inner face of the trench, and a gate electrode that is arranged inside the trench. When a distribution of a concentration of p-type impurities in the top body region and the floating region, which are located below the emitter region, is viewed along a thickness direction of a semiconductor substrate, the concentration of the p-type impurities decreases as a downward distance increases from an upper end of the top body region that is located below the emitter region, and assumes a local minimum value at a predetermined depth in the floating region..
Toyota Jidosha Kabushiki Kaisha


02/04/16
20160035858 

Finfet having highly doped source and drain regions


A method of forming a semiconductor device that includes forming an in-situ doped semiconductor material on a semiconductor substrate, and forming fin structures from the in-situ doped semiconductor material. A sacrificial channel portion of the fin structures may be removed, wherein a source region and a drain region portion of the fin structures of the in-situ doped semiconductor material remain.
International Business Machines Corporation


02/04/16
20160035857 

Extended contact area using undercut silicide extensions


The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a contact silicide on a source-drain (s-d) region of a field effect transistor (fet) having extensions by using an undercut etch and a salicide process. A method of forming a contact silicide extension is disclosed.
International Business Machines Corporation


02/04/16
20160035856 

Semiconductor structure including a ferroelectric transistor and the formation thereof


An illustrative semiconductor structure described herein includes a substrate including a logic transistor region, a ferroelectric transistor region and an input/output transistor region. A logic transistor is provided at the logic transistor region.
Globalfoundries Inc.


02/04/16
20160035854 

Method for fabricating semiconductor device


A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a nmos region and a pmos region; forming a dummy gate on each of the nmos region and the pmos region respectively; removing the dummy gates from each of the nmos region and the pmos region; forming a n-type work function layer on the nmos region and the pmos region; removing the n-type work function layer in the pmos region; forming a p-type work function layer on the nmos region and the pmos region; and depositing a low resistance metal layer on the p-type work function layer of the nmos region and the pmos region..
United Microelectronics Corp.


02/04/16
20160035853 

Semiconductor device


In a semiconductor device in the present disclosure, a first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an interface with a second nitride semiconductor layer. In plan view, an electrode portion is provided between a first electrode and a second electrode with a space between the first electrode and the second electrode, and a space between the second electrode and the electrode portion is smaller than the space between the first electrode and the electrode portion.
Panasonic Intellectual Property Management Co., Ltd.


02/04/16
20160035851 

Epitaxial metallic transition metal nitride layers for compound semiconductor devices


A method for integrating epitaxial, metallic transition metal nitride (tmn) layers within a compound semiconductor device structure. The tmn layers have a similar crystal structure to relevant semiconductors of interest such as silicon carbide (sic) and the group iii-nitrides (iii-ns) such as gallium nitride (gan), aluminum nitride (aln), indium nitride (inn), and their various alloys.

02/04/16
20160035850 

Semiconductor device and manufacturing method


A semiconductor device includes a trench extending into a semiconductor body from a first surface. At least one of a ternary carbide and a ternary nitride is in the trench..
Infineon Technologies Ag


02/04/16
20160035849 

Strained channel of gate-all-around transistor


The disclosure relates to a semiconductor device. An exemplary structure for a nanowire structure comprises a first semiconductor material having a first lattice constant and a first linear thermal expansion constant; and a second semiconductor material having a second lattice constant and a second linear thermal expansion constant surrounding the first semiconductor material, wherein a ratio of the first lattice constant to the second lattice constant is from 0.98 to 1.02, wherein a ratio of the first linear thermal expansion constant to the second linear thermal expansion constant is greater than 1.2 or less than 0.8..
Taiwan Semiconductor Manufacturing Company, Ltd.


02/04/16
20160035846 

High density mosfet array with self-aligned contacts enhancement plug and method


A semiconductor substrate comprises epitaxial region, body region and source region; an array of interdigitated active nitride-capped trench gate stacks (anctgs) and self-guided contact enhancement plugs (sgcep) disposed above the semiconductor substrate and partially embedded into the source region, the body region and the epitaxial region forming the trench-gated mosfet array. Each anctgs comprises a stack of a polysilicon trench gate embedded in a gate oxide shell and a silicon nitride spacer cap covering the top of the polysilicon trench gate; each sgcep comprises a lower intimate contact enhancement section (ices) in accurate registration to its neighboring anctgs; an upper distal contact enhancement section (dces) having a lateral mis-registration (ltmsrg) to the neighboring anctgs; and an intervening tapered transitional section (tts) bridging the ices and the dces; a patterned metal layer atop the patterned dielectric region atop the mosfet array forms self-guided source and body contacts through the sgcep..
Alpha And Omega Semiconductor Incorporated


02/04/16
20160035845 

Vertical semiconductor device having semiconductor mesas with side walls and a pn-junction extending between the side walls


A vertical semiconductor device includes a semiconductor body having a backside and extending, in a peripheral area and in a vertical direction substantially perpendicular to the backside, from the backside to a first surface of the semiconductor body, the body including in an active area spaced apart semiconductor mesas extending, in the vertical direction, from the first surface to a main surface arranged above the first surface, in a vertical cross-section the peripheral area extending between the active area and an edge that extends between the back-side and the first surface, in the vertical cross-section each of the mesas including first and second side walls, a first pn-junction extending between the first and second side walls, and a conductive region in ohmic contact with the mesa and extending from the main surface into the mesa. Gate electrodes are arranged between adjacent mesas and extend across the first pn-junctions..
Infineon Technologies Ag


02/04/16
20160035844 

Semiconductor device and manufacturing the same


A semiconductor device with enhanced reliability in which a gate electrode for a trench-gate field effect transistor is formed through a gate insulating film in a trench made in a semiconductor substrate. The upper surface of the gate electrode is in a lower position than the upper surface of the semiconductor substrate in an area adjacent to the trench.
Renesas Electronics Corporation


02/04/16
20160035842 

Semiconductor device including a trench at least partially filled with a conductive material in a semiconductor substrate and manufacturing a semiconductor device


A semiconductor device includes a semiconductor substrate and a first trench extending into or through the semiconductor substrate from a first side. The first trench is at least partially filled with a conductive material and electrically connected to the semiconductor substrate via a doped semiconductor layer at a sidewall of the first trench.
Infineon Technologies Austria Ag


02/04/16
20160035841 

Multi-composition gate dielectric field effect transistors


A first gate structure and a second gate structure are formed over a semiconductor material layer. The first gate structure includes a planar silicon-based gate dielectric, a planar high-k gate dielectric, a metallic nitride portion, and a first semiconductor material portion, and the second gate structure includes a silicon-based dielectric material portion and a second semiconductor material portion.
International Business Machines Corporation


02/04/16
20160035840 

Semiconductor device


According to one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer provided in a portion on the first semiconductor layer, a first insulating layer provided on the first semiconductor layer on a terminal region side of the second semiconductor layer, a third semiconductor layer provided on the first semiconductor layer on the terminal region side of the first insulating layer, a second insulating layer provided on the first semiconductor layer on the terminal region side of the third semiconductor layer, a fourth semiconductor layer provided between the first semiconductor layer and the second insulating layer, and a plurality of field plate electrodes provided inside an inter-layer insulating film, the plurality of field plate electrodes having mutually-different distances from the first semiconductor layer.. .
Kabushiki Kaisha Toshiba


02/04/16
20160035839 

Compound semiconductor stack and semiconductor device


There is provided a compound semiconductor stack including a substrate (101) of which electrical resistance is greater than or equal to 1×105 Ωcm, a first compound semiconductor layer (102) which is formed on the substrate (101), and contains in and sb doped with carbon, and a second compound semiconductor layer (103) which is formed on the first compound semiconductor layer (102), has a carbon concentration less than a carbon concentration of the first compound semiconductor layer (102), and contains in and sb. A film thickness of the first compound semiconductor layer (102) is greater than or equal to 0.005 μm and less than or equal to 0.2 μm.
National Institute Of Advanced Industrial Science And Technology


02/04/16
20160035837 

Frequency multiplier based on a low dimensional semiconductor structure


A frequency multiplier based on a low dimensional semiconductor structure, including an insulating substrate layer, a semiconductor conducting layer arranged on the surface of the insulating substrate layer, an insulating protective layer arranged on the surface of the semiconductor conducting layer, an insulating carving groove penetrating the semiconductor conducting layer, an inlet electrode arranged on the side surface of the semiconductor conducting layer, and an outlet electrode arranged on the side surface corresponding to the access electrode is provided. The semiconductor conducting layer comprises two two-dimensional, quasi-one-dimensional, or one-dimensional current carrying channels near to and parallel to each other.
South China Normal University


02/04/16
20160035836 

Silicon carbide power bipolar devices with deep acceptor doping


In a general aspect, a power semiconductor device can include a collector region disposed on a substrate, the collector region can include n-type silicon carbide (sic). The power semiconductor device can also include a base region disposed on the collector region.
Fairchild Semiconductor Corporation


02/04/16
20160035835 

Smart semiconductor switch


A semiconductor device comprises semiconductor substrate including vertical transistor and with dopants of a first type. Each transistor cell of transistor has body region formed in substrate and with dopants of second type.
Infineon Technologies Ag


02/04/16
20160035834 

Smart semiconductor switch


A semiconductor device comprises a semiconductor substrate doped with dopants of a first type and a vertical transistor composed of one or more transistor cells. Each transistor cell has a first region formed in the substrate and doped with dopants of a second type, and the first regions form first pn-junctions with the surrounding substrate.
Infineon Technologies Ag


02/04/16
20160035833 

Trap rich layer for semiconductor devices


An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer.
Silanna Semiconductor U.s.a., Inc.


02/04/16
20160035832 

Transistor design


Some embodiments of the present disclosure relate to a transistor device formed in a semiconductor substrate containing dopant impurities of a first impurity type. The transistor device includes channel composed of a delta-doped layer comprising dopant impurities of the first impurity type, and configured to produce a peak dopant concentration within the channel.
Taiwan Semiconductor Manufacturing Co., Ltd.


02/04/16
20160035831 

Channel region dopant control in fin field effect transistor


A dummy gate structure straddling at least one semiconductor fin is formed on a substrate. Active semiconductor regions and raised active semiconductor regions may be formed.
International Business Machines Corporation


02/04/16
20160035828 

Compound semiconductor device, producing same, and resin-sealed type semiconductor device


In a semiconductor element having a compound semiconductor layer epitaxially grown on a silicon substrate, an object is to suppress generation of deficiency or problems of reliability deriving from the ends of the element that are generated when dividing into semiconductor devices by dicing. A compound semiconductor layer epitaxially grown on a silicon substrate is formed via a buffer layer made of aluminum nitride.
Panasonic Intellectual Property Management Co., Ltd.


02/04/16
20160035827 

Fin structure of semiconductor device


A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the fin including a doped region defining a first furrow on a first side of the first plane.
Taiwan Semiconductor Manufacturing Company, Ltd.


02/04/16
20160035826 

Semiconductor device and related manufacturing method


A method for manufacturing a semiconductor device may include forming a semiconductor portion, forming a doped portion, and forming a dielectric member. A side of the dielectric member abuts each of the semiconductor portion and the doped portion.
Semiconductor Manufacturing International (shanghai) Corporation


02/04/16
20160035825 

Super junction semiconductor device and manufacturing the same


There is provided a super junction semiconductor device and a method of manufacturing the same. A super junction semiconductor device includes an n-type semiconductor region disposed in a substrate, two or more p-type semiconductor regions disposed adjacent to the n-type semiconductor region alternately in a direction parallel to a surface of the substrate, a p-type body region disposed on at least one of the p-type semiconductor regions, and a source region disposed in the p-type body region, and an n-type ion implantation region is formed along a lower end of the n-type semiconductor region and lower ends of the p-type semiconductor regions..
Magnachip Semiconductor, Ltd.


02/04/16
20160035824 

Semiconductor device, manufacturing the same, and power module


A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer portions of the n-type base layer and the p-type base layer, respectively, a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer, a gate electrode formed on the gate insulation film facing the p-type base layer across the gate insulation film, a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer, a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer and including first baryons converted to donors, a source electrode connected to the n-type source layer, and a drain electrode connected to the n-type drain layer.. .
Rohm Co., Ltd.


02/04/16
20160035823 

Semiconductor device


A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed in the substrate at two respectively sides of the gate, a first well region formed in the substrate, and a plurality of first doped islands formed in the source region. The drain region and the source region include a first conductivity, and the first well region and the first doped islands include a second conductivity.
United Microelectronics Corp.


02/04/16
20160035822 

High voltage semiconductor devices and methods for their fabrication


Semiconductor devices include: (a) a semiconductor substrate containing a source region and a drain region; (b) a gate structure supported by the semiconductor substrate between the source region and the drain region; (c) a composite drift region in the semiconductor substrate, the composite drift region extending laterally from the drain region to at least an edge of the gate structure, the composite drift region including dopant having a first conductivity type, wherein at least a portion of the dopant is buried beneath the drain region at a depth exceeding an ion implantation range; and (d) a well region in the semiconductor substrate, wherein the well region has a second conductivity type and wherein the well region is configured to form a channel therein under the gate structure during operation of the semiconductor device. Methods for the fabrication of semiconductor devices are described..
Freescale Semiconductor, Inc.


02/04/16
20160035821 

Power semiconductor device


A semiconductor device includes an active region and a semiconductor substrate layer having a lower part semiconductor layer of a second conductivity type. The active region includes a drift region formed by at least a part of the substrate layer, a body region of the second conductivity type formed on at least a part of the drift region, a source region of a first conductivity type disposed in the body region, and a first doped region of the first conductivity type at least partially disposed under the body region.
Infineon Technologies Ag


02/04/16
20160035820 

Uniaxially-strained fd-soi finfet


Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer.
Globalfoundries Inc.


02/04/16
20160035816 

Semiconductor structure and fabrication method thereof


A semiconductor structure is provided. The semiconductor structure includes a substrate; and a plurality of parallel first conductive layers formed on the substrate.
Semiconductor Manufacturing International (shanghai) Corporation


02/04/16
20160035815 

Display unit, manufacturing the same, and electronic apparatus


A display unit includes: a display layer including a pixel electrode; a semiconductor layer provided in a layer below the display layer, the semiconductor layer including a wiring layer that includes a material removable by an etchant by which the pixel electrode is also removable; and a terminal section configured to electrically connect the semiconductor layer to an external circuit, the terminal section including a first electrically-conductive layer made of a material same as a material of the wiring layer.. .
Sony Corporation


02/04/16
20160035814 

Organic light emitting diode display and manufacturing the same


An organic light emitting device includes a switching transistor and a driving transistor. A semiconductor layer is commonly used by the switching and driving transistors.
Samsung Display Co., Ltd.


02/04/16
20160035808 

Organic light emitting display panel and manufacturing the same


Provided are an organic light emitting display panel and a method of manufacturing the same. The organic light emitting display panel includes: a pixel defined by an intersection of one of a plurality of data lines and one of a plurality of gate lines, the pixel including: a transistor, a storage capacitor including: a first electrode, and a second electrode, and a semiconductor layer, a first plate partially overlapping the semiconductor layer in the pixel, the first plate including: a gate portion of the transistor, and a capacitor-forming portion including the first electrode of the storage capacitor, and a second plate on the first plate in the pixel, the second plate including the second electrode of the storage capacitor, the second plate not overlapping the semiconductor layer..
Lg Display Co., Ltd.


02/04/16
20160035798 

Light emitting device


A light emitting device includes a substrate, a coupling unit and an organic light emitting unit. The coupling unit includes a first conductive layer, a first light emitting layer and a second conductive layer.
Industrial Technology Research Institute


02/04/16
20160035792 

Semiconductor memory device and manufacturing same


According to one embodiment, a semiconductor memory device includes a substrate including a major surface; a plurality of first films having conductivity or semiconductivity, the first films being provided above the substrate and extending in a first direction inclined with respect to the major surface; a plurality of second films having conductivity, the second films being provided above the substrate and extending in a second direction inclined with respect to the major surface and crossing the first direction; and a plurality of storage films provided in crossing sections of the first films and the second films.. .
Kabushiki Kaisha Toshiba


02/04/16
20160035790 

Semiconductor device and producing semiconductor device


The present invention provides a memory structure including a resistance-changing storage element, which enables a reset operation with a reset gate and in which cross-sectional areas of a resistance-changing film and a lower electrode in a current-flowing direction can be decreased. The semiconductor device of the present invention comprises a first pillar-shaped semiconductor layer, a gate insulating film formed around the first pillar-shaped semiconductor layer, a gate electrode made of a metal and formed around the gate insulating film, a gate line made of a metal and connected to the gate electrode, a second gate insulating film formed around an upper portion of the first pillar-shaped semiconductor layer, a first contact made of a second metal and formed around the second gate insulating film, a second contact which is made of a third metal and which connects an upper portion of the first contact to an upper portion of the first pillar-shaped semiconductor layer, a second diffusion layer formed in a lower portion of the first pillar-shaped semiconductor layer, a pillar-shaped insulating layer formed on the second contact, a resistance-changing film formed around an upper portion of the pillar-shaped insulating layer, a lower electrode formed around a lower portion of the pillar-shaped insulating layer and connected to the resistance-changing film, a reset gate insulating film that surrounds the resistance-changing film, and a reset gate that surrounds the reset gate insulating film..
Unisantis Electronics Singapore Pte. Ltd.


02/04/16
20160035789 

Method of manufacturing semiconductor device and semiconductor device having unequal pitch vertical channel transistors


A semiconductor device comprises a set of selection transistors, such as in a three-dimensional memory structure or stack having resistance change memory cells arranged along vertical bit lines. Each selection transistor has a non-shared control gate and a shared control gate.
Sandisk 3d Llc


02/04/16
20160035788 

Methods of manufacturing semiconductor devices


Active patterns spaced apart from each other by an isolation layer are formed in a substrate. Gate structures extending in the isolation layer through the active patterns are formed.
Samsung Electronics Co., Ltd.


02/04/16
20160035787 

Method of manufacturing semiconductor device


A method of manufacturing a semiconductor device includes a step of vacuum packing a sawn wafer while being housed in a shipping case. The shipping case has the following structure.

02/04/16
20160035786 

Method of fabricating a semiconductor device


There is provided a method of fabricating a semiconductor device, including grinding a first surface of a first semiconductor layer to generate a damage layer in a surface region of the first surface of the first semiconductor layer, polishing the damage layer to remove a portion with predetermined thickness of the damage layer; and etching the damage layer and the first semiconductor layer to remove the first semiconductor layer from a third surface of a second semiconductor layer, the third surface contacting to a second surface opposed to the first surface in the first semiconductor layer.. .
Kabushiki Kaisha Toshiba


02/04/16
20160035782 

Shallow trench textured regions and associated methods


Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor layer having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor layer and positioned to interact with electromagnetic radiation.
Sionyx, Inc.


02/04/16
20160035781 

Solid-state imaging device and electronic instrument


A solid-state imaging device including, a first semiconductor region of the first conduction type, a photoelectric conversion part having a second semiconductor region of the second conduction type formed in the region separated by the isolation dielectric region of the first semiconductor region, pixel transistors formed in the first semiconductor region, a floating diffusion region of the second conduction type which is formed in the region separated by the isolation dielectric region of the first semiconductor region, and an electrode formed on the first semiconductor region existing between the floating diffusion region and the isolation dielectric region and is given a prescribed bias voltage.. .
Sony Corporation


02/04/16
20160035777 

Semiconductor device and manufacturing method


A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.. .
Sony Corporation


02/04/16
20160035776 

Method for manufacturing solid-state imaging device, and solid-state imaging device


Certain embodiments provide a method for manufacturing a solid-state imaging device, including thinning a semiconductor substrate, forming a plurality of masking patterns, and forming a groove having inclined surfaces that are inclined relative to a front surface of the semiconductor substrate at a back surface of the semiconductor substrate. A plurality of light receiving sections are provided in a lattice pattern at the front surface of the semiconductor substrate to be thinned.
Kabushiki Kaisha Toshiba


02/04/16
20160035773 

Semiconductor image sensors having channel stop regions and methods of fabricating the same


A semiconductor device includes a light-receiving element which outputs electric charges in response to incident light, and a drive transistor which is gated by an output of the light-receiving element to generate a source-drain current in proportion to the incident light, wherein the drive transistor include a first gate electrode, a first channel region which is disposed under the first gate electrode, first source-drain regions which are disposed at respective ends of the first channel region and that have a first conductivity type, and a first channel stop region which is disposed on a side of the first channel region, and that separates the light-receiving element and the first channel region, the first channel stop region having a second conductivity type that is different from the first conductivity type.. .
Samsung Electronics Co., Ltd.


02/04/16
20160035771 

Image sensor device and method


A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration.
Taiwan Semiconductor Manufacturing Company, Ltd.


02/04/16
20160035767 

Photoelectric transducer and imaging system


A photoelectric transducer includes a wiring structure and a photoelectric conversion section provided on a substrate. The photoelectric conversion section includes a first electrode and a photoelectric conversion layer provided on the first electrode.
Canon Kabushiki Kaisha


02/04/16
20160035766 

Semiconductor device and manufacturing method thereof


A semiconductor device such as, for example an imaging sensor, includes a semiconductor layer in which, for example, a photodiode may be formed. An insulation film is disposed on a surface of the semiconductor layer.
Kabushiki Kaisha Toshiba


02/04/16
20160035765 

Method of fabricating metal wiring and thin film transistor substrate


A method of fabricating metal wiring, including: sequentially forming first and second conductive layers on a substrate; forming a first photosensitive film pattern on the first and second conductive layers; forming first and second conductive patterns by etching parts of the first and second conductive layers by using the first photosensitive film pattern as a mask; forming a second photosensitive film pattern positioned inside the first photosensitive film pattern by a predetermined interval by ashing the first photosensitive film pattern; etching an exposed first conductive pattern by using the second photosensitive film pattern as a mask; and removing the second photosensitive film pattern.. .
Samsung Display Co., Ltd.


02/04/16
20160035758 

Semiconductor device and manufacturing the same


A semiconductor device includes a pixel portion having a first thin film transistor and a driver circuit having a second thin film transistor. Each of the first thin film transistor and the second thin film transistor includes a gate electrode layer, a gate insulating layer, a semiconductor layer, a source electrode layer, and a drain electrode layer.
Semiconductor Energy Laboratory Co., Ltd.


02/04/16
20160035757 

Semiconductor device


A semiconductor device capable of maintaining data during instantaneous power reduction or interruption. The semiconductor device includes first to sixth transistors.
Semiconductor Energy Laboratory Co., Ltd.


02/04/16
20160035754 

Semiconductor device, manufacturing method thereof, and display apparatus


Provided is a semiconductor device including a buffer layer that is on a substrate and includes an inclined surface; a crystalline silicon layer that is on the buffer layer; a gate electrode that is on the crystalline silicon layer while being insulated from the crystalline silicon layer; and a source electrode and a drain electrode that are each electrically connected to the crystalline silicon layer, the angle between the substrate and the inclined surface being in a range of about 17.5 degrees to less than about 70 degrees.. .
Samsung Display Co., Ltd.


02/04/16
20160035743 

Field effect transistor (fet) with self-aligned contacts, integrated circuit (ic) chip and manufacture


Field effect transistors (fets), integrated circuit (ic) chips including the fets, and a method of forming the fets and ic. Fet locations and adjacent source/drain regions are defined on a semiconductor wafer, e.g., a silicon on insulator (soi) wafer.
Globalfoundries Inc.


02/04/16
20160035742 

Spacer passivation for high-aspect ratio opening film removal and cleaning


A method of making a semiconductor device includes forming a stack of alternating layers of a first material and a second material over a substrate, etching the stack to form at least one opening in the stack such that a damaged region is located on a bottom surface of the at least one opening, forming a masking layer on a sidewall of the at least one opening while the bottom surface of the at least one opening is not covered by the masking layer, and further etching the bottom surface of the at least one opening remove the damaged region.. .
Sandisk Technologies Inc.


02/04/16
20160035741 

Non-volatile memory device


According to an embodiment, a non-volatile memory device includes first electrodes arranged in a first direction, a second electrode disposed on a side of the first electrodes in the first direction, a semiconductor layer extending in the first direction through the first electrodes and the second electrode, and a memory film provided between the semiconductor layer and each of the first electrodes. The semiconductor layer includes crystal grains and has a first portion and a second portion, the first portion being adjacent to the first electrodes, and the second portion being adjacent to at least a part of the second electrode, wherein the first portion includes a larger crystal grain than a crystal grain in the second portion..
Kabushiki Kaisha Toshiba


02/04/16
20160035740 

Non-volatile memory device and manufacturing same


According to an embodiment, a non-volatile memory device includes electrodes, an inter-layer insulating film between the electrodes and at least one semiconductor layer extending through the electrodes and the inter-layer insulating film. The device includes a charge storage layer between the semiconductor layer and each electrode, a first insulating film between the charge storage layer and the semiconductor layer, and a second insulating film.
Kabushiki Kaisha Toshiba


02/04/16
20160035739 

Semiconductor device and a manufacturing method thereof


The performances of a semiconductor device are improved. The semiconductor device has a first control gate electrode and a second control gate electrode spaced along the gate length direction, a first cap insulation film formed over the first control gate electrode, and a second cap insulation film formed over the second control gate electrode.
Renesas Electronics Corporation


02/04/16
20160035737 

System and uv programming of non-volatile semiconductor memory


A method of forming a semiconductor memory storage device that includes forming first and second doped regions of a first type in a semiconductor substrate and laterally spaced from one another, forming a gate dielectric extends over the semiconductor substrate between the first and second doped regions, forming a floating gate on the gate dielectric, and forming an ultraviolet (uv) light blocking material vertically disposed above the floating gate such that the floating gate remains electrically charged after the semiconductor memory storage device is exposed to uv light.. .
Taiwan Semiconductor Manufacturing Co., Ltd.


02/04/16
20160035735 

Antifuse element utilizing non-planar topology


Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements are configured with non-planar topology such as finfet topology.
Intel Corporation


02/04/16
20160035734 

Method for manufacturing a semiconductor device


The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate.
Renesas Electronics Corporation


02/04/16
20160035733 

Semiconductor circuit structure


A nand flash circuit structure includes two select gates disposed on a substrate, and an even number of spaced-apart word lines disposed between the two select gates. The select gate is provided with a first portion and a second portion.
Powerchip Technology Corporation


02/04/16
20160035732 

Three-dimensional non-volatile memory device


A semiconductor device includes at least one first conductive layer stacked on a substrate where a cell region and a contact region are defined; at least one first slit passing through the first conductive layer, second conductive layers stacked on the first conductive layer; a second slit passing through the first and second conductive layers and connected with one side of the first slit, and a third slit passing through the first and second conductive layers and connected with the other side of the first slit.. .
Sk Hynix Inc.


02/04/16
20160035731 

Semiconductor devices and methods of manufacturing semiconductor devices


A method of manufacturing a semiconductor device includes forming an isolation pattern on a substrate to define active patterns each having a first contact region at a center portion thereof and second and third contact regions at edge portions thereof. The method further includes forming a buried gate structure at upper portions of the isolation pattern and the active patterns, forming a first insulation layer on the isolation pattern and the active patterns, and etching a portion of the first insulation layer and an upper portion of the first contact region to form a preliminary opening exposing the first contact region.
Samsung Electronics Co., Ltd.


02/04/16
20160035730 

Semiconductor device


A semiconductor device according to this invention includes a support film that supports a lower electrode of a capacitor at an upper portion, and the support film includes a first insulating material having a stress within a range of +700 mpa to −700 mpa. Use of such a support film prevents a phenomenon in which the capacitor lower electrode is twisted.
Ps4 Luxco S.a.r.l.


02/04/16
20160035728 

Retrograde doped layer for device isolation


Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage.
Globalfoundries Inc.


02/04/16
20160035727 

Cmos structure with beneficial nmos and pmos band offsets


A cmos structure with beneficial nmos and pmos band offsets is disclosed. A first silicon germanium layer is formed on a semiconductor substrate.
Globalfoundries Inc.


02/04/16
20160035726 

Fin sidewall removal to enlarge epitaxial source/drain volume


A finfet device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer.
Taiwan Semiconductor Manufacturing Co., Ltd.


02/04/16
20160035722 

Semiconductor devices and structures


An integrated circuit device, including: a first layer including first transistors; and a second layer including second transistors overlaying the first layer, where the first transistors are facing down and the second transistors are facing up, and where the second layer includes a through layer via of less than 300 nm diameter.. .
Monolithic 3d Inc.


02/04/16
20160035721 

Common drain semiconductor device structure and method


In one embodiment, a common drain semiconductor device includes a substrate, having two transistors integrated therein. The substrate also includes a plurality of active regions on a major surface of the substrate.
Semiconductor Components Industries, Llc


02/04/16
20160035719 

Semiconductor device and manufacturing the same


Both a hemt and a sbd are formed on a nitride semiconductor substrate. The nitride semiconductor substrate comprises a hemt gate structure region and an anode electrode region.
Toyota Jidosha Kabushiki Kaisha


02/04/16
20160035718 

Electrostatic discharge devices and methods of manufacture


Electrostatic discharge (esd) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure from semiconductor material.
International Business Machines Corporation


02/04/16
20160035715 

System for designing a semiconductor device, device made, and using the system


A semiconductor device includes an edge active cell, an inner active cell and a middle active cell. The edge active cell is located near an edge of the semiconductor device.
Taiwan Semiconductor Manufacturing Company, Ltd.


02/04/16
20160035714 

Semiconductor device


A semiconductor device includes a plurality of bit lines that intersect an active region on a substrate and extend in a first direction, a contact pad formed on the active region between adjacent bit lines, and a plurality of spacers disposed on sidewalls of the plurality of bit lines. An upper portion of the contact pad is interposed between adjacent spacers, and a lower portion of the contact pad has a width greater than a distance between adjacent spacers..
Samsung Electronics Co., Ltd.


02/04/16
20160035713 

Semiconductor element and semiconductor device


A semiconductor device includes a voltage generation circuit configured to generate a specific voltage; a first terminal configured to output the specific voltage; a second terminal configured to receive a temperature sensitive voltage; an analog/digital conversion circuit configured to convert the specific voltage and the temperature sensitive voltage to digital values; a storage unit configured to store the specific voltage and the temperature sensitive voltage; and a third terminal configured to transmit the specific voltage and the temperature sensitive voltage to an external semiconductor device.. .
Lapis Semiconductor Co., Ltd.


02/04/16
20160035712 

Microelectronic package with stacked microelectronic units and manufacture thereof


A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge.
Invensas Corporation


02/04/16
20160035709 

Package on package devices and methods of packaging semiconductor dies


Package on package (pop) devices and methods of packaging semiconductor dies are disclosed. A pop device includes a first packaged die and a second packaged die coupled to the first packaged die.
Taiwan Semiconductor Manufacturing Company, Ltd.


02/04/16
20160035707 

Stacked structure of semiconductor chips having via holes and metal bumps


A stacked structure comprises a semiconductor chip which includes a substrate having at least one substrate via hole penetrating through the substrate; at least one backside metal layer formed on a backside of the substrate covering an inner surface of the substrate via hole and at least part of the backside of the substrate; at least one front-side metal layer formed on the front-side of the substrate and electrically connected to the at least one backside metal layer on a top of at least one of the at least one substrate via hole; at least one electronic device formed on the front-side of the substrate and electrically connected to the at least one front-side metal layer; and at least one metal bump formed on at least one of the backside metal layer and the front-side metal layer.. .
Win Semiconductors Corp.


02/04/16
20160035706 

Semiconductor device for battery power voltage control


A voltage generated in any of a plurality of semiconductor chips is supplied to another chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. For example, two chips are stacked with each other, first to third pads are disposed along corresponding sides of the respective chips, which are arranged close and in parallel to each other, and these pads are commonly connected to each other with first to third metal wires, respectively.
Renesas Electronics Corporation


02/04/16
20160035705 

Semiconductor device and manufacturing method therefor


A chip laminate in this semiconductor device has a structure consisting of a first semiconductor chip and a second semiconductor chip laminated together. The first semiconductor chip has a circuit-forming layer and a first bump electrode formed on one surface and a second bump electrode formed on the other surface.
Ps4 Luxco S.a.r.l.


02/04/16
20160035701 

Semiconductor tsv device package for circuit board connection


An electronic device includes a circuit board and a semiconductor device package. The semiconductor device package includes a laminate layer.
International Business Machines Corporation


02/04/16
20160035699 

Power semiconductor package having vertically stacked driver ic


In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (i/o) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control fet of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (ic) for driving the control fet.
Infineon Technologies Americas Corp.


02/04/16
20160035698 

Stack package


A stack package includes a substrate, a stack of semiconductor chips mounted to the substrate, a side semiconductor chip disposed on one side of the stack, and adhesive interposed between the lower surface of the side semiconductor chip and the stack of semiconductor chips and which attaches the side semiconductor chip to the stack.. .
Samsung Electronics Co., Ltd.


02/04/16
20160035696 

Method for forming package structure


A method for forming a package structure is provided, which includes: providing a pre-packaged panel including a first encapsulation layer, which includes multiple integrating units each including at least one semiconductor chip with multiple first pads, and first metal bumps are disposed on the first pads; providing a circuit board including a first surface and a second surface, where the circuit board includes multiple carrying units each including multiple input pads on the first surface and multiple output pads on the second surface; mounting the pre-packaged panel on the first surface to form multiple package units; forming a filling layer by filling a space between the first surface and the pre-packaged panel; forming second metal bumps on the output pads on the second surface; cutting the structure based on the multiple package units to form multiple independent package structures. Accordingly, the package structure improves package efficiency..
Nantong Fujitsu Microelectronics Co., Ltd.


02/04/16
20160035695 

Method of manufacturing semiconductor device


A semiconductor device includes a common wire that sequentially connects three or more pads; bonding portions at which a side surface of the wire is bonded to the pads; and looping portions looped from the bonding portions onto the other pads adjacent to the pads, the bonding portions and the looping portions are formed alternately. When the pads are recessed from the surface of semiconductor chips, the common wire is crushed to a thickness greater than the recess depth of the pads to be made into a flat shape.
Shinkawa Ltd.


02/04/16
20160035693 

Semiconductor tsv device package for circuit board connection


An electronic device includes a circuit board and a semiconductor device package. The semiconductor device package includes a laminate layer.
International Business Machines Corporation


02/04/16
20160035691 

Semiconductor device and fabricating same


A semiconductor device includes, an alloy layer sandwiched between a first ag layer formed on a mounting board or circuit board and a second ag layer formed on a semiconductor element, wherein the alloy layer contains an intermetallic compound of ag3sn formed by ag components of the first ag layer and the second ag layer and sn, and wherein a plurality of wires containing ag are arranged extended from an outside-facing periphery of the alloy layer.. .
Mitsubishi Electric Corporation


02/04/16
20160035690 

Semiconductor device and manufacturing semiconductor device


A solder joint layer has a structure in which plural fine-grained second crystal sections (22) precipitate at crystal grain boundaries between first crystal sections (21) dispersed in a matrix. The first crystal sections (21) are sn crystal grains containing tin and antimony in a predetermined proportion.
Fuji Electric Co., Ltd.


02/04/16
20160035688 

Semiconductor component, semiconductor-mounted product including the component, and producing the product


A semiconductor component includes a semiconductor package having a mountable face, a bump, and a coating part. The bump is made of first solder and is formed on the mountable face.
Panasonic Corporation


02/04/16
20160035683 

Semiconductor device


A highly reliable semiconductor device capable of heavy current conduction and high temperature operation has a module structure in which a semiconductor chip and a circuit pattern are electrically connected via a wire. A front surface metal film is formed on a front surface electrode of the chip, and the wire is bonded to the front surface metal film by wire bonding.
Fuji Electric Co., Ltd.


02/04/16
20160035681 

Semiconductor device structures inlcuding a distributed bragg reflector


A method of forming a semiconductor device structure comprises forming at least one reflective structure comprising at least two dielectric materials having different refractive indices over at least one radiation-sensitive structure, the at least one reflective structure configured to substantially reflect therefrom radiation within a predetermined wavelength range and to substantially transmit therethrough radiation within a different predetermined wavelength range. Additional methods of forming a semiconductor device structure are described.
Micron Technology, Inc.


02/04/16
20160035680 

Semiconductor package with conformal em shielding structure and manufacturing same


A semiconductor package includes a substrate having a front side, a bottom side, and a sidewall along a perimeter of the substrate, a plurality of solder pads on the bottom side, at least one em shielding contact structure on the bottom side and partially exposed on the sidewall, a semiconductor device mounted on the front side, a mold compound on the front side and covering the semiconductor device, and an em shielding layer conformally covering the mold compound and the sidewall. The em shielding layer is in direct contact with the exposed portion of the em shielding contact structure on the sidewall..
Cyntec Co., Ltd.


02/04/16
20160035678 

Semiconductor package and manufacturing the same


The semiconductor package includes: a substrate having at least one circuit layer; at least one electronic component mounted on at least one surface of the substrate; a molded part formed on the surface of the substrate to enclose the electronic component; at least one via formed in the molded part to be electrically connected to the circuit layer of the substrate; and a semiconductive pattern connected to one end of a plated tail connected to the circuit layer connected to the via and exposed to the exterior of the substrate.. .
Samsung Electro-mechanics Co., Ltd.


02/04/16
20160035676 

Semiconductor devices and methods of fabricating the same


Semiconductor devices may include a substrate including an active region defined by a device isolation layer, source/drain regions in the active region, word lines extending in a first direction parallel to the active region and being arranged in a second direction crossing the first direction, a bit line pattern extending in the second direction and crossing over a portion of the active region positioned between the word lines, and a graphene pattern covering at least a portion of the bit line pattern.. .
Samsung Electronics Co., Ltd.


02/04/16
20160035673 

Semiconductor device having a fuse element


A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse.
Renesas Electronics Corporation


02/04/16
20160035672 

Semiconductor device and manufacturing the same


A coil cl1 is formed on a semiconductor substrate sb via a first insulation film, a second insulation film is formed so as to cover the first insulation film and the coil cl1, and a pad pd1 is formed on the second insulation film. A laminated film lf having an opening op1 from which the pad pd1 is partially exposed is formed on the second insulation film, and a coil cl2 is formed on the laminated insulation film.
Renesas Electronics Corporation


02/04/16
20160035670 

Semiconductor device packages, packaging methods, and packaged semiconductor devices


Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a back side interconnect structure, and a winding of an inductor disposed in a material layer of the back side interconnect structure.
Taiwan Semiconductor Manufacturing Company, Ltd.


02/04/16
20160035669 

Routing paths and semiconductor devices including the same


A semiconductor device may include a global line coupled to a source, and a plurality of local lines coupled to a plurality of targets, respectively, and coupled to the global line. The local lines may be configured to have cross-sectional areas.
Sk Hynix Inc.


02/04/16
20160035667 

Methods of packaging semiconductor devices and packaged semiconductor devices


Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes providing a protective film, coupling dies to the protective film, and disposing a molding material around the dies.
Taiwan Semiconductor Manufacturing Company, Ltd.


02/04/16
20160035664 

Semiconductor package on package structure and forming the same


A package on package structure may be formed by fabricating or providing a bottom package having a substrate, at least one die on top of the substrate, and bonding pads on the top of the substrate. Next, a frame is formed on the bonding pads and connected to the bonding pads.
Qualcomm Incorporated


02/04/16
20160035663 

Semiconductor package system and method


A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings.
Taiwan Semiconductor Manufacturing Company, Ltd.


02/04/16
20160035662 

Semiconductor devices with close-packed via structures having in-plane routing and making same


The invention relates to a semiconductor structure, comprising a substrate of a semiconductor material having a first side (fs) and an opposite second side (bs). There is at least one conductive wafer-through via (v) comprising metal, and at least one recess (rdl) provided in the first side of the substrate and in the semiconductor material of the substrate.
Silex Microsystems Ab


02/04/16
20160035661 

Support member, wiring substrate, manufacturing wiring substrate, and manufacturing semiconductor package


A wiring substrate includes a support member, and a wiring member formed on one side of the support member. The support member includes metal foils and at least one resin layer alternately layered, so that one of the metal foils is provided as a first outermost layer on the one side of the support member and another one of the metal foils is provided as a second outermost layer on another side of the support member.
Shinko Electric Industries Co., Ltd.


02/04/16
20160035657 

Semiconductor device and semiconductor module


According to one embodiment, a semiconductor device includes a first base portion, a second base portion, a third base portion, and a semiconductor element. A first end portion of the first base portion is positioned closer to a side on which the semiconductor element is provided than a second end portion of the first base portion.
Kabushiki Kaisha Toshiba


02/04/16
20160035655 

Semiconductor package having etched foil capacitor integrated into leadframe


A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls.
Texas Instruments Incorporated


02/04/16
20160035654 

Source down semiconductor devices and methods of formation thereof


A method for forming a semiconductor device includes forming device regions in a semiconductor substrate having a first side and a second side. The device regions are formed adjacent the first side.
Infineon Technologies Ag


02/04/16
20160035653 

Mcsp power semiconductor devices and preparation methods thereof


The present invention discloses the mcsp power semiconductor device and the preparation method thereof. In the present invention method, a metal foil layer is attached to the back of the wafer using a conductive adhesive layer and a composite tape is laminated on the metal foil layer.
Alpha And Omega Semiconductor Incorporated


02/04/16
20160035651 

Leadless semiconductor package and method


A method of forming semiconductor devices on a leadframe structure. The leadframe structure comprising an array of leadframe sub-structures each having a semiconductor die arranged thereon.
Nxp B.v.


02/04/16
20160035649 

Semiconductor devices with optical through via structures, memory cards including the same, and electronic systems including the same


A semiconductor device is provided. The semiconductor device may include a substrate and a through via structure penetrating the substrate.
Sk Hynix Inc.


02/04/16
20160035648 

Semiconductor die assemblies with heat sink and associated systems and methods


Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a mold material surrounding at least a portion of the stack of semiconductor dies.
Micron Technology, Inc.


02/04/16
20160035647 

Semiconductor device having heat dissipation structure and laminate of semiconductor devices


A semiconductor device includes a semiconductor substrate, an electrode arranged on a first surface of the semiconductor substrate, a circuit formed on a second surface, of the semiconductor substrate, on an opposite side from the first surface, a conductor connecting the circuit and the electrode, a first lead arranged on an outer periphery of the semiconductor substrate, a connection member connecting the electrode and the first lead, and a sealing material sealing the semiconductor substrate, the first lead, and the connection member, where the second surface of the semiconductor substrate is exposed from the sealing material.. .
Panasonic Corporation


02/04/16
20160035646 

Semiconductor device, assembling semiconductor device, semiconductor device component, and unit module


A semiconductor device includes an insulating substrate; a semiconductor element mounted on the insulating substrate; and a radiation block bonded to the semiconductor element. The radiation block includes a three-dimensional radiation portion and a base portion connected to the radiation portion.
Fuji Electric Co., Ltd.


02/04/16
20160035645 

Exposed, solderable heat spreader for flipchip packages


A flipchip package may include a semiconductor die, a heat spreader, and encapsulation material. The semiconductor die may contain an electronic circuit and exposed electrical connections to the electronic circuit.
Linear Technology Corporation


02/04/16
20160035644 

Exposed, solderable heat spreader for integrated circuit packages


An integrated circuit package may include a semiconductor die, a heat spreader, and encapsulation material. The semiconductor die may contain an electronic circuit and exposed electrical connections to the electronic circuit.
Linear Technology Corporation


02/04/16
20160035643 

Semiconductor device and manufacturing the same


Aspects of the invention include a semiconductor device that enables both solder-outflow prevention and inhibition of seizures coming from laser processing residues. A semiconductor device can include a semiconductor chip, a plurality of insulating substrates on each of which the semiconductor chip is fixed, a heat sink having a plurality of first grooves surrounding each one of more than one predetermined arrangement area.
Fuji Electric Co., Ltd.


02/04/16
20160035641 

Semiconductor device including passivation layer encapsulant


A method of fabricating a semiconductor device includes forming a passivation layer on a least one capping layer of the semiconductor device, and forming an encapsulant layer on the passivation layer. The method further includes patterning the encapsulant layer to expose a portion of the passivation layer and forming a final via opening in the passivation layer.
Globalfoundries Inc.


02/04/16
20160035640 

Underfill film, sealing sheet, manufacturing semiconductor device, and semiconductor device


The present invention provides an underfill film and a sealing sheet that are excellent in thermal conductive property and are capable of satisfactorily filling the space between the semiconductor element and the substrate. The present invention relates to an underfill film having a resin and a thermally conductive filler, in which a content of the thermally conductive filler is 50% by volume or more, an average particle size of the thermally conductive filler is 30% or less of a thickness of the underfill film, and a maximum particle size of the thermally conductive filler is 80% or less of the thickness of the underfill film..
Nitto Denko Corporation


02/04/16
20160035639 

Semiconductor device and manufacturing the same


A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a chip substrate, a mold, and a buffer layer.
Taiwan Semiconductor Manufacturing Company Ltd.


02/04/16
20160035638 

Support base-attached encapsulant, encapsulated substrate having semiconductor devices mounted thereon, encapsulated wafer having semiconductor devices formed thereon, semiconductor apparatus, and manufacturing semiconductor apparatus


Support base-attached encapsulant for collectively encapsulating a semiconductor device mounting surface of a substrate or semiconductor device forming surface of a wafer, containing a support base having one fibrous film or a plurality of the fibrous films being laminated, the fibrous film subjected to surface treatment with an organosilicon compound, and a resin layer of thermosetting resin formed on one surface of the support base. The support base-attached encapsulant inhibit the substrate or wafer from warping and semiconductor devices from peeling away from the substrate, and collectively encapsulate the semiconductor device mounting surface of the substrate or the semiconductor device forming surface of the wafer even when a large-diameter wafer or large-area substrate is encapsulated.
Shin-etsu Chemical Co., Ltd.


02/04/16
20160035637 

Semiconductor device and manufacturing semiconductor device


A semiconductor device includes: a substrate; a semiconductor element disposed on the substrate; a plurality of electrodes disposed on the substrate separately from one another and arranged so as to surround the semiconductor element in a plan view; a lid that cover the semiconductor element, the lid including an inner portion and a periphery portion that is outer than the inner portion in a plan view, the lid including a plurality of first protruding members that is provided separately from one another, the first protruding members being disposed in the inner portion; and conductive members disposed between the plurality of electrodes and the plurality of protruding members disposed in positions opposed to the plurality of electrodes respectively, the conductive members being joined to the plurality of electrodes and the plurality of protruding members respectively.. .
Socionext Inc.


02/04/16
20160035636 

Manufacturing semiconductor device


Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip.
Renesas Electronics Corporation


02/04/16
20160035633 

Low energy collimated ion milling of semiconductor structures


A method of delayering a surface of a semiconductor structure may include applying a voltage in the range of about 50 ev to less than 300 ev to an inductively coupled argon ion source operating at a radio frequency. A collimated ion beam incident on the surface of the semiconductor structure may be generated, from the argon ion source, for the planar removal of layers of the surface.
International Business Machines Corporation


02/04/16
20160035632 

Semiconductor tsv device package to which other semiconductor device package can be later attached


A first package includes a laminate layer, an overmold layer above and in direct contact with the laminate layer, and a logic circuit-through-silicon via (tsv) layer including a first logic die and tsvs. The logic circuit-tsv layer is within the overmold layer, and the tsvs are electrically exposed at a top surface of the overmold layer.
International Business Machines Corporation


02/04/16
20160035631 

Atomic layer deposition of hfalc as a metal gate workfunction material in mos devices


Ald of hfxalycz films using hafnium chloride (hfcl4) and trimethylaluminum (tma) precursors can be combined with post-deposition anneal processes and ald liners to control the device characteristics in high-k metal-gate devices. Variation of the hfcl4 pulse time allows for control of the al % incorporation in the hfxalycz film in the range of 10-13%.
Intermolecular Inc.


02/04/16
20160035630 

Methods of forming transistors with retrograde wells in cmos applications and the resulting device structures


One illustrative method disclosed herein includes performing a first plurality of epitaxial deposition processes to form a first plurality of semiconductor materials selectively above the n-active region while masking the p-active region, performing a second plurality of epitaxial deposition processes to form a second plurality of semiconductor materials selectively above the p-active region while masking the n-active region, forming an n-type transistor in and above the n-active region and forming a p-type transistor in and above the p-active region.. .
Globalfoundries Inc.


02/04/16
20160035629 

Methods of forming low resistance contacts


Methods for forming electrical contacts are provided. First and second fets are formed over a semiconductor substrate.
Taiwan Semiconductor Manufacturing Company Limited


02/04/16
20160035627 

High performance cmos device design


A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


02/04/16
20160035626 

Stressed channel bulk fin field effect transistor


Effective transfer of stress to a channel of a fin field effect transistor is provided by forming stress-generating active semiconductor regions that function as a source region and a drain region on a top surface of a single crystalline semiconductor layer. A dielectric material layer is formed on a top surface of the semiconductor layer between semiconductor fins.
Kabushiki Kaisha Toshiba


02/04/16
20160035624 

Semiconductor device manufacturing method and semiconductor device thereof


According to one embodiment, a semiconductor device manufacturing method provides filling a through-hole which penetrates through a first side of substrate to a second side thereof. A seed film including copper is formed on the inner wall surface of the through-hole.
Kabushiki Kaisha Toshiba


02/04/16
20160035623 

Integrated circuits having device contacts and methods for fabricating the same


Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes providing a semiconductor device with a metal silicide electrically coupled thereto.
Globalfoundries Singapore Pte. Ltd.


02/04/16
20160035621 

Copper wire and dielectric with air gaps


Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask.
International Business Machines Corporation


02/04/16
20160035620 

Method for forming seed layer on high-aspect ratio via and semiconductor device having high-aspect ratio via formed thereby


Disclosed are a method of forming a seed layer on a high-aspect ratio via and a semiconductor device having a high-aspect ratio via formed thereby. Thus, efficient cu filling-plating is possible, and plating adhesion of the seed layer to filling-plated cu can be simply and profitably enhanced, thus imparting high durability upon forming metal wiring for electronic components.
Korea Institute Of Industrial Technology


02/04/16
20160035617 

Overlay marks, methods of forming the same, and methods of fabricating semiconductor devices using the same


In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area.

02/04/16
20160035616 

Handler wafer removal by use of sacrificial inert layer


The present invention relates generally to semiconductor structures and methods of manufacture and, more particularly, to the temporary bonding of a semiconductor wafer to handler wafer during processing. The semiconductor wafer may be temporarily bonded to the handler wafer by forming a sacrificial layer on a surface of a handler wafer, forming a first dielectric layer on a surface of the sacrificial layer, forming a second dielectric layer on a surface of a semiconductor wafer, and directly bonding the first dielectric layer and the second dielectric layer to form a bonding layer.
International Business Machines Corporation


02/04/16
20160035615 

Methods of manufacturing a semiconductor device


Methods of manufacturing a semiconductor device are described. In an embodiment, the method may include providing a substrate having a metal layer disposed thereon, the metal layer having a conductive trace pattern formed therein; depositing a dielectric material over the conductive trace pattern of the metal layer; determining a layout of a plurality of air gaps that will be formed in the dielectric material based on a design rule checking (drc) procedure and the conductive trace pattern; and forming the plurality of air gaps in the dielectric material based on the layout of the plurality of air gaps..
Taiwan Semiconductor Manufacturing Company, Ltd.


02/04/16
20160035612 

Temporary bonding laminates for used in manufacture of semiconductor devices and methods for manufacturing semiconductor devices


Provided is temporary bonding laminates for used in a manufacture of semiconductor devices, by which a member to be processed (a semiconductor wafer or the like) can be temporarily supported securely and readily during a mechanical or chemical process of the member to be processed and then the processed member can be readily released from the temporary support without damaging the processed member even after a high temperature process, and processes for manufacturing semiconductor devices. The temporary bonding laminate includes (a) a release layer and (b) an adhesive layer, wherein the release layer (a) comprises (a1) a first release layer having a softening point of 200° c.
Fujifilm Corporation


02/04/16
20160035611 

Carrier wafer, holding a flexible substrate and the manufacture of a carrier wafer


Carrier wafers are used to hold thin and ultra-thin substrates such as semiconductor components, for example. The carrier wafer of the invention has a plurality of electrodes insulated on all sides (floating electrodes).
Fraunhofer-gesellschaft Zur Foerderung Der Angewandten Forschung E.v.


02/04/16
20160035610 

Electrostatic chuck assemblies having recessed support surfaces, semiconductor fabricating apparatuses having the same, and plasma treatment methods using the same


An electrostatic chuck apparatus includes a base and a dielectric layer on the base. The dielectric layer includes a support surface opposite the base and a clamping electrode laterally extending along the support surface.

02/04/16
20160035607 

Semiconductor wafer stocker apparatus and wafer transferring methods using the same


A semiconductor wafer stocker apparatus includes a body frame, an inlet port to load a wafer shipping box into the body frame, an outlet port to unload the wafer shipping box from the body frame, an automated transfer robot operable to convey the wafer shipping box between the inlet port and the outlet port, and a shelf module within the body frame. The shelf module includes a shelf plate configured to support the wafer shipping box.
Samsung Electronics Co., Ltd.


02/04/16
20160035602 

Method of forming a composite substrate for layered heaters


A method of forming a heater assembly for use in semiconductor processing includes thermally securing a heater substrate to an application substrate; and applying a layered heater having at least one functional layer to the heater substrate after the heater substrate is secured to the application substrate. The heater substrate defines a material having a coefficient of thermal expansion that is matched to a coefficient of thermal expansion of the functional layer.
Watlow Electric Manufacturing Company


02/04/16
20160035599 

Method of forming a semiconductor die cutting tool


In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer..
Semiconductor Components Industries, Llc


02/04/16
20160035590 

System-in-packages and methods for forming same


One or more embodiments are directed to a system-in-package (sip) that includes a plurality of semiconductor chips and an interposer that that are molded in an encapsulation layer together. That is, a single processing step may be used to encapsulate the semiconductor chips and the interposer in the encapsulation layer.
Stmicroelectronics Pte Ltd


02/04/16
20160035589 

Semiconductor device, related manufacturing method, and related electronic device


A method for manufacturing semiconductor device may include the following steps: performing an etching process to remove a sacrificial layer from a first composite structure, wherein the first composite structure includes a first substrate structure; performing a heat treatment to release a gas from the first composite structure; performing a cleaning process to remove an oxide layer from the first composite structure; and combining the first composite structure with a second composite structure that includes a second substrate structure and an electronic component positioned on the second substrate substructure, such that the first substrate structure is combined with the second substrate structure to form an enclosure structure that encloses the electronic component.. .
Semiconductor Manufacturing International (shanghai) Corporation


02/04/16
20160035587 

Ultrasonic tank and methods for uniform glass substrate etching


In some embodiments, an ultrasonic tank includes a container, an etching solution tank comprising a working area disposed within the container, and a plurality of ultrasonic transducers arranged about a perimeter of the etching solution tank in a configuration that provides a standard deviation of ultrasonic power within the working area of less than about 0.35.. .
Corning Incorporated


02/04/16
20160035578 

Method of forming a semiconductor device including a pitch multiplication


Disclosed herein is a manufacturing method of a semiconductor device that includes forming first and second layers over an underlying martial such that the first layer is between the underlying material and the second layer, forming a third layer over the second layer, forming first and second core portions apart from each other over the third layer, forming a gap portion between the first and the second core portions; and removing the second and the third layers by using the first and the second core portions and the gap portion as a mask to expose a part of the first layer.. .
Micron Technology, Inc.


02/04/16
20160035577 

Multi-layer mask including non-photodefinable laser energy absorbing layer for substrate dicing by laser and plasma etch


Methods of dicing substrates having a plurality of ics. A method includes forming a multi-layered mask comprising a laser energy absorbing, non-photodefinable topcoat disposed over a water-soluble base layer disposed over the semiconductor substrate.
Applied Materials, Inc.


02/04/16
20160035576 

Split-gate semiconductor device with l-shaped gate


A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner.
Cypress Semiconductor Corporation


02/04/16
20160035575 

Methods of forming a semiconductor device


The present disclosure relates to methods for forming a high-k gate dielectric, the methods comprising the steps of providing a semiconductor substrate, cleaning the substrate, performing a thermal treatment, and performing a high-k dielectric material deposition, wherein said thermal treatment step is performed in a non-oxidizing ambient, leading to the formation of a thin interfacial layer between said semiconductor substrate and said high-k dielectric material and wherein the thickness of said thin interfacial layer is less than 10 Å.. .
Taiwan Semiconductor Manufacturing Company, Ltd.


02/04/16
20160035574 

Metal semiconductor alloy contact resistance improvement


Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. A first transition metal liner including at least one first transition metal element, a second transition metal liner including at least one second transition metal element that is different from the at least one first transition metal element and a metal contact are sequentially formed within each contact opening.
International Business Machines Corporation


02/04/16
20160035572 

Doping of a substrate via a dopant containing polymer film


Disclosed herein is a method for doping a substrate, comprising disposing a coating of a composition comprising a copolymer, a dopant precursor and a solvent on a substrate; where the copolymer is capable of phase segregating and embedding the dopant precursor while in solution; and annealing the substrate at a temperature of 750 to 1300° c. For 0.1 second to 24 hours to diffuse the dopant into the substrate.
Dow Global Technologies Llc


02/04/16
20160035571 

Lithography using high selectivity spacers for pitch reduction


A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask.
Taiwan Semiconductor Manufacturing Company, Ltd.


02/04/16
20160035567 

Semiconductor device


A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween.
Semiconductor Energy Laboratory Co., Ltd.


02/04/16
20160035566 

Methods and apparatuses for showerhead backside parasitic plasma suppression in a secondary purge enabled ald system


Disclosed are methods of depositing films of material on semiconductor substrates employing the use of a secondary purge. The methods may include flowing a film precursor into a processing chamber and adsorbing the film precursor onto a substrate in the processing chamber such that the precursor forms an adsorption-limited layer on the substrate.
Lam Research Corporation


02/04/16
20160035565 

Methods for fabricating integrated circuits using directed self-assembly chemoepitaxy


Methods for directed self-assembly (dsa) using chemoepitaxy in the design and fabrication of integrated circuits are disclosed herein. An exemplary method includes forming an a or b-block attracting layer over a base semiconductor layer, forming a trench in the a or b-block attracting layer to expose a portion of the base semiconductor layer, and forming a neutral brush or mat or sams layer coating within the trench and over the base semiconductor layer.
Globalfoundries, Inc.


02/04/16
20160035563 

Apparatus and processing semiconductor wafers


An apparatus for processing a semiconductor wafer includes a factory interface configured to couple with a manufacturing chamber. The factory interface includes a robot; an orienter adjacent to the robot; and a particle remover above the orienter and facing toward a wafer.
Taiwan Semiconductor Manufacturing Company Ltd.


02/04/16
20160035560 

Carrier system for processing semiconductor substrates, and methods thereof


In accordance with an alternative embodiment of the present invention, a method for forming a semiconductor device includes applying a paste over a semiconductor substrate, and forming a ceramic carrier by solidifying the paste. The semiconductor substrate is thinned using the ceramic carrier as a carrier..
Infineon Technologies Ag


02/04/16
20160035545 

Methods and systems for managing semiconductor manufacturing equipment


Provided are methods and systems for managing semiconductor manufacturing equipment. A method may include preventive maintenance involving steps of disassembling, cleaning, and assembling parts of a chamber.
Samsung Electronics Co., Ltd.


02/04/16
20160035542 

Method of conditioning vacuum chamber of semiconductor substrate processing apparatus


A method of conditioning a vacuum chamber of a semiconductor substrate processing apparatus includes forming a layer of an organic polymeric film on plasma or process gas exposed surfaces thereof. The method includes: (a) flowing a first reactant in vapor phase of a diacyl chloride into the vacuum chamber; (b) purging the vacuum chamber after a flow of the first reactant has ceased; (c) flowing a second reactant in vapor phase into the vacuum chamber selected from the group consisting of a diamine, a diol, a thiol, and a trifunctional compound to form a layer of an organic polymeric film on the plasma or process gas exposed surfaces of the vacuum chamber; and (d) purging the vacuum chamber to purge excess second reactant and reaction byproducts from the vacuum chamber..
Lam Research Corporation


02/04/16
20160035538 

Pattern shape evaluation method, semiconductor device manufacturing method, and pattern shape evaluation device


A cross-sectional shape or a three-dimensional shape of a circuit pattern is estimated and evaluated only from a planar image of the circuit pattern observed from the above of a wafer. The present invention includes a process of obtaining an observation image of an upper surface of a solid structure, by causing the upper surface of a substrate to be irradiated and scanned with a converged energy beam from a direction substantially perpendicular to a main surface of the substrate having the structure formed on the upper surface thereof, and detecting and/or measuring intensities of a secondary energy beam generated in the substrate and the structure or an energy beam reflected or scattered from the substrate or the structure, a process of obtaining uncertainty information regarding an intensity of scattering caused by an irregular shape of a surface of the structure, from an irradiation position of the converged energy beam in the observation image of the upper surface and the measured intensity, a process of obtaining an inclination angle θ of the surface of the structure, based on the obtained uncertainty information; and a process of estimating a solid shape of the structure, based on the obtained inclination angle θ..
Hitachi High-technologies Corporation


02/04/16
20160035527 

Fuse structure


A fuse structure comprises a first conductive layer on a first level. The first conductive layer comprises a fuse line extending in a first direction.
Taiwan Semiconductor Manufacturing Company, Ltd.


02/04/16
20160035500 

Ionic electron conductive polymer capacitor


Technologies are generally described for an electron conductive polymer capacitor may incorporate a conductive polymer mixture embedded with carbon nanoparticles between electrodes to rapidly charge and store large amounts of charge compared to conventional electrolytic capacitors. Such a capacitor may be constructed with a laminate sheet including layers of inner and outer electrodes, an electrolyte mixture between the electrodes, a conductive polymer mixture, and a composite mixture of carbon nanoparticles embedded in the conductive polymer between the inner electrodes.
Empire Technology Development Llc


02/04/16
20160035458 

The producing self-rolling elongate element, in particular an electric cable and self-rolling elongate element, in particular an electric cable


The subject of the invention is the method of producing self-rolling elongate element, in particular an electric cable and self-rolling elongate element, in particular an electric cable intended especially for power and signal transmission wires, ropes and cords. The essence of the method, according to the invention, consists in applying to the power transmission wires, the outer coating (1) of a polymer composite, consisting of a polymer and a material, which has magnetic properties in the amount of from 10% to 60% by weight and subsequently, the power transmission wire (2) with the applied outer layer (1) is being magnetized in the magnetic field, which lines are situated along the axis of element rolling, wherein the magnetic induction is equal to at least 2 tesla.

02/04/16
20160035457 

Field effect transistor


There is provided a field effect transistor which comprises a gate insulating layer, a gate electrode, a semiconductor layer, a source electrode and a drain electrode. The gate insulating layer contains an organic compound that contains a silicon-carbon bond and a metal compound that contains a bond between a metal atom and an oxygen atom; and the metal atoms are contained in the gate insulating layer in an amount of 10 to 180 parts by weight with respect to 100 parts by weight of the total of carbon atoms and silicon atoms.
Toray Industries, Inc.


02/04/16
20160035456 

Electrically conductive polymer compositions


Embodiments of the present invention relate to an electrically conductive composition and an article. The electrically conductive composition comprises a polymer, graphene sheets, and carbon black, wherein the ratio of the graphene sheets to carbon black is about 1:2 to about 1:20.
Vorbeck Materials Corp.


02/04/16
20160035405 

Semiconductor device capable of reducing power consumption


According to one embodiment, a semiconductor device includes a first transistor of a first conductivity type, and a first logical circuit. The first transistor of the first conductivity type is connected between a first node to which a power supply voltage is applied and a second node.
Kabushiki Kaisha Toshiba


02/04/16
20160035400 

Bank control circuit and semiconductor memory device including the same


A bank control circuit includes an implicit signal generation unit suitable for activating an implicit signal when a first active signal corresponding to a bank which is in an activated state bank, among a plurality of banks; and a delay unit suitable for delaying the implicit signal by a predetermined time, wherein the bank corresponding to the first active signal is precharged based on the implicit signal and activated again based on the delayed implicit signal.. .
Sk Hynix Inc.


02/04/16
20160035396 

Semiconductor device


According to an embodiment, a semiconductor device includes a plurality of wiring patterns of wiring lines disposed in parallel in a line-and-space pattern in a predetermined pitch and extend in a first direction in a first region, first bending patterns that extend pairs of the wiring lines in a second in a second region adjacent to the first region, second bending patterns extend the pairs of wiring lines in opposite directions along the orientation of the first direction in the second region, and dummy patterns separated from the two second bending patterns at a predetermined distance.. .
Kabushiki Kaisha Toshiba


02/04/16
20160035385 

Contamination reduction head for media


A cleaning head and methods for removing contaminants from a data storage media, the cleaning head having a cleaning surface comprising a self-assembled monolayer, with the cleaning surface leading a read/write transducer. The self-assembled monolayer is selected to have a terminal functional group that has a high affinity to the contaminant(s) desired to be attracted and/or removed..
Seagate Technology Llc


02/04/16
20160035379 

Devices including a gas barrier layer


Devices that include a near field transducer (nft); a gas barrier layer positioned on at least a portion of the nft; and a wear resistance layer positioned on at least a portion of the gas barrier layer wherein the gas barrier layer includes tantalum oxide (tao), titanium oxide (tio), chromium oxide (cro), silicon oxide (sio), aluminum oxide (alo), titanium oxide (tio), zirconium oxide (zro), yttrium oxide (yo), magnesium oxide (mgo), beryllium oxide (beo), niobium oxide (nbo), hafnium oxide (hfo), vanadium oxide (vo), strontium oxide (sro), or combinations thereof; silicon nitride (sin), aluminum nitride (al), boron nitride (bn), titanium nitride (tin), zirconium nitride (zrn), niobioum nitride (nbn), hafnium nitride (hfn), chromium nitride (crn), or combinations thereof silicon carbide (sic), titanium carbide (tic), zirconium carbide (zrc), niobioum carbide (nbc), chromium carbide (crc), vanadium carbide (vc), boron carbide (bc), or combinations thereof or combinations thereof.. .
Seagate Technology Llc


02/04/16
20160035366 

Echo suppression device and echo suppression method


An echo suppression device includes a processor; and a memory which stores a plurality of instructions, which when executed by the processor, cause the processor to execute: generating a corrected sound signal by suppressing an echo signal representing an echo generated by collecting, by a sound input unit, a sound arising from a reproduction sound signal reproduced by a sound output unit; obtaining a gain to attenuate the corrected sound signal according to a degree of distortion of the echo signal with which intensity of the echo signal non-linearly changes with respect to an intensity change of the reproduction sound signal; and suppressing the corrected sound signal according to the gain.. .
Fujitsu Limited


02/04/16
20160035331 

Installation structure for acoustic transducer and musical instrument


An installation structure for an acoustic transducer for vibrating a vibrated body of a musical instrument in a first direction for permitting the vibrated body to generate sounds, including: the acoustic transducer having a main body and a vibrating portion that vibrates in the first direction; a support portion to be fixed to a housing of the musical instrument for supporting the main body; and a cover member fixed to the support portion for covering the acoustic transducer, wherein the support portion includes a base plate portion to be held in surface contact with the housing so as to be fixed thereto, a first fixing portion to which the main body is fixed and which supports the main body, and a second fixing portion to which the cover member is fixed, and wherein the first and second fixing portions are connected to the base plate portion independently of each other.. .
Yamaha Corporation


02/04/16
20160035275 

Display device and electronic device including display device


Objects are to provide a display device the power consumption of which is reduced, to provide a self-luminous display device the power consumption of which is reduced and which is capable of long-term use in a dark place. A circuit is formed using a thin film transistor in which a highly-purified oxide semiconductor is used and a pixel can keep a certain state (a state in which a video signal has been written).
Semiconductor Energy Laboratory Co., Ltd.


02/04/16
20160035270 

Strobe driving circuit, strobe driving method, array substrate and display apparatus


There are provided with a strobe driving circuit, a strobe driving method, an array substrate and a display apparatus. The strobe driving circuit includes: a first driving unit for receiving a timing control signal, generating a first strobe driving signal based on the power signal under the control of the timing control signal; a first energy storing unit, storing energy based on the first strobe driving signal; a second driving unit connected to the first energy storing unit, for generating a second strobe driving signal based on the energy stored by the first energy storing unit under the control of the timing control signal.
Hefei Boe Optoelectronics Technology Co., Ltd.


02/04/16
20160035245 

Method and educational tool for teaching vocational skills to people with autism


The method involves teaching vocational skills to people with autism via facilitated, repeated hands-on practice. The method may include the system for analyzing the steps of a target vocational skill and the collecting the physical materials necessary to practice that skill in a hands-on fashion.

02/04/16
20160035244 

Newborn computer applications


An electronic version for how to care for an infant child on smartphone/tablet devices. Students will access the application via the appstore/playstore on their device and will be provided login information from their administrator/teacher.

02/04/16
20160035237 

Systems and methods for providing a personalized educational platform


The disclosed technology, in certain embodiments, generates customized assessments based on educational content to match the needs and learning styles of individual learners. The educational content may be identified and provided to a user based on user profile information such as grade, age, and/or education level.
Fishtree Ltd.






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