|| List of recent Duc-related patents
| Methods for distributing content in multi-room environment|
A method enables a user to pause or stop content reproduction in one viewing room, and resume content reproduction in another viewing room according to a timing condition. According to an exemplary embodiment, the method is used in a system including first and second video devices, and includes steps of: receiving by the first video device while playing back a program, a first control signal to interrupt the playback; enabling display of a message by the second video device for a predetermined time interval asking a viewer whether to continue playback of the program by the second video device; receiving by the second video device a second control signal within the predetermined time interval to continue playback of the program; and enabling playback of the program by the second video device in response to the second control signal..
| Content distribution|
A content receiver useable in a broadcast content distribution system includes a content source that broadcasts audio/video content for reception by content receivers with associated metadata defining links to other content for possible reproduction by the content receiver and information indicative of a category of each link. The content receiver is configured to generate link information for display in dependence upon received metadata relating to links having a subset of categories while reproducing the broadcast audio/video content, and includes a user control operable to select a link for which link information is currently displayed by the content receiver causing the content receiver to reproduce content defined by that link and a category memory storing category information defining the subset of categories, the content receiver configured to modify stored category information in dependence upon which links are selected using the user control..
| Analytical model for predicting current mismatch in metal oxide semiconductor arrays|
A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (mos) array. A first subset of cells in the mos array is selected and current measured for each of these cells.
| Triple-pattern lithography layout decomposition|
Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity.
| Semiconductor device, semiconductor system and control method of semiconductor device|
A semiconductor device includes a mode register set suitable for generating a first internal control signal and a second internal control signal, a per-dram addressability (pda) driving unit suitable for resetting the mode register set in response to the first internal control signal and an input value of data inputted through a data pad, and a cycle redundancy check (crc) driving unit suitable for performing a crc operation by checking whether or not data are correctly inputted through the data pad without an error in response to the first internal control signal and the second internal control signal.. .
| Semiconductor integrated circuit and method of processing in semiconductor integrated circuit|
A semiconductor integrated circuit includes: a first-combinational-circuit to output a state-value depending on an input signal and a parity-value of the state-value which are stored by a first-flip-flop-circuit; a first-parity-check-circuit to perform a parity check based on the state-value and the parity-value and output a first-parity-error; a second-flip-flop-circuit to store the state-value and the parity-value output by the first-combinational-circuit; a second-parity-check-circuit to perform a parity check based on the state-value and the parity-value stored in the second-flip-flop-circuit and output a second-parity-error; and a selector to, when the first-parity-error is not output but the second-parity-error is output, output the state-value stored in the first-flip-flop-circuit to the first-combinational-circuit, and when the first-parity-error is output but the second-parity-error is not output, output the state-value stored in the second-flip-flop-circuit to the first-combinational-circuit, wherein the first-combinational-circuit outputs a current state-value depending on the state-value output by the selector and the input signal.. .
| Power supply device|
In a power supply device, the bridge circuit is configured by connecting, in parallel, a plurality of series circuits of an inverse-parallel connection circuit of a semiconductor switch and a diode. A control unit controls switching of a semiconductor switch so that a voltage v between ac terminals becomes zero voltage in equal periods α before and after a center point shifted from one zero crossing point in one cycle of the input current by a compensation period (angle) β calculated from a voltage applied to a resonance circuit constituted by the power receiving coil and a resonance capacitor cr and an induced voltage of the power receiving coil, and becomes a positive-negative voltage whose peak value is the voltage vo between dc terminals in other periods..
| Memory system, semiconductor device and methods of operating the same|
A memory system, a semiconductor memory device and methods of operating the same may perform a read operation on the basis of flag data stored in a flag register, without reading the flag data stored in a memory array, when performing the read operation, so that a time taken for the read operation may be reduced.. .
| Semiconductor device with configurable support for multiple command specifications, and method regarding the same|
A device includes a nand flash memory, and a generic command interface configured to interpret both an open nand flash interface specification and a first nand flash specification to perform an associated one of command operations on the nand flash memory, the open nand flash interface specification and the first nand flash specification being different from each other.. .
| Semiconductor memory device and memory system|
A semiconductor memory device and a memory system are disclosed. The semiconductor memory device includes: a memory bank configured to include a first section and a second section, each of which is comprised of a plurality of memory cells; an lio line switching circuit configured to generate first and second selection signals on the basis of page-size information; and an input/output (i/o) circuit configured to access the first section, the second section, or the first and second sections on the basis of the first and second selection signals, wherein the page-size information includes first and second information.
| Data processing device, semiconductor external view inspection device, and data volume increase alleviation method|
Provided is a data processing device with which, when a temporary network congestion occurs, it is possible to avoid a buffer overflow and sustain a process. When a request for retransmission of the same data with respect to a processor element from a buffer occurs continuously a prescribed number of iterations, a data processing device according to the present invention determines that it is possible that a buffer overflow occurs, and suppresses an increase in the volume of data which is accumulated in the buffer (see fig.
| Wifi display compatible network gateway|
The invention relates to a method and a device for interconnection in a network gateway comprising a first wireless communication interface and a second interface adapted to the implementation of content sharing operations using an interoperability protocol, the method comprising steps of transmission, by the first interface, of at least one information element aiming to enable the gateway to be detected by a remote equipment as being compatible with a function for reproduction using a wireless communication interface, of reception of data frames defined in a link layer of a wireless network protocol, the data frames comprising an item of audiovisual content and being received from a second remote device connected to the first interface by means of a wireless connection and of transmission of the content received at said second interface to a reproduction device.. .
| Inferring user profile attributes from social information|
User profile information for a user of a social networking system is inferred based on information about user profile of the user's connections in the social networking system. The inferred user profile attributes may include age, gender, education, affiliations, location, and the like.
| Wellness segmentation tool|
Embodiments of the invention provide for systems, computer program products, and methods for a financial wellness segmentation tool that allows a user to create customized wellness segmentation reports in order to segment the wellness metrics of plan participants in one or more retirement accounts into customized groups for additional analysis. The wellness segmentation tool searches the underlying data related to individual wellness scores, wellness metrics, retirement accounts, and participant information, and creates customized wellness segmentation reports for the user based on one or more retirement plans, selection criteria, and data points selected by the user.
| Focused advertising across multiple communication channels|
This document describes, among other things, systems and methods for generating advertising campaigns or listings utilizing catalog information. A method comprises receiving, by an online publication system, a product catalog; accessing, by the online publication system, a merchant profile; and using the product catalog and the merchant profile to develop advertising data, wherein the advertising data includes at least one of an advertising campaign, a marketplace listing, or a store listing.
| Transcription support device, method, and computer program product|
According to an embodiment, a transcription support device includes a first voice acquisition unit, a second voice acquisition unit, a recognizer, a text acquisition unit, an information acquisition unit, a determination unit, and a controller. The first voice acquisition unit acquires a first voice to be transcribed.
| Method, a device, a system, a computer program and a computer program product for determining information about efficiency of an inductive charging system, having a primary coil embedded in a road infrastructure|
The invention concerns a method for determining information about efficiency of an inductive charging system having a primary coil (101, 112), in particular embedded in a road infrastructure (100), wherein a first inductive coupling efficiency component attributed to said road infrastructure is determined from a total efficiency depending on a second inductive coupling efficiency component attributed to a position of a secondary coil (102) relative to said primary coil (101, 112) and of a third inductive coupling efficiency component attributed to an electric circuit comprising said secondary coil (102).. .
| Adaptive inversion for vertical resistivity logs from multiaxial induction measurements|
A method for logging a formation or sample includes obtaining a plurality of multiaxial conductivity measurements from the formation or sample. A horizontal resistivity measurement, a dip measurement and a dip azimuth measurement are derived from the plurality of multiaxial conductivity measurements.
| Co-located scanning, printing and/or machining devices for medical constructs|
The present disclosure provides devices and methods for obtaining images of body parts, implants, bones, and other areas of a patient that are involved in plastic or reconstructive surgery. A scanning device obtains an image of a body part of a patient to be replicated, sends it to a computer for review and/or manipulation, and the computer sends it to a printer or fabricator for reproduction.
| Minimally invasive lung volume reduction devices, methods, and systems|
A lung volume reduction system is disclosed comprising an implantable device adapted to be delivered to a lung airway of a patient in a delivery configuration and to change to a deployed configuration to bend the lung airway. The invention also discloses a method of bending a lung airway of a patient comprising inserting a device into the airway in a delivery configuration and bending the device into a deployed configuration, thereby bending the airway..
| Absorbent articles having pockets and related methods therefor|
The present disclosure provides articles having an absorbent core. The absorbent core has a plurality of segmented volumes possessing an absorbent material therein.
| Ultrasonic transducer with shock pulsing masses|
What is presented is an ultrasonic waveguide for the transmission of ultrasonic vibrations that establishes a plurality of node and anti-node positions that are each along the ultrasonic waveguide's central axis. The ultrasonic waveguide comprises a waveguide tube, which has both a proximal end and a distal end; a waveguide fitting, which has both a threaded end and a impact surface; and a spring, shock-pulsing mass, and stop.
| Physiological acoustic monitoring system|
An acoustic monitoring system has an acoustic front-end, a first signal path from the acoustic front-end directly to an audio transducer and a second signal path from the acoustic front-end to an acoustic data processor via an analog-to-digital converter. The acoustic front-end receives an acoustic sensor signal responsive to body sounds in a person.
| Ultrasound medical apparatus and ultrasound diagnosis apparatus|
The ultrasound medical apparatus according to the embodiments include a sheath, a capsule body unit, and a fixation mechanism. The sheath is inserted into the inner cavity of a subject, having an outer peripheral surface that contacts the inner wall surface of the inner cavity of the subject with a liquid filled inside thereof.
| Flow measurement apparatus and method|
The velocity of fluids containing particles that scatter ultrasound can be measured by determining the doppler shift of the ultrasound scattered by the particles in the fluid. Measuring fluid flow in cylindrical vessels such as blood vessels is an important use of doppler ultrasound.
| Estimation and display for vector doppler imaging using plane wave transmissions|
Vector doppler imaging (vdi) improves on conventional color doppler imaging (cdi) by giving speed and direction of blood flow at each pixel of a display generated by a computing system. Multiple angles of plane wave transmissions (pwt) via an ultrasound transducer conveniently give projected doppler measurements over a wide field of view, providing enough angular diversity to identify velocity vectors in a short time window while capturing transitory flow dynamics.
| Methods and apparatus for stimulating and recording neural activity|
Thermal drawing processes can be used to make multifunctional, high-resolution neural probes for neural recording and stimulation. An exemplary neural probe may include one or more conductive fibers or microelectrodes coated with two or more layers of insulating material, at least one of which is partially etched to expose a tip at the neural probe's distal end.
| System and method for voice control of medical devices|
A diagnostic system includes a plurality of semiconductor diodes, a multiplexer, and one or more waveguide structures to form an output beam. A lens system communicates some of the output beam onto a part of a user's body comprising blood to perform a measurement.
| Cell surface coating with hyaluronic acid oligomer derivative|
A method of localizing reproduction assisting hyaluronic acid to reproductive cell surfaces by covalently linking it to lipids is disclosed.. .
| Method for continuous production of high-molecular-weight polycarbonate resin|
The process comprises a process (a) for producing an aromatic polycarbonate prepolymer by polycondensation reaction of an aromatic dihydroxy compound with diester carbonate and a process (b) for conducting linking and highly-polymerizing reaction of the aromatic polycarbonate prepolymer with an aliphatic diol compound in the linking and highly-polymerizing reactor, wherein the aromatic polycarbonate prepolymer produced by the process (a) is fed continuously to the linking and highly-polymerizing reactor, while the aliphatic diol compound is fed continuously thereto under reduced pressure of 10 torr or less to carry out the reaction.. .
| Method of treating diabetic peripheral neuropathy through amendment of pre-neuronal diabetic coagulative micro-angiopathy and neuronal deficiency of mitochondrial atp production, and through induction of neuronal regeneration|
Thus, sag+alc+ala was effective in mitigating and curing their distresses. It shall be one of the logical and practical means of prompt dpn therapy not only to alleviate dpn but also to lead to “cure.”.
| Indomethacin analogs for the treatment of castrate-resistant prostate cancer|
Provided are compositions for inhibiting a biological activity of an aldoketo reductase family 1, member c3 (akr1 c3) polypeptide. In some embodiments, the compositions are indomethacin derivatives that are akr1 c3-specific inhibitors.
| 9-[4-(3-chloro-2-fluoro-phenylamino)-7-methoxy-quinazoline-6-yloxy]-1,4-diaza-spiro[5.5]undecane-5-one dimaleate, use thereof as a medicament and method for the production thereof|
Which has valuable pharmacological properties, particularly an inhibiting effect on signal transduction mediated by tyrosine kinases, processes for stereoselectively preparing these compounds, particularly pharmaceutical formulations suitable for inhalation and their use for the treatment of diseases, particularly tumoral diseases, benign prostatic hyperplasia and diseases of the lungs and airways.. .
| Amyloid beta-protein-specific production-inhibiting polypeptide|
This object can be achieved by a polypeptide having the amino acid sequence represented by any one of seq id nos: 1, 13, 14, and 22, that binds to the n-terminal region of βctf; a γ-secretase activity inhibitor containing the polypeptide; β-secretase activity inhibitor; aβ protein production inhibitor; and an agent for treating and/or preventing alzheimer's disease.. .
| Cleaning liquid for semiconductor device and method for cleaning substrate for semiconductor device|
(4)′ water.. .
| Methods and apparatus for improving remote nfc device detection using a low power oscillator circuit|
A method, an apparatus, and a computer program product for inductive communication are provided in connection with providing mechanisms for detecting a remote nfc device without excessive power consumption. In one example, a communications device is equipped to monitor frequency oscillations associated with a nfc antenna using a calibrated lpo, determine that a number of occurrences of the frequency oscillations from a reference frequency is greater than a frequency deviation threshold, and perform a nfc polling procedure in response to the determination..
| Vacuum-grooved membrane abrasive polishing wafer workholder|
Hard-material, flat-surfaced workpieces such as semiconductor wafers or sapphire disks are attached with vacuum to the flexible elastomeric membrane of a wafer carrier that allows one surface of the workpiece to be in conformal abrading contact with a moving flat-surfaced abrasive. The elastomeric membrane external wafer attachment surface has a pattern of recessed vacuum grooves and vacuum is supplied to the grooves to firmly attach the rigid-material silicon wafer in flat-surfaced contact with the membrane.
| Method for the double-side polishing of a semiconductor wafer|
A method of simultaneous double-side polishing of at least one semiconductor material wafer includes disposing each wafer in a respective suitably dimensioned cutout in a carrier plate having a front and rear side. The at least one wafer is polished between an upper polishing plate covered with a first polishing pad and a lower polishing plate covered with a second polishing pad while supplying a polishing agent.
| Terminal connection device for a power cable|
Terminal connection device (10) for connecting an end of a medium- or high-voltage power cable (42) to a connection point, the terminal connection device (10) comprising an interface cable (12) having first and second end portions, comprising an inner conductor (14) and a conductive or semiconductive layer (18). The terminal connection device further comprises a first stress control tube (36) comprising—a stress control element (38), and an insulating layer (40) arranged around the stress control element (38), wherein the first stress control tube (36) is mounted on the first end portion of the interface cable (12).
| Method of focus measurement, exposure apparatus, and method of manufacturing semiconductor device|
A method of focus measurement of the embodiment irradiates exposure light from a first direction and projects first and second line-and-space patterns on a substrate. Further, exposure light is irradiated from a second direction and third and fourth line-and-space patterns are projected on the substrate.
| Method of forming fine patterns of a semiconductor device|
A method of forming fine patterns in a semiconductor device includes forming narrow-width patterns in a first region and wide-width patterns in a second region, where the widths of the narrow-width patterns are smaller than the resolution limitations in a photolithography process used to make the semiconductor device. The first and second regions may comprise cell array regions, with memory cells in the first region and peripheral circuits for operating the memory cells in the second region.
| Nitrogen doped amorphous carbon hardmask|
Embodiments described herein generally relate to the fabrication of integrated circuits and more particularly to nitrogen doped amorphous carbon layers and processes for depositing nitrogen doped amorphous carbon layers on a semiconductor substrate. In one embodiment, a method of forming a nitrogen doped amorphous carbon layer on a substrate is provided.
| Semiconductor device and method for manufacturing the same|
By using a conductive layer including cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a tft is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of cu can be prevented; thus, a highly reliable semiconductor device can be manufactured.
| Methods of forming semiconductor devices including low-k dielectric layer|
Methods of forming a dielectric layer are provided. The methods may include introducing oxygen radicals and organic silicon precursors into a chamber to form a preliminary dielectric layer on a substrate.
| Semiconductor device and method for fabricating the same|
A semiconductor device including a conductive layer, a diffusion barrier layer formed over the conductive layer, including a refractory metal compound, and acquired after a surface treatment, and a metal silicide layer formed over the diffusion barrier layer. The adhesion between a diffusion barrier layer and a metal silicide layer may be improved by increasing the surface energy of the diffusion barrier layer through a surface treatment.
| Method of fabricating semiconductor patterns|
A method of fabricating semiconductor patterns includes steps as follows: firstly, a substrate is provided and has at least a first semiconductor pattern and at least a second semiconductor pattern, wherein a line width of the first semiconductor pattern is identical to a line width of the second semiconductor pattern. Then, a barrier pattern is formed over a surface of the first semiconductor pattern, and the second semiconductor pattern is exposed.
| Method for fabricating semiconductor device|
A method of fabricating a semiconductor device includes forming an interlayer insulating layer on a substrate, the interlayer insulating layer including a first trench and a second trench, forming a first conductive layer along sidewall surfaces and bottom surface of the first trench and forming a second conductive layer along sidewall surfaces and bottom surface of the second trench, forming a mask pattern on the second conductive layer, the mask pattern filling the second trench and being a bottom anti-reflective coating (barc), and removing the first conductive layer using the mask pattern.. .
| Method for fabricating a semiconductor device|
The present invention relates to a method for fabricating a semiconductor structure comprising a semiconductor layer and a metallic layer, to improve the breakdown voltage properties of the device and reduce leakage currents, the method comprises the steps of a) providing a semiconductor layer comprising defects and/or dislocations; b) removing material at one or more locations of the defects and/or dislocations thereby forming pits in the semiconductor layer, c) passivating the pits, and c) providing the metallic layer over the semiconductor layer. The invention also relates to a corresponding semiconductor structure..
| Process for the manufacture of a semiconductor device|
A method for the manufacture of at least part of a thin-film device including forming one or more indentations in a substrate, preferably a plastic substrate, an indentation having sidewalls and a base; filling at least one of the one or more indentations with a first ink, the first ink having a first material precursor, preferably a first metal-, semiconductor-, or a metal-oxide precursor; and, annealing at least a portion of the first ink such that a surface of the base inside the indentation is dewetted and a narrowed first structure of the first material inside of the indentation is formed.. .
| Method for manufacturing a semiconductor device having a channel region in a trench|
A method of manufacturing a semiconductor device includes forming a semiconductor diode by forming a drift region, forming a first semiconductor region of a first conductivity type in or on the drift region and electrically coupling the first semiconductor region to a first terminal via a first surface of a semiconductor body, etching a trench into the semiconductor body, and forming a channel region of a second conductivity type in the trench and electrically coupling the channel region to the first terminal via the first surface of the semiconductor body. A first side of the channel region adjoins the first semiconductor region..
| Method of manufacturing semiconductor device, substrate processing apparatus and non-transitory computer-readable recording medium|
Provided is a method of manufacturing a semiconductor device, which is capable of increasing the controllability of the concentration of carbon in a film by increasing the yield when a boron carbonitride film or a boron nitride film is formed. The method includes forming a film containing boron, carbon and nitrogen or a film containing boron and nitrogen on the substrate by performing, a predetermined number of times, a cycle including supplying a source gas consisting of boron and a halogen element to a substrate and supplying a reactive gas consisting of carbon, nitrogen and hydrogen to the substrate..
| Quantum dots made using phosphine|
A process is disclosed for producing quantum dots (qds) by reacting one or more core semiconductor precursors with phosphine in the presence of a molecular cluster compound. The core semiconductor precursor(s) provides elements that are incorporated into the qd core semiconductor material.
| Method for separating and transferring ic chips|
A method for separating a multiple number of semiconductor devices or semiconductor integrated circuits from a wafer on which the multiple number of semiconductor devices or semiconductor integrated circuits are formed is provided. The method includes forming a mask pattern on a surface of the wafer, and separating each of the semiconductor devices or semiconductor integrated circuits along the mask pattern formed on the surface of the wafer.
| Soi structure for signal isolation and linearity|
Disclosed is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure comprises a first portion of a trench extending through the top semiconductor layer and through a base oxide layer below the top semiconductor layer.
| Method for forming a groove on a surface of flat plate formed of a nitride semiconductor crystal|
Provided is a novel method for forming a groove composed of two smooth inclined surfaces on a surface of a flat plate formed of a nitride semiconductor crystal having an a, c, m-axes. In the present invention, a disk-shaped dicing blade is moved along a direction of the a-axis to form first and second inclined surfaces on the surface of the flat plate.
| Methods for forming sub-resolution features in semiconductor devices|
Methods of forming semiconductor devices and features in semiconductor device structures include conducting an anti-spacer process to remove portions of a first mask material to form first openings extending in a first direction. Another anti-spacer process is conducted to remove portions of the first mask material to form second openings extending in a second direction at an angle to the first direction.
| T-shaped compound semiconductor lateral bipolar transistor on semiconductor-on-insulator|
A base region extends upward from a recessed semiconductor surface of a semiconductor material portion present on an insulator. The base region includes a vertical stack of, an extrinsic base region and an intrinsic base region.
| Method of manufacturing semiconductor device|
Extension regions 7 are formed through implantation using offset sidewalls 6a of a footing profile as a mask, and sidewalls 9 are formed on the offset sidewalls 6a so that source and drain regions 10 are formed into the sidewall through implantation, so that the extension regions 7 are made separated away from both edges of the gate, contributing to enlargement in an effective gate length, and dealing with the narrowed gate pitch, without increasing the number of processes.. .
| Method of fabricating high voltage device|
A method of fabricating a high voltage device includes the step of forming a patterned photoresist layer on a conductive layer and a dielectric below the conductive. The conductive layer and the dielectric layer are patterned by taking the patterned photoresist layer as a mask.
| Semiconductor device and method of manufacturing the same|
A semiconductor device according an aspect of the present disclosure may include an isolation layer formed within a substrate and formed to define an active region, a junction formed in the active region, well regions formed under the isolation layer, and a plug embedded within the substrate between the junction and the well regions and formed extend to a greater depth than the well regions.. .
| Semiconductor structure and method of forming the same|
A method of forming a semiconductor structure includes forming a second iii-v compound layer over a first iii-v compound layer, wherein a carrier channel is located between the first iii-v compound layer and the second iii-v compound layer. The method further includes forming a source feature and a drain feature over the second iii-v compound layer.
| Semiconductor device, memory system including the same, and method of manufacturing the same|
The semiconductor device includes a vertical channel layer formed on a substrate; conductive layer patterns and insulating layer patterns alternately formed around a length of each of the vertical channel layer; and a charge storing layer pattern formed between each of the vertical channel layers and the conductive layer patterns, where each of the charge storing layer patterns is isolated by the insulating layer patterns.. .
| Semiconductor device|
A semiconductor device includes a plurality of conductive layers and a plurality of insulating layers formed alternately with each other, at least one channel layer passing through the plurality of conductive layers and the plurality of insulating layers, and at least one first charge blocking layer surrounding the at least one channel layer, wherein a plurality of first regions, interposed between the at least one channel layer and the plurality of conductive layers, and a plurality of second regions, interposed between the at least one channel layer and the plurality of insulating layers, are alternately defined on the at least one first charge blocking layer, and each of the plurality of first regions has a greater thickness than each of the plurality of second regions.. .
| Semiconductor device and manufacturing method thereof|
A vertical super junction mosfet and a lateral mosfet are integrated on the same semiconductor substrate. The lateral mosfet is electrically isolated from the vertical super junction mosfet by an n-buried isolating layer and an n-diffused isolating layer.
| Method for fabricating semiconductor device|
In a method for fabricating a semiconductor device, a first gate electrode and a second gate electrode are provided on a substrate, the first gate electrode and the second gate electrode being formed in a first region and a second region of the substrate, respectively. A conductive buffer layer is formed along sidewalls of the first gate electrode and the second gate electrode and on upper surfaces of the first gate electrode and second gate electrode.
| Reliable electrical fuse with localized programming and method of making the same|
An electrical fuse has an anode contact on a surface of a semiconductor substrate. The electrical fuse has a cathode contact on the surface of the semiconductor substrate spaced from the anode contact.
| Semiconductor device and manufacturing method thereof|
It is an object to provide a semiconductor device in which a short-channel effect is suppressed and miniaturization is achieved, and a manufacturing method thereof. A trench is formed in an insulating layer and impurities are added to an oxide semiconductor film in contact with an upper end corner portion of the trench, whereby a source region and a drain region are formed.
| Method and system for a gallium nitride vertical jfet with self-aligned source and gate|
A semiconductor device includes a iii-nitride substrate, a first iii-nitride epitaxial layer coupled to the iii-nitride substrate and having a mesa, and a second iii-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a iii-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second iii-nitride epitaxial layer and the iii-nitride gate structure..
| Method of making a transitor|
The invention relates to a method for manufacturing a transistor comprising the preparation of a stack of layers of the semiconductor on insulator type comprising at least one substrate on which an insulating layer and an initial semiconductor layer are successively disposed. The method includes the formation of at least one oxide pad extending from a top face of the insulating layer, the formation of an additional layer made from semiconductor material covering the oxide pad and intended to form a channel for the transistor, the formation of a gate stack above the oxide pad, and the formation of a source and drain on either side of the gate stack..
| Tapered nanowire structure with reduced off current|
Non-planar semiconductor devices including at least one semiconductor nanowire having a tapered profile which widens from the source side of the device towards the drain side of the device are provided which have reduced gate to drain coupling and therefore reduced gate induced drain tunneling currents.. .
| Method of making a semiconductor layer having at least two different thicknesses|
A method is provided for producing a semiconductor layer having at least two different thicknesses from a stack of the semiconductor on insulator type including at least one substrate on which an insulating layer and a first semiconductor layer are successively disposed, the method including etching the first layer so that said layer is continuous and includes at least one first region having a thickness less than that of at least one second region; oxidizing the first layer to form an electrically insulating oxide film on a surface thereof so that, in the first region, the oxide film extends as far as the insulating layer; partly removing the oxide film to bare the first layer outside the first region; forming a second semiconductor layer on the stack, to form, with the first layer, a third continuous semiconductor layer having a different thickness than that of the first and second regions.. .
| Power semiconductor device and method for manufacturing such a power semiconductor device|
A method for manufacturing a power semiconductor device is disclosed which can include: providing a wafer of a first conductivity type; and applying on a second main side of the wafer at least one of a dopant of the first conductivity type for forming a layer of the first conductivity type and a dopant of a second conductivity type for forming a layer of the second conductivity type. A titanium layer with a metal having a melting point above 1300° c.
| Method for producing a semiconductor module|
A semiconductor module is produced by providing a circuit carrier having a metallization, an electrically conductive wire and a bonding device. With the aid of the bonding device, a bonding connection is produced between the metallization and a first section of the wire.
| Copper post solder bumps on substrates|
A method comprises forming semiconductor flip chip interconnects having electrical connecting pads and electrically conductive posts terminating in distal ends operatively associated with the pads. We solder bump the distal ends by injection molding, mask the posts on the pads with a mask having a plurality of through hole reservoirs and align the reservoirs in the mask to be substantially concentric with the distal ends.
| Dual lead frame semiconductor package and method of manufacture|
A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip.
| Semiconductor device and method of manufacturing the same|
A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, and a heat conductive member composed of a solder material. The heat conductive member covers the semiconductor element, and is connected to a connection pad formed on the substrate.
| Singulation apparatus and method|
A singulation apparatus includes a carrier having a plurality of singulation sites and a scribe line between each of the plurality of singulation sites and an adjacent singulation site. The carrier has a top surface configured to receive a semiconductor substrate thereon.
| Method of manufacturing semiconductor device|
In a manufacturing process of a transistor including an oxide semiconductor film, oxygen doping treatment is performed on the oxide semiconductor film, and then heat treatment is performed on the oxide semiconductor film and an aluminum oxide film provided over the oxide semiconductor film. Consequently, an oxide semiconductor film which includes a region containing more oxygen than a stoichiometric composition is formed.
| Semiconductor device and manufacturing method thereof|
A semiconductor device using an oxide semiconductor, with stable electric characteristics and high reliability. In a process for manufacturing a bottom-gate transistor including an oxide semiconductor film, dehydration or dehydrogenation is performed by heat treatment and oxygen doping treatment is performed.
| Gate insulator loss free etch-stop oxide thin film transistor|
A method is provided for fabricating a thin-film transistor (tft). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator.
| Semiconductor device and manufacturing method thereof|
A step for forming an island-shaped semiconductor layer of a semiconductor device used in a display device is omitted in order to manufacture the semiconductor device with high productivity and low cost. The semiconductor device is manufactured through four photolithography processes: four steps for forming a gate electrode, for forming a source electrode and a drain electrode, for forming a contact hole, and for forming a pixel electrode.
| Sputtering target and method for manufacturing semiconductor device|
An object is to provide a deposition technique for depositing an oxide semiconductor film. Another object is to provide a method for manufacturing a highly reliable semiconductor element using the oxide semiconductor film.
| Method of manufacturing semiconductor device|
A semiconductor device includes a substrate made of a semiconductor material, an n-type semiconductor layer arranged on a portion of one principal surface of the substrate, and a p-type semiconductor layer arranged on a portion of the one principal surface of the substrate, the portion not provided with the n-type semiconductor layer. The n-type semiconductor layer includes a portion located right above the p-type semiconductor layer..
| Monolithically isled back contact back junction solar cells using bulk wafers|
According to one aspect of the disclosed subject matter, a method for forming a monolithically isled back contact back junction solar cell using bulk wafers is provided. Emitter and base contact regions are formed on a backside of a semiconductor wafer having a light receiving frontside and a backside opposite said frontside.
| Polycrystalline cdte thin film semiconductor photovoltaic cell structures for use in solar electricity generation|
Solar cell structures formed using molecular beam epitaxy (mbe) that can achieve improved power efficiencies in relation to prior art thin film solar cell structures are provided. A reverse p-n junction solar cell device and methods for forming the reverse p-n junction solar cell device using mbe are described.
| Method of manufacturing semiconductor device|
An improvement is achieved in the performance of a semiconductor device. In a method of manufacturing the semiconductor device, in an n-type semiconductor substrate, a p-type well as a p-type semiconductor region forming a part of a photodiode is formed and a gate electrode of a transfer transistor is formed.
| Method of manufacturing solar cell|
A method of manufacturing a solar cell including a crystalline semiconductor substrate, includes: etching or washing at least part of a first principal surface of the substrate by treatment with an aqueous alkaline solution; and depositing a p-type semiconductor layer containing boron on at least part of a second principal surface of the substrate before the treatment with the aqueous alkaline solution.. .
| Process of forming a back side illumination image sensor|
A process of forming a back side illumination (bsi) image sensor is disclosed. An n-type implant is formed in a semiconductor substrate, and a p-type implant region, surrounding n-type in each pixel, is formed in the n-type implant such that in cross sectional view an n-type implant region is sandwiched between the two p-type implant regions.
| Micro electro mechanical system, semiconductor device, and manufacturing method thereof|
The present invention provides a mems and a sensor having the mems which can be formed without a process of etching a sacrifice layer. The mems and the sensor having the mems are formed by forming an interspace using a spacer layer.
| Method for fabricating nitride semiconductor thin film and method for fabricating nitride semiconductor device using the same|
A method for fabricating a nitride semiconductor thin film includes preparing a first nitride single crystal layer doped with an n-type impurity. A plurality of etch pits are formed in a surface of the first nitride single crystal layer by applying an etching gas thereto.
| Removal of 3d semiconductor structures by dry etching|
Various embodiments include methods of fabricating a semiconductor device that include providing a plurality of nanostructures extending away from a support, forming a flowable material layer between the nanostructures, forming a patterned mask over a first portion of the flowable material and the first portion of the plurality of nanostructures, such that a second portion of the flowable material and a second portion of the plurality of nanostructures are not located under the patterned mask and etching the second portion of the flowable material and the second portion of the plurality of nanostructures to remove the second portion of the flowable material and the second portion of the plurality of nanostructures to leave the first portion of the flowable material and the first portion of the plurality of nanostructures unetched.. .
| Method for manufacturing semiconductor light emitting device|
A semiconductor light emitting device having high reliability and excellent light distribution characteristics can be provided with an n-electrode arranged on a light extraction surface on the side opposite to the surface whereupon a semiconductor stack is mounted on a substrate. A plurality of convexes are arranged on a first convex region and a second convex region on the light extraction surface.
| Substrate processing apparatus, semiconductor device manufacturing method, substrate processing method, and recording medium|
According to the present disclosure, it is possible to prevent particles from being generated and to improve substrate processing quality. A substrate processing apparatus includes cassette mounting unit on which process substrate cassette and dummy substrate cassette are mounted, the process substrate cassette being configured to accommodate a plurality of process substrates, and the dummy substrate cassette being configured to accommodate a plurality of dummy substrates, process chamber configured to process the process substrates and the dummy substrates, substrate support unit installed within the process chamber and provided with a plurality of substrate mounting portions where the process substrates and the dummy substrates are mounted, transfer unit configured to transfer the process substrates and the dummy substrates between the cassette mounting unit and the process chamber, and control unit configured to control substrate processing and to transfer processing of the process substrates and the dummy substrates..
| Monitoring laser processing of semiconductors by raman spectroscopy|
A raman probe is used to detect crystal structure of a substrate undergoing thermal processing in a thermal processing system. The raman probe may be coupled to a targeting system of a laser thermal processing system.
| Wafer alignment and bonding tool for 3d integration|
A bonding apparatus for 3d integration may include a plurality of infrared microscopes that emit and receive infrared light for imaging, a first bonding chuck that holds a first semiconductor structure, and a second bonding chuck that holds a second semiconductor structure, whereby the second bonding chuck has a plurality of openings that are transparent to the received infrared light. A force pin is coupled to the first bonding chuck for applying a predetermined force to the first semiconductor structure for bonding to the second semiconductor structure.
| Expression vector organization, novel production cell generation methods and their use for the recombinant production of polypeptides|
Herein is reported an expression vector comprising—an antibody light chain expression cassette,—an antibody heavy chain expression cassette, and—a selection marker expression cassette, wherein the expression cassettes are arranged unidirectional, and wherein the expression cassettes are arranged in the 5′ to 3′ sequence of antibody heavy chain expression cassette, antibody light chain expression cassette and selection marker expression cassette. Further are reported herein methods for the generation of antibody producing cells and the use of these cells for the recombinant production of antibodies..
| Reengineering mrna primary structure for enhanced protein production|
Described herein are rules to modify natural mrnas or to engineer synthetic mrnas to increase their translation efficiencies. These rules describe modifications to mrna coding and 3′ utr sequences intended to enhance protein synthesis by: 1) decreasing ribosomal diversion via aug or non-canonical initiation codons in coding sequences, and/or 2) by evading mirna-mediated down-regulation by eliminating one or more mirna binding sites in coding sequences..
| Embedded assessment with curriculum feedback of tests generated from an infinite test bank of questions within an encapsulated e-book|
An educational electronic book (e-book) facility that may be suitable for use in public school classrooms and many other environments may be based on an encapsulated html technology to facilitate complete interactive operation without use or risks associated with an external network connection, such as the internet.. .
| Apparatus and method for measuring school climate|
Provided is a process for surveying students to assess school climate and, based on survey answers, providing a real-time dashboard showing school climate to teachers, such that a troubled student's problems can be addressed before the troubled student's education is impaired.. .
| Tooth loosening and removal apparatus with a motion transfer member|
An apparatus including a transducer head and a motion transfer member, and a method for rupturing connective tissues that attach a tooth to an alveolar bone socket are provided. The transducer head generates and transfers vibrational and tapping movements to the motion transfer member.
| Semiconductor device resolution enhancement by etching multiple sides of a mask|
A mask is disclosed which includes a plurality of first phase shift regions disposed on a first side of the mask, and a plurality of second phase shift regions disposed on a second side of the mask. The first phase shift regions and second phase shift regions may be alternating phase shift regions in which phase shift of the first phase shift regions is out of phase, for instance by 180 degrees, from phase shift of the second phase shift regions.
| Method for manufacturing semiconductor device|
A method for manufacturing a semiconductor device includes a photolithography process having steps of a developing solution immersing process. The steps of the developing solution immersing process includes step (a) of dropping a developing solution on a silicon carbide semiconductor substrate and forming a developing solution film so as to have a film thickness of more than 6 μm and step (b) of reducing the film thickness of the developing solution film to 6 μm or less..
| Substrate with multilayer reflective film, reflective mask blank for euv lithography, method of manufacturing reflective mask for euv lithography and method of manufacturing semiconductor device|
An object of the present invention is to provide a substrate with a multilayer reflective film and the like used in the manufacturing of a reflective mask blank for euv lithography which is to be subjected to dry etching with a cl-based gas, wherein in the substrate with the multilayer reflective film, the loss of protective films by the dry etching and subsequent wet cleaning is very limited. The present invention is a substrate with a multilayer reflective film used in the manufacturing of a reflective mask blank for euv lithography, comprising a substrate, a multilayer reflective film disposed on the substrate to reflect euv light, and a protective film disposed on the multilayer reflective film to protect the multilayer reflective film, the protective film includes an alloy containing at least two metals, the alloy being an all-proportional solid solution..
| Extreme ultraviolet (euv) radiation pellicle formation method|
An extreme ultraviolet (euv) photolithography pellicle with at least 70% transmissivity to euv can be formed from a layer of semiconductor material applied to a substrate. The bottom surface of the layer can be exposed by forming support structure(s) from the substrate.
| Secondary battery|
A secondary battery includes: a negative electrode; a positive electrode containing a p-type semiconductor material; and an isolation layer configured to isolate the negative electrode from the positive electrode and including a hole transmission member. The isolation layer is layered by being applied to at least one of the negative electrode and the positive electrode.
| Conductive polymer and si nanoparticles composite secondary particles and structured current collectors for high loading lithium ion negative electrode application|
Embodiments of the present invention disclose a composition of matter comprising a silicon (si) nanoparticle coated with a conductive polymer. Another embodiment discloses a method for preparing a composition of matter comprising a plurality of silicon (si) nanoparticles coated with a conductive polymer comprising providing si nanoparticles, providing a conductive polymer, preparing a si nanoparticle, conductive polymer, and solvent slurry, spraying the slurry into a liquid medium that is a non-solvent of the conductive polymer, and precipitating the silicon (si) nanoparticles coated with the conductive polymer.
| Secondary battery|
A secondary battery includes a first electrode, a second electrode, an ion transmission member in contact with the first electrode and the second electrode, and a hole transmission member in contact with the first electrode and the second electrode. Suitably, the first electrode contains a composite oxide.
| Electrode for secondary battery, preparation thereof, and secondary battery and cable-type secondary battery comprising the same|
The present disclosure provides a sheet-form electrode for a secondary battery, comprising a current collector; an electrode active material layer formed on one surface of the current collector; a conductive layer formed on the electrode active material layer and comprising a conductive material and a binder; and a first porous supporting layer formed on the conductive layer. The sheet-form electrode for a secondary battery according to the present disclosure has supporting layers on at least one surfaces thereof to exhibit surprisingly improved flexibility and prevent the release of the electrode active material layer from a current collector even if intense external forces are applied to the electrode, thereby preventing the decrease of battery capacity and improving the cycle life characteristic of the battery..
| Shell activated sintering of core-shell particles|
A sintered structure and method for forming it are disclosed. The method includes obtaining core-shell particles having a core material and a shell material, forming the particles into a powder compact, and annealing the powder compact at an annealing temperature.
| Conductive polymer composition and conductive film using the same|
Disclosed herein is a conductive polymer composition capable of deteriorating water-absorption property and maintaining electrical conductivity by neutralizing polyethylenedioxythiophene/polystyrenesulfonate (pedot/pss) with dicyclohexylmethylamine which is lipid-soluble tertiary amine, and a conductive film using the same.. .
| Method for making glass substrate for display, glass substrate and display panel|
A method for manufacturing a glass substrate for a display includes a step of producing a glass substrate and a step of performing a surface treatment on one glass surface of major surfaces of the glass substrate to form surface unevenness. The surface treatment is performed such that protruded portions having a height of 1 nm or more from the surface roughness central plane of the surface unevenness are dispersedly provided on the glass surface after the surface treatment and the area ratio of the protruded portions with respect to the area of the glass surface is 0.5-10%.
| Gluten-free cooking products|
The present invention relates to a composition for a gluten-free cooking product, and specifically for all products traditionally containing gluten, added as such or by way of bread flour, the products including, in particular, bakery products. The invention likewise relates to totally gluten-free cooking and/or bread products produced using the composition..
| Cosmetic products for aged skin|
A cosmetic product having a ph value of 3.0 to 5.2 is disclosed that is specifically suitable for treating aged skin and irritations occurring there. The cosmetic product is preferably a barrier-stabilizing lotion or a barrier-stabilizing cream that contains a dry extract obtained from lady's mantle (alchemilla)..
| Homopolymer nanoparticles by self-emulsion polymerization reaction and preparation method thereof|
Disclosed herein is a preparation method of homopolymer nanoparticles without using a surfactant. The homopolymer nanoparticles prepared thereby are expected to be widely used not only as a template of a semiconductor metal oxide, a drug delivery system (dds), an electron transport layer (etl), and a seed having vertical structural shape, but also in a high precision field such as replacement of an organic device polystyrene bead film..
| Novel use of angiogenin|
The present invention provides a pharmaceutical composition for the prevention or treatment of glaucoma, wherein the pharmaceutical composition includes angiogenin or a fragment thereof as an active ingredient. Angiogenin or a fragment thereof according to the present invention activates aqueous humor outflow due to no generation increase, schlemm's canal expansion, and intercellular interval widening, thereby reducing intraocular pressure.