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Duc patents

      

This page is updated frequently with new Duc-related patent applications.




 Pcb based semiconductor package having integrated electrical functionality patent thumbnailPcb based semiconductor package having integrated electrical functionality
A semiconductor package includes a metal baseplate, a semiconductor die having a reference terminal attached to the baseplate and an rf terminal facing away from the baseplate, and a multilayer circuit board having a first side attached to the baseplate and a second side facing away from the baseplate. The multilayer circuit board includes a plurality of interleaved signal and ground layers.
Infineon Technologies Ag


 Microcontroller-based multifunctional electronic switch and lighting apparatus having the same patent thumbnailMicrocontroller-based multifunctional electronic switch and lighting apparatus having the same
A microcontroller-based multifunctional electronic switch uses a detection circuit design to convert external motion signals into message carrying sensing signals readable to the microcontroller. Based on the time length of sensing signals and the format of the sensing signals received in a preset instant period of time the microcontroller through the operation of its software program codes written in the otprom is able to recognize the working modes chosen by the external signal generating user and thereby selecting the appropriate loops of subroutine for execution.

 Electrically heatable pane with switch region patent thumbnailElectrically heatable pane with switch region
An electrically heatable pane with a switch region is presented. The pane has a transparent substrate, with at least one transparent electrically conductive layer that is, at least partially, arranged on a surface of the pane.
Saint-gobain Glass France


 Method and  controlling visitor call in home network system patent thumbnailMethod and controlling visitor call in home network system
Disclosed is a technology for a sensor network, machine to machine (m2m), machine type communication (mtc), and internet of things (iot). The present disclosure can be used for intelligent services (for example, services related to a smart home, smart building, smart city, smart car, connected car, health care, digital education, retail business, security, and safety) based on the technology.
Samsung Electronics Co., Ltd.


 Ultrasonic transducer patent thumbnailUltrasonic transducer
An ultrasonic transducer includes: a diaphragm pot that has a surrounding wall; a transducer element mounted in a diaphragm pot on a transducer section on an inner side of the diaphragm for generating the ultrasonic vibrations; a first damping element situated in the diaphragm pot on transducer element for damping the diaphragm; and a second damping element situated within the diaphragm pot in an edge section of the diaphragm around the transducer element for damping vibrations of the wall; the second damping element being connected with force locking, at least section by section, both to the edge section and to the inner side of the wall.. .
Robert Bosch Gmbh


 Sound transducer structure and  manufacturing a sound transducer structure patent thumbnailSound transducer structure and manufacturing a sound transducer structure
A sound transducer structure includes a membrane and a counter electrode. The membrane includes a first main surface in a sound transducing region made of a membrane material, and an edge region.
Infineon Technologies Ag


 Sound field reproduction device, sound field reproduction method, and program patent thumbnailSound field reproduction device, sound field reproduction method, and program
A feature amount extraction unit extracts a main sound source feature amount from a sound pickup signal obtained by picking up a sound from a main sound source. A main sound source separation unit separates the sound pickup signal obtained through the sound pickup with a microphone array that mainly picks up a sound from the main sound source into a main sound source component and an auxiliary sound source component using the main sound source feature amount.

 System with wireless earphones patent thumbnailSystem with wireless earphones
Apparatus comprises adapter and speaker system. Adapter is configured to plug into port of personal digital audio player.
Koss Corporation


 Semiconductor device and image processing method patent thumbnailSemiconductor device and image processing method
An image processing apparatus includes an image processing unit that calculates two types of image data from one image data and outputs the calculated image data, a data combination unit that combines the two type of data supplied from the image processing unit and outputs the combined data to one terminal, an output buffer that adjusts an output timing of the combined data according to an instruction supplied from bus arbitration means for arbitrating a bus, and a data distribution unit that outputs the combined data output from the output buffer to the bus in a form of the combined data, or distributes the combined data and outputs the distributed data to the bus according to an external combination distribution instruction.. .
Renesas Electronics Corporation


 Imaging device, imaging system, communication device, imaging method, and computer readable recording medium patent thumbnailImaging device, imaging system, communication device, imaging method, and computer readable recording medium
An imaging device includes an imaging unit configured to generate plural pieces of image data, a storing unit, a first communication control unit configured to sequentially transmit a newest one of the plural pieces of image data and identification information for identifying the newest one of the plural pieces of image data to plural communication devices and receive the identification information received by an operated communication device and elapsed time information from the operated communication device, and an image selection unit configured to select reproduction priority candidate image data, which is obtainable and reproducible by the operated communication device, from among the plural pieces of image data stored in the storing unit based on the elapsed time information and the identification information received.. .
Olympus Corporation


Information processing apparatus, synchronization correction method and computer program

An information processing apparatus is provided which includes a transmission unit for transmitting a query request for querying another device for a count value held by such other device, a reception unit for receiving a return of the count value from such other device, a correction unit for performing, at a predetermined period, correction processing for synchronizing sampling frequency with such other device based on the received count value, and a reproduction unit for reproducing content in synchronization with such other device based on the sampling frequency. The correction unit corrects by taking into account a round trip time between the transmission of the query request and the reception of the return and residual difference occurred at a previous correction time..
Sony Corporation

Optical module and optical transmitter using the same

An optical module has an optical modulator configured to perform phase modulation on each of divided light components of an input light and output at least two phase-modulated signal lights, a semiconductor optical amplifier configured to amplify the phased-modulated signal lights in a same polarization mode, and a polarization multiplexer configured to convert the amplified signal lights into two orthogonally polarized signal lights and multiplex the orthogonally polarized signal lights.. .
Fujitsu Optical Components Limited

Modular electronics

A computing device includes an integrated unit having a plurality of functional components, and an extremely high frequency (ehf) communication unit operatively coupled to the integrated unit. The ehf communication unit includes a transducer configured to transmit and receive ehf electromagnetic signals, and convert between electrical signals and electromagnetic signals.
Keyssa, Inc.

One-port surface elastic wave resonator on high permittivity substrate

A surface elastic wave resonator comprises a piezoelectric material to propagate the surface elastic waves and a transducer inserted between a pair of reflectors comprising combs of interdigitated electrodes and having a number nc of electrodes connected to a hot spot and an acoustic aperture w wherein the relative permittivity of the piezoelectric material is greater than about 15, a product of nc·w/fa for the transducer being greater than 100 μm·mhz−1, where fa is the antiresonance frequency of the resonator. A circuit comprises a load impedance and a resonator according to the invention and having an electrical response manifesting as a peak in the coefficient of reflection s11 at a frequency of a minimum value of the parameter s11 that is lower than −10 db, the antiresonance peak of the resonator being matched to the impedance of the load..
Senseor

Semiconductor devices

A semiconductor device includes a first transistor cell of a plurality of transistor cells of a vertical field effect transistor arrangement, and a second transistor cell of the plurality of transistor cells. The first transistor cell and the second transistor cell are electrically connected in parallel.
Infineon Technologies Ag

Semiconductor device, display module, and electronic device

A semiconductor device with a novel structure is provided. A semiconductor device with reduced power consumption is provided.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor devices and semiconductor systems including the same

A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output set signals.
Sk Hynix Inc.

Isolated output switching circuit

A semiconductor device includes an output switching device having an input node, an output node, and a control input node. The control input node enables an input voltage applied to the input node to be switched to the output node.
Texas Instruments Incorporated

Semiconductor device for radio frequency switch, radio frequency switch, and radio frequency module

Provided is a semiconductor device for radio frequency switch that includes an soi substrate and a gate electrode. The soi substrate includes a buried oxide film and a semiconductor layer on a carrier substrate.
Sony Corporation

Semiconductor device and semiconductor package using the same

A semiconductor device may include a comparator and a pad. The comparator may compare a voltage level of a reference node with a voltage level of a reference voltage to generate a code.
Sk Hynix Inc.

Semiconductor device

A semiconductor device includes a first pre-stress block suitable for generating a first load signal, which corresponds to an active signal during an active mode and/or to a high voltage level during a precharge mode, in response to a stress section signal; a first delay amount reflection block suitable for reflecting a first delay amount in the first load signal in response to one or more first delay amount control signals; and a first main stress block suitable for generating a word line driving control signal, which corresponds to the active signal during the active mode and the high voltage level during the precharge mode, in response to the stress section signal and the first load signal.. .
Sk Hynix Inc.

System and digital signal processing

The present invention provides for methods and systems for digitally processing an audio signal to reproduce high quality sounds on various materials. In various embodiments, a method comprises filtering the signal with a low shelf filter and/or high shelf filter, passing the signal through a first compressor that, filtering the signal again with a low shelf filter and/or high shelf filter, processing the signal with a graphic equalizer based on a selected material profile, passing the signal through a second compressor, and outputting the signal to a transducer..

Bias circuits and methods for depletion mode semiconductor devices

A radio frequency (rf) amplifier includes a depletion mode semiconductor device having a gate, a bias device and an inverting circuit. The depletion mode semiconductor device may be a hemt and/or a mesfet.
Cree, Inc.

Method and system for testing indirect bandgap semiconductor devices using luminescence imaging

Embodiments of methods and systems for identifying or determining spatially resolved properties in indirect bandgap semiconductor devices such as solar cells are described. In one embodiment, spatially resolved properties of an indirect bandgap semiconductor device are determined by externally exciting the indirect bandgap semiconductor device to cause the indirect bandgap semiconductor device to emit luminescence (110), capturing images of luminescence emitted from the indirect bandgap semiconductor device in response to the external excitation (120), and determining spatially resolved properties of the indirect bandgap semiconductor device based on a comparison of relative intensities of regions in one or more of the luminescence images (130)..
Bt Imaging Pty Ltd

Control system for an induction motor

Control systems and methods for starting an induction motor. The control system includes a plurality of wye switches, a plurality of delta switches, an ac power supply, and a soft-starter.
Kmt Waterjet System Inc.

Power conversion device and ac electric-vehicle drive system

To generate a pwm signal, as an on/off signal of a semiconductor switch that constitutes a power conversion main circuit, by comparing a modulation wave command based on an input voltage waveform command of the power conversion main circuit with a carrier wave having changes from a lower limit to an upper limit and from the upper limit to the lower limit for an integral number of times per one cycle of an ac power supply, where the carrier wave has characteristics such that one change time from the lower limit to the upper limit and then returning to the lower limit is constant, and a time ratio between a change time from the lower limit to the upper limit and a change time from the upper limit to the lower limit changes periodically.. .
Mitsubishi Electric Corporation

Semiconductor device

Reliability of a semiconductor device is improved. A third semiconductor chip on which a control circuit is formed, and a first semiconductor chip of a plurality of igbt chips are electrically connected via a high-side relay board.
Renesas Electronics Corporation

Semiconductor device

A higher-current device is implemented by increasing cross-sectional areas of terminals while securing solderability during mounting. The device makes securing of a creepage distance between terminals compatible with a reduction in package size.
Mitsubishi Electric Corporation

Power supply apparatus

In a power supply apparatus, one of a transformer and a first semiconductor device is stacked on the other thereof to constitute a stack assembly. The stack assembly, a second semiconductor device, and a choke coil are located on the major surface.
Denso Corporation

Communicating across galvanic isolation

Signal transmission circuitry comprises a conductive transmitting coil, a first power supply, a semiconductor switch to reversibly couple the transmitting coil to the first power supply, control circuitry to control the coupling of the transmitting coil to the first power supply by the semiconductor switch, a second power supply coupled to supply power to the control circuitry.. .
Power Integrations Switzerland Gmbh

Wearable device and terminal

Disclosed are a wearable device and a terminal. The wearable device includes: a wearable component and a power supply component fixed on the wearable component.
Boe Technology Group Co., Ltd.

Battery system reset systems and related methods

A battery reset system. Implementations may include: an embedded battery, a battery control circuit coupled with the embedded battery, a discharging field effect transistor (fet) coupled with the battery control circuit, and a charging fet coupled with the battery control circuit.
Semiconductor Components Industries, Llc

Semiconductor device and cell voltage equalization battery cell

The present disclosure provides a semiconductor device, including: a serial resistance element section including plural resistance elements connected in series, each resistance element provided so as to correspond to one of a plural battery cells connected in series; a comparison section that compares a voltage of a connection point of the plural battery cells connected in series to a voltage of a connection point between the resistance elements that correspond to the battery cells; and a measurement section that measures a voltage of one of the plural battery cells.. .
Lapis Semiconductor Co., Ltd.

Semiconductor integrated circuit

A semiconductor integrated circuit according to an embodiment includes: an output circuit configured to cause a current to flow out from an output terminal to a control target or cause a current to flow in from the control target via the output terminal, based on a control signal; a current source portion provided for the output circuit and configured to be capable of switching a current suppliable to the output terminal; and an adjustment circuit configured to switch a current that the current source portion is caused to generate, based on the control signal.. .
Kabushiki Kaisha Toshiba

Semiconductor laser device

A semiconductor laser device includes: a semiconductor laser array in which a plurality of active layers that emit laser lights with a divergence angle θs (>4°) in a slow axis direction are arranged; a first optical element that reflects first partial lights by a first reflecting surface and returns the first partial lights to the active layers; and a second optical element that reflects partial mode lights of second partial lights by a second reflecting surface and returns the partial mode lights to the active layers, the first reflecting surface forms an angle equal to or greater than 2° and less than (θs/2) with a plane perpendicular to an optical axis direction of the active layers, and the second reflecting surface forms an angle greater than (−θs/2) and equal to or less than −2° with the plane perpendicular to the optical axis direction of the active layers.. .
Hamamatsu Photonics K.k.

Quantum cascade laser

A quantum cascade laser is configured with a semiconductor substrate, and an active layer provided on a first surface of the substrate and having a cascade structure in the form of a multistage lamination of unit laminate structures each of which includes an emission layer and an injection layer. The active layer is configured to be capable of generating first pump light of a frequency ω1 and second pump light of a frequency ω2 by intersubband emission transitions of electrons, and to generate output light of a difference frequency ω by difference frequency generation from the first pump light and the second pump light.
Hamamatsu Photonics K.k.

Light emitting element

A light emitting element includes at least a first light reflecting layer 41 formed on a surface of a substrate 11, a laminated structural body 20 made of a first compound semiconductor layer 21, an active layer 23 and a second compound semiconductor layer 22 formed on the first light reflecting layer 41, and a second electrode 32 and a second light reflecting layer 42 formed on the second compound semiconductor layer 22, the laminated structural body 20 is configured from a plurality of laminated structural body units 20a, a light emitting element unit 10a is configured from each of the laminated structural body units 20a, and a resonator length in the light emitting element unit 10a is different in every light emitting element unit.. .
Sony Corporation

Optical module, optical apparatus, fabricating optical module

An optical module includes a bench part and a cap on the bench part. The bench part includes a bench, an electrode, a semiconductor optical device and a lens.
Sumitomo Electric Industries, Ltd.

Method for manufacturing optical member, manufacturing semiconductor laser device, and semiconductor laser device

A method for manufacturing an optical member includes providing a silicon substrate having a first main surface of a {110} plane, forming a mask pattern having an opening extending in a <100> direction on the first main surface of the silicon substrate, and forming a sloped surface of a {100} plane in the silicon substrate by wet etching the silicon substrate from a first main surface side using the mask pattern as a mask. A method for manufacturing a semiconductor laser device includes fixing the optical member formed by the method for manufacturing the optical member and a semiconductor laser element to a mounting board so that laser light emitted from the semiconductor laser element is irradiated to a reflective film of the optical member..
Nichia Corporation

Transmitarray unit cell for a reconfigurable antenna

Unit cell including a receive antenna, a transmit antenna, and including first and second radiation surfaces separated from each other by a separation area, a phase-shift circuit comprising switches, each having an on, respectively off, state, wherein the corresponding switch allows, respectively blocks, the flowing of a current between the first and second radiation surfaces; a ground plane; a first printed circuit board including a first surface provided with the receive antenna, and a second opposite surface provided with the ground plane; a wafer of a semiconductor material including a first surface provide with first and second radiation surfaces and wherein the switches are formed in the separation area, monolithically with the transmit antenna.. .
Commissariat À L'energie Atomique Et Aux Energies Alternatives

Organic photodetector and image sensor

An organic photodetector includes an anode and a cathode facing each other and an active layer between the anode and the cathode and including a p-type semiconductor and an n-type semiconductor, wherein an energy barrier between the anode or the cathode and the active layer is greater than or equal to about 1.3 ev, a difference between a homo energy level of the p-type semiconductor and a lumo energy level of the n-type semiconductor is greater than or equal to about 0.8 ev.. .
Seoul National University R&db Foundation

Method of doping an organic semiconuctor and doping composition

A method of forming a n-doped semiconductor layer wherein a film comprising an organic semiconductor and an n-dopant reagent is irradiated by light having a wavelength that is within an absorption range of the organic semiconductor, and wherein an absorption maximum wavelength of the n-dopant precursor is shorter than any peak wavelength of the light. The n-doped semiconductor layer may be an electron-injection layer of an organic light-emitting device..
Sumitomo Chemical Company Limited

High density resistive random access memory (rram)

A memory cell includes a substrate layer, with a plurality of silicided semiconductor fins stacked on the substrate layer and spaced apart from one another. A first metal liner layer is stacked on the plurality of silicided semiconductor fins and on the substrate layer.
Stmicroelectronics, Inc.

Polishing stop layer(s) for processing arrays of semiconductor elements

Described embodiments can be used in semiconductor manufacturing and employ materials with high and low polish rates to help determine a precise polish end point that is consistent throughout a wafer and that can cease polishing prior to damaging semiconductor elements. The height of the low polish rate material between the semiconductor elements is used as the polishing endpoint.
Spin Transfer Technologies, Inc.

Electronic device and fabricating the same

An electronic device may include a semiconductor memory. The semiconductor memory may include a substrate including a first region and a second region; buried gates formed in the first region and the second region, the buried gates in the second region having a different density distribution from the buried gates in the first region; first and second junction regions formed in the first and second regions, respectively, and having a same depth as each other; and a variable resistance element formed over the substrate and electrically connected to the buried gates in the first region.
Sk Hynix Inc.

Trilayer josephson junction structure with small air bridge and no interlevel dielectric for superconducting qubits

A technique relates to a trilayer josephson junction structure. A dielectric layer is on a base electrode layer that is on a substrate.
International Business Machines Corporation

Method to make a flexible thermoelectric generator device and related devices

A method is for making a thermoelectric generator device. The method may include forming bottom contacts on a first substrate, and forming a polymer layer over the first substrate with recesses therein, the recesses being over the bottom contacts.
Stmicroelectronics S.r.l.

Optoelectronic component and production thereof

A method of producing an optoelectronic component includes providing a lead frame subdivided by a separating region into first and second lead frame parts, carrying out etching in which at least one trench structure is produced on the upper side of the first lead frame, producing a molded body by molding a molding material around the lead frame such that 1) a cavity is formed and exposes a region of the upper side of the first lead frame part and a region of the upper side of the second lead frame part, and 2) the trench structure is provided on the upper side of the exposed region of the first lead frame part, and arranging the optoelectronic semiconductor chip on the upper side of the exposed region of the first lead frame part such that the trench structure is used as an alignment mark.. .
Osram Opto Semiconductors Gmbh

Light-emitting diode (led) package

A light-emitting diode (led) package includes a light-emitting structure including a first conductive-type semiconductor layer, an active layer, and a second conductive-type semiconductor layer; an isolating insulation layer; a first connection electrode portion and a second connection electrode portion electrically connected to the first conductive-type semiconductor layer and the second conductive-type semiconductor layer, respectively; a first electrode pad and a second electrode pad electrically connected to the first connection electrode portion and the second connection electrode portion, respectively; a first molding resin layer provided between the first electrode pad and the second electrode pad; a first pillar electrode and a second pillar electrode electrically connected to the first electrode pad and the second electrode pad, respectively; and a second molding resin layer provided on the first molding resin layer, the first electrode pad, and the second electrode pad, and between the first pillar electrode and the second pillar electrode.. .
Samsung Electronics Co., Ltd.

Light-emitting device

A light-emitting device includes a substrate including an upper surface; a light-emitting stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, wherein the light-emitting stack includes a first surface and a second surface opposite to the first surface toward to the upper surface; a plurality of depressions formed in the light-emitting stack and penetrating the second semiconductor layer, the active layer and a portion of the first semiconductor layer; an insulative layer covering the second surface of the light-emitting stack; a connector including a first portion and a second portion; and an electrode disposed at a side of the light-emitting stack and electrically connecting the connector, wherein the first portion of the connector is formed in the plurality of depressions, the second portion of the connector is between the insulative layer and the light-emitting stack.. .
Epistar Corporation

Optoelectronic device with light-emitting diodes and an improved radiation pattern

An optoelectronic device provided with a support including a face having at least one concave or convex portion, the amplitude of the sagitta of said portion being higher than 1/20th of the chord of the portion, and light-emitting diodes arranged on the portion, each light-emitting diode including a cylindrical, conical or frustoconical semiconductor element in contact with the portion, the amplitude of the sagitta of the contact surface between each semiconductor element and the portion being lower than or equal to 0.5 um.. .
Aledia

Uv light emitting diode and fabricating the same

Exemplary embodiments provide a uv light emitting diode and a method of fabricating the same. The method of fabricating a uv light emitting diode includes growing a first n-type semiconductor layer including algan, wherein growth of the first n-type semiconductor layer includes changing a growth pressure within a growth chamber and changing a flow rate of an n-type dopant source introduced into the growth chamber.
Seoul Viosys Co., Ltd.

Light emitting element and light emitting device

A light emitting element with a hexagonal planar shape, has: an n-side semiconductor layer; a p-side semiconductor layer provided on the n-side semiconductor layer; a plurality of holes that are provided to an area excluding three corners at mutually diagonal positions of the p-side semiconductor layer in plan view, and expose the n-side semiconductor layer; a first p-electrode provided in contact with the p-side semiconductor layer; second p-electrodes provided to three corners on the first p-electrode; and an n-electrode that is provided on the first p-electrode and is electrically connected to the n-side semiconductor layer through the plurality of holes.. .
Nichia Corporation

Resonant cavity strained iii-v photodetector and led on silicon substrate

An optoelectronic device that includes a germanium containing buffer layer atop a silicon containing substrate, and a first distributed bragg reflector stack of iii-v semiconductor material layers on the buffer layer. The optoelectronic device further includes an active layer of iii-v semiconductor material present on the first distributed bragg reflector stack, wherein a difference in lattice dimension between the active layer and the first distributed brag reflector stack induces a strain in the active layer.
International Business Machines Corporation

Method of selectively transferring semiconductor device

A semiconductor device comprises a substrate, a first semiconductor unit on the substrate, and an first adhesion structure between the substrate and the first semiconductor unit, and directly contacting the first semiconductor unit and the substrate, wherein the first adhesion structure comprises an adhesion layer and a sacrificial layer, and the adhesion layer and the sacrificial layer are made of different materials, and wherein an adhesion between the first semiconductor unit and the adhesion layer is different from that between the first semiconductor unit and the sacrificial layer.. .
Epistar Corporation

Solar cell and manufacturing the same

A solar cell and a method for manufacturing the solar cell are discussed. The method for manufacturing the solar cell includes applying an electrode paste on a semiconductor substrate and sintering the electrode paste using a light sintering device to form an electrode.
Lg Electronics Inc.

Semiconductor light-receiving device

A semiconductor light-receiving device includes: a semi-insulating substrate; and a buffer layer, a p-type contact layer, a light absorption layer, a p-type field alleviating layer, an avalanche multiplication layer, an n-type field alleviating layer and an n-type contact layer laminated in order on the semi-insulating substrate, wherein the buffer layer includes a superlattice obtained by alternately laminating an inp layer and an alxgayin1-x-yas layer (0.16≦x≦0.48, 0≦y≦0.31) and does not absorb light of a wavelength band absorbed by the light absorption layer.. .
Mitsubishi Electric Corporation

Layer system for thin-film solar cells

A layer system (1) for thin-film solar cells (100), comprising an absorber layer (4), which contains a chalcogenide compound semiconductor, and a buffer layer (5), which is arranged on the absorber layer (4), wherein the buffer layer (5) has a semiconductor material of the formula axinysz, where a is potassium (k) and/or cesium (cs), with 0.015≦x/(x+y+z)≦0.25 and 0.30≦y/(y+z)≦0.45.. .
Bengbu Design & Reserach Institute For Glass Industry

Solar cell and solar cell panel including the same

Disclosed is a solar cell including a semiconductor substrate, a first conductive area formed on one surface of the semiconductor substrate, a second conductive area formed on a remaining surface of the semiconductor substrate, a first electrode connected to the first conductive area, and a second electrode connected to the second conductive area. The second electrode includes a pad portion and an electrode portion that include different conductive materials as main components.
Lg Electronics Inc.

Solar cell

Disclosed is a solar cell including a semiconductor substrate, a conductive area including first and second conductive areas disposed on one surface of the semiconductor substrate, and an electrode including a first electrode connected to the first conductive area and a second electrode connected to the second conductive area. The electrode includes an adhesive layer disposed on the semiconductor substrate or the conductive area, an electrode layer disposed on the adhesive layer and including a metal as a main component, and a barrier layer disposed on the electrode layer and including a metal that is different from the metal of the electrode layer as a main component.
Lg Electronics Inc.

Sensor package with cooling feature

A sensor device includes a first substrate of semiconductor material having opposing first and second surfaces, photodetectors configured to receive light impinging on the first surface, and first contact pads each exposed at both the first and second surfaces and electrically coupled to at least one of the photodetectors. A second substrate comprises opposing first and second surfaces, electrical circuits, a second contact pads each disposed at the first surface of the second substrate and electrically coupled to at least one of the electrical circuits, and a plurality of cooling channels formed as first trenches extending into the second surface of the second substrate but not reaching the first surface of the second substrate.
Optiz, Inc.

Semiconductor device and imaging device

A semiconductor device includes a substrate having a major surface and a thin film transistor on the substrate. The thin film transistor includes an oxynitride semiconductor layer, first and second conductive layers, a first gate electrode and a first insulating layer.
Kabushiki Kaisha Toshiba

Semiconductor device

The semiconductor device includes a first transistor provided in a driver circuit portion and a second transistor provided in a pixel portion; the first transistor and the second transistor have different structures. In an oxide semiconductor film of each of the transistors, an impurity element is contained in regions which do not overlap with a gate electrode.
Semiconductor Energy Laboratory Co., Ltd.

Field-effect transistor, display element, image display device, and system

A field-effect transistor including: a gate electrode; a source electrode and a drain electrode; an active layer disposed to be adjacent to the source electrode and the drain electrode and including a n-type oxide semiconductor; and a gate insulating layer disposed between the gate electrode and the active layer, wherein the n-type oxide semiconductor undergoes substitutional doping with at least one dopant selected from divalent, trivalent, tetravalent, pentavalent, hexavalent, heptavalent, and octavalent cations, valence of the dopant is greater than valence of a metal ion constituting the n-type oxide semiconductor, provided that the dopant is excluded from the metal ion, and the source electrode and the drain electrode include a material selected from au, pt, and pd and alloys including at least any one of au, pt, and pd, in at least contact regions of the source electrode and the drain electrode with the active layer.. .
Ricoh Company, Ltd.

Thin-film transistor structure

The present invention provides a thin-film transistor structure, which comprises a substrate, a first metal layer, a first buffer layer, a semiconductor layer, a second metal layer, a second buffer layer, and a third metal layer. The second metal layer includes a gap region; the semiconductor layer includes a channel region.
Giantplus Technology Co., Ltd.

Semiconductor device and manufacturing the same

One object is to provide a semiconductor device including an oxide semiconductor, which has stable electric characteristics and high reliability. Another object is to manufacture a highly reliable semiconductor device in a high yield.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and display device including the semiconductor device

In a transistor including an oxide semiconductor, a change in electrical characteristics is suppressed and reliability is improved. The transistor includes an oxide semiconductor film over a first insulating film; a second insulating film over the oxide semiconductor film; a gate electrode over the second insulating film; a metal oxide film in contact with a side surface of the second insulating film; and a third insulating film over the oxide semiconductor film, the gate electrode, and the metal oxide film.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and manufacturing the same

It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer.
Semiconductor Energy Laboratory Co., Ltd.

Stacked oxide material, semiconductor device, and manufacturing the semiconductor device

One embodiment is a method for manufacturing a stacked oxide material, including the steps of forming an oxide component over a base component; forming a first oxide crystal component which grows from a surface toward an inside of the oxide component by heat treatment, and leaving an amorphous component just above a surface of the base component; and stacking a second oxide crystal component over the first oxide crystal component. In particular, the first oxide crystal component and the second oxide crystal component have common c-axes.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device

To provide a transistor with stable electrical characteristics, a transistor with a low off-state current, a transistor with a high on-state current, a semiconductor device including the transistor, or a durable semiconductor device. The semiconductor device includes a first transistor using silicon, an aluminum oxide film over the first transistor, and a second transistor using an oxide semiconductor over the aluminum oxide film.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device

A highly reliable semiconductor device including an oxide semiconductor is provided by preventing a change in its electrical characteristics. A semiconductor device which includes a first oxide semiconductor layer which is in contact with a source electrode layer and a drain electrode layer and a second oxide semiconductor layer which serves as a main current path (channel) of a transistor is provided.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and manufacturing the same

In an active matrix display device, electric characteristics of thin film transistors included in a circuit are important, and performance of the display device depends on the electric characteristics. Thus, by using an oxide semiconductor film including in, ga, and zn for an inverted staggered thin film transistor, variation in electric characteristics of the thin film transistor can be reduced.
Semiconductor Energy Laboratory Co., Ltd.

Metal oxide tft with improved source/drain contacts and reliability

A method including providing a substrate with a gate, a layer of gate insulator material adjacent the gate, and a layer of metal oxide semiconductor material positioned on the gate insulator opposite the gate, forming a selectively patterned etch stop passivation layer and heating at elevated temperature in an oxygen-containing or nitrogen-containing or inert ambience to selectively increase the carrier concentration in regions of the metal oxide semiconductor not covered by the etch stop layer, on which overlying and spaced apart source/drain metals are formed. Subsequently heating the transistor in an oxygen-containing or nitrogen-containing or inert ambience to further improve the source/drain contacts and adjust the threshold voltage to a desired level.

Semiconductor device, manufacturing method thereof, module, and electronic device

A semiconductor device which includes a transistor having a miniaturized structure is provided. A first insulator is provided over a stack in which a semiconductor, a first conductor, and a second conductor are stacked in this order.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and fabricating the same

A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region.
Samsung Electronics Co., Ltd.

Air gap contact formation for reducing parasitic capacitance

A functional gate structure is located on a surface of a semiconductor material portion and including a u-shaped gate dielectric portion and a gate conductor portion. A source region is located on one side of the functional gate structure, and a drain region is located on another side of the functional gate structure.
International Business Machines Corporation

Selective growth for high-aspect ratio metal fill

An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon.
Taiwan Semiconductor Manufacturing Company, Ltd.

High doped iii-v source/drain junctions for field effect transistors

A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a iii-v material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped iii-v material between doped iii-v materials, the doped iii-v materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.. .
Stmicroelectronics, Inc.

Semiconductor device including fin structures disposed over buffer structures and manufacturing method thereof

A semiconductor fet device includes a buffer structure and a fin structure. The buffer structure has a fin shape, is disposed over a substrate and extends along a first direction.
Taiwan Semiconductor Manufacturing Company

Semiconductor device including fin having condensed channel region

A finfet semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The semiconductor fin includes a channel region interposed between opposing source/drain regions.
International Business Machines Corporation

Method for detecting presence and location of defects in a substrate

A method for detecting the presence and location of defects over a substrate is disclosed. In an embodiment, the method may include: forming a semiconductor material in a plurality of openings in a reference wafer using an epitaxial growth process; performing one or more measurements on the reference wafer to obtain a baseline signal; forming a plurality of gate stacks and stressor regions in a plurality of substrates; after forming the plurality of gate stacks, forming the semiconductor material in a plurality of openings in a batch wafer; performing the one or more measurements on the batch wafer to obtain a batch signal; comparing the batch signal to the baseline signal; and determining whether a defect in present in the plurality of substrates based on the comparison..
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor devices and methods of manufacturing the same

A semiconductor device includes a gate structure on a substrate. The gate structure includes a first gate insulation pattern, a conductive pattern for controlling a threshold voltage, a first gate electrode and a first mask sequentially stacked.
Samsung Electronics Co., Ltd.

Semiconductor device and manufacturing the same

The present disclosure relates to a semiconductor device and method of manufacturing the same. The method of manufacturing the semiconductor device includes: providing a substrate, forming a patterned semiconductor layer on the substrate, forming a filter layer to cover the patterned semiconductor layer and forming a low concentration dopant buried layer within the semiconductor substrate, wherein one to forty percent of dopant are filtered out by the filter layer in the formation of the low concentration dopant buried layer..
Taiwan Semiconductor Manufacturing Company Ltd.

Semiconductor device and fabrication method thereof

The present disclosure provides a method for forming a semiconductor device, including: providing a semiconductor substrate; forming a well region and a drift region in the semiconductor substrate; and forming one or more counter-doped regions in the drift region, the one or more counter-doped regions being aligned along a direction vertical to the semiconductor substrate to divide the drift region into a plurality of parts. The semiconductor fabrication method also includes: forming a gate structure on the semiconductor substrate, the gate structure covering a portion of the well region and a portion of the drift region; and forming a source electrode in the well region on one side of the gate structure and a drain electrode in the drift region on another side of the gate structure..
Semiconductor Manufacturing International (shanghai) Corporation

Mos transistor structure with hump-free effect

A mos transistor structure is provided. The mos transistor structure includes a semiconductor substrate having an active area including a first edge and a second edge opposite thereto.
Mediatek Inc.

Semiconductor device and transistor cell having a diode region

A transistor cell includes a drift region, a source region, and a body region arranged between the source region and the drift region in a semiconductor body. A drain region is below the drift region.
Infineon Technologies Ag

Breakdown resistant hemt substrate and device

A compound semiconductor device structure having a main surface and a rear surface includes a silicon substrate including first and second substrate layers. The first substrate layer extends to the rear surface.
Infineon Technologies Austria Ag

Semiconductor substrate and semiconductor device

A semiconductor substrate including a substrate, a buffer layer having a nitride-based semiconductor containing carbon provided on the substrate, a high-resistance layer having a nitride-based semiconductor containing carbon provided on the buffer layer, and a channel layer having a nitride-based semiconductor provided on the high-resistance layer, the high-resistance layer including a first region having carbon concentration lower than that of the buffer layer, and a second region which is provided between the first region and the channel layer, and has the carbon concentration higher than the first region. As a result, it is possible to provide the semiconductor substrate which can reduce a leak current by enhancing crystallinity of the high-resistance layer while maintaining a high resistance of the high-resistance layer, and suppress occurrence of a decrease in electron mobility or current collapse in the channel layer by likewise enhancing crystallinity of the channel layer formed on the high-resistance layer..
Shin-etsu Handotai Co. Ltd.

Turn-off power semiconductor device with improved centering and fixing of a gate ring, and manufacturing the same

The present application relates to a turn-off power semiconductor device having a wafer with an active region and a termination region surrounding the active region, a rubber ring as an edge passivation for the wafer and a gate ring placed on a ring-shaped gate contact on the termination region for contacting the gate electrodes of a thyristor cell formed in the active region of the wafer. In the turn-off power semiconductor device, the outer circumferential surface of the gate ring is in contact with the rubber ring to define the inner border of the rubber ring.
Abb Schweiz Ag

Semiconductor device and semiconductor device manufacturing method

A semiconductor device and manufacturing method achieve miniaturization, prevent rise in threshold voltage and on-state voltage, and prevent decrease in breakdown resistance. N+-type emitter region and p++-type contact region are repeatedly alternately disposed in a first direction in which a trench extends in stripe form in a mesa portion sandwiched between trench gates.
Fuji Electric Co., Ltd.

Semiconductor device

The performance of a semiconductor device is improved. An emitter electrode is coupled to a p-type body region and an n+-type emitter region of a linear active cell region via a contact groove formed on an interlayer insulating film and is coupled to a p-type body region of a linear hole connector cell region via a contact groove.
Renesas Electronics Corporation

Semiconductor device and manufacturing semiconductor device

In a top-gate transistor in which an oxide semiconductor film, a gate insulating film, a gate electrode layer, and a silicon nitride film are stacked in this order and the oxide semiconductor film includes a channel formation region, nitrogen is added to regions of part of the oxide semiconductor film and the regions become low-resistance regions by forming a silicon nitride film over and in contact with the oxide semiconductor film. A source and drain electrode layers are in contact with the low-resistance regions.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and manufacturing the same

A first source electrode is formed in contact with a semiconductor layer; a first drain electrode is formed in contact with the semiconductor layer; a second source electrode which extends beyond an end portion of the first source electrode to be in contact with the semiconductor layer is formed; a second drain electrode which extends beyond an end portion of the first drain electrode to be in contact with the semiconductor layer is formed; a first sidewall is formed in contact with a side surface of the second source electrode and the semiconductor layer; a second sidewall is formed in contact with a side surface of the second drain electrode and the semiconductor layer; and a gate electrode is formed to overlap the first sidewall, the second sidewall, and the semiconductor layer with a gate insulating layer provided therebetween.. .
Semiconductor Energy Laboratory Co., Ltd.

Mosfet with ultra low drain leakage

A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region.
International Business Machines Corporation

Localized fin width scaling using a hydrogen anneal

Transistors including one or more semiconductor fins formed on a substrate. The one or more semiconductor fins are thinner in a channel region than in source and drain regions and have rounded corners.
Renesas Electronics Corporation

Air gap contact formation for reducing parasitic capacitance

A functional gate structure is located on a surface of a semiconductor material portion and including a u-shaped gate dielectric portion and a gate conductor portion. A source region is located on one side of the functional gate structure, and a drain region is located on another side of the functional gate structure.
International Business Machines Corporation

Method of forming finfet gate oxide

A semiconductor device includes a semiconductor fin, a first silicon nitride based layer, a lining oxide layer, a second silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top surface, a first side surface adjacent to the top surface, and a second side surface which is disposed under and adjacent to the first side surface.
Taiwan Semiconductor Manufacturing Co., Ltd.

Fabricating a strained fet

A fabricating method of a strained fet includes providing a semiconductive layer having a gate structure disposed thereon, wherein an epitaxial layer is embedded in the semiconductive layer aside the gate structure. Later, an element supply layer is formed to contact the epitaxial layer, wherein the element supply layer and the epitaxial layer have at least one identical element besides silicon.
United Microelectronics Corp.

High doped iii-v source/drain junctions for field effect transistors

A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a iii-v material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped iii-v material between doped iii-v materials, the doped iii-v materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.. .
Stmicroelectronics, Inc.

Semiconductor device manufacturing method and semiconductor device

Technique disclosed herein can suppress performance variation among semiconductor devices to be manufactured upon manufacturing each semiconductor device by forming diffusion layer by ion implantation to semiconductor substrate after etching. A semiconductor device includes a semiconductor substrate.
Toyota Jidosha Kabushiki Kaisha

Structure and formation semiconductor device structure with a dummy fin structure

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure over a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Pure boron for silicide contact

A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.. .
International Business Machines Corporation

Semiconductor device comprising a gradually increasing field dielectric layer and manufacturing a semiconductor device

A semiconductor device is provided that includes a transistor in a semiconductor body having a main surface. The transistor includes a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region.
Infineon Technologies Ag

Semiconductor device and fabricating method thereof

In accordance with various embodiments of the disclosed subject matter, a semiconductor device, and a fabricating method thereof are provided. In some embodiments, the semiconductor device comprises: a semiconductor substrate, wherein a plurality of fins are projected on a surface of the semiconductor substrate; and an insulating layer on side walls of the plurality of fins, wherein the insulating layer is located on the surface of the semiconductor substrate, a surface of the insulating layer is lower than top surfaces of the plurality of fins, and a thermal conductivity of the insulating layer is larger than a thermal conductivity of silicon oxide..
Semiconductor Manufacturing International (shanghai) Corporation

Method of manufacturing a semiconductor structure and semiconductor device

A method of manufacturing a structure in a semiconductor body comprises forming a first mask above a first surface of the semiconductor body. The first mask comprises an opening surrounding a first portion of the first mask, thereby separating the first portion and a second portion of the first mask.
Infineon Technologies Ag

Pure boron for silicide contact

A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.. .
International Business Machines Corporation

Method of obtaining planar semipolar gallium nitride surfaces

Methods and structures for forming flat, continuous, planar, epitaxial layers of semipolar iii-nitride materials on patterned sapphire substrates are described. Semipolar gan may be grown from inclined c-plane facets on a patterned sapphire substrate, and coalesced to form a continuous layer of semipolar iii-nitride semiconductor over the sapphire substrate.
Yale University

Semiconductor device

A semiconductor device of an embodiment includes a sic layer having a surface inclined with respect to a {000-1} face at an angle of 0° to 10° or a surface a normal line direction of which is inclined with respect to a <000-1> direction at an angle of 80° to 90°, a gate electrode, an insulating layer at least a part of which is provided between the surface and the gate electrode, and a region, at least apart of which is provided between the surface and the insulating layer, including a bond between carbon and carbon.. .
Kabushiki Kaisha Toshiba

Semiconductor device including fin having condensed channel region

A finfet semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The semiconductor fin includes a channel region interposed between opposing source/drain regions.
International Business Machines Corporation

Strained group iv channels

Disclosed herein is a semiconductor structure including: (i) a monocrystalline substrate having a top surface, (ii) a non-crystalline structure overlying the monocrystalline substrate and including an opening having a width smaller than 10 microns and exposing part of the top surface of the monocrystalline substrate. The semiconductor structure also includes (iii) a buffer structure having a bottom surface abutting the part and a top surface having less than 108 threading dislocations per cm2, the buffer structure being made of a material having a first lattice constant.
Imec Vzw

Semiconductor structure with a silicon germanium alloy fin and silicon germanium alloy pad structure

A semiconductor structure is provided that includes a silicon germanium alloy fin having a second germanium content located on a first portion of a substrate. The structure further includes a laterally graded silicon germanium alloy material portion located on a second portion of the substrate.
International Business Machines Corporation

Methods of forming replacement fins comprised of multiple layers of different semiconductor materials

One illustrative method disclosed herein includes, among other things, individually forming alternating layers of different semiconductor materials in a substrate fin cavity so as to form a multi-layer fin above a recessed substrate fin, wherein each of the layers of different semiconductor materials is formed to a final thickness that is less than a critical thickness of the layer of different semiconductor material being formed, recessing the layer of insulating material so as to expose at least a portion of the multi-layer fin above a recessed upper surface of the layer of insulating material and forming a gate structure around at least a portion of the of exposed the multi-layer fin.. .
Globalfoundries Inc.

Mosfet with ultra low drain leakage

A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region.
International Business Machines Corporation

Trench structure of semiconductor device and manufacturing method thereof

A trench structure of a semiconductor device includes a substrate, an isolation structure, and a liner layer. The substrate has a trench therein.
Taiwan Semiconductor Manufacturing Co., Ltd.

Leakage-free implantation-free etsoi transistors

A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (etsoi) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer.
International Business Machines Corporation

Method of forming a semiconductor device termination and structure therefor

At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer.. .
Semiconductor Components Industries, Llc

Semiconductor device

According to one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a first electrode. The third semiconductor layer is provided between the first semiconductor layer and the second semiconductor layer.
Kabushiki Kaisha Toshiba

Metal line connection for improved rram reliability, semiconductor arrangement comprising the same, and manufacture thereof

Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array.
Taiwan Semiconductor Manufacturing Co., Ltd.

Resistive switching random access memory with asymmetric source and drain

A resistive random access memory (rram) structure includes a resistive memory element formed on a semiconductor substrate and designed for data storage. The resistive element includes a resistive material layer.
Taiwan Semiconductor Manufacturing Company., Ltd.

Semiconductor device and manufacturing the same

A semiconductor device including: a first member including a selection transistor on a front surface side of a first substrate; and a second member including a resistance change device and a connection layer that comes in contact with the resistance change device, the connection layer being bonded to a back surface of the first member.. .
Sony Corporation

Semiconductor devices comprising magnetic memory cells and methods of fabrication

A magnetic cell core includes a seed region with a plurality of magnetic regions and a plurality of nonmagnetic regions thereover. The seed region provides a template that enables formation of an overlying nonmagnetic region with a microstructure that enables formation of an overlying free region with a desired crystal structure.
Micron Technology, Inc.

Injection molded microoptics

A wafer-scale apparatus and method is described for the automation of forming, aligning and attaching two-dimensional arrays of microoptic elements on semiconductor and other image display devices, backplanes, optoelectronic boards, and integrated optical systems. In an ordered fabrication sequence, a mold plate comprised of optically designed cavities is formed by reactive ion etching or alternative processes, optionally coated with a release material layer and filled with optically specified materials by an automated fluid-injection and defect-inspection subsystem.
International Business Machines Corporation

Semiconductor device

A mask includes a substrate, an effective pixel formation region and a reference pattern formation region. A pixel pattern for forming a pixel component that constitutes a pixel is arranged in the effective pixel formation region.
Renesas Electronics Corporation

Image sensor and manufacturing method therefor

Disclosed is an improvement of strength of adhesion between a photoconductive layer and a substrate. The image sensor includes a first electrode and a protruding pattern formed around the first electrode on the substrate, a protective film having an protruded surface formed on the protruding pattern, the photoconductive layer formed on the protective film, and a second electrode formed on the photoconductive layer..
Vatech Ewoo Holdings Co., Ltd.

Method of manufacturing solid-state image sensor

A method of manufacturing a solid-state image sensor, including a first transistor for transferring charges from a charge accumulation region to a first charge holding region and a second transistor for transferring charges from the first charge holding region to a second charge holding region, the method comprising forming, on the semiconductor substrate, a resist pattern having a opening on the first charge holding region, and injecting a impurity via the opening so as to make the first charge holding region be a buried type, wherein the impurity is injected such that an impurity region, which makes the first charge holding region be a buried type, is formed at a position away from an end of the gate electrode of the second transistor.. .
Canon Kabushiki Kaisha

Solid-state imaging device, manufacturing same, and electronic device

The present disclosure relates to a solid-state imaging device, a method for manufacturing the same, and an electronic device capable of increasing utilization efficiency of a substrate. The solid-state imaging device includes a first semiconductor substrate provided with a sensor circuit having a photoelectric conversion part, and a second semiconductor substrate and a third semiconductor substrate provided with respective circuits different from the sensor circuit.
Sony Corporation

Stacked image sensor and system including the same

A stacked image sensor includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a pixel array of rows and columns of pixels, a first column interlayer-connection unit extending in the row direction and disposed adjacent the top or bottom of the pixel array and column routing wires extending in a diagonal direction and connecting the pixel columns and the first column interlayer-connection unit.

Crosstalk improvement through p on n structure for image sensor

The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a semiconductor substrate having a first type of dopant; a semiconductor layer having a second type of dopant different from the first type of dopant and disposed on the semiconductor substrate; a photo-sensitive structure formed in the semiconductor layer; a multi-layer interconnect (mli) structure disposed on the semiconductor layer; a color filter disposed on the mli structure and disposed above the photo-sensitive structure; and a microlens disposed over the color filter and disposed above the photo-sensitive structure..
Taiwan Semiconductor Manufacturing Company., Ltd.

Photodiode array

A photodiode array has a plurality of photodetector channels formed on an n-type substrate having an n-type semiconductor layer, with a light to be detected being incident to the photodetector channels. The array comprises: a p−-type semiconductor layer on the n-type semiconductor layer of the substrate; resistors is provided to each of the photodetector channels and is connected to a signal conductor at one end thereof; and an n-type separating part between the plurality of photodetector channels.
Hamamatsu Photonics K.k.

Method of making a sensor package with cooling feature

A sensor device includes a first substrate of semiconductor material having opposing first and second surfaces, photodetectors configured to receive light impinging on the first surface, and first contact pads each exposed at both the first and second surfaces and electrically coupled to at least one of the photodetectors. A second substrate comprises opposing first and second surfaces, electrical circuits, a second contact pads each disposed at the first surface of the second substrate and electrically coupled to at least one of the electrical circuits, and a plurality of cooling channels formed as first trenches extending into the second surface of the second substrate but not reaching the first surface of the second substrate.
Optiz, Inc.

Integrated passive device on soi substrate

A method for fabricating dual-tier radio-frequency devices involves providing a silicon-on-insulator integrated circuit wafer having a semiconductor substrate and a plurality of integrated circuit devices formed thereon, at least partially removing the semiconductor substrate from a backside of the integrated circuit wafer, adding a low-loss replacement substrate to the backside of the integrated circuit wafer, and forming an integrated passive device over each of the plurality of integrated circuit devices after the adding of the low-loss replacement substrate to form a dual-tier wafer.. .
Skyworks Solutions, Inc.

Semiconductor device and manufacturing same

A semiconductor device (100) includes: a substrate (11); a first thin film transistor (10a) supported on the substrate (11), the first thin film transistor (10a) having a first active region (13c) which mainly contains a crystalline silicon; and a second thin film transistor (10b) being supported on the substrate (11), the second thin film transistor (10b) having a second active region (17c) which mainly contains an oxide semiconductor having a crystalline portion.. .
Sharp Kabushiki Kaisha

Method of manufacturing pixel structure and pixel structure

A method of manufacturing a pixel structure includes: forming a source, a drain and a first capacitor electrode; forming a semiconductor layer in contact with a portion of the source and a portion of the drain; forming a gate and a second capacitor electrode, and the second capacitor electrode substantially aligned with the first capacitor electrode; forming a gate insulating layer between the semiconductor layer, the source, the drain and the first capacitor electrode, and the gate and the second capacitor electrode; forming a passivation layer over the source, the drain, the first capacitor electrode, the semiconductor layer, the gate and the second capacitor electrode; and forming a pixel electrode over the passivation layer, and the pixel electrode substantially aligned with the first capacitor electrode.. .
E Ink Holdings Inc.

Semiconductor device

A semiconductor device includes a first transistor which includes a first gate electrode below its oxide semiconductor layer and a second gate electrode above its oxide semiconductor layer, and a second transistor which includes a first gate electrode above its oxide semiconductor layer and a second gate electrode below its oxide semiconductor layer and is provided so as to at least partly overlap with the first transistor. In the semiconductor device, a conductive film serving as the second gate electrode of the first transistor and the second gate electrode of the second transistor is shared between the first transistor and the second transistor.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and manufacturing the same

The number of photolithography steps used for manufacturing a transistor is reduced to less than the conventional one and a highly reliable semiconductor device is provided. The present invention relates to a semiconductor device including a circuit including a transistor having an oxide semiconductor layer over a first substrate and a second substrate fixed to the first substrate with a sealant.
Semiconductor Energy Laboratory Co., Ltd.

Memory device, semiconductor device, and electronic device

An object is to provide a memory device which does not need a complex manufacturing process and whose power consumption can be suppressed, and a semiconductor device including the memory device. A solution is to provide a capacitor which holds data and a switching element which controls storing and releasing charge in the capacitor in a memory element.
Semiconductor Energy Laboratory Co., Ltd.

Control circuit of thin film transistor

A control circuit of a thin film transistor, comprising: a substrate; a silicon nitride layer disposed on the substrate; a silicon dioxide layer disposed on the silicon nitride layer; a light shielding layer disposed inside the silicon nitride layer, which comprising a first light shielding region and a second light shielding region; at least one n type metal oxide semiconductor disposed on the silicon dioxide layer at a position corresponding to the first light shielding region; at least one p type metal oxide semiconductor disposed on the silicon dioxide layer at a position corresponding to the second light shielding region; each of the n type metal oxide semiconductor and the p type metal oxide semiconductor has a gate electrode layer, a first control signal received by voltage pulses of the gate electrode layer synchronized with a second control signal received by the light shielding layer in voltage variation.. .
Wuhan China Star Optoelectronics Technology Co., Ltd.

Semiconductor device, and display device and electronic device having the same

An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and display device

According to one embodiment, a semiconductor device includes first and second gate electrodes, a semiconductor layer, an output electrode, and an insulating layer. The semiconductor layer includes first source and drain areas, a first channel area facing the first gate electrode, second source and drain areas, and a second channel area facing the second gate electrode.
Japan Display Inc.

Vertical neuromorphic devices stacked structure and array of the structure

Provided is a vertical neuromorphic devices stacked strticture comprising a main gate which is formed on a substrate and has a vertical pillar shape, a main gate insulating layer stack formed on outer side surface of the main gate; a semiconductor region formed on outer side surface of the main gate insulating layer stack, a plurality of electrode layers formed on the side surface of the semiconductor retnon, a plurality of control gates formed on the side surface of the semiconductor region; and a plurality of control gate insulating layer stacks which are surrounding surfaces of the control gates and are formed between the control gate and the semiconductor region, and between the control gate and the electrode layer, and wherein the electrode layers and the control gates surrounded by the control gate insulating layer stack are stacked sequentially and alternately on the side surface of the semiconductor region.. .
Snu R&db Foundation

Vertical non-volatile semiconductor devices

Semiconductor device are provided including a stacked structure having gate electrodes and interlayer insulating layers alternately stacked on a substrate; channel holes extending perpendicular to the substrate through the stacked structure and including channel regions therein; and horizontal parts at lower portions of the stacked structure and including areas in which the channel regions are horizontally elongated from the channel holes. The horizontal parts surround respective channel holes and are connected to each other between at a least portion of the channel holes..

Nonvolatile semiconductor memory device

According to one embodiment, a nonvolatile semiconductor memory device includes a first structure having a first insulating layer, a semiconductor layer, and a second insulating layer stacked in this order in a first direction, the first structure extending in a second direction, memory cells provided on a surface of the semiconductor layer facing in a third direction, and connected in series in the second direction, and a third insulating layer contacting at least one of first and second end portions of the first structure in the second direction and not covering at least a part of an area between the first and second end portions. A lattice spacing of semiconductor atoms in the semiconductor layer in the second direction is larger than a lattice spacing of the semiconductor atoms in the semiconductor layer in the first direction..
Kabushiki Kaisha Toshiba

Semiconductor device and manufacturing the same

Provided herein is a semiconductor device including n stacked groups (where n is a natural number greater than or equal to two) sequentially stacked over a substrate, each stacked group including interlayer insulating films and conductive patterns alternately stacked, and n concave portions each having stepped sidewalls formed in the interlayer insulating films and the conductive patterns of the stacked groups, the n concave portions each having stepped sidewalls being aligned in a first direction.. .
Sk Hynix Inc.

Recess channel semiconductor non-volatile memory device and fabricating the same

A recess channel semiconductor non-volatile memory (nvm) device is disclosed. The recess channel mosfet devices by etching into the silicon substrate for the device channel have been applied to advanced dram process nodes.
Flashsilicon Incorporation

Semiconductor device having embedded strain-inducing pattern and forming the same

In a semiconductor device, a first active region has a first Σ-shape, and the second active region has a second Σ-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm..
Samsung Electronics Co., Ltd.

Three-dimensional semiconductor device with co-fabricated adjacent capacitor

A three-dimensional semiconductor device includes a semiconductor substrate, fin(s) coupled to the substrate and surrounded at a bottom portion thereof by isolation material, each fin including a source region, a drain region and a channel region therebetween, a first gate and spacers over a portion of each fin, and a second gate and spacers, the second gate encompassing a common end portion of each fin. The first gate and corresponding source and drain regions act as an access transistor, and the second gate and common end portion(s) of the fin(s) act as a storage capacitor, and a top surface of the second gate acts as a plate for the storage capacitor, when multiple cells are arranged in an array..
Globalfoundries Inc.

Semiconductor device structure and forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device, circuit board, and electronic device

A novel semiconductor device or memory device is provided. Alternatively, a semiconductor device or memory device in which storage capacity per unit area is large is provided.
Semiconductor Energy Laboratory Co., Ltd.

Memory device and semiconductor device

It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and electronic device

A semiconductor device or a memory device with low power consumption and a small area is provided. The semiconductor device includes a sense amplifier and a memory cell.
Semiconductor Energy Laboratory Co., Ltd.

Method for manufacturing semiconductor device and semiconductor device

A semiconductor device includes a first and second fin-shaped semiconductor layers on a substrate. A first insulating film is around the first and second fin-shaped layers.
Unisantis Electronics Singapore Pte. Ltd.

Semiconductor device and manufacturing the same

A semiconductor device includes a substrate including at least one metal-oxide-semiconductor field-effect transistor (mosfet) region defined by a device isolation layer and having an active pattern extending in a first direction on the mosfet region, a gate electrode intersecting the active pattern on the substrate and extending in a second direction intersecting the first direction, and a first gate separation pattern adjacent to the mosfet region when viewed from a plan view and dividing the gate electrode into segments spaced apart from each other in the second direction. The first gate separation pattern has a tensile strain when the mosfet region is a p-channel.
Samsung Electronics Co., Ltd.

Non-merged epitaxially grown mosfet devices

Semiconductor devices include multiple fins formed in trenches in an insulator layer. Each of the plurality of fins has a uniform crystal orientation and a fin cap in a source and drain region that extends vertically and laterally beyond the trench.
Renesas Electronics Corporation

Bulk fin formation with vertical fin sidewall profile

A semiconductor device, having a heterogeneous silicon stack, wherein the heterogeneous silicon stack comprises at least a base layer, a doped silicon layer, and an undoped silicon layer. The semiconductor device further includes a plurality of silicon fins atop a doped silicon oxide fin layer and an undoped silicon oxide fin layer, wherein the plurality of silicon fins have a uniform width along the height of the plurality of silicon fins, and wherein the plurality of silicon fins have a plurality of hard mask caps..
International Business Machines Corporation

Semiconductor device

A semiconductor device includes a plurality of active regions including channel regions extending in a first direction on a semiconductor substrate and source/drain regions connected to the channel regions, a plurality of gate electrodes extending in a second direction different from the first direction to intersect the channel regions, a plurality of conductive lines electrically connected to at least one of the source/drain regions and the plurality of gate electrodes through a plurality of vias, and a power line disposed between the semiconductor substrate and the plurality of conductive lines and configured to supply a power supply voltage.. .
Samsung Electronics Co., Ltd.

Semiconductor device and manufacturing method thereof

A semiconductor device includes an interlayer insulating film in which first contact holes and second contact holes are provided. Each of the second contact holes has a width narrower than a width of the corresponding first contact hole.
Toyota Jidosha Kabushiki Kaisha

Electrostatic discharge protection device and manufacturing the same

An esd protection device includes an insulative substrate, first and second discharge electrodes contacting the insulative substrate, the first and second discharge electrodes being spaced apart from and opposed to each other, first and second outer electrodes provided on an outside surface of the insulative substrate and electrically connected to the first and second discharge electrodes, respectively; and a discharge auxiliary electrode extending from the first discharge electrode to the second discharge electrode in a region where the first and second discharge electrodes oppose each other. The discharge auxiliary electrode includes semiconductor particles and metal particles having an average particle diameter of about 0.3 μm to about 1.5 μm, and a density of the metal particles at a random cross-section of the discharge auxiliary electrode is greater than or equal to about 20 particles/50 μm2..
Murata Manufacturing Co., Ltd.

Semiconductor wafer for integrated packages

An embodiment semiconductor wafer includes a bottom semiconductor layer having a first doping concentration, a middle semiconductor layer over the bottom semiconductor layer, and a top semiconductor layer over the middle semiconductor layer. The middle semiconductor layer has a second doping concentration greater than the first doping concentration, and the top semiconductor layer has a third doping concentration less than the second doping concentration.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor chip, optoelectronic device with a semiconductor chip, and producing a semiconductor chip

A semiconductor chip, an optoelectronic device including a semiconductor chip, and a method for producing a semiconductor chip are disclosed. In an embodiment the chip includes a semiconductor body with a first main surface and a second main surface arranged opposite to the first main surface, wherein the semiconductor body includes a p-doped sub-region, which forms part of the first main surface, and an n-doped sub-region, which forms part of the second main surface and a metallic contact element that extends from the first main surface to the second main surface and that is electrically isolated from one of the sub-regions..
Osram Opto Semiconductors Gmbh

Improved disc-shaped thyristor for a plurality of plated-through semiconductor components

A disk cell for pressure contacting a plurality of semiconductor components via a clamping device to generate a clamping force. The disk cell includes a housing comprising at least one metallic pressure plate, a first semiconductor component arranged in the housing, and a second semiconductor component arranged in the housing.
Siemens Aktiengesellschaft

Stack semiconductor package structure and manufacturing the same

A stack semiconductor package structure includes a substrate; a second chip comprising a plurality of conductive bumps formed on a surface thereof; and a first chip positioned on the second chip, wherein the second chip is electrically connected to the substrate through the plurality of conductive bumps in a flip-chip manner, and wherein the first chip is electrically connected to the second chip through a plurality of bonding wires.. .
Samsung Electronics Co., Ltd.

Semiconductor device and manufacturing semiconductor device

A semiconductor device includes a wiring substrate that includes a base having a first surface, a second surface, and a wiring, a semiconductor chip located on the first surface, an external connection terminal located on the second surface and electrically connected to the wiring, a sealing resin layer covering the semiconductor chip, a metal compound layer containing a metal nitride in contact with a surface of the sealing resin layer, and a conductive shield layer covering the sealing resin layer with the metal compound layer interposed between the conductive shield layer and the sealing resin layer. The wiring is exposed at a side surface of the wiring substrate, and is electrically connected to the conductive shield layer..
Kabushiki Kaisha Toshiba

Semiconductor device

A semiconductor device, includes: a first semiconductor chip including: a first substrate; a first via; a first rear surface-side pad connected to the first via; a first wiring layer; a first front surface-side pad formed on the first wiring layer; and an input circuit formed in the first substrate, an input signal wire connecting the first via, the first front surface-side pad, and an input terminal of the input circuit; and a second semiconductor chip including: a second substrate; a second wiring layer; a second front surface-side pad; and an output circuit formed in the second substrate, an output signal wire connecting the second front surface-side pad to an output terminal of the output circuit. The second semiconductor chip is stacked on a rear surface side of the first semiconductor chip, and the first rear surface-side pad and the second front surface-side pad are connected..
Fujitsu Limited

Package-on-package semiconductor assembly having bottom device confined by dielectric recess

A package-on-package semiconductor assembly is characterized by a semiconductor device positioned in a dielectric recess of a core base and surrounded by an array of metal posts. The recess in the core provides lateral displacement control between the device and the metal posts, and the minimal height of the metal posts needed for the vertical connection between two both opposite sides of the core base can be reduced by the amount equal to the depth of the recess.
Bridge Semiconductor Corporation

Face-to-face semiconductor assembly having semiconductor device in dielectric recess

A face-to-face semiconductor assembly is characterized by a semiconductor device positioned in a dielectric recess of a core base and surrounded by an array of metal posts. The recess in the core provides lateral displacement control between the device and the metal posts, and the minimal height of the metal posts needed for the vertical connection between both opposite sides of the core base can be reduced by the amount equal to the depth of the recess.
Bridge Semiconductor Corporation

Stack package and manufacturing the stack package

A stack package may include a substrate, and a first semiconductor chip mounted over the substrate. The stack package may include a support member disposed over the substrate and the first semiconductor chip, and spaced apart from the substrate and the first semiconductor chip.
Sk Hynix Inc.

Semiconductor package structure and forming the same

A semiconductor package structure is provided. The semiconductor package structure includes a first electronic component on a substrate.
Mediatek Inc.

Systems and methods for optimizing looping parameters and looping trajectories in the formation of wire loops

A method of forming a wire loop in connection with a semiconductor package is provided. The method includes the steps of: (1) providing package data related to the semiconductor package to a wire bonding machine; (2) providing at least one looping control value related to a desired wire loop to the wire bonding machine, the at least one looping control value including at least a loop height value related to the desired wire loop; (3) deriving looping parameters, using an algorithm, for forming the desired wire loop; (4) forming a first wire loop on the wire bonding machine using the looping parameters derived in step (3); (5) measuring actual looping control values of the first wire loop formed in step (4) corresponding to the at least one looping control value; and (6) comparing the actual looping control values measured in step (5) to the at least one looping control value provided in step (2)..
Kulicke And Soffa Industries, Inc.

Production semiconductor package

Provided is a production method for a semiconductor package making it possible to embed, in its irregularities, a thermosetting resin sheet satisfactorily. The method is a production method, for a semiconductor package, including the step of forming a sealed body by pressurizing a stacked body which includes: a chip-temporarily-fixed body comprising a supporting plate, a temporarily-fixing material stacked over the supporting plate, and a semiconductor chip fixed temporarily over the temporarily-fixing material; a thermosetting resin sheet arranged over the chip-temporarily-fixed body; and a separator having a tensile storage elastic modulus of 200 mpa or less at 90° c.
Nitto Denko Corporation

Bonding structure for semiconductor package and manufacturing the same

A method of manufacturing a bonding structure includes (a) providing a substrate, wherein the substrate includes a top surface and at least one bonding pad disposed adjacent to the top surface of the substrate, at least one bonding pad having a sloped surface with a first slope; (b) providing a semiconductor element, wherein the semiconductor element includes at least one pillar, and at least one pillar has a sidewall with a second slope, wherein the absolute value of the first slope is smaller than the absolute value of the second slope; and (c) bonding at least one pillar to a portion of the sloped surface of corresponding ones of the at least one bonding pad.. .
Advanced Semiconductor, Inc.

Semiconductor device and its manufacturing method

A semiconductor device includes an opening and a redistribution layer gutter which are formed integrally in a polyimide resin film of a single layer. A redistribution layer is formed in the polyimide resin film of a single layer.
Renesas Electronics Corporation

Printed interconnects for semiconductor packages

A method forming a packaged semiconductor device includes providing a first semiconductor die (first die) having bond pads thereon mounted face-up on a package substrate or on a die pad of a lead frame (substrate), wherein the substrate includes terminals or contact pads (substrate pads). A first dielectric layer is formed including printing a first dielectric precursor layer including a first ink having a first liquid carrier solvent extending from the substrate pads to the bond pads.
Texas Instruments Incorporated

Semiconductor device

Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main surface and a second main surface opposite to the first main surface and a wiring substrate over which the semiconductor chip is mounted such that the second main surface of the semiconductor chip faces a first main surface of the wiring substrate.
Renesas Electronics Corporation

Semiconductor device and a manufacturing a semiconductor device

According to various embodiments, a semiconductor device may include: at least one first contact pad on a front side of the semiconductor device; at least one second contact pad on the front side of the semiconductor device; a layer stack disposed at least partially over the at least one first contact pad, wherein the at least one second contact pad is at least partially free of the layer stack; wherein the layer stack includes at least an adhesion layer and a metallization layer; and wherein the metallization layer includes a metal alloy and wherein the adhesion layer is disposed between the metallization layer and the at least one first contact pad for adhering the metal alloy of the metallization layer to the at least one first contact pad.. .
Infineon Technologies Ag

Semiconductor devices and methods of forming thereof

In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions.
Infineon Technologies Ag

Packaging devices and methods of manufacture thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad, a second portion of the contact pad being exposed.
Taiwan Semiconductor Manufacturing Company, Ltd.

Fan-out packages and methods of forming same

An embodiment a device package includes a semiconductor die, a molding compound extending along sidewalls of the semiconductor die, and a planarizing polymer layer over the molding compound and extending along the sidewalls of the semiconductor die. The molding compound includes first fillers, and the planarizing polymer layer includes second fillers smaller than the first fillers.
Taiwan Semiconductor Manufacturing Company, Ltd.

Antenna in embedded wafer-level ball-grid array package

A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant.
Stats Chippac Pte. Ltd.

Battery protection package and process of making the same

The present invention discloses small-size battery protection packages and provides a process of fabricating small-size battery protection packages. A battery protection package includes a first common-drain metal oxide semiconductor field effect transistor (mosfet), a second common-drain mosfet, a power control integrated circuit (ic), a plurality of solder balls, a plurality of conductive bumps, and a packaging layer.
Alpha And Omega Semiconductor Incorporated

Multi-layer ground shield structure of interconnected elements

A multi-layer ground shield structure of interconnected elements is disclosed. The ground shield structure may include a first patterned layer of a ground shield structure, a second patterned layer of the ground shield structure, and a spacer between the first patterned layer and the second patterned layer.
Qualcomm Incorporated

Structures and methods for semiconductor packaging

A semiconductor package including a lead frame having a die pad and a plurality of leads arranged along at least a portion of a periphery of the semiconductor package, a semiconductor die secured to the die pad, wherein at least a portion of the semiconductor die extends beyond a periphery of the die pad, and a molding material encapsulating the semiconductor die and at least a portion of the die pad.. .
Everspin Technologies, Inc.

Resin-encapsulated semiconductor device and its manufacturing method

A resin-encapsulated semiconductor device having a semiconductor chip which is prevented from being damaged. The resin-encapsulated semiconductor device (100) comprises a semiconductor chip (1) including a silicon substrate, a die pad (10) to which the semiconductor chip (1) is secured through a first solder layer (2), a resin-encapsulating layer (30) encapsulating the semiconductor chip (1), and lead terminals (21) electrically connected to the semiconductor chip (1) and including inner lead portion (21b) covered with the resin-encapsulating layer (30).
Rohm Co., Ltd.

Semiconductor leadframes and packages with solder dams and related methods

A semiconductor package includes a leadframe having a first island and second island each having an upper surface corresponding with an upper surface of the leadframe. One or more tie bars couple the first island with the second island.
Semiconductor Components Industries, Llc

Connection patterns for high-density device packaging

Connection patterns for device packaging allow high density circuitry dies to be assembled into packages of manufacturable size. The connection patterns may be patterns for solder ball arrays or other types of connection mechanisms under a semiconductor package.
Broadcom Corporation

Semiconductor device and a manufacturing the same

To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an lcd driver, a mark is formed in an alignment mark formation region over a semiconductor substrate.
Renesas Electronics Corporation

Interconnection structure

An interconnection structure fabrication method is provided. The method includes providing a substrate; forming a conductive film with a first thickness and having a first lattice structure and a first grain size, wherein the first thickness is greater than the first grain size; and performing an annealing process to change the first lattice structure of the conductive film to a second lattice structure and to change the first grain size to a second grain size.
Semiconductor Manufacturing International (shanghai) Corporation

Three-dimensional integrated circuit laminate, and interlayer filler for three-dimensional integrated circuit laminate

A three-dimensional integrated circuit laminate, which comprises a semiconductor substrate laminate having at least two semiconductor substrates each having a semiconductor device layer formed thereon laminated, and has a first interlayer filler layer containing a resin (a) and an organic filler (b) and having a thermal conductivity of at least 0.8 w/(m·k) between the semiconductor substrate.. .

Semiconductor devices

A semiconductor device includes a substrate with lower structures, an insulation layer covering the lower structures on the substrate, a contact hole through the insulation layer partially exposing the substrate, and a contact structure contacting the substrate through the contact hole, the contact structure including a barrier pattern having an upper barrier on an upper portion of a sidewall of the contact hole, and a lower barrier filling a lower portion of the contact hole, and a conductive contact pattern filling an upper portion of the contact hole defined by the upper barrier and the lower barrier.. .
Samsung Electronics Co., Ltd.

Contact structure for high aspect ratio and fabricating the same

A method of fabricating semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. A fist inter layer dielectric layer is deposited on the gate structures.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device

Object is to provide a semiconductor device with fewer malfunctions. The semiconductor device has a semiconductor chip having a first-signal-output circuit operating at a first-power-supply voltage, a second-signal-output circuit operating at a second power supply voltage, and a plurality of bump electrodes; and a wiring board including a first main surface facing the main surface of the semiconductor chip, a second main surface opposite to the first main surface with a wiring layer therebetween, first external terminals on the first main surface, and second ones on the second main surface; the former being mounted on the latter to couple the bump electrodes to the first external terminals.
Renesas Electronics Corporation

Semiconductor device and fabricating the same

A semiconductor device is provided. The semiconductor device includes a stack structure comprising insulating patterns and electrode structures alternately stacked on a substrate, and a vertical channel structure vertically penetrating the stack structure.

Semiconductor device having a porous low-k structure

The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device having a multi-level interconnection structure

A semiconductor device includes a semiconductor substrate, and a multi-level interconnection structure that is provided on the semiconductor substrate and that has a plurality of interconnection layers stacked one on another. Each interconnection layer includes a real interconnection and a dummy interconnection covered with an insulative film.
Rohm Co., Ltd.

High speed, high density, low power die interconnect system

A system for interconnecting at least two die each die having a plurality of conducting layers and dielectric layers disposed upon a substrate which may include active and passive elements. In one embodiment there is at least one interconnect coupling at least one conducting layer on a side of one die to at least one conducting layer on a side of the other die.
Gula Consulting Limited Liability Company

Semiconductor package and manufacturing the same

A semiconductor package includes a first substrate, a pattern layer disposed on the first substrate, a first chip member disposed on a surface of the first substrate, lead frames mounted on the first substrate surrounding the first chip member, and a first encapsulation layer disposed on the first substrate, encapsulating the first chip member and the lead frame, wherein upper end portions of the lead frame and the first encapsulation layer are removed, and lead frame columns are exposed through the first encapsulation layer.. .
Samsung Electro-mechanics Co., Ltd.

Semiconductor device and manufacturing the same

A semiconductor device includes a wiring substrate including wiring layers, a semiconductor chip including electrode pads and mounted on the wiring substrate, and a first capacitor including a first electrode and a second electrode, and mounted on the wiring substrate. The wiring layers include a first wiring layer including a first terminal pad electrically connected with the first electrode of the first capacitor and a second terminal pad electrically connected with the second electrode of the first capacitor; and a second wiring layer on an inner side by one layer from the first wiring layer of the wiring substrate and including a first conductor pattern having a larger area than each of the first terminal pad and the second terminal pad.
Renesas Electronics Corporation

Packaging substrate

A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads..
Siliconware Precision Industries Co., Ltd.

Printed wiring board, semiconductor package, and manufacturing printed wiring board

A printed wiring board includes a buildup wiring layer including resin insulation layers and conductive layers such that the conductive layers are laminated on the resin insulation layers, respectively, first pads formed in a center portion of a first surface of the buildup wiring layer and positioned to connect an electronic component, second pads formed on a periphery portion of the first surface of the buildup wiring layer and positioned to connect an external wiring board, a solder layer including a plating material and formed on the first pads such that the solder layer is formed on each of the first pads, conductive posts including a plating material and formed on the second pads, respectively, and a seed layer including first seed layer portions formed between the first pads and the solder layer and second seed layer portions formed between the second pads and the conductive posts.. .
Ibiden Co., Ltd.

Semiconductor device

To improve the reliability of a semiconductor device. A chip mounting portion tab5 is arranged to be shifted to the +x direction side.
Renesas Electronics Corporation

Semiconductor device

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive.
Renesas Semiconductor Package & Test Solutions Co., Ltd.

Semiconductor devices and methods of manufacturing the same, and semiconductor packages including the semiconductor devices

A semiconductor device includes a substrate having a die region and a scribe region surrounding the die region, a plurality of via structures penetrating through the substrate in the die region, a portion of the via structure being exposed over a surface of the substrate, and a protection layer pattern structure provided on the surface of the substrate surrounding a sidewall of the exposed portion of the via structure and having a protruding portion covering at least a portion of the scribe region adjacent to the via structure.. .
Samsung Electronics Co., Ltd.

Power amplifier die having multiple amplifiers

An apparatus, a semiconductor package including the apparatus and a method are disclosed. The apparatus includes a semiconductor die having second stages of power amplifier disposed over a module substrate.
Avago Technologies General Ip (singapore) Pte. Ltd.

Interconnect arrangement with stress-reducing structure and fabricating the same

A semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a gate structure embedded in a first dielectric layer over a substrate and a second dielectric layer formed over the first dielectric layer.
Taiwan Semiconductor Manufacturing Co., Ltd.

Method of making a plurality of semiconductor devices

A method of making a plurality of semiconductor devices comprising a chip scale packages. The method includes providing a semiconductor wafer having a major surface and a backside.
Nxp B.v.

Semiconductor device

A semiconductor device includes: a semiconductor element which includes semiconductor substrate, an insulating film formed on a front surface of the semiconductor substrate and having an opening, and an electrode formed in the opening on the front surface of the semiconductor substrate; and a first protective film disposed to cover the semiconductor element. The insulating film has a thickness of not less than 1/500 of a thickness of the semiconductor substrate and not more than 4 μm.
Mitsubishi Electric Corporation

Semiconductor device and forming small z semiconductor package

A semiconductor device has a plurality of first semiconductor die. A plurality of first bumps is formed over the first semiconductor die.
Semtech Corporation

Semiconductor package

Provided is a semiconductor package including a substrate; at least one semiconductor chip mounted on the substrate; a molding element, which is arranged on the substrate and encapsulates the at least one semiconductor chip; and a lattice element, which is arranged inside the molding element, where the lattice element includes a body having a plurality of openings.. .
Samsung Electronics Co., Ltd.

Vertical cmos structure and method

A method for forming stacked, complementary transistors is disclosed. Selective deposition techniques are used to form a column having a lower portion that includes one type of semiconductor (e.g.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device and fabricating the same

A semiconductor device includes: a fin-shaped structure on a substrate, in which the fin-shaped structure includes a top portion and a bottom portion; a doped layer around the bottom portion of the fin-shaped structure; a first liner on the doped layer, and a second liner on the top portion and the bottom portion of the fin-shaped structure. Preferably, the first liner and the second liner are made of different material..
United Microelectronics Corp.

Integrated circuit having strained fins on bulk substrate and method to fabricate same

A method includes forming a set of fins composed of a first semiconductor material. The method further heats the set of fins to condense the fins and cause growth of a layer of oxide on vertical sidewalls thereof, masking a first sub-set of the fins, forming a plurality of voids in the oxide by removing a second sub-set of fins, where each void has a three-dimensional shape and dimensions that correspond to a three dimensional shape and dimensions of a corresponding removed fin from the second sub-set, and epitaxially growing in the voids a third sub-set of fins.
International Business Machines Corporation

Manufacturing semiconductor structure

The present invention provides a method for forming a semiconductor structure, comprising: firstly, a substrate is provided, having a first fin structure and a second fin structure disposed thereon, next, a first isolation region is formed between the first fin structure and the second fin structure, a second isolation region is formed opposite the first fin structure from the first isolation region, and at least an epitaxial layer is formed on the side of the first fin structure and the second fin structure, wherein the epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region, in addition, the epitaxial layer has a stepped-shaped sidewall profile.. .
United Microelectronics Corp.

Semiconductor device and formation thereof

A semiconductor device and methods of formation are provided. The semiconductor device includes a first active region having a first active region height and an active channel region having an active channel region height over a fin.
Taiwan Semiconductor Manufacturing Company Limited

Method for fabricating fin of finfet of semiconductor device

A method for fabricating a semiconductor device on a wafer includes: patterning a plurality of fins on the wafer; forming a shallow-trench isolation region to surround the plurality of fins; and etching the sti region to form the plurality of fins having a fin height such that the semiconductor device has a desired power consumption. The plurality of fins corresponds to a plurality of finfets of the semiconductor device respectively..
Taiwan Semiconductor Manufacturing Company Ltd.

Method for forming a semiconductor device and a semiconductor device

A method of forming a semiconductor device and a semiconductor device are provided. The method includes providing a wafer stack including a carrier wafer comprising graphite and a device wafer comprising a wide band-gap semiconductor material and having a first side and a second side opposite the first side, the second side being attached to the carrier wafer, defining device regions of the wafer stack, partly removing the carrier wafer so that openings are formed in the carrier wafer arranged within respective device regions and that the device wafer is supported by a residual of the carrier wafer; and further processing the device wafer while the device wafer remains supported by the residual of the carrier wafer..
Infineon Technologies Ag

Method for forming a wafer structure, a forming a semiconductor device and a wafer structure

A method of producing a semiconductor device and a wafer structure are provided. The method includes attaching a donor wafer comprising silicon carbide to a carrier wafer comprising graphite, splitting the donor wafer along an internal delamination layer so that a split layer comprising silicon carbide and attached to the carrier wafer is formed, removing the carrier wafer above an inner portion of the split layer while leaving a residual portion of the carrier wafer attached to the split layer to form a partially supported wafer, and further processing the partially supported wafer..
Infineon Technologies Ag

Semiconductor device and method comprising redistribution layers

A method of making a semiconductor package can include placing a single layer dielectric film on a temporary carrier substrate. A plurality of semiconductor die can be placed directly on the first surface of the single layer dielectric film.
Deca Technologies Inc.

Method of forming interconnects for semiconductor devices

A method of forming interconnects for semiconductor devices includes forming a lower insulating layer and a lower interconnect on a semiconductor substrate, forming an insulating pattern layer on the lower interconnect through self-assembly, forming an interlayer insulating layer and a trench mask on the insulating pattern layer, forming a preparatory via hole allowing the insulating pattern layer to be exposed by removing a portion of the interlayer insulating layer, forming a trench by etching the interlayer insulating layer using the trench mask, forming a via hole allowing the lower interconnect to be exposed by selectively etching the insulating pattern layer within the preparatory via hole, and filling the trench and the via hole with an conductive material.. .
Samsung Electronics Co., Ltd.

Semiconductor device having groove-shaped via-hole

The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66.
Fujitsu Semiconductor Limited

Methods of fabricating a semiconductor device

A method of fabricating a semiconductor device, the method including forming at least one interconnection structure that includes a metal interconnection and a first insulating pattern sequentially stacked on a substrate; forming barrier patterns covering sidewalls of the interconnection structure; forming second insulating patterns at sides of the interconnection structure, the second insulating patterns being spaced apart from the interconnection structure with the barrier patterns interposed therebetween; forming a via hole in the first insulating pattern by etching a portion of the first insulating pattern, the via hole exposing a top surface of the metal interconnection and sidewalls of the barrier patterns; and forming a via in the via hole.. .
Samsung Electronics Co., Ltd.

Multilayer structure including diffusion barrier layer and device including the multilayer structure

A multilayer structure includes a first material layer, a second material layer, and a diffusion barrier layer. The second material layer is connected to the first material layer.
Samsung Electronics Co., Ltd.





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