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Duc patents

      

This page is updated frequently with new Duc-related patent applications.




 System and  clamping press pack high power semiconductor patent thumbnailSystem and clamping press pack high power semiconductor
Systems and methods for setting, assembling, and/or monitoring deflection (and thus load) in a load beam of a clamping system for a press pack high power semiconductor. The clamping system includes an assembly of a heat sink, a clamp component, and a semiconductor package.
Lwe, Inc.


 High voltage power module patent thumbnailHigh voltage power module
A power module includes a number of sub-modules connected via removable jumpers. The removable jumpers allow the connections between one or more power semiconductor die in the sub-modules to be reconfigured, such that when the removable jumpers are provided, the power module has a first function and when the removable jumpers are removed, the power module has a second function.
Cree, Inc.


 Circuit arrangement and  operating semiconductor light sources patent thumbnailCircuit arrangement and operating semiconductor light sources
Various embodiment may relate to a circuit arrangement for operating a load, including an input for inputting a mains input ac voltage, a power converter circuit, a converter circuit which converts the mains input ac voltage rectified by the power converter circuit into an output voltage, a control circuit for controlling the converter circuit, and a linear regulating circuit which sets a predetermined load current at the load. The load current is a direct current with a uniform current intensity.
Osram Gmbh


 Hearing device with vibration sensitive transducer patent thumbnailHearing device with vibration sensitive transducer
A hearing device, such as a hearing aid, having a vibration sensitive transducer being adapted to detect vibrations being generated by a human voice, and a digital signal processor for processing signals from the vibration sensitive transducer in order to identify a predetermined human voice vibration signal being related to the voice of the user of the hearing device, and control the hearing device in accordance therewith. The vibration sensitive transducer is secured directly to a shell so that vibrations are detected via a skull of the user of the hearing device.
Sonion Nederland B.v.


 Image display device patent thumbnailImage display device
Provided is an image display device, including: a light flux emitter (10) which emits a plurality of parallel light fluxes; and a controller (20) which periodically subjects, to two-dimensional deflection, the parallel light fluxes emitted from the light flux emitter (10), based on a scan signal, and controls, synchronously with the scan signal, light intensity of the plurality of parallel light fluxes based on a light intensity control signal based on image information input thereto, in which: the light flux emitter (10) has at least a plurality of photonic crystal semiconductor lasers (11a) which emit the plurality of parallel light fluxes and are two-dimensionally arranged; and the parallel light fluxes emitted from the plurality of photonic crystal semiconductor lasers (11a) are controlled in light intensity, based on the light intensity control signal.. .
Olympus Corporation


 Television with built-in dual membrane resonance sound box patent thumbnailTelevision with built-in dual membrane resonance sound box
Left and right sides in the television are provided symmetrically with independent sound boxes. Each sound box comprises a box body and a loudspeaker group, a front passive radiator and a rear passive radiator that are located in the box body.
Shen Zhen Neusound Co., Ltd


 Method and system for displaying object, and  providing the object patent thumbnailMethod and system for displaying object, and providing the object
A first device for displaying an object related to content reproduced by a second device is provided. The first device including a sensor which senses an exit of the first device from a service zone of the second device during reproduction of the content by the second device; a communication device which requests a management server for an object related to the content, the object including link information for receiving information about the content reproduced by the second device at a point of time when the sensor senses the exit, and for receiving the object related to the content from the management server; and a controller which controls a display to display the received object related to the content on a predetermined screen of the first device..
Samsung Electronics Co., Ltd.


 Balancing sense amplifier for ethernet transceiver patent thumbnailBalancing sense amplifier for ethernet transceiver
An ethernet or other communications module can amplify and reinforce a signal received from a non-local source without requiring a transformer or other magnetic component. A semiconductor integrated difference amplifier circuit can be used to amplify and reinforce a differential mode component of the received signal, while also attenuating a common mode component of the received signal.

 Methods for overdriving a base current of an emitter switched bipolar junction transistor and corresponding circuits patent thumbnailMethods for overdriving a base current of an emitter switched bipolar junction transistor and corresponding circuits
An emitter switched bipolar transistor circuit includes a bipolar junction transistor (bjt) having a collector coupled to an output terminal, a metal oxide semiconductor field effect transistor (mosfet) coupled to an emitter of the bjt, a bias voltage supply coupled to the base of the bjt, a buffer coupled to the base of the bjt, and a comparator. The comparator includes a first input coupled to the collector of the bjt, a second input coupled to a voltage reference, and an output coupled to an input of the buffer.
Astec International Limited


 Semiconductor device and driving system patent thumbnailSemiconductor device and driving system
A semiconductor device includes a high side driver, in which the high side driver has an output transistor configured to supply a power voltage to an output terminal based on a driving voltage applied to a gate electrode of the output transistor; a short circuit transistor configured to couple the gate electrode of the output transistor with the output terminal; and a switch transistor connected in series between the gate electrode of the output transistor and a drain electrode of the short circuit transistor. The switch transistor is controlled by a back gate of the switch transistor..
Renesas Electronics Corporation


Semiconductor device and manufacturing semiconductor device

A semiconductor device includes a plurality of semiconductor switching elements disposed on a single semiconductor substrate comprising a semiconductor having a bandgap that is wider than that of silicon; and a plurality of electrode pads that are disposed in a predetermined planar layout on a front surface of the semiconductor substrate, the plurality of electrode pads each being electrically connected to the plurality of semiconductor switching elements. A plurality of terminal pins to externally carry out voltage of the electrode pads is bonded through a plated film to all of the plurality of electrode pads by solder..
Fuji Electric Co., Ltd.

Buffer circuit, semiconductor integrated circuit, and system including the buffer circuit

According to an embodiment, a buffer circuit may be provided. The buffer circuit may include a first buffer configured to receive first and second external clock signals and generate a first pre-clock signal based on falling timings of the first and second external clock signals.
Sk Hynix Inc.

Semiconductor integrated circuit device

A semiconductor integrated circuit device includes a chip main circuit, a damper and a passive component. The chip main circuit is coupled to a power source and performs a predetermined function.
Mediatek Inc.

Method and data filtering, and constructing data filter

A method for data filtering includes segmenting a to-be-detected vector to obtain k to-be-detected sub-vectors, respectively performing an inner product operation on the k to-be-detected sub-vectors and corresponding detection vectors among preset k detection vectors to obtain k first operation results, determining a first operation result whose value is the maximum among the k first operation results and obtaining an identifier of a detection vector corresponding to the first operation result, where a detection vector is in a one-to-one correspondence to an identifier, and mapping the to-be-detected vector to a preset data filter according to the obtained identifier of the detection vector corresponding to the first operation result whose value is the maximum, and determining, using the data filter, whether to filter out the to-be-detected vector.. .
Huawei Technologies Co., Ltd.

Low frequency equalization for loudspeaker system

A method of optimizing the low frequency audio response emanating from a pair of low frequency transducers housed within a cabinet. The low frequency transducers are electrically connected to a power amplifier and source of audio content.

Coupling assembly and radiofrequency amplification system having the same

Rf amplification system includes a power cavity and a coupling loop operably positioned within the power cavity between an inner conductor and an outer conductor. The coupling loop includes a secured segment that is coupled to the grounding deck and a movable segment that is coupled to the secured segment.
General Electric Company

Solar panel accelerated regeneration and/or prevention of defects in solar panels

The present invention provides a solar panel installation, comprising at least one solar panel comprising photovoltaic cells, and a translucent plate on the upper side, wherein the translucent plate is provided with an electrically conductive layer that is provided in order to have an electric potential applied to it and which is electrically isolated from the photovoltaic cells, such that an electric potential applied to the electrically conductive layer will be uniformly distributed over the upper side of the at least one solar panel. In addition, the invention provides a method for applying the electrically conductive layer and for regenerating and/or preventing defects in the at least one solar panel..
Futech

Electrostatic induction power generator

A board arrangement structure includes a housing, a first board fastened to the housing, a second board arranged in parallel enabling, relative movement with respect to the first board, an electrically charged film, a counter electrode, and an output part outputting electric power generated between the electrically charged film and the counter electrode, at least one of the electrically charged film and the counter electrode being arranged at a first facing surface of the first board and the other being arranged at a second facing surface of the second board facing the first facing surface, and the first facing surface of the first board being, fastened to a reference mounting surface provided at the housing.. .
Citizen Holdings Co., Ltd.

Driver assembly

A driver assembly comprises several semiconductor switches that are arranged in a plane so that distances between adjacent semiconductor switches in the plane are equally large, and so that each semiconductor switch has the same number of adjacent semiconductor switches.. .
Lemförder Electronic Gmbh

Power module

A power module includes a substrate, a first sub-module, a second sub-module and a circuit board. The semiconductor switches and the diodes of the first sub-module and the second sub-module are embedded within insulation layers.
Delta Electronics Int'l (singapore) Pte Ltd

Enhanced fault reporting in voltage regulators

An electronic system, voltage regulator, controller and fault reporting method and circuit for a voltage regulator or other type of dc-dc converter are disclosed. For example, a fault reporting circuit is disclosed.
Intersil Americas Llc

Induction motor and manufacture

An electric motor includes a main winding coupled to a first line terminal, and first and second boost windings coupled in series to the main winding. A high-speed lead wire is coupled to a first tap between the main winding and the first boost winding, a medium-speed lead wire is coupled to a second tap between the first boost winding and the second boost winding, and a low-speed lead wire is coupled to a third tap after the second boost winding.
Regal Beloit America, Inc.

Semiconductor light-emitting device with an axis of symmetry

The present invention proposes a semiconductor light-emitting device having an axis of symmetry, the device including two or more laser diodes, each of the laser diodes has an axis of symmetry, wherein the laser diodes are arranged in series on the axis of symmetry of the light-emitting device in such a way that their axes of symmetry coincide, wherein faces of the laser diodes are connected so that they are in electric and mechanic contact and form a bar of the laser diodes, a directional pattern of radiation thereof has an axis of symmetry coinciding with the axis of symmetry of the light-emitting device. The proposed light-emitting device can be used in laser lamps of white light for exciting phosphors since it provides a high degree of flare of cylindrical surfaces..

Semiconductor light emitting element

A semiconductor light-emitting element includes a multilayer body including a first end surface and a second end surface which are opposed to each other, wherein a first semiconductor layer, a light emitting layer, and a second semiconductor layer are stacked; a pair of recesses that are formed on the second semiconductor layer, separated from the second end surface, and separated from each other in the direction parallel to the first and second end surfaces; a ridge portion that is a protrusion between the pair of recesses and extends along the direction perpendicular to the first and second end surfaces; a band-shaped electrode disposed on the ridge portion; and a light guide layer formed on the second semiconductor layer between the ridge portion and the second end surface and guides light from the light emitting layer.. .
Stanley Electric Co., Ltd.

Laser device

A laser device has a plurality of semiconductor lasers, a driving device that supplies a driving electric current to the semiconductor laser, a trigger generation circuit that sends a trigger signal to the driving device in order to output the driving electric current, and a wave-combining device that wave-combines laser light emitted from the semiconductor lasers at the combined-wave end, and at least any one of a signal transmitting time, an electric current transmitting time and a light transmitting time is adjusted so as to be the time set respectively for transmitting paths; wherein the signal transmitting time in which the trigger signal transmits over the signal path, the electric current transmitting time in which the laser light transmits over the electric current path, a light transmitting time in which the laser light transmits over the optical path.. .
Shimadzu Corporation

Press-fit pin for semiconductor packages and related methods

A press-fit pin for a semiconductor package includes a shaft terminating in a head. A pair of arms extends away from a center of the head.
Semiconductor Components Industries, Llc

Insulative fixing plate damaged when overheating as well as a plug and a socket using that insulative fixing plate

An insulative fixing plate damaged when overheating limits two conductive elements from contacting with each other, forming a closed path, when overheating, opening two conductive elements by an elastic force to form an open circuit. Each conductive element has a groove concaved in from an edge, and the groove has a groove width.

Terminal connection structure and semiconductor apparatus

A terminal connection structure includes a male terminal; and a female terminal having an elasticity and configured to have the male terminal fitted therein such that the female terminal sandwiches the male terminal from opposite sides; wherein the male includes a base material, a first primary coat coated on the base material, a second primary coat coated on the first primary coat, and a surface layer coated on the second primary coat, and the first primary coat and the second primary coat have different hardnesses.. .
Denso Corporation

Sensor and manufacturing the sensor

A sensor according to the present disclosure may include a substrate, an antenna pattern formed to transmit and receive a wireless signal to and from an external device, a sensing unit configured to be driven when the wireless signal is received through the antenna pattern and to generate a signal when in contact with a sensing target material, and a circuit line electrically connected between the antenna pattern and the sensing unit, wherein the antenna pattern and the circuit line are formed of a same material and on a same layer. A fabrication method of a sensor according to the present disclosure may include printing a conductive layer having an antenna pattern, a sensing electrode and a circuit line on one surface of a substrate with a single layer, heat-drying the conductive layer, printing, on a single layer, a circuit insulating layer that covers part of the circuit line and an antenna insulating layer that covers part of the antenna pattern, curing the insulating layer, printing an antenna bridge on the antenna insulating layer, heat-drying the antenna bridge, and bonding a device electrically connected to the circuit line to the substrate..
Lg Electronics Inc.

3d-microstrip branchline coupler

The disclosure is directed to semiconductor structures and, more particularly, to a three dimensional microstrip branchline coupler and methods of manufacture. The structure includes a plurality of through silicon vias and conductive lines electrically connected to a first end and a second end of respective ones of the plurality of through silicon vias.
International Business Machines Corporation

Electrode for photobattery

An electrode comprising an electrode material of the same type as electrode materials used in li-ion batteries and a dye is provided. The electrode may further comprise a semiconductor material.
Hydro-quÉbec

Cables and wires having conductive elements formed from improved aluminum-zirconium alloys

A conductive element of a cable or a wire is formed of an improved aluminum-zirconium alloy. The aluminum-zirconium alloy further includes an inoculant.
Nanoal, Llc

Battery separator for extending the cycle life of a battery

A battery separator for extending the cycle life of a battery has a separator and a conductive layer. The conductive layer is disposed upon the separator.
Daramic Llc

Semiconductor device and manufacturing method thereof

As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film..
Semiconductor Energy Laboratory Co., Ltd.

Vertical-type organic light-emitting transistors with reduced leakage current and fabricating the same

A vertical-type organic light-emitting transistor for reducing the off-state leakage current to improve the current and on-off ratio includes a gate electrode, a lower semiconductor layer disposed on the gate electrode, a source electrode disposed on the lower semiconductor layer, and a source insulation film disposed on the source electrode and covering top and sides of the source electrode, wherein the lower semiconductor layer is configured such that an electric charge is injected into the lower semiconductor layer from the source electrode when voltage is applied to the gate electrode.. .
Seoul National University R&db Foundation

Organic electroluminescent device, preparing the same and display panel

An organic electroluminescent device, a method for preparing an organic electroluminescent device, and a display panel are disclosed. The organic electroluminescent device comprises a conductive layer formed by transparent magnetic conductive particles which are mixed in the sealing layer and stacked on a surface of the first transparent electrode layer.
Boe Technology Group Co., Ltd.

Simple approach for preparing post-treatment-free solution processed non-stoichiometric niox nanoparticles as conductive hole transport materials

High-quality non-stoichiometric niox nanoparticles are synthesized by a facile chemical precipitation method. The niox film can function as an effective p-type semiconductor or hole transport layer (htl) without any post-treatments, while offering wide temperature applicability from room-temperature to 150° c.
The University Of Hong Kong

Dual-gate chemical field effect transistor sensor

A chemical sensing field effect transistor device is disclosed. The device can include a control gate structure interfacing a control side of a semiconductor channel region, a source region, and a drain region.
University Of Utah Research Foundation

Semiconducting compounds and related devices

Wherein x is a chalcogen; and one or more linear conjugated moieties and/or one or more cyclic conjugated moieties other than the moieties represented by formula (i). The present compounds can be used to prepare thin film semiconductor components which can be incorporated into various electronic, optical, and optoelectronic devices..

Film and organic semiconductor device containing the film

A film comprising a polymer compound and a low molecular weight compound having carrier transportability, wherein the content of the low molecular weight compound is 5 to 40 parts by mass with respect to 100 parts by mass of the sum of the polymer compound and the low molecular weight compound, the diffraction intensity a specified by the following measuring method a is 3 to 50, and the intensity ratio (a/b) of the diffraction intensity a specified by the following measuring method a to the diffraction intensity b specified by the following measuring method b is 30 or less: (measuring method a) the diffraction intensity a is the maximum diffraction intensity in a range of scattering vector of 1 nm−1 to 5 nm−1 in a profile obtained by an out-of plane measuring method using a film x-ray diffraction method; (measuring method b) the diffraction intensity b is the maximum diffraction intensity in a range of scattering vector of 10 nm−1 to 21 nm−1 in a profile obtained by an in-plane measuring method using a film x-ray diffraction method.. .
Sumitomo Chemical Company, Limited

Semiconductor memory device and manufacturing same

According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction, a plurality of stacked films respectively provided between the first interconnects and the second interconnects, each of the plurality of stacked films including a variable resistance film, a first inter-layer insulating film provided in a first region between the stacked films, and a second inter-layer insulating film provided in a second region having a wider width than the first region. The second inter-layer insulating film includes a plurality of protrusions configured to support one portion of the plurality of second interconnects on the second region.
Kabushiki Kaisha Toshiba

Methods of forming an interconnection line and methods of fabricating a magnetic memory device using the same

Provided herein are methods of fabricating a magnetic memory device including forming magnetic tunnel junction patterns on a substrate, forming an interlayered insulating layer on the substrate to cover the magnetic tunnel junction patterns, forming a conductive layer on the interlayered insulating layer, patterning the conductive layer to form interconnection patterns electrically connected to the magnetic tunnel junction patterns, and performing a cleaning process on the interconnection patterns. The cleaning process is performed using a gas mixture of a first gas and a second gas.
Samsung Electronics Co., Ltd.

Semiconductor memory device

A semiconductor memory device includes free magnetic pattern on a substrate, a reference magnetic pattern on the free magnetic pattern, the reference magnetic pattern including a first pinned pattern, a second pinned pattern, and an exchange coupling pattern between the first and second pinned patterns, a tunnel barrier pattern between the reference magnetic pattern and the free magnetic pattern, a polarization enhancement magnetic pattern between the tunnel barrier pattern and the first pinned pattern, and an intervening pattern between the polarization enhancement magnetic pattern and the first pinned pattern, wherein the first pinned pattern includes first ferromagnetic patterns and anti-ferromagnetic exchange coupling patterns which are alternately stacked.. .

Semiconductor memory device

A semiconductor memory device includes a selection transistor on a semiconductor substrate, a lower contact plug connected to a drain region of the selection transistor, and a magnetic tunnel junction pattern on the lower contact plug, the magnetic tunnel junction pattern including a bottom electrode in contact with the lower contact plug, the bottom electrode being an amorphous tantalum nitride layer, a top electrode on the bottom electrode, first and second magnetic layers between the top and bottom electrodes, and a tunnel barrier layer between the first and second magnetic layers.. .

Thermoelectric nanocomposite and process of producing the same

A thermoelectric nanocomposite is provided. The thermoelectric nanocomposite includes: a matrix having n-type semiconductor characteristics and comprising mg, si, al, and bi components, and a nanoinclusion comprising bi and mg components.
Industry-academic Cooperation Foundation, Yonsei University

Semiconductor package and manufacturing method thereof

A semiconductor package includes a substrate, at lest one support, a cover, and a plate. The substrate has at least one light sensor or thermal sensor, a first surface, and a second surface opposite to the first surface.
Xintec Inc.

Semiconductor device, semiconductor device package, and lightning apparatus

A semiconductor device includes a light emitting structure, and an interconnection bump including an under bump metallurgy (ubm) layer disposed on an electrode of at least one of the first and second conductivity-type semiconductor layers, and having a first surface disposed opposite to a surface of the electrode and a second surface extending from an edge of the first surface to be connected to the electrode, an intermetallic compound (imc) disposed. On the first surface of the ubm layer, a solder bump bonded to the ubm layer with the imc therebetween, and a barrier layer disposed on the second surface of the ubm layer and substantially preventing the solder bump from being diffused into the second surface of the ubm layer..
Samsung Electronics Co., Ltd.

Light emitting element package and manufacturing the same

There is provided a light emitting element package including: a light emitting laminate having a structure in which semiconductor layers are laminated and having a first main surface and a second main surface opposing the first main surface; a terminal unit disposed on an electrode disposed on the second main surface; a molded unit disposed on the second main surface of the light emitting laminate and allowing a portion of the terminal unit to be exposed; and a wavelength conversion unit disposed on the first main surface of the light emitting laminate.. .
Samsung Electronics Co., Ltd.

Semiconductor light emitting element, production method therefor, led element and electron-beam-pumped light source device

This method for producing a semiconductor light emitting element includes: a step (a) of preparing a growth substrate; a step (b) of growing a first layer made of alx1gay1in1-x1-y1n (0<x1≦1, 0≦y1≦1) on an upper layer of the growth substrate in a <0001> direction; a step (c) of forming a groove portion extending along a <11-20> direction of the first layer with respect to the first layer with such a depth that a surface of the growth substrate is not exposed; a step (d) of growing a second layer made of alx2gay2in1-x2-y2n (0<x2≦1, 0≦y2≦1) on an upper layer of the first layer with at least a {1-101} plane serving as a crystal growth plane; and a step (e) of growing an active layer on an upper layer of the second layer.. .
Ushio Denki Kabushiki Kaisha

Light emitting element

The light emitting element is provided to comprise: a first conductive type semiconductor layer; a mesa; a current blocking layer; a transparent electrode; a first electrode pad and a first electrode extension; a second electrode pad and a second electrode extension; and an insulation layer partially located on the lower portion of the first electrode, wherein the mesa includes at least one groove formed on a side thereof, the first conductive type semiconductor layer is partially exposed through the groove, the insulation layer includes an opening through which the exposed first conductive type semiconductor layer is at least partially exposed, the first electrode extension includes extension contact portions in contact with the first conductive type semiconductor layer through an opening, and the second electrode extension includes an end with a width different from the average width of the second electrode extension.. .
Seoul Viosys Co., Ltd.

Semiconductor structure with stress-reducing buffer structure

A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 gpa and 2.0 gpa.
Sensor Electronic Technology, Inc.

Composition of, and forming, a semiconductor structure with multiple insulator coatings

A semiconductor structure includes a nanocrystalline core comprising a first semiconductor material, and at least one nanocrystalline shell comprising a second, different, semiconductor material that at least partially surrounds the nanocrystalline core. The nanocrystalline core and the nanocrystalline shell(s) form a quantum dot.
Pacific Light Technologies Corp.

Method for manufacturing compound semiconductor solar cell

A solar cell includes a metal layer and a chalcopyrite compound semiconductor layer in this order on a polyimide film. A manufacturing method according to the present invention includes the following steps in the order: cast applying a polyimide precursor solution onto a support base containing an alkali metal; imidizing the polyimide precursor by heating to form a stacked body including a polyimide film on the support base; forming a metal layer on the polyimide film of the stacked body; and forming a chalcopyrite compound semiconductor layer on the metal layer..
Kaneka Corporation

Indentation approaches for foil-based metallization of solar cells

Indentation approaches for foil-based metallization of solar cells, and the resulting solar cells, are described. For example, a method of fabricating a solar cell includes forming a plurality of alternating n-type and p-type semiconductor regions in or above a substrate.

Multijunction solar cell assembly for space applications

A multijunction solar cell assembly and its method of manufacture including first and second discrete and different semiconductor body subassemblies which are electrically interconnected to form a five junction solar cell, each semiconductor body subassembly including first, second, third and fourth lattice matched subcells; wherein the average band gap of all four cells in each subassembly is greater than 1.44 ev.. .
Solaero Technologies Corp.

Multijunction metamorphic solar cell assembly for space applications

A multijunction solar cell and its method of manufacture including interconnected first and second discrete semiconductor regions disposed adjacent and parallel to each other in a single semiconductor body, including first top subcell, second (and possibly third) lattice matched middle subcells; a graded interlayer adjacent to the last middle solar subcell; and a bottom solar subcell adjacent to said graded interlayer being lattice mismatched with respect to the last middle solar subcell; wherein the interconnected regions form at least a four junction solar cell by a series connection being formed between the bottom solar subcell in the first semiconductor region and the bottom solar subcell in the second semiconductor region.. .
Solaero Technologies Corp.

Lattice matched multijunction solar cell assemblies for space applications

A multijunction solar cell and its method of manufacture including interconnected first and second discrete semiconductor regions disposed adjacent and parallel to each other in a single semiconductor body, including first top subcell, second (and possibly third) lattice matched middle subcells; and a bottom solar subcell adjacent to said last middle subcell and lattice matched thereto; wherein the interconnected regions form at least a four junction solar cell by a series connection being formed between the bottom solar subcell in the first semiconductor region and the bottom solar subcell in the second semiconductor region.. .
Solaero Technologies Corp.

Quantum dot image sensor

A photodetector includes a first doped region disposed in a semiconductor material and a second doped region disposed in the semiconductor material. The second doped region is electrically coupled to the first doped region, and the second doped region is of an opposite majority charge carrier type as the first doped region.
Omnivision Technologies, Inc.

Mixed oxides and sulphides of bismuth and silver for photovoltaic use

The invention relates to a material comprising at least one compound having formula bi1−xmxag1−y−εm′yos1−zm″z, the methods for producing said material and the use thereof as a semiconductor, such as for photovoltaic or photochemical use and, in particular, for supplying a photocurrent. The invention further relates to photovoltaic devices using said compounds..
Le Centre National De La Recherche Scientifique

Method of manufacturing photovoltaic device having ultra-shallow junction layer

The present invention relates to a method of manufacturing a photovoltaic device having an ultra-shallow junction layer. In the method, a crystalline silicon substrate is cleaned and a first doped semiconductor layer with 1.12 ev bandgap and 5˜80 nm of thickness is grown on the crystalline silicon substrate by high density plasma electron cyclotron resonance cvd in a preparation condition of a temperature of the crystalline silicon substrate ranging from 50° c.
National Central University

Semiconductor device and forming semiconductor die with active region responsive to external stimulus

A semiconductor device has a first semiconductor die including an active region formed on a surface of the first semiconductor die. The active region of the first semiconductor die can include a sensor.
Stats Chippac Pte. Ltd.

Semiconductor device and zener diode having branch impurity regions

A semiconductor device includes a substrate, a well region of a first-conductivity type disposed in the substrate, a first impurity region of a second-conductivity type and having a plurality of branches disposed in the well region, a second impurity region of the first-conductivity type and having a plurality of branches, and a third impurity region of the first-conductivity type disposed in the well region. The second-conductivity type is opposite to the first-conductivity type.
Macronix International Co., Ltd.

Semiconductor device

Provided is a device with improved reverse-recovery immunity of a diode element. The device includes: a first conductivity-type drift layer; a second conductivity-type anode region provided in an upper portion of the drift layer; a second conductivity-type extraction region in contact with and surrounding the anode region; and a second conductivity-type field limiting ring region surrounding and separated from the extraction region at the upper portion of the drift layer, wherein the extraction region has a greater depth than the anode region and the field limiting ring region..
Fuji Electric Co., Ltd.

Thin film transistor, thin film transistor manufacturing method and array substrate

The present disclosure relates to a thin film transistor, a method for manufacturing a thin film transistor and an array substrate. The thin film transistor comprises an active layer, a source and a drain, the source comprising a source first conductive layer and a source first buffer layer, the drain comprising a drain first conductive layer and a drain first buffer layer; at least a part of an upper surface of the source first buffer layer and at least a part of an upper surface of the drain first buffer layer being in contact with a lower surface of the active layer, at least a part of a side wall of the source first conductive layer and at least a part of a side wall of the drain first conductive layer being in contact with the active layer, the side wall of the source first conductive layer and the side wall of the drain first conductive layer in contact with the active layer being formed with an oxide layer.
Boe Technology Group Co., Ltd.

Array substrate and fabricating the same

A method of manufacturing an array substrate is discussed. The method includes forming a gate line on a substrate including a pixel region, forming a gate electrode on the substrate and connected to the gate line, and forming a gate insulating layer on the gate line and the gate electrode.
Lg Display Co., Ltd.

Thin film transistor array panel and manufacturing the same

One or more exemplary embodiments disclose a thin film transistor array panel and a manufacturing method thereof including a substrate, a gate line on the substrate, the gate line including a gate electrode, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, and the semiconductor layer including an oxide semiconductor, a data wire layer above the semiconductor layer, the data wire layer including a data line, a source electrode coupled to the data line, and a drain electrode facing the source electrode, and a metal phosphorus oxide layer configured to cover the source electrode and the drain electrode.. .
Samsung Display Co., Ltd.

Semiconductor device and manufacturing the same

An object is to provide a structure of a transistor which has a channel formation region formed using an oxide semiconductor and a positive threshold voltage value, which enables a so-called normally-on switching element. The transistor includes an oxide semiconductor stack in which at least a first oxide semiconductor layer and a second oxide semiconductor layer with different energy gaps are stacked and a region containing oxygen in excess of its stoichiometric composition ratio is provided..
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor structure

A semiconductor structure is provided. The semiconductor structure includes a substrate, a diffusion region, a first oxide layer, a second oxide layer and a polysilicon layer.
United Microelectronics Corp.

Semiconductor device and manufacturing the same

A semiconductor device includes a transistor including a gate electrode over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, and an oxide insulating film covering the transistor. The multilayer film includes an oxide semiconductor film and an oxide film containing in or ga, the oxide insulating film contains more oxygen than that in the stoichiometric composition, and in the transistor, by a bias-temperature stress test, threshold voltage does not change or the amount of the change in a positive direction or a negative direction is less than or equal to 1.0 v, preferably less than or equal to 0.5 v..
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and manufacturing the same

An oxide semiconductor layer is formed, a gate insulating layer is formed over the oxide semiconductor layer, a gate electrode layer is formed to overlap with the oxide semiconductor layer with the gate insulating layer interposed therebetween, a first insulating layer is formed to cover the gate insulating layer and the gate electrode layer, an impurity element is introduced through the insulating layer to form a pair of impurity regions in the oxide semiconductor layer, a second insulating layer is formed over the first insulating layer, the first insulating layer and the second insulating layer are anisotropically etched to form a sidewall insulating layer in contact with a side surface of the gate electrode layer, and a source electrode layer and a drain electrode layer in contact with the pair of impurity regions are formed.. .
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device

A semiconductor device or the like capable of preventing malfunction of a driver circuit is provided. In a driver circuit for driving a power device used for current supply, a transistor including an oxide semiconductor is used as a transistor in a circuit (specifically, for example, a level shift circuit) requiring a high withstand voltage.
Semiconductor Energy Laboratory Co., Ltd.

High doped iii-v source/drain junctions for field effect transistors

A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a iii-v material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped iii-v material between doped iii-v materials, the doped iii-v materials including a dopant in an amount in a range from about le18 to about le20 atoms/cm3 and contacting the epitaxial contacts.. .
Stmicroelectronics, Inc.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate, an insulating structure, and a gate stack. The substrate has at least one semiconductor fin.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor devices including a stressor in a recess and methods of forming the same

Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region.
Samsung Electronics Co., Ltd.

Semiconductor structure with enhanced contact and manufacture the same

A method of forming a semiconductor structure includes the following operations: (i) forming a fin structure on a substrate; (ii) epitaxially growing an epitaxy structure from the fin structure; (iii) forming a sacrificial structure surrounding the epitaxy structure; (iv) forming a dielectric layer covering the sacrificial structure; (v) forming an opening passing through the dielectric layer to partially expose the sacrificial structure; (vi) removing a portion of the sacrificial structure to expose a portion of the epitaxy structure; and (vii) forming a contact structure in contact with the exposed portion of the epitaxy structure. A semiconductor structure is disclosed herein as well..
Taiwan Semiconductor Manufacturing Co., Ltd.

Interlayer dielectric film in semiconductor devices

A method of forming a semiconductor device includes depositing a flowable dielectric layer on a substrate and annealing the flowable dielectric layer. The method further includes performing a high temperature (ht) doping process on the flowable dielectric layer.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device and fabricating the same

A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium..
Samsung Electronics Co., Ltd.

Semiconductor device with control structure including buried portions and manufacturing

A semiconductor device includes transistor cells and control structures. The transistor cells include source zones of a first conductivity type and body zones of a second conductivity type.
Lnfineon Technologies Ag

Method of manufacturing a semiconductor device with trench gate by using a screen oxide layer

A screen oxide layer is formed on a main surface of a semiconductor layer and a passivation layer is formed on the screen oxide layer. A gate trench is formed in a portion of the semiconductor layer exposed by a mask opening in a trench mask that comprises the passivation layer.
Infineon Technologies Austria Ag

Semiconductor devices, power semiconductor devices, and methods for forming a semiconductor device

A semiconductor device includes a drift region of a device structure arranged in a semiconductor layer. The drift region includes at least one first drift region portion and at least one second drift region portion.
Infineon Technologies Ag

Semiconductor device and manufacturing semiconductor device

In a front surface of a semiconductor base body, a gate trench is disposed penetrating an n+-type source region and a p-type base region to a second n-type drift region. In the second n-type drift region, a p-type semiconductor region is selectively disposed.
National Institute Of Advanced Industrial Science And Technology

Semiconductor devices and methods of manufacturing the same

A semiconductor device includes a gate structure on a substrate, a source/drain layer on a portion of the substrate adjacent the gate structure, a first contact plug contacting an upper surface of the source/drain layer, and a second contact plug contacting upper surfaces of the gate structure and the first contact plug. A bottom surface of the second contact plug has a first portion not contacting the upper surface of the first contact plug, and the first portion is higher than the upper surface of the gate structure..
Samsung Electronics Co., Ltd.

Semiconductor device

A semiconductor device includes: a substrate; a semiconductor stack including a first nitride semiconductor layer and a second nitride semiconductor layer formed above the substrate; a source electrode and a drain electrode formed above a lower surface of the semiconductor stack; a gate electrode; in plan view, a current-drift area; a non-current-drift area; and a collapse reducing electrode formed on the non-current-drift area in the second nitride semiconductor layer, the collapse reducing electrode being formed to have a substantially same potential as the gate electrode. In the semiconductor device, the collapse reducing electrode and the second nitride semiconductor layer have a junction surface functioning as an energy barrier having a rectifying effect in a forward direction from the collapse reducing electrode to the second nitride semiconductor layer..
Panasonic Intellectual Property Management Co., Ltd.

Optimized buffer layer for high mobility field-effect transistor

A stack along a z-axis for a high-electron-mobility field-effect transistor, comprises: a buffer layer comprising a first semiconductor material comprising a binary, ternary or quaternary nitride compound having a first bandgap, a barrier layer comprising a second semiconductor material comprising a binary, ternary or quaternary nitride compound and having a second bandgap, the second bandgap wider than the first bandgap, a heterojunction between the buffer and barrier layers and, a two-dimensional electron gas located in an xy plane perpendicular to the z-axis and in the vicinity of the heterojunction wherein: the buffer layer comprises a zone comprising fixed negative charges of density per unit volume higher than or equal to 1017 cm−3, the zone having a thickness smaller than or equal to 200 nm, the product of multiplication of the density per unit volume of fixed negative charges by the thickness of the zone between 1012 cm−2 and 3.1013 cm−2.. .
Commissariat A L'energie Atomique Et Aux Energies Alternatives

Semiconductor device including two-dimensional material

A semiconductor device includes a substrate, a two-dimensional (2d) material layer formed on the substrate and having a first region and a second region adjacent to the first region, and a source electrode and a drain electrode provided to be respectively in contact with the first region and the second region of the 2d material layer, the second region of the 2d material layer including an oxygen adsorption material layer in which oxygen is adsorbed on a surface of the second region.. .
Research & Business Foundation Sungkyunkwan University

Trench-type insulated gate semiconductor device including an emitter trench and an overlapped floating region

A semiconductor device of the present invention includes a semiconductor layer, a plurality of gate trenches formed in the semiconductor layer, a gate electrode filled via a gate insulating film in the plurality of gate trenches, an n+-type emitter region, a p-type base region, and an n−-type drift region disposed, lateral to each gate trench, in order in a depth direction of the gate trench from a front surface side of the semiconductor layer, a p+-type collector region disposed on a back surface side of the semiconductor layer with respect to the n−-type drift region, a plurality of emitter trenches formed between the plurality of gate trenches adjacent to each other, a buried electrode filled via an insulating film in the plurality of emitter trenches, and electrically connected with the n+-type emitter region, and a p-type floating region formed between the plurality of emitter trenches, and the p-type floating region is formed deeper than the p-type base region, and includes an overlap portion that goes around to a lower side of an emitter trench closest to the gate trench out of the plurality of emitter trenches and has an end portion positioned on a side closer to the gate trench with respect to a center in a width direction of the emitter trench.. .
Rohm Co., Ltd.

Semiconductor device

A planar mosfet is provided on the upper surface of the n−-type semiconductor substrate in a mesa portion between the trenches. A p+-type emitter layer is provided between the trench and the planar mosfet in the mesa portion.
Mitsubishi Electric Corporation

Multiple zone power semiconductor device

A power semiconductor device is comprised of a plurality of zones having similar structure. Each of the zones may be characterized by a switching loss during transitions to a non-conducting state.
Ford Global Technologies, Llc

Semiconductor device

To provide a semiconductor device in which an edge termination structure can be made smaller easily. A semiconductor device is provided, the semiconductor device including an active region and an edge termination structure formed on a front surface side of a semiconductor substrate, wherein an edge termination structure has a guard ring provided surrounding an active region on a front surface side of a semiconductor substrate, a first field plate provided on a front surface side of a guard ring, an electrode unit provided on a front surface side of a first field plate, a second field plate provided between a first field plate and a electrode unit, and a conductive connecting unit which mutually electrically connects a first field plate, an electrode unit, a second field plate, and a guard ring..
Fuji Electric Co., Ltd.

Vertical tunneling field-effect transistor cell and fabricating the same

A method for forming a tunneling field-effect transistor (tfet) is disclosed. The method includes etching a semiconductor substrate to form a semiconductor protrusion that protrudes out from a top surface of the semiconductor substrate, forming a drain region in lower portion of the semiconductor protrusion, and patterning a gate stack layer to form a gate stack.
Taiwan Semiconductor Manufacturing Co., Ltd.

Source/drain structure of semiconductor device

An exemplary method for forming a semiconductor device includes etching a top portion etching a top portion of a first semiconductor fin to produce a recessed top portion of the fin. A dielectric layer is deposited over the first semiconductor fin and an adjacent isolation structure.
Taiwan Semiconductor Manufacturing Company, Ltd.

Method for fabricating finfet isolation structure

A method for forming a semiconductor device. In this method, a semiconductor fin is formed on a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device and manufacturing the same

A method of manufacturing a semiconductor device that includes a junction field effect transistor, the junction field effect transistor including a semiconductor substrate of a first conductivity type, an epitaxial layer of the first conductivity type formed on the semiconductor substrate, a source region of the first conductivity type formed on a surface of the epitaxial layer, a channel region of the first conductivity type formed in a lower layer of the source region, a pair of trenches formed in the epitaxial layer so as to sandwich the source region therebetween, and a pair of gate regions of a second conductivity type, opposite to the first conductivity type, formed below a bottom of the pair of trenches.. .
Renesas Electronics Corporation

Semiconductor structure with insertion layer and manufacturing the same

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, an interfacial layer formed over the substrate, and an insertion layer formed over the interfacial layer.
Taiwan Semiconductor Manufacturing Co., Ltd.

Method and device for metal gate stacks

A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, a high-k dielectric layer on the substrate, a capping layer on the high-k dielectric layer, forming a first n-type work function metal layer on the capping layer, forming a second n-type work function metal layer on the first n-type work function metal layer, and forming a metal electrode layer on the second n-type work function metal layer. The second n-type work function metal layer has a ti/al atomic ratio greater than the ti/al atomic ratio of the first n-type work function metal layer.
Semiconductor Manufacturing International (shanghai) Corporation

Gate structure, semiconductor device and the forming semiconductor device

A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device with a gate contact positioned above the active region

One illustrative device disclosed herein includes a stepped conductive source/drain structure with a cavity defined therein, the cavity being located vertically above an active region, a non-conductive structure positioned in the cavity, a layer of insulating material positioned above the gate structure, the stepped conductive source/drain structure and the non-conductive structure, a gate contact opening defined in the layer of insulating material and a conductive gate contact positioned in the gate contact opening that is conductively coupled to the gate structure, wherein at least a portion of the conductive gate contact is positioned vertically above the non-conductive structure.. .
Globalfoundries Inc.

Nitride semiconductor device using insulating films having different bandgaps to enhance performance

The semiconductor device includes: a channel layer, a barrier layer, a first insulating film, and a second insulating film, each of which is formed above a substrate; a trench that penetrates the second insulating film, the first insulating film, and the barrier layer to reach the middle of the channel layer; and a gate electrode arranged in the trench and over the second insulating film via a gate insulating film. The bandgap of the second insulating film is smaller than that of the first insulating film, and the bandgap of the second insulating film is smaller than that of the gate insulating film gi.
Renesas Electronics Corporation

Semiconductor devices and fabricating methods thereof

Provided are semiconductor devices and fabricating methods thereof. The semiconductor device includes a field insulating layer formed in a substrate, an interlayer dielectric layer formed on the field insulating layer and including a trench exposing at least a portion of the field insulating layer, a deposition insulating layer formed in the trench to be disposed on the field insulating layer, a gate insulating layer formed the trench to be disposed on the deposition insulating layer, and a metal gate formed the trench on the gate insulating layer..
Samsung Electronics Co., Ltd.

Reduction of defect induced leakage in iii-v semiconductor devices

A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 10 cm−2. An n-type layer is formed on or in the p-doped layer.
International Business Machines Corporation

Semiconductor device

According to the present invention, a semiconductor device includes a first conductivity type sic layer, an electrode that is selectively formed upon the sic layer, and an insulator that is formed upon the sic layer and that extends to a timing region that is set at an end part of the sic layer. The insulator includes an electrode lower insulating film that is arranged below the electrode, and an organic insulating layer that is arranged so as to cover the electrode lower insulating film.
Rohm Co., Ltd.

Semiconductor device and manufacturing semiconductor device

A semiconductor device includes a wide-bandgap semiconductor substrate of a first conductivity type, a wide-bandgap semiconductor deposition layer of the first conductivity type, semiconductor regions of a second conductivity type, a wide-bandgap semiconductor layer of the second conductivity type, first regions of the first conductivity type, and second regions of the first conductivity type. The width w of a plating film formed on a source electrode of the semiconductor device is greater than or equal to 10 μm.
Fuji Electric Co., Ltd.

Three-dimensional semiconductor devices

A three-dimensional (3d) semiconductor device includes a plurality of gate electrodes stacked on a substrate in a direction normal to a top surface of the substrate, a channel structure passing through the gate electrodes and connected to the substrate, and a void disposed in the substrate and positioned below the channel structure.. .

Semiconductor device having multi-channel and forming the same

A semiconductor device includes an isolation pattern on a substrate, the isolation pattern having a lower insulating pattern on the substrate, and a spacer to cover side surfaces of the lower insulating pattern, a vertical structure through the isolation pattern to contact the substrate, the vertical structure having a first semiconductor layer on the substrate, a lower end of the first semiconductor layer being at a lower level than a lower surface of the isolation pattern, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, and a gate electrode crossing the vertical structure and extending over the isolation pattern.. .

Nanowire channel structures of continuously stacked heterogeneous nanowires for complementary metal oxide semiconductor (cmos) devices

Aspects disclosed in the detailed description include nanowire channel structures of continuously stacked heterogeneous nanowires for complementary metal oxide semiconductor (cmos) devices. Each of the nanowires has a top end portion and a bottom end portion that are narrower than a central portion.
Qualcomm Incorporated

Method for making iii-v nanowire quantum well transistor

The present invention provides a filed effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first iii-v compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first iii-v compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first iii-v compound layer.
Zing Semiconductor Corporation

Expitaxially regrown heterostructure nanowire lateral tunnel field effect transistor

After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type..
Globalfoundries Inc.

Deep trench isolation structures and systems and methods including the same

Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device.
Nxp Usa, Inc.

Metal-oxide-semiconductor transistor and forming gate layout

A metal-oxide-semiconductor transistor includes a substrate, a gate insulating layer disposed on the surface of the substrate layer, a metal gate disposed on the gate insulating layer and having at least one plug hole, at least one dielectric plug disposed in the plug hole, and two diffusion regions disposed at two sides of the metal gate in the substrate. The metal gate is configured to operate under an operation voltage greater than 5 v..
United Microelectronics Corp.

Silicon carbide semiconductor device, and manufacturing same

The silicon carbide substrate includes a first impurity region, a second impurity region, and a third impurity region. The first impurity region includes: a first region in contact with the second impurity region; a second region that is in contact with the first region, that is located opposite to the second impurity region when viewed from the first region, and that has an impurity concentration higher than an impurity concentration of the first region; and a third region that is in contact with the second region, that is located opposite to the first region when viewed from the second region, and that has an impurity concentration lower than the impurity concentration of the second region.
Sumitomo Electric Industries, Ltd.

Thin film transistor substrate and organic light-emitting display using the same

A thin film transistor substrate that includes a substrate, a lower gate electrode arranged on the substrate, a semiconductor layer arranged on the substrate and overlapping the lower gate electrode, the semiconductor layer including a channel region interposed between a source region and a drain region, and an upper gate electrode arranged on the substrate and overlapping the semiconductor layer, the upper gate electrode being arranged on an opposite side of the semiconductor layer than the lower gate electrode, wherein at least one of the lower gate electrode and the upper gate electrode is perforated by an aperture to reduce a parasitic capacitance between the upper and lower gate electrodes.. .
Samsung Display Co., Ltd.,

Method for manufacturing tft substrate and structure thereof

The present invention provides a method for manufacturing a tft substrate and a structure thereof. The method for manufacturing a tft substrate uses a gray tone mask to apply a single photolithographic process to simultaneously manufacture a gate insulation layer, a semiconductor layer, and a etch stop so as to reduce the number of the photolithographic processes used from ten processes to eight processes and reduce the number of masks used thereby simplifying the manufacturing process and effectively increasing the manufacturing efficiency and the yield rate.
Shenzhen China Star Optoelectronics Technology Co. , Ltd.

Electronic device and fabricating the same

An electronic device and a method for fabricating the same are provided. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a plurality of first lines extending in a first direction; a plurality of second lines extending in a second direction that intersects with the first direction; a plurality of variable resistance elements disposed between the first lines and the second lines and located at intersections of the first lines and the second lines; and a plug connected to a first portion of each of the first lines, wherein the plug comprises a conductive layer and a material layer having a resistance value higher than that of the conductive layer..
Sk Hynix Inc.

Semiconductor integrated circuit device capable of reducing a leakage current

A semiconductor integrated circuit device may include a semiconductor substrate, a source pattern, a drain pattern, a nano wire pattern and a gate. The source pattern may be formed on an upper surface of the semiconductor substrate.
Sk Hynix Inc.

Method of producing a semiconductor device

A semiconductor device includes four or more first memory cells arranged on a row, the first memory cells each including a first pillar-shaped semiconductor layer, a first gate insulating film formed around the first pillar-shaped semiconductor layer, a first gate line formed around the first gate insulating film, and a first magnetic tunnel junction storage element formed on the first pillar-shaped semiconductor layer. The semiconductor device further includes a first source line that connects lower portions of the first pillar-shaped semiconductor layers to each other, a first bit line that extends in a direction perpendicular to a direction in which the first gate line extends and that is connected to an upper portion of the first magnetic tunnel junction storage element, and a second source line that extends in a direction perpendicular to a direction in which the first source line extends..
Unisantis Electronics Singapore Pte. Ltd.

Mtj structures and magnetoresistive random access memory devices including the same

A magnetic tunnel junction (mtj) structure includes a fixed layer pattern structure having a perpendicular magnetization direction, a tunnel barrier pattern on the fixed layer pattern structure, a free layer pattern on the tunnel barrier pattern, the free layer pattern having a perpendicular magnetization direction, a first surface magnetism induction pattern on the free layer pattern, the first surface magnetism induction pattern inducing a perpendicular magnetism in a surface of the free layer pattern, a conductive pattern on the first surface magnetism induction pattern, and a ferromagnetic pattern on the conductive pattern.. .

Semiconductor device and forming the same

A semiconductor device includes an active region defining an isolation region. First and second cell interconnection structures are on the active region and the isolation region, and have line shapes that are parallel to each other.

Magnetoresistive sensor module and manufacturing the same

In the method of manufacturing a magnetoresistive sensor module, at first a composite arrangement out of a semiconductor substrate and a metal-insulator arrangement is provided, wherein a semiconductor circuit arrangement is integrated adjacent to a main surface of the semiconductor substrate into the same, wherein the metal-insulator arrangement is arranged on the main surface of the semiconductor substrate and comprises a structured metal sheet and insulation material at least partially surrounding the structured metal sheet, wherein the structured metal sheet is electrically connected to the semiconductor circuit arrangement. Then, a magnetoresistive sensor structure is applied onto a surface of the insulation material of the composite arrangement, and finally an electrical connection between the magnetoresistive sensor structure and the structured metal sheet is established, so that the magnetoresistive sensor structure is connected to the integrated circuit arrangement..
Infineon Technologies Ag

Integrated piezoelectric micromechanical ultrasonic transducer pixel and array

An ultrasonic sensor pixel includes a substrate, a piezoelectric micromechanical ultrasonic transducer (pmut) and a sensor pixel circuit. The pmut includes a piezoelectric layer stack including a piezoelectric layer disposed over a cavity, the cavity being disposed between the piezoelectric layer stack and the substrate, a reference electrode disposed between the piezoelectric layer and the cavity, and one or both of a receive electrode and a transmit electrode disposed on or proximate to a first surface of the piezoelectric layer, the first surface being opposite from the cavity.
Qualcomm Incorporated

Phase detection autofocus techniques

The present disclosure relates to an image sensor having autofocus function and associated methods. In some embodiments, the integrated circuit has a photodiode array with a plurality of photodiodes disposed within a semiconductor substrate and a composite grid overlying the photodiode array and having a first plurality of openings and a second plurality of openings extending vertically through the composite grid.
Taiwan Semiconductor Manufacturing Co., Ltd.

Solid-state imaging apparatus, manufacturing method therefor, and electronic apparatus

A charge accumulation section that is formed on a first semiconductor substrate and accumulates photoelectrically converted charges, a charge-retaining section that is formed on a second semiconductor substrate and retains charges accumulated in the charge accumulation section, and a transfer transistor that is formed on the first semiconductor substrate and the second semiconductor substrate and transfers charges accumulated in the charge accumulation section to the charge-retaining section are provided. A bonding interface between the first semiconductor substrate and the second semiconductor substrate is formed in a channel of the transfer transistor..

Semiconductor device

A plurality of pixel regions are aligned in a matrix in a semiconductor substrate, and each of the plurality of pixel regions includes an active region, two photoelectric conversion elements, two floating capacitance regions, and a first transistor. Each of the plurality of pixel regions includes two transfer transistors each having each of the two photoelectric conversion elements and each of the two floating capacitance regions.
Renesas Electronics Corporation

Interconnect apparatus and method

An apparatus comprises a first semiconductor chip including a first substrate, a plurality of first inter-metal dielectric layers and a plurality of first metal lines, a second semiconductor chip having a surface in contact with a surface of the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate, a plurality of second inter-metal dielectric layers and a plurality of second metal lines and a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion over a first side of a hard mask layer and a second portion over a second side of the hard mask layer, wherein the hard mask layer is a ring-shaped layer, and wherein the conductive plug is formed in a center opening of the ring-shaped layer.. .
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device and forming the same

A semiconductor device includes a semiconductor substrate, a radiation-sensing region, at least one isolation structure, and a doped passivation layer. The radiation-sensing region is present in the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor on insulator substrate with back bias

A semiconductor on insulator substrate includes an electrically conductive layer disposed between an electrically insulating handle layer and the semiconductor layer to facilitate the application of a back bias. The connection of the electrically conductive layer to a reference voltage reduces the effects of trapped or fixed charges associated with the handle layer on the threshold voltage of a transistor formed on the semiconductor layer.
International Business Machines Corporation

Manufacture dual gate oxide semiconductor tft substrate and structure thereof

The present invention provides a manufacture method of an oxide semiconductor tft substrate and a structure thereof. The manufacture method of the dual gate oxide semiconductor tft substrate utilizes the halftone mask to implement one photo process, which cannot only accomplish the patterning to the oxide semiconductor layer but also obtain the oxide conductor layer (52′) with ion doping process, and the oxide conductor layer (52′) is employed as being the pixel electrode of the lcd to replace the ito pixel electrode in prior art; the method manufactures the source (81), the drain (82) and the top gate (71) at the same time with one photo process; the method implements patterning process to the passivation layer (8) and the top gate isolation layer (32) together with one photo process, to reduce the number of the photo processes to nine for shortening the manufacture procedure, raising the production efficiency and lowering the production cost..
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Liquid crystal display device and manufacturing the same

Provided are liquid crystal display and the method for manufacturing the same. According to an aspect of the present invention, there is provided a liquid crystal display device, including a first substrate; a gate electrode disposed on the first substrate; a semiconductor pattern layer disposed on the gate electrode; and a source electrode and a drain electrode disposed on the semiconductor pattern layer and facing each other, wherein a diffusion prevention pattern is disposed on the semiconductor pattern layer to prevent diffusion into the semiconductor pattern layer or to maintain uniform thickness of the semiconductor pattern layer..
Samsung Display Co., Ltd.

Method of tuning source/drain proximity for input/output device reliability enhancement

A semiconductor device includes a first finfet device and a second finfet device. The first finfet device includes a first gate, a first source, and a first drain.
Taiwan Semiconductor Manufacturing Company, Ltd.

Three-dimensional semiconductor devices

A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.. .

Semiconductor device and manufacturing the same

A semiconductor device includes a first stack including a plurality of alternating layers of first interlayer insulating layers and first conductive patterns; a second stack including a plurality of alternating layers of second conductive patterns and second interlayer insulating layers, the second stack being positioned above the first stack; a plurality of pillar-structures each pillar structure passing through the first and second stacks; and a ring pattern layer disposed between the first and second stacks, the ring pattern layer comprising a plurality of ring patterns, each ring pattern surrounding each pillar-structure.. .
Sk Hynix Inc.

Semiconductor device

According to one embodiment, a semiconductor device includes a stacked body; a columnar portion; a plate portion; and a blocking insulating film. The stacked body includes a plurality of electrode layers.
Kabushiki Kaisha Toshiba

Semiconductor device and manufacturing same

According to one embodiment, the stacked body includes a plurality of electrode layers stacked with an insulator interposed. The semiconductor body extends in a stacking direction through the stacked body.
Kabushiki Kaisha Toshiba

Methods for manufacturing ultrathin semiconductor channel three-dimensional memory devices

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack to the substrate.
Sandisk Technologies Inc.

Semiconductor structure and manufacturing method thereof

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, a non-volatile memory cell, and a gate stack.
United Microelectronics Corp.

Semiconductor device and manufacturing the same

The semiconductor device may include a first sub-pipe gate having a pipe hole formed therein; a second sub-pipe gate disposed on the first sub-pipe gate and passed-through by vertical holes being coupled to the pipe hole, wherein a material of the second sub-pipe gate has a lower oxidation rate than that of a material of the first sub-pipe gate; a first oxidized layer formed within a portion of the first sub-pipe gate to conform to a contour of the pipe hole; and a second oxidized layer formed within a portion of the second sub-pipe gate to conform to a contour of the vertical holes and the contour of the pipe hole.. .
Sk Hynix Inc.

Semiconductor structure and forming the same

A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Ultrathin semiconductor channel three-dimensional memory devices

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack to the substrate.
Sandisk Technologies Inc.

Semiconductor memory device and manufacturing the same

In general, according to one embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first sub-conductive layer, a first insulating film. One portion of the first conductive layer overlaps at least one portion of the first sub-conductive layer in the first direction.
Kabushiki Kaisha Toshiba

Semiconductor device

At least one of a plurality of transistors which are highly integrated in an element is provided with a back gate without increasing the number of manufacturing steps. In an element including a plurality of transistors which are longitudinally stacked, at least a transistor in an upper portion includes a metal oxide having semiconductor characteristics, a same layer as a gate electrode of a transistor in a lower portion is provided to overlap with a channel formation region of the transistor in an upper portion, and part of the same layer as the gate electrode functions as a back gate of the transistor in an upper portion.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device, electronic component, and electronic device

A semiconductor device excellent in writing operation is provided. In a structure where a data voltage supplied to a source line is supplied to a node of a memory cell via a bit line, a switch is provided between memory cells connected to the bit line.
Semiconductor Energy Laboratory Co., Ltd.

Transistor, fabricating the same, and electronic device including the same

A semiconductor device includes a stressed substrate stressed by a first stress, a first stressed channel formed in the substrate and having the first stress, and a first strained gate electrode strained by a first strain generating element. A first strained gate electrode is formed over the first stressed channel, the first strained gate electrode including a first lattice-mismatched layer to induce a second stress to the first stressed channel..
Sk Hynix Inc.

Semiconductor devices including insulating materials in fins

Semiconductor devices are provided. A semiconductor device includes a first insulating material in a first fin.
Samsung Electronics Co., Ltd.

Semiconductor device and semiconductor integrated circuit using the same

A semiconductor device includes a channel region of a first conductivity type, a gate insulating film formed on the channel region, a gate electrode formed on the gate insulating film, a first region of a second conductivity type and a second region of the second conductivity type, which are formed along the gate electrode while facing each other with the gate electrode interposed between the first region and the second region, a semiconductor region of the second conductivity type on which the first region, the second region and the channel region are formed, and an element isolation region which surrounds the semiconductor region. The gate electrode extends beyond a boundary portion between the channel region and the element isolation region.
Rohm Co., Ltd.

Semiconductor device and manufacturing method thereof

A semiconductor device includes first and second fin fet and a separation plug made of an insulating material and disposed between the first and second fin fets. The first fin fet includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending a second direction perpendicular to the first direction.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device

A semiconductor device with a small number of transistors is provided. The semiconductor device includes a first transistor, a second transistor, a third transistor, a first wiring, and a second wiring.
Semiconductor Energy Laboratory Co., Ltd.

Method of manufacturing a semiconductor device having reduced on-state resistance and structure

A semiconductor device includes a singulated region of semiconductor material having a first major surface and a second major surface opposite to the first major surface. In one embodiment, the second major surface includes a recessed surface portion bounded by opposing sidewall portions extending outward from the region of semiconductor material in cross-sectional view.
Semiconductor Components Industries, Llc

Semiconductor device and manufacturing semiconductor device

A second electrode provided on the fifth semiconductor region and the seventh semiconductor region.. .

Semiconductor apparatus

A semiconductor apparatus includes a semiconductor substrate, a semiconductor element, an edge termination region that surrounds the semiconductor element, a protective diode that has a first terminal and a second terminal, where the first terminal is positioned within the edge termination region and the second terminal is positioned outside the edge termination region, and a diffusion layer that has a floating potential, where the diffusion layer is provided in a gap portion between a region of the edge termination region that is aligned with the protective diode and the protective diode.. .
Fuji Electric Co., Ltd.

Electrostatic discharge protection semiconductor device

An esd protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, and at least a first doped region formed in the drain region. The source region and the drain region include a first conductivity type, and the first doped region includes a second conductivity type.
United Microelectronics Corp.

Semiconductor devices having hybrid stacking structures and methods of fabricating the same

A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other.

Semiconductor device

A semiconductor device according to the present invention includes: a through via formed to penetrate a semiconductor substrate; first and second buffer circuits; a wiring forming layer formed in an upper layer of the semiconductor substrate; a connecting wiring portion formed in an upper portion of the through via assuming that a direction from the semiconductor substrate to the wiring forming layer is an upward direction, the connecting wiring portion being formed on a chip inner end face that faces the upper portion of the semiconductor substrate at an end face of the through via; a first path connecting the first buffer circuit and the through via; and a second path connecting the second buffer circuit and the through via. The first path and the second path are electrically connected through the connecting wiring portion..
Renesas Electronics Corporation

Semiconductor package and manufacturing same

Provided are a semiconductor package and method for manufacturing the same. The semiconductor package includes a first semiconductor chip.
Samsung Electronics Co., Ltd.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a plurality of semiconductor dies stacked vertically to have a vertical height and a dielectric surrounding the stacked semiconductor dies. The semiconductor device further has a conductive post external to the stacked semiconductor dies and extending through the dielectric.
Taiwan Semiconductor Manufacturing Company Ltd.

Wire bond cleaning method and wire bonding recovery process

Methods, systems and devices are disclosed for performing a semiconductor processing operation. In some embodiments this includes configuring a wire bonding machine to perform customized movements with a capillary tool of the wire bonding machine, etching bulk contaminants over one or more locations of a semiconductor device with the capillary tool, and applying plasma to the semiconductor device to remove residual contaminants..
Skyworks Solutions, Inc.

Plasma etch singulated semiconductor packages and related methods

A method of forming a plurality of semiconductor packages includes providing an array of unsingulated semiconductor packages that are at least partially encapsulated in an encapsulant. The array of unsingulated semiconductor packages may be coupled with a lead frame or a substrate.
Semiconductor Components Industries, Llc

Press fitting head and semiconductor manufacturing apparatus using the same

A press fitting head comprising an elastic member in a part where the press fitting head contacts a semiconductor device, and an alignment mark recognition area capable of detecting an optically readable marker provided on a surface to be contacted to the semiconductor device is provided. Additionally, a semiconductor manufacturing apparatus in which the press fitting head is applied is provided..
J-devices Corporation

Bonding wire for semiconductor device

The present invention provides a bonding wire which can satisfy bonding reliability, spring performance, and chip damage performance required in high-density packaging. A bonding wire contains one or more of in, ga, and cd for a total of 0.05 to 5 at %, and a balance being made up of ag and incidental impurities..
Nippon Micrometal Corporation

Semiconductor device with an anti-pad peeling structure and associated method

A semiconductor device with an anti-pad peeling structure is disclosed. The semiconductor device includes: a semiconductor substrate including a through substrate via (tsv); a dielectric layer on the semiconductor substrate and including a plurality of recesses therein; and a pad above the semiconductor substrate to cover a portion of the dielectric layer and extend to the recesses; wherein the pad extends to the plurality of recesses, and a plurality of contact points are confined in the recesses between the pad and the conductive layer, and each of the contact points is at least partially excluded from a boundary of the tsv when being seen from a top-down perspective..
Taiwan Semiconductor Manufacturing Company Ltd.

Semiconductor chip with patterned underbump metallization and polymer film

Various semiconductor chip solder bump and underbump metallization (ubm) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes forming a first underbump metallization layer on a semiconductor chip is provided.

Lid structure and semiconductor device package including the same

The present disclosure relates to a semiconductor device package, which includes a carrier, a lid, a first adhesive layer and a constraint structure. The carrier includes a surface and a first conductive pad on the surface of the carrier.
Advanced Semiconductor Engineering, Inc.

Semiconductor die contact structure and method

A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor chip device

According to various embodiments, a method may include: forming a first layer on a surface using a first lift-off process; forming a second layer over the first layer using a second lift-off process; wherein the second lift-off process is configured such that the second layer covers at least one sidewall of the first layer at least partially.. .
Infineon Technologies Ag

Semiconductor device and method

A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material..
Taiwan Semiconductor Manufacturing Company, Ltd.

Wafer level package with tsv-less interposer

A semiconductor device includes an interposer having a first side and a second side opposite to the first side; a first semiconductor die mounted on the first side within a first chip mounting area through a plurality of first bumps; a second semiconductor die mounted on the first side within a second chip mounting area being adjacent to the first chip mounting area; a ring-shaped supporting feature disposed on the first side and encompassing the first chip mounting area and the second chip mounting area; and a plurality of solder bumps mounted on the second side.. .
Inotera Memories, Inc.

Method for manufacturing semiconductor apparatus and semiconductor apparatus

A method for manufacturing a semiconductor apparatus, including an encapsulating step of collectively encapsulating a device mounting surface of a substrate having semiconductor devices mounted thereon with a base-attached encapsulant having a base and a thermosetting resin layer formed on one surface of the base, the semiconductor devices being mounted by flip chip bonding, the encapsulating step including a unifying stage of unifying the substrate having the semiconductor devices mounted thereon and the base-attached encapsulant under a reduced pressure condition with a vacuum of 10 kpa or less, and a pressing stage of pressing the unified substrate with a pressure of 0.2 mpa or more.. .
Shin-etsu Chemical Co., Ltd.

Compound semiconductor substrate

A compound semiconductor substrate according to the present invention includes a compound semiconductor layer formed on one main surface of a ground substrate via a seed layer, wherein the ground substrate is formed of a sintered body, the seed layer is formed of a single crystal, the compound semiconductor layer includes a structure having a buffer layer and an active layer that are sequentially crystal-grown on the seed layer, a thermal expansion coefficient of the sintered body is 0.7 times or more and 1.4 times or less an average thermal expansion coefficient of the entire compound semiconductor layer, and an fwhm of an x-ray diffraction peak of the buffer layer obtained by an x-ray diffraction rocking curve measurement is 800 arcsec or less.. .
Coorstek Kk

Semiconductor device and manufacturing method thereof

A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package.
Taiwan Semiconductor Manufacturing Company Ltd.

Method of forming deep trench and deep trench isolation structure

A method of forming a deep trench in a semiconductor substrate includes: forming a first mask pattern over the semiconductor substrate, in which the first mask pattern has a first opening exposing a portion of the semiconductor substrate; forming a second mask pattern over the first mask pattern, in which the second mask pattern has a second opening substantially aligned with the first opening to expose the portion of the semiconductor substrate, and the second opening has a width greater than a width of the first opening to further expose a portion of the first mask pattern; and removing the portion of the semiconductor substrate, the portion of first mask pattern and another portion of the semiconductor substrate beneath the portion of the first mask pattern to form the deep trench.. .
Taiwan Semiconductor Manufacturing Co., Ltd.

Interposer-less stack die interconnect

Techniques for providing a semiconductor assembly having an interconnect die for die-to-die interconnection, an ic package, a method for manufacturing, and a method for routing signals in an ic package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die coupled to a first integrated circuit (ic) die and a second ic die by inter-die connections.
Xilinx, Inc.

Semiconductor package assembly with through silicon via interconnect

The invention provides a semiconductor package assembly with a tsv interconnect. The semiconductor package assembly includes a first semiconductor package mounted on a base, having: a semiconductor die, a semiconductor substrate, and a first array of tsv interconnects and a second array of tsv interconnects formed through the semiconductor substrate, wherein the first array and second array of tsv interconnects are separated by an interval region.
Mediatek Inc.

Trench mosfet with self-aligned body contact with spacer

Trench mosfet with self-aligned body contact with spacer. In accordance with an embodiment of the present invention, a semiconductor device includes a semiconductor substrate, and at least two gate trenches formed in the semiconductor substrate.
Vishay-siliconix

Package structure, fan-out package structure and the same

A package structure includes a spiral coil, a redistribution layer (rdl) and a molding material. The molding material fills gaps of the spiral coil.
Taiwan Semiconductor Manufacturing Company Ltd.

Conductive structures, systems and devices including conductive structures and related methods

Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the plurality of conductive steps and insulated from at least another one of the conductive steps. Devices may include such conductive structures.
Micron Technology, Inc.

Layout compound semiconductor integrated circuits

A layout method for compound semiconductor integrated circuits, comprising following steps of: forming a first metal layer within a first circuit layout area which intersects with a second circuit layout area at an intersection area on a compound semiconductor substrate; defining an adjacent crossover area including said intersection area and a peripheral adjacent area thereof; a first dielectric area located within said adjacent crossover area and intersected with at least part of said intersection area; forming a first dielectric block within said first dielectric area or forming said first dielectric block within said first dielectric area and a second dielectric block outside said first dielectric area, the thickness of said second dielectric block is no greater than and the thickness of at least part of said second dielectric block is smaller than the thickness of said first dielectric block; forming a second metal layer within said second circuit layout area.. .
Win Semiconductors Corp.

Semiconductor device and manufacturing the same

A semiconductor device includes an interlayer insulating film ins2, adjacent cu wirings m1w formed in the interlayer insulating film ins2, and an insulating barrier film br1 which is in contact with a surface of the interlayer insulating film ins2 and surfaces of the cu wirings m1w and covers the interlayer insulating film ins2 and the cu wirings m1w. Between the adjacent cu wirings m1w, the interlayer insulating film ins2 has a damage layer dm1 on its surface, and has an electric field relaxation layer er1 having a higher nitrogen concentration than a nitrogen concentration of the damage layer dm1 at a position deeper than the damage layer dm1..
Renesas Electronics Corporation

Semiconductor device

A semiconductor device, in which a plurality of control terminals that correspond to a main terminal and the same semiconductor chip protrude from a surface of an encapsulating part, and a plurality of signal paths that include the plurality of control terminals are positioned so as to be aligned with the main terminal in a first direction. Provided in each of the plurality of signal paths are pairs of relay members having identical functions, and a first relay grouping that includes one relay member of the pair of relay and a second relay grouping that includes the other relay member of the pair are positioned neighboring each other aligned in the first direction, with the ordering of the first relay grouping being mirror-inverted relative to the second relay grouping..
Denso Corporation

Semiconductor package structure and manufacturing the same structure

A semiconductor package structure includes a first semiconductor substrate, a second semiconductor substrate, a semiconductor die electrically connected to the first semiconductor substrate, an interconnection element and an encapsulant. The first semiconductor substrate includes a first top pad, and the second semiconductor substrate includes a second bottom pad.
Advanced Semiconductor Engineering, Inc.

Single or multi chip module package and related methods

Implementations of a semiconductor device package may include: a plurality of electrical contacts on a first face of a die, at least one clip electrically and mechanically coupled with at least one electrical contact on a second face of the die where the second face of the die is on an opposing side of the die from the first face of the die. The at least one clip may include at least one lead in electrical communication with the at least one electrical contact on the second face of the die.
Semiconductor Components Industries, Llc

Support and/or clip for semiconductor elements, semiconductor component, and production method

The invention relates to a support and/or clip for at least one semiconductor element with at least one functional surface (10) for connecting to the semiconductor element. The invention is further characterized by at least one solder resist cavity (12) with at least one flank wall (13), in particular a straight flank wall (13), and a delimiting edge (14) which adjoins the flank wall (13) and delimits the functional surface (10) at least on one side.
Heraeus Deutschland Gmbh & Co. Kg

Lead frame and semiconductor device

A semiconductor device includes a lead frame; a semiconductor chip mounted on the lead frame; and an encapsulation resin, wherein a convexo-concave portion including a plurality of concave portions is provided at a covered portion of the lead frame that is covered by the encapsulation resin, wherein the planer shape of each of the concave portions is a circle, the diameter of which is greater than or equal to 0.020 mm and less than or equal to 0.060 mm, or a polygon, the diameter of whose circumcircle is greater than or equal to 0.020 mm and less than or equal to 0.060 mm, and wherein a ratio s/s0 is greater than or equal to 1.7 where “s” is a surface area of the convexo-concave portion that is formed at a flat surface whose surface area is “s0”.. .
Shinko Electric Industries Co., Ltd.

Semiconductor device

A semiconductor device includes a semiconductor chip having an active surface and a non-active surface opposite to the active surface, an upper insulating layer provided on the non-active surface of semiconductor chip, and a via and a connection pad penetrating the semiconductor chip and the upper insulating layer, respectively. The connection pad has a first surface exposed outside the upper insulating layer and a second surface opposite to the first surface and facing the semiconductor chip.
Samsung Electronics Co., Ltd.

Semiconductor device with heat information mark

A semiconductor device includes a semiconductor package and a mark. The semiconductor package includes a semiconductor chip including a hot spot from which heat is generated, and a mold layer encapsulating the semiconductor chip.
Samsung Electronics Co., Ltd.

Semiconductor device including electromagnetic absorption and shielding

A semiconductor device is disclosed including material for absorbing emi and/or rfi. The device includes a substrate, one or more semiconductor die, and molding compound around the one or more semiconductor die.
Sandisk Information Technology (shanghai) Co. Ltd.

Semiconductor package, fabricating the same, and semiconductor module

A semiconductor package, a semiconductor module, a method of fabricating a semiconductor package are disclosed. The semiconductor package may include a substrate, a semiconductor chip, a connection terminal, a mold layer, and a protection layer.

External gettering

Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be incorporated as part of an electronic packaging for the structure, is disclosed.
Micron Technology, Inc.

Monitoring method and manufacturing semiconductor device

A monitoring method that can detect a sign of disconnection of a heat generation source is provided. Further, a highly reliable semiconductor device is provided.
Renesas Electronics Corporation

Semiconductor structure and forming the same

A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof.
Taiwan Semiconductor Manufacturing Co., Ltd.

Structures with thinned dielectric material

The disclosure relates to semiconductor structures and, more particularly, to structures with thinned dielectric material and methods of manufacture. The method includes depositing a high-k dielectric on a substrate.
Globalfoundries Inc.

Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (cmos) devices

Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (cmos) devices are disclosed. In one aspect, an exemplary cmos device includes a nanowire channel structure that includes a plurality of continuously stacked nanowires.
Qualcomm Incorporated

Complementary metal-oxide-semiconductor field-effect transistor and method thereof

This invention application provides a complementary metal-oxide-semiconductor field-effect transistor and method thereof. The transistor comprises a semiconductor substrate, a n-type field-effect transistor positioned in the semiconductor substrate, and a p-type field-effect transistor positioned in the semiconductor substrate and spaced apart the n-type field-effect transistor.
Zing Semiconductor Corporation

Semiconductor device and fabricating the same

A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.. .
Samsung Electronics Co., Ltd.

Method of dicing a wafer and semiconductor chip

A method of dicing a wafer may include forming a plurality of active regions in a wafer, each active region including at least one electronic component, the active regions extending from a first surface of the wafer into the wafer by a height and being separated by separation regions, forming at least one trench in the wafer by plasma etching in at least one separation region from the first surface of the wafer. The at least one trench is extending into the wafer farther than the plurality of active regions.
Infineon Technologies Ag

Systems and methods for producing flat surfaces in interconnect structures

In interconnect fabrication (e.g. A damascene process), a conductive layer is formed over a substrate with holes, and is polished to provide interconnect features in the holes.
Tessera, Inc.

Selective bottom-up metal feature filling for interconnects

A method for selective bottom-up filling of recessed features with a low resistivity metal for semiconductor devices is described in several embodiments. The method includes providing a substrate containing a patterned dielectric layer having a recessed feature with dielectric layer surfaces and a metal-containing surface on a bottom of the recessed feature, reacting the dielectric layer surfaces with a reactant gas containing a hydrophobic functional group to form hydrophobic dielectric layer surfaces, and at least substantially filling the recessed feature with a metal in a bottom-up gas phase deposition process that hinders deposition of the metal on the hydrophobic dielectric layer surfaces.
Tokyo Electron Limited

Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device

In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer.
Qualcomm Incorporated

Liquid composition for cleaning semiconductor device, cleaning semiconductor device, and fabricating semiconductor device

[solution] a liquid cleaning composition of the present invention used for fabricating a semiconductor device comprises hydrogen peroxide at 1-30% by mass, potassium hydroxide at 0.01-1% by mass, aminopolymethylene phosphoric acid at 0.0001-0.01% by mass, a zinc salt at 0.0001-0.1% by mass and water.. .

Dielectric with air gaps for use in semiconductor devices

Aspects of the invention are directed to a method for forming a semiconductor device. A dielectric layer is formed on a semiconductor substrate.
International Business Machines Corporation

Heating member, electrostatic chuck, and ceramic heater

A heating member includes a ceramic substrate having a structure in which a plurality of ceramic layers are laminated together; a resistance heat-generating element embedded in the ceramic substrate; an electricity supply element disposed on a surface of the ceramic substrate; and an electricity supply path embedded in the ceramic substrate and electrically connecting the resistance heat-generating element and the electricity supply element. The electricity supply path includes a plurality of conductive layers disposed along the planar direction of the ceramic layers at different positions in the thickness direction of the ceramic substrate, and a plurality of vias disposed along the thickness direction of the ceramic substrate.
Ngk Spark Plug Co., Ltd.

Electrostatic chuck design for cooling-gas light-up prevention

An electrostatic chuck (esc) in a chamber of a semiconductor manufacturing apparatus is presented for eliminating cooling-gas light-up. One wafer support includes a baseplate connected to a radiofrequency power source, a dielectric block, gas supply channels for cooling the wafer bottom, and first and second electrodes.
Lam Research Corporation

Service tunnel for use on capital equipment in semiconductor manufacturing and research fabs

A system for processing substrates is provided, comprising: a wafer transport assembly that is configured to transport wafers to and from one or more process modules, the wafer transport assembly having at least one wafer transport module, wherein lateral sides of the at least one wafer transport module are configured to couple to the one or more process modules; a service floor defined below the wafer transport assembly, the service floor being defined at a height that is less than a height of a fabrication facility floor in which the system is disposed.. .
Lam Research Corporation

Semiconductor device leadframe

For so called film assisted moulding (fam) device processing techniques there is provided lead frame for a semiconductor device, comprising a base portion and a connection lead, said base portion arranged for mounting a semiconductor die, said connection lead comprising a horizontal portion for external connection and an angled portion for connection to said semiconductor die, wherein the angled portion has a positive angle with respect to the base portion. The connection lead may comprise a recessed portion..
Ampleon Netherlands B.v.

Semiconductor device manufacturing method

A pressing unit including a pressing pin is attached to a mold, a semiconductor chip, first and second heat sinks, and solders are disposed in a cavity of the mold, a mold closing state is made, and a reflow is carried out in a state where the first and second heat sinks are pressed against first and second wall surfaces by the pressing pin to form a laminated body. After the laminated body is formed, the pressing pin is pulled out from the cavity, and a resin molded body is formed by injecting a resin..
Denso Corporation

Manufacturing semiconductor device

A semiconductor device including an oxide conductor with high conductivity and high transmittance is provided. A manufacturing method for a semiconductor device includes the steps of: forming an oxide semiconductor over a first insulator; forming a second insulator over the first insulator and the oxide semiconductor; forming a first conductor over the second insulator; forming an etching mask over the first conductor; forming a second conductor including a region overlapping with the oxide semiconductor by etching the first conductor with use of the etching mask as a mask; removing the etching mask; and performing heat treatment after forming a hydrogen-containing layer over the second insulator and the second conductor..
Semiconductor Energy Laboratory Co., Ltd.

Methods for forming semiconductor devices

A method for forming a semiconductor device includes etching, in a masked etching process, through a layer stack located on a surface of a semiconductor substrate to expose the semiconductor substrate at unmasked regions of the layer stack. The method further includes etching, in a selective etching process, at least a first layer of the layer stack located adjacently to the semiconductor substrate.
Infineon Technologies Austria Ag

Local semiconductor wafer thinning

A local thinning process is employed on the backside of a semiconductor substrate such as a wafer in order to improve the thermal performance of the electronic device built on or in the front side of the wafer.. .
Vishay General Semiconductor Llc

Method of fabricating semiconductor device

Methods for fabricating semiconductor devices include forming a fin-type pattern protruding on a substrate, forming a gate electrode intersecting the fin-type pattern, forming a first recess adjacent to the gate electrode and within the fin-type pattern by using dry etching, forming a second recess by treating a surface of the first recess with a surface treatment process including a deposit process and an etch process, and forming an epitaxial pattern in the second recess.. .
Samsung Electronics Co., Ltd.

Semiconductor manufacturing apparatus and manufacturing semiconductor device

According to one embodiment, a semiconductor manufacturing apparatus includes a chamber, a stage, and first gas injector. The chamber is configured to contain a wafer.
Kabushiki Kaisha Toshiba

Method of fabricating semiconductor device

Provided is a method of fabricating a semiconductor device. In the method, a double patterning technology is used to form various patterns with different widths..
Samsung Electronics Co., Ltd.

Semiconductor forming a semiconductor device

A method for forming a semiconductor device includes implanting doping ions into a semiconductor substrate. A deviation between a main direction of a doping ion beam implanting the doping ions and a main crystal direction of the semiconductor substrate is less than ±0.5° during the implanting of the doping ions into the semiconductor substrate.
Infineon Technologies Ag

Orientation layer for directed self-assembly patterning process

Disclosed is a method of forming a semiconductor device using a self-assembly (dsa) patterning process. The method includes forming a patterned feature over a substrate; applying an orientation material that includes a first polymer and a second polymer over the substrate, wherein the first polymer has a first activation energy and the second polymer has a second activation energy; baking the substrate at first temperature thereby forming a first orientation layer that includes the first polymer; baking the substrate at second temperature thereby forming a second orientation layer that includes the second polymer; and performing a directed self-assembly (dsa) process over the first and the second orientation layers..
Taiwan Semiconductor Manufacturing Company, Ltd.

Chemical vapor deposition manufacturing semiconductor device using the same

A method for manufacturing a semiconductor device includes forming a transistor on a substrate. Precursor gases are provided from a showerhead of a chemical vapor deposition (cvd) apparatus to form a contact etch stop layer (cesl) to cover the transistor and the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Post-cmp hybrid wafer cleaning technique

A brush-cleaning apparatus is disclosed for use in cleaning a semiconductor wafer after polishing. Embodiments of the brush-cleaning apparatus implemented with a multi-branch chemical dispensing unit are applied beneficially to clean semiconductor wafers, post-polish, using a hybrid cleaning method.
Stmicroelectronics, Inc.

Method of cleaning substrate and fabricating semiconductor device using the same

A method of cleaning a substrate includes providing the substrate, the substrate including a metal material film, performing physical cleaning of the substrate, performing chemical cleaning of the substrate, and drying a surface of the substrate. Performing the chemical cleaning includes supplying a chemical cleaning solution including an anionic surfactant at a concentration that is equal to or greater than a critical micelle concentration (cmc) onto the surface of the substrate..
Samsung Electronics Co., Ltd.

Apparatus of processing semiconductor substrate

An apparatus of processing a semiconductor substrate include a chuck, a holder, a liquid supplying system and a positive pressure unit. The chuck has a principal surface and at least a hole formed thereon.
Taiwan Semiconductor Manufacturing Co., Ltd.

Oxidation resistant induction devices

Certain embodiments described herein are directed to induction devices comprising an oxidation resistant material. In certain examples, the induction device comprises a coil of wire that is produced from the oxidation resistant material.
Perkinelmer Health Sciences, Inc.

System and treating substrate

Provided are a system and a method for treating a substrate. The substrate treating system may include a process chamber including a body with an open top and a dielectric window hermetically sealing the top of the body from an outside, a supporting unit provided in the process chamber to support a substrate, a gas-supplying unit supplying a process gas into the process chamber, a plasma source provided outside the process chamber to generate plasma from the process gas supplied into the process chamber, and a heating unit heating the dielectric window.
Semes Co., Ltd.

Bulk sintered solid solution ceramic which exhibits fracture toughness and halogen plasma resistance

A bulk, sintered solid solution-comprising ceramic article useful in semiconductor processing, which is resistant to erosion by halogen-containing plasmas and provides advantageous mechanical properties. The solid solution-comprising ceramic article is formed from a combination of yttrium oxide and zirconium oxide.
Applied Materials, Inc.

Plasma processing equipment and plasma generation equipment

A plasma processing equipment includes a vacuum processing chamber, an insulating material, a gas inlet, a high frequency induction antenna provided at an upper outside of the vacuum processing chamber, a magnetic field coil, a yoke for controlling distribution of a magnetic field in the vacuum processing chamber, a high frequency power supply for generating plasma and supplying a high frequency current to the antenna, and a power supply for supplying power to the magnetic field coil. The antenna is divided into n high frequency induction antenna elements are arranged in tandem on one circle so that a high frequency current delayed sequentially by λ (wavelength of high frequency power supply)/n flows clockwise through the antenna elements arranged in tandem via a delay unit, and a magnetic field is applied from the magnetic field coil to generate electron cyclotron resonance (ecr) phenomenon..
Hitachi High-technologies Corporation

Intermodulation-free electrical contact for hf applications

What is provided is an arrangement for electrically contacting electrically conductive elements, comprising a first element, at least a portion of which is electrically conductive, at least one second element, at least a portion of which is electrically conductive, for electrically contacting the first element, comprising a contact area in at least one end region thereof, the contact area having a radius at least at predefined contact points. The first electrically conductive element has at least one area that is designed to receive at least a portion of the contact area of the second electrically conductive element such that an electrical contact is created between the first electrically conductive element and the contact points of the second electrically conductive element.
Kathrein Werke Kg

Reflective conductive composite film

A reflective conductive film includes (i) a reflective polymeric substrate having a polymeric base layer and a polymeric binding layer, wherein the polymeric material of the base layer has a softening temperature ts-b, and the polymeric material of the binding layer has a softening temperature ts-hs; and (ii) a conductive layer that includes a plurality of nanowires, wherein the nanowires are bound by the polymeric matrix of the binding layer such that the nanowires are dispersed at least partially in the polymeric matrix of the binding layer, wherein the polymeric substrate is a biaxially oriented substrate, and wherein the polymeric binding layer is a copolyester.. .
Dupont Teijin Films U.s. Limited Partnership

Electrical conductors, production methods thereof, and electronic devices including the same

An electrical conductor includes: a first conductive layer including a plurality of ruthenium oxide nanosheets, wherein at least one ruthenium oxide nanosheet of the plurality of ruthenium oxide nanosheets includes a halogen, a chalcogen, a group 15 element, or a combination thereof on a surface of the ruthenium oxide nanosheet.. .
Samsung Electronics Co., Ltd

Semiconductor memory devices and methods of operating the same

A method of operating a semiconductor memory device is provided. In a method of operating a semiconductor memory device including a memory cell array which includes a plurality of bank arrays, memory cells in a first region of the memory cell array are tested to detect one or more failed cells in the first region, a fail address corresponding to the detected one or more failed cells is determined and the determined fail address is stored in a second region different from the first region, in the memory cell array..
Samsung Electronics Co., Ltd.

Semiconductor memory device, testing the same and operating the same

A method of testing a semiconductor memory device is provided. Data is written to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device.
Samsung Electronics Co., Ltd.

Test line patterns in split-gate flash technology

The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, an integrated chip is disclosed.
Taiwan Semiconductor Manufacturing Co., Ltd.

Test line letter for embedded non-volatile memory technology

The present disclosure relates to a substrate having test line letters that are used to identify a test line on an integrated chip, while avoiding contamination of high-k metal gate processes, and a method of formation. In some embodiments, the substrate has a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Nonvolatile semiconductor memory device

A semiconductor memory device includes a memory cell array, a sense amplifier, a register, a controller. The memory cell array includes a memory cell.
Kabushiki Kaisha Toshiba

Method for fabricating semiconductor memory device having integrated dosram and nosram

A method for fabricating a semiconductor memory device is disclosed. A semiconductor substrate having a main surface is prepared.
United Microelectronics Corp.

Semiconductor memory device configured to sense memory cell threshold voltages in ascending order

According to one embodiment, a semiconductor memory device includes first and second memory cells, a word line, first and second bit lines, a sense amplifier and a driver. The first and second memory cells have first and second threshold voltages, respectively.
Kabushiki Kaisha Toshiba

Method and decoding commands

Method and apparatuses for of decoding commands for a semiconductor device are described. An example method includes receiving a portion of a command at first and second clock cycles; validating the portion of the command received at the first and second clock cycles at a third clock cycle when a chip select signal indicates a first state and continuing to receive the remaining portion of the command at the third clock cycle and a fourth clock cycle so that the command can be completely received by the semiconductor device by the fourth clock cycle; and invalidating the portion of the command received at the first and second clock cycles at the third clock cycle when the chip select signal indicates a second state different from the first state, so that a new command can be input to the semiconductor device at the third clock cycle..
Micron Technology, Inc.

Semiconductor devices including reversible and one-time programmable magnetic tunnel junctions

A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (otp) resistance state..

Data sensing circuit and semiconductor apparatus using the same

A data sensing circuit may include a pair of first signal lines, and a pair of second signal lines precharged with a first power supply voltage. The data sensing circuit may also include a line level control block configured for applying a second power supply voltage to any one signal line of the pair of second signal lines in response to a read command..
Sk Hynix Inc.

Semiconductor device having redistribution lines

A semiconductor device includes, a semiconductor chip having a first surface over which bonding pads are positioned, a second surface which faces away from the first surface, and a plurality of signal lines formed over the first surface, extending in a first direction; a plurality of redistribution lines formed over the first surface, having one set of ends electrically coupled to the bonding pads of the semiconductor chip, and extending in a direction oblique to the first direction; and a plurality of redistribution pads disposed over the first surface, and electrically coupled with an other set of ends of the redistribution lines which face away from the one set of ends.. .
Sk Hynix Inc.

Semiconductor chip module and semiconductor package including the same

A semiconductor chip module includes a chip unit including first and second semiconductor chips formed over a single body to be adjacent in a first direction with a scribe line region interposed therebetween, and having a first surface over which bonding pads of the first and second semiconductor chips are positioned; redistribution lines formed over the first surface, having one set of ends which are respectively electrically coupled to the bonding pads, and extending in a direction oblique to the first direction toward the scribe line region; and redistribution pads disposed over the first surface, and electrically coupled with another set of ends of the redistribution lines. The redistribution pads includes shared redistribution pads electrically coupled in common to the redistribution lines electrically coupled to the bonding pads of the first semiconductor chip and the redistribution lines electrically coupled to the bonding pads of the second semiconductor chip; and individual redistribution pads individually electrically coupled to the redistribution lines which are not electrically coupled with the shared redistribution pads..
Sk Hynix Inc.

Semiconductor device and control the same

A semiconductor device includes semiconductor chips stacked each other. Each of the semiconductor chips converts second reception data received by second reception terminals arranged in point symmetry on the first face by a conversion method to convert first reception data received by first reception terminals arranged in point symmetry on the first face into a reference data; and generates an identification information of the each semiconductor chip based upon the converted second reception data; and outputs the bit sequence obtained by converting the generated identification information by means of the inverse conversion method of the conversion method..
Fujitsu Limited

Phoneme-to-grapheme mapping systems and methods

Systems and methods for automatically mapping english phonemes to graphemes to support better reading and spelling instruction may include a mapping process for systematically dividing text words into graphemes made up of one or more text characters corresponding to appropriately identified phonemes (which may be represented by one or more phonetic characters). The process may also include automatically correlating each phoneme of a word with a grapheme representing the phoneme in order to produce a phoneme-to-grapheme map that may be optimized for educational use.
Vkidz, Inc.

Ultrasonic lens for receiver application

An improved ultrasonic lens and associated system is provided. Specifically, there is provided an ultrasonic lens with two sets of parallel sound ports operatively connected to an electrodynamic transducer to extend the working range of both audible and ultrasonic sound signals.
Sound Solutions International Co., Ltd.

Semiconductor integrated circuit, timing controller, and display device

A semiconductor integrated circuit connected to another circuit via differential transmission lines of n channels (where n is a natural number), the circuit includes: n pairs of differential output pins each of which is connected to a differential transmission line of a corresponding channel; n differential transmitters each of which is configured to drive a differential transmission line of a corresponding channel; and an abnormality detection circuit configured to detect abnormality in the differential transmission lines. The abnormality detection circuit includes: n amplifiers configured to detect a potential difference between differential transmission lines of corresponding channels; n first comparators each of which is configured to compare an output voltage of a corresponding amplifier with a first threshold voltage; and a logic circuit configured to detect abnormality of a first mode in a differential transmission line of a corresponding channel based on an output from each of the n first comparators..
Rohm Co., Ltd.





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