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Duc patents

      

This page is updated frequently with new Duc-related patent applications.




Date/App# patent app List of recent Duc-related patents
08/18/16
20160242313 
 Electronic assembly with one or more heat sinks patent thumbnailElectronic assembly with one or more heat sinks
An electronic assembly comprises a semiconductor device that has conductive pads on a semiconductor first side and a metallic region on a semiconductor second side opposite the first side. A lead frame provides respective separate terminals that are electrically and mechanically connected to corresponding conductive pads.
Deere & Company


08/18/16
20160242312 
 Electronic assembly with one or more heat sinks patent thumbnailElectronic assembly with one or more heat sinks
An electronic assembly comprises a semiconductor device that has conductive pads on a semiconductor first side and a metallic region on a semiconductor second side opposite the first side. A lead frame provides respective separate terminals that are electrically and mechanically connected to corresponding conductive pads.
Deere & Company


08/18/16
20160242298 
 Partially depopulated interconnection arrays for packaged semiconductor devices and printed circuit boards patent thumbnailPartially depopulated interconnection arrays for packaged semiconductor devices and printed circuit boards
In one embodiment, a ball grid array (bga) of a packaged semiconductor device and a corresponding landing pad array of a printed circuit board each have a layout defined by an interconnection array having (i) an inner sub-array of locations having connectors arranged in rows and columns separated by a specified pitch and (ii) an outer rectangular ring of locations having connectors arranged in rows and columns separated by the specified pitch. The outer rectangular ring is separated from the inner sub-array by a depopulated rectangular ring having a width of at least twice the specified pitch, wherein the depopulated rectangular ring has no connectors.
Lattice Semiconductor Corporation


08/18/16
20160242294 
 Electronic device patent thumbnailElectronic device
The present disclosure provides an electronic device suitable for miniaturization. The present electronic device includes: a substrate (1), having a main surface (111) and a back surface (112) facing opposite sides with each other in a thickness direction, wherein the substrate comprises a semiconductor material; an electronic component (8), which is disposed over the substrate (1); and a conductive layer (3), which is electrically connected with the electronic component (8); wherein a recess for disposing the component (14) and a through recess (17) are formed in the substrate, in which recess for disposing the component (14) is recessed from the main surface (111), and the through recess (17) penetrates from the recess for disposing the component (14) to the back surface (112); the electronic component (8) is disposed over the recess for disposing the component (14); a metal-filled portion (4) is formed in the through recess (17), wherein the metal-filled portion blocks at least the bottom of the through recess (17) and is filled with a metal material; and the conductive layer (3) is formed at least from the through recess (17) to the back surface (112)..
Rohm Co., Ltd.


08/18/16
20160242292 
 Electronic device patent thumbnailElectronic device
An electronic device includes a semiconductor substrate, an electronic element mounted on the substrate, a conductive layer electrically connected to the electronic element, a sealing resin and a columnar conductor. The substrate has a recess formed in its obverse surface.
Rohm Co., Ltd.


08/18/16
20160242291 
 Printed circuit board patent thumbnailPrinted circuit board
Various embodiments related to a printed circuit board in which a capacitor is embedded are described. The capacitor may include: a plurality of first conductive layers that have a plurality of first via holes; a plurality of second conductive layers that have a plurality of second via holes, wherein the first and second conductive layers are alternately arranged in turns; and a plurality of dielectric layers that are arranged between the first and second conductive layers.
Samsung Electronics Co., Ltd.


08/18/16
20160242283 
 Wiring board, and mounting structure and laminated sheet using the same patent thumbnailWiring board, and mounting structure and laminated sheet using the same
A wiring board excellent in electrical reliability is provided. A wiring board includes a first resin layer; an inorganic insulating layer disposed on the first resin layer; a second resin layer disposed on the inorganic insulating layer; and a conductive layer disposed on the second resin layer.
Kyocera Corporation


08/18/16
20160242281 
 Copper foil with carrier patent thumbnailCopper foil with carrier
Provided is a copper foil for a printed wiring board including a roughened layer on at least one surface thereof. In the roughened layer, the average diameter d1 at the particle bottom being apart from the bottom of each particle by 10% of the particle length is 0.2 to 1.0 μm, and the ratio l1/d1 of the particle length l1 to the average diameter d1 at the particle bottom is 15 or less.
Jx Nippon Mining & Metals Corporation


08/18/16
20160242239 
 Electric induction melting and holding furnaces for reactive metals and alloys patent thumbnailElectric induction melting and holding furnaces for reactive metals and alloys
An electric induction furnace for melting and holding a reactive metal or alloy is provided with an upper furnace vessel, an induction coil positioned below the upper furnace vessel, and a melt-containing vessel positioned inside the induction coil with a gap between the outside surface of the melt-containing vessel and the inside surface of the induction coil that can be used to circulate a cooling fluid for cooling the wall of the melt-containing vessel to inhibit leakage of the reactive metal or alloy melt from the vessel. The melt-containing vessel can be integrated with a cooling system for cooling the melt-containing vessel.
Inductotherm Corp.


08/18/16
20160242238 
 A method and a device for checking an ideal position of a cooking pot above an induction coil of an induction cooking hob patent thumbnailA method and a device for checking an ideal position of a cooking pot above an induction coil of an induction cooking hob
The present invention relates to a method for checking an ideal position of a cooking pot (20) above an induction coil (14) of an induction cooking hob (10), wherein said method includes the following steps: a) starting the method for checking the ideal position, b) detecting a first parameter related to the power of the electromagnetic field and/or to the position of the cooking pot (20) above the induction coil (14), c) detecting a second parameter related to the power of the electromagnetic field and/or to the position of the cooking pot (20) above the induction coil (14), d) comparing the detected first and second parameters with a stored relationship between said first and second parameters and the position of the cooking pot (20) above the induction coil (14), e) determining a deviation of the position of the cooking pot (20) from the ideal position above the induction coil (14), f) performing periodic repetitions of the steps b) to e) after predetermined time, and g) outputting at least one signal corresponding with the deviation of the position of the cooking pot (20) from the ideal position, if said deviation exceeds a minimum value. Further, the present invention relates to an induction cooking hob (10) including a system for checking an ideal position of a cooking pot (20) above an induction coil (14) of said induction cooking hob (10)..
Electrolux Appliances Aktiebolag


08/18/16
20160242237 

Heating device and biochemical reactor having the same


The present disclosure relates to a heating device and a biochemical reactor having the heating device. The heating device includes an upper plate, a lower plate, a middle plate, and an electric heating element.
Genereach Biotechnology Corp.


08/18/16
20160242209 

Nfc collision avoidance with controllable nfc transmission delay timing


A first near field communication (nfc) circuit includes an antenna, a charging circuit, a transceiver circuit, and a transmission delay circuit. The antenna is configured to inductively couple to signals emitted by a second nfc circuit.
Sony Corporation


08/18/16
20160242024 

Purposed device management platform


A purposed-device management platform monitors a network of mobile devices dedicated to a single purpose. The single purpose may be to function as a point-of-sale terminal at a retail shop or a plurality of retail shops or for other purposes, such as customer service, digital signage security, resource management, testing and an educational function.
Moki Mobility, Inc.


08/18/16
20160241979 

Monolithic complementary metal-oxide semiconductor (cmos) - integrated silicon microphone


Some embodiments relate to a manufacturing process that combines a mems capacitor of a microelectromechanical systems (mems) microphone and an integrated circuit (ic) onto a single substrate. A dielectric is formed over a device substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/18/16
20160241965 

Mems microphone and forming the same


A micro-electro-mechanical system (mems) microphone and a method for forming the same are provided. The method includes: providing a first substrate including a first surface and a second surface opposite to each other; providing a second substrate including a third surface and a fourth surface opposite to each other; bonding the first surface of the first substrate and the third surface of the second substrate to each other; removing a second base of the second substrate to form a fifth surface opposite to the third surface of the second substrate; forming a cavity between the first substrate and the sensitive region of the second substrate; and forming a first conductive plug from the side of the fifth surface of the second substrate, with the first conductive plug passing through to at least one of the conductive layers..
Memsen Electronics Inc


08/18/16
20160241958 

Microphone arrangement


The present invention relates to a microphone arrangement (m) which has a charge pump (lp), which produces a dc voltage, a transducer (wa), which converts acoustic signals into electrical signals and which is connected to the charge pump (lp), and a control unit (vclfs), which controls the charge pump (lp) and which adjusts the dc voltage produced by the charge pump (lp).. .
Epcos Ag


08/18/16
20160241956 

Digital electronic interface circuit for an acoustic transducer, and corresponding acoustic transducer system


A interface circuit for an acoustic transducer provided with a first detection structure and a second detection structure has: a first input and a second input; a first processing path and a second processing path coupled, respectively, to the first input and second input and supply a first processed signal and a second processed signal; and a recombination stage, which supplies a mixed signal by combining the first processed signal and the second processed signal with a respective weight that is a function of a first level value of the first processed signal. The first and second inputs receive a respective detection signal associated, respectively, to the first detection structure and to the second detection structure of the acoustic transducer; and an output stage the first processed signal, the second processed signal or the mixed signal, on the basis of a second level value of the first processed signal..
Stmicroelectronics S.r.l.


08/18/16
20160241950 

Sound transducer acoustic back cavity system


An apparatus including a housing member and an airflow spreader. The housing member includes an acoustic back cavity for a sound transducer and at least two second cavities in the housing member spaced from the acoustic back cavity.
Nokia Corporation


08/18/16
20160241947 

Method and system for audio sharing


The present invention provide a method and system of audio sharing aimed to revolutionize the way people listen and share music and to give multiple uses to a wireless headphone referred to as hedphone. A communication protocol referred to as hedtech protocol is used in a hed system to allow users to share music amongst a plurality of hedphones while using a single audio source.

08/18/16
20160241943 

System and a transducer interface


According to an embodiment, an interface circuit includes a current replicator and a receiver. The current replicator includes a power terminal coupled to a first reference node, an output terminal configured to output a signal proportional to a signal received from a transducer, and an interface terminal coupled to the transducer.
Infineon Technologies Ag


08/18/16
20160241925 

Transmission method, reception method, transmission apparatus, and reception apparatus


A transmission method includes generating one or more frames for content transfer using ip (internet protocol) packets, and transmitting the one or more generated frames by broadcast. Each of the one or more frames contains a plurality of second transfer units, each of the plurality of second transfer units contains one or more first transfer units, and each of the one or more first transfer units contains at least one of the ip packets.
Panasonic Intellectual Property Corporation Of America


08/18/16
20160241294 

Switched-mode power supply with switch resizing


Switched-mode power supply with switch resizing. A power converter can include an inductor coupled between an input node and an intermediate node, a semiconductor device coupled between the intermediate node and an output node, and a plurality of drive transistors.
Skyworks Solutions, Inc.


08/18/16
20160241255 

Semiconductor device, electronic component, and electronic device


A semiconductor device with a novel structure. An upper-bit grayscale voltage and a lower-bit grayscale voltage are separately produced, and then the grayscale voltages are converted into currents and the currents are synthesized.
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160241242 

Drive unit


A drive unit includes a reverse conducting transistor including a transistor and a first diode being connected in inverse-parallel to the transistor, the transistor and the first diode being provided on a common semiconductor substrate; a second diode including a cathode being connected to a collector of the transistor the second diode being provided on the semiconductor substrate; and a detection portion configured to detect a voltage between the collector and an emitter of the transistor via an anode of the second diode.. .
Toyota Jidosha Kabushiki Kaisha


08/18/16
20160241239 

Semiconductor chip


According to one embodiment, a chip has a circuit with at least one p channel field effect transistor (fet); at least one n channel fet; a first and a second power supply terminal; wherein the n channel fet, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the p channel fet; and the p channel fet, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the n channel fet; wherein the logic state of the gate of the p channel fet and of the n channel fet can only be changed by at least one of the first and second supply voltage to the circuit; and a connection coupled to the gate of the p channel fet or the n channel fet and a further component of the semiconductor chip.. .
Infineon Technologies Ag


08/18/16
20160241235 

Transmission circuit and semiconductor integrated circuit


A transmission circuit includes a driver circuit that includes: a first transistor to regulate output impedance, and a switching circuit that is connected to the first transistor and switches an output polarity for differential output; and a bias circuit that includes: a first replica circuit including a second transistor corresponding to the first transistor, the bias circuit generating a gate voltage so as to make a current-voltage characteristic of the first transistor correspond to a first output impedance value, and supply the gate voltage to a gate of the first transistor.. .
Socionext Inc.


08/18/16
20160241230 

Control circuit and control turning on a power semiconductor switch


A control circuit for turning on a power semiconductor switch comprises an input which is configured to receive a signal that characterizes the switch-on behavior of the power semiconductor switch, a variable current source which is configured to supply a current with a variable level to a control input of the power semiconductor switch in order to switch on the power semiconductor switch, wherein the control circuit is configured to control the variable current source in a closed control loop in response to the signal that characterizes the switch-on behavior of the power semiconductor switch.. .
Power Integrations Switzerland Gmbh


08/18/16
20160241227 

Semiconductor switching element driver circuit


A driver circuit 101 is connected to a control terminal of a semiconductor switching element 1. The driver circuit 101 includes an input circuit 3 connected to an input terminal 50, and an output control circuit 4 connected to the input circuit 3.
Mitsubishi Electric Corporation


08/18/16
20160241218 

Semiconductor device


In a semiconductor device, a charge pump operates in accordance with a clock signal and thereby generates a boosted voltage of a polarity which is the same as or reverse to the polarity of an input voltage. An oscillation circuit generates and outputs a clock signal.
Renesas Electronics Corporation


08/18/16
20160241196 

Multi-band device having multiple miniaturized single-band power amplifiers


Multi-band device having multiple miniaturized single-band power amplifiers. In some embodiments, a power amplifier die can include a semiconductor substrate, and a plurality of power amplifiers (pas) implemented on the semiconductor substrate.
Skyworks Solutions, Inc.


08/18/16
20160241190 

Oscillation circuit, oscillator, electronic apparatus and moving object


An oscillation circuit includes a circuit for oscillation that oscillates a resonator, an output circuit that has a signal, output from the circuit for oscillation, input thereto to thereby output an oscillation signal, a connection terminal to which power is applied, a first wiring that connects from the connection terminal to the output circuit, and a second wiring that is connected to the first wiring through a connection node provided on the first wiring and connects from the connection node to the circuit for oscillation. The circuit for oscillation, the output circuit, the connection terminal, the first wiring, and the second wiring are provided on a semiconductor substrate.
Seiko Epson Corporation


08/18/16
20160241186 

Stress compensated oscillator circuitry and integrated circuit using the same


A stress compensated oscillator circuitry comprises a sensor arrangement for providing a sensor output signal ssensor, wherein the sensor output signal ssensor is based on an instantaneous stress or strain component σ in the semiconductor substrate, a processing arrangement for processing the sensor output signal ssensor and providing a control signal scontrol depending on the instantaneous stress or strain component σ in the semiconductor substrate, and an oscillator arrangement for providing an oscillator output signal sosc having an oscillator frequency fosc based on the control signal scontrol, wherein the control signal scontrol controls the oscillator output signal sosc, and wherein the control signal scontrol reduces the influence of the instantaneous stress or strain component σ in the semiconductor substrate onto the oscillator output signal sosc, so that the oscillator circuitry provides a stress compensated oscillator output signal.. .
Infineon Technologies Ag


08/18/16
20160241168 

Thermal energy harvesting device


A first closed enclosure defines a cavity having an inner dimension smaller than 5 mm. At least one second resiliently deformable closed enclosure is connected in fluid communication with the first enclosure.
Socpra Sciences Et Génie S.e.c.


08/18/16
20160241161 

Converting circuit


A current converter circuit arrangement, and a current converter device embodying such arrangement, having positive and negative potential voltage connections, a neutral connection, an ac voltage connection, and first and second inductances. The arrangement further has at least six power semiconductor switches, to each of which a diode is electrically connected back-to-back in parallel, and two further diodes, for a total of eight.
Semikron Elektronik Gmbh & Co., Kg


08/18/16
20160241159 

Resonant type high frequency power supply device


A resonant type high frequency power supply device provided with a power semiconductor element that performs a switching operation at a high frequency exceeding 2 mhz, the resonant type high frequency power supply device including a resonance matched filter that controls both the waveform of a switching voltage of the power semiconductor element and the waveform of an output voltage.. .
Mitsubishi Electric Engineering Company, Limited


08/18/16
20160241156 

Power conversion apparatus


A power converter of a power conversion apparatus includes any one or more of a functional module in which a rectifier unit rectifying an externally supplied alternating-current voltage and an inverter unit converting a direct-current voltage into alternating-current power are combined, a functional module in which a converter unit converting an alternating-current voltage into a direct-current voltage and an inverter unit converting a direct-current voltage converted by the converter unit into alternating-current power are combined, and a functional module in which an inverter unit converting a direct-current voltage into alternating-current power is provided. The functional module has a cooler cooling a semiconductor component..
Mitsubishi Electric Corporation


08/18/16
20160241136 

Power unit and power conversion apparatus


To reduce radiation noise generated when a semiconductor device in a power unit performs switching, a core is provided outside the power unit. The closer the core is disposed to the semiconductor device that is generating the radiation noise, the greater the effect of reducing the radiation noise is obtained.
Mitsubishi Electric Corporation


08/18/16
20160241119 

Vibration component that harvests energy for electronic devices


An energy harvesting component for use in a portable electronic device includes a housing, a mass element within the housing, an energy transducer positioned inductively proximate the mass element, and a coupling between the mass element and the housing. In a first mode, the energy harvesting component may convert mechanical energy from agitation of the portable electronic device to electrical energy for use by the electronic device and, in a second mode, the energy harvesting component may induce movement of the mass element to provide haptic feedback..
Apple Inc.


08/18/16
20160241018 

Semiconductor device and semiconductor module


The semiconductor device of the present invention includes a semiconductor substrate, a switching element which is defined on the semiconductor substrate, and a temperature sense element which is provided on the surface of the semiconductor substrate independently from the switching element and characterized by being dependent on a temperature.. .
Rohm Co., Ltd.


08/18/16
20160240868 

Bipolar plate design with non-conductive picture frame


The present inventions are directed to fluid flow assemblies, and systems incorporating such assemblies, each assembly comprising a conductive element disposed within a non-conductive element; the non-conductive element being characterized as framing the conductive central element and the elements together defining a substantially planar surface when engaged with one another; each of the conductive and non-conductive elements comprising channels which, when taken together, form a flow pattern on the substantially planar surface; and wherein the channels are restricted, terminated, or both restricted and terminated in the non-conductive element.. .
Lockheed Martin Advanced Energy Storage, Llc


08/18/16
20160240865 

Corrosion resistant metal bipolar plate for a pemfc including a radical scavenger


The present disclosure includes fuel cell bipolar plates and methods of forming a radical scavenging coating on a bipolar plate. The bipolar plates may include a steel substrate, a middle layer contacting the steel substrate and including a bulk material and a radical scavenging material, and a conductive layer contacting the middle layer.
Ford Global Technologies, Llc


08/18/16
20160240840 

Alkali metal-sulfur secondary battery containing a pre-sulfurized cathode and production process


A method of producing a pre-sulfurized active cathode layer for a rechargeable alkali metal-sulfur cell; the method comprising: (a) preparing an integral layer of meso-porous structure of a carbon, graphite, metal, or conductive polymer having a specific surface area greater than 100 m2/g; (b) preparing an electrolyte comprising a solvent and a sulfur source; (c) preparing an anode; and (d) bringing the integral layer and the anode in ionic contact with the electrolyte and imposing an electric current between the anode and the integral layer (serving as a cathode) to electrochemically deposit nano-scaled sulfur particles or coating on the graphene surfaces. The sulfur particles or coating have a thickness or diameter smaller than 20 nm (preferably <10 nm, more preferably <5 nm or even <3 nm) and occupy a weight fraction of at least 70% (preferably >90% or even >95%)..

08/18/16
20160240821 

Frequency dependent light emitting devices


An electroluminescent device described herein, in one aspect, comprises a first electrode and second electrode and a light emitting layer positioned between the first and second electrodes. A current injection gate is positioned between the first electrode and the light emitting layer or the second electrode and the light emitting layer.
Wake Forest University


08/18/16
20160240816 


The laminate includes an organic semiconductor film, a protective film on the organic semiconductor film, and a resist film on the protective film, in which the resist film is formed of a photosensitive resin composition that contains a photoacid generator (a) which generates an organic acid of which a pka of the generated acid is −1 or less and a resin (b) which reacts with an acid generated by the photoacid generator so that the rate of dissolution in a developer containing an organic solvent is decreased.. .

08/18/16
20160240804 

Coating material for forming semiconductors, semiconductor thin film, thin film solar cell and manufacturing thin film solar cell


The present invention aims to provide a coating liquid for forming a semiconductor which facilitates large-area production of a semiconductor that is useful as a semiconductor material of a solar cell with high conversion efficiency and small variation in the conversion efficiency, and enables control of the film thickness. The present invention also aims to provide a semiconductor thin film produced from the coating liquid for forming a semiconductor, a thin film solar cell, and a method for producing the thin film solar cell.
Sekisui Chemical Co., Ltd.


08/18/16
20160240803 

Printable nanoparticle conductor ink with improved charge injection


A transistor has a substrate, source and drain electrodes on the substrate, the source and drain electrodes formed of a conductor ink having silver nanoparticles with integrated dipolar surfactants, an organic semiconductor forming a channel between the source and drain electrodes, the organic semiconductor in contact with the source and drain electrodes, a gate dielectric layer having a first surface in contact with the organic semiconductor, and a gate electrode in contact with a second surface of the gate dielectric layer, the gate electrode formed of silver nanoparticles with integrated dipolar surfactants.. .
Palo Alto Research Center Incorporated


08/18/16
20160240789 

Perylene-based semiconductors


The present invention relates to new semiconductor materials prepared from perylene-based compounds. Such compounds can exhibit high carrier mobility and/or good current modulation characteristics.
Polyera Corporation


08/18/16
20160240786 

Methods and compositions for enhancing processability and charge transport of polymer semiconductors and devices made therefrom


Methods of making solid-state semiconducting films. The methods include forming a mixture by mixing at least two monomers in a pre-determined proportion such that at least one of the at least two monomers contains at least one non-conjugation spacer.
Purdue Research Foundation


08/18/16
20160240781 

Organic semiconductor doping process


The present invention relates to the doping of organic semiconductors and processes for producing layers of p-doped organic semiconductors. Disclosed is a process for p-doping organic semiconductors comprising treating the organic semiconductor with an oxidised salt of the organic semiconductor.
Isis Innovation Limited


08/18/16
20160240775 

Semiconductor structure with data storage structure and manufacturing the same


A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/18/16
20160240774 

Semiconductor device and producing the same


A memory device includes memory elements arranged in two or more rows and two or more columns. Each memory element includes a pillar-shaped insulator layer, a phase change film around an upper portion of the pillar-shaped insulator layer, a lower electrode formed around a lower portion of the pillar-shaped insulator layer and connected to the phase change film, a reset gate insulating film surrounding the phase change film, and a reset gate surrounding the reset gate insulating film.
Unisantis Electronics Singapore Pte. Ltd.


08/18/16
20160240761 

Thermoelectric device


A thermoelectric device includes a semiconductor stacked thin film including a sige layer and a si layer in contact with the sige layer. The sige has a si:ge composition ratio by atomic number ratio within a range of 85:15 to 63:37.
Tdk Corporation


08/18/16
20160240758 

Light emitting diode


Provided is a light emitting diode (led) mounted on a carrier substrate and including a semiconductor epitaxial structure and at least one electrode pad structure. The semiconductor epitaxial structure is electrically connected to the carrier substrate.
Genesis Photonics Inc.


08/18/16
20160240757 

Light-emitting element


A light-emitting element includes a semiconductor stacked body, a light transmissive conductive film disposed on the semiconductor stacked body, the light transmissive conductive film including a plurality of through holes, insulation films disposed in the plurality of through holes, the plurality of through holes being disposed on the semiconductor stacked body; and a pad electrode disposed on the light transmissive conductive film and the insulation films.. .
Nichia Corporation


08/18/16
20160240756 

Optoelectronic component and producing same


An optoelectronic component includes a housing including a plastic material and a first lead frame section at least partly embedded in the plastic material, a first recess and a second recess, wherein a first upper section of an upper side of the first lead frame section is not covered by the plastic material in the first recess, a second upper section of the upper side of the first lead frame section is not covered by the plastic material in the second recess, the first recess and the second recess are separated from one another by a section of the plastic material, an optoelectronic semiconductor chip is arranged in the first recess, and no optoelectronic semiconductor chips is arranged in the second recess.. .
Osram Opto Semiconductors Gmbh


08/18/16
20160240753 

Film-like thermosetting silicone sealing material


The present invention relates to a film-like thermosetting silicone sealing material for sealing a semiconductor element by means of compression molding, the sealing material having an initial torque value of less than 15 dn·m as measured by an mdr (moving die rheometer) at a molding temperature of from room temperature to 200° c., to a method for producing an led by means of compression molding using the same, and to an led produced by this method. The sealing material has excellent moldability, causes no problems such as overflow from a die, and has no defects such as voids..
Dow Corning Toray Co., Ltd.


08/18/16
20160240746 

Semiconductor light-emitting device


A semiconductor light-emitting device includes: a package substrate having a mounting surface on which a first circuit pattern and a second circuit pattern are disposed; a semiconductor led chip mounted on the mounting surface, having a first surface which faces the mounting surface and on which a first electrode and a second electrode are disposed, a second surface opposing the first surface, and side surfaces located between the first surface and the second surface, the first electrode and the second electrode being connected to the first circuit pattern and the second circuit pattern, respectively; a wavelength conversion film disposed on the second surface; and a side surface inclined portion disposed on the side surfaces of the semiconductor led chip, providing inclined surfaces, and including a light-transmitting resin containing a wavelength conversion material.. .
Samsung Electronics Co., Ltd.


08/18/16
20160240744 

Light emitting diode having distributed bragg reflectors (dbr) and manufacturing method thereof


A light emitting diode (led) having distributed bragg reflector (dbr) and a manufacturing method thereof are provided. The distributed bragg reflector is used as a reflective element for reflecting the light generated by the light emitting layer to an ideal direction of light output.
Genesis Photonics Inc.


08/18/16
20160240742 

Method of manufacturing light emitting element


A method of manufacturing a semiconductor light emitting element includes providing a semiconductor stacked layer body; forming an insulating layer on a portion of the semiconductor stacked layer body; forming a light-transmissive electrode covering an upper surface of the semiconductor stacked layer body and an upper surface of the insulating layer, and on a region at least partially overlapping a region for disposing an extending portion in a plan view; forming a light reflecting layer in each of the openings of the light-transmissive electrode; forming a protective layer on a main surface side of the semiconductor stacked layer body; forming a mask on an upper surface of the protective layer except for the region for forming the pad electrode; etching the protective layer to form an opening in the protective layer; and forming a pad electrode in the opening of the protective layer.. .
Nichia Corporation


08/18/16
20160240741 

Light emitting component


A light emitting component includes an epitaxial structure, a first electrode, a conducting layer and a second electrode. The epitaxial structure includes a substrate, a first semiconductor layer, a light emitting layer and a second semiconductor layer.
Genesis Photonics Inc.


08/18/16
20160240739 

Patterned substrate design for layer growth


A patterned surface for improving the growth of semiconductor layers, such as group iii nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings.
Sensor Electronic Technology, Inc.


08/18/16
20160240738 

Light-emitting element


A light-emitting element includes: a sapphire substrate having a c-plane at a main surface thereof; and a semiconductor layer provided at the main surface side of the sapphire substrate. The sapphire substrate includes a first unit including a first region, a second region, and a third region, wherein, when viewed from the main surface side, the three regions together have a shape of a regular hexagon that is evenly divided into the three regions such that each region has a shape of a rhombus; and a plurality of second units disposed to be aligned with each side of the first unit, the second unit having mirror symmetry relative to the first unit.
Nichia Corporation


08/18/16
20160240737 

Light-emitting device and production method therefor


The present invention provides a light-emitting device exhibiting improved light extraction performance. The light-emitting device is of a flip-chip type wherein a group iii nitride semiconductor layer is disposed on one surface of a gan substrate, light is extracted from a rear surface of the substrate (the other surface of the substrate), and an uneven structure is formed on the rear surface of the substrate.
Toyoda Gosei Co., Ltd.


08/18/16
20160240736 

Semiconductor chip and separating a composite into semiconductor chips


The invention concerns a semiconductor chip (100) with a semiconductor body (2) having a semiconductor layer sequence, and with a substrate body (4) and at least one upper side contact (8). In projection the semiconductor chip (100) has a shape which deviates from a rectangular shape.
Osram Opto Semiconductors Gmbh


08/18/16
20160240735 

Top emitting semiconductor light emitting device


Embodiments of the invention include a semiconductor structure including a light emitting layer sandwiched between an n-type region and a p-type region. A growth substrate is attached to the semiconductor structure.
Koninklijke Philips N.v.


08/18/16
20160240734 

Optoelectronic semiconductor device


An optoelectronic semiconductor component includes a layer stack based on a nitride compound semiconductor and has an n-type semiconductor region , a p-type semiconductor region and an active layer arranged between the n-type semiconductor region and the p-type semiconductor region. In order to form an electron barrier, the p-type semiconductor region includes a layer sequence having a plurality of p-doped layers composed of alxinga1-x-yn where 0<=x<=1, 0<=y<=1 and x+y<=1.
Osram Opto Semiconductors Gmbh


08/18/16
20160240733 

Semiconductor light emitting device


A semiconductor light emitting device is provided. The semiconductor light emitting device includes: a support substrate; a first layer disposed on the support substrate and applying tensile stress to the support substrate; a bonding layer disposed on the first layer; a second layer disposed on the bonding layer and applying compressive stress to the support substrate; and a light emitting structure disposed on the second layer and including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer..

08/18/16
20160240732 

Light emitting component


A light emitting component includes an epitaxial structure, an adhesive layer, a first reflective layer, a second reflective layer, a block layer, a first electrode and a second electrode. The epitaxial structure includes a substrate, a first semiconductor layer, a light emitting layer and a second semiconductor layer.
Genesis Photonics Inc.


08/18/16
20160240731 

Light-emitting diode


A light-emitting diode, comprises an active layer for emitting a light with a phase and a peak wavelength λ in air, a reflector, a lower semiconductor stack between the active layer and the reflector, wherein the lower semiconductor stack comprises multiple semiconductor layers, and each of the multiple semiconductor layers has a refractive index ni, a thickness di and two sides each contacting adjacent layers to form two interfaces, wherein each interface has a phase shift when the light passes through the interface.. .
Epistar Corporation


08/18/16
20160240727 

Nitride semiconductor ultraviolet light-emitting element


A nitride semiconductor ultraviolet light-emitting element is provided with: an underlying structure portion including a sapphire (0001) substrate and an aln layer formed on the substrate; and a light-emitting element structure portion including an n-type cladding layer of an n-type algan based semiconductor layer, an active layer having an algan based semiconductor layer, and a p-type cladding layer of a p-type algan based semiconductor layer, formed on the underlying structure portion. The (0001) surface of the substrate is inclined at an off angle which is equal to or greater than 0.6° and is equal to or smaller than 3.0°, and an aln molar fraction of the n-type cladding layer is equal to or higher than 50%..
Soko Kagaku Co., Ltd.


08/18/16
20160240725 

Method of fabricating a solar cell


A method for fabricating a solar cell includes the steps of providing a substrate, forming a transparent conductive layer on a surface of the substrate, forming a plurality of photoresist patterns on the transparent conductive layer, forming a dielectric layer on the photoresist patterns and the transparent conductive layer, in which a part of a sidewall of the photoresist pattern is exposed from the dielectric layer, removing the photoresist patterns and a part of the dielectric layer covering the photoresist pattern so that a plurality of openings are defined in the remaining part of the dielectric layer, and forming plural electrodes in the openings respectively. A solar cell fabricated by the method is also disclosed..
Au Optronics Corporation


08/18/16
20160240724 

Method for producing a solar cell


The invention relates to a method for producing a solar cell (1) from crystalline semiconductor material. In a first surface (3a) of a semiconductor substrate (3), a first doping area (5) is formed by thermally diffusing a first dopant and in the second surface (3b) of the semiconductor substrate, a second doping area (7) is formed by implanting ions and thermally implanting a second dopant..
Ion Beam Services


08/18/16
20160240723 

Anneal techniques for chalcogenide semiconductors


Techniques for precisely controlling the composition of volatile components (such as sulfur (s), selenium (se), and tin (sn)) of chalcogenide semiconductors in real-time—during production of the material are provided. In one aspect, a method for forming a chalcogenide semiconductor material includes providing a s source(s) and a se source(s); heating the s source(s) to form a s-containing vapor; heating the se source(s) to form a se-containing vapor; passing a carrier gas first through the s-containing vapor and then through the se-containing vapor, wherein the s-containing vapor and the se-containing vapor are transported via the carrier gas to a sample; and contacting the s-containing vapor and the se-containing vapor with the sample under conditions sufficient to form the chalcogenide semiconductor material.
International Business Machines Corporation


08/18/16
20160240720 

Improved semiconductor radiation detector


A semiconductor radiation detector device includes a semiconductor substrate. On one surface of the substrate are a mig layer (241) of semiconductor of second conductivity type, a barrier layer (251) of semiconductor of first conductivity type, and pixel dopings of semiconductor of the second conductivity type.

08/18/16
20160240719 

Semiconductor devices comprising 2d-materials and methods of manufacture thereof


Semiconductor devices comprising two-dimensional (2d) materials and methods of manufacture thereof are described. In an embodiment, a method for manufacturing a semiconductor device comprising 2d materials may include: epitaxially forming a first 2d material layer on a substrate; and epitaxially forming a second 2d material layer over the first 2d material layer, the first 2d material layer and the second 2d material layer differing in composition..
National Taiwan University


08/18/16
20160240718 

Double-pass photodiode with embedded reflector


A photodiode, in particular photodiode for data transmission applications, can include a semiconductor substrate, which can also be referred to as a substrate layer, and a first semiconductor layer supported by, for instance arranged on, the semiconductor substrate. The photodiode can further include a second semiconductor layer supported by, for instance arranged on, the first semiconductor layer.
Fci Americas Technology Llc


08/18/16
20160240710 

Photodetection semiconductor device having light receiving element


In order to provide a photodetection semiconductor device including a light receiving element configured to reduce afterimages, a photodiode is formed by a pn junction into a circular shape so that a uniform distance from an end portion of a light receiving element to an electrode serving as a carrier outlet is realized, to thereby enable carriers to be uniformly taken out from all directions.. .
Sii Semiconductor Corporation


08/18/16
20160240709 

Solar cell having three-dimensional p-n junction structure and manufacturing same


The present invention provides a 3-dimensional p-n junction solar cell composed of a base board coated with a back plate on the upper face of the same; a p type semiconductor thin film formed on the top side of the back plate which has a 3-dimensional porous structure and is composed of p type semiconductor crystal grains; a n type buffer layer formed on the surface of the crystal grains of the said p type semiconductor thin film with playing a role of coating the thin film; and a transparent electrode formed on the surface of the crystal grains of the p type semiconductor thin film on which the n type buffer layer is formed. The solar cell of the present invention is a p-n junction solar cell including a 3-dimensional photo catalytic thin film, which can provide an improved photoelectric conversion efficiency, compared with the conventional p-n junction solar cell, owing to the formation of the n-type buffer layer on the surface of the crystal grains of the 3-dimensional p type semiconductor thin film..
Daegu Gyeongbuk Institute Of Science And Technology


08/18/16
20160240708 

Solar cell with a hetero-junction structure and manufacturing the same


A solar cell with a hetero junction structure includes a substrate, a first buffer layer, a second buffer layer, a second n-type amorphous semiconductor layer, a second p-type amorphous semiconductor layer, a first transparent conductive oxide (tco) layer and a second tco layer. A method for manufacturing the aforesaid solar cell includes the steps of forming the first n-type and the first p-type amorphous semiconductor layers respectively on a first surface and a second surface of the substrate, dope-treating the first n-type and the first p-type amorphous semiconductor layers by a gas plasma, and forming a first and a second intrinsic amorphous semiconductor layers respectively on the first n-type and the first p-type amorphous semiconductor layers..
Neo Solar Power Corp.


08/18/16
20160240707 

Photoconducting layered material arrangement, fabricating the photoconducting layered material arrangement, and use of photoconducting layered material arrangement


A photoconducting layered material arrangement for producing or detecting high frequency radiation includes a semiconductor material including an alloy comprised of ingaas, ingaassb, or gasb, with an admixture of al, which material is applied to a suitable support substrate in a manner such that the lattices are suitably adjusted, wherewith the semiconductor material comprised of ingaalas, ingaalassb, or gaalsb has a band gap of more than 1 ev, as a consequence of the admixed proportion of al. The proportion x of al in the semiconductor material inyga1−y−xalxas is between x=0.2 and x=0.35, wherewith the proportion y of in may be between 0.5 and 0.55.
Technische Universität Darmstadt


08/18/16
20160240702 

Solar cell with reduced absorber thickness and reduced back surface recombination


Manufacture of an improved stacked-layered thin film solar cell. The solar cell has reduced absorber thickness and an improved back contact for copper indium gallium selenide solar cells.
International Business Machines Corporation


08/18/16
20160240698 

Semiconductor light receiving device, optical receiver module and manufacturing method thereof


Provided are a semiconductor light receiving device, an optical receiver module, and a manufacturing method thereof in which characteristics of the device are improved when the device has a structure in which a mesa structure including layers formed of a common material is buried by a buried layer. The semiconductor light receiving device includes the mesa structure including the layers formed of a commonmaterial, the layers including an absorbing layer, the mesa structure being buried by the buried layer formed so as to surround side surfaces of the mesa structure.
Oclaro Japan, Inc.


08/18/16
20160240695 

Mos p-n junction diode with enhanced response speed and manufacturing method thereof


A mos p-n junction diode includes a semiconductor substrate, a mask layer, a guard ring, a gate oxide layer, a polysilicon structure, a central conductive layer, a silicon nitride layer, a metal diffusion layer, a channel region, and a metal sputtering layer. For manufacturing the mos p-n junction diode, a mask layer is formed on a semiconductor substrate.
Pfc Device Holdings Ltd


08/18/16
20160240694 

Oxide semiconductor film and semiconductor device


An oxide semiconductor film which has more stable electric conductivity is provided. The oxide semiconductor film comprises a crystalline region.
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160240693 

Semiconductor device and manufacturing method thereof


A transistor having a multi-layer structure of oxide semiconductor layers is provided in which a second oxide semiconductor layer having a crystalline structure including indium zinc oxide is formed over a first oxide semiconductor layer having an amorphous structure, and at least a third oxide semiconductor layer is formed stacked over the second oxide semiconductor layer. The second oxide semiconductor layer mainly serves as a carrier path for the transistor.
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160240690 

Semiconductor device


A semiconductor device in which an increase in oxygen vacancies in an oxide semiconductor layer can be suppressed is provided. A semiconductor device with favorable electrical characteristics is provided.
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160240688 

Thin film transistor, display apparatus including the thin film transistor, and manufacturing the thin film transistor


A thin film transistor includes: a substrate, a semiconductor layer disposed on the substrate, a first gate electrode and a second gate electrode disposed on the semiconductor layer, a gate insulating layer disposed between the semiconductor layer and the first and second gate electrodes and having a first through hole between the first and second gate electrodes and a capping layer covering the first gate electrode and contacting the semiconductor layer via the first through hole. The capping layer includes a conductive material..
Samsung Display Co., Ltd.


08/18/16
20160240686 

Non-volatile memory and fabricating method thereof


A non-volatile memory including the following elements is provided. A first conductive layer and a second conductive layer are disposed on a substrate and separated from each other.
Powerchip Technology Corporation


08/18/16
20160240685 

Semiconductor device and electronic device including the semiconductor device


In a semiconductor device including a transistor, an oxygen release type oxide insulating film is formed in contact with a channel formation region of the transistor. The channel formation region is formed in an oxide semiconductor film.
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160240684 

Semiconductor device and manufacturing the same


A miniaturized transistor, a transistor with low parasitic capacitance, a transistor with high frequency characteristics, or a semiconductor device including the transistor is provided. The semiconductor device includes a first insulator, an oxide semiconductor over the first insulator, a first conductor and a second conductor that are in contact with the oxide semiconductor, a second insulator that is over the first and second conductors and has an opening reaching the oxide semiconductor, a third insulator over the oxide semiconductor and the second insulator, and a fourth conductor over the third insulator.
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160240683 

Semiconductor device and display device including the semiconductor device


To reduce parasitic capacitance in a semiconductor device having a transistor including an oxide semiconductor. The transistor includes a first gate electrode, a first gate insulating film over the first gate electrode, an oxide semiconductor film over the first gate insulating film, and source and drain electrodes electrically connected to the oxide semiconductor film.
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160240682 

Oxide semiconductor film and semiconductor device


To provide a novel oxide semiconductor film. The oxide semiconductor film includes in, m, and zn.
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160240681 

Stacked gate-all-around finfet and ming the same


A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240680 

Semiconductor device having a silicon and germanium material filling a cavity region comprising a notch region formed within a semiconductor substrate


The present invention is directed to semiconductor processes and devices. More specifically, embodiments of the present invention provide a semiconductor device that comprises a shaped cavity formed from two trench structures, and the shaped cavity is filled with silicon and germanium material.
Shanghai Huali Microelectronics Corporation


08/18/16
20160240676 

Reacted conductive gate electrodes and methods of making the same


A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240675 

Structure and transistors with line end extension


A method includes forming an isolation feature in a semiconductor substrate; forming a first fin-like active region and a second fin-like active region in the semiconductor substrate and interposed by the isolation feature; forming a dummy gate stack on the isolation feature, wherein the dummy gate extends to the first fin-like active region from one side and to the second fin-like active region from another side.. .
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240674 

Method for manufacturing semiconductor device with recess, epitaxial growth and diffusion


A semiconductor device including a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate..
Sony Corporation


08/18/16
20160240673 

Methods and doped sige source/drain stressor deposition


A method of manufacturing a semiconductor device includes etching a recess into a substrate and epitaxially growing a source/drain region in the recess. The source/drain region includes a first undoped layer of stressor material lining the recess, a lightly doped layer of stressor material over the first undoped layer, a second undoped layer of stressor material over the lightly doped layer, and a highly doped layer of stressor material over the second undoped layer..
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240672 

Semiconductor devices with shaped cavities for embedding germanium material and manufacturing processes thereof


The present invention is directed to semiconductor processes and devices. More specifically, embodiments of the present invention provide a shaped cavity that this later to be filled with sige material.
Shanghai Huali Microelectronics Corporation


08/18/16
20160240670 

Semiconductor device, related manufacturing method, and related electronic device


A semiconductor device may include the following elements: a first doped region; a second doped region, which contacts the first doped region; a third doped region, which contacts the first doped region; a first dielectric layer, which contacts the above-mentioned doped regions; a first gate member, which is conductive and comprises a first gate portion, a second gate portion, and a third gate portion, wherein the first gate portion contacts the first dielectric layer, wherein the second gate portion is positioned between the first gate portion and the third gate portion, and wherein a width of the second portion is unequal to a width of the third gate portion; a doped portion, which is positioned between the third gate portion and the third doped region; a second gate member; and a second dielectric layer, which is positioned between the third gate portion and the second gate member.. .
Semiconductor Manufacturing International (shanghai) Corporation


08/18/16
20160240669 

System and fabricating high voltage power mosfet


A high voltage power mosfet includes a semiconductor substrate doped by a first conducting type, a source doped by a second conducting type and over the semiconductor substrate, and a drain region doped by the second conducting type and on the semiconductor substrate. One or more drain layers doped by the second conducting type and on the semiconductor substrate span between the body region and the drain region.
Powerwyse, Inc.


08/18/16
20160240668 

Ultra high voltage device


According to an embodiment, a semiconductor device is provided. The device includes: the second region has a greater curvature than the first region.
Taiwan Semiconductor Manufacturing Company Limited


08/18/16
20160240667 

Medium high voltage mosfet device


A semiconductor device includes a medium voltage mosfet having a vertical drain drift region between resurf trenches containing field plates which are electrically coupled to a source electrode of the mosfet. A split gate with a central opening is disposed above the drain drift region between the resurf trenches.
Texas Instruments Incorporated


08/18/16
20160240666 

Semiconductor device and manufacturing method thereof


A device includes a first and a second semiconductor-layer. The second semiconductor-layer is on the first semiconductor-layer, and has a first and a second side-surface.
Kabushiki Kaisha Toshiba


08/18/16
20160240665 

Vertical transistor and local interconnect structure


A first patterned stack and a second patterned stack are formed over a substrate, each of which includes a bottom semiconductor layer, a bottom dielectric spacer layer, a conductive material layer, and a top dielectric spacer layer. Gate dielectrics and vertical semiconductor portions are sequentially formed on each patterned stack.
Sandisk 3d Llc


08/18/16
20160240664 

Semiconductor device


There is provided a semiconductor device having ldmos transistors embedded in a semiconductor substrate to boost source-drain breakdown voltage, with arrangements to prevent fluctuations of element characteristics caused by electric field concentration so that the reliability of the semiconductor device is improved. A trench is formed over the upper surface of a separation insulating film of each ldmos transistor, the trench having a gate electrode partially embedded therein.
Renesas Electronics Corporation


08/18/16
20160240663 

Semiconductor device and fabricating the same


A semiconductor device includes: a semiconductor substrate; a semiconductor layer disposed over the semiconductor layer; a first well region disposed in the semiconductor layer and the semiconductor substrate; a second well region disposed in the semiconductor layer; a first isolation element disposed in the first well region; a second isolation element disposed in the second well region; a gate structure disposed in the semiconductor layer between the first isolation element and the second isolation element; a first doped region disposed in the first well region; and a second doped region disposed in the second well region. The bottom surface of the gate structure is above, below or substantially level with a bottom surface of the first isolation structure..
Vanguard International Semiconductor Corporation


08/18/16
20160240661 

Semiconductor device comprising a transistor array and a termination region and manufacturing such a semiconductor device


A semiconductor device formed in a semiconductor substrate having a first main surface comprises a transistor array and a termination region. The transistor array comprises a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region.

08/18/16
20160240659 

Laterally diffused metal oxide semiconductor device and manufacturing method therefor


An ldmos device, comprising a substrate (202), a gate electrode (211) on the substrate (202), a buried layer area in the substrate (202), and a diffusion layer on the buried layer area, wherein the buried layer area comprises a first buried layer (201) and a second buried layer (203), wherein the conduction types of impurities doped in the first buried layer (201) and the second buried layer (203) are opposite; the diffusion layer comprises a first diffusion area (205) and a second diffusion area (206), wherein the first diffusion area (205) is located on the first buried layer (201) and abuts against the first buried layer (201), and the second diffusion area (206) is located on the second buried layer (203) and abuts against the second buried layer (203); and the conduction types of impurities doped in the first buried layer (201) and the first diffusion area (205) are the same, and the conduction types of impurities doped in the second buried layer (203) and the second diffusion area (206) are the same. Additionally, also disclosed is a manufacturing method for the ldmos device.
Csmc Technologies Fab1 Co., Ltd.


08/18/16
20160240658 

Power integrated devices, electronic devices including the same, and electronic systems including the same


A power integrated device includes a semiconductor layer having first conductivity, a source region and a drain region each having second conductivity and disposed in the semiconductor layer, wherein the source region and the drain region are spaced apart from each other, a first drift region having the second conductivity, disposed in the semiconductor layer, and surrounding the drain region, a second drift region having the second conductivity, disposed in the semiconductor layer, contacting a sidewall of the first drift region, and having an impurity concentration lower than an impurity concentration of the first drift region, a gate insulation layer disposed over a channel region between the source region and the second drift region and extending over the second drift region, a field insulation plate disposed over the second drift region and the first drift region, contacting a sidewall of the gate insulation layer, and having a planar structure, and a gate conductive pattern disposed over the gate insulation layer, wherein the gate conductive pattern extends over the field insulation plate.. .
Sk Hynix Inc.


08/18/16
20160240657 

Semiconductor device having buried layer


A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and formed in the substrate, a drift region formed in the high-voltage well, and a buried layer having the first conductivity type formed below the high-voltage well and vertically aligned with the drift region.. .
Macronix International Co., Ltd.


08/18/16
20160240656 

Silicon carbide semiconductor device and manufacturing the same


A silicon carbide semiconductor device includes a silicon carbide semiconductor layer having a main surface, the main surface of the silicon carbide semiconductor layer being provided with a trench having a closed shape when seen in plan view, the trench including a bottom, a plurality of sidewalls continuous with the bottom, and a sidewall-connecting corner portion at a connection portion between two adjacent sidewalls of the plurality of sidewalls, the silicon carbide semiconductor device further including a gate insulating film covering the bottom and the sidewalls of the trench, and a gate electrode provided on the gate insulating film, between the bottom and an upper end of the trench, the thickness of the gate insulating film at the sidewall-connecting corner portion of the trench being greater than the thickness of the gate insulating film at a portion other than the sidewall-connecting corner portion.. .
Sumitomo Electric Industries, Ltd.


08/18/16
20160240655 

Method for manufacturing silicon carbide semiconductor device


A method for manufacturing a sic semiconductor device includes the steps of: forming an impurity region in a sic layer; forming a first carbon layer on a surface of the sic layer having the impurity region formed therein, by selectively removing silicon from the surface; forming a second carbon layer on the first carbon layer; and heating the sic layer having the first carbon layer and the second carbon layer formed therein.. .
Sumitomo Electric Industries, Ltd.


08/18/16
20160240654 

Semiconductor device manufacturing method and semiconductor device


In order to improve the performance of a semiconductor device, a p type impurity is ion implanted into an area of an n type semiconductor film that is epitaxially grown over a p type semiconductor substrate, and the p type impurity is not ion implanted into an area of the n type semiconductor film, which is adjacent to the area in which the p type impurity is ion implanted. In this way, a p− type drift layer comprised of the area in which the p type impurity is introduced, as well as an n− type semiconductor region comprised of the area in which the p type impurity is not introduced are formed..
Renesas Electronics Corporation


08/18/16
20160240653 

Medium high voltage mosfet device


A semiconductor device includes a medium voltage mosfet having a vertical drain drift region between resurf trenches containing field plates which are electrically coupled to a source electrode of the mosfet. A split gate with a central opening is disposed above the drain drift region between the resurf trenches.
Texas Instruments Incorporated


08/18/16
20160240652 

Finfets with wrap-around silicide and ming the same


A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240651 

Structure and formation finfet device


Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a fin structure over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


08/18/16
20160240650 

Semiconductor structure with extending gate structure and forming the same


A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a fin structure formed over the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


08/18/16
20160240649 

Controlling current or mitigating electromagnetic or radiation interference effects using multiple and different semi-conductive channel regions generating structures


Systems and methods for controlling current or mitigating electromagnetic or radiation interference effects using multiple different semi-conductive channel regions generating structures formed by multiple different semi-conductive electrical current or voltage control structures. One embodiment includes providing a first and second metal oxide semiconductor field effect transistor (mosfet) sections formed on opposite sides of a junction field effect transistor (jfet) such that operation of the jfet modulates or controls current otherwise controlled by an electrical path of the mosfet sections.
The United States Of America As Represented By The Secretary Of The Navy


08/18/16
20160240648 

Semiconductor device and manufacturing the same


A semiconductor device includes a first nitride semiconductor layer formed above a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer, a trench passing through the second nitride semiconductor layer and into the first nitride semiconductor layer, a gate insulation film formed in the trench, and a gate electrode disposed by way of the gate insulation film in an inside of the trench. The corner of the trench between a side wall of the trench and a bottom of the trench includes a rounded shape, and a corner of the gate insulation film in contact with the corner of the trench includes a rounded shape..
Renesas Electronics Corporation


08/18/16
20160240647 

Multi-finger large periphery alinn/aln/gan metal-oxide-semiconductor heterostructure field effect transistors on sapphire substrate


Moshfet devices are provided, along with their methods of fabrication. The moshfet device can include a substrate; a multilayer stack on the substrate; a ultra-thin barrier layer on the multilayer stack, wherein the ultra-thin barrier layer has a thickness of about 0.5 nm to about 10 nm; a dielectric, discontinuous thin film layer on portions of the ultra-thin barrier layer, wherein the dielectric, discontinuous thin film layer comprises sio2; a plurality of source electrodes and drain electrodes formed directly on the ultra-thin barrier layer in an alternating pattern such that the dielectric, discontinuous thin film layer is positioned between adjacent source electrodes and drain electrodes; a plurality of gate electrodes on the dielectric, discontinuous thin film layer; and a gate interconnect electrically connecting the plurality of gate electrodes..
University Of South Carolina


08/18/16
20160240645 

Semiconductor device


In an embodiment, a semiconductor device includes a substrate, a group iii nitride-based semiconductor layer formed on the substrate, a first current electrode and a second current electrode formed on the group iii nitride-based semiconductor layer and spaced from each other, and a control electrode formed on the group iii nitride-based semiconductor layer between the first current electrode and the second current electrode. The control electrode includes at least a middle portion, configured to switch off a channel below the middle portion when a first voltage is applied to the control electrode, and second portions adjoining the middle portion.
Infineon Technologies Austria Ag


08/18/16
20160240644 

Semiconductor devices and a forming a semiconductor device


A semiconductor device includes a first transistor structure including a first transistor body region of a first conductivity type located within a semiconductor substrate. At least part of the first transistor body region is located between a first source/drain region of the first transistor structure and a second source/drain region of the first transistor structure.
Infineon Technologies Ag


08/18/16
20160240643 

Semiconductor device


A switching loss is prevented from being deteriorated by suppressing increase in a gate capacitance due to a cell shrink of an ie type trench gate igbt. A cell formation region is configured of a linear active cell region, a linear hole collector cell region, and a linear inactive cell region between them.
Renesas Electronics Corporation


08/18/16
20160240642 

Semiconductor devices and a forming a semiconductor device


Some embodiments relate to a method for forming a semiconductor device. The method includes forming a source region of a field effect transistor structure in a semiconductor substrate.
Infineon Technologies Ag


08/18/16
20160240641 

Semiconductor device and manufacturing the semiconductor device


A semiconductor device includes: a semiconductor substrate, an upper electrode, a lower electrode and a gate electrode. In the semiconductor substrate, a body region, a pillar region, and a barrier region are formed.
Toyota Jidosha Kabushiki Kaisha


08/18/16
20160240640 

Power semiconductor device


A semiconductor substrate has a first surface and a second surface. A gate electrode has a part buried in a first trench.
Mitsubishi Electric Corporation


08/18/16
20160240639 

Semiconductor device


A semiconductor device includes: metal collector layer on backside, p-type collector layer, n-type field stop layer, n-drift layer and n-type cs layer within the n-drift layer near the top side. Multiple trench structures are formed by polysilicon core and gate oxide layer near the front side.
Changzhou Zhongmin Semi-tech Co. Ltd.


08/18/16
20160240638 

Semiconductor device


Provided is a semiconductor device including a plurality of trenches, including an emitter electrode; a floating layer of a first conduction type provided between adjacent trenches; and a low-dielectric-constant film provided between the floating layer and the emitter electrode, in which a dielectric constant of the low-dielectric-constant film is less than 3.9. Also provided is a semiconductor device further including a gate electrode formed in the trenches, in which capacitance between the gate electrode and the floating layer is greater than capacitance between the emitter electrode and the floating layer..
Fuji Electric Co., Ltd.


08/18/16
20160240637 

Semiconductor device and semiconductor module


In a semiconductor device, an element forming region formed with a semiconductor element for controlling a current is defined on a surface of a semiconductor substrate. A termination region is defined so as to surround the element forming region.
Mitsubishi Electric Corporation


08/18/16
20160240636 

Bipolar junction transistor (bjt) base conductor pullback


Some embodiments are directed to a bipolar junction transistor (bjt) with a collector region formed within a body of a semiconductor substrate, and an emitter region arranged over an upper surface of the semiconductor substrate. The bjt includes a base region arranged over the upper surface of the semiconductor substrate, which vertically separates the emitter and collector regions.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/18/16
20160240635 

Semiconductor device


A semiconductor device includes a first main electrode; a second main electrode; a first semiconductor region of a first conductivity type; a second semiconductor region of the first conductivity type; a third semiconductor region of a second conductivity type arranged between the first semiconductor region and the second semiconductor region; and a depletion layer suppression region arranged inside of the third semiconductor region and being configured to suppress a spread of a depletion layer extending in the third semiconductor region when a reverse bias voltage is applied between the second semiconductor region and the third semiconductor region. The third semiconductor region includes a shortest region where a distance between a first boundary surface and a second boundary surface is shortest, and the shortest region includes a region where the depletion layer suppression region does not exist between the first boundary surface and the second boundary surface..
Toyota Jidosha Kabushiki Kaisha


08/18/16
20160240633 

Semiconductor device


A p-type well is formed in a semiconductor substrate, and an n+-type semiconductor region and a p+-type semiconductor region are formed in the p-type well to be spaced apart from each other. The n+-type semiconductor region is an emitter semiconductor region of a bipolar transistor, and the p-type well and the p+-type semiconductor region are base semiconductor regions of the bipolar transistor.
Renesas Electronics Corporation


08/18/16
20160240632 

Method of manufacturing thin-film transistor substrate


A method of manufacturing a thin-film transistor substrate that includes a thin-film transistor having a semiconductor layer, includes: forming a cumn alloy film (third conductive film) above a substrate; forming a first silicon oxide film (first insulation film) on the cumn alloy film at a first temperature; forming an aluminum oxide film (second insulation film) on the first silicon oxide film; and forming a second silicon oxide film (third insulation film) on the aluminum oxide film at a second temperature higher than the first temperature.. .
Joled Inc.


08/18/16
20160240630 

Semiconductor devices and methods for fabricating the same


The inventive concept relates to a semiconductor device and a method for fabricating the same. The semiconductor device comprises active patterns protruding from a substrate, an interlayer dielectric layer disposed on the substrate and including grooves exposing the active patterns, and gate electrodes in the grooves.

08/18/16
20160240629 

Semiconductor process for forming gates with different pitches and different dimensions


A semiconductor process for forming gates with different pitches includes the following steps. A gate layer is formed on a substrate.
United Microelectronics Corp.


08/18/16
20160240627 

Methods of forming metal silicide layers including dopant segregation


A method of forming a metal silicide layer can include implanting dopants to a first depth below a surface of a semiconductor substrate including an active area. A metal-silicon composite layer can be formed on the semiconductor substrate and the metal-silicon composite layer can be silicided to form the metal silicide layer on the active area..
Samsung Electronics Co., Ltd.


08/18/16
20160240625 

Semiconductor device


The present invention makes it possible to lower the on resistance of a semiconductor element without hindering the function of a diffusion prevention film in a semiconductor device having the semiconductor element that uses a wire in a wiring layer as a gate electrode and has a gate insulation film in an identical layer to the diffusion prevention film. A first wire and a gate electrode are embedded into the surface layer of an insulation layer comprising a first wiring layer.
Renesas Electronics Corporation


08/18/16
20160240624 

Semiconductor devices and methods for manufacturing the same


Semiconductor devices and methods for manufacturing the same are provided. An example method may include: forming a sacrificial gate stack on a substrate; forming a gate spacer on sidewalls of the sacrificial gate stack; forming an interlayer dielectric layer on the substrate and planarizing it to expose the sacrificial gate stack; partially etching back the sacrificial gate stack to form an opening; expanding the resultant opening so that the opening is in a shape whose size gradually increases from a side adjacent to the substrate towards an opposite side away from the substrate; and removing a remaining portion of the sacrificial gate stack and forming a gate stack in a space defined by the gate spacer..
Institute Of Microelectronics, Chinese Academy Of Sciences


08/18/16
20160240621 

Insulating block in a semiconductor trench


A semiconductor device is produced by: creating an opening in a mask formed on a semiconductor body; creating, underneath the opening, a trench in the semiconductor body which has a side wall and a trench bottom; creating, while the mask is on the semiconductor body, an insulating layer covering the trench bottom and the side wall; depositing a spacer layer including a first electrode material on the insulating layer; removing the spacer layer from at least a portion of the insulating layer that covers the trench bottom; filling at least a portion of the trench with an insulating material; removing the part of the insulating material laterally confined by the spacer layer so as to leave an insulating block in the trench; and filling at least a portion of the trench with a second electrode material so as to form an electrode within the trench.. .
Infineon Technologies Austria Ag


08/18/16
20160240620 

Doped zinc oxide and n- doping to reduce junction leakage


A semiconductor device includes a substrate and a p-doped layer including a doped iii-v material on the substrate. An n-doped layer is formed on the p-doped layer, the n-doped layer including a doped iii-v material.
International Business Machines Corporation


08/18/16
20160240619 

Semiconductor device having buried gate structure and fabricating the same


A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer.
Samsung Electronics Co., Ltd.


08/18/16
20160240618 

Depression filling method and processing apparatus


A method of filling a depression of a workpiece is provided. The depression passes through an insulating film and extends up to an inside of a semiconductor substrate.
Tokyo Electron Limited


08/18/16
20160240617 

Group iii-n transistors on nanoscale template structures


A iii-n semiconductor channel is formed on a iii-n transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the iii-n epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness.
Intel Corporation


08/18/16
20160240616 

Nmos and pmos strained devices without relaxed substrates


Techniques and methods related to strained nmos and pmos devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor.. .

08/18/16
20160240615 

Semiconductor device and a forming a semiconductor device


A semiconductor device comprises at least one strip-shaped cell compensation region of a vertical electrical element arrangement, at least one strip-shaped edge compensation region and a bridge structure. The at least one strip-shaped cell compensation regions extends into a semiconductor substrate and comprises a first conductivity type.
Infineon Technologies Austria Ag


08/18/16
20160240614 

Semiconductor device and semiconductor package


A semiconductor device according to an embodiment includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a first electrode, a gate electrode, a third insulating layer, a second electrode, a third electrode, and a fourth electrode. The third insulating layer is provided between the gate electrode and the first semiconductor region, between the gate electrode and the second semiconductor region, and between the gate electrode and the third semiconductor region.
Kabushiki Kaisha Toshiba


08/18/16
20160240613 

Iii-v semiconductor devices with selective oxidation


Embodiments of the present invention provide methods for fabricating a semiconductor device with selective oxidation. One method may include providing a semiconductor substrate including a stack of two semiconductor layers; depositing an insulating material on the semiconductor substrate; forming a set of fins; selectively oxidizing one of the semiconductor layers; forming a dummy gate structure and a set of spacers along the sides of the dummy gate structure; forming a source drain region adjacent to the dummy gate structure; removing the dummy gate structure; and releasing the selectively oxidized semiconductor layer..
International Business Machines Corporation


08/18/16
20160240612 

Non-planar semiconductor device having group iii-v material active region with multi-dielectric gate stack


Non-planar semiconductor devices having group iii-v material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate.

08/18/16
20160240610 

Junction interlayer dielectric for reducing leakage current in semiconductor devices


A semiconductor device includes a substrate and a p-doped layer including a doped iii-v material on the substrate. A dielectric interlayer is formed on the p-doped layer.
International Business Machines Corporation


08/18/16
20160240609 

Semiconductor device structure and forming the same


A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first trench between a first active region and a second active region of the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


08/18/16
20160240607 

Oxide material and semiconductor device


Stable electrical characteristics are given to a transistor and a highly reliable semiconductor device is provided. In addition, an oxide material which enables manufacture of such a semiconductor device is provided.
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160240598 

Organic light-emitting diode display and manufacturing the same


An organic light-emitting diode (oled) display and a method of manufacturing an oled display are disclosed. In one aspect, the display includes a display substrate including a display area and a non-display area surrounding the display area.
Samsung Display Co., Ltd.


08/18/16
20160240586 

Memory device, semiconductor device, and methods for producing memory device and semiconductor device


A memory that includes a memory device having a phase change layer that can be reset by using a reset gate is provided. A memory device includes memory elements arranged in two or more rows and two or more columns.
Unisantis Electronics Singapore Pte. Ltd.


08/18/16
20160240584 

High-performance radiation detectors and methods of fabricating thereof


A method of fabricating a solid state radiation detector method includes mechanically lapping and polishing the first and the second surfaces of a semiconductor wafer using a plurality of lapping and polishing steps. The method also includes growing passivation oxide layers by use of oxygen plasma on the top of the polished first and second surfaces in order to passivate the semiconductor wafer.
Redlen Technologies, Inc.


08/18/16
20160240583 

Cis chips and methods for forming the same


A device includes a semiconductor substrate, an image sensor at a front surface of the semiconductor substrate, and a plurality of dielectric layers over the image sensor. A color filter and a micro lens are disposed over the plurality of dielectric layers and aligned to the image sensor.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240581 

Electromagnetic wave detecting element


The present invention provides an electromagnetic wave detecting element that can suppress occurrence of cracking at a substrate peripheral portion, and occurrence of breakage of lead-out wires. An interlayer insulating film is formed so as to cover tft switches on a substrate.
Fujifilm Corporation


08/18/16
20160240579 

Stacked embedded spad image sensor for attached 3d information


A pixel array includes a plurality of visible light pixels arranged in the pixel array. Each one of the plurality of visible light pixels includes a photosensitive element arranged in a first semiconductor die to detect visible light.
Omnivision Technologies, Inc.


08/18/16
20160240578 

Cmos image sensor structure


A semiconductor device includes a substrate, a logic gate structure, a photosensitive gate structure, a hard mask layer, a first spacer, a first source, a first drain, a second spacer, a second source and a second drain. The logic gate structure and the photosensitive gate structure are disposed on a surface of the substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/18/16
20160240576 

Method of manufacturing semiconductor device


A method of manufacturing a semiconductor device, comprising forming an insulating member on a structure having a height difference, and forming openings in the insulating member, the forming openings including first etching under a condition with a microloading phenomenon and second etching under a condition with a reverse microloading phenomenon, wherein the first etching is stopped before an upper face of the structure is exposed and then the second etching is started.. .
Canon Kabushiki Kaisha


08/18/16
20160240575 

Optical device


The invention provides an optical device. The optical device includes an image capture unit, at least one light emitting device, and a light conductor.
Novatek Microelectronics Corp.


08/18/16
20160240574 

Integrated circuit and image sensing device having metal shielding layer and related fabricating method


An integrated circuit includes a first semiconductor device, a second semiconductor device, and a metal shielding layer. The first semiconductor device includes a first substrate and a first multi-layer structure, and the first substrate supports the first multi-layer structure.
Taiwan Semiconductor Manufacturing Company Ltd.


08/18/16
20160240570 

Dual photodiode image pixels with preferential blooming path


An image sensor with an array of image sensor pixels is provided. Each image sensor pixel may include a set of photodiodes formed in a semiconductor substrate, a color filter structure formed over the set of photodiodes, a microlens formed over the color filter structure, and associated pixel circuitry coupled to the set of photodiodes.
Semiconductor Components Industries, Llc


08/18/16
20160240566 

Semiconductor device


A semiconductor device having a high aperture ratio and including a capacitor capable of increasing the charge capacity is provided. A semiconductor device includes a transistor over a substrate, a first light-transmitting conductive film over the substrate, an oxide insulating film covering the transistor and having an opening over the first light-transmitting conductive film, a nitride insulating film over the oxide insulating film and in contact with the first light-transmitting conductive film in the opening, a second light-transmitting conductive film connected to the transistor and having a depressed portion in the opening, and an organic resin film with which the depressed portion of the second light-transmitting conductive film is filled..
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160240565 

Display backplane and fabricating the same


An organic light emitting display is provided. The organic light emitting display comprises a multi-type thin-film transistor (tft) and an organic light emitting diode.
Lg Display Co., Ltd.


08/18/16
20160240564 

Semiconductor device and semiconductor device manufacturing method


A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view..
Renesas Electronics Corporation


08/18/16
20160240563 

Semiconductor device and fabricating the same


Provided is a semiconductor device. The semiconductor device includes a second semiconductor pattern disposed on the substrate and configured to provide a channel region, and a first semiconductor pattern disposed between the substrate and the second semiconductor pattern, wherein the first semiconductor pattern includes a channel region that is a portion in contact with the second semiconductor pattern and source/drain regions that are portions exposed by the second semiconductor pattern..
Korea Advanced Institute Of Science And Technology


08/18/16
20160240562 

Semiconductor device and manufacturing the same


An object is to provide a display device with high productivity by reducing the number of masks and the number of steps. Another object is to provide a display device with high yield.
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160240561 

Semiconductor light emitting device


According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer. The third semiconductor is provided between the first semiconductor layer and the second semiconductor layer.
Kabushiki Kaisha Toshiba


08/18/16
20160240559 

Thin film transistor substrate and display panel comprising the same


A display panel is provided, which includes a substrate and a first metal layer on the substrate. The first metal layer includes a gate electrode and a gate line connecting to the gate electrode.
Innolux Corporation


08/18/16
20160240558 

Manufacturing array substrate, array substrate and display device


A manufacturing method comprises steps of: forming a metal pattern having a thickness d on a substrate; forming an insulating film layer on the substrate on which the metal pattern is formed, so that the insulating film layer has an overlap region with the metal pattern, an absolute value of a height difference between the overlap region of the insulating film layer and other regions of the insulating film layer being less than the thickness d; and, forming a pattern of a semiconductor layer and a source/drain metal layer on the substrate on which the insulating film layer is formed.. .
Hefei Xinsheng Optoelectronics Technology Co., Ltd.


08/18/16
20160240556 

Nonvolatile semiconductor memory device and manufacturing the same


A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; a tunnel insulating film that is formed on the semiconductor layer and includes a first organic molecular film including first organic molecules each having an alkyl molecular chain as the main chain; a charge storage layer formed on the tunnel insulating film, the charge storage layer being made of an inorganic material; a block insulating film formed on the charge storage layer; and a control gate electrode formed on the block insulating film.. .
Kabushiki Kaisha Toshiba


08/18/16
20160240555 

Three-dimensional (3d) semiconductor devices and methods of fabricating 3d semiconductor devices


A three-dimensional (3d) semiconductor device includes a stack of conductive layers spaced from each other in a vertical direction, the stack having a staircase-shaped section in a connection region, and ends of the conductive layers constituting treads of the staircase-shaped section, respectively. The 3d semiconductor device further includes buffer patterns disposed on and protruding above the respective ends of the conductive layers, an interconnection structure disposed above the stack and including conductive lines, and contact plugs extending vertically between the conductive lines and the buffer patterns and electrically connected to the conductive layers of the stack via the buffer patterns..
Samsung Electronics Co., Ltd.


08/18/16
20160240554 

Non-volatile semiconductor storage device and manufacturing the same


A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer.
Kabushiki Kaisha Toshiba


08/18/16
20160240553 

Nonvolatile memory device and manufacturing the same


A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.. .
Samsung Electronics Co., Ltd.


08/18/16
20160240552 

Semiconductor memory device and manufacturing same


According to one embodiment, a semiconductor memory device includes a substrate; a conductive layer provided on the substrate; a stacked body provided on the conductive layer and including a plurality of electrode layers separately stacked each other; a coupling portion provided in the conductive layer; a semiconductor portion provided integrally in the stacked body and in the coupling portion; a charge storage film provided between the semiconductor portion and the plurality of electrode layers; and an interconnect portion provided integrally in the stacked body and in the conductive layer and extending in a stacking direction of the stacked body. The interconnect portion includes a side surface provided in the conductive layer, and the side surface is in contact with an entire side surface of the semiconductor portion in the coupling portion..
Kabushiki Kaisha Toshiba


08/18/16
20160240551 

Semiconductor structure and manufacturing the same


A semiconductor structure is provided. The semiconductor structure comprises a substrate, stacks, a blocking layer-trapping layer-tunneling layer structure, channel layers, a first insulating material and a dielectric layer.
Macronix International Co., Ltd


08/18/16
20160240550 

Non-volatile memory devices including charge storage layers


A non-volatile memory device includes gate electrodes stacked on a substrate, a semiconductor pattern penetrating the gate electrodes and connected to the substrate, and a charge storage layer between the semiconductor pattern and the gate electrodes. The charge storage layer includes a first charge storage layer between the semiconductor pattern and the gate electrodes, a second charge storage layer between the first charge storage layer and the semiconductor pattern, and a third charge storage layer between the first charge storage layer and the gate electrodes.

08/18/16
20160240549 

Method for manufacturing semiconductor device


According to one embodiment, a method for manufacturing a semiconductor device includes forming a first film on a multilayer body including two or more stacked films. One stacked film includes a first layer and a second layer.
Kabushiki Kaisha Toshiba


08/18/16
20160240547 

Semiconductor memory device


According to one embodiment, a semiconductor memory device includes first plate-like members, a first wiring, a second plate-like member, a second wiring, first to third semiconductor pillars, a memory film, first to third contacts, first to third plugs, and third wirings. The first wiring is placed between two adjacent ones of the first plate-like members.
Kabushiki Kaisha Toshiba


08/18/16
20160240543 

Semiconductor device manufacturing method and semiconductor device


A semiconductor device manufacturing method includes: forming an element isolation insulating film in a semiconductor substrate; forming a first film on a surface of the semiconductor substrate; forming a second film on the element isolation insulating film and on the first film; forming a first resist pattern that includes a first open above the element isolation insulating film in a first region; removing the second film on the element isolation insulating film in the first region to separate the second film in the first region into a plurality of parts by performing first etching; forming a third film on the second film in the first region; forming a first gate electrode on the third film in the first region; and forming a first insulating film that includes the first to third films under the first gate electrode by patterning the first to third films.. .
Fujitsu Semiconductor Limited


08/18/16
20160240540 

Semiconductor structure having a center dummy region


A semiconductor structure is provided, including a substrate, a plurality of first semiconductor devices, a plurality of second semiconductor devices, and a plurality of dummy slot contacts. The substrate has a device region, wherein the device region includes a first functional region and a second functional region, and a dummy region is disposed therebetween.
United Microelectronics Corp.


08/18/16
20160240538 

Semiconductor device having buried gate, fabricating the same, and module and system having the same


A semiconductor device includes junction regions formed in upper portions of both sidewalls of a trench formed in a semiconductor substrate, a first gate electrode buried in the trench and having a stepped upper surface, and a second gate electrode formed on the first gate electrode to overlap a junction region.. .
Sk Hynix Inc.


08/18/16
20160240537 

Semiconductor device including fin structures and manufacturing method thereof


A semiconductor device includes a fin fet transistor. The fin fet transistor includes a first fin structure extending in a first direction, a gate stack and a source and a drain.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/18/16
20160240536 

Structure and formation finfet device


Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a first gate stack and a second gate stack over the semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd


08/18/16
20160240533 

Vertical cmos structure and method


A method for forming stacked, complementary transistors is disclosed. Selective deposition techniques are used to form a column having a lower portion that includes one type of semiconductor (e.g.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240532 

Gate-all-around semiconductor device and fabricating the same


The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between sti regions at least one suspended nanostructure anchored by a source region and a drain region.
Imec Vzw


08/18/16
20160240531 

Finfet device and manufacturing same


A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240530 

Finfet structure and forming same


A method of forming a semiconductor device includes providing a semiconductor substrate. The semiconductor substrate includes fins formed thereon and a patterned hard mask layer formed on a top surface of the fins.
Semiconductor Manufacturing International (shanghai) Corporation


08/18/16
20160240529 

Die including a schottky diode


According to an embodiment of the invention there may be provided a die that may include (a) a first region of a first type; (b) a first conductor that contacts the first region; (c) a substrate having a substrate portion of the first type; wherein the substrate portion contacts the first region; an intermediate region of a second type; wherein the first type and the second type are selected from an n-type semiconductor and a p-type semiconductor; wherein the first type differs from the second type; (d) a second region of the second type; (e) a second conductor that contacts the second region; (f) a third region of the second type; (g) a third conductor that contacts the third region; (h) a fourth region of the first type; wherein the third region contacts the fourth region and does not contact the intermediate region; (i) a fourth conductor that contacts the intermediate region to form a first schottky diode. A doping concentration of the intermediate region may be lower that a doping concentration of each one of the second region and the third region.
Tower Semiconductor Ltd.


08/18/16
20160240528 

Igbt with built-in diode and manufacturing method therefor


An insulated gate bipolar translator (igbt) with a built-in diode and a manufacturing method thereof are provided. The igbt comprises: a semiconductor substrate (1) of the first conduction type which has a first major surface (1s1) and a second major surface (1s2), wherein the semiconductor substrate (1) comprises an active region (100) and a terminal protection area (200) which is located at the outer side of the active region; an insulated gate transistor unit which is formed at the side of the first major surface (1s1) of the active region (100), wherein a channel of the first conduction type is formed thereon during the conduction thereof; and first semiconductor layers (10) of the first conduction type and second semiconductor layers (11) of the second conduction type of the active region, which are formed at the side of the second major surface (1s2) of the semiconductor substrate (1) alternately, wherein the igbt only comprises the second semiconductor layers (11) in the terminal protection area (200) which is located at the side of the second major surface (1s2) of the semiconductor substrate (1)..
Csmc Technologies Fab1 Co., Ltd.


08/18/16
20160240526 

Apparatus and methods for modulating current / voltage response using multiple semi-conductive channel regions (scr) produced from different integrated semiconductor structures


Apparatuses and methods for modulating current/voltage response using multiple semi-conductive channel regions (scr) produced from different integrated semiconductor structures are provided. In particular, embodiments include systems and methods for controlling current or mitigating electromagnetic or radiation interference effects using combined integrated functions of a lateral double-diffused metal-oxide semiconductor field effect transistor (ldmosfet) and junction field effect transistor (jfet) disposed in proximity of a ldmosfet's scr within a certain orientation forming a second scr..
The United States Of America As Represented By The Secretary Of The Navy


08/18/16
20160240525 

Semiconductor devices and arrangements for electrostatic discharge protection


A semiconductor device and device arrangement including a plurality of semiconductor regions of different conductivity types and a plurality of gates which form electrically conducting paths between the semiconductor regions. The semiconductor device and device arrangement may be configured to protect against electrostatic discharge..
Intel Ip Corporation


08/18/16
20160240524 

Electrostatic discharge (esd) protection device


An electrostatic discharge (esd) protection device includes a semiconductor layer having a first doped region, a second doped region, and an intrinsic region formed therein, and a plurality of insulating elements respectively formed therein. The plurality of insulating elements is respectively formed in a portion of the semiconductor layer between the first, second and third doped regions.
Mediatek Inc.


08/18/16
20160240523 

Method for manufacturing semiconductor device, sheet-shaped resin composition, and dicing tape-integrated sheet-shaped resin composition


Provided is a method for manufacturing a semiconductor device, which can manufacture a semiconductor device at a high yield ratio by suppressing dissolution of a sheet-shaped resin composition when cleaning a wafer after peeling a supporting member from the wafer. The present invention provides a method for manufacturing a semiconductor device, the method including: a step a of preparing a wafer; a step b of pasting together a second main surface of the wafer and a supporting member including a support and a temporary fixing layer formed on the support with the temporary fixing layer interposed between the second main surface and the supporting member; a step c of preparing a laminate including a dicing tape and an ultraviolet curable sheet-shaped resin composition laminated on the dicing tape; a step d of pasting together a first main surface of the wafer and the sheet-shaped resin composition; a step e of peeling the supporting member from the wafer after the step d; a step f of cleaning the second main surface of the wafer after the step e; and a step s of irradiating a peripheral part of the sheet-shaped resin composition with ultraviolet light to cure the peripheral part after the step d and before the step f, the peripheral part not overlapping with the wafer in a plan view..
Nitto Denko Corporation


08/18/16
20160240517 

Display device using semiconductor light emitting devices


A display device including a wiring substrate having a wiring electrode; a plurality of semiconductor light emitting devices which form pixels; and a conductive adhesive layer configured to electrically connect the wiring electrode with the plurality of semiconductor light emitting devices. Further, the conductive adhesive layer includes a body provided with a resin having an adhesive property; and a metallic aggregation part disposed in the body, and formed as metallic atoms precipitated from a metal-organic compound and aggregated with each other..
Lg Electronics Inc.


08/18/16
20160240516 

Method of manufacturing semiconductor device array


Present disclosure provides a method for manufacturing a semiconductor device array, including (1) providing a temporary substrate; (2) forming a plurality of discrete semiconductor structures over the temporary substrate; and (3) removing a surface portion of the temporary substrate to expose a peripheral bottom surface of the discrete semiconductor structure. Present disclosure also provides a method for transferring discrete semiconductor device, including (1) detaching discrete semiconductor structures of a first type from a first temporary substrate supporting the discrete semiconductor structures of the first type by a transfer stamp; (2) carrying the discrete semiconductor structures over a target substrate by the transfer stamp; and (3) dismounting the discrete semiconductor structures of the first type from the transfer stamp to predetermined sites on the target substrate.
Globalwafers Co., Ltd.


08/18/16
20160240511 

Power package lid


The present disclosure relates to a ring-frame power package. In this regard, the ring-frame power package includes a thermal carrier and a ring structure.
Triquint Semiconductor, Inc.


08/18/16
20160240509 

Semiconductor packages


Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter..
Samsung Electronics Co., Ltd.


08/18/16
20160240507 

Wafer-level package with at least one input/output port connected to at least one management bus


A wafer-level package has a first input/output (i/o) port, a second i/o port, a first semiconductor die, and a second semiconductor die. The first i/o port and the second i/o port of the wafer-level package are arranged to connect at least one management bus.
Mediatek Inc.


08/18/16
20160240504 

Method for manufacturing semiconductor device


A method for manufacturing a semiconductor device includes a first step of forming a first electrode on one main surface side of a semiconductor wafer; a second step of bonding a first film to another main surface side of the semiconductor wafer; a third step of bonding a second film to an outer peripheral portion of the semiconductor wafer by applying pressure to the second film on the semiconductor wafer using a plurality of cylindrical rollers, after the second step; and a fourth step of forming a plating layer on the first electrode on the one main surface side of the semiconductor wafer by a plating process, after the third step.. .
Fuji Electric Co., Ltd.


08/18/16
20160240503 


The present disclosure relates to bonding structures useful in semiconductor packages and methods of manufacturing the same. In an embodiment, the bonding structure comprises a substrate, having a top surface and including at least one bonding pad, wherein each bonding pad is disposed adjacent to the top surface of the substrate and has a sloped surface; and a semiconductor element including at least one pillar, wherein each pillar is bonded to a portion of the sloped surface of a corresponding bonding pad, and a gap is formed between a sidewall of the pillar and the sloped surface of the corresponding bonding pad..
Advanced Semiconductor Engineering, Inc.


08/18/16
20160240502 

Integrated circuit packaging substrate, semiconductor package, and manufacturing method


An integrated circuit (ic) packaging substrate includes a main body, at least one first conductive line, at least one second conductive line, and at least one protrusion pad. The first conductive line is embedded in the main body.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/18/16
20160240500 

Packaged semiconductor devices


A packaged semiconductor device is provided, which includes a substrate comprising a contact pad; a passivation layer disposed on the substrate, where the passivation layer covers part of the contact pad; an under bump metallization (ubm) layer disposed on the substrate, where the ubm layer is coupled to the contact pad; a conductive bump disposed on the ubm layer, where the conductive bump comprises a column connecting the ubm layer and a cap disposed on top of the column; and a solder ball encapsulating the conductive bump. The cap includes a bottom area larger than a cross-sectional area of the column, and a bottom of the cap is distant from an upper surface of the passivation layer by a space..
Chipmos Technologies (bermuda) Ltd.


08/18/16
20160240499 

Semiconductor device and manufacturing the same


The semiconductor device includes a plurality of wiring layers formed on a semiconductor substrate, a pad formed on an uppermost wiring layer of the plurality of wiring layers, a surface protection film which includes an opening on the pad and is made of an inorganic insulating film, a rewiring formed on the surface protection film; a pad electrode formed on the rewiring, and a wire connected to the pad electrode. The rewiring includes a pad electrode mounting portion on which the pad electrode is mounted, a connection portion which is connected to the pad, and an extended wiring portion which couples the pad electrode mounting portion and the connection portion, and the pad electrode mounting portion has a rectangular shape when seen in a plan view..

08/18/16
20160240496 

Devices and methods related to electrostatic discharge protection benign to radio-frequency operation


Disclosed are systems, devices and methods for providing electrostatic discharge (esd) protection for integrated circuits. In some implementations, first and second conductors with ohmic contacts on an intrinsic semiconductor region can function similar to an x-i-y type diode, where each of x and y can be n-type or p-type.
Skyworks Solutions, Inc.


08/18/16
20160240495 

Integrated antennas in wafer level package


A semiconductor module comprises an integrated circuit device, the ic device embedded in a compound material, wherein the compound material at least partially extends lateral to the ic device. The semiconductor module further comprises interconnect structures arranged lateral to the ic device to provide at least one external electrical contact; a patch antenna structure integrated in the semiconductor module and electrically connected to the ic device and a layer interfacing the ic device and the compound, wherein the layer comprises first and second planar metal structures coupled to the ic device, wherein the first planar metal structure is electrically connected to the ic device and the interconnect structures and wherein the second planar metal structure is electrically connected to the ic device and the patch antenna structure..
Infineon Technologies Ag


08/18/16
20160240494 

Rf package and manufacturing method thereof


Disclosed is a method of improving performance and increasing a freedom degree of design of an interconnect structure in a radio frequency (rf) package. The rf package may include a package base, a semiconductor die mounted on the package base, a package substrate formed on the package base, the package substrate comprising at least one defected substrate structure (dss), and a conducting pattern formed on one side of the package substrate and electrically connected with the semiconductor die, wherein the at least one dss overlaps at least a portion of the conducting pattern in perspective of a top view of the rf package..
Electronics And Telecommunications Research Institute


08/18/16
20160240493 

Semiconductor device packages and making the same


The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a semiconductor device, a plurality of electronic components, a first package body, a patterned conductive layer and a feeding element.
Advanced Semiconductor Engineering, Inc.


08/18/16
20160240490 

Method for fabricating semiconductor devices having reinforcing elements


The present disclosure provides a method for fabricating semiconductor devices having reinforcing elements. The method includes steps of providing a first wafer having a lower electrode layer and an insulation layer; forming a device layer; etching the device layer and the insulation layer to form recesses; etching the device layer to form separation trenches and upper electrodes; forming reinforcing elements; and depositing metal pads.
Asia Pacific Microsystems, Inc.


08/18/16
20160240488 

Semiconductor device with an isolation structure coupled to a cover of the semiconductor device


A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling are presented. The semiconductor device is formed on a substrate.
Freescale Semiconductor, Inc.


08/18/16
20160240487 

Semiconductor device


Signal transmission characteristics of a semiconductor device are improved. A plurality of wirings of a wiring substrate on which a semiconductor chip is mounted include a first wiring and a second wiring that constitute a differential pair for use in transmitting a differential signal.
Renesas Electronics Corporation


08/18/16
20160240485 

Middle-of-line integration methods and semiconductor devices


An electronic device includes a middle-of-line (mol) stack. The electronic device includes a top local interconnect layer and a contact coupling the top local interconnect layer to a gate of a semiconductor device through a first dielectric layer.
Qualcomm Incorporated


08/18/16
20160240484 

Semiconductor device and manufacturing same


To provide a semiconductor device having improved reliability by improving a coupling property between a semiconductor chip and a bonding wire. A redistribution layer is comprised of a cu film, an ni film, and a pd film which have been formed successively from the side of a semiconductor substrate.
Renesas Electronics Corporation


08/18/16
20160240482 

Layer structure including diffusion barrier layer and manufacturing the same


Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween.
Samsung Electronics Co., Ltd.


08/18/16
20160240481 

Interposer substrate, semiconductor structure and fabricating process thereof


Described herein are interposer substrate designs for warpage control, semiconductor structures including said interposer substrates, and fabricating processes thereof. An interposer substrate defines a cavity and further includes a reinforcement structure, wherein the reinforcement structure is used to control warpage of the semiconductor package structure..
Advanced Semiconductor Engineering, Inc.


08/18/16
20160240477 

Semiconductor arrangement and formation thereof


A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes an interconnect which includes an interconnect metal plug surrounded by a second metal layer.
Taiwan Semiconductor Manufacturing Company Limited


08/18/16
20160240476 

Self-aligned integrated line and via structure for a three-dimensional semiconductor device


At least one via level dielectric layer and at least one line level dielectric layer are sequentially formed over an array of device structures. Conductive line structures are formed within the at least one line level dielectric layer.
Sandisk Technologies Inc.


08/18/16
20160240475 

Semiconductor devices including sealing regions and decoupling capacitor regions


Semiconductor devices may include an internal circuit, a sealing region surrounding the internal circuit, and a decoupling capacitor region in the sealing region. The decoupling capacitor region may include decoupling capacitors.
Samsung Electronics Co., Ltd.


08/18/16
20160240474 

Method, system and computer readable medium using stitching for mask assignment of patterns


A method comprises: accessing data representing a layout of a layer of an integrated circuit (ic) comprising a plurality of polygons defining circuit patterns to be divided among a number (n) of photomasks for multi-patterning a single layer of a semiconductor substrate, where n is greater than one. For each set of n parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least n−1 stitches are inserted in each polygon within that set to divide each polygon into at least n parts, such that adjacent parts of different polygons are assigned to different photomasks from each other.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/18/16
20160240473 

Wafer with improved plating current distribution


A semiconductor wafer is provided including a plurality of dies, each of the plurality of dies including a plurality of semiconductor devices, a plurality of die seals, each of the plurality of die seals being formed at a perimeter of one of the plurality of dies, and a plurality of electrically conductive links, each of the plurality of conductive links connecting one of the plurality of die seals with another one of the plurality of die seals.. .
Globalfoundries Inc.


08/18/16
20160240472 

Semiconductor device, layout design and manufacturing a semiconductor device


A semiconductor device includes a first interconnect structure. The first interconnect structure includes a first interconnect portion, a second interconnect portion and a third interconnect portion.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240470 

Semiconductor modules and methods of forming the same


Electronic modules, and methods of forming and operating modules, are described. The modules include a capacitor, a first switching device, and a second switching device.
Transphorm Inc.


08/18/16
20160240469 

Semiconductor substrate, semiconductor package structure and making the same


The present disclosure relates to a semiconductor substrate, a semiconductor package structure, and methods for making the same. A method includes providing a substrate and a carrier layer.
Advanced Semiconductor Engineering, Inc.


08/18/16
20160240467 

Wiring board and semiconductor package


A wiring board includes a wiring layer including a surface on which a recess is formed and a metal layer formed on a bottom surface of the recess. A surface of the metal layer facing away from the bottom surface of the recess is closer to the bottom surface of the recess than is the surface of the wiring layer..
Shinko Electric Industries Co., Ltd.


08/18/16
20160240464 

Hybrid circuit board and making the same, and semiconductor package structure


A hybrid circuit board includes an insulate molding layer having a first surface and a second surface which is opposite to the first surface, a solder mask layer on the first surface, a conductive patterned layer on the first surface and embedded in the solder mask layer, and a plurality of conductive pillars embedded in the insulate molding layer. The thickness of the conductive patterned layer is substantially equal to the thickness of the solder mask layer.
Zhen Ding Technology Co., Ltd.


08/18/16
20160240462 

Semiconductor substrate structure, semiconductor package and manufacturing the same


The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure, a dielectric structure and a metal bump.
Advanced Semiconductor Engineering, Inc.


08/18/16
20160240461 

Semiconductor package with multi-section conductive carrier


In one implementation, a power semiconductor package includes a non-contiguous, multi-section conductive carrier. A control transistor with a control transistor terminal is coupled to a first section of the multi-section conductive carrier, while a sync transistor with a sync transistor terminal is coupled to a second section of the multi-section conductive carrier.
Infineon Technologies Americas Corp.


08/18/16
20160240460 

Singulation semiconductor package with plating on side of connectors


A method of singulating semiconductor packages, the method comprising: providing a plurality of semiconductor dies coupled to a single common leadframe, wherein a molding compound at least partially encases the semiconductor dies and the leadframe; singulating the plurality of semiconductor dies, wherein the leadframe is at least partially cut between adjacent semiconductor dies, thereby forming exposed side surfaces on leads of the leadframe; and plating the exposed side surfaces of the leads with a plating material, wherein the plating material is a different material than the leads. In some embodiments, singulating the plurality of semiconductor dies comprises performing a full cut of the leadframe.
Utac Thai Limited


08/18/16
20160240458 

Package


A package includes: a plurality of lead frames configured to extend inwardly from an outer circumferential portion of the package; a die pad region surrounded with the lead frames in a plane view; a semiconductor chip mounted on the die pad region; a plurality of bonding pads disposed on the semiconductor chip; and a plurality of bonding wires configured to connect the lead frames and the bonding pads, respectively, wherein the bonding wires are respectively connected to front end portions of the lead frames by bonding with an angle ranging from 45 to 135 degrees with respect to a trace of front end portions of the lead frames in the plane view.. .
Rohm Co., Ltd.


08/18/16
20160240456 

Semiconductor device


A semiconductor device (10) includes a metallic base plate (22) provided with an upper surface (22a) and a lower surface (22b), a plurality of insulating substrates (24) provided on the upper surface (22a), and a plurality of semiconductor elements (26) and (28) mounted side by side on the respective insulating substrates (24). Annular grooves (50) and (52) for storing insulating grease are provided on the lower surface (22b) of the base plate (22).
Mitsubishi Electric Corporation


08/18/16
20160240455 

Systems, apparatus, and methods for heat dissipation


Some examples of the disclosure include a semiconductor package having a heat spreader, an outer perimeter portion attached to the bottom of the heat spreader along the perimeter and having a plurality of electrical pathways, a package substrate located below and spaced from the outer perimeter portion and having a plurality of electrical pathways, a plurality of connection points located between the outer perimeter component and the package substrate to provide connection points coupling the plurality of electrical pathways of the outer perimeter portion to the plurality of electrical pathways in the package substrate, and a cavity formed on the bottom of the heat spreader inside the outer perimeter portion.. .
Qualcomm Incorporated


08/18/16
20160240454 

Semiconductor structure having thermal backside core


A semiconductor structure includes a semiconductor substrate having a recess disposed beneath a semiconductor device. The semiconductor structure also includes a thermally conductive core disposed in the recess, and a package substrate including a heat sink.
Avago Technologies General Ip (singapore) Pte. Ltd.


08/18/16
20160240453 

Semiconductor device and manufacturing the same


The method of manufacturing a semiconductor device includes receiving a substrate. The substrate comprises at least one chip region and at least one scribe line next to the chip region, and each chip region comprises an active region.
Taiwan Semiconductor Manufacturing Company Ltd.


08/18/16
20160240452 

Semiconductor packages with sub-terminals and related methods


A semiconductor device package includes a substrate having first and second opposing surfaces. A first surface of a die couples to the second surface of the substrate, and a first surface of an electrically conductive sub-terminal electrically couples with an electrical contact of the die and physically couples to the second surface of the substrate.
Semiconductor Components Industries, Llc


08/18/16
20160240451 

Interconnect structure for semiconductor package and fabricating the interconnect structure


A semiconductor package includes a carrier, at least and adhesive portion, a plurality of micro pins and a die. The carrier has a first surface and second surface opposite to the first surface.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/18/16
20160240450 

Semiconductor device


A semiconductor device has a semiconductor element provided with a functional surface on which a functional circuit is formed and with a back surface facing in the opposite direction to the functional surface, while also having a lead supporting the semiconductor element and electrically connected to the semiconductor element, and a resin package covering at least a portion of the semiconductor element and the lead. The semiconductor element has a functional surface side electrode formed on the functional surface and equipped with a functional surface side raised part that projects in the direction in which the functional surface faces.
Rohm Co., Ltd.


08/18/16
20160240446 

Semiconductor manufacturing apparatus and manufacturing semiconductor device


According to one embodiment, a semiconductor manufacturing apparatus includes a manufacturing processor, a signal acquisition unit, a frequency characteristic acquisition unit, and an end-point acquisition unit. The signal acquisition unit acquires a first processing signal which shows a different behavior during processing of a stacked body and after the processing of the stacked body.
Kabushiki Kaisha Toshiba


08/18/16
20160240444 

Method of semiconductor fabrication with height control through active region profile


The present disclosure provides a method for fabricating an integrated circuit in accordance with some embodiments. The method includes forming a trench on a semiconductor substrate, thereby defining fin active regions; extracting a profile of the fin active regions; determining an etch dosage according to the profile of the fin active regions; filling in the trench with a dielectric material; and performing an etching process to the dielectric material using the etch dosage, thereby recessing the dielectric material and defining a fin height of the fin active regions..
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240443 

Semiconductor manufacturing method and tool


An overlay measurement and correction method and device is provided. In an embodiment the measurement device takes measurements of a first semiconductor wafer and uses the measurements in a plurality of correction techniques to generate an overlay correction model.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240442 

Semiconductor device and forming the same


A method of forming a semiconductor device includes forming a gate stack over a substrate, forming an amorphized region in the substrate adjacent to an edge of the gate stack, forming a stress film over the substrate, performing a process to form a dislocation with a pinchoff point in the substrate, removing at least a portion of the dislocation to form a recess cavity with a tip in the substrate, and forming a source/drain feature in the recess cavity.. .
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240439 

Semiconductor device and method


A semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor device and a second semiconductor device are formed within a semiconductor wafer and a scribe region between the first semiconductor device and the second semiconductor device is patterned.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240434 

Method for via plating with seed layer


Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240433 

Ruthenium film forming method, film forming apparatus, and semiconductor device manufacturing method


A ruthenium film forming method includes a deposition process of introducing a mixed gas of a ruthenium carbonyl gas and a co gas into a processing vessel 1 by supplying the co gas as a carrier gas from a co gas container 43 configured to contain the co gas into a film forming source container 41 configured to contain ruthenium carbonyl in a solid state as a film forming source material, and forming ruthenium film by decomposing the ruthenium carbonyl on a wafer w; and a co gas introduction process of bringing the co gas into contact with a surface of the wafer w by introducing the co gas directly into the processing vessel 1 from the co gas container 43 after stopping the introducing of the mixed gas into the processing vessel 1. The deposition process and the co gas introduction process are repeated multiple times..
Tokyo Electron Limited


08/18/16
20160240430 

Method of fabricating semiconductor device


A method for fabricating a semiconductor device includes forming a hard mask (hm) layer over a material layer, forming a first trench in the hm layer, which extends along a first direction. The method also includes forming a first patterned resist layer over the hm layer.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240428 

Method of forming an interconnect structure having an air gap and structure thereof


A semiconductor device and method of manufacture are provided which utilize an air gap to help isolate conductive structures within a dielectric layer. A first etch stop layer is deposited over the conductive structures, and the first etch stop layer is patterned to expose corner portions of the conductive structures.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240427 

Semiconductor structure and manufacturing method thereof


A semiconductor structure includes a substrate, at least one first epitaxial layer, and at least one second epitaxial layer. The substrate has a plurality of recesses multidimensionally arranged therein.
Taiwan Semiconductor Manufacturing Co., Ltd.


08/18/16
20160240411 

Multi-processing manufacturing semiconductor device


A multi-processing apparatus includes an electron beam irradiation unit, a dry etching unit and a transfer unit. The transfer unit is connected to the electron beam irradiation unit and the dry etching unit, and is configured to transfer a wafer under a reduced-pressure atmosphere from the electron beam irradiation unit to the dry etching unit..
Kabushiki Kaisha Toshiba


08/18/16
20160240409 

Systems and methods for microwave-radiation annealing


Systems and methods are provided for annealing a semiconductor structure using microwave radiation. A semiconductor structure is provided.
Taiwan Semiconductor Manufacturing Company Limited


08/18/16
20160240405 

Stand alone anneal system for semiconductor wafers


A high throughput stand-alone anneal system has a horizontal row of docking stations at a front wall of an enclosure. A rack in the enclosure has a plurality of vertically stacked anneal modules.
Applied Materials, Inc.


08/18/16
20160240396 

Apparatus for manufacturing semiconductor package and manufacturing semiconductor package using the same


The inventive concepts provide an apparatus for manufacturing a semiconductor package and a method for manufacturing a semiconductor package using the same. The apparatus includes a mold unit with a cavity formed by an inner space of the mold unit.
Samsung Electronics Co., Ltd.


08/18/16
20160240394 

Semiconductor device manufacturing method


A method for producing a semiconductor device includes: a step a of preparing a chip with sheet-shaped resin composition in which a sheet-shaped resin composition is pasted onto a bump formation surface of a semiconductor chip, a step b of preparing a substrate for mounting on which an electrode is formed, a step c of pasting the chip with resin composition to the substrate for mounting so that the resin composition serves as a pasting surface with the bump formed on the semiconductor chip facing toward the electrode formed on the substrate for mounting, a step d of heating the resin composition to semi-cure the resin composition after the step c, and a step e of heating the resin composition at a higher temperature than that in the step d to cure the resin composition after the step d while bonding the bump and the electrode.. .
Nitto Denko Corporation


08/18/16
20160240387 

Method of fabricating semiconductor device


A method for fabricating a semiconductor device includes forming a first hard mask (hm) layer over a material layer, forming a patterned second hm layer over the first hm layer. The patterned second hm layer has first trench extending along a first direction.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240386 

Self-aligned multiple spacer patterning process


Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including pattering a mandrel layer disposed over a semiconductor device layer to form a mandrel, forming a first set of spacers on sidewalls of the mandrel using a first material, selectively removing the mandrel disposed between the first set of spacers.
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240380 

Method of manufacturing silicon carbide semiconductor device


A method of manufacturing a silicon carbide semiconductor device includes a step of preparing a silicon carbide substrate having a first main surface and a second main surface located opposite to the first main surface, a step of forming a doped region in the silicon carbide substrate by doping the first main surface with an impurity, a step of forming a first protecting film on the first main surface, and a step of forming a second protecting film on the second main surface, the step of forming a first protecting film being performed after the step of forming a doped region, the method further including a step of activating the impurity included in the doped region by annealing with at least a portion of the first main surface covered with the first protecting film and at least a portion of the second main surface covered with the second protecting film.. .
Sumitomo Electric Industries, Ltd.


08/18/16
20160240379 

Depression filling method and processing apparatus


A method of filling a depression of a workpiece is provided. The method includes forming a first thin film made of a semiconductor material substantially not containing an impurity along a wall surface which defines the depression, forming an epitaxial region conforming to crystals of the semiconductor substrate from the semiconductor material of the first thin film moved toward a bottom of the depression by annealing, etching the first thin film remaining on the wall surface, performing gas phase doping upon the epitaxial region, forming a second thin film made of a semiconductor material substantially not containing an impurity along the wall surface, further forming an epitaxial region from the semiconductor material of the second thin film moved toward the bottom of the depression by annealing, and performing gas phase doping upon the second thin film remaining on the wall surface and the epitaxial region..
Tokyo Electron Limited


08/18/16
20160240378 

Vertical gate all around (vgaa) devices and methods of manufacturing the same


Vertical gate all around (vgaa) devices and methods of manufacture thereof are described. A method for manufacturing a vgaa device includes: forming a first doped region having a first conductivity in a substrate; forming a second doped region having a second conductivity different from the first conductivity in the substrate, the second doped region disposed laterally adjacent to and spaced apart from the first doped region; and oxidizing a semiconductive layer disposed between the substrate and the second doped region to form an oxidized isolation layer..
Taiwan Semiconductor Manufacturing Company, Ltd.


08/18/16
20160240374 

Method for forming insulating film and manufacturing semiconductor device


In a method for forming a fluorocarbon-based insulating film to be in contact with a metal, a microwave is irradiated to the metal to which moisture is adhered in a hydrogen-containing atmosphere. Then plasma cvd using a fluorocarbon-based gas is performed on the metal to which the microwave is irradiated to form the insulating film..
Tokyo Electron Limited


08/18/16
20160240373 

Method for forming oxide layer by oxidizing semiconductor substrate with hydrogen peroxide


In some embodiments, an oxide layer is grown on a semiconductor substrate by oxidizing the semiconductor substrate by exposure to hydrogen peroxide at a process temperature of about 500° c. Or less.
Asm Ip Holding B.v.


08/18/16
20160240369 

Method for manufacturing compound semiconductor epitaxial substrates including heating of carrier gas


An aspect of the present disclosure resides in a method for manufacturing a compound semiconductor epitaxial substrate including a substrate and a compound semiconductor epitaxial layer disposed on the substrate, the method including providing the substrate, heating a carrier gas, preparing a mixed gas by mixing the heated carrier gas with at least a portion of a source gas that is a source for the compound semiconductor epitaxial layer, the source gas having a lower temperature than the heated carrier gas, and forming the compound semiconductor epitaxial layer on the substrate by supplying the mixed gas onto the substrate.. .
Panasonic Corporation


08/18/16
20160240368 

Method and composition for selectively removing metal hardmask and other residues from semiconductor device substrates comprising low-k dielectric material and copper


An aqueous removal composition having a ph in the range of from 2 to 14 and method for selectively removing an etching mask consisting essentially of tin, tan, tinxoy, tiw, w, or alloy of ti or w relative to low-k materials from a semiconductor substrate comprising said low-k materials having a tin, tan, tinxoy, tiw, w, or alloy of ti or w etching mask thereon wherein the removal composition comprises at least one oxidizing agent and a carboxylate compound.. .
Ekc Technology, Inc.


08/18/16
20160240366 

Processing of semiconductor devices


A method of thinning a wafer includes thinning the wafer using a grinding process. The wafer, after the grinding processing, has a first non-uniformity in thickness.
Infineon Technologies Ag


08/18/16
20160240327 

Capacitor unit with high-energy storage


The present invention provides a capacitor unit with high-energy storage which includes an electrolyte, a positive electrode, and a negative electrode. The electrolyte includes an electrically conductive polymer composition.
Apaq Technology Co., Ltd.


08/18/16
20160240322 

Composition for conductive polymer synthesis


A composition for conductive polymer synthesis is disclosed. The composition includes a monomer, an oxidant, and a nitrogen-containing polymer.
Industrial Technology Research Institute


08/18/16
20160240312 

Low temperature multilayer dielectric film for passivation and capacitor


The present disclosure generally relates to capacitors having a multilayer dielectric material between two electrodes. The multilayer dielectric material can have a small thickness with little to no breakdown strength reduction.
Applied Materials, Inc.


08/18/16
20160240264 

Semiconductor memory device


A semiconductor memory device includes a first memory cell, a first word line electrically connected to a gate of the first memory cell, a first bit line electrically connected to one end of the first memory cell, and a controller configured to execute a write operation, which includes a first cycle and a second cycle that is executed after the first cycle. The first cycle includes a first operation of applying a program voltage to the first word line, a second operation executed after the first operation of applying a first voltage to the first bit line and a second voltage lower than the first voltage to the first word line, and a third operation executed after the second operation of applying a verify voltage to the first word line.
Kabushiki Kaisha Toshiba


08/18/16
20160240261 

Nonvolatile semiconductor memory device


A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode.
Kabushiki Kaisha Toshiba


08/18/16
20160240260 

Flash memory system using complementary voltage supplies


A non-volatile memory device comprises a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is located in the semiconductor substrate and arranged in a plurality of rows and columns.
Silicon Storage Technology, Inc.


08/18/16
20160240247 

Semiconductor memory device


According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data.
Kabushiki Kaisha Toshiba


08/18/16
20160240246 

Semiconductor storage device


A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level.
Renesas Electronics Corporation


08/18/16
20160240243 

Semiconductor device


A semiconductor device capable of reconfiguration, including a plurality of logic units which are connected to each other by an address line or a data line, wherein each of the logic units includes: a plurality of address lines; a plurality of data lines; a clock signal line to receive a system clock signal; a first and a second memory cell units which operate synchronously with the clock signal; a first address decoder which decodes an address signal and outputs a decode signal to the first memory cell unit; a second address decoder which decodes an address signal and outputs a decode signal to the second memory cell unit; and an address transition detection unit which generates an internal clock signal and outputs the internal clock signal to the first memory cell unit, when a transition of the address signal input from the plurality of address lines is detected, wherein the first memory cell unit operates synchronously with the internal clock signal, and the second memory cell unit operates synchronously with the system clock signal.. .
Taiyo Yuden Co., Ltd.


08/18/16
20160240241 

Semiconductor memory device, controlling read preamble signal thereof, and data transmission system


A system, includes a controller comprising a plurality of first external terminals configured to supply a command and an address, and communicate a data, and communicate a strobe signal related to the data; and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, at least one of the plurality of first external terminals and at least one of the plurality of second external terminals each being capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data between the controller and the semiconductor memory device, the semiconductor memory device further including a preamble register configured to be capable of storing the information.. .
Ps4 Luxco S.a.r.l.


08/18/16
20160240240 

Semiconductor memory device, semiconductor memory system and operation method thereof


Disclosed herein is a semiconductor memory device which performs a refresh operation. The semiconductor memory device may include an information detection unit suitable for detecting a refresh characteristic of a memory cell, a control signal generation unit suitable for generating a refresh control signal having a refresh cycle corresponding to the refresh characteristic, and a refresh driving unit suitable for driving a refresh operation on the memory cell with the refresh cycle in response to the refresh control signal..
Sk Hynix Inc.


08/18/16
20160240239 

Semiconductor device and electronic device


A semiconductor device capable of generating a signal (e.g., a potential signal or a current signal) suitable for usage environment or a purpose. The semiconductor device includes a first memory circuit, a first circuit, and a second memory circuit.
Semiconductor Energy Laboratory Co., Ltd.


08/18/16
20160240234 

Semiconductor apparatus configured to manage an operation timing margin


A semiconductor apparatus may include a read path configured to transmit data from the semiconductor apparatus in response to a read command and at least one read operation control signal, and an operation control circuit configured to receive a plurality of divided clock signals and the read command to identify the one of the plurality of divided clock signals that is relatively better matched to the received read command to manage timings associated with at least one of the read operation control signals.. .
Sk Hynix Inc.


08/18/16
20160240233 

Memory, semiconductor device including the same, and testing the same


A memory includes a first memory cell, a second memory cell, a latch unit, and a switch unit. The latch unit has a true node and a complement node.
Taiwan Semiconductor Manufacturing Company Limited


08/18/16
20160240232 

Semiconductor device having high-voltage transistor


A semiconductor device includes a semiconductor device, comprising a memory cell array including a plurality of memory cells connected to a first bit line and a second bit line, respectively, a page buffer group, and bit line selection circuits including a plurality of selection circuit blocks to connect the first bit lines or the second bit lines to the page buffer group, wherein each of the selection circuit blocks includes a first contact region and a second contact region to which the first and second bit lines coupled, and same bit lines of the first and second bit lines are coupled to contact regions adjacent to one another of the first and second contact regions included in bit line selection circuits adjacent to one another of the bit line selection circuits.. .
Sk Hynix Inc.


08/18/16
20160240227 

Semiconductor device package with mirror mode


Semiconductor device assemblies with semiconductor device packages configured to operate in mirror mode are disclosed herein. In one embodiment a semiconductor device assembly includes a first semiconductor device package attached to a front side of a support substrate, and a second semiconductor device package attached to a back side of the support substrate.
Micron Technology, Inc.


08/18/16
20160240184 

Method and nonlinear compensation in an active noise control system


A self tuned apparatus (100) for active noise control includes a first transducer (105) and a second transducer (110), a noise controlling module (115), a power amplifier (120) and a first loudspeaker (125) and a second loudspeaker (130) coupled to the power amplifier (120). The noise controlling module (115) is coupled to the first transducer (105) and the second transducer (110).
Universiti Putra Malaysia


08/18/16
20160240179 

Technique for reproducing waveform by switching between plurality of sets of waveform data


The object of the invention is to switch between plural sets of waveform data at desired timing while preventing noise. In response to an instruction for switching from a currently reproduced set of waveform data to another set of waveform data, either a switching position in the other set of waveform data or a switching in the currently reproduced set of waveform data is set as end timing for ending the reproduction of the currently reproduced set, with reference to switching position information of the two sets.
Yamaha Corporation


08/18/16
20160240166 

Image processing apparatus, image processing method, and computer-readable recording medium


An image processing method is provided. The image processing method includes: converting a color reproduction target of an input image according to a color gamut of a target display device; generating a file of the input image of which the color reproduction target is converted; and storing the file of the input image..
Samsung Electronics Co., Ltd.


08/18/16
20160240103 

Counting wheel odometer with movable decimal point


An improved numeracy and place-value educational device which accurately displays a range of both whole-number and decimal place-value properties. A conventional counting-wheel odometer comprising a plurality of sequentially numbered counting wheels (10a-10f) and motion transfer components (not shown) is supported by a frame (12).





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