|| List of recent Duc-related patents
|Eda tool and method, and integrated circuit formed by the method|
A method comprises: accessing data representing a layout of a layer of an integrated circuit (ic) comprising a plurality of polygons defining circuit patterns to be divided among a number (n) of photomasks for multi-patterning a single layer of a semiconductor substrate, where n is greater than one. For each set of n parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least n−1 stitches are inserted in each polygon within that set to divide each polygon into at least n parts, such that adjacent parts of different polygons are assigned to different photomasks from each other.
|Diagnostic x-ray imaging equipment and x-ray image display method|
There is provided diagnostic x-ray imaging equipment that can reproduce only a desired image range at a desired reproduction speed among a series of consecutive images for an operator. A first band-shaped region 44 of which an overall length corresponds to an overall length of time of consecutive x-ray images in chronological order and a second band-shaped region 44 in which a plurality of positions in a length direction respectively correspond to a plurality of types of reproduction speed determined in advance are displayed on a display device.
|Memory system and method for controlling a nonvolatile semiconductor memory|
A memory system includes a nonvolatile semiconductor memory having blocks, the block being data erasing unit; and a controller configured to execute; an update processing for; writing superseding data in a block, the superseding data being treated as valid data; and invalidating superseded data having the same logical address as the superseding data, the superseded data being treated as invalid data; and a compaction processing for; retrieving blocks having invalid data using a management table, the management table managing blocks in a linked list format for each number of valid data included in the block; selecting a compaction source block having at least one valid data from the retrieved blocks; copying a plurality of valid data included in the compaction source blocks into a compaction target block; invalidating the plurality of valid data in the compaction source blocks; and releasing the compaction source blocks in which all data are invalidated.. .
|Thin translation for system access of non volatile semicondcutor storage as random access memory|
A semiconductor chip is described having a controller having a point-to-point link interface and non volatile memory interfacing circuitry. The point-to-point link interface is to receive a command from a system that identifies a particular non volatile memory.
|Method and system for advanced learning experience (alex)|
To assist student learning, an educational goal of the student can be identified and validated by a teacher. Educational landmarks that need to be reached can be identified.
|Method and apparatus for self-learning and self-improving a semiconductor manufacturing tool|
Performance of a manufacturing tool is optimized. Optimization relies on recipe drifting and generation of knowledge that capture relationships among product output metrics and input material measurement(s) and recipe parameters.
|Distributing relevant information to users of an enterprise network|
Various implementations are directed to systems, apparatus, computer-implemented methods and storage media for identifying a target set of users of an enterprise network to which to distribute a communication of enterprise-related information. For example, when a communication system receives a request to distribute a communication, the communication system analyzes the communication to identify a set of enterprise users that are predicted to find the information in the communication relevant, and especially, relevant from the enterprise's perspective.
|Efficient incremental modification of optimized finite-state transducers (fsts) for use in speech applications|
Methods of incrementally modifying a word-level finite state transducer (fst) are described for adding and removing sentences. A prefix subset of states and arcs in the fst is determined that matches a prefix portion of the sentence.
|Method and apparatus for delivering a substance|
A method of delivering a substance includes providing a substance at a location in a gastrointestinal (gi) tract, excluding a buccal membrane, of a biological body; and applying ultrasonic waves, having a frequency between about 20 khz and about 10 mhz, at the location. The method can include storing the substance in at least one reservoir and exposing a medium within or of the gi tract to the substance.
|Methods for positioning an ultrasonic catheter|
An emitter may be disposed in a patient. Output from the emitter may be detected by a detector connected with the guide rod and by a detector connected with the tracheal tube.
|Remanufactured medical sensor with flexible faraday shield|
Present embodiments include a remanufactured bandage-type medical sensor having an optical assembly with an emitter adapted to transmit one or more wavelengths of light and a photodetector adapted to receive the one or more wavelengths of light transmitted by the emitter. The sensor also includes a laminate assembly having an electrically conductive adhesive transfer tape (ecatt) layer disposed over the photodetector, and the ecatt layer is adapted to shield the photodetector from electromagnetic interference (emi).
|Method for the catalytic reduction of acid chlorides and imidoyl chlorides|
The present application relates to methods for the catalytic reduction of acid chlorides and/or imidoyl chlorides. The methods comprise reacting the acid chloride or imidoyl chloride with a silane reducing agent in the presence of a catalyst such as [cp(pri3p)ru(ncme)2]+[pf6]−..
|Process for continuous production of halogen-free thermoplastic elastomer compositions|
A continuous process for the production of a dynamically vulcanized thermoplastic elastomer comprising a thermoplastic resin and a non-halogenated elastomer with a multiolefin content of greater than 3.5 mol % that has been modified in situ with a carboxylic anhydride. The process provides materials with improved elongation at break and ultimate tensile strength that can be produced economically and with reduced environmental impact..
|Sustainable thermoplastic compounds|
A thermoplastic compound is formed using a blend that includes one of processed fly ash, cinders and processed fly ash and cinders with a fractional melt having a melt flow index of less than 1 or a low melt resin with a melt flow index between 1 and about 3 or both, and a resin compatible with the fractional melt or low melt resin and having a melt flow index that is different from the melt flow index of the fractional melt or the low melt resin. Presence of the processed fly ash and cinders is believed to reduce cycle time for forming the thermoplastic compound into a plastic product from about 5 percent to about 30 percent merely because of the presence of the processed fly ash and cinders.
|Novel inhibitors of proliferation and activation of signal transducer and activator of transcription (stats)|
Pyridine compounds effective in modulation stat3 and/or stat5 activation are provided that are useful in the prevention and treatment of proliferative disease and conditions including cancer, inflammation and proliferative skin disorders.. .
|Water soluble salts of aldose reductase inhibitors for treatment of diabetic complications|
The present invention relates to pharmaceutically acceptable water soluble salts of aldose reductase inhibitors, 2-(8-oxo-7-((5-trifluromethyl)-1h-benzo[d]imidazol-2-yl)methyl)7,8-dihydropyrazin[2,3-d]pyridazin-5-yl)acetic acid and [4-oxo-(5-trifluoromethyl-benzothaiazol-2-ylmethyl)-3,4-dihydro-phthalazin-1-yl]-acetic acid (also known as zopolrestat), pharmaceutical compositions thereof and methods of treating diabetic complications in mammals comprising administering to mammals these salt and compositions.. .
|Long acting biologically active luteinizing hormone (lh) compound|
The present invention relates to a long acting biologically active luteinizing hormone (lh) compound comprising an lh agonist linked to a pharmaceutically acceptable molecule providing an in vivo plasma half-life of the lh agonist or lh compound which is increased substantially compared to the in vivo plasma half-life of an lh agonist administered in the same manner as the lh compound. The present invention relates to methods for controlled ovarian stimulation which can be used in conjunction with assisted reproduction technologies such as in vitro fertilisation, intra cytoplasmatic sperm injection, intra uterine insemination and in vitro maturation.
|Biomarkers, methods, and compositions for inhibiting a multi-cancer mesenchymal transition mechanism|
The present invention relates to the discovery that the modulation of particular micrornas can be employed to inhibit a mesenchymal transition that, in certain instances, correlates with resistance to therapy and recurrence as the corresponding cells acquire properties of stem cells as they start undergoing this transition, as well as with invasiveness, e.g., invasion of certain cells of primary tumors into adjacent connective tissue during the initial phase of metastasis. Accordingly, the identification inhibitors of this mechanism, such as inhibitors of certain micrornas, disclosed herein, can be used for inhibiting the mesenchymal transition to reduce the invasive nature of certain cells of primary cancerous tumors and, in certain instances, to prevent the recurrence of cancer by inhibiting the induction of stem cell-like features in certain cancer cells..
|Systems and methods for superconducting integrated circuits|
A superconducting integrated circuit may include a magnetic flux transformer having an inner inductive coupling element and an outer inductive coupling element that surrounds the inner inductive coupling element along at least a portion of a length thereof. The magnetic flux transformer may have a coaxial-like geometry such that a mutual inductance between the first inductive coupling element and the second inductive coupling element is sub-linearly proportional to a distance that separates the first inner inductive coupling element from the first outer inductive coupling element.
An ammonia-producing catalyst includes a p-type semiconductor, an n-type semiconductor, and a metal fine particle having a function of adsorbing nitrogen. In the ammonia-producing catalyst including the metal fine particle, generation of ammonia is promoted, and the generated amount of ammonia is increased.
A speed reducer includes an internal gear, an input shaft coaxial with the internal gear, and an eccentric disk on the input shaft and rotatable inside the internal gear, and an eccentric disk on the input shaft and rotatable inside the internal gear. A cage at an end of an output shaft, coaxial with the input shaft, and rotatable between the internal gear and the eccentric disk has pockets fewer in number than the internal gear's internal teeth.
|Motor vehicle noise management|
A device and method that is configured to control the operation of a motor vehicle cabin active sound management (asm) system that uses an asm controller to control operation of one or more sound transducers that transmit audio signals in the cabin so as to alter vehicle powertrain-related sounds in the cabin, wherein the motor vehicle further comprises a mobile telephone system that is configured to receive incoming mobile telephone calls and transmit outgoing mobile telephone calls. The device can include a controller that is configured to receive from the mobile telephone system an indication that a mobile telephone call is incoming or an outgoing call is being initiated.
|Semiconductor circuit, d/a converter, mixer circuit, radio communication device, method for adjusting threshold voltage, and method for determining quality of transistor|
According to an embodiment, a semiconductor circuit includes a substrate, a tunnel oxide film, a charge storage film, a blocking layer, and plural nodes. The substrate is made of a semiconductor in which two diffusion layers each serving as either a source or a drain are formed.
|Methods and apparatus for improving remote nfc device detection using an oscillator circuit|
A method, an apparatus, and a computer program product for wireless and/or inductive communications are provided in connection with improving remote nfc device detection through use of an oscillator circuit connected to an nfc antenna and matching network. In one example, a communications device is equipped to monitor frequency oscillations generated by an oscillator circuit associated with a transmitter path of a nfc antenna and matching network, determine that a number of occurrences of the frequency oscillations from a reference frequency is greater than a frequency deviation threshold, and perform a nfc polling procedure in response to the determination..
|Conductive chemical mechanical planarization polishing pad|
A polishing pad for polishing a substrate. The pad comprises a layer of material having an upper polishing surface and a lower surface interfacing with a proximate platen, the material comprising a mixture of a conductive polymer distributed in a structure of a dielectric polymeric material using predetermined relationships.
|Chemical mechanical planarization platen|
A method and system for planarizing or polishing a semiconductor wafer. The system includes a carrier adaptable to hold a semiconductor wafer, a polishing pad, and a platen having a substantially planar surface in contact with the polishing pad, the planar surface having a distribution of holes.
|Interdigitated chip capacitor assembly|
An interdigitated chip capacitor (“idc”) assembly including an idc having a semiconductor block with a top portion, a bottom portion opposite the top portion, a plurality of sidewall portions extending between the top and bottom portions, and a plurality of terminals located on the sidewall portions; and a substrate having a top portion with a plurality of generally flat, vertically extending, nonconductive abutment surfaces thereon, the sidewall portions of the idc being abuttingly engaged with at least some of the plurality of abutment surfaces.. .
|Apparatus and methods for improving the intensity profile of a beam image used to process a substrate|
Methods and apparatuses are provided for improving the intensity profile of a beam image used to process a semiconductor substrate. At least one photonic beam may be generated and manipulated to form an image having an intensity profile with an extended uniform region useful for thermally processing the surface of the substrate.
|Remote plasma radical treatment of silicon oxide|
Embodiments described herein generally relate to methods for manufacturing flash memory devices. In one embodiment, the method includes generating a plasma comprising nitrogen-containing radicals in a remote plasma applicator, flowing the plasma comprising nitrogen-containing radicals into a processing region of the processing chamber where a semiconductor device is disposed, wherein the semiconductor device has a substrate comprising an oxide layer formed thereon, exposing an exposed surface of the oxide layer to the nitrogen-containing radicals, and incorporating nitrogen in the exposed surface of the oxide layer of the substrate..
|Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium|
A method of manufacturing a semiconductor device is disclosed. The method includes forming a thin film containing a predetermined element, boron, carbon, and nitrogen on a substrate by performing a cycle a predetermined number of times.
|Semiconductor processing systems having multiple plasma configurations|
An exemplary system may include a chamber configured to contain a semiconductor substrate in a processing region of the chamber. The system may include a first remote plasma unit fluidly coupled with a first access of the chamber and configured to deliver a first precursor into the chamber through the first access.
|Methods for fabricating integrated circuits with improved semiconductor fin structures|
Methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes providing a mandrel layer overlying a semiconductor substrate and patterning the mandrel layer into mandrel structures.
|Semiconductor device manufacturing method|
In a semiconductor device manufacturing method having a plasma etching process, a substrate is plasma etched using a resist layer as a mask. The plasma etching process has: a first etching step wherein a mixed gas having a deposition gas and an etching gas mixed at a ratio is introduced into the processing chamber, and the substrate is plasma etched in the mixed gas atmosphere; and a step of repeating multiple times a deposition step, wherein the deposition gas is introduced into the processing chamber, and the plasma-etched substrate is subjected to deposition treatment in an atmosphere having the deposition gas as a main component, and a second etching step, wherein the etching gas is introduced into the processing chamber, and the substrate that has been subjected to the deposition treatment in the deposition step is plasma etched in an atmosphere having the etching gas as a main component..
|Semiconductor device and process for producing the same|
A semiconductor device having a contact structure is provided. The semiconductor device includes: a conductive region; a first film and a second film which are formed over the conductive region to realize a layer; and a contact electrode which extends through the layer to the conductive region, and is formed so as to replace a portion of the layer with a portion of the contact electrode, where the portion of the layer is constituted by only the first film, only the second film, or both of a portion of the first film and a portion of the second film, and the portion of the first film occupies a major part of the portion of the layer..
|Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region|
A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case, capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions.
|Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via|
A method for fabricating through-silicon vias (tsvs) for semiconductor devices is provided. Specifically, the method involves utilizing copper contact pads in a back-end-of-line wiring level, wherein the copper contact pads act as cathodes for performing an electroplating technique to fill tsvs with plated-conductive material (e.g., copper) from an electroplating solution.
|Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regions|
One method disclosed includes forming a sidewall spacer proximate a gate structure, forming a sacrificial layer of material above a protective cap layer, the sidewall spacer and a substrate, forming a sacrificial protection layer above the sacrificial layer, reducing a thickness of the sacrificial protection layer such that its upper surface is positioned at a level that is below the upper surface of the protective cap layer, performing a first etching process to remove a portion of the sacrificial layer and thereby expose the protective cap layer for further processing, performing a wet acid etching process that includes diluted hf acid in the etch chemistry to remove the protective cap layer and performing at least one process operation to remove at least one of the reduced-thickness sacrificial protection layer or the sacrificial layer from above the surface of the substrate.. .
|Semiconductor device and method for fabricating the same|
A method of fabricating a semiconductor device includes forming a first gate pattern and a dummy gate pattern on a first active area and a second active area of a substrate, respectively, the first gate pattern including a first gate insulating layer and a silicon gate electrode, removing the dummy gate pattern to expose a surface of the substrate in the second active area, forming a second gate pattern including a second gate insulating layer and a metal gate electrode on the exposed surface of the substrate, the first gate insulating layer having a thickness larger than a thickness of the second gate insulating layer, and forming a gate silicide on the silicon gate electrode after forming the second gate pattern.. .
|Self-aligned insulating etchstop layer on a metal contact|
A semiconductor device comprising a substrate having a transistor that includes a metal gate structure; a first oxide layer formed over the substrate; a silane layer formed on the first oxide layer; and a non-conductive metal oxide layer grown on the metal gate structure, wherein the silane layer inhibits nucleation and growth of the non-conductive metal oxide layer.. .
|Method of making a gas distribution member for a plasma processing chamber|
A method of making a si containing gas distribution member for a semiconductor plasma processing chamber comprises forming a carbon member into an internal cavity structure of the si containing gas distribution member. The method includes depositing si containing material on the formed carbon member such that the si containing material forms a shell around the formed carbon member.
|Method for producing group iii nitride semiconductor|
Group iii nitride semiconductor having reduced threading dislocation density and uniform ga-polar surface is provided. Forming a capping layer on a buffer layer containing al as an essential element at a temperature lower than a temperature at which an oxide of element constituting the buffer layer is formed.
|Methods of forming a metal telluride material, related methods of forming a semiconductor device structure, and related semiconductor device structures|
Accordingly, a method of forming a metal chalcogenide material may comprise introducing at least one metal precursor and at least one chalcogen precursor into a chamber comprising a substrate, the at least one metal precursor comprising an amine or imine compound of an alkali metal, an alkaline earth metal, a transition metal, a post-transition metal, or a metalloid, and the at least one chalcogen precursor comprising a hydride, alkyl, or aryl compound of sulfur, selenium, or tellurium. The at least one metal precursor and the at least one chalcogen precursor may be reacted to form a metal chalcogenide material over the substrate.
|Semiconductor nanocrystals and methods|
In one embodiment, a method for forming a coating comprising a semiconductor material on at least a portion of a population of semiconductor nanocrystals comprises providing a first mixture including semiconductor nanocrystals and an aromatic solvent, introducing one or more cation precursors and one or more anion precursors into the first mixture to form a reaction mixture for forming the semiconductor material, reacting the precursors in the reaction mixture, without the addition of an acid compound, under conditions sufficient to grow a coating comprising the semiconductor material on at least a portion of an outer surface of at least a portion of the semiconductor nanocrystals, and wherein an amide compound is formed in situ in the reaction mixture prior to isolating the coated semiconductor nanocrystals. In another embodiment, method for forming a coating comprising a semiconductor material on at least a portion of a population of semiconductor nanocrystals comprises providing a first mixture including semiconductor nanocrystals and a solvent, introducing an amide compound, one or more cation precursors and one or more anion precursors into the first mixture to form a reaction mixture for forming the semiconductor material, and reacting the precursors in the reaction mixture in the presence of the amide compound, under conditions sufficient to grow a coating comprising the semiconductor material on at least a portion of an outer surface of at least a portion of the semiconductor nanocrystals.
|Bottom-up peald process|
The present disclosure relates to a method and apparatus for performing a plasma enhanced ald (peald) process that provides for improved step coverage. The process introduces a precursor gas into a processing chamber comprising a semiconductor workpiece.
|Shallow trench isolation integration methods and devices formed thereby|
Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a tsv device having a “buffer zone” or gap layer between the tsv and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices.
|Methods of fabricating semiconductor devices including fin-shaped active regions|
A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.. .
|Methods of fabricating semiconductor device having shallow trench isolation (sti)|
Methods of fabricating a semiconductor device include forming a field trench in a silicon substrate, forming a first oxide layer in the field trench, forming a first thinned oxide layer by partially removing a surface of the first oxide layer, and forming a first nitride layer on the first thinned oxide layer.. .
|Semiconductor device having gate trench and manufacturing method thereof|
Disclosed herein is a semiconductor device that includes a trench formed across active regions and the element isolation regions. A conductive film is formed at a lower portion of the trench, and a cap insulating film is formed at an upper portion of the trench.
|Semiconductor device and fabricating method of the same|
Openings are formed by lithography and subsequent dry etching at the portions of a first protective film which correspond to connecting holes of second plugs which will be described later, namely at the portions thereof which align with first plugs, wherein the openings have a diameter greater than that of connecting holes by about 0.4 μm.. .
|Semiconductor device and method for manufacturing the same|
A semiconductor device and a method for manufacturing the same are disclosed. An additional spacer is formed at a lateral surface of an upper part of the bit line so that the distance of insulation films between a storage node and a neighboring storage node contact plug is increased.
|Semiconductor device and method of fabricationg the same|
A method of fabricating a semiconductor device includes forming first gate patterns on a semiconductor substrate using an etch mask pattern, forming a trench in the semiconductor substrate between the first gate patterns, forming an insulating layer in the trench, such that the insulating layer fills the trench and is disposed on the etch mask pattern, planarizing the insulating layer until a top surface of the etch mask pattern is exposed, etching a portion of the planarized insulating layer to form a device isolation layer in the trench, forming a second gate layer covering the etch mask pattern and disposed on the device isolation pattern, and planarizing the second gate layer until the top surface of the etch mask pattern is exposed, such that a second gate pattern is formed.. .
|Method for fabricating a semiconductor device|
A method for fabricating a semiconductor device includes forming a pre-isolation layer covering a fin formed on a substrate, the pre-isolation layer including a lower pre-isolation layer making contact with the fin and an upper pre-isolation layer not making contact with the fin, removing a portion of the upper pre-isolation layer by performing a first polishing process, and planarizing the pre-isolation layer such that an upper surface of the fin and an upper surface of the pre-isolation layer are coplanar by performing a second polishing process for removing the remaining portion of the upper pre-isolation layer.. .
|Methods of forming multiple n-type semiconductor devices with different threshold voltages on a semiconductor substrate|
One illustrative method disclosed herein involves forming an integrated circuit product comprised of first and second n-type transistors formed in and above first and second active regions, respectively. The method generally involves performing a common threshold voltage adjusting ion implantation process on the first and second active regions, forming the first and second transistors, performing an amorphization ion implantation process to selectively form regions of amorphous material in the first active region but not in the second active region, after performing the amorphization ion implantation process, forming a capping material layer above the first and second transistors and performing a re-crystallization anneal process to convert at least portions of the regions of amorphous material to a crystalline material.
|Method of manufacturing a semiconductor device|
A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n+-type semiconductor regions for a source or a drain of misfet are formed in the peripheral circuit region.
|3d structured memory devices and methods for manufacturing thereof|
A 3d structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region.
|Three-dimensional semiconductor memory devices and methods of fabricating the same|
Example embodiments relate to a three-dimensional semiconductor memory device including an electrode structure on a substrate, the electrode structure including at least one conductive pattern on a lower electrode, and a semiconductor pattern extending through the electrode structure to the substrate. A vertical insulating layer may be between the semiconductor pattern and the electrode structure, and a lower insulating layer may be between the lower electrode and the substrate.
|Method of manufacturing semiconductor device|
Provided is a semiconductor device having improved performance. In a semiconductor substrate located in a memory cell region, a memory cell of a nonvolatile memory is formed while, in the semiconductor substrate located in a peripheral circuit region, a misfet is formed.
|Method of manufacturing semiconductor device|
A method of manufacturing a semiconductor device which includes forming first and second gate patterns, forming first and second sidewall spacers on sidewalls of the first and second gate patterns respectively, implanting a first impurity into the semiconductor substrate, forming a third sidewall spacer on the first sidewall spacer and a fourth sidewall spacer on the second sidewall spacer in such a manner that the third sidewall spacer is in contact with the fourth sidewall spacer between the first and second gate patterns, implanting a second impurity into the semiconductor substrate, and removing the third and the fourth sidewall spacers.. .
|Lateral super junction device with high substrate-gate breakdown and built-in avalanche clamp diode|
A lateral super junction jfet is formed from stacked alternating p type and n type semiconductor layers over a p-epi layer supported on an n+ substrate. An n+ drain column extends down through the super junction structure and the p-epi to connect to the n+ substrate to make the device a bottom drain device.
|Nitride based semiconductor device and method for manufacturing the same|
Disclosed herein is a nitride based semiconductor device including: a base substrate; an epitaxial growth layer disposed on the base substrate and generating a 2-dimensional electron gas in an inner portion thereof; and an electrode structure disposed on the epitaxial growth layer, wherein the electrode structure includes: a gate electrode; a source electrode disposed at one side of the gate electrode; and a drain electrode disposed at the other side of the gate electrode and having an extension part extended to the inner portion of the epitaxial growth layer to contact the 2-dimensional electron gas.. .
|Semiconductor packages and methods of packaging semiconductor devices|
A device is disclosed. The device includes a carrier substrate having first and second major surfaces.
|Dye-sensitized solar cell and method for manufacturing the same|
Provided is a dye-sensitized solar cell, and a method for manufacturing the same, that in a technology in which a current collector electrode is used instead of a transparent conductive film, can be manufactured by a simple cell producing operation and is capable of achieving a desirably thin thickness for the current collector electrode. A dye-sensitized solar cell 10 includes a transparent substrate 12 provided on the side where solar light is incident, a conductive substrate 14 that serves as a cathode and is provided opposite the transparent substrate 12, a porous semiconductor layer 16, a porous conductive metal layer 18 that serves as a current collector electrode, and a porous insulating layer 20.
|Method for treating a semiconductor|
Methods for treating a semiconductor material, and for making devices containing a semiconducting material, are presented. One embodiment is a method for treating a semiconductor material that includes a chalcogenide.
|Semiconductor structure with lamella defined by singulation trench|
A method for fabricating a semiconductor structure includes etching a first opening into a substrate; etching a chip singulation trench into the substrate to define a lamella between the first opening and the chip singulation trench; fabricating a sense element for sensing a deflection of the lamella; and singulating the semiconductor structure at the chip singulation trench.. .
|Method to package multiple mems sensors and actuators at different gases and cavity pressures|
A method for fabricating a multiple mems device. A semiconductor substrate having a first and second mems device, and an encapsulation wafer with a first cavity and a second cavity, which includes at least one channel, can be provided.
|Method of manufacturing light-emitting device|
An led includes a compound semiconductor structure having first and second compound layers and an active layer, first and second electrode layers atop the second compound semiconductor layer and connected to respective compound layers. An insulating layer is coated in regions other than where the first and second electrode layers are located.
|Method for producing an optoelectronic device with wireless contacting|
A method for producing an optoelectronic device is provided, in which a luminescent diode chip (10) is mounted on a base surface (8) on the first terminal area (1) of a carrier (3). An electrically insulating layer (4) is applied to side faces (17) of the luminescent diode chip (10).
|Semiconductor manufacturing apparatus and manufacturing method of semiconductor device|
A semiconductor manufacturing apparatus according to the present embodiment includes a vacuum chamber. A stage mounts a semiconductor substrate thereon within the vacuum chamber.
|System and process to remove film from semiconductor devices|
Embodiments of the present disclosure are a method of forming a semiconductor device, a method of forming a magnetic tunnel junction (mtj) device, and a process tool. An embodiment is a process tool comprising an ion beam etch (ibe) chamber, an encapsulation chamber, a transfer module interconnecting the ibe chamber and the encapsulation chamber, the transfer module being capable of transferring a workpiece from the ibe chamber to the encapsulation chamber without exposing the workpiece to an external environment..
|Process to remove film from semiconductor devices|
Embodiments of the present disclosure are a method of forming a semiconductor device, a method of forming an mram device, and a method of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method comprising forming a second layer over a first layer, and performing a first etch process on the second layer to define a feature, wherein the first etch process forms a film on a surface of the feature.
|Crispr-cas systems and methods for altering expression of gene products|
The invention provides for systems, methods, and compositions for altering expression of target gene sequences and related gene products. Provided are vectors and vector systems, some of which encode one or more components of a crispr complex, as well as methods for the design and use of such vectors.
|Retroviral vector particles and methods for their generation and use|
The present invention relates to methods of host cell transduction utilising ecotropic retroviral vector particles. The retroviral vector particle may comprise an envelope of friend murine leukaemia virus, in particular the envelope encoded by molecular clone pvc-211 and the host cell may be engineered to recombinantly express the rec1 receptor.
|Method for enhancing the fermentative potential and growth rate of microorganisms under anaerobiosis|
The present invention concerns a method for enhancing the growth rate, the biomass production and/or the fermentative potential of an anaerobic microorganism, comprising the steps consisting in: (a) modifying said anaerobic microorganism by inactivating the ohrr gene, the ohrr gene product or homolog thereof; (b) culturing the modified anaerobic microorganism obtained in step (a) under low-orp anaerobic conditions.. .
|N-demethyase genes and uses thereof|
The invention provides isolated nucleic acid encoding one or more gene products that allow for degradation of caffeine and related structures, and for preparation of intermediates in that catabolic pathway. Further provided are methods of using one or more of those gene products..
|Interactive education and entertainment system having digital avatar and physical toy|
An interactive educational and entertainment system comprised of a toy as an avatar in the physical world and a digital environment, where the represented avatar has a corresponding physical toy. The system enables three way communications among the player, the physical toy and the digital environment or the avatar presented in digital environment.
|Method and system for implementing a comprehensive, nation-wide, cloud-based education support platform|
A system is disclosed for a software-as-a-service platform supporting every level of a national educational system. The system organizes users into subgroups based upon the users' level and function in the educational hierarchy; for example, teachers or parents at school could share a user group.
|Battery cell assembly and method for manufacturing the battery cell assembly|
A battery cell assembly is provided. The battery cell assembly includes a cooling fin having first and second plate portions and a first thermally conductive layer.
|Conductive layer and preparation method for conductive layer|
Provided are a conductive layer and a method of manufacturing the same. The conductive layer is formed without, so called, a high temperature process but has suitable crystallinity, excellent transparency and excellent resistance characteristic, and the method of manufacturing the same is also provided..
|Thermally conductive polymer composite material and an article comprising same|
A thermally conductive polymer composite material and an article including the same. The thermally conductive polymer composite material includes 15 to 20 parts by weight of a wholly aromatic liquid crystalline polyester resin; and 80 to 85 parts by weight of a thermally conductive additive..
|Film-forming material, group iv metal oxide film and vinylenediamide complex|
An object of the present invention is to provide a method for producing a group iv metal oxide film useful as a semiconductor element or an optical element at a low temperature. The present invention relates to a method for producing a group iv metal oxide film, comprising coating a surface of a substrate with a film-forming material dissolved in an organic solvent, and subjecting the substrate to a heat treatment, an ultraviolet irradiation treatment, or both of these treatments, wherein a film-forming material obtained by reacting a vinylenediamide complex having a specific structure with an oxidizing agent such as oxygen gas, air, ozone, water and hydrogen peroxide is used as the film-forming material..
|Method for forming patterned conductive film|
According to the present invention, there is provided a method for forming a patterned conductive layer, which can ensure electrical bonding with a substrate and also can be suitably applied to various electronic devices, simply without requiring a massive and heavy apparatus.. .
|Treating inflammation with a combination of an ellagitannin and hydrogen peroxide|
The teachings provided herein generally relate to site-activated binding systems that selectively increase the bioactivity of phenolic compounds at target sites. More particularly, the systems taught here include a phenolic compound bound to a reactive oxygen species, wherein the phenolic compound and the reactive oxygen species react at a target area in the presence of an oxidoreductase enzyme..
|Microcapsules having an envelope composed essentially of silsesquioxane homopolymers or copolymers|
A microcapsule having a reservoir that includes a core containing at least one active principle, the core being surrounded by a polymer shell, is presented. The polymer shell contains 50% to 100% by weight of a silsesquioxane compound with respect to the total weight of the shell.
|Immunogenic compositions against human progastrin peptides|
Immunogens against human extended-progastrin species comprise (a) a mimetic peptide comprised of (i) the amino acid sequence of a progastrin or a n- and/or c-terminal processed species of a progastrin joined to (ii) a 7 amino-acid spacer coupled to (b) an immunogenic carrier. Illustrative of the mimetic peptide/spacer combination are a 21 amino-acid peptide (seq id no.: 1) and other, related polypeptides (seq id nos.: 2-5).
|Inhibition of innate immune response|
The present invention provides methods, kits, and compositions for reducing an innate immune system response in a human or animal cell, tissue or organism. One embodiment comprises: introducing an agent mrna comprising in vitro-synthesized mrna encoding one or more proteins that affect the induction, activity or response of an innate immune response pathway; whereby, the innate immune response in the cell, tissue or organism is reduced compared to the innate immune response in the absence of the agent mrna.
|Pd-1 antagonists and methods for treating infectious disease|
Methods and compositions for treating an infection or disease that results from (1) failure to elicit rapid t cell mediated responses, (2) induction of t cell exhaustion, t cell anergy or both, or (3) failure to activate monocytes, macrophages, dendritic cells and/or other apcs, for example, as required to kill intracellular pathogens. The method and compositions solve the problem of undesired t cell inhibition by binding to and blocking pd-1 to prevent or reduce inhibitory signal transduction, or by binding to ligands of pd-1 such as pd-l1, thereby preventing (in whole or in part) the ligand from binding to pd-1 to deliver an inhibitory signal.
|Nanoparticle delivery compositions|
Nanoparticle delivery systems for use in targeting biologically active agents to the central nervous system comprise a composition comprising (a) a nanoparticle comprising: (i) a core comprising a metal and/or a semiconductor; and (ii) a corona comprising a plurality of ligands covalently linked to the core, wherein said ligands comprise a carbohydrate, insulin and/or a glutathione; and (b) the at least one agent to be delivered to the cns. Methods of treatment and diagnosing cns disorders utilising the nanoparticle delivery systems and related screening methods are also disclosed..
|Microfluidic device and method|
A microfluidic device includes a semiconductor chip having a main chip surface. The microfluidic device further includes an encapsulation body embedding the semiconductor chip, the encapsulation body having a main body surface.
|Urea spray scr control system|
A urea spray selective catalytic reduction (“scr”) control system includes an scr catalyst provided in a discharge pipe of an engine, a dosing valve for injecting urea water at an upstream side of the scr catalyst, and nox sensors, wherein the system controls injection of the urea water from the dosing valve. The system includes a plurality of nox model maps corresponding to an atmospheric pressure condition, an outdoor air temperature, and an engine water temperature, and determines an amount of nox from each nox model map on a basis of detection values of an atmospheric pressure detector, an outdoor air temperature detector, and an engine water temperature detector, and controls an amount of injection of the urea water from the dosing valve on a basis of the amount of nox thus determined..
|Device for packaging and applying a solid cosmetic product|
The invention relates to a device for packaging a cosmetic product (p) in solid form and applying it to the skin, having a longitudinal axis x, comprising: a sleeve (70) containing the cosmetic product (p), an elevator means (50) able to support the cosmetic product (p) at a current position in the sleeve and to axially move the cosmetic product along the axis x to make it emerge from the sleeve (70) bypassing through the orifices (77), a means (60) for manually actuating the elevator, a means (80) for partial covering of the outlet of the sleeve (70) comprising a vault (71) formed solely of an elastically deformable material.. .
|Fuser for preventing excessive increased temperature in paper non-passing region|
A fuser includes an endless heat generating part including a conductive layer, an induced current generating part to heat the conductive layer by electromagnetic induction, and a magnetic shunt metal member that is located at a side opposite to the induced current generating part across the heat generating part, forms a first gap between the magnetic shunt metal member and the heat generating part in a first paper passing region of the heat generating part, and forms a second gap, which is different from the first gap in size, between the magnetic shunt metal member and the heat generating part in a second paper passing region different from the first paper passing region.. .
|Image forming apparatus|
An image forming apparatus may include exposure members, a drum supporting member, guide members configured to support the drum supporting member, a main body circuit board and a relay board. The drum supporting member may include a pair of side walls spaced apart from each other and configured to support photoconductor drums and the exposure members therebetween.