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Duc patents

      

This page is updated frequently with new Duc-related patent applications.




 Thermal interface foil patent thumbnailThermal interface foil
A method of producing a power electronic assembly and a power electronic assembly comprising a power electronic module incorporating multiple of semiconductor power electronic switch components, the power electronic module comprising a bottom surface, the power electronic assembly comprises further a cooling arrangement for cooling the power electronic module, the cooling arrangement comprising a cooling surface adapted to be attached against the bottom surface of the power electronic module, wherein the power electronic assembly comprises further a thermal interface material arranged between the bottom surface of the power electronic module and the cooling surface of the cooling arrangement to transfer heat from the power electronic module to the cooling arrangement, the thermal interface material comprises an aluminium foil having a polymer coating.. .
Abb Technology Oy


 Thin film surface mount components patent thumbnailThin film surface mount components
Surface mount components and related methods involve thin film circuits between first and second insulating substrates. The thin film circuits may include passive components, including resistors, capacitors, inductors, arrays of such components, networks, or filters of multiple passive components.
Avx Corporation


 Method for producing conductive member, and conductive member patent thumbnailMethod for producing conductive member, and conductive member
Provided is a method for producing a conductive member including: forming a first silver halide emulsion layer, a light absorption layer, and a second silver halide emulsion layer on a transparent support in this order; performing pattern exposure on the first silver halide emulsion layer; and the second silver halide emulsion layer and applying a development treatment thereto to obtain a conductive layer comprising a thin metal wire, in which the light absorption layer absorbs at least some of the wavelengths of light to which the first silver halide emulsion layer or the second silver halide emulsion layer is exposed.. .
Fujifilm Corporation


 Driving several light sources patent thumbnailDriving several light sources
A device for driving several light sources is provided, wherein the several light sources are arranged in a matrix structure; wherein the several light sources of the matrix structure are connected to a semiconductor device; wherein a portion of the semiconductor device corresponds to a light source of the matrix structure, wherein the portion of the semiconductor device comprises a diagnosis function which when activated is arranged for supplying an output diagnosis signal.. .
Infineon Technologies Ag


 System and  processing solids and liquids patent thumbnailSystem and processing solids and liquids
A magnetic induction heating element is used for outputting a magnetic field corresponding to an electrical current passing through the magnetic induction element. The magnetic induction element is placed close to or attached to a vessel in which a material containing a mixture of solids and liquids is to be processed to reduce the volume of liquid in the solid through evaporation.

 Method and  determining that an almost-contiguous resource allocation a-mpr applies to an uplink transmission patent thumbnailMethod and determining that an almost-contiguous resource allocation a-mpr applies to an uplink transmission
A method and apparatus determine that an almost-contiguous resource allocation additional maximum power reduction (a-mpr) applies to an uplink transmission power. An indication of a resource allocation of resource blocks for a transmission can be received.
Motorola Mobility Llc


 Optical and capacitive sensing of electroacoustic transducers patent thumbnailOptical and capacitive sensing of electroacoustic transducers
Speakers do not always operate linearly. Linearity of the speaker can affect the quality of the sound produced by the speaker, i.e., causing distortions in the sound, if the nonlinearites are not accounted for.
Analog Devices, Inc.


 Automatic gain control for implanted microphone patent thumbnailAutomatic gain control for implanted microphone
A method for use in an implantable hearing instrument, including receiving an output signal from an implanted microphone implanted in a person, identifying a first characteristic of said output signal, based on said first characteristic, amplifying said microphone output signal by at least one of a plurality of gain settings to produce an amplified signal, wherein said plurality of gain setting comprise at least two different gain settings, inputting said amplified signal into a signal processor, processing said amplified signal to generate a transducer drive signal; and using said transducer drive signal to drive implanted auditory stimulation device implanted in a person to stimulate an auditory component.. .

 Speaker device patent thumbnailSpeaker device
Acoustic conversion efficiency is improved and a stable signal reproduction operation is ensured. Provided is a speaker device including: a magnet a yoke attached to the magnet and, at least one sub-plate that is separated from the main plate in an axial direction of the central axis; a coil bobbin formed in a tubular shape and changeable in the axial direction; a voice coil wound around an outer circumferential surface of the coil bobbin, at least a portion of the voice coil being disposed in a main magnetic gap formed between the main plate and the yoke; a vibration plate having an inner circumferential portion connected to the coil bobbin; and a magnetic fluid filling at least one sub-magnetic gap formed between the sub-plate and the yoke, wherein a through-hole positioned in the sub-magnetic gap filled with the magnetic fluid is formed in the coil bobbin..
Sony Corporation


 Inertial electroacoustic transducer unit patent thumbnailInertial electroacoustic transducer unit
Inertial electroacoustic transducer unit (300; 400) comprising a first exciter (100) and a second exciter (200), the second exciter (200) is disposed in overturned position on the first exciter (100), that is to say in a first configuration the bases (41) of the two cups (40) face each other, or in a second configuration the cavities of the two cups face each other; the two exciters (100, 200) are fixed together or to a plane intended to be put into vibration in such manner that the axes (a) of the cylindrical supports (10) of the coils coincide, the ends of the coils (1) of the two exciters being connected in counter-phase in such manner to obtain a consistent movement in the same direction as the magnetic units (4) of the two exciters.. .
Ask Industries Societa' Per Azioni


Electro-acoustic transducer with radiating accoustic seal and stacked magnetic circuit assembly

An electro-acoustic transducer includes an accordion-type structure that functions as both an acoustic radiation element and an acoustic seal. In one example, the transducer includes parallel, accordion-type structures that attach to a flat, rectangular diaphragm.
Bose Corporation

Electro-acoustic transducer with radiating accoustic seal and stacked magnetic circuit assembly

An electro-acoustic transducer includes an accordion-type structure that functions as both an acoustic radiation element and an acoustic seal. In one example, the transducer includes parallel, accordion-type structures that attach to a flat, rectangular diaphragm.
Bose Corporation

Systems and methods for improved audio output in electronic devices

Embodiments are provided for devices for audio playback and configuring devices for audio playback. According to certain aspects, an electronic device is configured with an exterior casing that has a cutout area formed thereon.
Google Inc.

Diaphragm, electroacoustic transducer, and electroacoustic transducer apparatus

A diaphragm is provided that has small mechanical anisotropy even when heat is applied to the diaphragm in the production process. The diaphragm includes a biaxially stretched film stretched in a first direction (the machine direction) and a second direction (the transverse direction), wherein the entire surface of the biaxially stretched film has a first pattern and a second pattern, the first pattern has ridges and grooves with a first pitch, the second pattern has ridges and grooves with a second pitch, the second pitch is smaller than the first pitch, the second pattern is formed along the first direction or the second direction, and the length of regions defined by the first pattern in the first direction differs from the length of the regions in the second direction..
Kabushiki Kaisha Audio-technica

Wireless audio system

A wireless audio system may be configured with a mobile communication device that is concurrently wirelessly connected to first and second monitors, respectively, via first and second wireless pathways. The first and second wireless pathways can be different and provide stereo audio reproduction with the first and second monitors with 5 ms of latency or less..
Fender Musical Instruments Corporation

Systems and methods for audio creation and delivery

Systems and methods of providing an audio signal are disclosed herein. In one embodiment, a method of producing an audio signal includes applying, for example, a head related transfer function (hrtf) and a transducer position compensation filter to an input audio signal to generate an enhanced audio signal configured to be transmitted toward an entrance of the user's ear from a transducer carried by a headset and spaced apart from the entrance to a user's ear..

Compact electroacoustic transducer and loudspeaker system and use thereof

An improved compact electroacoustic transducer and loudspeaker system. The electroacoustic transducer (or array of electroacoustic transducers) can generate the desired sound by the use of pressurized airflow.
Clean Energy Labs, Llc

Reproduction method and reproduction apparatus

In a reproduction method, a first video stream has a first dynamic range where a maximum value of a luminance dynamic range is more than 100 nits, and a display apparatus displays video in a second dynamic range narrower than the first dynamic range. The method includes: determining whether the first video stream is quantized based on a hybrid oetf; (i) when it is determined that the first video stream is quantized based on the hybrid oetf, reproducing the first video stream; and (ii) when it is determined that the first video stream is not quantized based on the hybrid oetf, converting a luminance dynamic range of the first video stream from the first dynamic range to the second dynamic range to obtain a second video stream, and reproducing the second video stream..
Panasonic Intellectual Property Management Co., Ltd.

Streaming reproduction device, audio reproduction device, and audio reproduction method

A streaming reproduction device according to the present disclosure includes a decoder for decoding a file transmitted from a library, an image reproduction device for reproducing an image decoded in the decoder, an audio reproduction device for reproducing an audio decoded in the decoder, and a synchronizer for synchronizing image information with audio information to output the synchronized information. In accordance with the present disclosure, regardless of file information and a communication environment, the stereo extension device may be optimally activated, a sound quality may be improved, and stereo may be stably provided under a streaming environment..
Gwangju Institute Of Science And Technology

Extremely high frequency converter

An extremely high frequency (ehf) protocol converter may include a transducer, an ehf communication circuit, a protocol conversion circuit, and a circuit port. The transducer may be configured to convert between an electromagnetic ehf data signal and an electrical ehf signal.
Keyssa, Inc.

Content provision system, information processing apparatus and content reproduction method

There is provided a content provision system including an information processing apparatus and a terminal device wherein the information processing apparatus provides a content that includes images respectively captured at discrete capturing locations to the terminal device, the information processing apparatus comprising: a retrieving unit configured to retrieve the content and a position information item associated with the content; and a transmission unit configured to transmit the content and the position information item to the terminal device; the terminal device comprising: a reception unit configured to receive the content and the position information item; and a content reproduction unit configured to reproduce the content by selecting an image to be displayed and displaying a partial area of the selected image, the displayed partial area being extracted from the selected image to show a view in a direction of the designated position for at least one of the images.. .
Ricoh Company, Ltd.

Methods for reconfiguring directional couplers in an rf transceiver

Provided herein are methods of reconfiguring directional couplers in an rf transceiver. The methods can include designing and reconfiguring the directional couplers to provide high directivity and a desired coupling factor using configurable capacitors to effect a mutual coupling and using lumped components or delay lines to effect a phase shift.
Skyworks Solutions, Inc.

Apparatus for reconfigurable directional couplers in an rf transceiver with selectable phase shifters

Provided herein are apparatus and methods for reconfigurable directional couplers in an rf transceiver. Reconfigurable directional couplers can be reconfigured and designed to provide high directivity using configurable capacitors to effect a mutual coupling and using lumped components or delay lines to effect a phase shift.
Skyworks Solutions, Inc.

Selector circuit, equalizer circuit, and semiconductor integrated circuit

A first p-channel transistor to a gate of which a first input signal is inputted and a second p-channel transistor to a gate of which a selection signal is inputted are provided in series between a power supply line and an output node. A first n-channel transistor to a gate of which a second input signal is inputted and a second n-channel transistor to a gate of which the selection signal is inputted are provided in series between a ground line and the output node.
Socionext Inc.

Semiconductor device

A semiconductor device includes a 2-input nand decoder and an inverter that have six mos transistors arranged in a line. The mos transistors of the decoder are formed in a planar silicon layer disposed on a substrate and each have a structure in which a drain, a gate, and a source are arranged vertically and the gate surrounds a silicon pillar.
Unisantis Electronics Singapore Pte. Ltd.

Method and charge transfer

A circuit comprises: a first capacitor; a second capacitor; a mos (metal oxide semiconductor) transistor; and an operational amplifier, wherein the first capacitor is configured to couple to the second capacitor via the mos transistor; the operational amplifier is configured to receive a voltage at the first capacitor and output a control voltage; and the mos transistor is configured to be controlled by the control voltage.. .
Realtek Semiconductor Corp.

Thin film surface mount components

Surface mount components and related methods involve thin film circuits between first and second insulating substrates. The thin film circuits may include passive components, including resistors, capacitors, inductors, arrays of such components, networks, or filters of multiple passive components.
Avx Corporation

Element, and oscillator and information acquiring device including the element

An element, including: a first conductor layer extending in a first direction; a second conductor layer extending in the first direction; and a semiconductor disposed between the first and second conductor layers, the semiconductor including: a first semiconductor layer in contact with the first conductor layer; a second semiconductor layer in contact with the second conductor layer; and an active layer disposed between the first and second semiconductor layers, in which: the semiconductor has a width of 0.5 μm or more and 5 μm or less in a direction intersecting the first and second directions, and has a thickness of 0.1 μm or more and 1.0 μm or less in the second direction; the active layer includes a double-barrier resonant tunnel diode; and each of the two barrier layers has a thickness of 0.7 nm or more and 2.0 nm or less in the second direction.. .
Canon Kabushiki Kaisha

Tapped inductor voltage controlled oscillator

A voltage controlled oscillator includes a resonator and an amplifier. The resonator includes a capacitive element and an inductive element.
Futurewei Technologies, Inc.

Magnetic sensor and an integrated circuit

The present teaching relates to a method/apparatus for a magnetic sensor. The apparatus of the magnetic sensor resides in a housing and includes an input port and an output port, both extending from the housing.
Johnson Electric S.a.

Magnetic sensor and an integrated circuit

The present teaching relates to a magnetic sensor that comprises a housing, an input port and an output port, both extending from the housing and the input port being connected to an external alternating current (ac) power supply, and an electrical circuit. The electrical circuit comprises an output control circuit coupled with the output port and configured to be responsive to a magnetic induction signal to control the magnetic sensor to operate in a state in which a load current flows through the output port when a predetermined condition is satisfied, and operate in another state when the predetermined condition is not satisfied.
Johnson Electric S.a.

Triboelectric nanogenerator for harvesting broadband kinetic impact energy

A triboelectric generator includes a first triboelectric member, which includes a first conductive layer and an insulating triboelectric material layer disposed on the first conductive layer. The triboelectric material layer includes a first material having a first position on a triboelectric series.
Georgia Tech Research Corporation

Semiconductor power conversion apparatus and output current control method

Provided is a semiconductor power conversion apparatus that includes: a semiconductor power converter that performs power conversion by using switching elements and supplies power to a load; a converter-voltage command calculation unit that outputs a voltage command value vref that controls the semiconductor power converter; a voltage control unit that superimposes a second voltage command value on the voltage command value vref to generate a voltage command value vref2; a pwm-signal generation unit that generates a gate signal for controlling driving of the switching elements based on the voltage command value vref2 and outputs the gate signal; and a bypass unit that is connected to the semiconductor power converter in parallel with the load and branches a current of a frequency of the second voltage command value off from an output current iout that is output from the semiconductor power converter to the load.. .
Mitsubishi Electric Corporation

Switching device

A switching device according to the present invention is a switching device for switching a load by on-off control of voltage, and includes an sic semiconductor layer where a current path is formed by on-control of the voltage, a first electrode arranged to be in contact with the sic semiconductor layer, and a second electrode arranged to be in contact with the sic semiconductor layer for conducting with the first electrode due to the formation of the current path, while the first electrode has a variable resistance portion made of a material whose resistance value increases under a prescribed high-temperature condition for limiting current density of overcurrent to not more than a prescribed value when the overcurrent flows to the current path.. .
Rohm Co., Ltd.

Wireless recharging system for mobile electronic devices

A wireless recharging system for mobile electronic devices charges mobile electronic devices wirelessly. The recharging system is comprised of two components.

Apparatus and wireless power transfer in furniture

An article of furniture having an internal frame and an upholstery covering is provided with at least one transmitting resonator carried by said frame and disposed at least partially beneath said upholstery covering. The resonator is tuned for resonance at a predetermined frequency and driven by a high frequency power source also carried by said frame.
La-z-boy Incorporated

Device and protecting an electrical system component of a vehicle electrical system

The invention relates to a device (1) for protecting at least one electrical system component (2, 3) of a vehicle electrical system. The device comprises at least one semiconductor switch (4), which is connected to the at least one electrical system component (2, 3) in an electrically conductive manner.
Lisa Draexlmaier Gmbh

Spliced shielded wire cable

A wire harness having at least wire harness assembly having a splice of at least three shielded wire cables is presented. The assembly includes a flexible insulation layer wrapped about the joined core conductors of the three cables, a flexible conductive layer wrapped about the shield conductors of the cables, and a section of dual wall heat shrink tubing enclosing the flexible conductive layer and portions of the insulative jackets of the cables.
Delphi Technologies, Inc.

Package and methods for the fabrication and testing thereof

Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure.
Nuvotronics, Inc.

Field-stabilized induction heating

Methods and systems for the uniform induction heating of forming dies, where the forming die may be heated by an induction coil in conjunction with a pair of electromagnetic (em) field stabilizers, each em field stabilizer configured to be adjacent one end of the forming die while the forming die is within the induction heating coil.. .
The Boeing Company

Separable electrical connector and making it

A novel, low profile connector element is disclosed for the purpose of electrically and mechanically interconnecting circuit elements in electronic devices, said circuit elements including but not limited to printed circuit boards, flexible printed circuits, rigid flex circuits, semiconductors, semiconductor package substrates, ground shields, and batteries, whereby the connector includes electrical contacts which have a unitary structure consisting of at least a distal end, a proximal end, and a middle section between the distal and proximal ends. The contacts of the present invention exhibit a contact diametric true position with respect to one another in an array of less than 0.2 millimeters.

System or connector for voltage bus structures

A first bus structure comprises a first outer conductive layer and a first inner conductive layer separated by a an first dielectric layer. A second bus structure comprises a second outer conductive layer and a second inner conductive layer separated by a second dielectric layer.
Deere & Company

Combination antenna

Disclosed is an antenna apparatus including a radio frequency (rf) antenna, a magnetic induction (mi) antenna disposed within the rf antenna, and electronic circuitry to receive and process audio received from at least one of the rf antenna and mi antenna.. .
Nxp B.v.

Co-located nfc reader

Systems and techniques are provided for a co-located nfc reader. A top conductive layer may include an inner pcb section, including a circuit for an electronic device, and an outer pcb section, including a near-field communications (nfc) chipset, separated by a gap in which an nfc antenna connected to the nfc chipset may be located.
Google Inc.

Method of manufacturing organic light emitting display panel

A method of manufacturing an organic light emitting display panel, the method including: providing a pixel defined by an intersection of one of a plurality of data lines and one of a plurality of gate lines, the providing the pixel including: providing a transistor, providing a storage capacitor including: a first electrode, and a second electrode, and providing a semiconductor layer, providing a first plate partially overlapping the semiconductor layer in the pixel, the providing a first plate including: providing a gate portion of the transistor, and providing a capacitor-forming portion including the first electrode of the storage capacitor, and providing a second plate on the first plate in the pixel, the second plate including the second electrode of the storage capacitor, the second plate not overlapping the semiconductor layer.. .
Lg Display Co., Ltd.

Encapsulated semiconductor device and encapsulation method

The present invention relates to an encapsulated semiconductor device (20) provided on a flexible substrate (1), a method of providing an at least partially encapsulated semiconductor device (20) on a flexible substrate (1) and a software product for providing an at least partially encapsulated semiconductor device (20) on a flexible substrate (1). In a preferred embodiment, an encapsulation method is presented in which the organic layer (3) of an inorganic/organic/inorganic multilayer barrier (5) on a plastic foil (1) as a substrate is removed at the edges of an oled (13).
Oledworks Gmbh

Sealing film, organic electroluminescent display, and organic semiconductor device

A sealing film including a substrate film, a sealing layer, and an adhesive layer in this order, wherein the sealing film has a tensile elastic modulus of equal to or higher than 1,000 mpa, and retardation of a layer portion provided at the sealing layer side relative to the substrate film in the sealing film after sealing is equal to or smaller than 20 nm.. .
Zeon Corporation

Conductive flexible substrate and manufacture thereof, and oled display device and manufacture method thereof

The present invention provides a conductive flexible substrate and a manufacture method thereof and an oled display device and a manufacture method thereof. The conductive flexible substrate comprises a flexible substrate (1), mesh conductive lines (2) located on the flexible substrate (1) and embossing from a surface of one side of the flexible substrate (1), and a conductive layer (3) filling among the mesh conductive lines (2); a surface of one side of the flexible substrate (1) away from the mesh conductive lines (2) and the conductive layer (3) is flat.
Shenzhen China Star Optoelectronics Technology Co.

Organic transistor, compound, organic semiconductor material for non-light-emitting organic semiconductor device, material for organic transistor, coating solution for non-light-emitting organic semiconductor device, and organic semiconductor film for non-light-emitting organic semiconductor device

Provided are an organic transistor containing a compound represented by the following formula, results in high carrier mobility when being used in a semiconductor active layer of the organic transistor, and exhibits high solubility in an organic solvent, in a semiconductor active layer. X is o, s, or se; p and q are 0 to 2; r1 to r10, ra, and rb are hydrogen, halogen, or -l-r; one of r1 to r10, ra, and rb is -l-r; l is a specific divalent linking group; and r is an alkyl group, a cyano group, etc..
Fujifilm Corporation

Non-stoichiometric resistive switching memory device and fabrication methods

Providing for a resistive switching memory device is described herein. By way of example, the resistive switching memory device can comprise a bottom electrode, a conductive layer, a resistive switching layer, and a top electrode.
Crossbar, Inc.

Sacrificial shorting straps for superconducting qubits

A technique relates to protecting a tunnel junction. A first electrode paddle and a second electrode paddle are on a substrate.
International Business Machines Corporation

Sacrificial shorting straps for superconducting qubits

A technique relates to protecting a tunnel junction. A first electrode paddle and a second electrode paddle are on a substrate.
International Business Machines Corporation

Semiconductor package assembly with thermal recycling function

The invention provides a portable electronic system. The portable electronic system includes a semiconductor package.
Mediatek Inc.

Method for manufacturing semiconductor light-emitting device and semiconductor light-emitting device

Methods for manufacturing semiconductor light-emitting devices and semiconductor light-emitting devices having a high radiating performance and can include a metallic laminate substrate, a semiconductor light-emitting chip and a transparent resin. The metallic laminate substrate can include a cavity so as to be able to accurately mount the light-emitting chip, and also can structures to efficiently radiate heat generated from the light-emitting chip.
Stanley Electric Co., Ltd.

Light-emitting element

A light-emitting element includes a semiconductor layered body comprising: an n-type semiconductor layer, and p-type semiconductor layer; an insulating film disposed on the semiconductor layered body and defining at least one p-side opening above the p-type semiconductor layer and a plurality of n-side openings exposing the n-type semiconductor layer; an n-side electrode disposed on the insulating film and comprising a plurality of first n-contact portions each electrically connected to the n-type semiconductor layer through one of the plurality of n-side openings; a p-side electrode electrically connected to the p-type semiconductor layer through the at least one p-side opening; a p-side post electrode disposed on the p-side electrode; and an n-side post electrode disposed on the n-side electrode. A total area of one or more first n-contact portions located on the second side is smaller than a total area of one or more first n-contact portion located on the first side..
Nichia Corporation

Led-based light emitting devices having metal spacer layers

Light emitting devices include an led that includes an n-type semiconductor layer and a p-type semiconductor layer that is stacked on top of the n-type semiconductor layer. A p-contact metallization stack is on top of the p-type semiconductor layer.
Cree, Inc.

Light emitting device and fabricating the same

Disclosed are a light emitting device and a method of fabricating the same. The light emitting device comprises a substrate.
Seoul Viosys Co., Ltd.

Optoelectronic semiconductor chip, optoelectronic semiconductor component, and a producing an optoelectronic semiconductor component

An optoelectronic semiconductor chip includes a semiconductor body that emits primary light, and a luminescence conversion element that emits secondary light by wavelength conversion of at least part of the primary light, wherein the luminescence conversion element has a first lamina fixed to a first partial region of an outer surface of the semiconductor body, the outer surface emitting primary light, and leaving free a second partial region of the outer surface, the luminescence conversion element has a second lamina fixed to a surface of the first lamina facing away from the semiconductor body and spaced apart from the semiconductor body, the first lamina is at least partly transmissive to the primary radiation, a section of the second lamina covers at least the second partial region, and at least the section of the second lamina is absorbent and/or reflective and/or scattering for the primary radiation.. .
Osram Opto Semiconductors Gmbh

Semiconductor device

A semiconductor device includes a mounting substrate with a land having a first surface and a second surface higher than the first surface, a side-emission type light emitting device including an external connecting terminal disposed on the first surface, and a bonding member disposed at least on the second surface to bond the external connecting terminal and the land.. .
Nichia Corporation

Semiconductor light emitting device

Disclosed is a semiconductor light emitting device including: a plurality of semiconductor layers; and a first electrode which is formed on an exposed region of the first semiconductor layer created by mesa etching portions of the second semiconductor layer, the active layer and the first semiconductor layer, and includes a contact layer in contact with the first semiconductor layer, a reflective layer formed on the contact layer, while facing an exposed region of the active layer created by mesa etching and reflecting light, and an anti-rupture layer formed on the reflective layer.. .
Semicon Light Co., Ltd.

Light-emitting device

The present disclosure provides a light-emitting device. The light-emitting device comprises a light-emitting stack comprising an active layer and a first surface comprising a roughened area; a smoothing layer on the first surface, wherein the smoothing layer has a surface smoother than the first surface; and a transparent conductive layer on the smoothing layer.
Epistar Corporation

Solid-state radiation transducer devices having at least partially transparent buried-contact elements, and associated systems and methods

Solid-state radiation transducer (ssrt) devices having buried contacts that are at least partially transparent and associated systems and methods are disclosed herein. An ssrt device configured in accordance with a particular embodiment can include a radiation transducer including a first semiconductor material, a second semiconductor material, and an active region between the first semiconductor material and the second semiconductor material.
Micron Technology, Inc.

Light emitting diode and light emitting diode package

A light emitting diode including a first conductive type semiconductor layer, a mesa disposed on the first conductive type semiconductor layer, the mesa including an active layer and a second conductive type semiconductor layer, a reflective electrode disposed on the mesa and configured to be in ohmic-contact with the second conductive type semiconductor layer, a current spreading layer disposed on the mesa and the reflective electrode, the current spreading layer including a first portion configured to be in ohmic-contact with an upper surface of the first conductive type semiconductor layer, a first n-contact region spaced apart from a second n-contact region with the mesa disposed between the first and second n-contact regions, and an insulation layer including a first opening exposing the reflective electrode between the first and second n-contact regions. The first and second n-contact regions have a second opening that exposes the first conductive type semiconductor layer..
Seoul Viosys Co., Ltd.

Light-emitting device and manufacturing the same

A light-emitting device includes a substrate and a first light-emitting unit. The first light-emitting unit is disposed on the substrate, and includes a first semiconductor layer, a first light-emitting layer, and a second semiconductor layer.
Genesis Photonics Inc.

Semiconductor light-emitting element and semiconductor light-emitting device

A semiconductor light-emitting element comprises: a semiconductor structure layer including a first semiconductor layer having a first conductivity type, a light-emitting layer and a second semiconductor layer having a second conductivity type opposite to the first conductivity type being laminated in sequence; a first electrode including a first electrode layer formed on the first semiconductor layer and a first contact electrode connected to the first electrode layer at a position displaced from a center of the first electrode layer in an intra-layer direction of the first electrode layer; and a second electrode extending through the first electrode layer, the first semiconductor layer and the light-emitting layer and being connected to the second semiconductor layer.. .
Stanley Electric Co., Ltd.

Semiconductor light emitting device

A semiconductor light emitting device including a substrate, an electrode and a light emitting region is provided. The substrate may have protruding portions formed in a repeating pattern on substantially an entire surface of the substrate while the rest of the surface may be substantially flat.
Nichia Corporation

Semiconductor structure with stress-reducing buffer structure

A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 gpa and 2.0 gpa.
Sensor Electronic Technology, Inc.

Nitride semiconductor light-emitting device and producing the same

A nitride semiconductor light-emitting device includes a substrate which includes polycrystal silicon dioxide or amorphous silicon dioxide as a main component, an underlying layer that is provided on the substrate, and a multilayer structure that is provided on the underlying layer and includes at least one layer made of a nitride semiconductor single crystal. The underlying layer includes crystals oriented to a c-axis and is formed by sputtering..
Sharp Kabushiki Kaisha

Semiconductor layer including compositional inhomogeneities

A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy.
Sensor Electronic Technology, Inc.

Semiconductor light emitting device

A semiconductor light emitting device includes: an n-type layer; a p-type layer; and an emission layer interposed between the n-type layer and the p-type layer and having a multiple quantum well (mqw) structure in which barrier layers and quantum well layers are alternately stacked over a plurality of periods, wherein n-type impurity concentrations of the barrier layers disposed up to a predetermined α-th layer (where a is a natural number), when counting from the p-type layer, are smaller than an n-type impurity concentration of the barrier layer disposed at an (α+1)-th layer counting from the p-type layer.. .
Rohm Co., Ltd.

Photovoltaic devices with an interfacial band-gap modifying structure and methods for forming the same

A schottky-barrier-reducing layer is provided between a p-doped semiconductor layer and a transparent conductive material layer of a photovoltaic device. The schottky-barrier-reducing layer can be a conductive material layer having a work function that is greater than the work function of the transparent conductive material layer.
Egypt Nanotechnology Center

Photovoltaic cell and photovoltaic cell manufacturing method

A photovoltaic cell manufacturing method includes depositing a first buffer layer for performing lattice relaxation on a first silicon substrate; depositing a first photoelectric conversion cell on the first buffer layer, the first photoelectric conversion cell being formed with a compound semiconductor including a pn junction, and the first photoelectric conversion cell having a lattice constant that is higher than that of silicon; connecting a support substrate to the first photoelectric conversion cell to form a first layered body; and removing the first buffer layer and the first silicon substrate from the first layered body.. .
Ricoh Company, Ltd.

Solar cell structure and manufacturing the same

A solar cell structure is disclosed, which includes a solar cell array, including multiple solar cells arranged in parallel, wherein each solar cell includes a first semiconductor layer, a second semiconductor layer under the first semiconductor layer, top electrodes and bottom electrodes formed on surfaces of the first and second semiconductor layers, respectively; a top wire group on top of the solar cell array wherein each wire connects each of the multiple solar cells; a bottom wire group under the solar cell array wherein each wire connects each of the multiple solar cells and is placed away from the wires of the top wire group; and conductive adhesive on top of the top electrodes and on top of the bottom electrodes, being sandwiched between the top wire group and the solar cell array as well as between the bottom wire group and the solar cell array.. .
Sunovel Suzhou Technologies Ltd.

Solar cell and solar cell module

A solar cell and a solar cell module are disclosed. The solar cell includes a semiconductor substrate containing a crystalline silicon material, a first conductive region on a back surface of the semiconductor substrate, a second conductive region positioned in a portion except the first conductive region from the back surface of the semiconductor substrate and having a conductive type opposite the first conductive region, a first electrode connected to the first conductive region, and a second electrode connected to the second conductive region.
Lg Electronics Inc.

Method for manufacturing thin-film solar cell and thin-film solar cell

The present disclosure provides a method for manufacturing a thin-film solar cell, and the thin-film solar cell. The method includes steps of: forming a first electrode on a substrate; forming an n-type doped layer and an intrinsic semiconductor film on the first electrode; doping ions into the intrinsic semiconductor film, and subjecting the ion-doped intrinsic semiconductor film to activation treatment using an excimer laser annealing (ela) process, so as to form a p-type doped layer at an upper layer of the intrinsic semiconductor film; and forming a second electrode on the p-type doped layer..
Boe Technology Group Co., Ltd.

Semiconductor device including two-dimensional material, and manufacturing the semiconductor device

Example embodiments relate to semiconductor devices including two-dimensional (2d) materials, and methods of manufacturing the semiconductor devices. A semiconductor device may be an optoelectronic device including at least one doped 2d material.
Samsung Electronics Co., Ltd.

Semiconductor light trap devices

Embodiments relate to buried structures for silicon devices which can alter light paths and thereby form light traps. Embodiments of the lights traps can couple more light to a photosensitive surface of the device, rather than reflecting the light or absorbing it more deeply within the device, which can increase efficiency, improve device timing and provide other advantages appreciated by those skilled in the art..
Infineon Technologies Dresden Gmbh

Photoelectric conversion device

Provided is a photoelectric conversion device with an excellent conversion efficiency in which a series resistance between a semiconductor substrate and an electrode is reduced. The photoelectric conversion device includes a semiconductor substrate; a first conductivity region formed on the semiconductor substrate; and an electrode electrically connected to the first conductivity region, in which the first conductivity region includes an electrode region which faces the electrode, and crystal defects in the semiconductor substrate which faces the electrode region..
Sharp Kabushiki Kaisha

Charge stabilized dielectric film for electronic devices

Methods of manufacturing a substrate unit that achieve improved levels of efficiency and/or longevity are disclosed. The substrate units may be used for example in solar cells, semiconductor detectors or electrostatic actuators, sensors, harvesters or other electro-mechanical devices.
Isis Innovation Limited

Solar cell having doped semiconductor heterojunction contacts

A silicon solar cell has doped amorphous silicon contacts formed on a tunnel silicon oxide layer on a surface of a silicon substrate. High temperature processing is unnecessary in fabricating the solar cell..
Sunpower Corporation

Chip package and manufacturing method thereof

A chip package includes a chip, an insulating layer, a flowing insulating material layer and conductive layer. The chip has a conductive pad, a side surface, a first surface and a second surface opposite to the first surface, which the side surface is between the first surface and the second surface, and the conductive is below the first surface and protruded from the side surface.
Xintec Inc.

Semiconductor device

A semiconductor device includes a fin-shaped silicon layer on a silicon substrate. A first insulating film is around the fin-shaped silicon layer and a pillar-shaped silicon layer is on the fin-shaped silicon layer.
Unisantis Electronics Singapore Pte. Ltd.

Method for producing semiconductor device and semiconductor device

A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film; a second step of forming a pillar-shaped semiconductor layer and a first dummy gate; a third step of forming a second dummy gate on side walls of the first dummy gate and the pillar-shaped semiconductor layer; a fourth step of forming a fifth insulating film and a sixth insulating film around the second dummy gate; a fifth step of depositing a first interlayer insulating film, removing the second dummy gate and the first dummy gate, forming a gate insulating film around the pillar-shaped semiconductor layer, depositing metal, and performing etch back to form a gate electrode and a gate line; and a sixth step of forming a first diffusion layer in an upper portion of the pillar-shaped semiconductor layer.. .
Unisantis Electronics Singapore Pte. Ltd.

Thin film transistor substrate having high reliability metal oxide semiconductor material

The present disclosure relates to a thin film transistor substrate having a high reliability oxide semiconductor material including a metal oxide semiconductor material. A thin film transistor substrate includes a substrate, a gate electrode disposed on the substrate, a semiconductor layer including an oxide semiconductor material combining one or more of indium, gallium and zinc, oxygen, and a doping material.
Industry-academic Cooperation Foundation, Yonsei University

Thin film transistor and manufacturing method thereof

The disclosure is related to a thin film transistor and a method of manufacturing the thin film transistor. The thin film transistor comprises a substrate, a gate, a gate insulation layer, a first semiconductor layer, an etch stop layer and a second semiconductor layer sequentially stacked on a surface of the substrate, and a source and a drain formed separating from each other and the source and the drain overlapping two ends of the second semiconductor layer respectively.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Thin film transistor and manufacturing method thereof

The disclosure is related to a thin film transistor and a method of manufacturing the thin film transistor. The thin film transistor comprises a substrate, a first semiconductor layer, an etch stop layer and a second semiconductor layer stacked on a surface of the substrate, and a first via and a second via formed on the etch stop layer; a source and a drain formed separating from each other and the source and the drain overlapping two ends of the second semiconductor layer respectively, wherein the source connects the first semiconductor layer through the first via, and the drain connects the first semiconductor layer through the second via, a gate insulation layer formed on the source and the drain; and a gate formed on the gate insulation layer.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Manufacture dual gate oxide semiconductor tft substrate and structure thereof

The present invention provides a manufacture method of an oxide semiconductor tft substrate and a structure thereof. The manufacture method of the dual gate oxide semiconductor tft substrate utilizes the halftone mask to implement one photo process, which cannot only accomplish the patterning to the oxide semiconductor layer but also obtain the oxide conductor layer (52′) with ion doping process, and the oxide conductor layer (52′) is employed as being the pixel electrode of the lcd to replace the ito pixel electrode in prior art; the method manufactures the source (81), the drain (82) and the top gate (71) at the same time with one photo process; the method implements patterning process to the passivation layer (8) and the top gate isolation layer (32) together with one photo process, to reduce the number of the photo processes to nine for shortening the manufacture procedure, raising the production efficiency and lowering the production cost..
Shenzhen China Star Optoelectronics Technology Co. Ltd.

Method for producing semiconductor device and semiconductor device

A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate, and forming a first insulating film; a second step of forming a second insulating film, and forming a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; a third step of forming a second hard mask on a side wall of the first hard mask, and etching a second polysilicon so as to be left on side walls of the first dummy gate and the pillar-shaped semiconductor layer to form a second dummy gate; and a fourth step of forming a fifth insulating film around the second dummy gate, etching the fifth insulating film so as to have a sidewall shape to form a sidewall formed of the fifth insulating film, and forming a first epitaxially grown layer on the fin-shaped semiconductor layer.. .
Unisantis Electronics Singapore Pte. Ltd.

Semiconductor device and manufacturing semiconductor device

A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the semiconductor, the electron trap layer includes crystallized hafnium oxide.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and manufacturing same

A semiconductor device includes a substrate; a gate electrode provided on the substrate; a first insulating layer formed on the gate electrode; an island-shaped oxide semiconductor layer formed on the first insulating layer; a source electrode electrically connected to the oxide semiconductor layer; and a drain electrode electrically connected to the oxide semiconductor layer, wherein the first insulating layer has a recess in the surface, wherein the oxide semiconductor layer is formed on a bottom surface and side walls of said recess and on an upper face of the first insulating layer, and wherein at least one of the source electrode and the drain electrode is disposed on a portion of the oxide semiconductor layer over the side walls of said recess, and is not formed on a portion of the oxide semiconductor layer over the upper face of the first insulating layer.. .
Sharp Kabushiki Kaisha

Semiconductor device and display device including the semiconductor device

The reliability of a transistor including an oxide semiconductor is improved. The transistor in a semiconductor device includes a first oxide semiconductor film over a first insulating film, a gate insulating film over the first oxide semiconductor film, a second oxide semiconductor film over the gate insulating film, and a second insulating film over the first oxide semiconductor film and the second oxide semiconductor film.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and electronic device including the semiconductor device

A semiconductor device includes a first oxide semiconductor film, a second oxide semiconductor film over the first oxide semiconductor film, a source electrode in contact with the second oxide semiconductor film, a drain electrode in contact with the second oxide semiconductor film, a metal oxide film over the second oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film over the metal oxide film, and a gate electrode over the gate insulating film. The metal oxide film contains m (m represents ti, ga, y, zr, la, ce, nd, or hf) and zn.
Semiconductor Energy Laboratory Co., Ltd.

Semiconductor device and display device including semiconductor device

The reliability of a transistor including an oxide semiconductor can be improved by suppressing a change in electrical characteristics. A transistor included in a semiconductor device includes a first oxide semiconductor film over a first insulating film, a gate insulating film over the first oxide semiconductor film, a second oxide semiconductor film over the gate insulating film, and a second insulating film over the first oxide semiconductor film and the second oxide semiconductor film.
Semiconductor Energy Laboratory Co., Ltd.

Thin-film transistor and manufacturing method thereof, array substrate and manufacturing method thereof, and display apparatus

A thin-film transistor and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display apparatus are provided. The method for manufacturing the tft includes: forming a gate electrode, a gate insulating layer, a metal oxide semiconductor active layer, a source electrode and a drain electrode on a substrate; the forming the metal oxide semiconductor active layer includes: forming the metal oxide semiconductor active layer by electrochemical reaction.
Boe Technology Group Co., Ltd.

Oxide thin film transistor and manufacturing method thereof

The invention provides an oxide thin film transistor and a manufacturing method thereof. The manufacturing method includes sequentially forming a gate electrode, a gate insulating layer and an oxide semiconductor film on a first substrate; sequentially forming a first metal layer and a second metal layer on the oxide semiconductor film, and forming a drain electrode and a source electrode on the second metal layer, the drain electrode and the source electrode being separated by a channel and the channel exposing a portion of the first metal layer; oxidizing the exposed portion of the first metal layer; forming an insulating passivation layer and disposing contact electrodes.
Shenzhen China Star Optoelectronics Technology Co. Ltd.

Structure and formation semiconductor device structure

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate.
Taiwan Semiconductor Manufacturing Co., Ltd.

Structure and process to tuck fin tips self-aligned to gates

A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion.
International Business Machines Corporation

Semiconductor device and fabricating the same

A semiconductor device and a method of fabricating the same are provided. The semiconductor device comprises a first multi-channel active pattern which is defined by a field insulating layer, extends along a first direction, and includes a first portion and a second portion; a gate electrode which extends along a second direction different from the first direction and is formed on the first portion; and a first source/drain region which is formed around the second portion protruding further upward than a top surface of the field insulating layer and contacts the field insulating layer, wherein the second portion is disposed on both sides of the first portion in the first direction and is more recessed than the first portion, a top surface of the first portion and a top surface of the second portion protrude further upward than the top surface of the field insulating layer, and a profile of sidewalls of the second portion is continuous..
Samsung Electronics Co., Ltd.

Semiconductor devices having multiple gate structures and methods of manufacturing such devices

A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.. .

Semiconductor device and manufacturing method thereof

A method of manufacturing a fin fet includes forming a fin structure over a substrate. The fin structure includes an upper layer, and part of the upper layer is exposed from an isolation insulating layer.
Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor device and forming the same

Provided is a semiconductor device including a substrate, an insulating layer, a conductive layer and at least one spacer. The substrate has at least two shallow trenches therein.
United Microelectronics Corp.

Semiconductor device

A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate. A first insulating film is around the fin-shaped semiconductor layer and a pillar-shaped semiconductor layer is on the fin-shaped semiconductor layer.
Unisantis Electronics Singapore Pte. Ltd.

Extended drain metal-oxide-semiconductor transistor

Devices and methods for forming a device are disclosed. A substrate is provided.
Globalfoundries Singapore Pte. Ltd.

Semiconductor devices with vertical field floating rings and methods of fabrication thereof

A semiconductor device includes a semiconductor substrate having a first conductivity type. A gate structure is supported by a surface of the semiconductor substrate, and a current carrying region (e.g., a drain region of an ldmos transistor) is disposed in the semiconductor substrate at the surface.
Freescale Semiconductor, Inc.

Vertical transistor with improved robustness

A transistor is disclosed that includes a semiconductor body having a first horizontal surface. A drift region is arranged in the semiconductor body.
Infineon Technologies Austria Ag

Devices, components and methods combining trench field plates with immobile electrostatic charge

N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits off-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate)..
Maxpower Semiconductor Inc.

Transistor arrangement including power transistors and voltage limiting means

A transistor arrangement in a semiconductor body comprises a power transistor with at least two transistor cells, each transistor cell arranged in a semiconductor fin of the semiconductor body and with a voltage limiting device with at least two device cells. Each device cell is arranged adjacent a transistor cell in the semiconductor fin of the respective transistor cell and the voltage limiting device is separated from the power transistor by a dielectric layer..
Infineon Technologies Dresden Gmbh

Method for producing semiconductor device and semiconductor device

A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film; a second step of forming a pillar-shaped semiconductor layer and a first dummy gate; a third step of forming a second dummy gate; a fourth step of forming a fifth insulating film and a sixth insulating film; a fifth step of depositing a first interlayer insulating film, removing the second dummy gate and the first dummy gate, forming a gate insulating film, depositing metal, and performing etch back to form a gate electrode and a gate line; a seventh step of forming a seventh insulating film; and an eighth step of forming insulating film sidewalls, forming a first epitaxially grown layer on the fin-shaped semiconductor layer, and forming a second epitaxially grown layer on the pillar-shaped semiconductor layer.. .
Unisantis Electronics Singapore Pte. Ltd.

(110) surface orientation for reducing fermi-level-pinning between high-k dielectric and group iii-v compound semiconductor device

A device with improved device performance, and method of manufacturing the same, are disclosed. An exemplary device includes a group iii-v compound semiconductor substrate that includes a surface having a (110) crystallographic orientation, and a gate stack disposed over the group iii-v compound semiconductor substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device and manufacturing method thereof

A fin structure including a well layer, an oxide layer over the well layer and a channel layer over the oxide layer is formed. An isolation insulating layer is formed so that the channel layer protrudes from the isolation insulating layer and at least a part of the oxide layer is embedded in the isolation insulating layer.
Taiwan Semiconductor Manufacturing Co., Ltd.

Non-planar iii-n transistor

Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls.
Intel Corporation

Semiconductor device and manufacturing method thereof

A semiconductor device includes an electron transit layer configured to be formed on a substrate; an electron supply layer configured to be formed on the electron transit layer; an upper surface layer configured to be formed on the electron supply layer; a gate electrode configured to be formed on the electron supply layer or the upper surface layer; a source electrode and a drain electrode configured to be formed on the upper surface layer; and first conductivity-type regions configured to be formed in the upper surface layer and the electron supply layer immediately below regions where the source electrode and the drain electrode are formed. The electron supply layer is formed of a nitride semiconductor including in.
Fujitsu Limited

Method of growing an epitaxial substrate and forming a semiconductor device on the epitaxial substrate

A process of forming an epitaxial substrate for a high electron mobility transistor (hemt) is disclosed. The process includes a sequential growth of a buffer layer, a barrier layer, and a cap layer, where those layers are made of nitride semiconductor materials.
Sumitomo Electric Device Innovations, Inc.

Hetero-junction semiconductor device and manufacturing a hetero-junction semiconductor device

A hetero-junction semiconductor device includes: a channel layer that includes a first semiconductor; a barrier layer that is provided on the channel layer and includes a semiconductor having a band gap larger than a band gap of the first semiconductor; a source electrode and a drain electrode that are provided on the barrier layer and are ohmic contacted to the barrier layer; a p-type semiconductor layer provided on the barrier layer, the p-type semiconductor layer being provided in a region between the source electrode and the drain electrode on the barrier layer; an n-type semiconductor layer that is provided on the p-type semiconductor layer; and a gate electrode that is joined to the n-type semiconductor layer. A joint interface between the p-type semiconductor layer and the n-type semiconductor layer has a concavo-convex structure..
Toyota Jidosha Kabushiki Kaisha

Electronic device

Provided is an electronic device including a semiconductor memory. The semiconductor memory includes first and second selecting elements coupled to a variable resistance element, and each of the first and second selecting elements includes a single-electron transistor..
Sk Hynix Inc.

Semiconductor element drive apparatus and power conversion apparatus using same

This semiconductor element drive apparatus switches an insulating gate at a positive voltage to at a negative voltage just before recovery when an anode current is large, and holds the insulating gate at the positive voltage when the anode current is small in a semiconductor element that is provided with: a first conductivity type first semiconductor layer (n− type drift layer); a second conductivity type second semiconductor layer (p type anode layer) that is adjacent to the first semiconductor layer and is exposed on one main surface (anode side); a first conductivity type third semiconductor layer (n type cathode layer) that is adjacent to the first semiconductor layer, is exposed on the other main surface (cathode side), and has an impurity concentration higher than that of the first semiconductor layer (n− type drift layer); and the insulating gate on the other main surface (cathode side).. .
Hitachi, Ltd.

Compound semiconductor device

A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors.
Murata Manufacturing Co., Ltd.

Method for manufacturing semiconductor device

In a transistor including an oxide semiconductor film, a metal oxide film for preventing electrification which is in contact with the oxide semiconductor film and covers a source electrode and a drain electrode is formed. Then, oxygen is introduced (added) to the oxide semiconductor film through the metal oxide film and heat treatment is performed.
Semiconductor Energy Laboratory Co., Ltd.

Method for manufacturing thin-film transistor

A method for manufacturing a thin-film transistor includes: forming a first metal layer of a pattern including a gate on a substrate through pattern formation operations; forming a gate insulation layer on the substrate and the first metal layer and forming an oxide semiconductor layer, of which an orthogonal projection is cast on the gate, on the gate insulation layer within a thin-film transistor area and an etch stop layer on the oxide semiconductor layer, in which two etching operations are applied to the patternized oxide semiconductor layer and etch stop layer; forming a patternized second metal layer on the thin-film transistor area and an exposed portion of the gate insulation layer, forming a patternized insulation protection layer on the substrate and the patternized second metal layer, and forming a patternized pixel electrode on the insulation protection layer.. .
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Self-aligned passivation of active regions

A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin.
Taiwan Semiconductor Manufacturing Company, Ltd.

Formation of high quality fin in 3d structure by way of two-step implantation

The present disclosure discloses a method of fabricating a semiconductor device. A fin structure is formed over a substrate.
Taiwan Semiconductor Manufacturing Company., Ltd.

Structure and formation semiconductor device structure

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack.
Taiwan Semiconductor Manufacturing Co., Ltd

Iii-v mosfet with strained channel and semi-insulating bottom barrier

Embodiments include a method for fabricating a semiconductor device and the resulting structure comprising forming a semi-insulating bottom barrier on a semiconductor substrate. A channel is formed on the bottom barrier.
International Business Machines Corporation

Method for fabricating semiconductor device having a silicide layer

A method for fabricating a semiconductor device is provided. The method includes forming a gate electrode and a source or drain disposed at opposite sides of the gate electrode, forming an interlayer insulating layer covering the gate electrode and the source or drain, forming a contact hole exposing the source or drain in the interlayer insulating layer, forming a silicide layer on a bottom surface of the contact hole, and forming a spacer on sidewalls of the contact hole and an upper surface of the silicide layer..
Samsung Electronics Co., Ltd.

Hybrid gate dielectrics for semiconductor power devices

In a general aspect, a power semiconductor device can include a silicon carbide (sic) substrate and a sic epi-layer disposed on the sic substrate. The device can also include a well region disposed in the sic epi-layer and a source region disposed in the well region.
Fairchild Semiconductor Corporation

Semiconductor structures

A semiconductor structure comprising a substrate, a pre-metal-interconnect dielectric (pmid) layer and a composite layer is disclosed. The pmid layer is above the substrate.
Taiwan Semiconductor Manufacturing Company Ltd.

Contact structure for thin film semiconductor

A method is described for forming a circuit that comprises forming a layer of semiconductor material on the substrate and an interlayer conductor contacting the layer. The layer can be a thin film layer.
Macronix International Co., Ltd.

Silicon carbide semiconductor device and manufacturing same

A silicon carbide substrate includes a first impurity region, a well region in contact with the first impurity region, and a second impurity region separated from the first impurity region by the well region. A first main surface includes a first region in contact with a channel region, and a second region different from the first region.
Sumitomo Electric Industries, Ltd.

Semiconductor devices including field effect transistors and methods of fabricating the same

A semiconductor device includes a fin structure on a substrate, device isolation patterns on the substrate at opposite sides of the fin structure, a gate electrode intersecting the fin structure and the device isolation patterns, a gate dielectric pattern between the gate electrode and the fin structure and between the gate electrode and the device isolation patterns, and gate spacers on opposite sidewalls of the gate electrode, wherein, on each of the device isolation patterns, a bottom surface of the gate dielectric pattern is at a higher level than bottom surfaces of the gate spacers.. .
Samsung Electronics Co., Ltd.

Metal nanodot formation method, metal nanodot formation apparatus and semiconductor device manufacturing method

A metal nanodot formation method includes: loading a target substrate inside a processing container of a processing apparatus; depositing a plurality of metal nanodots on a surface of the target substrate by a sequence of: supplying a co gas from a co gas container which stores the co gas into a raw material container which stores a metal carbonyl compound; generating gas of the metal carbonyl compound; introducing the generated gas of the metal carbonyl compound as a mixture gas containing the co gas into the processing container; and decomposing the metal carbonyl compound on the target substrate, and directly introducing the co gas from the co gas container into the processing container, in a state where the introduction of the mixture gas into the processing container is stopped, such that the co gas is brought into contact with the metal nanodots on the surface of the target substrate.. .
Tokyo Electron Limited

Wrap-around contact on finfet

A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface.
Taiwan Semiconductor Manufacturing Company, Ltd.

Transistor with a low-k sidewall spacer and making same

A transistor is formed by defining a gate stack on top of a semiconductor layer. The gate stack includes a gate dielectric and a gate electrode.
Stmicroelectronics (crolles 2) Sas

Semiconductor device having reduced drain-to-source capacitance

A semiconductor device includes a source finger electrode coupled to a source region in a semiconductor die, a drain finger electrode coupled to a drain region in the semiconductor die, where the source finger electrode includes at least one isolated segment and a main segment having a first portion and a second portion narrower than the first portion, whereby the source finger electrode reduces a drain-to-source capacitance of the semiconductor device. A common source rail is electrically coupled to the at least one isolated segment and the main segment of the source finger electrode.
Newport Fab, Llc Dba Jazz Semiconductor

Semiconductor device and manufacturing the same

According to one embodiment, a semiconductor device includes a semiconductor substrate in which a recess is provided on a back surface thereof, and a shape of the recess is reflected on a surface of a metal film which is also provided on the back surface of the semiconductor substrate.. .
Kabushiki Kaisha Toshiba

Method for manufacturing semiconductor device using high speed epitaxial lift-off and template for iii-v direct growth and semiconductor device manufactured using the same

Disclosed is a method for manufacturing a semiconductor device, which includes providing a template having a first substrate and a patterned first iii-v group compound layer located on the first substrate, forming a sacrificial layer on the patterned first iii-v group compound layer by epitaxial growth, forming a second iii-v group compound layer on the sacrificial layer by epitaxial growth, bonding a second substrate made of silicon onto the second iii-v group compound layer, and separating the second iii-v group compound layer and the second substrate from the template by removing the sacrificial layer.. .
Korea Institute Of Science And Technology

Device with a conductive feature formed over a cavity and method therefor

An embodiment of a device includes a semiconductor substrate, a transistor formed at the first substrate surface, a first conductive feature formed over the first substrate surface and electrically coupled to the transistor, and a second conductive feature covering only a portion of the second substrate surface to define a first conductor-less region. A cavity vertically aligned with the first conductive feature within the first conductor-less region extends into the semiconductor substrate.
Freescale Semiconductor, Inc.

Silicon carbide substrate, semiconductor device, and methods for manufacturing them

A silicon carbide substrate has a first main surface, and a second main surface opposite to the first main surface. A region including at least one main surface of the first and second main surfaces is made of single-crystal silicon carbide.
Sumitomo Electric Industries, Ltd.

Semiconductor device including metal-2 dimensional material-semiconductor contact

A semiconductor device includes a semiconductor layer, a metal layer electrically contacting the semiconductor layer, and a two-dimensional material layer between the semiconductor layer and the metal layer and having a two-dimensional crystal structure.. .
Samsung Electronics Co., Ltd.

Semiconductor structures and methods of forming the same

Semiconductor structures and methods of forming the same are provided. A semiconductor structure includes a substrate and an annular nanowire disposed over the substrate..
Taiwan Semiconductor Manufacturing Company Limited

Semiconductor device

A semiconductor device includes a semiconductor chip formed with an sic-igbt including an sic semiconductor layer, a first conductive-type collector region formed such that the collector region is exposed on a second surface of the sic semiconductor layer, a second conductive-type base region formed such that the base region contacts the collector region, a first conductive-type channel region formed such that the channel region contacts the base region, a second conductive-type emitter region formed such that the emitter region contacts the channel region to define a portion of a first surface of the sic semiconductor layer, a collector electrode connected to the collector region, and an emitter electrode connected to the emitter region. A mosfet of the device is connected in parallel to the sic-igbt, and includes a second conductive-type source region electrically connected to the emitter electrode and a second conductive-type drain region electrically connected to the collector electrode..
Rohm Co., Ltd.

Power device integration on a common substrate

A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region.
Silanna Asia Pte Ltd

Method of forming a semiconductor die

In one embodiment, semiconductor die having non-rectangular shapes and die having various different shapes are formed and singulated from a semiconductor wafer.. .
Semiconductor Components Industries, Llc

Semiconductor device with metal extrusion formation

Embodiments disclose a method of fabrication and a semiconductor structure comprising a metal-insulator-metal (mim) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate.
International Business Machines Corporation

Semiconductor device with metal extrusion formation

Embodiments disclose a method of fabrication and a semiconductor structure comprising a metal-insulator-metal (mim) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate.
International Business Machines Corporation

Capacitor structure and forming the same

A capacitor structure includes first and second interdigitated conductive elements formed over different portions of a semiconductor substrate, and a dielectric layer formed between the first and second interdigitated conductive elements. The first interdigitated conductive element that is formed includes a first base portion and a plurality of first protrusion portions.
Mediatek Inc.

Coa woled structure and manufacturing method thereof

The present invention provides a coa woled structure and a manufacturing method thereof. The structure includes red/green/blue sub pixel zones and each sub pixel zone includes a substrate, a gate terminal, a gate insulation layer, an oxide semiconductor layer, an etch stop layer, source/drain terminals, a passivation protection layer, a red/green/blue photoresist layer, a planarization layer, a semi-reflection layer, a transparent photoresist layer, an anode layer, a pixel definition layer, a photo spacer, a white light emission layer, a cathode layer, and a packaging lid.
Shenzhen China Star Optoelectronics Technology Co. Ltd.

Coa woled structure and manufacturing method thereof

The present invention provides a coa woled structure and a manufacturing method thereof. The structure includes red/green/blue sub pixel zones and each sub pixel zone includes a substrate (1), a gate terminal (2), a gate insulation layer (3), an oxide semiconductor layer (4), an etch stop layer (5), source/drain terminals (6), a passivation protection layer (7), a red/green/blue photoresist layer (71/72/73), a planarization layer (8), a semi-reflection layer (9), an anode layer (10), a pixel definition layer (11), a photo spacer (12), a white light emission layer (13), a cathode layer (14), and a packaging lid (15).
Shenzhen China Star Optoelectronics Technology Co. Ltd.

Semiconductor device and structure

A semiconductor device, including: a first memory cell including a first transistor; a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor self-aligned to the first transistor; and a plurality of junctionless transistors, where at least one of the junctionless transistors controls access to at least one of the memory cells.. .
Monolithic 3d Inc.

Method for manufacturing solid-state image pickup apparatus, solid-state image pickup apparatus, and image pickup system including the same

A method for manufacturing a solid-state image pickup apparatus includes forming a first insulating film over a substrate after forming a gate electrode of a first transfer transistor and a gate electrode of a second transfer transistor, forming a second insulating film on the first insulating film, forming a first structure and a second structure on side surfaces of the gate electrodes of the first and second transfer transistors, respectively, via the first insulating film by etching the second insulating film in such a manner that the first insulating film remains on a semiconductor region of a photoelectric conversion unit and a semiconductor region of a charge holding unit, and forming a light shielding film that covers the gate electrode of the first transfer transistor, the semiconductor region of the charge holding unit, and the gate electrode of the second transfer transistor.. .
Canon Kabushiki Kaisha

Semiconductor device, manufacturing method thereof, and electronic apparatus

A semiconductor device having a first semiconductor section including a first wiring layer at one side thereof; a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other; a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication; and an opening, other than the opening for the conductive material, which extends through the first semiconductor section to the second wiring layer.. .
Sony Corporation

Semiconductor device, fabrication a semiconductor device and electronic apparatus

Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.. .
Sony Corporation

Semiconductor device, fabrication a semiconductor device and electronic apparatus

Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.. .
Sony Corporation

Image pickup manufacturing image pickup apparatus

At least one of a passivation film extending from a pixel circuit region to a peripheral circuit region and a member disposed between a semiconductor layer and the passivation film in the peripheral circuit region contains hydrogen. The passivation film in the peripheral circuit region has a portion overlapping one conductive line of the plurality of conductive lines in a direction perpendicular to a main surface of the semiconductor layer, the one conductive line being closest to the passivation film among the plurality of conductive lines.
Canon Kabushiki Kaisha

Semiconductor device and manufacturing method thereof

Provided is a semiconductor device which allows an alignment mark used for the manufacturing of a solid-state image sensor (semiconductor device) having a back-side-illumination structure to be formed in a smaller number of steps. The semiconductor device includes a semiconductor layer having a first main surface and a second main surface opposing the first main surface, a plurality of photodiodes which are formed in the semiconductor layer and in each of which photoelectric conversion is performed, a light receiving lens disposed over the second main surface of the semiconductor layer to supply light to each of the photodiodes, and a mark for alignment formed inside the semiconductor layer.
Renesas Electronics Corporation

Photodetector and forming the photodetector on stacked trench isolation regions

Disclosed are structures and methods of forming the structures so as to have a photodetector isolated from a substrate by stacked trench isolation regions. In one structure, a first trench isolation region is in and at the top surface of a substrate and a second trench isolation region is in the substrate below the first.
Globalfoundries Inc.

Semiconductor integrated circuit device

Provided is a semiconductor integrated circuit device having pixel regions in a photodiode array region and having, in each of the pixel regions, a waveguide holding hole having a substantially perpendicular sidewall above the photodiode and embedded with a silicon oxide-based sidewall insulating film reaching the bottom surface of the hole and two or more silicon nitride-based insulating films having a higher refractive index on the inner side of the hole. This structure makes it possible to prevent deterioration of pixel characteristics of an imaging device, such as cmos sensor, which is rapidly decreasing in size..
Renesas Electronics Corporation

Semiconductor device for optical applications and producing such a semiconductor device

A sensor (2) is arranged at a main surface (10) of a semiconductor substrate (1), and a filter (3) is arranged above the sensor. A through-substrate via (4) penetrates the substrate outside the region of the sensor.
Ams Ag

Semiconductor device

A semiconductor device includes a package having a cavity and terminals (te1), a semiconductor chip that has an imaging unit and is arranged in the cavity, and a cap material with which the cavity is sealed and which has translucency. In addition, the semiconductor device includes a mounting board that has a through-hole and terminals (te2) and is arranged so as to electrically couple the terminals (te1) to the terminals (te2), a heat transfer member that is inserted into the through-hole and is coupled to the package, and a heat sink coupled to the heat transfer member..

Backside illuminated image sensor and manufacturing the same

A backside illuminated (bsi) image sensor comprises a semiconductor substrate having a first surface and a second surface opposite to the first surface; a photosensitive element in the semiconductor substrate; a gate structure partially over the first surface of the semiconductor substrate; and a temporary carrier depository in proximity to the first surface of the semiconductor substrate, wherein the gate structure has a plug portion extending from the first surface toward the second surface. The plug portion of the gate structure helps to increase the charge transfer efficiency so as to improve quantum efficiency of the bsi image sensor..
Taiwan Semiconductor Manufacturing Company Ltd

Vertical transfer gate structure for a back-side illumination (bsi) complementary metal-oxide-semiconductor (cmos) image sensor using global shutter capture

A back-side illumination (bsi) complementary metal-oxide-semiconductor (cmos) image sensor using a vertical transfer gate structure for improved quantum efficiency (qe) and global shutter efficiency (gse) is provided. A semiconductor column extends vertically from a photodetector, towards a back-end-of-line (beol) stack.
Taiwan Semiconductor Manufacturing Co., Ltd.

Image pickup apparatus, image pickup system, and manufacturing image pickup apparatus

An image pickup apparatus includes a semiconductor layer that constitutes a pixel circuit region and a peripheral circuit region. An element isolation portion is disposed in the pixel circuit region and the peripheral circuit region, defines an element portion of the semiconductor layer, and contains an insulator.
Canon Kabushiki Kaisha

Ltps tft pixel unit and manufacture method thereof

The present invention discloses a ltps tft pixel unit and a manufacture method thereof. The method comprises steps of: providing a substrate and forming a buffer layer on the substrate; forming a semiconductor pattern layer and a first insulative layer on the buffer layer, and the semiconductor pattern layer and the first insulative layer are located in the same layer and heights of the semiconductor pattern layer and the first insulative layer are the same.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Ltps array substrate

An ltps array substrate includes a plurality of ltps thin-film transistors and a bottom transparent conductive layer, a protective layer, and a top transparent conductive layer. Each ltps thin-film transistor includes a substrate, a patternized light shield layer, a buffering layer, a patternized poly-silicon layer, a gate insulation layer, a gate line, and a common electrode line, an insulation layer, a drain and a source, and a planarization layer that are formed to sequentially stack on each other.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Liquid crystal display panel, array substrate and manufacturing thin-film transistor

An lcd panel, an array substrate and a manufacturing method for tft are disclosed. The method includes: providing a substrate; forming a first metal layer on the substrate, wherein the first metal layer includes an aluminum metal layer, an aluminum oxide layer and a molybdenum metal layer stacked sequentially; patterning the first metal layer to form a gate electrode of a tft; sequentially forming a gate insulation layer, a semiconductor layer and an ohmic contact layer on the gate electrode; forming a second metal layer on the ohmic contact layer; and patterning the second metal layer to form a source electrode and a drain electrode of the tft.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Thin-film transistor, array substrate, and display device

A thin-film transistor includes a gate, a first source, a second source, a first drain, a second drain, a first semiconductor layer, a second semiconductor layer, a first insulation layer, and a second insulation layer. The gate includes a first surface and a second surface that are opposite to each other.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Thin-film transistor, display device, and manufacturing thin-film transistor

A thin-film transistor includes a substrate, a gate electrode formed on a surface of the substrate, a gate protection layer and a semiconductor layer stacked on the gate electrode, and an etch stop layer, source terminal metal, and drain terminal metal formed on a surface of the semiconductor layer in such a way that the source terminal metal and the drain terminal metal are respectively located on two opposite sides of the etch stop layer. The thin-film transistor further includes a light shielding layer, an insulation medium layer, and a pixel electrode.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Semiconductor device and manufacturing the semiconductor device

An object is to provide a semiconductor device provided with a thin film transistor having excellent electric characteristics using an oxide semiconductor layer. An in—sn—o-based oxide semiconductor layer including siox is used for a channel formation region.
Semiconductor Energy Laboratory Co., Ltd.

Metallized junction finfet structures

Finfet devices are provided wherein the current path is minimized and mostly limited to spacer regions before the channel carriers reach the metal contacts. The fins in the source/drain regions are metallized to increase the contact area and reduce contact resistance.
International Business Machines Corporation

Manufacturing semiconductor device

To provide a method for manufacturing a semiconductor device including an oxide semiconductor film having conductivity, or a method for manufacturing a semiconductor device including an oxide semiconductor film having a light-transmitting property and conductivity. The method for manufacturing a semiconductor device includes the steps of forming an oxide semiconductor film over a first insulating film, performing first heat treatment in an atmosphere where oxygen contained in the oxide semiconductor film is released, and performing second heat treatment in a hydrogen-containing atmosphere, so that an oxide semiconductor film having conductivity is formed..
Semiconductor Energy Laboratory Co., Ltd.

Vertical memory devices

A vertical memory device includes a substrate, a channel on the substrate, extending in a vertical direction with respect to a top surface of the substrate, and including a protrusion at a lower portion of the channel, the protrusion extending in a parallel direction with respect to the top surface of the substrate, a semiconductor pattern connecting the protrusion and the substrate, and gate lines stacked and spaced apart from each other in the vertical direction, the gate lines on the protrusion and the semiconductor pattern and surrounding the channel.. .

Method of manufacturing a semiconductor device

A method of manufacturing a semiconductor device, the method including forming a structure on a substrate, the structure including a metal pattern, at least a portion of the metal pattern being exposed; forming a preliminary buffer oxide layer to cover the structure, a metal oxide layer being formed at the exposed portion of the metal pattern; and deoxidizing the metal oxide layer so that the preliminary buffer oxide layer is transformed into a buffer oxide layer.. .

Electronic device and fabricating the same

A method for fabricating an electronic device including a semiconductor memory may include: forming a stack structure in which an interlayer dielectric layer and a material layer are alternately stacked on a substrate; forming a plurality of holes arranged to have a substantially constant interval while exposing the substrate by passing through the stack structure; forming a channel layer in a first hole of the plurality of holes; forming a dummy layer in a second hole of the plurality of holes; forming a mask pattern on a resultant structure including the dummy layer and the channel layer to expose an area extending in a first direction while overlapping the dummy layer arranged in the first direction; and forming a slit by etching the stack structure using the mask pattern as an etching barrier and removing the dummy layer.. .
Sk Hynix Inc.

Flash memory device

A method is provided for fabricating a flash memory device. The method includes providing a semiconductor substrate and thrilling a first polysilicon layer.

Method for producing one-time-programmable memory cells and corresponding integrated circuit

An integrated circuit includes a silicon on insulator substrate having a semiconductor film located above a buried insulating layer. At least one memory cell of the one-time-programmable type includes an mos capacitor having a first electrode region including a gate region at least partially silicided and flanked by an insulating lateral region, a dielectric layer located between the gate region and the semiconductor film, and a second electrode region including a silicided zone of the semiconductor film, located alongside the insulating lateral region and extending at least partially under the dielectric layer..
Stmicroelectronics Sa

Semiconductor devices and methods for fabricating the same

A semiconductor device includes a substrate and a plurality of storage nodes on the substrate and extending in a vertical direction relative to the substrate. A lower support pattern is in contact with the storage nodes between a bottom and a top of the storage nodes, the lower support pattern spaced apart from the substrate in the vertical direction, and the lower support pattern having a first maximum thickness in the vertical direction.
Samsung Electronics Co., Ltd.

Semiconductor device having buried gate structure and fabricating the same

A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench..
Samsung Electronics Co,. Ltd.

Semiconductor device and method

Vertical gate all around devices are formed by initially forming a first doped region and a second doped region that are planar with each other. A channel layer is formed over the first doped region and the second doped region, and a third doped region is formed over the channel layer.
Taiwan Semiconductor Manufacturing Company, Ltd.

Enhanced integration of dmos and cmos semiconductor devices

A method of fabricating a power semiconductor device includes: forming at least one lateral diffused metal-oxide-semiconductor (ldmos) structure having a first fully silicided gate including a first metal silicide material; and forming at least one complementary metal-oxide-semiconductor (cmos) structure integrated with the ldmos structure on a same substrate, the cmos structure having a second fully silicided gate including a second metal silicide material. The first metal silicide material preferably includes tungsten silicide and the second metal silicide material includes a material other than tungsten silicide..
Coolstar Technology, Inc.

Semiconductor device using three dimensional channel

According to example embodiments, a semiconductor device includes a first fin, a second fin that is separated from the first fin, and a gate on the first fin and the second fin. The gate crosses the first fin and the second fin.
Samsung Electronics Co., Ltd.

Structure and finfet device

A semiconductor device includes a first fin structure extending from a semiconductor substrate. A second fin structure is disposed over the first fin structure.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device

A semiconductor device includes a first active region and a second active region, which are disposed in a semiconductor substrate and have side surfaces facing each other, an isolation pattern disposed between the first and second active regions, a semiconductor extension layer disposed between the first and second active regions, a first source/drain semiconductor layer disposed on the first active region, and a second source/drain semiconductor layer disposed on the second active region. The facing side surfaces of the first and second active regions are closer to the semiconductor extension layer than the isolation pattern..
Samsung Electronics Co., Ltd.

Semiconductor devices and methods of manufacturing the same

A semiconductor device may include a substrate, a plurality of first contact plugs, a first via and a power rail. The substrate may include first and second cell regions and a power rail region.

Semiconductor devices having fins

A semiconductor device includes a first fin on a substrate, a gate electrode on the substrate to intersect the first fin, an epitaxial layer on both sides of the gate electrode to contact side surfaces of the first fin, and a metal alloy layer which contacts an upper surface of the first fin and part of the epitaxial layer, wherein a first region of the first fin has a higher doping concentration than a second region of the first fin which is located under the first region.. .
Samsung Electronics Co., Ltd.

Contact structure and extension formation for iii-v nfet

Finfet devices including iii-v fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the iii-v fin structures to form n-type junctions.
International Business Machines Corporation

Scalable voltage source

A scalable voltage source having a number n of mutually series-connected partial voltage sources designed as semiconductor diodes, wherein each of the partial voltage sources comprises a p-n junction of a semiconductor diode, and each semiconductor diode has a p-doped absorption layer, wherein the p-absorption layer is passivated by a p-doped passivation layer with a wider band gap than the band gap of the p-absorption layer and the semiconductor diode has an n-absorption layer, wherein the n-absorption layer is passivated by an n-doped passivation layer with a wider band gap than the band gap of the n-absorption layer, and the partial source voltages of the individual partial voltage sources deviate by less than 20%, and between in each case two successive partial voltage sources, a tunnel diode is arranged.. .
Azur Space Solar Power Gmbh

Semiconductor devices having stud patterns that are aligned and misaligned with contact patterns

A semiconductor device includes an active region, a gate pattern on the active region, the active region including a source region at a first side of the gate pattern and a drain region at a second side of the gate pattern, a gate contact pattern on the gate pattern and a drain contact pattern on the drain region, and a gate stud pattern on the gate contact pattern and a drain stud pattern on the drain contact pattern. A distance between a gate contact axis passing through a center portion of the gate contact pattern and a drain contact axis passing through a center portion of the drain contact pattern is different from a distance between a gate stud axis passing through a center portion of the gate stud pattern and a drain stud axis passing through a center portion of the drain stud pattern..

Semiconductor device and manufacturing the same

A semiconductor device is capable of accurately sensing a temperature of a semiconductor element incorporated in a semiconductor substrate. The semiconductor device includes a temperature sensor.
Toyota Jidosha Kabushiki Kaisha

Zener triggered silicon controlled rectifier with small silicon area

A semiconductor device includes a p-type semiconductor substrate, an n-well and a p-well disposed adjacent to each other and extending along a first direction within the p-type semiconductor substrate, a first n+ doped region and a first p+ doped region extending along the first direction within the n-well and spaced away from each other along a second direction perpendicular to the first direction, a second n+ doped region and a second p+ doped region extending along the first direction within the p-well and spaced away from each other along the second direction, and a plurality of third n+ doped regions and a plurality of p+ doped regions alternatively disposed in a junction region formed between the n-well and p-well the third n+ doped regions. The third n+ doped regions and the third p+ doped regions form a zener diode..
Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor device

A capacitive component region is formed below a temperature detecting diode or below a protective diode. In addition, the capacitive component region is formed below an anode metal wiring line connecting the temperature detecting diode and an anode electrode pad and below a cathode metal wiring line connecting the temperature detecting diode and a cathode electrode pad.
Fuji Electric Co., Ltd.

Stacked semiconductor die assemblies with support members and associated systems and methods

Stacked semiconductor die assemblies with support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a plurality of support members also attached to the package substrate.
Micron Technology, Inc.

Package-on-package structure including a thermal isolation material and forming the same

A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate.
Taiwan Semiconductor Manufacturing Company, Ltd.

Package and integration of heterogeneous integrated circuits

A package for holding a plurality of heterogeneous integrated circuits includes a first chip having a first conductive pad and a first substrate including a first semiconductor, and a second chip having a second conductive pad and a second substrate including a second semiconductor. The second semiconductor is different from the first semiconductor.
Taiwan Semiconductor Manufacturing Co., Ltd.

Solar cell powered integrated circuit device and method therefor

A semiconductor device includes a circuitry die and a solar cell die. The circuitry die includes a plurality of interconnect layers on a front side of the circuitry die, a metallization layer on a back side of the circuitry die, and at least one tsv (through substrate via) that makes an electrical connection between a last metal interconnect layer on the front side of the circuitry die and the metallization layer on the back side of the circuitry die.
Freescale Semiconductor, Inc.

Semiconductor package assembly and forming the same

A semiconductor package assembly is provided. The semiconductor package assembly includes a first semiconductor package.
Mediatek Inc.

Semiconductor package assembly and forming the same

A semiconductor package assembly is provided. The semiconductor package assembly includes a semiconductor package.
Mediatek Inc.

Semiconductor packaging structure and method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact.
Taiwan Semiconductor Manufacturing Company, Ltd.

Mechanisms of forming connectors for package on package

A method of forming a semiconductor device includes preparing a first semiconductor die package with conductive elements embedded in a molding compound, wherein the conductive elements are exposed on a surface of the molding compound. A top surface of the conductive elements is above or co-planar with a top-most surface of the molding compound.
Taiwan Semiconductor Manufacturing Company, Ltd.

Package-on-package semiconductor assemblies and methods of manufacturing the same

Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device.
Micron Technology, Inc.

Interconnect structure with improved conductive properties and associated systems and methods

Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die.
Micron Technology, Inc.

Method for fabricating semiconductor package having a multi-layer molded conductive substrate and structure

In one embodiment, a method for fabricating a semiconductor package includes providing a multi-layer molded conductive structure. The multi-layer molded conductive structure includes a first conductive structure disposed on a surface of a carrier and a first encapsulant covering at least portions of the first conductive structure while other portions are exposed in the first encapsulant.
Amkor Technology, Inc.

Semiconductor device assembly with heat transfer structure formed from semiconductor material

Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate.
Micron Technology, Inc.

Semiconductor package assembly and forming the same

A semiconductor package assembly is provided. The semiconductor package assembly includes a first semiconductor package.
Mediatek Inc.

Semiconductor package with elastic coupler and related methods

A semiconductor package includes: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die. The pin includes a reversibly elastically deformable lower portion, which in implementations includes a spring, configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.
Semiconductor Components Industries, Llc

Semiconductor device

Certain embodiments provide a method for manufacturing a semiconductor device including forming a first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer, forming a second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer, forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than the surface of the first conductive layer, the partial area containing surroundings of the first conductive layer, and connecting the surface of the first conductive layer and the surface of the second conductive layer and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer.. .
Kabushiki Kaisha Toshiba

Semiconductor device

A semiconductor device includes a pad group including pads provided on a semiconductor substrate and arranged in a row to form a pad row as a whole. The pad group includes at least one first pad provided with a first via-connection part electrically connected therewith and extending in a first direction perpendicular to a row direction of the pad row, and at least one second pad provided with a second via-connection part electrically connected therewith and extending in a second direction opposite to the first direction.
Lapis Semiconductor Co., Ltd.

Conductive paths through dielectric with a high aspect ratio for semiconductor devices

Conductive paths through a dielectric are described that have a high aspect ratio for semiconductor devices. In one example, a plurality of conductive connection pads are formed on a semiconductor substrate to connect to circuitry formed on the substrate.
Intel Ip Corporation

Method for manufacturing a semiconductor component having a common mode filter monolithically integrated with a protection device

In accordance with an embodiment, a semiconductor component, includes a common mode filter monolithically integrated with a protection device. The common mode filter includes a plurality of coils and the protection device has a terminal coupled to a first coil and another terminal coupled to a second coil..
Semiconductor Components Industries, Llc

Semiconductor device including semiconductor chips mounted over both surfaces of substrate

A semiconductor chip 10 flip-chip mounted on a first surface 32 of a wiring substrate 30, a semiconductor chip 20 flip-chip mounted on a second surface 33 of the wiring substrate 30, a sealing resin 71 covering the semiconductor chip 10, a sealing resin 72 covering the semiconductor chip 20, a plurality of conductive posts provided to penetrate through the sealing resin 72, and a plurality of solder balls mounted on second ends of the plurality of conductive posts exposed from the sealing resin 72 are provided; and the mounting directions of the semiconductor chips 10 and 20 are mutually different by 90°. Both of the planar shapes of the semiconductor chips 10 and 20 are rectangular shapes, the semiconductor chip 10 is mounted so that the long sides thereof are parallel to the long sides of the wiring substrate 30, and the semiconductor chip 20 is mounted so that the long sides thereof are perpendicular to the long sides of the wiring substrate 30..
Micron Technology, Inc.

Substrate dividing method

A substrate dividing method which can thin and divide a substrate while preventing chipping, and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness..
Hamamatsu Photonics K.k.

Seal ring structure to avoid delamination defect

A semiconductor device includes a semiconductor substrate, a plurality of integrated circuit devices on the semiconductor substrate, and a seal ring structure surrounding each one of the integrated circuit devices. The seal ring structure includes a plurality of interlayer dielectric layers and a plurality of hollow through-hole structures disposed within each of the interlayer dielectric layers.
Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor device package and manufacturing the same

A semiconductor device package includes a substrate, electrical components disposed on the substrate, and a conductive frame disposed on the substrate. The conductive frame includes a top portion including at least one opening, a rim connected to the top portion and surrounding the electrical components, and a compartment extending from the top portion of the conductive frame and separating one or more of the electrical components from others of the electrical components.
Advanced Semiconductor Engineering, Inc.

Method of forming electromagnetic interference shielding layer of ball grid array semiconductor package and base tape for the method

According to the method of forming an emi shielding layer of a bga semiconductor package, the emi shielding layer may be formed on the bga semiconductor package quickly, easily, and effectively by using the base tape, thereby not only improving process productivity but also remarkably reducing the manufacturing costs.. .

Flexible device having flexible interconnect layer using two-dimensional materials

A flexible device includes an electronic device having an electrode and a flexible interconnect layer formed on the electrode. The flexible interconnect layer includes a two-dimensional (2d) material and a conductive polymer to have high electric conductivity and flexibility.
Samsung Electronics Co., Ltd.

Semiconductor device

A semiconductor device may include pillars and a plurality of conductive layers being stacked while surrounding the pillars and including a plurality of first regions including non-conductive material layers and a plurality of second regions including conductive material layers, wherein the first regions and the second regions are alternately arranged.. .
Sk Hynix Inc.

Material and process for copper barrier layer

A method of fabricating a semiconductor device comprises forming a first dielectric material layer on a semiconductor substrate. The first dielectric material layer is patterned to form a plurality of vias therein.
Taiwan Semiconductor Manufacturing Company, Ltd.

Methods related to a sputtered titanium tungsten layer formed over a copper interconnect stack structure

Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a stack disposed over a compound semiconductor, with the stack including a barrier, a copper (cu) layer disposed over the barrier, and a first titanium (ti) layer disposed over the cu layer.
Skyworks Solutions, Inc.

Method for forming metal semiconductor alloys in contact holes and trenches

A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region.
International Business Machines Corporation

Semiconductor structure and making same

One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.. .
Infineon Technologies Ag

Structure for coupling metal layer interconnects in a semiconductor device

A mos device includes a first interconnect extending in a first direction, the first interconnect being configured in a metal layer. The mos device further includes a second interconnect extending in the first direction parallel to the first interconnect, the second interconnect being configured in the metal layer.
Qualcomm Incorporated

Wiring structures and semiconductor devices

A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.. .

E-fuse in soi configuration

A method of forming a semiconductor device comprising a fuse is provided including providing a semiconductor-on-insulator (soi) structure comprising an insulating layer and a semiconductor layer formed on the insulating layer, forming raised semiconductor regions on the semiconductor layer adjacent to a central portion of the semiconductor layer and performing a silicidation process of the central portion of the semiconductor layer and the raised semiconductor regions to form a silicided semiconductor layer and silicided raised semiconductor regions.. .
Globalfoundries Inc.

Semiconductor device and manufacturing the same

According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)th second sidewall film matching a pattern of a nth (where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer.
Kabushiki Kaisha Toshiba

Semiconductor device and manufacturing the same

According to one embodiment, a semiconductor device includes a stacked body, a core film, and a stacked film. The stacked body includes a plurality of conductive layers stacked with an insulating layer between the conductive layers.
Kabushiki Kaisha Toshiba

Semiconductor device and manufacturing semiconductor device

A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature..
Taiwan Semiconductor Manufacturing Company, Ltd.

Substrate structure with array of micrometer scale copper pillar based structures and manufacturing same

Micro bump interconnection structures for semiconductor devices, and more specifically, a substrate structure comprising an array of micrometer scale copper pillar based structures or micro bumps eventually comprising a solder material and a method for manufacturing the same are provided. .
Imec Vzw

Molding compound structure

A device comprises a package component comprising a plurality of bumps formed on a first side of the package component, a semiconductor die mounted on the first side of the package component, a dielectric material formed over the first side of the package component, wherein four corners of the top surface of the package component are free from the dielectric material and a top package bonded on the first side of the package component, wherein the semiconductor die is located between the top package and the package component.. .
Taiwan Semiconductor Manufacturing Company, Ltd.

Interposer and semiconductor module for use in automotive applicatons

An interposer of silicon for use in a semiconductor module, wherein the interposer has a top side serving for arrangement of functional semiconductor and an underside and is subdivided into a connection layer and a thermal layer along a plane running between the top side and the underside. The connection layer forming the surface of the interposer has a network with contact pads arranged on the surface for connection of the functional semiconductors arranged on the surface of the interposer, while the thermal layer has no metallization, and the underside of the interposer formed by the thermal layer serves for dissipating the heat generated by the functional semiconductors..
Volkswagen Ag

Semiconductor device, metal member, and manufacturing semiconductor device

A flange on first open end of a tubular contact member is soldered to a conductive plate of an insulating substrate. An external electrode terminal is fitted into a main body tube portion of the tubular contact member.
Fuji Electric Co., Ltd.

High aspect ratio interconnect for wafer level package (wlp) and integrated circuit (ic) package

A package (e.g., wafer level package) that includes a die, a redistribution portion coupled to the die, a first high aspect ratio (har) interconnect coupled to the redistribution portion of the package, where the first high aspect ratio (har) interconnect comprises a width to height ratio of about at least 1:2, and a first solder interconnect coupled to the first high aspect ratio (har) interconnect and the redistribution portion. In some implementations, the first high aspect ratio (har) interconnect is a composite interconnect that includes a first conductive core and a first conductive layer that at least partially encapsulates the first conductive core.
Qualcomm Incorporated

Power semiconductor device and manufacturing the same

A power semiconductor element is fixed on a die pad of the lead frame. A metal plate is bonded to a lower surface of the die pad via an insulating film.
Mitsubishi Electric Corporation

Semiconductor lead frame, semiconductor package, and manufacturing method thereof

A semiconductor lead frame includes a metal plate and a semiconductor chip mounting area provided on a top surface of the metal plate. A first plating layer for an internal terminal is provided around the semiconductor chip mounting area.
Sh Materials Co., Ltd.

Semiconductor device

A semiconductor device includes a laminated substrate having a circuit board; a semiconductor chip fixed to the circuit board; a terminal having a leading end portion with a cylindrical shape and a wiring portion with a shape other than the cylinder, the leading end portion and the wiring portion being formed of one conductive member; and a joining material which electrically and mechanically connects the circuit board and the leading end portion.. .
Fuji Electric Co., Ltd.

Power semiconductor module

A power semiconductor module includes a cooler; a plurality of power semiconductor units fixed on the cooler; and a bus bar unit connected electrically to the plurality of power semiconductor units. Each of the plurality of power semiconductor units includes a multilayered substrate including a circuit plate, an insulating plate, and a metal plate laminated in respective order; a semiconductor element fixed to the circuit plate; a wiring member having a printed circuit board and a plurality of conductive posts; external terminals connected electrically and mechanically to the circuit plate; and an insulating sealing material.
Fuji Electric Co., Ltd.

Semiconductor device

A cooler 20 of a semiconductor device includes an inlet portion 27 and an outlet portion 28 for a cooling liquid, an inlet path 24, an outlet path 25, and a cooling flow path 26. The inlet path 24 and the outlet path 25 have asymmetrical planar shapes.
Fuji Electric Co., Ltd.

Seminconductor device assembly with vapor chamber

Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die, a second semiconductor die at a base region of the first die, and a thermal transfer device attached to a peripheral region of the first die and extending over the second die.
Micron Technology, Inc.

Waterproof electronic device and manufacturing method thereof

A waterproof electronic device includes: an electronic component module having an electronic component including a semiconductor element, a heat dissipating member provided on the electronic component in a thermally conductive manner, and an insulating material that surrounds the electronic component in such a manner that one surface of the heat dissipating member is exposed; and a waterproof film that is formed at least on whole surfaces in regions of the electronic component module that are to be immersed in a coolant.. .
Hitachi Automotive Systems, Ltd.

Thin film based fan out and multi die package platform

Thin film based fan out wafer level packaging and a method of manufacturing the same are disclosed. Embodiments include a method including forming tapered via holes in a first surface of a polymer film; forming a conductive pillar on the first surface of a semiconductor device; bonding a solderable surface of the conductive copper pillars to metallization on the second side of the polymer film; bonding the semiconductor device to the first surface of the polymer film over the conductive pillars with an underfill material; and depositing an encapsulant material over the semiconductor device and polymer film..
Globalfoundries Inc.

Semiconductor devices comprising getter layers and methods of making and using the same

Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device.
Monolith Semiconductor Inc.

Semiconductor device and manufacturing the same

A semiconductor device includes a metal member, a semiconductor element, a resin part, a primer layer, and a peel-off restraining part. The metal member has a surface that includes a semiconductor element mounting region and a resin close contact region that extends from the semiconductor element mounting region to an outer peripheral edge of the metal member.
Toyota Jidosha Kabushiki Kaisha

Wafer stack protection seal

A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing a wafer stack with first and second wafers bonded together.
Globalfoundries Singapore Pte. Ltd.

Semiconductor device

A purpose of the present invention is to provide a semiconductor device that can restrain occurrence of partial discharge in evaluation of electric characteristics and can carry out failure analysis from the upper side of a measurement object. A semiconductor device according to the present invention includes: at least one electrode; a protective layer having at least one opening part provided such that a portion of the electrode is exposed at the opening part, and being formed to cover the other portion of the electrode excluding the portion of the electrode exposed at the opening part, the protective layer being insulative; and a conductive layer formed so as to cover the protective layer and the opening part and be directly connected to the electrode at the opening part..
Mitsubishi Electric Corporation

Thermocompression bonders, methods of operating thermocompression bonders, and horizontal correction motions using lateral force measurement in thermocompression bonding

A method of operating a thermocompression bonding system is provided. The method includes the steps of: (a) applying a first level of bond force to a semiconductor element while first conductive structures of the semiconductor element are in contact with second conductive structures of a substrate in connection with a thermocompression bonding operation; (b) measuring a lateral force related to contact between (i) ones of the first conductive structures and (ii) corresponding ones of the second conductive structures; (c) determining a corrective motion to be applied based on the lateral force measured in step (b); and (d) applying the corrective motion determined in step (c)..
Kulicke And Soffa Industries, Inc.

Method and system for controlling plasma in semiconductor fabrication

A plasma processing system and a method for controlling a plasma in semiconductor fabrication are provided. The system includes a remote plasma module configured to generate a plasma.
Taiwan Semiconductor Manufacturing Co., Ltd.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes: forming lower-layer wirings for a transistor, a circuit element and a plurality of contact pads on a substrate independently of each other; forming a first feed layer over an entire surface of the substrate on which the lower-layer wirings are formed; patterning the first feed layer to form a test pattern connecting terminals of the transistor to the separate contact pads independently of the circuit element; making a test on the transistor in a stand-alone state by using the contact pad and the test pattern; and after the test, connecting the transistor and the circuit element to form a circuit.. .
Mitsubishi Electric Corporation

Implant-free punch through doping layer formation for bulk finfet structures

A punch through stop layer is formed in a bulk finfet structure using doped oxides. Dopants are driven into the substrate and base portions of the fins by annealing.
Globalfoundries Inc.

Selective thickening of pfet dielectric

A complementary metal-oxide semiconductor (cmos) device and a method of fabricating a cmos device are described. The method includes forming an interfacial layer in a trench on a substrate in both a p-channel field effect transistor (pfet) area of the cmos device and an n-channel fet (nfet) area of the cmos device, depositing a high-k dielectric on the interfacial layer in both the pfet area and the nfet area, selectively forming a first metal layer on the high-k dielectric in only the pfet area, and depositing a second metal layer on the first metal layer in the pfet area and on the high-k dielectric in the nfet area.
International Business Machines Corporation

Directly forming sige fins on oxide

Semiconductor mandrel structures are formed extending upward from a remaining portion of a semiconductor substrate. A first oxide isolation structure is formed on exposed surfaces of the remaining portion of the semiconductor substrate and between each semiconductor mandrel structure.
International Business Machines Corporation

Substrate dividing method

A substrate dividing method which can thin and divide a substrate while preventing chipping, and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness..
Hamamatsu Photonics K.k.

Substrate dividing method

A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness..
Hamamatsu Photonics K.k.

Substrate dividing method

A substrate dividing method which can thin and divide a substrate while preventing chipping, and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness..
Hamamatsu Photonics K.k.

Semiconductor device including at least one element

A semiconductor device includes a chip, at least one element electrically coupled to the chip, an adhesive at least partially covering the at least one element, and a mold material at least partially covering the chip and the adhesive.. .
Infineon Technologies Ag

Methods of packaging semiconductor devices and structures thereof

Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer.
Taiwan Semiconductor Manufacturing Company, Ltd.

Shallow trench isolation trenches and methods for nand memory

A method of forming a shallow trench isolation trench in a semiconductor substrate is described. The method includes forming a trench in a region of the substrate, forming a liner in the trench, wherein the liner includes a first dielectric material, adhering a halogen element to the liner, forming a second dielectric material in the trench, annealing the first dielectric material and the second dielectric material, exposing a portion of a surface of the second dielectric material, and isotropically etching the exposed portion of the surface of the second dielectric material to form an air gap in the shallow trench isolation trench..
Sandisk Technologies Inc.

Air gap forming techniques based on anodic alumina for interconnect structures

An aluminum (al) layer is formed over a semiconductor substrate. A selective portion of the al layer is removed to form openings.
Taiwan Semiconductor Manufacturing Co., Ltd.

Solvent-based oxidation on germanium and iii-v compound semiconductor materials

A method to provide an isolation feature over a semiconductor structure is disclosed. The method includes forming a fin structure over a semiconductor substrate, forming an oxide layer over the fin structure, wherein forming the oxide layer includes performing a wet chemical oxidation process on the fin structure with a solvent mixture, forming a dielectric layer over the oxide layer, and forming at least one isolation feature over the semiconductor structure..
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor device manufacturing method and foup to be used therefor

A semiconductor device manufacturing method which uses a foup capable of suppressing semiconductor substrate defects due to outgas. The foup includes: a main body having an opening for taking in or out a semiconductor wafer; a cover detachably attached to the main body in close contact with the main body in a manner to cover the opening; an intake hole and an exhaust hole which are formed in the main body; and a first filter provided on the intake hole and a second filter provided on the exhaust hole.
Renesas Electronics Corporation

Manufacturing semiconductor device, and semiconductor device

Provided is a semiconductor device that suppresses the occurrence of defects due to photocorrosion. A method for manufacturing the semiconductor device includes the steps of: forming an insulating layer with a concave portion over a substrate; forming a conductive film over the insulating film and the inside of the concave portion; polishing and removing the conductive film positioned over the insulating layer; and cleaning the insulating layer in a light-shielded state.
Renesas Electronics Corporation

Corrosion resistant gas distribution manifold with thermally controlled faceplate

An apparatus for semiconductor manufacturing is provided. The apparatus may include a gas distribution manifold.
Lam Research Corporation

Semiconductor package including premold and manufacturing the same

A semiconductor package including a premold which is used to define support structure for a semiconductor die which is mounted to the premold by a layer of suitable adhesive. Embedded within the premold are lands which each include oppose upper and lower surfaces exposed in respective ones of upper and lower surfaces define by the premold.
Amkor Technology, Inc.

Power module and fabrication the same

The power module includes: a first metallic circuit pattern, a semiconductor device disposed on the first metallic circuit pattern; a leadframe electrically connected to the semiconductor device; and a stress buffering layer disposed on an upper surface of the semiconductor device, and capable of buffering a cte difference between the semiconductor device and the leadframe. The leadframe is connected to the semiconductor device via the stress buffering layer, a cte of the stress buffering layer is equal to or less than a cte of the leadframe, and a cross-sectional shape of the stress buffering layer is l-shape.
Rohm Co., Ltd.

Deposition apparatus, successive deposition, and manufacturing semiconductor device

An oxide semiconductor layer is formed with a deposition apparatus including a transfer mechanism for a substrate, a first deposition chamber in which an oxide semiconductor is deposited, and a first heating chamber in which first heat treatment is performed. The first deposition chamber and the first heating chamber are sequentially provided along a path of the substrate transferred by the transfer mechanism.
Semiconductor Energy Laboratory Co., Ltd.

Wiring board, semiconductor device, and manufacturing methods thereof

It is an object to reduce defective conduction in a wiring board or a semiconductor device whose integration degree is increased. It is another object to manufacture a highly reliable wiring board or semiconductor device with high yield.
Semiconductor Energy Laboratory Co., Ltd.

Contact structure and extension formation for iii-v nfet

Finfet devices including iii-v fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the iii-v fin structures to form n-type junctions.
International Business Machines Corporation

Method of laser annealing a semiconductor wafer with localized control of ambient oxygen

Laser annealing of a semiconductor wafers using a forming gas for localized control of ambient oxygen gas to reduce the amount of oxidization during laser annealing is disclosed. The forming gas includes hydrogen gas and an inert buffer gas such as nitrogen gas.
Ultratech, Inc.

Technique to deposit sidewall passivation for high aspect ratio cylinder etch

Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner.
Lam Research Corporation

Chamber cleaning and semiconductor etching gases

The present invention relates to fluoroolefin compositions useful as gases for cvd semiconductor manufacture, particularly for etching applications including methods for removing surface deposits from the interior of a chemical vapor deposition chamber by using an activated gas mixture, and methods for etching the surface of a semiconductor.. .
The Chemours Company Fc, Llc

Methods for manufacturing semiconductor devices

A method for forming a semiconductor device includes providing a semiconductor substrate having an upper side and comprising, in a vertical cross-section substantially orthogonal to the upper side, a plurality of semiconductor mesas of a first monocrystalline semiconductor material which are spaced apart from each other by sacrificial layers selectively etchable with respect to the first monocrystalline semiconductor material and arranged in trenches extending from the upper side into the semiconductor substrate, forming on the semiconductor mesas a support structure mechanically connecting the semiconductor mesas, at least partly replacing the sacrificial layers while the semiconductor mesas remain mechanically connected via the support structure, and at least partly removing the support structure.. .
Infineon Technologies Dresden Gmbh

Semiconductor device having electrode made of high work function material, manufacturing the same

Provided is a semiconductor device including a metal film which can be formed with lower costs but still manage to have a necessary work function and oxidation resistance. The semiconductor device includes an insulating film disposed on a substrate; and a metal film disposed on the insulating film.
Hitachi Kokusai Electric Inc.

Metallized junction finfet structures

Selective removal of semiconductor fins in the source/drain regions following source/drain epitaxy facilitates replacement thereof by the metallized fins. A spacer formed subsequent to source/drain epitaxy prevents the etching of extension/channel regions during semiconductor fin removal..

Method for removing dielectric layers from semiconductor components by using a laser beam

A method for removing dielectric layers from semiconductor components by way of a laser beam. The dielectric layer is irradiated with a laser beam which has, upon incidence on the dielectric layer, a substantially homogeneous power density over the laser beam cross-section..
Rofin-baasel Lasertech Gmbh & Co. Kg

Method for forming polysilicon

A method for forming polysilicon on a semiconductor substrate that include providing amorphous silicon on a semiconductor substrate, exposing at least an area of the amorphous silicon to a first laser beam and a second laser beam, characterized in that during exposing the area to the second laser beam no displacement of the laser beam relative to the area occurs. In addition, the use of such method for producing large grain polysilicon.
Laser Systems & Solutions Of Europe

Deposition of solid state electrolyte on electrode layers in electrochemical devices

Methods and apparatus are described for improving the fabrication of thin film electrochemical devices such as thin film batteries and electrochromic devices, with respect to deposition of lipon, or other lithium ion conducting electrolyte, thin films on electrodes such as li metal, li—coo2, wo3, nio, etc. A method of fabricating an electrochemical device in a deposition system may comprise: configuring an electrically conductive layer substantially peripherally to a portion of the surface of an electrode layer of the electrochemical device; electrically connecting the electrically conductive layer to an electrically conductive, but electrically floating, surface; and depositing a lithium ion conducting solid state electrolyte layer on the portion of the surface of the electrode layer of the electrochemical device within the deposition chamber, wherein the depositing comprises forming a plasma within the deposition chamber; wherein during the depositing, the electrically conductive, but electrically floating, surface is within the deposition chamber..
Applied Materials, Inc.

Conductive resin molded body, structure, aluminum porous body, producing aluminum porous body, current collector, electrode, non-aqueous electric double layer capacitor, and lithium ion capacitor

Provided is a conductive resin molded body that has a three-dimensional network structure and is suitable for producing an aluminum porous body in which the water adsorption amount is small. The conductive resin molded body includes a resin molded body having a three-dimensional network structure and a conductive layer at least containing carbon black and carboxymethylcellulose on the surface of the skeleton of the resin molded body.
Sumitomo Electric Industries, Ltd.

Dye-sensitized solar cell and manufacturing thereof

A dye-sensitized solar cell formed by layering a conductive layer; a photoelectric conversion layer in which a dye is adsorbed in a porous semiconductor layer and the layer is filled with a carrier transporting material; and a counter electrode including only a counter electrode conductive layer or including a catalyst layer and a counter electrode conductive layer on a support made of a light transmitting material, in which the photoelectric conversion layer is brought into contact with the counter electrode; the porous semiconductor layer forming the photoelectric conversion layer has two or more layers with different light scattering properties; and the two or more porous semiconductor layers are layered in an order of from a layer with lower light scattering property to a layer with higher light scattering property from a light receiving face side of the dye-sensitized solar cell.. .
Sharp Kabushiki Kaisha

Electrical cable with shielded conductors

An electrical cable includes at least one conductor assembly. Each conductor assembly includes at least one inner conductor that extends along a length, an insulator, and a shield layer.
Tyco Electronics Corporation

Electronic device

An electronic device applicable to an artificial neuron network. The electronic device includes a first circuit, a second circuit, and first to sixth wirings.
Semiconductor Energy Laboratory Co., Ltd.

3-dimensional semiconductor memory device and operating method thereof

Disclosed is a three-dimensional semiconductor memory device, comprising a cell array formed on a first substrate and a peripheral circuit formed on a second substrate that is at least partially overlapped by the first substrate, wherein the peripheral circuit is configured to provide signals for controlling the cell array. The cell array comprises insulating patterns and gate patterns stacked alternately on the first substrate, and at least a first pillar formed in a direction perpendicular to the first substrate and being in contact with the first substrate through the insulating patterns and the gate patterns.

Voltage generator, semiconductor memory device having the same, and operating semiconductor memory device

A voltage generator that includes an operation mode determination circuit suitable for determining an active mode or a standby mode based on a chip enable signal to activate an active mode signal or a standby mode signal according to a result of the determination; and a bulk voltage generation circuit outputting a bulk voltage having an internal power voltage when the active mode signal is activated, and outputting the bulk voltage having an external power voltage when the standby mode signal is activated.. .
Sk Hynix Inc.

Non-volatile semiconductor memory device

According to one embodiment, a non-volatile semiconductor memory device comprises a memory cell array and a memory region. The memory cell array has a plurality of physical blocks.
Kabushiki Kaisha Toshiba

Pillar-shaped semiconductor memory device and producing the same

A pillar-shaped semiconductor memory device includes si pillars arranged in at least two rows; a tunnel insulating layer; a data charge storage insulating layer; first, second, and third interlayer insulating layers; and first and second conductor layers, all of which surround outer peripheries of the si pillars, the first and second conductor layers being located at the same height in a perpendicular direction. A row of the semiconductor pillars is interposed between the first and second conductor layers of si pillars arranged in an x direction.
Unisantis Electronics Singapore Pte. Ltd.

Semiconductor device with control of maximum value of current capable of being supplied

According to one embodiment, a semiconductor device includes: a first semiconductor chip including a first via and a second via; and a second semiconductor chip including a third via and a fourth via and being located above the first semiconductor chip. The first semiconductor chip includes: a first detector capable of coupling to the third via through the second and fourth vias; and a first current source configured to control an output current in accordance with a voltage of the third via detected by the first detector..
Kabushiki Kaisha Toshiba

Apparatus and methods including source gates

Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described..
Micron Technology, Inc.

Semiconductor devices including auxiliary bit lines

Semiconductor devices are provided. A semiconductor device includes a stack of alternating gates and insulating layers.

Semiconductor device having cal latency function

One semiconductor device includes a command receiver receiving the command signal to generate a first internal command signal, and a latency control circuit activating a second internal chip select signal after elapse of first cycles of a clock signal since a first internal chip select signal is activated. The latency control circuit activates a second control signal when the chip select signal is maintained in an inactive state during second cycles of the clock signal that is larger than the first cycles.
Ps4 Luxco S.a.r.l.

Semiconductor memory device with a delay locked loop circuit and a controlling an operation thereof

An operation control method of a semiconductor memory device includes executing a delay locked loop (dll) locking in response to a dll reset signal and measuring a loop delay of a dll. The operation control method further includes storing measured loop delay information and dll locking information; and performing a delay control of a command path using the stored loop delay information and dll locking information independent of the dll, during a latency control operation..
Samsung Electronics Co., Ltd.

Semiconductor memory device and operating method thereof

A semiconductor memory device includes a memory cell array including a plurality of pages; a peripheral circuit suitable for performing a program operation and a read operation on the memory cell array; and a control logic suitable for controlling the peripheral circuit to apply first and second pass voltages respectively to first and second word lines adjacent to a selected word line during a program verify operation or the read operation.. .
Sk Hynix Inc.

Contamination reduction head for media

A cleaning head and methods for removing contaminants from a data storage media, the cleaning head having a cleaning surface comprising a self-assembled monolayer, with the cleaning surface leading a read/write transducer. The self-assembled monolayer is selected to have a terminal functional group that has a high affinity to the contaminant(s) desired to be attracted and/or removed..
Seagate Technology Llc

Extruded sonar chassis

An aluminum transducer chassis prepared by a process having the following steps: performing an extrusion using a die and an aluminum billet to create an extruded chassis, wherein the die has a cross sectional shape of the transducer chassis; and cutting the extruded chassis to a plurality of predetermined lengths, each length corresponding to the length of a transducer chassis.. .
Navico Holding As

Scan driving circuit and nor gate logic operation circuit thereof

The disclosure is related to a scan driving circuit for an oxide semiconductor thin film transistor and the nor gate logic operation circuit thereof. The nor gate logic operation circuit includes a first invertor and a second invertor applied in the pull down holding circuit of the goa circuit, and a plurality of transistors.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Scan driving circuit for oxide semiconductor thin film transistor

The invention provides a scan driving circuit for an oxide semiconductor thin film transistor. The scan driving circuit for an oxide semiconductor thin film transistor includes multiple cascade connected goa units and a shared auxiliary inverter.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Scan driving circuit for oxide semiconductor thin film transistors

The present invention provides a scan driving circuit for oxide semiconductor thin film transistors, a pull-down holding circuit part (600) employed of the circuit comprises a first pull-down holding module (601) and a second pull-down holding module (602) which is capable of extending the lifetime of the circuit; the first pull-down holding module (601) comprises a first main inverter and a first auxiliary inverter with introducing a constant low voltage level (dcl); the second pull-down holding module (602) comprises a second main inverter and a second auxiliary inverter with introducing a constant low voltage level (dcl); setting the constant low voltage level (dcl)<the second negative voltage level (vss2)<the first negative voltage level (vss1), the influence of electrical property of the oxide semiconductor thin film transistors to the scan driving circuit, particularly the bad function due to the electric leakage issue, can be prevented to ensure that the pull-down holding circuit part (600) can be normally pulled down in the functioning period and at higher voltage level in a non-functioning period to effectively maintain the first node (q(n)) and the output end (g(n)) at low voltage level.. .
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Scan driving circuit for oxide semiconductor thin film transistors

The present invention provides a scan driving circuit for oxide semiconductor thin film transistors, a pull-down holding circuit part (600) employed in the scan driving circuit for the oxide semiconductor thin film transistors comprises a main inverter and an auxiliary inverter. By introducing a constant low voltage level (dcl) and setting the constant low voltage level (dcl)<the second negative voltage level (vss2)<the first negative voltage level (vss1), the influence of electrical property of the oxide semiconductor thin film transistors to the scan driving circuit, particularly the bad function due to the electric leakage issue, can be prevented to ensure that the pull-down holding circuit part (600) can be normally pulled down in the functioning period and at higher voltage level in a non-functioning period to effectively maintain the first node (q(n)) and the output end (g(n)) at low voltage level..
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Scan driving circuit for oxide semiconductor thin film transistors

The present invention provides a scan driving circuit for oxide semiconductor thin film transistors, a pull-down holding circuit part (600) employed in the scan driving circuit for the oxide semiconductor thin film transistors comprises a main inverter and an auxiliary inverter. By introducing a constant low voltage level (dcl) and setting the constant low voltage level (dcl)<the second negative voltage level (vss2)<the first negative voltage level (vss1), the influence of electrical property of the oxide semiconductor thin film transistors to the scan driving circuit, particularly the bad function due to the electric leakage issue, can be prevented to ensure that the pull-down holding circuit part (600) can be normally pulled down in the functioning period and at higher voltage level in a non-functioning period to effectively maintain the first node (q(n)) and the output end (g(n)) at low voltage level..
Shenhen China Star Optoelectronics Technology Co., Ltd.

Goa circuit of ltps semiconductor tft

The present invention provides a goa circuit of ltps semiconductor tft, employed for forward-backward bidirectional scan transmission, comprising a plurality of goa units which are cascade connected, and n is set to be a positive integer and an nth goa unit utilizes a plurality of n-type transistors and a plurality of p-type transistors and comprises a transmission part (100), a transmission control part (200), an information storage part (300), a data erase part (400), an output control part (500) and an output buffer part (600). The transmission gate is employed to perform the former-latter level transferring signal, and the nor gate logic unit and the nand gate logic unit are employed to convert the signals, and the sequence inverter and the inverter are employed to save and transmit the signals to solve the issues that the stability of the circuit is poor, and the power consumption is larger as concerning the ltps with single type tft elements, and the problem of tft leakage of the single type goa circuit to optimize the performance of the circuit.
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Goa circuit based on ltps semiconductor tft

The present invention provides a goa circuit based on ltps semiconductor tft, comprising a plurality of goa units which are cascade connected, and n is set to be a positive integer and an nth goa unit comprises a pull-up control part (100), a pull-up part (200), a first pull-down part (400), a pull-down holding part (500) and a transfer part (600); the pull-down holding part (500) utilizes a high/low voltage reverse design and comprises a first, a second and a third dc constant low voltage levels (vss1, vss2, vss3) which are sequentially abated and a dc constant high voltage level (h), the influence of electrical property of the ltps semiconductor tft to the goa driving circuit, and particularly the bad function due to the electric leakage issue can be solved; meanwhile, the existing issue that the second node voltage level the pull-down holding circuit part in the goa circuit based on the ltps semiconductor tft cannot be at higher voltage level in the functioning period can be solved to effectively maintain the first node (q(n)) and the output end (g(n)) at low voltage level.. .
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Goa circuit based on ltps semiconductor tft

The present invention provides a goa circuit based on ltps semiconductor tft, comprising a plurality of goa units which are cascade connected, and n is set to be a positive integer and an nth goa unit comprises a pull-up control part (100), a pull-up part (200), a first pull-down part (400) and a pull-down holding part (500); the pull-down holding part (500) utilizes a high/low voltage reverse design and comprises a first, a second and a third dc constant low voltage levels (vss1, vss2, vss3) which are sequentially abated and a dc constant high voltage level (h), the influence of electrical property of the ltps semiconductor tft to the goa driving circuit, and particularly the bad function due to the electric leakage issue can be solved; meanwhile, the existing issue that the second node voltage level and the pull-down holding circuit part in the goa circuit based on the ltps semiconductor tft cannot be at higher voltage level in the non-functioning period can be solved to effectively maintain the first node (q(n)) and the output end (g(n)) at low voltage level.. .
Shenzhen China Star Optoelectronics Technology Co., Ltd.

Organic light emitting diode display and manufacturing the same

An organic light emitting diode display includes a pixel portion displaying an image and a peripheral portion surrounding the pixel portion, a semiconductor layer including a pixel switching semiconductor layer on the pixel portion on the substrate, a being driving semiconductor layer, and a peripheral switching semiconductor layer on the peripheral portion, a first gate insulating layer on the semiconductor layer, a peripheral switching gate electrode on the first gate insulating layer of the peripheral portion, a second gate insulating layer covering the peripheral switching gate electrode and the first gate insulating layer, a pixel switching gate electrode and a driving gate electrode on the second gate insulating layer of the pixel portion, and a third gate insulating layer covering the pixel switching gate electrode, the driving gate electrode, and the second gate insulating layer.. .
Samsung Display Co., Ltd.

Laser light source device and display apparatus

A laser light source device includes a semiconductor laser, a current supplying unit to supply a driving current to the semiconductor laser, and a signal generator to generate current intensity data for setting an intensity of the driving current. The signal generator generates, for an input signal corresponding to continuous pixels for a same color, a plurality of sets of the current intensity data indicating current intensities different from each other, and transmits the plurality of sets of the current intensity data to the current supplying unit while sequentially switching the plurality of sets of the current intensity data.
Panasonic Intellectual Property Management Co., Ltd.

Educational game system

An educational game system is provided having a plurality of counting pieces with a number mounted on each of the counting pieces. A resilient ball and a pair of dice are also provided.

Multi-functional chopsticks for children

The multifunctional chopsticks comprise an intelligent control device having a sensor module, a pressure induction module, a timing module, a voice module, a communication module and a power module; the sensor module is arranged at one end of the chopstick body and connected with the timing module, the pressure induction module is arranged on the middle upper portion of the chopstick body and also connected with the timing module; the voice module, the communication module and the power module are arranged at the other end of the chopstick body; the voice module is connected with the sensor module, the timing module and the pressure induction module; and the voice module is connected with the communication module and the power module. The pair of multifunctional chopsticks for children can help the children to use the chopsticks correctly, enables parents to learn about the children's dining habits and obtain specific food information..

Apparatus and alarm service using user status recognition information in electronic device

The present disclosure relates to a sensor network, machine type communication (mtc), machine-to-machine (m2m) communication, and technology for internet of things (iot). The present disclosure may be applied to intelligent services based on the above technologies, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services.
Samsung Electronics Co., Ltd.

Method and system for measurement of students', teachers' and educational institutions' performance

The invention relates to a method and system for measurement of students' improvement, more particularly the method and system aims at devising a methodology for measurement of improvement as percentage of the improvement achieved to scope of maximum improvement possible in previous performance of a particular student. The invention also relates to a method and system for measurement of teachers and educational institutions' performance, more particularly the method and system aims at devising a methodology for measurement of performance based on percentage of the average improvement achieved to scope of maximum improvement possible in previous performance of a relevant group of students..





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