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Digital Logic patents



      

This page is updated frequently with new Digital Logic-related patent applications.




Date/App# patent app List of recent Digital Logic-related patents
05/19/16
20160140290 
 Bioinformatics systems, apparatuses, and methods executed on an integrated circuit processing platform patent thumbnailBioinformatics systems, apparatuses, and methods executed on an integrated circuit processing platform
A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes a structured asic formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the structured asic connected with an electronic data source for receiving reads of genomic data.
Edico Genome, Inc.


05/12/16
20160132638 
 Bioinformatics systems, apparatuses, and methods executed on an integrated circuit processing platform patent thumbnailBioinformatics systems, apparatuses, and methods executed on an integrated circuit processing platform
A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes an integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data.
Edico Genome, Inc.


05/05/16
20160126895 
 Switched mode power amplifier with ideal iq combining patent thumbnailSwitched mode power amplifier with ideal iq combining
An i converter outputs i sign data and i magnitude data based on received i data. A q converter outputs q sign data and q magnitude data based on received q data.
Texas Instruments Incorporated


03/17/16
20160078170 
 Bioinformatics systems, apparatuses, and methods executed on an integrated circuit processing platform patent thumbnailBioinformatics systems, apparatuses, and methods executed on an integrated circuit processing platform
A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes a structured asic formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the structured asic connected with an electronic data source for receiving reads of genomic data.
Edico Genome Corporation


03/03/16
20160062924 
 Simultaneous video and bus protocols over single cable patent thumbnailSimultaneous video and bus protocols over single cable
Method and systems are disclosed for transporting simultaneous video and bus protocols over a single cable. At least some of the illustrative embodiments are systems including a main switch configured to operate in an enhanced mode where the main switch is configured to transfer data from a first data source and a second data source to a cable, operate in a default mode where the main switch is configured to transfer data from the second data source to the cable without transferring data from the first data source; a multipurpose switch configured to operate in a handshake mode where the multipurpose switch transports handshake data between the cable and a digital logic, operate in a data mode where the multipurpose switch transports bus data between the cable and the second data source; and the digital logic programed to enable modes of operation of the multipurpose switch and the main switch..
Texas Instruments Incorporated


02/18/16
20160049205 
 Rank determination patent thumbnailRank determination
Technologies are generally provided for methods and circuitry to rank a large number of cells in a timeframe of about one sense cycle. In some examples, an architecture may be implemented to rank memory cells such as volatile memories, non-volatile memories, and other types of data storage devices, where there may not be an equivalent to threshold voltage.
Empire Technology Development Llc


02/11/16
20160042203 
 Charge measurement patent thumbnailCharge measurement
An apparatus comprises a comparator that includes a first input, a second input and an output. The comparator is configured for measuring a difference in voltage between a source coupled to the first input and another source coupled to the second input, and providing information associated with the measured difference at the output.
Atmel Corporation


01/28/16
20160027493 
 Dynamic random access memory for communications systems patent thumbnailDynamic random access memory for communications systems
An integrated circuit may comprise a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (dram) cells, and a second one or more dram cells. The first dram cell(s) may be refreshed by the memory refresh circuit whereas the second dram cell(s) is not refreshed by any memory refresh circuit.
Maxlinear, Inc.


01/21/16
20160020770 
 Programmable mixed-signal input/output (io) patent thumbnailProgrammable mixed-signal input/output (io)
Techniques are described for providing highly integrated and configurable io ports for integrated circuits that can be individually configured for a variety of general purpose digital or analog functions, such as multiple channel analog-to-digital converters (adc), multiple channel digital-to-analog converters (dac), multiplexers, gpios, analog switches, switch and multiplexers, digital logic level translators, comparators, temperature sensors and relays, and so forth. The configurations of individual ports can be set by a configuration register that can, for instance, designate the function and voltage range of the port without impacting the other ports.
Maxim Integrated Products, Inc.


01/21/16
20160019126 
 Failure recovery apparatus of digital logic circuit and method thereof patent thumbnailFailure recovery apparatus of digital logic circuit and method thereof
Exemplary embodiments of the present invention relate to a failure recovery apparatus of digital logic circuit and method thereof when a fault occurs in the digital logic circuit. A failure recovery apparatus according to an embodiment of the present invention comprises: a fault detection block configured to determine fault occurrence by comparing output results of a plurality of digital logic circuit which perform the same operation using a clock having a first cycle; and a failure recovery block configured to perform a failure recovery operation of the plurality of digital logic circuit by using a clock having a second cycle which is longer than the first cycle when it is determined as that a fault occurs.
Electronics And Telecommunications Research Institute


12/31/15
20150379309 

Charge distribution control for secure systems


Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply.
Chaologix, Inc.


12/24/15
20150371068 

Tag powersave


A tag includes a communication interface that is configured to receive and transmit wireless transmissions, a movement detector and a digital logic circuit configured to perform operations. The operations may include broadcasting wireless transmissions comprising a tag id of the tag from the communication interface according to a transmission pattern.
Sony Corporation


12/03/15
20150346742 

Energy recycling for a cost effective platform to optimize energy efficiency for low powered system


A system including: a voltage converter configured to convert a voltage from a power source to a different voltage; a memory coupled to the voltage converter; a digital logic circuit; and a level shifter coupled between the memory and digital logic circuit; wherein leakage current from the memory is stored in a capacitance in the digital logic circuit, wherein the voltage converter is further coupled to a node between the memory and digital logic circuit, and wherein the voltage converter is configured to: monitor a voltage at the node wherein the node has a desired operating voltage value; and adjust the voltage at the node when the voltage at the node varies from the desired operating voltage value.. .
Nxp B.v.


11/26/15
20150341033 

Apparatus and methods for leakage current reduction in integrated circuits


This disclosure relates to leakage current reduction in integrated circuits (ics). In one aspect, an ic can include a digital logic circuit and a polarization circuit.
Micron Technology, Inc.


11/26/15
20150339586 

Method for calling for preemptive maintenance and for equipment failure prevention


A method for operating digital electronic appliance that empanels several different artificial intelligence (ai) classification technologies into a “jury” uses combinational digital logic to render “verdicts” about the need for service and impending equipment failures of the machines they monitor. Networks can be used to forward signals from remote locations to a centralized appliance that may be plugged as a module into a server.
Brighterion, Inc.


11/19/15
20150331432 

Hvac controller having multiplexed input signal detection and operation thereof


A heating, ventilation and air conditioning (hvac) controller, a method of detecting multiplexed input signals and an hvac system employing the controller or the method. In one embodiment, the hvac controller includes: (1) a signal conditioner configured to convert received alternating current (ac) input signals into corresponding square wave signals of a digital logic voltage, (2) a multiplexer coupled to the signal conditioner and configured to select one of the square wave signals and (3) a sample analyzer coupled to the multiplexer and configured to evaluate multiple samples of the selected one of the square wave signals to derive a binary state..
Lennox Industries Inc.


11/12/15
20150320315 

Method and system for providing data communication in continuous glucose monitoring and management system


Method and apparatus for providing a data stream generator that generates a data stream associated with a monitored analyte level, and a radio frequency logic portion operatively coupled to the data stream generator, the radio frequency logic portion configured to generate a radio frequency data stream based on the data stream generated from the data stream generator, the radio frequency logic portion further including one or more finite state machines and a plurality of discrete digital logic circuits, the one or more finite state machines configured to control the plurality of digital logic circuits to generate the radio frequency data stream for wireless communication are provided. Systems and kits incorporating the same are also provided..
Abbott Diabetes Care Inc.


10/29/15
20150312479 

Image sensor having a uniform digital power signature


An image sensor and a method of operating an image sensor to achieve a substantially uniform power signature. An array of pixels may be scanned using analog sensing circuitry to obtain an analog sensor output.
Apple Inc.


10/08/15
20150287273 

Power cycling of gaming machine


The present invention relates to enabling an operating system software to selectively power cycle one or more components of a wagering gaming system comprising a central processing unit board having one or more central processing units, and one or more central processing unit components. The invention uses a memory comprising a dedicated power cycle control register, a power controller, and digital logic configured to initiate a power cycle of the one or more components of the wagering gaming machine when the operating system writes a predetermined value to the power cycle control register.

10/01/15
20150279486 

System and adding error protection capability to a digital logic circuit


A system and method for adding error protection capability to a digital logic circuit, for example including random storage logic. Various aspects of the present disclosure, for example, comprise providing error protection against soft errors that occur during operation of digital logic circuitry..
Emulex Corporation


09/17/15
20150262074 

Solving digital logic constraint problems via adiabatic quantum computation


A constraint problem may be represented as a digital circuit comprising at least one gate and at least one constrained input or at least one constrained output, or a combination of at least one constrained input and at least one constrained output. A matrix may be generated for each of the at least one gates.
Temporal Defense Systems, Llc


08/20/15
20150235061 

Tag reading apparatus and method, tag identification system


An apparatus for reading a tag, includes: a reading module for reading first tag information from the tag; a digital logic control module coupled to the reading module, the digital logic control module including a preset digital logic circuit for performing a logical operation on the first tag information to obtain second tag information, the second tag information including real information of the tag; and an output module coupled to the digital logic control module for outputting the second tag information.. .
I-patrol Technology Limited


08/20/15
20150235012 

Digital resource protection method and apparatus, and digital resource using method and apparatus


A digital resource protection apparatus, includes: a configuring module to configure n encryption index values for a digital resource to be encrypted, wherein n is an integer greater than 0; and a digital logic control module configured to perform a logic encryption of the digital resource through a preset digital logic circuit, by using one or more of the n encryption index values and the digital resource as input parameters of the preset digital logic circuit.. .
I-patrol Technology Limited


08/13/15
20150227688 

Bioinformatics systems, apparatuses, and methods executed on an integrated circuit processing platform


A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes a structured asic formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the structured asic connected with an electronic data source for receiving reads of genomic data.
Edico Genome Corporation


08/06/15
20150220126 

Computing subsystem hardware recovery via automated selective power cycling


Various embodiments are generally directed to automated selective power cycling of an inoperative hardware-based subsystem of a computing device, while not power cycling other components of the computing device, in response to detection of that subsystem becoming inoperative. An apparatus comprising a controller processor circuit; a first component comprising digital logic and provided with electric power controlled by the controller processor circuit; a second component comprising digital logic and provided with electric power controlled by the controller processor circuit; and a controller storage communicatively coupled to the controller processor circuit and arranged to store instructions operative on the controller processor circuit to receive a signal that indicates that the first component is inoperative, and cycle the electric power to the first component while continuing to provide electric power to the second component based on the signal.
Intel Corporation


07/23/15
20150207432 

System on chip with power switches


According to an exemplary implementation, an integrated circuit (ic) includes a logic circuit monolithically formed on the ic. The logic circuit is configured to generate modulation signals for controlling power switches of a power inverter.
International Rectifier Corporation


07/02/15
20150187769 

Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods


A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type.
Tela Innovations, Inc.


07/02/15
20150185285 

System and reduced pin logic scanning


A system and method for reduced scan pin logic scanning is provided. The system may include a reduced test pin integrated circuit having at least one scan chain comprising a plurality of sequentially connected flip-flop circuits.
Sandisk Technologies Inc.


06/25/15
20150178432 

Automated state machine extraction for rapid-single flux-quantum circuits


The invention provides a method and system for extracting a state machine representation of a digital logic superconductive circuit from an alphanumeric representation of the circuit. The alphanumeric representation typically specifies circuit components including inductive elements, their interconnectivity and input and output nodes.
Stellenbosch University


06/11/15
20150162926 

Successive approximation register analog-to-digital converter


A successive approximation register (sar-adc) including a digital-to-analog conversion (dac) circuit, a sample-and-hold circuit, a comparison circuit and a sar logic control circuit is provided. The dac circuit is configured to convert an n-bits digital logic signal into a comparison signal, where n is a positive integer.
Beyond Innovation Technology Co., Ltd.


05/14/15
20150130505 

Charge distribution control for secure systems


Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply.

05/07/15
20150123627 

Power converters and compensation circuits thereof


In an embodiment, a circuit includes a direct current (dc)-dc buck-boost converter and a controller. The controller includes an error amplifier configured to receive a feedback signal responsive to an output signal of the buck-boost converter.
Texas Instruments Incorporated


04/02/15
20150092759 

Low-latency synchronous clock distribution and recovery for high-speed ofmda-based mobile backhaul


A communication system includes an ofdma transmitter (tx) at an optical line terminal (olt) generating an ofdma signal by assigning orthogonal subcarriers to different cell sites through digital logic, an electrical multiplexer combining the electrical ofdma signal with two electrical clock signals, and an optical intensity modulator intensity-modulating the resulting joint electrical ofdma+clocks signal; an optical multiplexer receiving aggregate ofdma signals on multiple wavelengths with tight dwdm λ-spacing; a remote node (rn) receiving the ofdma signals, such that each wavelength is distributed by a de-multiplexer (demux) to designated general small cell area, to which cell sites are connected by optical splitters; and an optical network unit (onu) to directly photodetect and digitize received ofdma signal, wherein downstream (ds) information for each cell is digitally extracted and prepared for wireless radio frequency (rf) transmission over an air interface, and an electrical splitter and bandpass filters to separate the ofdma and clock signals for dsp-free clock recovery.. .
Nec Laboratories America, Inc.


03/12/15
20150070313 

Charge measurement


An apparatus comprises a comparator that includes a first input, a second input and an output. The comparator is configured for measuring a difference in voltage between a source coupled to the first input and another source coupled to the second input, and providing information associated with the measured difference at the output.
Atmel Corporation


03/12/15
20150070049 

Apparatus and methods for leakage current reduction in integrated circuits


This disclosure relates to leakage current reduction in integrated circuits (ics). In one aspect, an ic can include a digital logic circuit and a polarization circuit.
Micron Technology, Inc.


03/05/15
20150061727 

Analog signal compatible cmos switch as an integrated peripheral to a standard microcontroller


At least one analog signal compatible complementary metal oxide semiconductor (cmos) switch circuit is incorporated with digital logic circuits in an integrated circuit. The integrated circuit may further comprise a digital processor and memory, e.g., microcontroller, microprocessor, digital signal processor (dsp), programmable logic array (pla), application specific integrated circuit (asic), etc., for controlling operation of the at least one analog signal compatible cmos switch for switching analog signals, e.g., audio, video, serial communications, etc.
Microchip Technology Incorporated


02/26/15
20150056937 

Systems and methods for controlling the second order intercept point of receivers


In accordance with some embodiments, methods for controlling the second order intercept point in a receiver are provided, the methods comprising: generating an amplitude modulated test tone; causing the test tone to be received by a receiver; determining a characteristic of a second order intercept point of the receiver based on the received test tone; and based on the characteristic, adjusting a parameter of the receiver. In accordance with some embodiments, systems for controlling the second order intercept point in as receiver are provided, the systems comprising: a test tone generator that generates an amplitude modulated test tone; a receiver that receives the test tone; a correlator that determines a characteristic of a second order intercept point of the receiver based on the received test tone; and digital logic that, based on the characteristic, adjusts a parameter of the receiver..

02/26/15
20150054547 

Hardware prefix reduction circuit


A hardware prefix reduction circuit includes a plurality of levels. Each level includes an input conductor, an output conductor, and a plurality of nodes.
Netronome Systems, Inc.


02/05/15
20150035004 

Semiconductor devices with graded dopant regions


Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved.

12/18/14
20140371110 

Bioinformatics systems, apparatuses, and methods executed on an integrated circuit processing platform


A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes a structured asic formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the structured asic connected with an electronic data source for receiving reads of genomic data.
Edico Genome, Corp.


12/18/14
20140371109 

Bioinformatics systems, apparatuses, and methods executed on an integrated circuit processing platform


A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes a structured asic formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the structured asic connected with an electronic data source for receiving reads of genomic data.
Edico Genome, Corp.


12/18/14
20140367799 

Semiconductor chip including digital logic circuit including at least nine linear-shaped conductive structures collectively forming gate electrodes of at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods


At least nine linear-shaped conductive structures (lcs's) are positioned in accordance with a first pitch. Five of the at least nine lcs's collectively form three transistors of a first transistor type and three transistors of a second transistor type.
Tela Innovations, Inc.


12/04/14
20140354328 

Programmable mixed-signal input/output (io)


Techniques are described for providing highly integrated and configurable io ports for integrated circuits that can be individually configured for a variety of general purpose digital or analog functions, such as multiple channel analog-to-digital converters (adc), multiple channel digital-to-analog converters (dac), multiplexers, gpios, analog switches, switch and multiplexers, digital logic level translators, comparators, temperature sensors and relays, and so forth. The configurations of individual ports can be set by a configuration register that can, for instance, designate the function and voltage range of the port without impacting the other ports.

10/23/14
20140317343 

Configuration of data strobes


Disclosed embodiments may include a circuit having a plurality of data terminals, no more than two pairs of differential data strobe terminals associated with the plurality of data terminals, and digital logic circuitry. The digital logic circuitry may be coupled to the data terminals and configured to use the no more than two pairs of differential data strobe terminals concurrently with the plurality of data terminals to transfer data.

10/16/14
20140309944 

Bioinformatics systems, apparatuses, and methods executed on an integrated circuit processing platform


A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes an integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data.

10/02/14
20140291730 

Semiconductor chip including digital logic circuit including linear-shaped conductive structures having electrical connection areas located within inner region between transistors of different type and associated methods


A first linear-shaped conductive structure (lcs) forms a gate electrode (ge) of a first transistor of a first transistor type. A second lcs forms a ge of a first transistor of a second transistor type.

09/18/14
20140266136 

Hybrid digital pulse width modulation (pwm) based on phases of a system clock


Pulse width modulation (pwm) based on selectable phases of a system clock may be implemented with respect to leading-edge-modulation (lem), trailing-edge-modulation (tem), and/or dual-edge-modulation. An initial pulse may be generated based on a duty command, synchronous with the system clock, and may be registered with a d flip-flop under control of a selected phase of the system clock.

08/28/14
20140240022 

Charge measurement


An apparatus comprises a comparator that includes a first input, a second input and an output. The comparator is configured for measuring a difference in voltage between a source coupled to the first input and another source coupled to the second input, and providing information associated with the measured difference at the output.

08/21/14
20140236490 

Bioinformatics systems, apparatuses, and methods executed on an integrated circuit processing platform


A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes an integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data.

08/21/14
20140233355 

Wideband sonar with pulse compression


A sonar transmitter includes digital logic that controls switches coupled to a primary coil of a transformer. The switches are driven to produce at least one voltage pulse across a secondary coil for the transformer to produce a series of voltage pulses approximating the desired signal.

07/31/14
20140211210 

Fiber optic gyroscope mixed signal application specific integrated circuit


A system comprising a fiber optic gyroscope and a mixed signal application specific integrated circuit (asic) connected to the gyroscope is provided. The mixed signal asic comprises a digital logic unit, a relative intensity noise (rin) analog-to-digital converter (adc) coupled to the digital logic unit and configurable to receive a signal from a rin detector, and a rate adc coupled to the digital logic unit and configurable to receive a signal from a rate detector.

07/17/14
20140200166 

Bioinformatics systems, apparatuses, and methods executed on an integrated circuit processing platform


A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes an integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data.

07/17/14
20140198597 

Dynamic random access memory for communications systems


An integrated circuit may comprise a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (dram) cells, and a second one or more dram cells. The first dram cell(s) may be refreshed by the memory refresh circuit whereas the second dram cell(s) is not refreshed by any memory refresh circuit.

07/17/14
20140197895 

Variability and aging sensor for integrated circuits


A ring-oscillator-based on-chip sensor (ocs) includes a substrate having a semiconductor surface upon which the ocs is formed. The ocs includes an odd number of digital logic stages formed in and on the semiconductor surface including a first stage and a last stage each including at least one nor gate including a first gate stack and/or a nand gate including a second gate stack.

07/10/14
20140194037 

Spring ball toy


A spring ball toy includes spherical core and a plurality of spring arms radiating from the spherical core. The distal end of each spring arm is fitted with one of a selection of different types of spring feet.

06/26/14
20140181605 

Asynchronous programmable jtag-based interface to debug any system-on-chip states, power modes, resets, clocks, and complex digital logic


An asynchronous debug interface is disclosed that allows tag agents, jtag-based debuggers, firmware, and software to debug, access, and override any functional registers, interrupt registers, power/clock gating enables, etc., of core logic being tested. The asynchronous debug interface works at a wide range of clock frequencies and allows read and write transactions to take place on a side channel, as well as within the on chip processor fabric without switching into a debug or test mode.

06/19/14
20140169801 

Semiconductor package with optical port


Described herein are technologies related to a semiconductor package that is installed in a portable device for data communications. More particularly, the semiconductor package that contains a memory, a digital logic chip, and an optical port in a single module or mold is described..

06/19/14
20140167837 

Charge distribution control for secure systems


Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply.

06/19/14
20140167830 

Delay time adjusting circuit, method, and integrated circuit


A delay time adjusting circuit is described, in which a reference signal circuit generates at least one reference signal to an a/d conversion circuit, an input signal circuit generates an input signal to the a/d conversion circuit, the a/d conversion circuit compares the input signal with the at least one reference signal to output a digital signal to a digital logic chip, and the digital logic chip determines a delay time based on the digital signal. In this way, the delay time can be determined digitally, and an adjusting accuracy of the delay time can be increased; and also, the delay time can be adjusted through changing the level of the input signal, thus reducing circuit losses and costs.

05/22/14
20140143745 

Techniques for segmenting of hardware trace and verification of individual trace segments


A logic verification program, method and system that segments simulation results and then processes the resulting segments separately, and optionally in parallel, reduces memory and other system requirements and improves efficiency of verification of digital logic designs. The verification process fixes up event dependency check for past-directed checkers by including additional information with each segment after an initial segment that describes at least a portion of a state of the logic design, so that resultant events in the current segment that are caused by events in the previous segment(s) can be traced back to those events.

05/22/14
20140140445 

Apparatus and demodulation of fsk signals


An apparatus and method for demodulation of fsk signals are provided. Digital pulses of the fsk signals can be processed to detect digital data contained in the fsk frequencies by converting the fsk frequencies from a frequency signal to a digital logic signal and vice versa..

05/15/14
20140132337 

Clocked charge domain logic


Advantageous digital logic cells and methods of powering logic blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply.

05/08/14
20140125399 

Charge measurement


An apparatus comprises a comparator that includes a first input, a second input and an output. The comparator is configured for measuring a difference in voltage between a source coupled to the first input and another source coupled to the second input, and providing information associated with the measured difference at the output.

05/08/14
20140125307 

Synchronized self-referenced high voltage alternating current power saving regenerator switch system


A method and apparatus for self-referenced alternating current (ac) voltage chopping using non-linear dual switches configured in series with the load to regulate voltage according to a positive or negative instantaneous voltage value and a positive going or negative going state is disclosed. Power applied to inductive loads is conserved by automatically tracking the current demand of the load and reusing the reactive energy held by the load.

04/03/14
20140092951 

Jitter tolerant receiver


An embodiment of the invention includes a receiver with reduced error terms and incoming jitter tracking that improves jitter tolerance. An embodiment provides these benefits based on a voltage integrator that recovers data and clock information from incoming signals without use of a pll, pi, cdr, and the like.

02/27/14
20140055254 

Collision avoidance system for vehicles


A continuous exterior perimeter monitoring system for collision avoidance by vehicles with exterior objects is provided utilizing microelectronic digital logic circuits and techniques to produce a visual three-digit numerical display, a discrete multi-color display and a multi-level sound warning system, indicating precise and range of distances of exterior objects from vehicles which could collide therewith within pre-selected distances. The system displays many types of vehicle information but prioritizes and acts on collision avoidance data before displaying or acting on non-collision avoidance related information.

01/02/14
20140003169 

Configuration of data strobes


Disclosed embodiments may include a circuit having a plurality of data terminals, no more than two pairs of differential data strobe terminals associated with the plurality of data terminals, and digital logic circuitry. The digital logic circuitry may be coupled to the data terminals and configured to use the no more than two pairs of differential data strobe terminals concurrently with the plurality of data terminals to transfer data.

11/07/13
20130291672 

Detecting a relative shaft position on geared shafts


A system for determining a relative position of a secondary gear includes a gear assembly including a phonic wheel fixed to a primary gear and a secondary gear rotatably engaged to the first gear, a sensor configured to output a signal upon detecting a tooth of the phonic wheel, and a digital logic circuit configured to detect a revolution of the phonic wheel, to generate a primary gear tooth pulse at intervals corresponding to intervals of teeth of the primary gear based on the detected revolution of the phonic wheel, and to generate a secondary gear revolution signal at an interval corresponding to a revolution of the secondary gear based on the primary gear tooth pulse.. .

10/24/13
20130278302 

Clock signal generator


Embodiments of the present invention provide a clock signal generator, and the clock signal generator is applied to a physical layer subsystem supporting data transmission at multiple baud rates. The clock signal generator includes: a source clock signal generator, and two or more processors connected to an output end of the source clock signal generator; where the source clock signal generator outputs multiple source clock signals with the same frequency according to a reference signal of a reference clock in the subsystem; the processors perform frequency dividing processing on the multiple source clock signals through a digital logic circuit according to an oversampling technology, to obtain a synchronous clock signal corresponding to a baud rate of data transmission in the subsystem, so as to implement timing and transceiving functions when data is transmitted at the baud rate..

10/17/13
20130271201 

System on chip for power inverter


According to an exemplary implementation, an integrated circuit (ic) includes a logic circuit monolithically formed on the ic. The logic circuit is configured to generate modulation signals for controlling power switches of a power inverter.

10/03/13
20130261743 

System controller for variable-optic electronic ophthalmic lens


A system controller for an ophthalmic lens comprising an electronic system which actuates a variable-focus optic is disclosed herein. The system controller is part of an electronic system incorporated into the ophthalmic lens.

10/03/13
20130259269 

Button-press detection and filtering


The disclosure provides a button-press detection and filtering method, related circuit, and button-press detection chip for a external device. A button-press signal from a wire control apparatus is coupled to the button-press detection chip for the external device.

08/29/13
20130221488 

Semiconductor devices with graded dopant regions


Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved.

08/15/13
20130211788 

Method and system for providing data communication in continuous glucose monitoring and management system


Method and apparatus for providing a data stream generator that generates a data stream associated with a monitored analyte level, and a radio frequency logic portion operatively coupled to the data stream generator, the radio frequency logic portion configured to generate a radio frequency data stream based on the data stream generated from the data stream generator, the radio frequency logic portion further including one or more finite state machines and a plurality of discrete digital logic circuits, the one or more finite state machines configured to control the plurality of digital logic circuits to generate the radio frequency data stream for wireless communication are provided. Systems and kits incorporating the same are also provided..

07/25/13
20130187697 

Multi-level high voltage pulser integrated circuit using low voltage mosfets


A multi-level high-voltage pulse generator integrated circuit has a digital logic-level control interface circuit. A pair of complementary mosfets is controlled by the digital control interface circuit.

07/18/13
20130181295 

Analog signal compatible cmos switch as an integrated peripheral to a standard microcontroller


At least one analog signal compatible complementary metal oxide semiconductor (cmos) switch circuit is incorporated with digital logic circuits in an integrated circuit. The integrated circuit may further comprise a digital processor and memory, e.g., microcontroller, microprocessor, digital signal processor (dsp), programmable logic array (pla), application specific integrated circuit (asic), etc., for controlling operation of the at least one analog signal compatible cmos switch for switching analog signals, e.g., audio, video, serial communications, etc.

04/18/13
20130093505 

On-chip voltage regulator


A digital logic controller for regulating a voltage of a soc includes a first input for receiving a reference signal having a first property that is constant over a range of operating conditions of the soc, and a second input for receiving a second signal that has a second property that is indicative of an operating condition of the soc. The second property may vary over a range of operating conditions of the soc.

03/21/13
20130069688 

Digital test value based data


Embodiments of the present invention provide an inequality indication system (iis). The iis provides built in test support which enables evaluation, in an on-chip digital logic circuit, of digital values as inequalities, with either a single pass/fail bit expressed on a device i/o or a readable register containing inequality evaluation results.

03/14/13
20130064043 

Compact, energy-efficient ultrasound imaging probes using cmut arrays with integrated electronics


A cmut on cmos imaging chip is disclosed. The imaging chip can use direct connection, cmos architecture to minimize both internal and external connection complexity.

01/31/13
20130028446 

Orientation adjusting stereo audio output electrical devices


Arrangements described herein relate to systems and methods for adjusting the audio output from an electrical device based on the orientation of the device to provide proper stereo audio output for more than one orientation of the device. The audio output system includes at least two speakers.



Digital Logic topics: Digital Logic, Integrated Circuit, State Machine, Semiconductor, Power Management, Physical Layer, Synchronous, Modulation, Voltage Level Shifter, Level Shift, System On Chip, Level Shifter, Voltage Level Shift, Electronic Device, Ophthalmic

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