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Decoder patents



      
           
This page is updated frequently with new Decoder-related patents. Subscribe to the Decoder RSS feed to automatically get the update: related Decoder RSS feeds.

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Date/App# patent app List of recent Decoder-related patents
04/10/14
20140101510
 Low density parity check layer decoder for codes with overlapped circulants patent thumbnailLow density parity check layer decoder for codes with overlapped circulants
The present inventions are related to systems and methods for decoding data in an ldpc layer decoder for ldpc codes with overlapped circulants.. .
04/10/14
20140101501
 Scan test circuitry configured to prevent violation of multiplexer select signal constraints during scan testing patent thumbnailScan test circuitry configured to prevent violation of multiplexer select signal constraints during scan testing
An integrated circuit comprises a decoder having a plurality of select signal outputs, a multiplexer having a plurality of select signal inputs subject to a specified select signal constraint, and scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells coupled between respective ones of the select signal outputs of the decoder and respective ones of the select signal inputs of the multiplexer.
04/10/14
20140100856
 Apparatus and method for coding and decoding multi object audio signal with multi channel patent thumbnailApparatus and method for coding and decoding multi object audio signal with multi channel
Provided are an apparatus and method for coding and decoding a multi object audio signal with multi channel. The apparatus includes: a multi channel encoding means for down-mixing an audio signal including a plurality of channels, generating a spatial cue for the audio signal including the plurality of channels, and generating first rendering information including the generated spatial cue; and a multi object encoding unit for down-mixing an audio signal including a plurality of objects, which includes the down-mixed signal from the multi channel encoding unit, generating a spatial cue for the audio signal including the plurality of objects, and generating second rendering information including the generated spatial cue, wherein the multichannel encoding unit generates a spatial cue for the audio signal including the plurality of objects regardless of a coder-decoder (codec) scheme the limits the multi channel encoding unit..
04/10/14
20140100629
 Method and system for providing stimulation inputs to a visual prosthesis implant patent thumbnailMethod and system for providing stimulation inputs to a visual prosthesis implant
Stimulation inputs are provided to a visual prosthesis implant. The images captured by a video decoder are received and digitized to provide a plurality of video frames; integrity of the video frames is checked, the checked video frames are filtered, and the filtered video frames are converted to stimulation inputs.
04/10/14
20140099103
 Ldpc-coded modulation for ultra-high-speed optical transport in the presence of phase noise patent thumbnailLdpc-coded modulation for ultra-high-speed optical transport in the presence of phase noise
Methods and systems for decoding a signal include compensating for impairments in a received signal using at least carrier phase estimation, where residual phase error remains after compensation; calculating symbol log-likelihood ratios (llrs) for symbols in the compensated signal using monte carlo integration; demapping the symbols in the compensated signal using the symbol llrs and extrinsic information from signal decoding to produce one or more estimated codewords; and decoding each estimated codeword with a decoder that generates a decoded codeword and extrinsic information.. .
04/10/14
20140099068
 System and methodology for utilizing a portable media player patent thumbnailSystem and methodology for utilizing a portable media player
A low-cost portable digital video player receives proprietary compressed data from a source such as a personal video recorder (pvr), and displays the data on an integral display. A rewritable non-volatile memory of the player stores the data and a media decoder of the player transforms and decompresses the data.
04/10/14
20140098895
 Hypothetical reference decoder parameter syntax structure patent thumbnailHypothetical reference decoder parameter syntax structure
A video encoder signals, in an encoded video bitstream, a video parameter set (vps) that includes a plurality of hypothetical reference decoder (hrd) parameter syntax structures that each include hrd parameters. For each respective hrd parameter syntax structure in the plurality of hrd parameter syntax structures, the vps further includes a syntax element indicating whether the hrd parameters of the respective hrd parameter syntax structure include a common set of hrd parameters in addition to a set of sub-layer-specific hrd parameter information specific to a particular sub-layer of the encoded video bitstream.
04/10/14
20140098890
 Neighbor determination in video decoding patent thumbnailNeighbor determination in video decoding
Video decoding innovations for multithreading implementations and graphics processor unit (“gpu”) implementations are described. For example, for multithreaded decoding, a decoder uses innovations in the areas of layered data structures, picture extent discovery, a picture command queue, and/or task scheduling for multithreading.
04/10/14
20140098889
 Frame block comparison patent thumbnailFrame block comparison
Various arrangements for testing video decoder device functionality are presented. A video frame decoded by a video decoder device under test may be received.
04/10/14
20140098887
 Reducing memory consumption during video decoding patent thumbnailReducing memory consumption during video decoding
Video decoding innovations for multithreading implementations and graphics processor unit (“gpu”) implementations are described. For example, for multithreaded decoding, a decoder uses innovations in the areas of layered data structures, picture extent discovery, a picture command queue, and/or task scheduling for multithreading.
04/10/14
20140098878
Method and device for motion information prediction in multi-view video coding
The invention concerns a method for encoding a video stream, an associated method for decoding a video stream, an associated encoder, an associated decoder and associated computer programs. The encoding method is directed to encoding a video stream comprising at least one video sequence, comprising, for the encoding of a square or rectangular block of a picture of a video sequence of the video stream, selecting a motion information predictor for said block from a list of candidate motion information predictors, and entropic encoding of an index representative of a position of the selected motion information predictor in said list.
04/10/14
20140098863
Video coder providing implicit coefficient prediction and scan adaptation for image coding and intra coding of video
A predictive video coder performs gradient prediction based on previous blocks of image data. For a new block of image data, the prediction determines a horizontal gradient and a vertical gradient from a block diagonally above the new block (vertically above a previous horizontally adjacent block).
04/10/14
20140098858
High precision encoding and decoding of video images
Methods, systems, and computer programs for improved quality video compression. Image quality from mpeg-style video coding may be improved by preserving a higher number of bits during intermediate encoding and decoding processing steps.
04/10/14
20140098855
Lossless intra-prediction video coding
Blocks of a frame of a video stream can be encoded using lossless inter-frame prediction encoding. The compression ratio of lossless inter-frame encoding can be improved by first examining the magnitude of a motion vector used to perform inter-frame prediction.
04/10/14
20140098854
Lossless intra-prediction video coding
Blocks of a frame of a video stream can be encoded using lossless intra-prediction encoding. The compression ratio of lossless intra-prediction encoding can be improved by performing lossy encoding on the intra-predicted residual.
04/10/14
20140098853
Output management of prior decoded pictures at picture format transitions in bitstreams
Systems and methods may be provided for determining whether or not to output the “decoded pictures yet to be output” (dpytbo) after decoding a random access point (rap) picture of the second of two consecutive coded video sequences in a bitstream. The dpytbo pictures may reside in a portion of memory coupled to a video decoder.
04/10/14
20140098851
Indication of video properties
In one example, a method of decoding video data includes receiving, by a video decoder, a coded video sequence and decoding one or more bits of a reserved bits syntax element for the coded video sequence as one or more coding tool enable bits, wherein the reserved bit syntax element is part of a syntax structure that includes profile and level information, and wherein the one or more coding tool enable bits indicate whether one or more coding tools are enabled for use by the video decoder in decoding the video sequence. In some examples, the syntax structure is a profile_tier_level syntax structure.
04/10/14
20140098609
Nonvolatile semiconductor memory apparatus
According to one embodiment, a nonvolatile semiconductor memory apparatus includes a memory cell array, a row decoder, a controller. The memory cell array includes a plurality of memory strings.
04/10/14
20140098592
Resistive memory device including compensation resistive device and method of compensating resistance distribution
A resistive memory device includes a memory cell array, an input/output (i/o) sense amplifier unit, an address input buffer, a row decoder, and a column decoder. The memory cell array includes unit memory cells, and operates in response to a word line driving signal and a column selecting signal, each unit memory cell includes a resistive device and a compensation resistive device.
04/10/14
20140097691
Intelligent power sensing device
The power sensing device includes a power input interface in electrical communication with a current sensing circuit and a voltage sensing circuit. The current sensing circuit is connected to a load.
04/10/14
20140097362
System and method for compressed data transmission in a maskless lithography system
Compression, transmission and decompression of gray-tone imagery data includes receiving a gray-tone image suitable for printing at least a portion of a pattern onto a substrate by operation of an electron beam lithography system, aggregating sets of lines of the gray-tone image into trilines, sequentially encoding each of the trilines of the gray-tone image by operation of one or more encoders, the one or more encoders equipped with a codebook configured to store a plurality of triline fragments and a write location and transmitting the encoded trilines of the gray-tone image to a set of decoders of the digital pattern generator via a set of data pathways established between the one or more encoders and each of the decoders.. .
04/03/14
20140095961
Layered decoder enhancement for retained sector reprocessing
A system is described for recovering data from a number of sectors, such as the sectors of a hard disk drive (hdd) disk platter, and so forth. The system receives data from the sectors via a read channel and uses a layered data decoder to recover data from the sectors.
04/03/14
20140095960
Fully parallel encoding method and fully parallel decoding method of memory system
A memory system, a fully parallel encoding method, and a fully parallel decoding method are disclosed. The encoding method utilizes a plurality of minimal polynomials that constitute a generator polynomial to derive a plurality of roots from the minimal polynomials.
04/03/14
20140095954
Modified targeted symbol flipping for non-binary ldpc codes
A ldpc decoder includes a processor for targeted symbol flipping of suspicious bits in a ldpc codeword with unsatisfied checks. All combinations of check indices and variable indices are compiled and correlated into a pool of targeted symbol flipping candidates and returned along with symbol indices to a process that uses such symbol indices to identify symbols to flip in order to break a trapping set..
04/03/14
20140095947
Functional memory array testing with a transaction-level test engine
A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine hardware is configurable for different tests.
04/03/14
20140095946
Transaction-level testing of memory i/o and memory device
A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine receives a command to cause it to generate transactions to implement a memory test.
04/03/14
20140095891
Instruction set for sha1 round processing on 128-bit data paths
According to one embodiment, a processor includes an instruction decoder to receive a first instruction to process a sha1 hash algorithm, the first instruction having a first operand, a second operand, and a third operand, the first operand specifying a first storage location storing four sha states, the second operand specifying a second storage location storing a plurality of sha1 message inputs in combination with a fifth sha1 state. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to perform at least four rounds of the sha1 round operations on the sha1 states and the message inputs obtained from the first and second operands, using a combinational logic function specified in the third operand..
04/03/14
20140095832
Method and apparatus for performance efficient isa virtualization using dynamic partial binary translation
Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set.
04/03/14
20140093068
Instruction set for skein256 sha3 algorithm on a 128-bit processor
According to one embodiment, a processor includes an instruction decoder to receive a first instruction to perform first skein256 mix-permute operations, the first instruction having a first operand associated with a first storage location to store a plurality of odd words, a second operand associated with a second storage location to store a plurality of even words, and a third operand. The processor further includes a first execution unit coupled to the instruction decoder, in response to the first instruction, to perform multiple rounds of the first skein256 mix-permute operations based on the odd words and even words using a first rotate value obtained from a third storage location indicated by the third operand, and to store new odd words in the first storage location indicated by the first operand..
04/03/14
20140092998
Frame packing and unpacking higher-resolution chroma sampling formats
Video frames of a higher-resolution chroma sampling format such as yuv 4:4:4 are packed into video frames of a lower-resolution chroma sampling format such as yuv 4:2:0 for purposes of video encoding. For example, sample values for a frame in yuv 4:4:4 format are packed into two frames in yuv 4:2:0 format.
04/03/14
20140092997
Error resilient transmission of random access frames and global coding parameters
Error mitigation techniques are provided for video coding system in which input frames are selected for coding either as a random access pictures (“rap frames”) or as a non-rap frame. Coded rap frames may include rap identifiers that set an id context for subsequent frames.
04/03/14
20140092994
Supplemental enhancement information message coding
Techniques are described for signaling decoding unit identifiers for decoding units of an access unit. The video decoder determines which network abstraction layer (nal) units are associated with which decoding units based on the decoding unit identifiers.
04/03/14
20140092993
Error resilient decoding unit association
Techniques are described for signaling decoding unit identifiers for decoding units of an access unit. The video decoder determines which network abstraction layer (nal) units are associated with which decoding units based on the decoding unit identifiers.
04/03/14
20140092992
Supplemental enhancement information including confidence level and mixed content information
This application relates to video encoding and decoding, and specifically to tools and techniques for using and providing supplemental enhancement information in bitstreams. Among other things, the detailed description presents innovations for bitstreams having supplemental enhancement information (sei).
04/03/14
20140092991
Conditional signalling of reference picture list modification information
Innovations in signaling of reference picture list (“rpl”) modification information. For example, a video encoder evaluates a condition that depends at least in part on a variable indicating a number of total reference pictures.
04/03/14
20140092977
Apparatus, a method and a computer program for video coding and decoding
In some embodiments, there is provided an apparatus, a computer readable storage medium stored with code thereon for use by an apparatus, and a video decoder, for decoding a video bitstream, to derive a motion compensated prediction for an enhancement layer block based on a motion compensation process on the co-located base layer block using the same or similar motion vector of enhancement layer blocks and base layer reference pictures. In other embodiments, there is provided a method, an apparatus, a computer readable storage medium stored with code thereon for use by an apparatus, and a video encoder, for encoding a video bitstream, to derive a motion compensated prediction for an enhancement layer block based on a motion compensation process on the co-located base layer block using the same or similar motion vector of enhancement layer blocks and base layer reference pictures..
04/03/14
20140092973
System and method for video transcoding
A video transcoding system includes a video decoder, a video encoder, and a video interface. The video decoder is configured to decode a received video signal.
04/03/14
20140092972
Picture processing in scalable video systems
A system utilizing picture processing in a scalable video system is described. The system may include an electronic device configured to recover a picture processing index corresponding to one or more picture processors, e.g.
04/03/14
20140092971
Picture processing in scalable video systems
A system utilizing picture processing in a scalable video system is described. The system may include an electronic device configured to recover a picture processing index corresponding to one or more picture processors, e.g.
04/03/14
20140092964
Apparatus, a method and a computer program for video coding and decoding
There are disclosed various methods, apparatuses and computer program products for video encoding and decoding. In other embodiments, there is provided a method, an apparatus, a computer readable storage medium stored with code thereon for use by an apparatus, and a video encoder, for encoding a scalable bitstream, to provide indicating an encoding configuration, where only samples and syntax from intra coded pictures of base layer is used for coding the enhancement layer pictures.
04/03/14
20140092963
Signaling of regions of interest and gradual decoding refresh in video coding
During a coding process, systems, methods, and apparatus may code information indicating whether gradual decoder refresh (gdr) of a picture is enabled. When gdr is enabled, the coding process, systems, methods, and apparatus may code information that indicates whether one or more slices of the picture belong to a foreground region of the picture.
04/03/14
20140092961
Signaling decoder picture buffer information
A system for decoding a video bitstream includes receiving a frame of the video that includes at least one slice and at least one tile and where each of the at least one slice and the at least one tile are not all aligned with one another.. .
04/03/14
20140092960
Bounded rate compression with rate control for slices
A system implements rate control for encoding and decoding operations, for example, operations performed on slices of data such as image data. The system implements a transformation from actual buffer fullness to rate controlled fullness.
04/03/14
20140092957
2d block image encoding
A coder (e.g., an encoder or decoder) implements coding of two dimensional blocks of image data using two dimensional differential pulse code modulation (2d dpcm). The coder may switch between dpcm and other types of coding, such as transform coding on a block by block basis.
04/03/14
20140092955
Signaling layer identifiers for operation points in video coding
Techniques described herein are related to coding layer identifiers for operation points in video coding. In one example, a method of decoding video data is provided.
04/03/14
20140092954
Method and apparatus for encoding video to play at multiple speeds
Data that is to be transmitted to a viewer is encoded multiple times at multiple playback speeds. For example, a video advertisement may be encoded to play at normal speed, 4× normal speed, and 16× normal speed.
04/03/14
20140092218
Apparatus and method for stereoscopic video with motion sensors
An apparatus and method for a video capture device for recording 3 dimensional (3d) stereoscopic video with motion sensors is provided are provided. The apparatus includes includes a camera unit having one lens for capturing video, a video encoder/decoder for encoding the captured video, a motion sensor for capturing motion data of the video capture device corresponding to the captured video, and a controller for controlling the video encoder/decoder and motion sensor to encode the captured video with the captured motion data..
04/03/14
20140092213
Sub-bitstream extraction for multiview, three-dimensional (3d) and scalable media bitstreams
Techniques are described for modal sub-bitstream extraction. For example, a network entity may select a sub-bitstream extraction mode from a plurality of sub-bitstream extraction modes.
04/03/14
20140091843
Plesiochronous clock generation for parallel wireline transceivers
A method for plesiochronous clock generation for parallel wireline transceivers, includes: inputting, into at least one decoder, at least one digital frequency mismatch number; decoding, with the at least one decoder, the at least one digital frequency mismatch number to obtain at least one digital frequency divider number that represents a transmit frequency associated with at least one signal; inputting the at least one digital frequency divider number into at least one fractional-n phase lock loop; and utilizing, by the at least one fractional-n phase lock loop, the at least one digital frequency divider number and an analog reference signal produced by a reference oscillator to produce a resultant signal at the transmit frequency; wherein the at least one decoder and the at least one fractional-n phase lock loop are contained on a single integrated circuit.. .
03/27/14
20140089757
Ldpc decoder with fractional local iterations
The present inventions are related to systems and methods for an ldpc decoder with fractional local iterations that may be used in a data processing system with an ldpc decoder and data detector to better balance processing times in the ldpc decoder and data detector.. .
03/27/14
20140089754
Soft message-passing decoder with efficient message computation
A method includes, in a decoder of an error correction code (ecc), maintaining only aggregated information regarding a set of messages, a function of which is to be reported from a first node to a second node of the decoder. The function of the set is determined and reported using the aggregated information.
03/27/14
20140089722
Single wire serial interface
A single wire serial interface for power ics and other devices is provided. To use the interface, a device is configured to include an en/set input pin.
03/27/14
20140089577
Volatile memory device and memory controller
A volatile memory device includes a memory cell array, a command decoder, a self-refresh circuit, and a register. The command decoder is configured to decode a self-refresh entry command, a self-refresh exit command, and a register read command based on external command signals received from outside the volatile memory device.
03/27/14
20140089574
Semiconductor memory device storing memory characteristic information, memory module and memory system having the same, and operating method of the same
A semiconductor memory device storing memory characteristic information, a memory module including the semiconductor memory device, a memory system, and an operating method of the semiconductor memory device. The semiconductor memory device may include a cell array including a plurality of areas; a command decoder configured to decode a command and generate an internal command; and an information storage unit configured to store characteristic information of at least one of the plurality of areas.
03/27/14
20140089363
High speed and low power circuit structure for barrel shifter
A barrel shifter uses a sign magnitude to 2's complement converter to generate decoder signals for its cascaded multiplexer selectors. The sign input receives the shift direction and the magnitude input receives the shift amount.
03/27/14
20140088753
Control system for a fastening power tool
A fastening power tool such as a nailer is provided including a tool housing, an input unit actuated in response to an operator input, and a motor assembly including a motor housed within the tool housing. A control unit is provided including a controller programmable to control an operation of the motor and a decoder circuit configured to control a supply of power from a power source to the controller based on a status of the power source and a status of the input unit.
03/27/14
20140086564
Decoding interdependent frames of a video for display
A module may provide codec-independent services including determining frame display order, frame dependency sets, and queuing the dependency frames in advance so as to enable display of a video. The module enables a video to be played forwards or backwards at a variety of playback speeds from any position within the video.
03/27/14
20140086347
Apparatus and method of receiver architecture and low-complexity decoder for line-coded and amplitude-modulated signal
Interface configured to receive a signal from a transmitter and output an input sequence of m-bit samples. The apparatus also includes a quantizer circuit configured to convert the input sequence of m-bit samples into an output sequence of n-bit samples, wherein m and n are positive integer numbers, and wherein m is greater than n.
03/27/14
20140086344
Coded picture buffer arrival and nominal removal times in video coding
A video coding device, such as a video decoder, may be configured to derive at least one of a coded picture buffer (cpb) arrival time and a cpb nominal removal time for an access unit (au) at both an access unit level and a sub-picture level regardless of a value of a syntax element that defines whether a decoding unit (du) is the entire au. The video coding device may further be configured to determine a removal time of the au based at least in part on one of the cpb arrival time and a cpb nominal removal time and decode video data of the au based at least in part on the removal time..
03/27/14
20140086343
Buffering period and recovery point supplemental enhancement information messages
A video coding device, such as a video decoder, may be configured to decode a buffering period supplemental enhancement information (sei) message associated with an access unit (au). The video decoder is further configured to decode a duration between coded picture buffer (cpb) removal time of a first decoding unit (du) in the au and cpb removal time of a second du from the buffering period sei message, wherein the au has a temporalid equal to 0.
03/27/14
20140086342
Sequence level flag for sub-picture level coded picture buffer parameters
A video coding device, such as a video encoder or a video decoder, may be configured to decode a sequence level flag to determine the presence of one or more sub-picture level coded picture buffer (cpb) parameters for a decoding unit (du) of an access unit (au) in either in a picture timing supplemental enhancement information (sei) message or a sub-picture timing sei message associated with the du. The coding device may also decode the one or more sub-picture level cpb parameters from the picture timing sei message or the sub-picture timing sei message based on the sequence level flag..
03/27/14
20140086341
Coded picture buffer removal times signaled in picture and sub-picture timing supplemental enhancement information messages
A video coding device, such as a video encoder or a video decoder, may be configured to code a sub-picture timing supplemental enhancement information (sei) message associated with a first decoding unit (du) of an access unit (au). The video coding device may further code a duration between coded picture buffer (cpb) removal time of a second du of the au in decoding order and cpb removal time of the first du in the sub-picture sei message.
03/27/14
20140086340
Expanded decoding unit definition
A video coding device, such as a video encoder or a video decoder, may be configured to decode a duration between coded picture buffer (cpb) removal time of a first decoding unit (du) in an access unit (au) and cpb removal time of a second du, wherein the first du comprises a non-video coding layer (vcl) network abstraction layer (nal) unit with nal_unit_type equal to unspec0, eos_nut, eob_nut, in the range of rsv_nvcl44 to rsv_nvcl47 or in the range of unspec48 to unspec63. The video decoder determines a removal time of the first du based at least in part on the decoded duration and decodes video data of the first du based at least in part on the removal time..
03/27/14
20140086337
Indication and activation of parameter sets for video coding
In some examples, a video encoder includes multiple sequence parameter set (sps) ids in an sei message, such that multiple active spss can be indicated to a video decoder. In some examples, a video decoder activates a video parameter set (vps) and/or one or more spss through referencing an sei message, e.g., based on the inclusion of the vps id and one or more sps ids in the sei message.
03/27/14
20140086336
Hypothetical reference decoder parameters in video coding
A computing device selects, from among a set of hypothetical reference decoder (hrd) parameters in a video parameter set and a set of hrd parameters in a sequence parameter set, a set of hrd parameters applicable to a particular operation point of a bitstream. The computing device performs, based at least in part on the set of hrd parameters applicable to the particular operation point, an hrd operation on a bitstream subset associated with the particular operation point..
03/27/14
20140086332
Access unit independent coded picture buffer removal times in video coding
A video coding device, such as a video encoder or a video decoder, may be configured to code a duration between coded picture buffer (cpb) removal time of a first decoding unit (du) in an access unit (au) and a second du, wherein the second du is subsequent to the first du in decoding order and in the same au as the first du. The video coding device may further determine a removal time of the du based at least on the coded duration.
03/27/14
20140086331
Hypothetical reference decoder parameters in video coding
A device performs a hypothetical reference decoder (hrd) operation that determines conformance of a bitstream to a video coding standard or determines conformance of a video decoder to the video coding standard. As part of performing the hrd operation, the device determines a highest temporal identifier of a bitstream-subset associated with a selected operation point of the bitstream.
03/27/14
20140086318
Video compression with color space scalability
An image decoder includes a base layer to decode at least a portion of an encoded video stream into a first image having a first image format. The image decoder can generate a color space prediction by scaling a color space of the first image from the first image format into a color space corresponding to a second image format.
03/27/14
20140086317
Indication and activation of parameter sets for video coding
In some examples, a video encoder includes multiple sequence parameter set (sps) ids in an sei message, such that multiple active spss can be indicated to a video decoder. In some examples, a video decoder activates a video parameter set (vps) and/or one or more spss through referencing an sei message, e.g., based on the inclusion of the vps id and one or more sps ids in the sei message.
03/27/14
20140086316
Video compression with color space scalability
An image decoder includes a base layer to decode at least a portion of an encoded video stream into a first image having a first image format. The image decoder can generate a color space prediction by scaling a color space of the first image from the first image format into a color space corresponding to a second image format.
03/27/14
20140086315
Error resilient management of picture order count in predictive coding systems
Coding techniques for input video may include assigning picture identifiers to input frames in either long-form or short-form formats. If a network error has occurred that results in loss of previously-coded video data, a new input frame may be assigned a picture identifier that is coded in a long-form coding format.
03/27/14
20140086304
Histogram segmentation based local adaptive filter for video encoding and decoding
Reconstructed picture quality for a video codec system may be improved by categorizing reconstructed pixels into different histogram bins with histogram segmentation and then applying different filters on different bins. Histogram segmentation may be performed by averagely dividing the histogram into m bins or adaptively dividing the histogram into n bins based on the histogram characteristics.
03/27/14
20140086299
Frequency domain equalization for wireless communication
Some demonstrative embodiments include devices, systems and/or methods of equalizing received wireless communication signals. For example, a device may include a pre-decoding equalizer to determine a plurality of filter weights by applying both a blind-equalization and a least-mean-squares (lms) equalization to a wireless communication signal received over a wireless communication channel; a channel estimator to estimate a channel frequency response of the channel based on the filtering weights; and a turbo-equalization scheme including a decoder to decode the wireless communication signal and a turbo equalizer to equalize the decoded wireless communication signal using the estimated channel frequency response..
03/27/14
20140086001
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors.


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