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Decoder patents



      
           
This page is updated frequently with new Decoder-related patents. Subscribe to the Decoder RSS feed to automatically get the update: related Decoder RSS feeds.

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Date/App# patent app List of recent Decoder-related patents
04/17/14
20140108880
 Systems and methods for enhanced local iteration randomization in a data decoder patent thumbnailSystems and methods for enhanced local iteration randomization in a data decoder
Systems and methods for data processing particularly related local iteration randomization in a data decoding circuit.. .
04/17/14
20140108716
 Dynamic random access memory for storing randomized data and method of operating the same patent thumbnailDynamic random access memory for storing randomized data and method of operating the same
A dynamic random access memory (dram) includes a memory cell array, a data input/output circuit, and a data randomizer configured to randomize data to be stored in the memory cell array. The data randomizer includes an encoder configured to generate write data by encoding input data received from the data input/output circuit using a randomization code and to output the write data to the memory cell array.
04/17/14
20140108363
 Encoding/decoding processing method, encoder/decoder and terminal patent thumbnailEncoding/decoding processing method, encoder/decoder and terminal
Embodiments of the present invention provide an encoding/decoding processing method, an encoder/decoder, and a terminal. The method includes determining whether a field in a file is a locally recognizable field.
04/17/14
20140108007
 Method and system for low bit rate voice encoding and decoding applicable for any reduced bandwidth requirements including wireless patent thumbnailMethod and system for low bit rate voice encoding and decoding applicable for any reduced bandwidth requirements including wireless
A voice encoder/decoder (vocoder) may provide receiving a voice sample and generating zero crossings of the voice sample in response to voice excitation in a first formant and creating a corresponding output signal. Additional operations may include dividing the output signal by two, and sampling the output signal at a predefined frequency such that a resulting combination uses half of a bit rate for an excitation and a remainder for short term spectrum analysis..
04/17/14
20140105405
 Method and apparatus for creating spatialized sound patent thumbnailMethod and apparatus for creating spatialized sound
A method and apparatus for creating spatialized sound, including the operations of determining a spatial point in a spherical coordinate system, and applying an impulse response filter corresponding to the spatial point to a first segment of the audio waveform to yield a spatialized waveform. The spatialized waveform emulates the audio characteristics of a non-spatialized waveform emanating from the chosen spatial point.
04/17/14
20140105404
 Method, medium, and system synthesizing a stereo signal patent thumbnailMethod, medium, and system synthesizing a stereo signal
A method, medium, and system generating a 3-dimensional (3d) stereo signal in a decoder by using a surround data stream. According to such a method, medium, and system, a head related transfer function (hrtf) is applied in a quadrature mirror filter (qmf) domain, thereby generating a 3d stereo signal by using a surround data stream..
04/17/14
20140105309
 Systems and methods for signaling and performing temporal level switching in scalable video coding patent thumbnailSystems and methods for signaling and performing temporal level switching in scalable video coding
Media communication systems and methods for media encoded using scalable coding with temporal scalability are provided. Transmitting endpoints include switching information in their transmitted media to indicate if temporal level switching at a decoder can occur at any frame of the transmitted encoded media..
04/17/14
20140105290
 Method and apparatus for intra prediction within display screen patent thumbnailMethod and apparatus for intra prediction within display screen
The present invention relates to a method and apparatus for intra prediction. The intra prediction method for a decoder, according to the present invention, comprises the steps of entropy-decoding a received bitstream, generating reference pixels to be used in the intra prediction of a prediction unit; generating a prediction block from the reference pixels on the basis of a prediction mode for the prediction unit and reconstructing an image from the prediction block and a residual block, which is obtained as a result of entropy encoding, wherein the reference pixels and/or the prediction block pixels are predicted on the basis of a base pixel, and the predicted pixel value can be the sum of the pixel value of the base pixel and the difference between the pixel values of the base pixel and the generated pixel..
04/17/14
20140105289
 Efficient architecture for layered vdr coding patent thumbnailEfficient architecture for layered vdr coding
In layered visual dynamic range (vdr) coding, inter-layer prediction requires several color-format transformations between the input vdr and standard dynamic range (sdr) signals. Coding and decoding architectures are presented wherein inter-layer prediction is performed in the sdr-based color format, thus reducing computational complexity in both the encoder and the decoder, without compromising coding efficiency or coding quality..
04/17/14
20140105274
 Video coding redundancy reduction patent thumbnailVideo coding redundancy reduction
Embodiments for reducing redundancy in video coding are disclosed. In accordance with at least one embodiment, video content is represented as a tree structure in which the nodes of the tree structure are associated with attributes of the video content.
04/17/14
20140105272
Low power context adaptive binary arithmetic decoder engine
A technique for decoding data within a context-based adaptive binary arithmetic coding (cabac) stream processes one or more bins of compressed data based on video format parameters associated with the stream. A configurable cabac decoder circuit cascades one or more instances of cabac bin decoder logic to operate properly within a timing constrain established by a decoder clock frequency.
04/17/14
20140105225
Error resilient coding and decoding for media transmission
A “media transmission optimizer” provides a media transmission optimization framework for lossy or bursty networks such as the internet. This optimization framework provides a novel form of dynamic forward error correction (fec) that focuses on the perceived quality of a recovered media signal rather than on the absolute accuracy of the recovered media signal.
04/17/14
20140104948
Split block decoder for a nonvolatile memory device
A non-volatile memory device having a memory array organized into a plurality of memory blocks, having either planar memory cells or stacks of cells. Row decoding circuitry of the memory device is configured to select a group of the plurality of memory blocks in response to a first row address, and to select a memory block of the group for receiving row signals in response to a second row address.
04/17/14
20140104925
Cross-point variable resistance nonvolatile memory device and reading method for cross-point variable resistance nonvolatile memory device
A cross-point variable resistance nonvolatile memory device comprises: a memory cell array; a column decoder and pre-charge circuit which pre-charges a selected word line to a first voltage in a period p1 among the period p1, a period p2, and a period s that are included in this order in a read operation of a memory cell; a low decoder driver which pre-charges a selected word line to the first voltage in the periods p1 and p2 and sets the selected word line to a third voltage different from the first voltage in the period s; a feedback controlled bit line voltage clamp circuit which sets the selected bit line to a second voltage in the periods p2 and s; and a sense amplifier which determines the resistance state in a memory cell at a cross-point of the selected word line and the selected bit line in the period s.. .
04/17/14
20140104715
Data reproduction apparatus, disk storage apparatus and method for reproducing data
According to one embodiment, a data reproduction apparatus includes a decoder, a cancellation process module and a calculator. The cancellation process module cancels, from equalized-waveform data of a read signal, the interference between a signal read from a first track and a signal read form a second track adjacent to the first track.
04/17/14
20140104263
Semiconductor devices having image sensor and memory device operation modes
A semiconductor device may include a plurality of banks; and a control unit configured to receive a command from an external device and independently control the plurality of banks according to the received command. Each bank comprises a pixel array including a plurality of pixels; a row decoder configured to activate word lines connected to the plurality of pixels under control of the control unit; a column decoder configured to activate bit lines connected to the plurality of pixels under control of the control unit; a sense amplifier and write driver configured to control and detect respective voltages of the activated bit lines to provide respective amplified voltages; and an input/output buffer configured to output data states of the pixels based on the respective amplified voltages.
04/17/14
20140104247
Devices and systems for rendering ambient light effects in video
Systems and devices for rendering video associated with ambient light effects are provided. A system includes a receiving device including at least one decoder programmed to parse an incoming video file to separate at least one track including at least one ambient light effect associated with at least one portion of the video file.
04/17/14
20140104083
Two-dimensional run-length limited codec with protection words and method for using same
The invention provides a two-dimensional run-length limited (rll) (1,3) code method and apparatus. The codec comprises an encoder and a decoder comprising a data buffer and grouping module, a two-dimensional code word generating module, a two-dimensional word unit page constructing module, a two-dimensional code word write array module, and a protection word stuffing module.
04/17/14
20140104041
Encoded antenna array and method
A system for identifying which equipment slots of an equipment enclosure have equipment components located in them when specific equipment components containing radio frequency identification (rfid) tags thereon are inserted into specific ones of the equipment slots. The system may use a plurality of antenna elements that wirelessly sense the presence of an rfid tag at any of the equipment slots, and which generate outputs that may be interpreted as forming a plurality of codes.
04/17/14
20140103985
Digitally controlled delay line for a structured asic having a via configurable fabric for high-speed interface
A digitally controlled delay line (dcdl) for a structured asic chip is used to delaying input or output signals into or out of core logic in a structured asic. The dcdl has a multi-stage configuration that in a preferred embodiment comprises two fine delay stages for fine tuning the delay using sub-gate delay through an inverter whose delay can be adjusted with parallel cmos transistors whose gates are biased with a voltage control signal that is thermometer coded.
04/10/14
20140101510
Low density parity check layer decoder for codes with overlapped circulants
The present inventions are related to systems and methods for decoding data in an ldpc layer decoder for ldpc codes with overlapped circulants.. .
04/10/14
20140101501
Scan test circuitry configured to prevent violation of multiplexer select signal constraints during scan testing
An integrated circuit comprises a decoder having a plurality of select signal outputs, a multiplexer having a plurality of select signal inputs subject to a specified select signal constraint, and scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells coupled between respective ones of the select signal outputs of the decoder and respective ones of the select signal inputs of the multiplexer.
04/10/14
20140100856
Apparatus and method for coding and decoding multi object audio signal with multi channel
Provided are an apparatus and method for coding and decoding a multi object audio signal with multi channel. The apparatus includes: a multi channel encoding means for down-mixing an audio signal including a plurality of channels, generating a spatial cue for the audio signal including the plurality of channels, and generating first rendering information including the generated spatial cue; and a multi object encoding unit for down-mixing an audio signal including a plurality of objects, which includes the down-mixed signal from the multi channel encoding unit, generating a spatial cue for the audio signal including the plurality of objects, and generating second rendering information including the generated spatial cue, wherein the multichannel encoding unit generates a spatial cue for the audio signal including the plurality of objects regardless of a coder-decoder (codec) scheme the limits the multi channel encoding unit..
04/10/14
20140100629
Method and system for providing stimulation inputs to a visual prosthesis implant
Stimulation inputs are provided to a visual prosthesis implant. The images captured by a video decoder are received and digitized to provide a plurality of video frames; integrity of the video frames is checked, the checked video frames are filtered, and the filtered video frames are converted to stimulation inputs.
04/10/14
20140099103
Ldpc-coded modulation for ultra-high-speed optical transport in the presence of phase noise
Methods and systems for decoding a signal include compensating for impairments in a received signal using at least carrier phase estimation, where residual phase error remains after compensation; calculating symbol log-likelihood ratios (llrs) for symbols in the compensated signal using monte carlo integration; demapping the symbols in the compensated signal using the symbol llrs and extrinsic information from signal decoding to produce one or more estimated codewords; and decoding each estimated codeword with a decoder that generates a decoded codeword and extrinsic information.. .
04/10/14
20140099068
System and methodology for utilizing a portable media player
A low-cost portable digital video player receives proprietary compressed data from a source such as a personal video recorder (pvr), and displays the data on an integral display. A rewritable non-volatile memory of the player stores the data and a media decoder of the player transforms and decompresses the data.
04/10/14
20140098895
Hypothetical reference decoder parameter syntax structure
A video encoder signals, in an encoded video bitstream, a video parameter set (vps) that includes a plurality of hypothetical reference decoder (hrd) parameter syntax structures that each include hrd parameters. For each respective hrd parameter syntax structure in the plurality of hrd parameter syntax structures, the vps further includes a syntax element indicating whether the hrd parameters of the respective hrd parameter syntax structure include a common set of hrd parameters in addition to a set of sub-layer-specific hrd parameter information specific to a particular sub-layer of the encoded video bitstream.
04/10/14
20140098890
Neighbor determination in video decoding
Video decoding innovations for multithreading implementations and graphics processor unit (“gpu”) implementations are described. For example, for multithreaded decoding, a decoder uses innovations in the areas of layered data structures, picture extent discovery, a picture command queue, and/or task scheduling for multithreading.
04/10/14
20140098889
Frame block comparison
Various arrangements for testing video decoder device functionality are presented. A video frame decoded by a video decoder device under test may be received.
04/10/14
20140098887
Reducing memory consumption during video decoding
Video decoding innovations for multithreading implementations and graphics processor unit (“gpu”) implementations are described. For example, for multithreaded decoding, a decoder uses innovations in the areas of layered data structures, picture extent discovery, a picture command queue, and/or task scheduling for multithreading.
04/10/14
20140098878
Method and device for motion information prediction in multi-view video coding
The invention concerns a method for encoding a video stream, an associated method for decoding a video stream, an associated encoder, an associated decoder and associated computer programs. The encoding method is directed to encoding a video stream comprising at least one video sequence, comprising, for the encoding of a square or rectangular block of a picture of a video sequence of the video stream, selecting a motion information predictor for said block from a list of candidate motion information predictors, and entropic encoding of an index representative of a position of the selected motion information predictor in said list.
04/10/14
20140098863
Video coder providing implicit coefficient prediction and scan adaptation for image coding and intra coding of video
A predictive video coder performs gradient prediction based on previous blocks of image data. For a new block of image data, the prediction determines a horizontal gradient and a vertical gradient from a block diagonally above the new block (vertically above a previous horizontally adjacent block).
04/10/14
20140098858
High precision encoding and decoding of video images
Methods, systems, and computer programs for improved quality video compression. Image quality from mpeg-style video coding may be improved by preserving a higher number of bits during intermediate encoding and decoding processing steps.
04/10/14
20140098855
Lossless intra-prediction video coding
Blocks of a frame of a video stream can be encoded using lossless inter-frame prediction encoding. The compression ratio of lossless inter-frame encoding can be improved by first examining the magnitude of a motion vector used to perform inter-frame prediction.
04/10/14
20140098854
Lossless intra-prediction video coding
Blocks of a frame of a video stream can be encoded using lossless intra-prediction encoding. The compression ratio of lossless intra-prediction encoding can be improved by performing lossy encoding on the intra-predicted residual.
04/10/14
20140098853
Output management of prior decoded pictures at picture format transitions in bitstreams
Systems and methods may be provided for determining whether or not to output the “decoded pictures yet to be output” (dpytbo) after decoding a random access point (rap) picture of the second of two consecutive coded video sequences in a bitstream. The dpytbo pictures may reside in a portion of memory coupled to a video decoder.
04/10/14
20140098851
Indication of video properties
In one example, a method of decoding video data includes receiving, by a video decoder, a coded video sequence and decoding one or more bits of a reserved bits syntax element for the coded video sequence as one or more coding tool enable bits, wherein the reserved bit syntax element is part of a syntax structure that includes profile and level information, and wherein the one or more coding tool enable bits indicate whether one or more coding tools are enabled for use by the video decoder in decoding the video sequence. In some examples, the syntax structure is a profile_tier_level syntax structure.
04/10/14
20140098609
Nonvolatile semiconductor memory apparatus
According to one embodiment, a nonvolatile semiconductor memory apparatus includes a memory cell array, a row decoder, a controller. The memory cell array includes a plurality of memory strings.
04/10/14
20140098592
Resistive memory device including compensation resistive device and method of compensating resistance distribution
A resistive memory device includes a memory cell array, an input/output (i/o) sense amplifier unit, an address input buffer, a row decoder, and a column decoder. The memory cell array includes unit memory cells, and operates in response to a word line driving signal and a column selecting signal, each unit memory cell includes a resistive device and a compensation resistive device.
04/10/14
20140097691
Intelligent power sensing device
The power sensing device includes a power input interface in electrical communication with a current sensing circuit and a voltage sensing circuit. The current sensing circuit is connected to a load.
04/10/14
20140097362
System and method for compressed data transmission in a maskless lithography system
Compression, transmission and decompression of gray-tone imagery data includes receiving a gray-tone image suitable for printing at least a portion of a pattern onto a substrate by operation of an electron beam lithography system, aggregating sets of lines of the gray-tone image into trilines, sequentially encoding each of the trilines of the gray-tone image by operation of one or more encoders, the one or more encoders equipped with a codebook configured to store a plurality of triline fragments and a write location and transmitting the encoded trilines of the gray-tone image to a set of decoders of the digital pattern generator via a set of data pathways established between the one or more encoders and each of the decoders.. .
04/03/14
20140095961
Layered decoder enhancement for retained sector reprocessing
A system is described for recovering data from a number of sectors, such as the sectors of a hard disk drive (hdd) disk platter, and so forth. The system receives data from the sectors via a read channel and uses a layered data decoder to recover data from the sectors.
04/03/14
20140095960
Fully parallel encoding method and fully parallel decoding method of memory system
A memory system, a fully parallel encoding method, and a fully parallel decoding method are disclosed. The encoding method utilizes a plurality of minimal polynomials that constitute a generator polynomial to derive a plurality of roots from the minimal polynomials.
04/03/14
20140095954
Modified targeted symbol flipping for non-binary ldpc codes
A ldpc decoder includes a processor for targeted symbol flipping of suspicious bits in a ldpc codeword with unsatisfied checks. All combinations of check indices and variable indices are compiled and correlated into a pool of targeted symbol flipping candidates and returned along with symbol indices to a process that uses such symbol indices to identify symbols to flip in order to break a trapping set..
04/03/14
20140095947
Functional memory array testing with a transaction-level test engine
A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine hardware is configurable for different tests.
04/03/14
20140095946
Transaction-level testing of memory i/o and memory device
A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine receives a command to cause it to generate transactions to implement a memory test.
04/03/14
20140095891
Instruction set for sha1 round processing on 128-bit data paths
According to one embodiment, a processor includes an instruction decoder to receive a first instruction to process a sha1 hash algorithm, the first instruction having a first operand, a second operand, and a third operand, the first operand specifying a first storage location storing four sha states, the second operand specifying a second storage location storing a plurality of sha1 message inputs in combination with a fifth sha1 state. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to perform at least four rounds of the sha1 round operations on the sha1 states and the message inputs obtained from the first and second operands, using a combinational logic function specified in the third operand..
04/03/14
20140095832
Method and apparatus for performance efficient isa virtualization using dynamic partial binary translation
Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set.
04/03/14
20140093068
Instruction set for skein256 sha3 algorithm on a 128-bit processor
According to one embodiment, a processor includes an instruction decoder to receive a first instruction to perform first skein256 mix-permute operations, the first instruction having a first operand associated with a first storage location to store a plurality of odd words, a second operand associated with a second storage location to store a plurality of even words, and a third operand. The processor further includes a first execution unit coupled to the instruction decoder, in response to the first instruction, to perform multiple rounds of the first skein256 mix-permute operations based on the odd words and even words using a first rotate value obtained from a third storage location indicated by the third operand, and to store new odd words in the first storage location indicated by the first operand..
04/03/14
20140092998
Frame packing and unpacking higher-resolution chroma sampling formats
Video frames of a higher-resolution chroma sampling format such as yuv 4:4:4 are packed into video frames of a lower-resolution chroma sampling format such as yuv 4:2:0 for purposes of video encoding. For example, sample values for a frame in yuv 4:4:4 format are packed into two frames in yuv 4:2:0 format.
04/03/14
20140092997
Error resilient transmission of random access frames and global coding parameters
Error mitigation techniques are provided for video coding system in which input frames are selected for coding either as a random access pictures (“rap frames”) or as a non-rap frame. Coded rap frames may include rap identifiers that set an id context for subsequent frames.
04/03/14
20140092994
Supplemental enhancement information message coding
Techniques are described for signaling decoding unit identifiers for decoding units of an access unit. The video decoder determines which network abstraction layer (nal) units are associated with which decoding units based on the decoding unit identifiers.
04/03/14
20140092993
Error resilient decoding unit association
Techniques are described for signaling decoding unit identifiers for decoding units of an access unit. The video decoder determines which network abstraction layer (nal) units are associated with which decoding units based on the decoding unit identifiers.
04/03/14
20140092992
Supplemental enhancement information including confidence level and mixed content information
This application relates to video encoding and decoding, and specifically to tools and techniques for using and providing supplemental enhancement information in bitstreams. Among other things, the detailed description presents innovations for bitstreams having supplemental enhancement information (sei).
04/03/14
20140092991
Conditional signalling of reference picture list modification information
Innovations in signaling of reference picture list (“rpl”) modification information. For example, a video encoder evaluates a condition that depends at least in part on a variable indicating a number of total reference pictures.
04/03/14
20140092977
Apparatus, a method and a computer program for video coding and decoding
In some embodiments, there is provided an apparatus, a computer readable storage medium stored with code thereon for use by an apparatus, and a video decoder, for decoding a video bitstream, to derive a motion compensated prediction for an enhancement layer block based on a motion compensation process on the co-located base layer block using the same or similar motion vector of enhancement layer blocks and base layer reference pictures. In other embodiments, there is provided a method, an apparatus, a computer readable storage medium stored with code thereon for use by an apparatus, and a video encoder, for encoding a video bitstream, to derive a motion compensated prediction for an enhancement layer block based on a motion compensation process on the co-located base layer block using the same or similar motion vector of enhancement layer blocks and base layer reference pictures..
04/03/14
20140092973
System and method for video transcoding
A video transcoding system includes a video decoder, a video encoder, and a video interface. The video decoder is configured to decode a received video signal.
04/03/14
20140092972
Picture processing in scalable video systems
A system utilizing picture processing in a scalable video system is described. The system may include an electronic device configured to recover a picture processing index corresponding to one or more picture processors, e.g.
04/03/14
20140092971
Picture processing in scalable video systems
A system utilizing picture processing in a scalable video system is described. The system may include an electronic device configured to recover a picture processing index corresponding to one or more picture processors, e.g.
04/03/14
20140092964
Apparatus, a method and a computer program for video coding and decoding
There are disclosed various methods, apparatuses and computer program products for video encoding and decoding. In other embodiments, there is provided a method, an apparatus, a computer readable storage medium stored with code thereon for use by an apparatus, and a video encoder, for encoding a scalable bitstream, to provide indicating an encoding configuration, where only samples and syntax from intra coded pictures of base layer is used for coding the enhancement layer pictures.
04/03/14
20140092963
Signaling of regions of interest and gradual decoding refresh in video coding
During a coding process, systems, methods, and apparatus may code information indicating whether gradual decoder refresh (gdr) of a picture is enabled. When gdr is enabled, the coding process, systems, methods, and apparatus may code information that indicates whether one or more slices of the picture belong to a foreground region of the picture.
04/03/14
20140092961
Signaling decoder picture buffer information
A system for decoding a video bitstream includes receiving a frame of the video that includes at least one slice and at least one tile and where each of the at least one slice and the at least one tile are not all aligned with one another.. .
04/03/14
20140092960
Bounded rate compression with rate control for slices
A system implements rate control for encoding and decoding operations, for example, operations performed on slices of data such as image data. The system implements a transformation from actual buffer fullness to rate controlled fullness.
04/03/14
20140092957
2d block image encoding
A coder (e.g., an encoder or decoder) implements coding of two dimensional blocks of image data using two dimensional differential pulse code modulation (2d dpcm). The coder may switch between dpcm and other types of coding, such as transform coding on a block by block basis.
04/03/14
20140092955
Signaling layer identifiers for operation points in video coding
Techniques described herein are related to coding layer identifiers for operation points in video coding. In one example, a method of decoding video data is provided.
04/03/14
20140092954
Method and apparatus for encoding video to play at multiple speeds
Data that is to be transmitted to a viewer is encoded multiple times at multiple playback speeds. For example, a video advertisement may be encoded to play at normal speed, 4× normal speed, and 16× normal speed.
04/03/14
20140092218
Apparatus and method for stereoscopic video with motion sensors
An apparatus and method for a video capture device for recording 3 dimensional (3d) stereoscopic video with motion sensors is provided are provided. The apparatus includes includes a camera unit having one lens for capturing video, a video encoder/decoder for encoding the captured video, a motion sensor for capturing motion data of the video capture device corresponding to the captured video, and a controller for controlling the video encoder/decoder and motion sensor to encode the captured video with the captured motion data..
04/03/14
20140092213
Sub-bitstream extraction for multiview, three-dimensional (3d) and scalable media bitstreams
Techniques are described for modal sub-bitstream extraction. For example, a network entity may select a sub-bitstream extraction mode from a plurality of sub-bitstream extraction modes.


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