|| List of recent Decimation-related patents
|Implement for extraction and decimation of plant stalks|
An implement for extraction and decimation of plant stalks with a puller section and flail section. The puller section is driven by a motor and uses a pair of track belts with interlocking protrusions to grab plant stalks and pull them up by the root.
|Direct conversion receiver including a charge area decimation filter|
A direct conversion receiver includes: a high linearity mixer device including a sampler unit charge-sampling an input current according to a sampling frequency, and a buffer unit receiving an output signal from the sampler unit while having a low input impedance, amplifying the received signal, and outputting a current signal; and a filter device decimating an output signal from the mixer device and fir-filtering the decimated signal.. .
|Computation of statistics for statistical data decimation|
Systems and methods for statistical data decimation are described. The method includes receiving a variable from a radio frequency (rf) system, propagating the variable through a model of the rf system, and counting an output of the model for the variable to generate a count.
|Harmonic decimation of real time data for unique word (or sync cell) acquisition in a limited processing environment|
A non-transitory computer-readable medium, method, and system for processing a first data stream being in a first format from a link, the first data stream having a plurality of frames, each frame having a fixed frame length; selecting a plurality of sections of the first data stream based on a harmonic pattern of the first format, each selected section being separated from a neighboring selected section by a fixed separation length that is a whole number multiple of the fixed frame length; and creating a second data stream in a second format that includes a contiguous sequence of the selected sections. The second data stream can be further processed to acquire frame alignment with a reduction of required processing power..
|Method and device for testing the material of a test object in a nondestructive manner|
A method for testing the material of a test object (8) in a nondestructive manner, said test object being moved relative to a probe (1) at a variable relative speed, comprises the following steps: detecting a probe signal (us) by means of the probe (1), subjecting the probe signal (us) to analog-to-digital conversion in order to generate a digitized probe signal (usd) in the form of a sequence of digital words with a predefined, in particular constant, word repetition rate, n-stage decimation of the word repetition rate of the digitized probe signal (usd) or of a digital demodulation signal (um) derived from the digitized probe signal by means of n cascaded decimation stages (5_1 to 5_n), where n≧2, selecting an output signal (ua_1 to ua_n) of one of the n decimation stages (5_1 to 5_n) depending on the instantaneous relative speed and filtering the selected output signal by means of a digital filter (7), which is clocked with the word repetition rate of the selected output signal.. .
|Method and system for processing data acquired in an electromagnetic survey|
The current application is directed to methods and systems for processing em-survey data in order to extract accurate earth-response curves from the raw em-survey data. The more accurate earth-response curves are obtained as a result of a generally non-linear decimation, or parameterization, of the earth-response curves, the non-linear parameterization generally applied to extraction of earth responses from raw em-survey data collected by multiple em sensors.
|Wideband software-defined rf receiver|
An rf receiver is disclosed. The rf receiver includes an analog-to-digital converter for converting an analog intermediate frequency band signal to a digital intermediate frequency band signal.
|Interleaved phase sector based rf signal decimation|
Values representative of modulation signal components are extracted from a modulated signal. The modulated signal contains a modulation signal.
|Periodic time segment sequence based decimation|
Filtered signal values are extracted from an input signal. A periodic time segment sequence having a plurality of ordered time segments is defined.
|Phase sector based rf signal decimation|
Values representative of modulation signal components are extracted from a modulated signal. The modulated signal contains a modulation signal.
|Lensless imaging camera performing image formation in software employing micro-optic elements creating overlap of light from distant sources over multiple photosensor elements|
A lensless camera with image formation performed by image processing software rather than by lens. Image formation operations are coordinated with a micro-optical element array that can comprise apertures, micro-optic layers, etc.
A system includes a decimation module having an adjustable decimation rate and a filter module responsive to the decimation module. A digital phase lock loop is operable to control a decimation rate of the decimation module.
|Lte-advanced primary synchronization signal detection|
Various embodiments of primary synchronization signal detection are provided. In one aspect, a method receives one or more signals at one or more antennas of a receiver.
|Velocity estimation for vector flow imaging (vfi) in ultrasound|
An ultrasound imaging system includes a transducer array, with an array of transducer elements that transmits an ultrasound signal and receives a set of echoes generated in response to the ultrasound signal traversing a flowing structure. The ultrasound imaging system further includes a beamformer that beamforms the set of echoes, generating a beamformed signal.
|System and method of image reconstruction with dual line scanner using line counts|
A fingerprint scanning and image reconstruction system and method including a fingerprint scanner providing a first scan line and a second scan line separated by a line separation distance in a scanning direction. The system includes an image reconstruction module accumulating scan lines including at least the first scan line and the second scan line over a time period t.
|Delta-sigma analog-to-digital converter with error suppression|
A delta-sigma analog-to-digital converter (ΔΣ adc) has a delta-sigma modulator, a decimation filter and an error suppression circuit. The delta-sigma modulator receives an analog input, and converts the analog input into a first digital output.
|Image pickup apparatus capable of shooting at high frame rate, control method therefor, and storage medium|
An image pickup apparatus which is capable of obtaining a high-quality image at high speed even when frame rate is high. A frame rate control unit controls frame rate for the shooting.
|Collaborative giving system and method|
A collaborative giving system/method that coordinates the decimation and sharing of donor gifts within a cooperating group of donee recipients is disclosed. The system/method allows donee-specific donor databases to drive automated and spatially-distributed fundraising efforts for a collaborative project with donated funds being decimated and shared among collaborative donees while simultaneously guaranteeing that donor anonymity is maintained with respect to each individual donee-specific donor database.
|Systems and methods for programmatically filtering frequency signals|
Certain embodiments herein describe filtering signals or channels using a programmable bandwidth filter. Each channel may be filtered according to a different bandwidth such that noise may be removed from each channel without the need to increase the complexity of an anti-aliasing filter, for example.
|System and method for selecting parameters for compressing coefficients for nodescale vectoring|
In general, the present invention relates to methods and systems for optimizing the precoder coefficient compression parameters for reducing the storage and other demands on a vectored dsl system. Embodiments of the invention can be implemented in conjunction with various existing coefficient compression techniques such as quantization of coefficients and decimation in frequencies.
|On-the-fly compensation of sampling frequency and phase offset in receiver performing ultra-high-speed wireless communication|
Received data oversampled twice is polyphased by the receiver, feedback is applied using an adaptive algorithm, and the filter coefficients (tap coefficient sequence) of a compensation filter are simultaneously shifted when the data shifts. The sampling frequency and the phase offset can be compensated for on the fly using a filter combining a tapped filter whose initial value is a correlation value obtained from the preamble and header of a received signal, and a wavefront aligner.
|Multi-mode orthogonal frequency division multiplexing transmitter for highly-spectrally-efficient communications|
A transmitter may comprise a symbol mapper circuit and operate in at least two modes. In a first mode, the number of symbols output by the mapper circuit per orthogonal frequency division multiplexing (ofdm) symbol transmitted by said transmitter may be greater than the number of data-carrying subcarriers used to transmit the ofdm symbol.
|Non-interfering physiological sensor system|
A system includes a light source, a photodetector in optical communication with the light source, and a processor in communication with said photodetector and configured to output a signal representing oxygen saturation independent of an interfering signal from an interfering source. The system may further include an analog-to-digital converter in communication with the processor that is configured to digitize a signal from the photodetector by oversampling and output oversampling data to the processor.
|Systems and methods for ycc image processing|
Systems and methods for processing ycc image data provided. In one example, an electronic device includes memory to store image data in rgb or ycc format and a ycc image processing pipeline to process the image data.
|System and method for operating an analog to digital converter|
A system and method can be used for scaling an output of a modulator of a sigma-delta analog to digital converter and systems and a method can be used for compensating temperature-dependent variations of a reference voltage in a sigma-delta analog to digital converter. In accordance with one embodiment, a system can be used for scaling an output of a modulator of a sigma-delta analog digital converter (adc).
|Video encoding device and encoding method thereof|
A video encoding device includes a codec unit to encode first image data to be output as a bitstream and to generate a rate control signal according to a result of the encoding and a pre-processor to perform a decimation operation on second image data successive to the first data and to transmit the second image data to the codec unit.. .
|Multi-rate oversampling of analog signals in storage devices|
Multi-rate oversampling of analog signals in storage devices is described. A method of processing an analog signal derived from a storage medium in a storage device includes: filtering the analog signal with an anti-alias filter having a fixed cut-off frequency related to a target sampling rate; sampling the analog signal using an over-sampling rate of a plurality of over-sampling rates provided by a variable-rate analog-to-digital converter (adc) to produce an over-sampled digital signal; and filtering the over-sampled digital signal using a decimation filter of a plurality of decimation filters provided by a digital signal processor (dsp) to produce a digital signal having the target sampling rate..
A receiver and method is provided for sigma-delta converting an rf signal to a digital signal and downconverting to a digital baseband signal. The rf signal is split into n phases, as can be accomplished using a sample and hold circuit, and each phase is digitized, as can be accomplished using an analog-to-digital (a/d) sigma-delta converter.
|3d video transmission on a legacy transport infrastructure|
The present disclosure relates to a method for transmitting two consecutive pairs of images. The method may include decimating each image with a ratio of 2, assembling the two decimated images of each pair in a composite image, transmitting the composite images, and reconstructing complete images from the composite images.
|All-pass filter phase linearization of elliptic filters in signal decimation and interpolation for an audio codec|
An audio signal processing system includes parallel speech and generic audio signal processing paths. One path includes a linear predictive coder and a resampling filter having a non-linear phase characteristic.
|Non-uniform echo train decimation|
Method and apparatus using at least one process to reduce a data set using a data adaptive down-sampling scheme comprising a plurality of non-uniform down-sampling factors. The method may include separating the data set into a plurality of data windows, where each of the plurality of data windows corresponds to one of the plurality of non-uniform data-sampling factors; applying the down-sampling factors, and transmitting the reduced data set from a downhole location to the surface.
|Measuring device and a method for the decimation of a datastream|
A measuring device for an oscilloscope provides a decimation unit. The decimation unit provides at least one input, which receives a datastream with a plurality of sampled values from at least one data source.
|Systems and methods for decimation based over-current control|
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. In some such systems and methods, the operation of one or more calibration circuits is modified when it is determined that too many data processing circuits are active..
|Digital front end receiver using dc offset compensation scheme|
The present invention relates to a digital front end receiver using a dc offset compensation scheme. The digital front end receiver includes a dc offset compensation filter configured to remove dc offset components from signals received from a digital mixer and a cascaded integrator-comb (cic) decimation filter configured to reduce a sampling rate of the signals received from the dc offset compensation block..
|Powerline communication receiver|
Aspects of the present disclosure are directed towards a circuit-based apparatus for receiving data communications over power distribution lines that carry power using alternating current (ac). The apparatus has a processing circuit that is configured and arranged to receive an input signal representing the data communications over power distribution lines.
|Digital signal processing for plc communications having communication frequencies|
Aspects of the present disclosure are directed toward receiver devices and methods of using receiver devices. One such method can include converting, using an analog-to-digital converter (adc), and an analog input signal from power distribution lines that carry power using alternating current (ac) to a digital form.
|High sensitivity environmental sensor board and methods for structural health monitoring|
A smart sensor circuit board comprises an interface to a wireless smart sensor board platform, a multi-axis accelerometer having a sensitivity that can measure ambient structural vibrations resulting from non-catastrophic routine environmental factors, an analog to digital converter (adc) for converting signals from the multi-axis accelerometer having a plurality of individual channels including oversampling, filtering, and decimation, and each channel being individually programmable for gain, anti-aliasing, cut-off frequency, sampling, and frequency providing data to the interface, and a low noise and high sensitivity amplifier having the plurality of individual channels to receive signals from the multi-axis accelerometer.. .
|Image processing device and image processing method|
In the printer, the correction content setting portion sets equal to or more than one correction contents, the decimation rate setting portion sets decimation rates for respective planes of y, cb, and cr of jpeg data (compressed data) based on the set correction contents. Pixels are decimated at the set decimation rates and the decompression processing unit decompresses the jpeg data so as to generate image data.
|Microphone array with daisy-chain summation|
Microphone stages in a microphone array may be coupled together in a daisy chain. Each stage may include a microphone, an analog to digital converter, a decimation unit, a receiver, an adder, and a transmitter.
|Control channel information transmission method, and base station and terminal using the same method|
A radio communication system that includes an encoder configured to perform error correction coding for control channel information by a given error correction coding rate and a modulator configured to perform modulation of the error correction coded control channel information for transmission according to a given modulation scheme, code decimation being performed for the error correction coded control channel information prior to the modulation, and the code decimation being different according to whether multi input multi output is applied or not.. .
|Control channel information transmission method, and base station and terminal using the same method|
A radio communication system that includes an encoder configured to perform error correction coding for control channel information by a given error correction coding rate; a modulator configured to perform modulation of the error correction coded control channel information for transmission according to a given modulation scheme; and a processing section configured to perform code decimation of the error correction coded control channel information prior to the modulation, the code decimation being different according to whether the multi input multi output is applied or not.. .
The present invention relates to an orthogonal frequency-division multiplexing receiver, and more particular to an orthogonal frequency-division multiplexing receiver including an fft/ifft operating core and a scheduler. In order to simultaneously share the fft/ifft operating core, the scheduler manages input/output timings of fft/ifft operations and control signals.
|Simd memory circuit and methodology to support upsampling, downsampling and transposition|
An apparatus and method for creation of reordered vectors from sequential input data for block based decimation, filtering, interpolation and matrix transposition using a memory circuit for a single instruction, multiple data (simd) digital signal processor (dsp). This memory circuit includes a two-dimensional storage array, a rotate-and-distribute unit, a read-controller and a write to controller, to map input vectors containing sequential data elements in columns of the two-dimensional array and extract reordered target vectors from this array.
|Physiological acoustic monitoring system|
A physiological acoustic monitoring system receives physiological data from an acoustic sensor, down-samples the data to generate raw audio of breathing sounds and compresses the raw audio. The acoustic monitoring system has an acoustic sensor signal responsive to tracheal sounds in a person.
|Image processing apparatus, display apparatus, and image processing method|
When a single pixel is displayed by four color sub-pixels, or r (red), g (green), b (blue), and g, in a bayer array, this invention sets the scaling rate of a scaling process to 3/2 times when executing the scaling process on image data having three color components, or r, g, and b, and then executes a color conversion process for finding four color components from the three color components; after this, a decimation process for reducing the number of pixels is carried out. Setting the scaling rate of the scaling process to an integer proportion, moirés caused by the scaling process can be made less noticeable.
|Novel efficient digital microphone decimation filter architecture|
A new and more efficient filtering system (e.g., digital microphone decimation filter architecture system) is described. A key to this architecture is the use of two parallel filter paths.
|Fully compensated adaptive interference cancellation system|
A system for removing interference comprising a receive decimation filter that accepts a composite received baseband signal and generates filtered sampled data at a decimation rate, a transmit decimation filter that accepts a digitally converted replica of an interfering signal and generates filtered sampled data at a decimation rate, an integer sample delay control (isdc) that provides multiple sample delay control for the replica and stores an estimated delay value, an adaptive filter that provides fractional sample delay control for the replica of the interfering signal and optimizes cancellation of the interfering signal, a digital phase-locked loop (dpll) programmed with a known frequency offset of the interfering signal that tracks a phase and frequency of the replica of the interfering signal, an automatic gain control (agc) that maintains near full scale operation of adaptive filtering and the dpll, and a slicer, mixer, and delay unit forming an error estimator.. .
To variably change the filter characteristic of a decimation filter in accordance with a sampling rate. A decimation filter 13 in a semiconductor device 1 sequentially inputs a signal sampled at a predetermined sampling rate fos, and calculates, for each input signal that is input within a predetermined period (a period for m+2n), a filter coefficient cj for performing predetermined filtering processing in response to a trigger signal tr continuously applied, and furthermore sequentially multiplies the input signal by the calculated filter coefficient, accumulates a multiplication value within the predetermined period, and sequentially outputs the result.
|Image pickup device and evaluation value generating device|
An image pickup device may include an image capturing unit that includes a solid-state image pickup device having a plurality of pixels arrayed in a matrix form, the image capturing unit sequentially outputting a plurality of image capturing signals each of which corresponds to one of a plurality of pixel signals output from the solid-state image pickup device, and an evaluation value generating unit to which the plurality of image capturing signals output from the image capturing unit are sequentially input, the evaluation value generating unit generating an evaluation value based on the input image capturing signals. The evaluation value generating unit may include a horizontal decimation unit, a vertical decimation unit, a vertical evaluation value generating unit, and a horizontal evaluation value generating unit..
|Image processing apparatus, image processing method, and computer-readable, non-transitory medium|
There are provided an image processing apparatus, image processing method, and a computer-readable, non-transitory medium that can determine with high accuracy whether or not an input image contains a background element. The image processing apparatus includes a decimated image generator for generating a decimated image through pixel decimation from an input image, an edge pixel extractor for extracting edge pixels from the decimated image, an edge class extractor for extracting an isolated edge pixel from among the edge pixels, a histogram generator for generating an isolated histogram based on the isolated edge pixel, and a decision unit for making, based on the isolated histogram, a decision as to whether or not the input image contains a background element..
|Method and a device for preventing signal-edge losses|
A method for marking a signal edge, which has been removed from at least one decimated binary signal after the decimation of an associated binary signal, within the decimated binary signal, establishes successive signal portions of the respective binary signal, in each case with a number of sampled values corresponding to a decimation factor of the decimation. It detects a signal edge removed through decimation from each signal portion if the number of signal edges determined in each signal portion of the respective binary signal is greater than one.