|| List of recent Deasserted-related patents
|Method and circuit for detecting usb 3.0 lfps signal|
A system and method for efficient detection of low frequency periodic signaling (lfps) input signals. A receiver receives two input differential signals that are lfps input signals.
Advanced Micro Devices, Inc.
|Apparatus and a erasing data stored in a memory device|
The present invention provides an apparatus and method for erasing data in a memory device comprising an array of memory cells, and configured to operate from a clock signal. The apparatus includes erase circuitry, responsive to receipt of an erase signal in an asserted state, to perform a forced write operation independently of the clock signal in respect of each memory cell within a predetermined erase region of said array.
|Non-volatile memory using bi-directional resistive elements|
A memory cell includes a first bidirectional resistive memory element (brme), and a second brme, a first storage node, and a second storage node . A resistive memory write to the cell includes placing the first brme and the second brme in complementary resistive states indicative of the value being written.
|Display circuitry with reduced pixel parasitic capacitor coupling|
A touch screen display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor (tft) layer.
|Method and adaptive timing write control in a memory|
A bit line, which is coupled to a resistive element of a memory cell is set to a first voltage level. The memory cell may be an mram cell or an rram cell.
|Methods and improving backlight driver efficiency|
An electronic device may be provided with display circuitry that includes a display timing controller, a backlight driver, a light source, and other associated backlight structures. The backlight control circuitry may generate a control signal having an adjustable duty cycle to the backlight driver.
|Apparatus and hidden-refresh modification|
A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration.
|Forward error correction decoder|
A method for determining an initial alignment for a frame of input data is provided. A frame for the input data is set, and the frame is synchronized.
|Method and automatic time-shifting for a content recorder|
A content player includes a pausable mass storage device player that can be used to record and play content. The pausable mass storage device can become paused in response to an assertion of a pause signal.
|Oscillators and clock generation|
Oscillator circuitry having a switching inverting amplifier arranged in a ring oscillator configuration of at least two stages. A bias generator for supplying the amplifiers of neighboring stages, is responsive to an enable signal to supply the amplifiers only when the enable signal is asserted.
Power contollers and control methods
Disclosure has power controllers and control methods used therein. A disclosed power controller is adapted for a power converter to power at least one light emitting diode.
Pipeline power gating
Leakage current is reduced in a plurality of gates coupled between source storage elements and destination storage elements by waking the plurality of gates to allow current flow in response to assertion of any source clock enable signals that enable clocking of the source storage elements. The gates are slept to reduce leakage current in the plurality of gates, in response to assertion of a destination clock enable signal and all of the one or more source clock enable signals being deasserted, the destination clock enable signal enabling clocking of the destination storage elements..
Multi-mode combined rotator
A system and method for efficiently rotating data in a processor for multiple operand sizes. A processor comprises a rotator configured to support multiple operand sizes.