|| List of recent Conductive Layer-related patents
| Method of forming semiconductor structure having contact plug|
A method of forming a semiconductor structure having at least a contact plug includes the following steps. At first, at least a transistor and an inter-layer dielectric (ild) layer are formed on a substrate, and the transistor includes a gate structure and two source/drain regions.
| Method of fabricating capacitor structure|
A method of fabricating a capacitor structure includes the following steps. Firstly, a substrate is provided.
| Organic light emitting diode display and method for manufacturing the same|
An organic light emitting diode (oled) display and a manufacturing method thereof, the oled display includes: a substrate main body; a polycrystalline silicon layer pattern including a polycrystalline active layer formed on the substrate main body and a first capacitor electrode; a gate insulating layer pattern formed on the polycrystalline silicon layer pattern; a first conductive layer pattern including a gate electrode and a second capacitor electrode that are formed on the gate insulating layer pattern; an interlayer insulating layer pattern formed on the first conductive layer pattern; and a second conductive layer pattern including a source electrode, a drain electrode and a pixel electrode that are formed on the interlayer insulating layer pattern. The gate insulating layer pattern is patterned at a same time with any one of the polycrystalline silicon layer pattern and the first conductive layer pattern..
| Electrophotographic photoconductor, image forming apparatus, and process cartridge|
An electrophotographic photoconductor, including: an electroconductive substrate; and at least a photoconductive layer and a surface layer in this order over the electroconductive substrate, wherein the surface layer includes a resin having no charge transport properties, and first inorganic fine particles, and wherein the first inorganic fine particles are inorganic fine particles having surfaces modified with at least one of a primary amino group and a secondary amino group, and a volume resistivity of the first inorganic fine particles is 1×108 Ω·cm or less.. .
| Electric storage device and manufacturing method thereof|
Provided is an electric storage device including: a first electrode plate, a second electrode plate having a polarity opposite to that of the first electrode plate, and a separator interposed between the first electrode plate and the second electrode plate, wherein the first electrode plate includes a current collector, a conductive layer laminated onto the current collector, and a mixture layer laminated onto the conductive layer, the mixture layer contains a binder and primary particles of an active material as its constituents, and the primary particles as a constituent of the mixture layer are partially retained in the conductive layer.. .
| Integrated circuit 3d phase change memory array and manufacturing method|
A 3d phase change memory device can store multiple bits per cell represented by a plurality of non-overlapping ranges of resistance all of which are established by different resistance ranges corresponding to respective amorphous phase thickness of the phase change memory material. An array of access devices can underlie a plurality of conductive layers, separated from each other and from the array of access devices by insulating layers.
| Metal mesh conductive layer and touch panel having the same|
The present invention relates to to a metal mesh conductive layer and touch panel having the conductive layer. A surface of the conductive layer includes a transparent electrode region and an electrode lead region, the transparent electrode region having a mesh made of metal; the electrode lead region having a mesh made of conductive material containing metal.
| Input element for operating a touch-screen|
There is described an input element for operating a touch-screen, said input element comprising an electrically conductive layer which is applied to an electrically non-conductive substrate. The electrically conductive layer is structured and has at least one button, conductor track and/or electrode, wherein at least one electrode and/or conductor track is operatively connected to the touch-screen..
| Touch display apparatus|
A touch display apparatus including a display panel, a touch panel, a transparent conductive layer, and a conductive adhesive layer is provided. The touch panel is disposed on the display panel, and includes a cover lens, a touch device, and a shielding conductive ring.
| Silicon-based electrode for a lithium-ion cell|
A silicon-based electrode includes a silicon layer on a substrate, an electrically conductive layer overlying a top surface of the silicon layer, an optional polymer layer overlying the top surface of the electrically conducting layer, and a plurality of channels extending through the electrically conductive layer and the silicon layer to the substrate. The channels define sidewalls in the silicon layer.
| Conductive layer of a large surface for distribution of power using capacitive power transfer|
An apparatus (300) for supplying power to a load in a capacitive power transfer system comprises a power generator (350) operating at a first frequency; a transmitter comprising a plurality of first electrodes (310) connected to a first terminal of the power generator (350) and a plurality of second electrodes (320) connected to a second terminal of the power generator (350) of a transmitter portion of the apparatus (300); and a plurality of inductors (340), wherein each inductor of the plurality of inductors is connected between a pair of a first electrode and a second electrode of the plurality of first and second electrodes, wherein each inductor comprises, together with a parasitic capacitor (330) formed between each pair of the first electrode and the second electrode, a resonant circuit at the first frequency in order to compensate for current loss due to parasitic capacitances.. .
| Mold, mold manufacturing method and method for manufacturing anti-reflection film using the mold|
A mold of at least one embodiment of the present invention includes: a base; a conductive layer provided on the base; and an anodized film provided on the conductive layer, the anodized film having an inverted motheye structure in its surface, the inverted motheye structure having a plurality of recessed portions whose two-dimensional size viewed in a direction normal to the surface is not less than 10 nm and less than 500 nm, wherein the base, the conductive layer, and the anodized film are capable of transmitting ultraviolet light.. .
| Package structure and method for manufacturing thereof|
The invention provides an electronic device package and method for manufacturing thereof. The electronic device package includes a substrate, an electronic chip, a bonding pad, a first passivation layer, a conductive layer, a second passivation layer, and a solder ball.
| Mim capacitor and mim capacitor fabrication for semiconductor devices|
In a particular embodiment, a method of forming a metal-insulator-metal (mim) capacitor includes removing, using a lithographic mask, a first portion of an optical planarization layer to expose a region in which the mim capacitor is to be formed. A second portion of an insulating layer is formed on a first conductive layer that is formed on a plurality of trench surfaces within the region.
| Circuit board and display device|
A source and drain electrode layer (3s/3d) of an oxide tft element (3) is formed by a first conductive layer. A gate electrode (3g) of the oxide tft element (3) and a gate electrode (5g) of an a-si tft element (5) are formed by a single conductive layer, that is, a second conductive layer.
| Transistor and display device|
It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material.
| Thin film transistor and display substrate having the same|
A display substrate includes a base substrate, a semiconductor active layer disposed on the base substrate, a gate insulating layer disposed on the semiconductor active layer, a first conductive pattern group disposed on the gate insulating layer and including at least a gate electrode, a second conductive pattern group insulated from the first conductive pattern group and including at least a source electrode, a drain electrode, and a data pad. The second conductive pattern group includes a first conductive layer and a second conductive layer disposed on the first conductive layer to prevent the first conductive layer from being corroded and oxidized..
| Sputtering apparatus and method for forming a transmissive conductive layer of a light emitting device|
There is provided a method for manufacturing a nitride semiconductor light emitting device, including: forming a light emitting structure including first and second conductive nitride semiconductor layers on a substrate and an active layer formed therebetween; forming the first conductive nitride semiconductor layer, the active layer, and the second conductive nitride semiconductor layer in sequence; forming a first electrode connected to the first conductive nitride semiconductor layer; forming a photo-resist layer on the second conductive nitride semiconductor layer so as to expose a portion of the semiconductor layer; and removing the photo-resist layer after a reflective metal layer and a barrier metal layer serving as a second electrode structure are successively formed on the second conductive nitride semiconductor layer exposed by the photo-resist layer.. .
| Resilient adherent emi shielding member|
In order to prevent emi leakage from various openings formed in module-receiving receptacles, a flexible, conductive shield member is provided. The shield member may have multiple layers but includes at least a conductive layer and an adhesive layer.
| A composite glass plate|
In order to obtain a composite glass plate which shields infrared light and/or ultraviolet light, two glass substrates on which transparent conductive layers are formed respectively are disposed with the transparent conductive layers thereof facing each other. Infrared light is shielded and electric power is generated by using one glass substrate as a light incident side electrode, disposing a silicon dioxide particle layer thereon, and filling a colorless electrolyte between the two glass substrates.
|Method for forming interlayer connectors to a stack of conductive layers|
A method forms interlayer connectors extending to conductive layers of a stack of w conductive layers interleaved with dielectric layers. The stack is etched to expose landing areas at w−1 conductive layers using a set of m etch masks.
|Backlight module, printed circuit board used for backlight module, and manufacturing method for the same|
The present invention discloses a backlight module, a printed circuit board used for a backlight module, and a manufacturing method for the same. The printed circuit board comprises a light bar region and a heat dissipating region.
|Borderless touch panel design|
A borderless touchscreen panel includes a first conductive layer having rows of capacitive sensors and receiving traces, and a second conductive layer having columns of sensor bars and transmitting traces. The capacitive sensors are coupled to control circuitry via the receiving traces, and the sensor bars are coupled to the control circuitry via the transmitting traces.
|Interconnection structures and fabrication method thereof|
A method is provided for fabricating an interconnection structure. The method includes providing a semiconductor substrate having certain semiconductor devices inside, a dielectric layer covering the semiconductor devices, and vias inside the dielectric layer connecting with connection pads of the semiconductor devices.
|Forming vias and trenches for self-aligned contacts in a semiconductor structure|
A semiconductor structure is formed to include a non-conductive layer with at least one metal line, a first dielectric layer, a first stop layer, a second dielectric layer, a second stop layer, a third stop layer and a fourth stop layer. A first photoresist layer is formed over the upper stop layer to develop at least one via pattern.
|Semiconductor device and method of manufacturing the same|
A semiconductor device includes a substrate in which a cell region and a contact region are defined, a pad structure including a plurality of first conductive layers and a plurality of first insulating layers formed alternately with each other in the contact region of the substrate, wherein an end of the pad structure is patterned stepwise, portions of the first conductive layers exposed at the end of the pad structure are defined as a plurality of pad portions, and the plurality of pad portions have a greater thickness than unexposed portions of the plurality of first conductive layers.. .
|3d stacking semiconductor device and manufacturing method thereof|
A 3d stacking semiconductor device and a manufacturing method thereof are provided. The manufacturing method includes the following steps.
|Semiconductor package and fabrication method thereof|
A semiconductor package is provided. The semiconductor package includes a substrate; a semiconductor element having opposite active and inactive surfaces and disposed on the substrate via the active surface thereof, wherein the inactive surface of the semiconductor element is roughened; a thermally conductive layer bonded to the inactive surface of the semiconductor element; and a heat sink disposed on the thermally conductive layer.
|Semiconductor package and fabrication method thereof|
A semiconductor package is provided, including: a substrate; a first semiconductor element disposed on the substrate and having a first conductive pad grounded to the substrate; a conductive layer formed on the first semiconductor element and electrically connected to the substrate; a second semiconductor element disposed on the first semiconductor element through the conductive layer; and an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements. Therefore, the first and second semiconductor elements are protected from electromagnetic interference (emi) shielding with the conductive layer being connected to the grounding pad of the substrate.
|Semiconductor-on-oxide structure and method of forming|
Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer..
|Method of manufacturing a non-volatile memory|
The disclosure relates to a method of manufacturing vertical gate transistors in a semiconductor substrate, comprising implanting, in the depth of the substrate, a doped isolation layer, to form a source region of the transistors; forming, in the substrate, parallel trench isolations and second trenches perpendicular to the trench isolations, reaching the isolation layer, and isolated from the substrate by a first dielectric layer; depositing a first conductive layer on the surface of the substrate and in the second trenches; etching the first conductive layer to form the vertical gates of the transistors, and vertical gate connection pads between the extremity of the vertical gates and an edge of the substrate, while keeping a continuity zone in the first conductive layer between each connection pad and a vertical gate; and implanting doped regions on each side of the second trenches, to form drain regions of the transistors.. .
|Light emitting device and lighting system|
A light emitting device includes a conductive support member, a first conductive layer disposed on the conductive support member, a second conductive layer disposed on the first conductive layer, a light emitting structure including a first semiconductor layer, layer disposed on the second conductive layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer, and an insulation layer disposed between the first conductive layer and the second conductive layer. The first conductive layer includes a first expansion part penetrating through the second conductive layer, the second semiconductor layer and the active layer, and includes a second expansion part extending from the first expansion part and being disposed in the first semiconductor layer.
|Light emitting device and lighting system|
A light emitting device includes a conductive support member, a first conductive layer disposed on the conductive support member, a second conductive layer disposed on the first conductive layer, a light emitting structure including a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer, and an insulation layer disposed between the first conductive layer and the second conductive layer. The first conductive layer includes a first expansion part penetrating through the second conductive layer, the second semiconductor layer and the active layer, and includes a second expansion part extending from the first expansion part and being disposed in the first semiconductor layer.
|Graphene electronic devices and methods of manufacturing the same|
A graphene electronic device includes: a first conductive layer and a semiconductor layer on a first region of an intermediate layer; a second conductive layer on a second region of the intermediate layer; a graphene layer on the intermediate layer, the semiconductor layer, and the second conductive layer; and a first gate structure and a second gate structure on the graphene layer.. .
|Vertical bipolar transistor|
The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer..
|Method of fabricating a vertical mos transistor|
The disclosure relates to a method of fabricating a vertical mos transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole.. .
|Sample block holder|
A sample holder assembly includes a sample tray, a base plate, a stage mount, and a calibration standard mounted onto the stage mount. Three mating structures on the bottom of the base plate mate with corresponding structures on a stage mount that is attached to the sample stage of the sem.
|Flexible printed circuit|
A flexible printed circuit includes a first insulating substrate layer and a first electrically conductive layer located adjacent to a first side of the insulating substrate layer. The first conductive layer has a first portion that is substantially solid and a second portion having a multiplicity of voids in the first conductive layer in a pattern for providing a lower stiffness in the second portion relative to the first portion, thereby providing more flexibility in the second portion relative to the first portion..
|Method of fabricating flexible metal core printed circuit board|
A flexible metal core printed circuit board assembly comprises a flexible printed circuit board structure. The flexible printed circuit board structure includes a flexible substrate, a conductive layer on the flexible substrate and a space formed in the flexible printed circuit board structure.
|Tandem solar cell|
A solar cell is configured by: arranging two glass substrates, each of which is provided with a transparent conductive layer, so that the transparent conductive layers face each other; disposing a titanium dioxide layer on one glass substrate; disposing silicon dioxide particles on the other glass substrate; and filling the space between the two glass substrates with an electrolyte. The glass substrate on which light does not enter may alternatively be a metal plate.
|Patterned electrodes for tissue treatment systems|
Methods, apparatus, and systems for treating tissue located beneath a tissue surface with electromagnetic energy delivered from a treatment electrode. The treatment electrode may include a conductive layer and a plurality of openings extending through the conductive layer.
|Semiconductor device with self-aligned air gap and method for fabricating the same|
A method for fabricating a semiconductor device includes forming a plurality of semiconductor structures over a substrate, forming an interlayer dielectric layer over the semiconductor structures, etching the interlayer dielectric layer, and defining open parts between the semiconductor structures to expose a surface of the substrate, forming sacrificial spacers on sidewalls of the open parts, forming conductive layer patterns in the open parts, and causing the conductive layer patterns and the sacrificial spacers to reach each other, and defining air gaps on the sidewalls of the open parts.. .
|Semiconductor device with recess gate and method for fabricating the same|
A method for fabricating a semiconductor device includes forming a conductive layer over first and second regions of a semiconductor substrate, forming a trench extended in the first region of the semiconductor substrate through the conductive layer, forming a recessed gate electrode in the trench, doping the conductive layer and the recessed first gate electrode, and forming a second gate electrode by etching the doped conductive layer.. .
|Customized shield plate for a field effect transistor|
A customized shield plate field effect transistor (fet) includes a semiconductor layer, a gate dielectric, a gate electrode, and at least one customized shield plate. The shield plate includes a conductive layer overlying a portion of the gate electrode, one of the gate electrode sidewalls, and a portion of the substrate adjacent to the sidewall.
|Nanostructured electrolytic energy storage devices|
In one embodiment, a structure for an energy storage device may include a first nanostructured substrate having a conductive layer and a dielectric layer formed on the conductive layer. A second nanostructured substrate includes another conductive layer.
|Touch panel and touch display device|
The present invention provides a touch panel and a touch display device, the touch panel includes: a transparent substrate; a conductive layer disposed on the transparent substrate, where the conductive layer includes a plurality of first conductive patterns and a plurality of second conductive patterns intersecting with the plurality of first conductive patterns, and each of the second conductive patterns is separated into multiple segments by the plurality of first conductive patterns; a color resistance insulating layer disposed on the conductive layer, where the color resistance insulating layer includes a plurality of through-holes; and a metal bridging layer disposed on the color resistance insulating layer, where the multiple segments of the second conductive pattern are connected together by the metal bridging layer via the through-holes. With the technical solutions of the present invention, the color resistor is used as the insulating layer to replace the existing organic film layer, thus avoiding the undesirable risk brought about by the manufacturing process for coating the organic film, simplifying the manufacturing process and reducing the production costs..
|Mobile device and antenna structure therein|
A mobile device includes a ground element, a conductive bezel, a nonconductive layer, and a feeding element. The conductive bezel is substantially independent of the ground element.
|Resonant embedded antenna|
A planar antenna, such as included as a portion of a printed circuit board assembly, can include a first conductive layer comprising a feed conductor and a patch. The planar antenna can include a second conductive layer comprising a reference conductor, a first arm defined by a first arm length and a first arm width, and a second arm located parallel to the first arm and defined by a second arm length and a second arm width.
|Laminated waveguide diplexer with shielded signal-coupling structure|
A laminated waveguide diplexer includes an upper conductive layer having a first slot and a second slot; a first line crossing over the first slot; a first shielding conductor disposed over the first line; a plurality of first conductive pillars connecting the upper conductive layer and the first shielding conductor; a second line crossing over the second slot; a second shielding conductor disposed over the second line; and a plurality of second conductive pillars connecting the upper conductive layer and the second shielding conductor.. .
|Fabricating polysilicon mos devices and passive esd devices|
A semiconductor fabrication is described, wherein a mos device and a mems device is fabricated simultaneously in the beol process. A silicon layer is deposited and etched to form a silicon film for a mos device and a lower silicon sacrificial film for a mems device.
|Gate electrode(s) and contact structure(s), and methods of fabrication thereof|
A conductive structure(s), such as a gate electrode(s) or a contact structure(s), and methods of fabrication thereof are provided. The conductive structure(s) includes a first conductive layer of a first conductive material, and a second conductive layer of a second conductive material.
|Package on package (pop) bonding structures|
Various embodiments of mechanisms for forming through package vias (tpvs) with multiple conductive layers and/or recesses in a die package and a package on package (pop) device with bonding structures utilizing the tpvs are provided. One of the multiple conductive layers acts as a protective layer of the main conductive layer of the tpvs.
|Energy storage devices formed with porous silicon|
In one embodiment, an energy storage device (e.g., capacitor) may include a porous silicon layer formed within a substrate. The porous silicon layer includes pores with a mean pore diameter less than approximately 100 nanometers.
|Semiconductor device and method of manufacturing the same|
A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.. .
|Semiconductor device and microphone|
A package is formed by vertically stacking a cover and a substrate. A microphone chip is mounted at the top surface of a concave portion provided to the cover, and a circuit element is mounted on the upper surface of the substrate.
|Nanopore sensor device|
A pair of electrode plates can be provided by directional deposition and patterning of a conductive material on sidewalls of a template structure on a first dielectric layer. An electrode line straddling the center portion is formed.
|Nanopore sensor device|
A pair of electrode plates can be provided by directional deposition and patterning of a conductive material on sidewalls of a template structure on a first dielectric layer. An electrode line straddling the center portion is formed.
|Method for manufacturing semiconductor device using thin hard mask and structure manufactured by the same|
A method for manufacturing semiconductor device is disclosed. A substrate with a plurality of protruding strips formed vertically thereon is provided.
|Thin film transistor array substrate, method for manufacturing the same and electronic device|
According to embodiments of the present invention, there are provided a tft array substrate, a method for manufacturing the tft array substrate and an electronic device. The method for manufacturing the tft array substrate comprises: a first patterning process, in which a pattern of a pixel electrode formed by a first transparent conductive layer and patterns of a drain electrode and a source electrode that are separated from each other and a data line, which are formed by a first metal layer, are formed on a transparent substrate; a second patterning process, in which a pattern of a gate insulating layer and a pattern of an active layer formed by a transparent oxide layer are formed on the transparent substrate subjected to the first patterning process; and a third patterning process, in which a pattern of a common electrode formed by a second transparent conductive layer and patterns of a gate electrode and a gate line which are formed by a second metal layer are formed on the transparent substrate subjected to the second patterning process..
|Organic light emitting display device and method of manufacturing the same|
An organic light emitting display device with enhanced luminous efficiency and color viewing angle and a method of manufacturing the same are disclosed. The method includes forming a first electrode of each of red, green, blue and white sub-pixels on a substrate, forming a white organic common layer on the first electrodes, and forming a second electrode on the white organic common layer, wherein the first electrodes each includes multiple transparent conductive layers and is formed such that a thickness of the first electrode of each of two sub-pixels among the red, green, blue and white sub-pixels is greater than a thickness of the first electrode of each of the other two sub-pixels, and at least two layers excluding the lowermost layer among the multiple transparent conductive layers of each first electrode are formed to cover opposite sides of the lowermost layer..
A touch panel has a substrate on which a first conductive layer, an insulating layer, a second conductive layer and a protective layer are formed in order. The second conductive layer and the first conductive layer form a touch-sensing area.
A shielded cable includes a twisted cable including a plurality of electric wires each including a conductor covered with an insulation therearound, and an electrically conductive wire twisted together with the plurality of electric wires, and a strip-like member including a conductive layer and an insulating layer. The strip-like member is wound around the twisted cable in the same direction as a twist direction of the twisted cable and at substantially the same winding pitch as a twist pitch of the twisted cable such that the conductive layer is continuously contacted with and along the lead wire..
|Solar cell and production method for solar cell|
A solar cell, comprising: a photoelectric conversion unit; a transparent conductive layer comprising a transparent conductive oxide, and formed upon the main surface of the photoelectric conversion unit; and a finger section and a bus bar section that are formed upon the transparent conductive layer. The transparent conductive layer has particles on a contact surface where the finger section and the bus bar section are formed.
|Back contact having selenium blocking layer for photovoltaic devices such as copper-indium-diselenide solar cells|
A photovoltaic device (e.g., solar cell) includes: a front substrate (e.g., glass substrate); a semiconductor absorber film; a back contact including a first conductive layer of or including copper (cu) and a second conductive layer of or including molybdenum (mo); and a rear substrate (e.g., glass substrate). A selenium blocking layer is provided between at least the cu inclusive layer and the mo inclusive layer..
|Substrate for optical device|
The present invention relates to a substrate for an optical device, which is configured to connect an optical element substrate and an electrode substrate in a fitting manner, and simultaneously, to form one or more bridge pads which are insulated from the optical element substrate by a horizontal insulating layer, on the optical element substrate. The substrate for an optical device according to a first aspect of the present invention comprises: an optical element substrate which is made of a metal plate and contains a plurality of optical elements therein; a pair of electrode substrates which are made of an insulating material to form a conductive layer on at least a portion of the upper surface thereof, are connected to both side surfaces of the optical element substrate, respectively, and are wire-bonded to the electrodes of the optical elements; and a fitting means which is formed on the side surfaces of the electrode substrate and the optical element substrate to fit the optical element substrate and the electrode substrate.
|Switchable window having low emissivity (low-e) coating as conductive layer and/or method of making the same|
A switchable window includes: first and second substrates (e.g., glass substrates); a liquid crystal inclusive layer (e.g., pdlc layer) disposed between at least the first and the second substrates; and a low-e coating provided between at least the liquid crystal inclusive layer and the first substrate. Voltage is applied to the liquid crystal inclusive layer via the low-e coating and a substantially transparent conductive coating which are on opposite sides of the liquid crystal inclusive layer.
|Liquid ejecting head, liquid ejecting apparatus, piezoelectric element, and method for manufacturing piezoelectric element|
A flow channel substrate has pressure chambers, and the pressure chambers communicate with nozzle openings for ejecting liquid. Each of piezoelectric elements on the flow channel substrate has a piezoelectric layer, a pair of electrodes, and a wiring layer coupled to the electrodes.
|Touch panel and a manufacturing method thereof|
The present disclosure provides a method for manufacturing a touch panel, wherein the method comprises: forming a touch sensing layer on a visible region and a non-visible region of a cover substrate, wherein the non-visible region is located at periphery of the visible region forming a first opaque insulating layer on the touch sensing layer in the non-visible region; forming a wiring layer on the first opaque insulating layer: and forming a conductive layer to electrically connect the wiring layer and the touch sensing layer. Moreover, the present disclosure also provides a touch panel.
|High-frequency signal line and electronic device including the same|
A high-frequency signal line includes a dielectric element body including regions and a plurality of flexible dielectric sheets. A signal conductive layer is provided in or on the dielectric element body.
|Variable capacitive electrostatic machinery with macro pressure-gap product|
An operational electrostatic machine having a gap distance and a gap medium pressure product above 100 μm*atm, outside enclosure housing dimensions having a height, a length and a width, that are each greater than one hundred times (100×) the product of the gap distance and the gap medium pressure, one or more electrically isolated conductive layers that, during operation, facilitate storage of electric charge, and an electric field created by the stored charge of a particular polarity passes through surrounding insulative layers, making a path to couple to an electric field of a stored charge of opposite polarity on a contiguous plate, and where, during operation, unaligned conductive layers that are repetitively charged and discharged using appropriate control techniques facilitate production of useful forces.. .
|Semiconductor device and method of simultaneous molding and thermalcompression bonding|
A semiconductor device has a semiconductor die disposed over a substrate. The semiconductor die and substrate are placed in a chase mold.
|Segmented conductive top layer for radio frequency isolation|
A radio frequency (rf) module comprises a conductive top layer configured to improve rf interference-shielding functionality with respect to one or more rf devices disposed on the module. The conductive top layer may be segmented as to form one or more segments of the top layer that are at least partially electrically isolated from surrounding segments or devices.
|Semiconductor device integrating passive elements|
The present invention provides a semiconductor device integrating passive elements, which applies to analog circuits, wherein capacitors, resistors and inductors are fabricated by a tvs technology. The semiconductor device comprises a substrate; at least one passive element arranged in the substrate; and at least one semiconductor integrated circuit formed in the substrate.
|Double diffused drain metal-oxide-semiconductor devices with floating poly thereon and methods of manufacturing the same|
A metal-oxide-semiconductor (mos) device is disclosed. The mos device includes a substrate of a first impurity type, a diffused region of a second impurity type in the substrate, a patterned first dielectric layer including a first dielectric portion over the diffused region, a patterned first conductive layer on the patterned first dielectric layer, the patterned first conductive layer including a first conductive portion on the first dielectric portion, a patterned second dielectric layer including a second dielectric portion that extends on a first portion of an upper surface of the first conductive portion and along a sidewall of the first conductive portion to the substrate; and a patterned second conductive layer on the patterned second dielectric layer, the patterned second conductive layer including a second conductive portion on the second dielectric portion..
|Method for manufacturing semiconductor device|
A method for manufacturing semiconductor device is disclosed. A substrate with a conductive layer is provided, and a dummy layer is formed on the conductive layer.
|Non-volatile memory structure and manufacturing method thereof|
A method for manufacturing a non-volatile memory structure includes providing a substrate having a gate structure, performing a first oxidation process to form a first sio layer at least covering a bottom corner of the conductive layer, performing a first etching process to remove the first sio layer and a portion of the dielectric layer to form a cavity, performing a second oxidation process to form a second sio layer covering sidewalls of the cavity and a third sio layer covering a surface of the substrate, forming a first sin layer filling in the cavity and covering the gate structure on the substrate, and removing a portion of the first sin layer to form a sin structure including a foot portion filling in the cavity and an erection portion upwardly extended from the foot portion, and the erection portion covering sidewalls of the gate structure.. .
|Thin film transistor array substrate|
A thin film transistor array substrate includes a substrate, a plurality of pixel elements arranged on the substrate, each of the pixel elements including a thin film transistor and a pixel electrode electrically connected with the thin film transistor, a light shielding electrode disposed between the substrate and the thin film transistor to shield a channel of the thin film transistor, and a storage capacitor including a first electrode and a second electrode disposed opposite to each other. The light shielding electrode includes a transparent electrically-conductive layer and a non-transparent electrically-conductive layer stacked on top of each other.
|Electronically induced ceramic fusible metal system|
An electrically induced fusing system includes a module having walls and a base to define a module body. The module body includes first and second conductive layers stacked next to one another.