Conductive Layer

Conductive Layer-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).

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NEW Transparency including conductive mesh
May 25, 2017 - N°20170150659

A transparency includes a transparent substrate and a plurality of electrically conductive lines on the transparent substrate, at least one of the electrically conductive lines intersecting at least one other electrically conductive line, and at least one of the electrically conductive lines having a width of no more than 50 μm to reduce distraction resulting from optical diffraction of ...
NEW Heater, in particular high-temperature heater, and method for the production thereof
May 25, 2017 - N°20170150552

A heater, in particular a high-temperature heater, for example for domestic heating appliances, in which a layer that produces heat when a current flows through is provided on a carrier material as a heating element, wherein a first electrically conductive layer which is formed from a free-flowing, non-electrically conductive base material and carbon nano tubes dispersed therein is applied to ...
NEW Devices and methods related to packaging of radio-frequency devices on ceramic substrates
May 25, 2017 - N°20170149466

Devices and methods related to packaging of radio-frequency (rf) devices on ceramic substrates. In some embodiments, a packaged electronic device can include a ceramic substrate configured to receive one or more components. The ceramic substrate can include a conductive layer in electrical contact with a ground plane. The packaged electronic device can further include a die having an integrated circuit ...
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NEW Multi-layered film and method of manufacturing the same
May 25, 2017 - N°20170148975

A multi-layered film includes an electroconductive layer made of platinum (pt), a seed layer including lanthanum (la), nickel (ni), and oxygen (o), and a dielectric layer being preferentially oriented in a c-axis direction, which are at least sequentially disposed on a main surface of a substrate made of silicon.
NEW Opto-electronic element and method for manufacturing the same
May 25, 2017 - N°20170148953

An opto-electronic element according to an exemplary embodiment of the present disclosure includes a transparent conductive layer including a first material made of a metal and a second material made of a metal halide.
NEW Thin-film-transistor, thin-film-transistor array substrate, fabricating methods thereof, and display panel
May 25, 2017 - N°20170148821

In accordance with some embodiments of the disclosed subject matter, a tft, a related tft array substrate, fabricating methods thereof, a display panel and a display device containing the same are provided. A method for fabricating a tft is provided, the method comprising: forming an initial conductive layer on a base substrate; performing an oxidization process to partially oxidize the ...
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NEW Three-dimensional nand device containing support pedestal structures for a buried source line and method of ...
May 25, 2017 - N°20170148810

A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. An alternating sequence of support pedestal structures and conductive rail structures extending along a same horizontal direction are provided between the substrate and the alternating stack. Each memory stack structure straddles a vertical interface between ...
NEW Split memory cells with unsplit select gates in a three-dimensional memory device
May 25, 2017 - N°20170148809

Split memory cells can be provided within an alternating stack of insulating layers and word lines. At least one lower-select-gate-level electrically conductive layers and/or at least one upper-select-level electrically conductive layers without a split memory cell configuration can be provided by limiting the levels of separator insulator structures within the levels of the word lines. At least one etch ...
NEW Within array replacement openings for a three-dimensional memory device
May 25, 2017 - N°20170148808

An alternating stack of sacrificial material layers and insulating layers is formed over a substrate. Replacement of sacrificial material layers with electrically conductive layers can be performed employing a subset of openings. A predominant subset of the openings is employed to form memory stack structures therein. A minor subset of the openings is employed as access openings for introducing an ...
NEW Semiconductor memory device
May 25, 2017 - N°20170148806

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, and a columnar part. The stacked body is provided on the substrate. The stacked body includes a plurality of first insulating films and a plurality of electrode films alternately stacked one layer by one layer. The columnar part includes a semiconductor pillar provided in the stacked ...
NEW Method for forming flash memory structure
May 25, 2017 - N°20170148803

Methods for forming semiconductor structures are provided. The method for forming the semiconductor structure includes forming a word line cell over a substrate and forming a dielectric layer over the word line cell. The method further includes forming a conductive layer over the dielectric layer and polishing the conductive layer until the dielectric layer is exposed. The method further includes ...
NEW Three dimensional nand device containing dielectric pillars for a buried source line and method of ...
May 25, 2017 - N°20170148800

A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures, each memory stack structure extending through the alternating stack and including a memory film and a semiconductor channel laterally surrounded by the memory film, and an array of dielectric pillars located between the alternating stack ...
NEW Semiconductor package
May 25, 2017 - N°20170148766

A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. ...
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NEW Semiconductor device and method of manufacturing the same
May 25, 2017 - N°20170148760

A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and one or more conductive layers and a solder resist layer that are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous ...
NEW Chip package and manufacturing method thereof
May 25, 2017 - N°20170148752

A chip package includes a substrate, an isolation layer, a redistribution layer, a passivation layer, a first conductive layer, a second conductive layer, and a conductive structure. The isolation layer is located on the substrate. The redistribution layer is located on the isolation layer. The passivation layer is located on the isolation layer and the redistribution layer. The passivation layer ...
NEW Reduced-warpage laminate structure
May 25, 2017 - N°20170148749

A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively patterned high-modulus dielectric material that balances a differential stress between the conductive layer and the dielectric layer to mechanically stiffen the laminate structure and reduce warpage.
NEW Semiconductor device and method of forming openings through insulating layer over encapsulant for enhanced adhesion ...
May 25, 2017 - N°20170148721

A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over a portion of the encapsulant within an interconnect site outside a footprint of the semiconductor die. An opening is formed through the first insulating layer within the interconnect ...
NEW Device manufacture and packaging method thereof
May 25, 2017 - N°20170148666

Some embodiments of the present disclosure provide a semiconductive device. The semiconductive device includes a first conductive layer and a second conductive layer above the first conductive layer. The second conductive layer includes a first portion and a second portion protruding from the first portion. A via structure is under the second conductive layer and on top of the first ...
NEW Method of manufacturing a semiconductor device having a vertical edge termination structure
May 25, 2017 - N°20170148663

A method of manufacturing a semiconductor device includes forming a frame trench extending from a first surface into a base substrate, forming, in the frame trench, an edge termination structure comprising a glass structure, forming a conductive layer on the semiconductor substrate and the edge termination structure, and removing a portion of the conductive layer above the edge termination structure. ...
NEW Touch screen and a system of controlling the same
May 25, 2017 - N°20170147102

A touch screen includes a display, a touch sensor disposed above or within the display, and a conductive layer disposed under the display for detecting pressure.
NEW Fixing device
May 25, 2017 - N°20170146936

A fixing device for fixing an image on a recording material includes a cylindrical rotatable member including an electroconductive layer; a coil, provided inside the rotatable member, for forming an alternating magnetic field for causing the electroconductive layer to generate heat through electromagnetic induction heating, wherein the coil includes a helically-shaped portion having a helical axis along a generatrix direction ...