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Conductive Layer patents

      

This page is updated frequently with new Conductive Layer-related patent applications.




 Semi-finished product for the production of connection systems for electronic  components and method patent thumbnailSemi-finished product for the production of connection systems for electronic components and method
A semi-finished product for the production of connection systems for electronic components comprises two groups (a, b) of alternately applied conductive layers and insulating layers, wherein outer layers (2, 2′) of the two groups (a, b) are facing each other to form a separation area for the groups (a, b) to be separated from each other to yield connection systems for electronic components and the separation area is overlapped and sealed on all sides thereof at least by the two insulating layers (4, 4′) following the separation area. The method for the production of connection systems for electronic components is characterized by the following steps: a) orienting two groups (a, b) of alternately applied conductive layers and insulating layers (4, 4′) to face each other with outer layers to form a separation area for the groups (a, b) to be separated from each other and safeguarding that the separation area is overlapped and sealed on all sides thereof at least by the two insulating layers (4, 4′) following the separation area, b) processing the groups (a, b) of alternately applied conductive layers and insulating layer, c) cutting through the separation area along the edges thereof..
At&s (china) Co., Ltd.


 Fabrication of flexible electronic devices patent thumbnailFabrication of flexible electronic devices
Disclosed are methods for fabrication of flexible circuits and electronic devices in cost effective manner that can include integration of submicron structures directly onto target substrates compatible with industrial microfabrication techniques. In one aspect, a method to fabricate an electronic device, includes depositing an electrically conductive layer on a processing substrate including a weakly-adhesive interface layer on a support substrate; depositing an insulating layer on the conductive layer to attach to the conductive layer; forming a circuit on the processing substrate by etching selected portions of the conductive layer based on a circuit design; and producing a flexible electronic device by attaching a flexible substrate to the formed circuit on the processing substrate and detaching the circuit and the flexible substrate from the interface layer, in which the flexible electronic device includes the circuit attached to the flexible substrate..
The Regents Of The University Of California


 Heat spreader in multilayer build ups patent thumbnailHeat spreader in multilayer build ups
Connection system for electronic components, the connection system comprising at least one electrically insulating layer and at least one electrically conductive layer, wherein the connection system further comprises a heat distributing layer arranged within the at least one electrically insulating layer wherein the at least one heat distributing layer is made of thermally conductive, and electrically insulating, matrix-free material.. .
At & S Austria Technologie & Systemtechnik Aktiengesellschaft


 Simplified electronic module for a smartcard with a dual communication interface patent thumbnailSimplified electronic module for a smartcard with a dual communication interface
An electronic module for a smartcard has a dual, contact and contactless, communication interface. The module includes an electrically insulating substrate on which are produced electrical contact pads enabling operation via contact with corresponding contacts of a smartcard reader, and contact pads for connection to corresponding pads of an antenna located on the body of the smartcard and enabling a contactless operation with a remote smartcard reader.
Smart Packaging Solutions


 Fuel cell housing patent thumbnailFuel cell housing
A fuel cell housing has at least one portion that has at least three layers, including a first, outward-facing layer designed as an electrically conductive layer, a second layer for absorbing mechanical forces and as a penetration shield, and a third layer designed as a high voltage-insulating, hydrogen-insulating layer.. .
Bayerische Motoren Werke Aktiengesellschaft


 Multivalent metal salts for lithium ion cells having oxygen containing electrode active materials patent thumbnailMultivalent metal salts for lithium ion cells having oxygen containing electrode active materials
A material and method for a surface-treated electrode active material for use in a lithium ion battery is provided. The surface-treated electrode active material includes an ionically conductive layer comprising a multivalent metal present as a direct conformal layer on at least a portion of the outer surface of the electrode active material.
A123 Systems, Llc


 Methods for fabricating an organic electro-luminescence device and flexible electric device patent thumbnailMethods for fabricating an organic electro-luminescence device and flexible electric device
A method for fabricating an organic electro-luminescence device, comprising: forming a first conductive layer comprising a first electrode and a contact pattern on a substrate; forming a first mask on the first conductive layer, the first mask comprising an opening for exposing a portion of the first electrode and a portion of the contact pattern; forming a patterned organic functional layer by shielding of a second mask, the patterned organic functional layer covering the first mask and the first electrode exposed by the first mask, and the second mask being disposed over the first mask to shield the portion of the contact pattern exposed by the opening; forming a second conductive layer and patterning the second conductive layer by removing the first mask and a portion of the second conductive layer on the first mask to form a second electrode electrically connected to the contact pattern.. .
Industrial Technology Research Institute


 Applying compliant compliant interfacial layers in thermoelectric devices patent thumbnailApplying compliant compliant interfacial layers in thermoelectric devices
A thermoelectric power generation technique is disclosed using one or more mechanically compliant and thermally and electrically conductive layers at the thermoelectric material interfaces to accommodate high temperature differentials and stresses induced thereby. The compliant material may be metal foam or metal graphite composite (e.g.
California Institute Of Technology


 Light-emitting device patent thumbnailLight-emitting device
A light-emitting device includes a substrate that is capable of transmitting light, a conductive layer that includes a first conductive portion provided on the substrate and a second conductive portion which is provided on the substrate so as to be adjacent to the first conductive portion, the second conductive portion is thinner than the first conductive portion. A light emitting layer is provided on the first conductive portion.
Kabushiki Kaisha Toshiba


 Semiconductor device patent thumbnailSemiconductor device
A semiconductor device according to an embodiment includes a first metal layer, a second metal layer, an n-type first sic region provided between the first metal layer and the second metal layer and having an n-type impurity concentration of 1×1018 cm−3 or less, and a conductive layer provided between the first sic region and the first metal layer and containing titanium (ti), oxygen (o), and at least one element selected from the group consisting of vanadium (v), niobium (nb), and tantalum (ta).. .
Kabushiki Kaisha Toshiba


High-voltage metal-oxide-semiconductor transistor device and manufacturing method thereof

The present invention provides a high-voltage metal-oxide-semiconductor transistor device and a manufacturing method thereof. First, a semiconductor substrate is provided and a dielectric layer and a conductive layer sequentially stacked on the semiconductor substrate.
United Microelectronics Corp.

Semiconductor device

A semiconductor device of an embodiment includes an n-type sic region, a metal layer, and a conductive layer provided between the n-type sic region and the metal layer, the conductive layer including titanium (ti), oxygen (o), at least one first element from zirconium (zr) and hafnium (hf), and at least one second element from vanadium (v), niobium (nb), and tantalum (ta).. .
Kabushiki Kaisha Toshiba

Semiconductor device

This semiconductor device comprises a plurality of first conductive layers arranged above a substrate in a first direction intersecting an upper surface of the substrate. The conductive layers includes a portion in which positions of ends of the first conductive layers made different from each other in a second direction intersecting the first direction.
Kabushiki Kaisha Toshiba

Augmented capacitor structure for high quality (q)-factor radio frequency (rf) applications

An augmented capacitor structure includes a substrate and a first capacitor plate of a first conductive layer on the substrate. The augmented capacitor structure also includes an insulator layer on a surface of the first capacitor plate facing away from the substrate and a second capacitor plate.
Qualcomm Incorporated

Display device

A display device includes a display region arranged with a plurality of pixels in a matrix shape, a pixel electrode including at least a first conductive layer and a second conductive layer, an end part of the second conductive layer existing further to the exterior than an end part of the first conductive layer, a protective layer covering a region spreading further to the exterior than an end part of the first conductive layer of the second conductive layer so as to expose a part of a surface of the second conductive layer of a region stacked with the first conductive layer and the second conductive layer, and a bank layer covering an end part of the pixel electrode and an end part of the protective layer so as to expose a part of the second conductive layer.. .
Japan Display Inc.

Nonvolatile storage device, semiconductor element, and capacitor

A nonvolatile storage device of an embodiment includes a first wiring layer extending in a first direction, a second wiring layer extending in a second direction intersecting with the first direction, a conductive layer between the first wiring layer and the second wiring layer at an intersection of the first wiring layer and the second wiring layer, and a resistance change region including at least one of an oxide, a nitride, and an oxynitride in the first wiring layer. The resistance change region exists in the first wiring layer including an interface between the first wiring layer and the conductive layer..
Kabushiki Kaisha Toshiba

Magnetic memory and manufacturing same

According to one embodiment, a magnetic memory includes a structure body including a first magnetic layer and a conductive layer, a second magnetic layer, a first electrode, a second electrode, a third magnetic layer, an intermediate layer, a third electrode, a fourth magnetic layer, and a circuit element. The first magnetic layer is disposed between the second magnetic layer and the conductive layer.
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing same

According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on the insulating layer; a stacked body provided on the conductive layer and including a plurality of electrode layers and a plurality of insulating layers respectively provided among the plurality of electrode layers; a columnar section piercing through the stacked body to reach the conductive layer and extending in a first direction in which the stacked body is stacked; and a source layer. The columnar section includes a channel body and a charge storage film provided between the channel body and the respective electrode layers.
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing method thereof

A semiconductor memory device according to an embodiment includes a laminated body. The laminated body is disposed above a semiconductor substrate.
Kabushiki Kaisha Toshiba

Semiconductor memory device

According to one embodiment, a semiconductor memory device comprises a first semiconductor region of n-type conductivity, a second semiconductor region of p-type conductivity, a third semiconductor region of n-type conductivity, a stacked body, a semiconductor pillar, a first insulating layer, a charge storage layer, a second insulating layer, a first conductive portion, and a second conductive portion. The semiconductor pillar extends in the stacked body in a direction in which the conductive layers and the insulating layers are stacked.
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing same

According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of insulating layers and including a first insulating layer and a plurality of conductive layers including a first conductive layer; a first semiconductor film extending in a stacking direction of the stacked body; a second semiconductor film, the second semiconductor film having a maximum thickness thicker than a maximum thickness of the first semiconductor film in a first direction crossing the stacking direction; and a first insulating film. The second semiconductor film has an upper face, and a height of the upper face is lower than a height of the first conductive layer.
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing the same

A semiconductor memory device according to an embodiment includes a first semiconductor layer containing an acceptor and a memory cell array including an interlayer insulating layer and a conductive layer arranged in a first direction above the first semiconductor layer and a memory columnar body extending in the first direction and having a lower end positioned lower than a position of a top surface of the first semiconductor layer, the memory columnar body containing a second semiconductor layer in a columnar shape having a side face opposite to a side face of the conductive layer, wherein a first portion of the first semiconductor layer in contact with the side face of the memory columnar body contains a donor in a higher concentration than a second portion different from the first portion of the first semiconductor substrate.. .
Kabushiki Kaisha Toshiba

Semiconductor memory device and production method thereof

A semiconductor memory device according to an embodiment includes a memory cell array which has: a first conductive layer which is arranged in a first direction on a first semiconductor layer; a second conductive layer which is arranged in the first direction above the first conductive layer; a columnar second semiconductor layer which extends in the first direction; and a contact unit which electrically connects the first semiconductor layer and the second conductive layer. The contact unit has a first film which contains silicide as a first metal, and is in contact with the first semiconductor layer; and a second film which contains the first metal, is in contact with the first film, and is in contact with the first semiconductor layer with the first film interposed therebetween..
Kabushiki Kaisha Toshiba

Semiconductor memory device

A semiconductor memory device according to an embodiment includes: an insulating layer; a conductive layer stacked above the insulating layer in a first direction, the conductive layer having a second direction as a longitudinal direction and a third direction as a short direction; and a channel semiconductor layer extending in the first direction, and the conductive layer including a recessed portion narrowed in the third direction.. .
Kabushiki Kaisha Toshiba

Structure and operation for improved gate capacity for 3d nor flash memory

Embodiments of the present invention provide improved three-dimensional memory cells, arrays, devices, and/or the like and associated methods. In one embodiment, a three-dimensional memory cell is provided.
Macronix International Co., Ltd.

Semiconductor memory device and manufacturing the same

An embodiment includes: a semiconductor substrate, a memory cell array region including a plurality of conductive layers connected to memory cells arranged in a stacking direction on the semiconductor substrate; a peripheral region including a transistor on the substrate ; a plurality of first layers and second layers stacked alternately in the stacking direction, above the transistor; and a plurality of first contacts penetrating the plurality of first and second layers and connected to the transistor. The plurality of first layers and second layers are stacked alternately in the stacking direction, above the transistor disposed in the peripheral region.
Kabushiki Kaisha Toshiba

Semiconductor device

According to an embodiment, a semiconductor device, includes: a first region of an n-type conductive layer; a second region of a p-type conductive layer on the first region; a first tfet having an n-type drain region formed in the second region; a second tfet provided adjacent to the first tfet and of a tfet having an n-type drain region formed in the second region; and an insulating film formed between the drain region of the first tfet and the drain region of the second tfet, and reaching the first region.. .
Kabushiki Kaisha Toshiba

Backside coupled symmetric varactor structure

A symmetric varactor structure may include a first varactor component. The first varactor component may include a gate operating as a second plate, a gate oxide layer operating as a dielectric layer and a body operating as a first plate of an area modulating capacitor.
Qualcomm Incorporated

Semiconductor memory device and manufacturing method thereof

According to an embodiment, a semiconductor memory device includes a plurality of first conductive layers disposed above a substrate in a laminating direction. A stepped wiring area includes a second conductive layer electrically connected to the first conductive layer.
Kabushiki Kaisha Toshiba

Semiconductor substrate, semiconductor module and manufacturing the same

A semiconductor substrate includes: 1) a first dielectric structure having a first surface and a second surface opposite the first surface; 2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; 3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and 4) a second patterned conductive layer, disposed on the second surface of the first dielectric structure and including at least one conductive trace. The first dielectric structure defines at least one opening to expose a portion of the second patterned conductive layer..
Advanced Semiconductor Engineering, Inc.

Wireless power receiver and manufacturing the same

A wireless power receiver can include a magnetic substrate and a coil configured to wirelessly receive power. The coil can be formed as a conductive layer on the magnetic substrate.
Lg Innotek Co., Ltd.

Coil, inductor device and manufacturing the coil

A coil comprises a plurality of conductive layers, wherein a first conductive layer and a second conductive layer of the plurality of conductive layers each comprises a winding, and the first conductive layer is adjacent to the second conductive layer; wherein a first winding on the first conductive layer is electrically connected to a second winding on the second conductive layer, a first end of the first winding is connected to a first terminal electrode, and a second end on the second winding is connected to a second terminal electrode; wherein geometric central points of the first winding and the second winding are not spatially aligned.. .
Xytech Electronic Technology (shanghai) Co., Ltd.

Electrical cables with strength elements

An electrical cable may include: at least two first members extending along a length of the electrical cable, each of the first members including a conducting element and an insulating layer radially external to the conducting element; at least two second members extending along the length of the electrical cable, each of the second members including a strength element and a conductive layer radially external to the strength element; and/or the first and second members being stranded around and in contact with a cradle extending along the length of the electrical cable. The cradle may be made of polymeric material having a tensile modulus greater than or equal to 1 gpa and a vicat softening temperature greater than or equal to 125° c..
Prysmian S.p.a.

Capacitive force sensing touch panel

A capacitive force sensing touch panel is disclosed. The capacitive force sensing touch panel includes pixels.
Raydium Semiconductor Corporation

Electro-optical device, projection-type display device, electronic device, and manufacturing the electro-optical device

An electro-optical device including a pixel electrode provided over one side of a substrate, a conductive layer provided between the substrate and the pixel electrode, and a relay electrode provided between the substrate and the conductive layer. The conductive layer includes a first conduction section protruding toward the pixel electrode and a second conduction section protruding toward the relay electrode.
Seiko Epson Corporation

Display device and manufacturing the same

A display device includes a first substrate, a second substrate, and a liquid crystal layer. The first substrate includes a common electrode, a pixel electrode, a first conductive layer spaced apart from the common electrode, and a second conductive layer disposed on the first conductive layer.
Samsung Display Co., Ltd

Optical composite layer structure with a built-in touch sensitive polymer dispersed liquid crystal structure

The invention provides an optical composite layer structure with a built-in touch sensitive polymer dispersed liquid crystal (pdlc) structure. The optical composite layer structure comprises an upper transparent substrate, a lower transparent substrate, an upper transparent conductive layer, a lower transparent conductive layer and a pdlc layer.
Nanobit Tech. Co., Ltd.

Magneto-impedance sensing device method and manufacturing method thereof

An electromagnetic impedance sensing device includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a magneto-conductive wire and an encapsulation layer. The substrate has a surface and a trench extending into thereof.
Prolific Technology Inc.

Magneto-impedance sensing device and manufacturing method thereof

An electromagnetic impedance sensing device includes a first substrate, a first patterned conductive layer, a second substrate, a second patterned conductive layer, a magneto-conductive wire and an encapsulation layer. The first substrate has a first surface, and the first patterned conductive layer is formed on the first surface.
Prolific Technology Inc.

Reliability testing method

Disclosed is a chip reliability testing method that includes mounting a test chip on a test board whereby each test circuit of the test chip is connected to a different pair of input and output terminals. The reliability test can include applying a test voltage to a first (input) bump and measuring an output voltage on a second (output) bump connected to the same test circuit.
Taiwan Semiconductor Manufacturing Company, Ltd.

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes first-third conductive layers, a semiconductor layer, a resistance change layer and a metal-containing layer. The second conductive layer is separated from the first conductive layer in a first direction.
Kabushiki Kaisha Toshiba

Light emitting device

A light-emitting device comprises a first semiconductor layer; an active layer on the first semiconductor layer; a second semiconductor layer on the active layer; and an electrode structure on the second semiconductor layer, wherein the electrode structure comprises an adhesion layer on the second semiconductor layer, a conductive layer on the adhesion layer, and a bonding layer on the conductive layer, and wherein the electrode structure comprises a center region and an edge region, a thickness of each layer of the edge region of the electrode structure is smaller than that of the center region.. .
Epistar Corporation

Photovoltaic cell structure and manufacturing a photovoltaic cell

The invention relates to the photo-voltalic cell structure comprising semiconductor type-p substrate with bottom electric contact upon which the active zno film is present, with the transparent conductive layer upon it, preferably zno:al film, with an electric contact, characterized in that the active zno layer consists of zno nanostructures film at least 50 nm thick, deposited on nucleating layer and covered with zno film at least 1 nm thick, and the method to produce the photovoltaic structure.. .
Instytut Fizyki Pan

Nonvolatile memory device and manufacturing the same

A nonvolatile memory device includes a pipe gate electrode layer formed over a substrate; a plurality of conductive layers stacked over the pipe gate electrode layer; source lines formed over an uppermost one of the conductive layers; first slits passing through the pipe gate electrode layer at positions overlapping with the source lines, and dividing the pipe gate electrode layer into a plurality of pipe gate electrodes, and second slits passing through the conductive layers at positions different from the first slits, and dividing the conductive layers into a plurality of memory blocks.. .
Sk Hynix Inc.

Display device

A display device includes a display panel including a display area for displaying an image, and a non-display area outside of the display area and including a pad area, a pad in the pad area, and including a plurality of pad lines extending from wire lines drawn from the display area toward the non-display area, a driver including a plurality of terminal lines respectively electrically connected to the pad lines, the driver being configured to transmit a signal to, and to receive a signal from, an external board, and a conductive layer between the pad and the driver for electrically connecting the pad and the driver, wherein each of the pad lines crosses and contacts at least two points of a corresponding one of the terminal lines.. .
Samsung Display Co., Ltd.

Semiconductor memory device and manufacturing the same

According to one embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer separated from the first conductive layer in a first direction, a resistance change layer provided between the first and second conductive layers, a third conductive layer, a fourth conductive layer and a first intermediate layer. The third conductive layer is arranged with the first conductive layer in a second direction crossing the first direction.
Kabushiki Kaisha Toshiba

Magnetoresistive memory device and manufacturing the same

According to one embodiment, a magnetoresistive memory device includes a magnetoresistive element having a stacked layer structure includes a first magnetic layer, a second magnetic layer, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer, an insulating layer provided on the first magnetic layer, a conductive layer provided on a surface of the insulating laver, opposite to the first magnetic layer, and a sidewall conductive film configure to connect the conductive layer and the first magnetic layer.. .
Kabushiki Kaisha Toshiba

Semiconductor memory device and manufacturing the same

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a pillar, and memory film. The substrate has a major surface.
Kabushiki Kaisha Toshiba

Microelectronic assembly with redistribution structure formed on carrier

A microelectronic assembly can be made by forming a redistribution structure supported on a carrier, the structure including two or more layers of deposited dielectric material and two or more electrically conductive layers and including conductive features such as pads and traces electrically interconnected by vias. Electrical connectors may project above a second surface of the structure opposite an interconnection surface of the redistribution structure adjacent to the carrier.
Invensas Corporation

Semiconductor package

According to one embodiment, a semiconductor package includes a first substrate, first conductive layers, first semiconductor chips, a second conductive layer, a first terminal, and a second terminal. The first substrate has a first surface.
Kabushiki Kaisha Toshiba

Memory structure

A memory structure is provided. The memory structure comprises m array regions and n contact regions.
Macronix International Co., Ltd.

Electrostatic substrate holder with non-planar surface and etching

An apparatus and method of etching. The apparatus including a support substrate having a top surface; a stack of a multiplicity of layers formed on the top surface of the support substrate from a lowermost layer on the top surface of the support substrate to a topmost layer that is furthest from the support substrate; and wherein an entirety of the top surface of the topmost layer is not planar and at least one of the multiplicity of layers that is not the topmost layer is an electrically conductive layer..
Globalfoundries Inc.

Non-volatile memory device

A nonvolatile memory device includes a conductive layer, a semiconductor layer extending in a first direction on the conductive layer, a first insulating layer provided between the conductive layer and the semiconductor layer, a word line extending in a second direction on the semiconductor layer, the second direction intersecting the first direction, a charge storage layer provided between the semiconductor layer and the word line, and a circuit electrically connected to the conductive layer. The circuit applies an electric potential to the conductive layer when programming data, the electric potential of the conductive layer having the same polarity as an electric potential of the word line..
Kabushiki Kaisha Toshiba



Conductive Layer topics:
  • Conductive Layer
  • Ultrasound
  • Radiograph
  • Attenuation
  • Electronic Device
  • Photoelectric Conversion
  • Electric Conversion


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