|| List of recent Conductive Layer-related patents
| Treatment device using nanotechnology|
The current invention discloses a treatment device having a heat source, a power source and a heat applicator. The power source includes at least one nanotech battery, ensuring superior properties such as prolonged electricity production and prompt recharging.
| Heating device using exothermic chemical reaction|
The current invention discloses a treatment device having a heat source, a power source, a heat applicator and a lighting mechanism. The power source includes at least one nanotech battery, ensuring superior properties such as prolonged electricity production and prompt recharging.
| Heating device using exothermic chemical reaction|
The current invention discloses a treatment device having a heat source, a power source, a heat applicator and a lighting mechanism. The power source includes at least one battery having superior properties such as prolonged electricity production and prompt recharging.
| Method for repairing white defect of liquid crystal display panel|
A method for repairing white defect of liquid crystal display panel includes: (1) providing a laser repairing platform and a liquid crystal display panel that contains a white defect to be repaired, wherein the white defect contained liquid crystal display panel comprises a substrate, a first insulation layer formed on the common wiring layer, a metal layer formed on the first insulation layer, a second insulation layer formed on the metal layer, and a transparent conductive layer formed on the second insulation layer; and (2) applying the laser repairing platform to carry out multi-spot welding on the common wiring layer, the metal layer, and the transparent conductive layer at a location corresponding to a white defect of the liquid crystal display panel so as to have the common wiring layer, the metal layer, and the transparent conductive layer electrically connected at sites corresponding to the multiple welding spots.. .
| Method of fabricating mos device|
Provided is a method of fabricating a mos device including the following steps. At least one gate structure is formed on a substrate, wherein the gate structure includes a gate conductive layer and a hard mask layer disposed on the gate conductive layer.
| Fabrication method of semiconductor package having electrical connecting structures|
A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability..
| Avalanche photodiodes and methods of fabricating the same|
Provided are an avalanche photodiode and a method of fabricating the same. The method of fabricating the avalanche photodiode includes sequentially forming a compound semiconductor absorption layer, a compound semiconductor grading layer, a charge sheet layer, a compound semiconductor amplification layer, a selective wet etch layer, and a p-type conductive layer on an n-type substrate through a metal organic chemical vapor deposition process..
| Fuel cell and proces for manufacturing a fuel cell|
The present invention pertains to a fuel cell with a storage unit (4) for storing hydrogen (hx), with a proton conductive layer, which covers a surface of the storage unit (4), and with a cathode (7) on a side of the proton conductive layer, which side is located opposite, wherein the storage unit (4) is directly coupled with an anode and/or the storage unit (4) is incorporated in a substrate (1) of a semiconductor. The storage unit (4) is preferably connected to the substrate (1) at least via a stress compensation layer (3)..
| Circuit board material|
A circuit board material includes an electrical resistance material layer having a preselected resistivity adhered to the support layer, and a barrier layer adhered to the electrical resistive layer, and a conductive layer adhered to the barrier layer, wherein the barrier layer is plated on the conductive material such that the resistance of the subsequently applied resistive layer does not vary substantially during exposure to printed circuit board processing chemistries. The process for making the material is directed to adjusting the electro deposition of the barrier layer by using the time for etching the resistive layer of the circuit board material in a standard etching bath..
| Circuit substrate|
A circuit substrate includes: a laminate substrate in which a conductive layer and an insulating layer are laminated; a filter chip that has an acoustic wave filter and is provided inside of the laminate substrate; and a chip component that is provided on a surface of the laminate substrate and is connected to the filter chip, at least a part of the chip component overlapping with a projected region that is a region of the filter chip projected in a thickness direction of the laminate substrate.. .
| Pcb stackup having high- and low-frequency conductive layers and having insulating layers of different material types|
A printed circuit board (pcb) stackup includes conductive layers and insulating layers interleaved among the conductive layers. The conductive layers include one or more power layers, one or more ground layers, one or more high-frequency layers, and one or more low-frequency layers.
| Electrochromic multi-layer devices with spatially coordinated switching|
A multi-layer device comprising a first substrate and a first electrically conductive layer on a surface thereof, the first electrically conductive layer having a sheet resistance to the flow of electrical current through the first electrically conductive layer that varies as a function of position.. .
| Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core|
A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer.
| Semiconductor device and method of manufacturing the same|
The semiconductor device includes a first conductive layer, a first interlayer insulating film, a bit line, a first insulating film, a second interlayer insulating film, and a second conductive layer. The first insulating film that covers a side surface of the bit line has a portion perpendicular to a main surface of a semiconductor substrate in a region lower than a position lower than an uppermost portion of the first insulating film by a thickness, in a direction along the main surface of the semiconductor substrate, of the first insulating film that covers the side surface of the bit line at a lowermost portion of the bit line..
| Lead frame and a method of manufacturing thereof|
A method of manufacturing a lead frame, comprising the steps of: providing an electrically-conductive base material having first and second planar sides; forming a patterned conductive layer on the first planar side of the base material; etching the second planar side of the base material at portions with respect to exposed portions on the first planar side of the base material comprising the patterned conductive layer, to form partially-etched portions on the second planar side of the base material; providing a non-conductive filling material over the second planar side of the base material, wherein the filling material fills spaces inside the partially-etched portions on the second planar side of the base material to form adjacent portions of the filling material and a plurality of conductive portions on the second planar side of the base material; and etching the exposed portions of the first planar side of the base material comprising the patterned conductive layer to form partially-etched portions on the first planar side of the base material that combine with the partially-etched portions on the second planar side of the base material to thereby form a plurality of separate conductive regions on the first planar side of the base material, each conductive region being electrically conductive with at least a respective one of the plurality of conductive portions on the second planar side of the base material.. .
| Chip with through silicon via electrode and method of forming the same|
The present invention provides a method of forming a chip with tsv electrode. A substrate with a first surface and a second surface is provided.
| Semiconductor device and method of manufacturing the same|
According to a method of manufacturing a semiconductor device, hard mask lines are formed in parallel in a substrate and the substrate between the hard mask lines is etched to form grooves. A portion of the hard mask line and a portion of the substrate between the grooves are etched.
| Metallized film-over-foam contacts|
A metallized film-over-foam contact suitable for circuit grounding of surface mount technology devices generally includes a silicone foam resilient core member, a solderable electrically conductive layer, and an adhesive bonding the solderable electrically conductive layer to the resilient core member. The adhesive has no more than a maximum of 900 parts per million chlorine, no more than a maximum of 900 parts per million bromine, and no more than a maximum of 1,500 parts per million total halogens..
| Method for online detection of liner buckling in a storage system for pressurized gas|
A pressurized gas storage system includes an outer shell having an inner and outer surface. The inner surface defines an inner volume for holding a pressurized gas.
| Method of manufacturing multilayer wiring substrate, and multilayer wiring substrate|
In a build-up step, a plurality of resin insulation layers and a plurality of conductive layers are alternately laminated in multilayer arrangement on a metal foil separably laminated on a side of a base material, thereby forming a wiring laminate portion. In a drilling step, a plurality of openings are formed in an outermost resin insulation layer through laser drilling so as to expose connection terminals.
| Transparent conductive film, method of manufacturing the same, and touch panel having the same|
Provided are a transparent conductive film, a method of manufacturing the same, and a touch panel having the same, the transparent conductive film including: a transparent film; and a conductive layer formed on one surface of the transparent film, wherein the conductive layer includes a linear interconnecting structure layer and a pedot(poly-3,4-ethylene dioxythiophene)-pss(polystyrenesulfonate) layer. In accordance with the present invention, it can be provided with the conductive film, which has improved haze and non-resistant properties, excellent flexibility, and low costs by economic processes, even without a structural change of the transparent conductive film, and the touch panel and the display using the same..
| Light control panel|
Alight control panel is provided, comprising: a transmissive substrate; a transmissive electrically conductive layer arranged on a surface of said substrate; a transmissive dielectric layer arranged on said electrically conductive layer; a flexible roll-up blind attached to said dielectric layer, said flexible roll-up blind layer comprising a flexible electrically conductive layer and a flexible optically functional layer, said flexible layer having naturally a rolled configuration and being capable of unrolling in response to electrostatic force; and an optoelectronic device. The panel may be useful in various energy saving applications including smart windows for buildings or vehicles, e.g.
| Solar cell and method of manufacturing the solar cell|
A solar cell is disclosed. The solar cell includes a transparent conductive layer formed on a substrate, microstructures protruding vertically aslant from a surface of the transparent conductive layer, an electron transport layer configured to cover the microstructures and formed of an electron transport metal oxide, a light absorber adhered to inner pores and a surface of the electron transport layer, a hole transport layer configured to cover the surface of the electron transport layer and formed of a hole transport material, and an electrode formed on the hole transport layer.
| Substrate processing apparatus and susceptor|
A substrate processing apparatus includes a chamber, a susceptor to receive a substrate and provided in the chamber, a gas supply source to supply a predetermined gas into the chamber, and a high frequency power source to treat the substrate by plasma. The susceptor includes a first ceramics base member including a flow passage to let a coolant pass through, a first conductive layer formed on a principal surface and a side surface on a substrate receiving side of the first ceramics base member, and an electrostatic chuck stacked on the first conductive layer and configured to electrostatically attract the wafer received thereon.
| Method for connecting plates of a substrate device|
An approach is provided for a method for connecting multiple plates of a substrate device, the substrate device at least comprises a conductive layer and a plate has at least one hollowed hole that is used to directly transfer the heat from a high power electrical chip to the conductive layer, the method comprises acts of forming a first cupper layer on a top surface of the plate and forming a second cupper layer on a bottom surface of the plate, printing a circuit on the first cupper layer, and soldering the second cupper layer on the conductive layer with a soldering paste.. .
|Method of forming semiconductor structure having contact plug|
A method of forming a semiconductor structure having at least a contact plug includes the following steps. At first, at least a transistor and an inter-layer dielectric (ild) layer are formed on a substrate, and the transistor includes a gate structure and two source/drain regions.
|Method of fabricating capacitor structure|
A method of fabricating a capacitor structure includes the following steps. Firstly, a substrate is provided.
|Organic light emitting diode display and method for manufacturing the same|
An organic light emitting diode (oled) display and a manufacturing method thereof, the oled display includes: a substrate main body; a polycrystalline silicon layer pattern including a polycrystalline active layer formed on the substrate main body and a first capacitor electrode; a gate insulating layer pattern formed on the polycrystalline silicon layer pattern; a first conductive layer pattern including a gate electrode and a second capacitor electrode that are formed on the gate insulating layer pattern; an interlayer insulating layer pattern formed on the first conductive layer pattern; and a second conductive layer pattern including a source electrode, a drain electrode and a pixel electrode that are formed on the interlayer insulating layer pattern. The gate insulating layer pattern is patterned at a same time with any one of the polycrystalline silicon layer pattern and the first conductive layer pattern..
|Electrophotographic photoconductor, image forming apparatus, and process cartridge|
An electrophotographic photoconductor, including: an electroconductive substrate; and at least a photoconductive layer and a surface layer in this order over the electroconductive substrate, wherein the surface layer includes a resin having no charge transport properties, and first inorganic fine particles, and wherein the first inorganic fine particles are inorganic fine particles having surfaces modified with at least one of a primary amino group and a secondary amino group, and a volume resistivity of the first inorganic fine particles is 1×108 Ω·cm or less.. .
|Electric storage device and manufacturing method thereof|
Provided is an electric storage device including: a first electrode plate, a second electrode plate having a polarity opposite to that of the first electrode plate, and a separator interposed between the first electrode plate and the second electrode plate, wherein the first electrode plate includes a current collector, a conductive layer laminated onto the current collector, and a mixture layer laminated onto the conductive layer, the mixture layer contains a binder and primary particles of an active material as its constituents, and the primary particles as a constituent of the mixture layer are partially retained in the conductive layer.. .
|Integrated circuit 3d phase change memory array and manufacturing method|
A 3d phase change memory device can store multiple bits per cell represented by a plurality of non-overlapping ranges of resistance all of which are established by different resistance ranges corresponding to respective amorphous phase thickness of the phase change memory material. An array of access devices can underlie a plurality of conductive layers, separated from each other and from the array of access devices by insulating layers.
|Metal mesh conductive layer and touch panel having the same|
The present invention relates to to a metal mesh conductive layer and touch panel having the conductive layer. A surface of the conductive layer includes a transparent electrode region and an electrode lead region, the transparent electrode region having a mesh made of metal; the electrode lead region having a mesh made of conductive material containing metal.
|Input element for operating a touch-screen|
There is described an input element for operating a touch-screen, said input element comprising an electrically conductive layer which is applied to an electrically non-conductive substrate. The electrically conductive layer is structured and has at least one button, conductor track and/or electrode, wherein at least one electrode and/or conductor track is operatively connected to the touch-screen..
|Touch display apparatus|
A touch display apparatus including a display panel, a touch panel, a transparent conductive layer, and a conductive adhesive layer is provided. The touch panel is disposed on the display panel, and includes a cover lens, a touch device, and a shielding conductive ring.
|Silicon-based electrode for a lithium-ion cell|
A silicon-based electrode includes a silicon layer on a substrate, an electrically conductive layer overlying a top surface of the silicon layer, an optional polymer layer overlying the top surface of the electrically conducting layer, and a plurality of channels extending through the electrically conductive layer and the silicon layer to the substrate. The channels define sidewalls in the silicon layer.
|Conductive layer of a large surface for distribution of power using capacitive power transfer|
An apparatus (300) for supplying power to a load in a capacitive power transfer system comprises a power generator (350) operating at a first frequency; a transmitter comprising a plurality of first electrodes (310) connected to a first terminal of the power generator (350) and a plurality of second electrodes (320) connected to a second terminal of the power generator (350) of a transmitter portion of the apparatus (300); and a plurality of inductors (340), wherein each inductor of the plurality of inductors is connected between a pair of a first electrode and a second electrode of the plurality of first and second electrodes, wherein each inductor comprises, together with a parasitic capacitor (330) formed between each pair of the first electrode and the second electrode, a resonant circuit at the first frequency in order to compensate for current loss due to parasitic capacitances.. .
|Mold, mold manufacturing method and method for manufacturing anti-reflection film using the mold|
A mold of at least one embodiment of the present invention includes: a base; a conductive layer provided on the base; and an anodized film provided on the conductive layer, the anodized film having an inverted motheye structure in its surface, the inverted motheye structure having a plurality of recessed portions whose two-dimensional size viewed in a direction normal to the surface is not less than 10 nm and less than 500 nm, wherein the base, the conductive layer, and the anodized film are capable of transmitting ultraviolet light.. .
|Package structure and method for manufacturing thereof|
The invention provides an electronic device package and method for manufacturing thereof. The electronic device package includes a substrate, an electronic chip, a bonding pad, a first passivation layer, a conductive layer, a second passivation layer, and a solder ball.
|Mim capacitor and mim capacitor fabrication for semiconductor devices|
In a particular embodiment, a method of forming a metal-insulator-metal (mim) capacitor includes removing, using a lithographic mask, a first portion of an optical planarization layer to expose a region in which the mim capacitor is to be formed. A second portion of an insulating layer is formed on a first conductive layer that is formed on a plurality of trench surfaces within the region.
|Circuit board and display device|
A source and drain electrode layer (3s/3d) of an oxide tft element (3) is formed by a first conductive layer. A gate electrode (3g) of the oxide tft element (3) and a gate electrode (5g) of an a-si tft element (5) are formed by a single conductive layer, that is, a second conductive layer.
|Transistor and display device|
It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material.
|Thin film transistor and display substrate having the same|
A display substrate includes a base substrate, a semiconductor active layer disposed on the base substrate, a gate insulating layer disposed on the semiconductor active layer, a first conductive pattern group disposed on the gate insulating layer and including at least a gate electrode, a second conductive pattern group insulated from the first conductive pattern group and including at least a source electrode, a drain electrode, and a data pad. The second conductive pattern group includes a first conductive layer and a second conductive layer disposed on the first conductive layer to prevent the first conductive layer from being corroded and oxidized..
|Sputtering apparatus and method for forming a transmissive conductive layer of a light emitting device|
There is provided a method for manufacturing a nitride semiconductor light emitting device, including: forming a light emitting structure including first and second conductive nitride semiconductor layers on a substrate and an active layer formed therebetween; forming the first conductive nitride semiconductor layer, the active layer, and the second conductive nitride semiconductor layer in sequence; forming a first electrode connected to the first conductive nitride semiconductor layer; forming a photo-resist layer on the second conductive nitride semiconductor layer so as to expose a portion of the semiconductor layer; and removing the photo-resist layer after a reflective metal layer and a barrier metal layer serving as a second electrode structure are successively formed on the second conductive nitride semiconductor layer exposed by the photo-resist layer.. .
|Resilient adherent emi shielding member|
In order to prevent emi leakage from various openings formed in module-receiving receptacles, a flexible, conductive shield member is provided. The shield member may have multiple layers but includes at least a conductive layer and an adhesive layer.
|A composite glass plate|
In order to obtain a composite glass plate which shields infrared light and/or ultraviolet light, two glass substrates on which transparent conductive layers are formed respectively are disposed with the transparent conductive layers thereof facing each other. Infrared light is shielded and electric power is generated by using one glass substrate as a light incident side electrode, disposing a silicon dioxide particle layer thereon, and filling a colorless electrolyte between the two glass substrates.
|Method for forming interlayer connectors to a stack of conductive layers|
A method forms interlayer connectors extending to conductive layers of a stack of w conductive layers interleaved with dielectric layers. The stack is etched to expose landing areas at w−1 conductive layers using a set of m etch masks.
|Backlight module, printed circuit board used for backlight module, and manufacturing method for the same|
The present invention discloses a backlight module, a printed circuit board used for a backlight module, and a manufacturing method for the same. The printed circuit board comprises a light bar region and a heat dissipating region.
|Borderless touch panel design|
A borderless touchscreen panel includes a first conductive layer having rows of capacitive sensors and receiving traces, and a second conductive layer having columns of sensor bars and transmitting traces. The capacitive sensors are coupled to control circuitry via the receiving traces, and the sensor bars are coupled to the control circuitry via the transmitting traces.
|Interconnection structures and fabrication method thereof|
A method is provided for fabricating an interconnection structure. The method includes providing a semiconductor substrate having certain semiconductor devices inside, a dielectric layer covering the semiconductor devices, and vias inside the dielectric layer connecting with connection pads of the semiconductor devices.
|Forming vias and trenches for self-aligned contacts in a semiconductor structure|
A semiconductor structure is formed to include a non-conductive layer with at least one metal line, a first dielectric layer, a first stop layer, a second dielectric layer, a second stop layer, a third stop layer and a fourth stop layer. A first photoresist layer is formed over the upper stop layer to develop at least one via pattern.
|Semiconductor device and method of manufacturing the same|
A semiconductor device includes a substrate in which a cell region and a contact region are defined, a pad structure including a plurality of first conductive layers and a plurality of first insulating layers formed alternately with each other in the contact region of the substrate, wherein an end of the pad structure is patterned stepwise, portions of the first conductive layers exposed at the end of the pad structure are defined as a plurality of pad portions, and the plurality of pad portions have a greater thickness than unexposed portions of the plurality of first conductive layers.. .
|3d stacking semiconductor device and manufacturing method thereof|
A 3d stacking semiconductor device and a manufacturing method thereof are provided. The manufacturing method includes the following steps.
|Semiconductor package and fabrication method thereof|
A semiconductor package is provided. The semiconductor package includes a substrate; a semiconductor element having opposite active and inactive surfaces and disposed on the substrate via the active surface thereof, wherein the inactive surface of the semiconductor element is roughened; a thermally conductive layer bonded to the inactive surface of the semiconductor element; and a heat sink disposed on the thermally conductive layer.
|Semiconductor package and fabrication method thereof|
A semiconductor package is provided, including: a substrate; a first semiconductor element disposed on the substrate and having a first conductive pad grounded to the substrate; a conductive layer formed on the first semiconductor element and electrically connected to the substrate; a second semiconductor element disposed on the first semiconductor element through the conductive layer; and an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements. Therefore, the first and second semiconductor elements are protected from electromagnetic interference (emi) shielding with the conductive layer being connected to the grounding pad of the substrate.
|Semiconductor-on-oxide structure and method of forming|
Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer..
|Method of manufacturing a non-volatile memory|
The disclosure relates to a method of manufacturing vertical gate transistors in a semiconductor substrate, comprising implanting, in the depth of the substrate, a doped isolation layer, to form a source region of the transistors; forming, in the substrate, parallel trench isolations and second trenches perpendicular to the trench isolations, reaching the isolation layer, and isolated from the substrate by a first dielectric layer; depositing a first conductive layer on the surface of the substrate and in the second trenches; etching the first conductive layer to form the vertical gates of the transistors, and vertical gate connection pads between the extremity of the vertical gates and an edge of the substrate, while keeping a continuity zone in the first conductive layer between each connection pad and a vertical gate; and implanting doped regions on each side of the second trenches, to form drain regions of the transistors.. .
|Light emitting device and lighting system|
A light emitting device includes a conductive support member, a first conductive layer disposed on the conductive support member, a second conductive layer disposed on the first conductive layer, a light emitting structure including a first semiconductor layer, layer disposed on the second conductive layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer, and an insulation layer disposed between the first conductive layer and the second conductive layer. The first conductive layer includes a first expansion part penetrating through the second conductive layer, the second semiconductor layer and the active layer, and includes a second expansion part extending from the first expansion part and being disposed in the first semiconductor layer.
|Light emitting device and lighting system|
A light emitting device includes a conductive support member, a first conductive layer disposed on the conductive support member, a second conductive layer disposed on the first conductive layer, a light emitting structure including a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer, and an insulation layer disposed between the first conductive layer and the second conductive layer. The first conductive layer includes a first expansion part penetrating through the second conductive layer, the second semiconductor layer and the active layer, and includes a second expansion part extending from the first expansion part and being disposed in the first semiconductor layer.
|Graphene electronic devices and methods of manufacturing the same|
A graphene electronic device includes: a first conductive layer and a semiconductor layer on a first region of an intermediate layer; a second conductive layer on a second region of the intermediate layer; a graphene layer on the intermediate layer, the semiconductor layer, and the second conductive layer; and a first gate structure and a second gate structure on the graphene layer.. .
|Vertical bipolar transistor|
The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer..
|Method of fabricating a vertical mos transistor|
The disclosure relates to a method of fabricating a vertical mos transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole.. .
|Sample block holder|
A sample holder assembly includes a sample tray, a base plate, a stage mount, and a calibration standard mounted onto the stage mount. Three mating structures on the bottom of the base plate mate with corresponding structures on a stage mount that is attached to the sample stage of the sem.
|Flexible printed circuit|
A flexible printed circuit includes a first insulating substrate layer and a first electrically conductive layer located adjacent to a first side of the insulating substrate layer. The first conductive layer has a first portion that is substantially solid and a second portion having a multiplicity of voids in the first conductive layer in a pattern for providing a lower stiffness in the second portion relative to the first portion, thereby providing more flexibility in the second portion relative to the first portion..
|Method of fabricating flexible metal core printed circuit board|
A flexible metal core printed circuit board assembly comprises a flexible printed circuit board structure. The flexible printed circuit board structure includes a flexible substrate, a conductive layer on the flexible substrate and a space formed in the flexible printed circuit board structure.
|Tandem solar cell|
A solar cell is configured by: arranging two glass substrates, each of which is provided with a transparent conductive layer, so that the transparent conductive layers face each other; disposing a titanium dioxide layer on one glass substrate; disposing silicon dioxide particles on the other glass substrate; and filling the space between the two glass substrates with an electrolyte. The glass substrate on which light does not enter may alternatively be a metal plate.
|Patterned electrodes for tissue treatment systems|
Methods, apparatus, and systems for treating tissue located beneath a tissue surface with electromagnetic energy delivered from a treatment electrode. The treatment electrode may include a conductive layer and a plurality of openings extending through the conductive layer.
|Semiconductor device with self-aligned air gap and method for fabricating the same|
A method for fabricating a semiconductor device includes forming a plurality of semiconductor structures over a substrate, forming an interlayer dielectric layer over the semiconductor structures, etching the interlayer dielectric layer, and defining open parts between the semiconductor structures to expose a surface of the substrate, forming sacrificial spacers on sidewalls of the open parts, forming conductive layer patterns in the open parts, and causing the conductive layer patterns and the sacrificial spacers to reach each other, and defining air gaps on the sidewalls of the open parts.. .
|Semiconductor device with recess gate and method for fabricating the same|
A method for fabricating a semiconductor device includes forming a conductive layer over first and second regions of a semiconductor substrate, forming a trench extended in the first region of the semiconductor substrate through the conductive layer, forming a recessed gate electrode in the trench, doping the conductive layer and the recessed first gate electrode, and forming a second gate electrode by etching the doped conductive layer.. .
|Customized shield plate for a field effect transistor|
A customized shield plate field effect transistor (fet) includes a semiconductor layer, a gate dielectric, a gate electrode, and at least one customized shield plate. The shield plate includes a conductive layer overlying a portion of the gate electrode, one of the gate electrode sidewalls, and a portion of the substrate adjacent to the sidewall.
|Nanostructured electrolytic energy storage devices|
In one embodiment, a structure for an energy storage device may include a first nanostructured substrate having a conductive layer and a dielectric layer formed on the conductive layer. A second nanostructured substrate includes another conductive layer.
|Touch panel and touch display device|
The present invention provides a touch panel and a touch display device, the touch panel includes: a transparent substrate; a conductive layer disposed on the transparent substrate, where the conductive layer includes a plurality of first conductive patterns and a plurality of second conductive patterns intersecting with the plurality of first conductive patterns, and each of the second conductive patterns is separated into multiple segments by the plurality of first conductive patterns; a color resistance insulating layer disposed on the conductive layer, where the color resistance insulating layer includes a plurality of through-holes; and a metal bridging layer disposed on the color resistance insulating layer, where the multiple segments of the second conductive pattern are connected together by the metal bridging layer via the through-holes. With the technical solutions of the present invention, the color resistor is used as the insulating layer to replace the existing organic film layer, thus avoiding the undesirable risk brought about by the manufacturing process for coating the organic film, simplifying the manufacturing process and reducing the production costs..
|Mobile device and antenna structure therein|
A mobile device includes a ground element, a conductive bezel, a nonconductive layer, and a feeding element. The conductive bezel is substantially independent of the ground element.
|Resonant embedded antenna|
A planar antenna, such as included as a portion of a printed circuit board assembly, can include a first conductive layer comprising a feed conductor and a patch. The planar antenna can include a second conductive layer comprising a reference conductor, a first arm defined by a first arm length and a first arm width, and a second arm located parallel to the first arm and defined by a second arm length and a second arm width.
|Laminated waveguide diplexer with shielded signal-coupling structure|
A laminated waveguide diplexer includes an upper conductive layer having a first slot and a second slot; a first line crossing over the first slot; a first shielding conductor disposed over the first line; a plurality of first conductive pillars connecting the upper conductive layer and the first shielding conductor; a second line crossing over the second slot; a second shielding conductor disposed over the second line; and a plurality of second conductive pillars connecting the upper conductive layer and the second shielding conductor.. .