|| List of recent Circuit Pack-related patents
| Bumpless build-up layer package with pre-stacked microelectronic devices|
The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (bbul) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package..
|Package for high frequency circuits|
The present invention relates to integrated circuit packaging and methods of manufacturing these. In particular, but not exclusively the present invention relates to improvements in the suppression of spurious wave modes within cavity packages in which are mounted circuits operating at high frequencies, for example monolithic microwave integrated circuits (mmic's)..
|Solar powered ic chip|
A self-powered circuit package includes a substrate and an integrated circuit (ic). The ic is mounted on a surface of the substrate.
|3d integrated circuit package with through-mold first level interconnects|
3d integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate.
|Low profile zero/low insertion force package top side flex cable connector architecture|
An integrated circuit package is presented. In an embodiment, the integrated circuit package has contact pads formed on the top side of a package substrate, a die electrically attached to the contact pads, and input/output (i/o) pads formed on the top side of the package substrate.
|Induction-coupled clock distribution for an integrated circuit|
An integrated circuit package including an induction-coupled clock distribution system is disclosed. An exemplary embodiment of the disclosure includes a transmission module coupled to a main clock line, a clock reception module coupled to the transmission module, the clock reception module including a clock output line, and an electronic circuit coupled to the clock output line of the clock reception module, the electronic circuit including at least one clocked element and configured to operate synchronously with a clocking signal received through the clock output line of the clock reception module.
|Integrated circuit package with active interposer|
An integrated circuit package may include a substrate and an interposer. The interposer is disposed over the substrate.
|Open cavity plastic package|
A method for manufacturing open cavity integrated circuit packages, the method comprising: placing a wire-bound integrated circuit in a mold; forcing a pin to contact a die of the wire-bound integrated circuit by applying a force between the pin and the mold; injecting plastic into the mold; allowing the plastic to set around the integrated circuit to form a package having an open cavity defined by the pin; and removing the open cavity integrated circuit package from the mold. A mold for forming a package for an integrated circuit sensor device, comprising: a bottom part for supporting an integrated circuit die; a top part that is operable to be placed on top of said bottom part to form a cavity into which a plastic material can be injected to form the package, wherein the top part of the mold comprises a spring-loaded pin arrangement comprising a cover that covers a sensor area on the integrated circuit die and provides for an opening when the plastic material is injected..
|Integrated circuit packaging system with molded grid-array mechanism and method of manufacture thereof|
A method of manufacture of an integrated circuit packaging system includes: providing a lead-frame having a metal connector mounted thereon and having a peripheral mounting region; forming an insulation cover on the lead-frame and on the metal connector; connecting an integrated circuit die over the insulation cover; forming a top encapsulation on the integrated circuit die with the peripheral mounting region exposed from the top encapsulation; forming a routing layer, having a conductive land, from the lead-frame; and forming a bottom encapsulation partially encapsulating the routing layer and the insulation cover.. .
|Treatment method of electrodeposited copper for wafer-level-packaging process flow|
A method of treating a copper containing structure on a substrate is disclosed. The method includes electrodepositing the copper containing structure on a substrate, annealing the copper containing structure, and forming an interface between a pad of the copper containing structure and a solder structure after anneal.
|3d integrated circuit package with window interposer|
3d integrated circuit packages with window interposers and methods to form such semiconductor packages are described. For example, a semiconductor package includes a substrate.
|Integrated circuit package and method of making|
An integrated circuit (“ic”) device and method of making it. The ic device may include a conductive lead frame that has a die pad with a relatively larger central body portion and at least one relatively smaller peripheral portion in electrical continuity with the central body portion.
|Integrated circuit package|
An integrated circuit (ic) package including a bottom leadframe, an interposer mounted on the bottom leadframe, a flipchip die mounted on the interposer and a top leadframe electrically connected to the interposer. Also, a method of making an integrated circuit (ic) package including electrically and physically attaching a die to an interposer, attaching the interposer to a bottom leadframe, attaching a discrete circuit component to the interposer and attaching a top leadframe to the bottom leadframe..
|Integrated circuit package|
An integrated circuit package comprising a substrate and at least one semiconductor die is described. A connection unit may provide electrical connections between the substrate and the semiconductor die.
|Mechanism for facilitating and employing a magnetic grid array|
A mechanism is described for facilitating and employing a magnetic grid array according to one embodiment. A method of embodiments may include engaging, via magnetic force of a magnet, magnetic contacts of a magnetic grid array to substrate lands of a package substrate of an integrated circuit package of a computing system, and disengaging, via a removal lever, the magnetic contacts from the substrate lands..
|Solder mask shape for bot laminate packages|
A device is provided. The device may comprise an integrated circuit package.
|Ball grid array package with improved thermal characteristics|
An integrated circuit package includes a substrate having first and second surfaces and a plurality of conductive traces therebetween and a semiconductor die mounted on the first surface of the substrate. A plurality of wire bonds connect the semiconductor die to ones of the conductive traces of the substrate and an encapsulant encapsulates the wirebonds and the semiconductor die.
|Compartmentalized heat spreader for electromagnetic mitigation|
An approach for compartmentalizing heat spreaders within an integrated circuit package is provided. In one aspect, the approach comprises a shielding member that is connected to the integrated circuit package.
|Reduction of underfill filler settling in integrated circuit packages|
Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (ic) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the ic package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature.
|Image display system and method for displaying image|
An image display system and a method for displaying the image are disclosed, in which the image display system includes a display device and a host. The display device includes an acceleration sensor and a microcontroller.
|Absorbing excess under-fill flow with a solder trench|
One embodiment sets forth an integrated circuit package that includes a substrate, one or more devices mounted on the substrate, a layer of under-fill configured to secure the one or more devices on the substrate, and a solder trench formed in the substrate, where the aggregate volume of the solder trench is large enough to capture a flow of excess under-fill during fabrication. One advantage of the disclosed integrated circuit package is that the solder trench is used in lieu of solder dam structures, thereby allowing a stencil to be lowered closer to the substrate surface during fabrication, which facilitates depositing solder paste during fabrication..
|Integrated circuit package and method of manufacture|
An integrated circuit package has a leadframe having an open space extending therethrough. An integrated circuit device is attached to a portion of the upper surface of the leadframe.
|Integrated circuit package with printed circuit layer|
An integrated circuit (ic) package including an ic die and a conductive ink printed circuit layer electrically connected to the ic die.. .
|Low parasitic package substrate having embedded passive substrate discrete components and method for making same|
One feature pertains to a multi-layer package substrate of an integrated circuit package that comprises a discrete circuit component (dcc) having at least one electrode. The dcc is embedded within an insulator layer, and a via coupling component electrically couples to the electrode.
|Integrated circuit packaging system with transferable trace lead frame|
System and method of manufacturing an integrated circuit packaging system using transferable trace lead frame. A lead frame is provided having lower metal contacts.
|Semiconductor cooling device|
A system and a method of self-cooling a semiconductor package are described. A cell is formed, which contains a thermally conductive and electrically insulative material, sandwiched between a first thermally conductive plate and a second thermally conductive plate.
|Integrated circuit packaging system with routable grid array lead frame|
System and method of manufacturing an integrated circuit packaging system using routable grid array lead frame. Method includes providing a lead frame having top metal connector and bottom contact, and treating the top metal connector with an additive, or the bottom contact with an additive, or both.
|Electrical connectivity for circuit applications|
According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits.
|Package having thermal compression flip chip (tcfc) and chip with reflow bonding on lead|
Some exemplary implementations of this disclosure pertain to an integrated circuit package that includes a substrate, a first die and a second die. The substrate includes a first set of traces and a second set of traces.
|Electrical interconnect for an integrated circuit package and method of making same|
An interconnect assembly for an embedded chip package includes a dielectric layer, first metal layer comprising upper contact pads, second metal layer comprising lower contact pads, and metalized connections formed through the dielectric layer and in contact with the upper and lower contact pads to form electrical connections therebetween. A first surface of the upper contact pads is affixed to a top surface of the dielectric layer and a first surface of the lower contact pads is affixed to a bottom surface of the dielectric layer.
|Symmetrical hexagonal-based ball grid array pattern|
The present disclosure provides techniques for creating a symmetrical ball grid array pattern for an integrated circuit package. The ball grid array includes a symmetrical pattern of circuit connection points, wherein the symmetrical pattern is derived from a base hexagonal pattern that is repeated in at least one or more sections of the ball grid array..
|Transmission line for an integrated circuit package|
Communication between chips is provided using a transmission line. Any one of the chips may tap into the transmission line, and communicate with another chip tapped into the transmission line by transmitting a radio frequency (rf) signal to the other chip via the transmission line or receiving an rf signal from the other chip via the transmission line.
|Integrated circuits including magnetic devices, and associated methods|
An integrated circuit includes a semiconductor die including one or more switching circuits, a magnetic core having length and width, first and second metallic leads, and integrated circuit packaging material. The first metallic lead forms a first winding turn around a portion of the magnetic core, and the first metallic lead is electrically coupled to the semiconductor die.
|Embedded integrated circuit package and method for manufacturing an embedded integrated circuit package|
A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects.. .
|Millimeter-wave radio frequency integrated circuit packages with integrated antennas|
A package structure includes a planar core structure, an antenna structure disposed on one side of the planar core structure, and an interface structure disposed on an opposite side of the planar core structure. The antenna structure and interface structure are each formed of a plurality of laminated layers, each laminated layer having a patterned conductive layer formed on an insulating layer.
|Thermal interface material for integrated circuit package assembly and associated techniques and configurations|
Embodiments of the present disclosure are directed towards a thermal interface material for integrated circuit package assembly and associated techniques and configurations. In one embodiment, an apparatus includes a die and a layer of thermal interface material (tim) thermally coupled with the die, the tim including a polymer matrix and carbon filler having anisotropic thermal conductivity disposed in the polymer matrix, the polymer matrix being configured for deposition on the die in liquid form.
|Preventing shorting dendritic migration between electrodes|
In a general aspect, an integrated circuit package includes a first electrode and a second electrode on a support substrate. The first electrode and the second electrode are configured to be electrically coupled to a voltage differential.
|Offset integrated circuit packaging interconnects|
One embodiment of the present invention sets forth an integrated circuit package including a substrate, an integrated circuit die, and a plurality of solder bump structures. The substrate includes a first plurality of interconnects disposed on a first surface of the substrate.
|Variable-size solder bump structures for integrated circuit packaging|
One embodiment of the present invention sets forth an integrated circuit package including a substrate, an integrated circuit die, a first plurality of solder bump structures, and a first plurality of variable-size solder bump structures. The first plurality of solder bump structures electrically couple the integrated circuit die to the substrate.
|Integrated circuit package and method of manufacture|
An integrated circuit (ic) package, device, including a substrate having a top surface with an ic die mounting area and a peripheral area surrounding the mounting area, a plurality of parallel conductor layers, a plurality of insulating layers and a plurality of plated through holes (pths) extending through the conductor layers and insulating layers. Various substrate structures in which certain of the pths and/or conductor layers and/or insulating layers have different cte's than the others is disclosed.
|System for no-lead integrated circuit packages without tape frame|
A system has a leadframe strip and a plurality of integrated circuit dies are each encapsulated in an encapsulant. The encapsulant has a plurality of first cuts and a plurality of second cuts therein.
|Noise cancellation for a magnetically coupled communication link utilizing a lead frame|
An integrated circuit package includes an encapsulation and lead frame with a portion of the lead frame disposed within the encapsulation. The lead frame includes a first conductor formed in the lead frame having a first conductive loop and a third conductive loop disposed substantially within the encapsulation.
|Switch mode power converters using magnetically coupled galvanically isolated lead frame communication|
An integrated circuit package for use in a switch mode power converter comprises an encapsulation and a lead frame. A portion of the lead frame is disposed within the encapsulation.
|Magnetically coupled galvanically isolated communication using lead frame|
An integrated circuit package includes an encapsulation and a lead frame. A portion of the lead frame is disposed within encapsulation.
|Integrated circuit package including wire bond and electrically conductive adhesive electrical connections|
A system may include a package defining a cavity and an integrated circuit (ic) disposed within the cavity. The package may include a first electrically conductive package contact and a second electrically conductive package contact.
|Multi-solder techniques and configurations for integrated circuit package assembly|
Embodiments of the present disclosure are directed towards multi-solder techniques and configurations for integrated circuit (ic) package assembly. In one embodiment, a method includes depositing a plurality of solder balls on a plurality of pads of a package substrate, the plurality of solder balls corresponding with the plurality of pads and performing a solder reflow process to form a solder joint between the plurality of solder balls and the plurality of pads.
|Thermal improvement of integrated circuit packages|
An integrated circuit package comprising an active semiconductor device layer and at least one heat-transfer semiconductor layer on the active semiconductor device layer. The heat-transfer semiconductor layer has a coefficient of thermal expansion that substantially matches a coefficient of thermal expansion of the active semiconductor device layer..
|Built-up substrate, method for manufacturing same, and semiconductor integrated circuit package|
A method for manufacturing a build-up substrate, the build-up substrate comprising an insulating layer and a wiring pattern layer stacked over a circuit substrate, said method comprising the steps of: (i) applying a photoactive metal oxide precursor material to one or both sides of the circuit substrate with a wiring pattern, and drying the applied photoactive metal oxide precursor material to form an insulating film; (ii) forming an opening for a via hole in the insulating film by exposure and development of the insulating film; (iii) applying a heat treatment to the insulating film to convert the insulating film into a metal oxide film, thereby forming a build-up insulating layer of the metal oxide film; and (iv) plating the build-up insulating layer to form via holes in the openings, forming a metal layer on the build-up insulating layer, and etching the metal layer to form a build-up wiring pattern; and (v) repeating the steps from (i) to (iv) at least one time.. .
|Reduced integrated circuit package lid height|
One embodiment of the present invention sets forth an integrated circuit package that includes a substrate, one or more devices mounted on the substrate, and a lid having a top portion and an end portion and configured to encapsulate the one or more devices. The top portion is thinner than the end portion.
|Switch circuit package module|
A switch circuit package module includes a semiconductor switch unit and a capacitor unit. The semiconductor switch unit includes sub micro-switch elements.
|Methods and integrated circuit package for sensing fluid properties|
An integrated circuit package for sensing fluid properties includes: a substrate made of semiconductor material; a fluid property measurement circuit formed on the substrate; and a sensor circuit coupled to the fluid property measurement circuit within a same integrated circuit package. The sensor circuit is configured to generate a field that interacts with the fluid.
|Storage apparatus and storage controller of storage apparatus|
Storage apparatus configured to provide an external apparatus with logical storage area as data storage area, the storage apparatus having a physical storage medium configured to generate the logical storage area, and storage controller communicatively coupled to physical storage medium to control data input/output processing between the external apparatus and the logical storage area, wherein the storage controller includes circuit package including circuit board which implements predetermined function of storage controller and a circuit board case to accommodate the circuit board, plurality of cooling fan units that generate cooling air for cooling circuit component mounted on the circuit board of the circuit package, and a chassis having a structure for accommodating the circuit package and the cooling fan units, some of circuit packages are inserted to be accommodated in chassis from opening thereof and are arranged side by side across width direction of chassis.. .
|Inductor with conductive trace|
Among other things, an inductor comprising a conductive trace and a method for forming the inductor are provided. The inductor comprises a magnetic structure, such as a ferrite core.
|Die down integrated circuit package with integrated heat spreader and leads|
Methods, systems, and apparatuses for integrated circuit packages are provided. An integrated circuit package, such as a quad flat no-lead (qfn) package, includes a plurality of peripherally positioned leads, a heat spreader, an integrated circuit die, and an encapsulating material.
|Reconfiguring through silicon vias in stacked multi-die packages|
Through silicon vias (tsvs) in a stacked multi-die integrated circuit package are controlled to assume different connection configurations as desired during field operation of the package in its normal mission mode. Tsv connections may be reconfigured to connect an affected die in a manner different from, for example, a factory default connection of that die.
|Stacked multi-chip integrated circuit package|
A multi-chip integrated circuit (ic) package is provided which is configured to protect against failure due to warpage. The ic package may comprise a substrate, a level-one ic die and a plurality of level-two ic dies.
|Integrated circuit package|
An integrated circuit package and a manufacturing method thereof are provided. The integrated circuit package can include a substrate provided with a circuit pattern, a first set of bonding fingers and a second set of bonding fingers, a first chip stack mounted on the substrate and having a plurality of first semiconductor chips stacked in a first direction in a stepped manner, each of the first semiconductor chips being provided with a first bonding pad at an end thereof on one side, a second chip stack mounted on the first chip stack and having a plurality of second semiconductor chips stacked in a second direction opposite to the first direction in a stepped manner..
|Method of manufacture integrated circuit package|
An integrated circuit package may be formed using a leadframe having an open space extending therethrough. A shunt is located within the open space such that it is not in contact with any portion of the leadframe.
|Integrated circuit packaging system with coreless substrate and method of manufacture thereof|
A method of manufacture of an integrated circuit packaging system includes: forming a first metal layer on a carrier; forming an insulation layer directly on the first metal layer; exposing a portion of the first metal layer for directly attaching to a die interconnect connecting to an integrated circuit; forming a second metal layer directly on the insulation layer opposite the side of the insulation layer exposed by removing the carrier; and forming a protective layer directly on the insulation layer and the second metal layer, the protective layer exposing a portion of the second metal layer for directly attaching an external interconnect.. .
|Film interposer for integrated circuit devices|
In one embodiment, a stack device comprising a film interposer of a polyimide film material, for example, is assembled. In accordance with one embodiment of the present description, a front side of the film interposer is attached to a first element of the stack device, which may be an integrated circuit package, an integrated circuit die, a substrate such as a printed circuit board, or other structure used to fabricate electronic devices.
|Integrated assembly for installing integrated circuit devices on a substrate|
In one embodiment, a biasing device is actuated using an actuator which is aligned with the biasing device along an alignment axis. A first frame is thereby biased toward a second frame along the alignment axis to bias an integrated circuit package toward a socket.
|Method and apparatus for multiplexing pins of an integrated circuit|
An integrated circuit within an integrated circuit package, including a configuration module and a timing module. The configuration module configures the integrated circuit using a configure operation performed via n pins of the integrated circuit package, where n is an integer greater than 1.
|Mems microphone system for harsh environments|
A mems microphone system suited for harsh environments. The system uses an integrated circuit package.
|Thermal analysis of integrated circuit packages|
A method includes retrieving a first component information of a secured portion of a package, wherein the first component information is encrypted. The step of retrieving includes decrypting the first component information.
|Mold chase for integrated circuit package assembly and associated techniques and configurations|
Embodiments of the present disclosure are directed towards a mold chase for integrated circuit package assembly and associated techniques and configurations. In one embodiment, a method includes receiving a package substrate, the package substrate including a first die mounted on the package substrate by a plurality of first interconnect structures, and a plurality of second interconnect structures disposed on the package substrate and configured to route electrical signals of a second die, protecting a top surface of individual interconnect structures of the plurality of second interconnect structures from deposition of a mold material, and depositing the mold material on the package substrate between the individual interconnect structures of the plurality of second interconnect structures.
|Methods and apparatus for magnetic sensor having non-conductive die paddle|
Methods and apparatus to provide an integrated circuit package having a conductive leadframe, a non-conductive die paddle mechanically coupled to the leadframe, and a die disposed on the die paddle and electrically connected to the leadframe. With this arrangement, eddy currents are reduced near the magnetic field transducer to reduce interference with magnetic fields..
|Three-dimensional semiconductor package device having enhanced security|
A semiconductor package device that includes an integrated circuit device package having a storage circuitry is disclosed. In an implementation, the semiconductor package device includes a semiconductor substrate having a first surface and a second surface.
|Integrated circuit package|
An integrated circuit package has a host integrated circuit with an active front side that is surface-mounted on a support and an inactive backside. Conductive pathways extend between the front and back sides of the integrated circuit.
|Multi-segment led components and led lighting apparatus including the same|
An integrated circuit component can include an integrated circuit package and a plurality of terminals provided on the exterior of the integrated circuit package. The terminals are configured to provide electrical connectivity to an interior of the integrated circuit package and a plurality of light emitting diode (led) segments that includes an led string in the interior of the package, coupled to the plurality of terminals..
|Integrated circuit package having medium-independent signaling interface coupled to connector assembly|
An integrated circuit (ic) package includes electrical contacts disposed at a first surface of the ic package, an integrated circuit implementing an electrical signaling interface, and a connector assembly accessible at a second surface of the ic package. The connector assembly is to mechanically attach to another connector assembly and includes contact terminals electrically coupled to the electrical signaling interface.
|Ridged integrated heat spreader|
An integrated circuit package is presented. In an embodiment, the integrated circuit package has a package substrate, an integrated circuit die attached to the package substrate, and a package level heat dissipation device, such as an integrated heat spreader, attached to the package substrate encapsulating the integrated circuit die.
|Integrated circuit packaging system with array contacts and method of manufacture thereof|
A method of manufacture of an integrated circuit packaging system includes: providing an array of leads having a jumper lead and a covered contact; coupling an insulated bonding wire between the jumper lead and the covered contact; attaching an integrated circuit die over the covered contact; and coupling a bond wire between the integrated circuit die and the jumper lead including coupling the integrated circuit die to the covered contact through the insulated bonding wire.. .