| Patent Application Title
||Patent App Num.
| Sensor module and production method of a sensor module|| 20130145844 || 20130613 |
| A sensor module and method for producing the sensor module including a chip carrier and a sensor chip disposed thereon. The sensor module includes at least one partial cover having a recess on a second face of the chip carrier, such that heat from the chip carrier and/or the sensor chip can be dissipated to the recess.
| Fluid pressure sensor and measurement probe|| 20130145853 || 20130613 |
| A fluid pressure measurement sensor (11) comprises a microelectromechanical system (MEMS) chip (23). The MEMS chip (23) comprises two lateral walls (56), a sensitive membrane (49) connected to said lateral walls (56) and sealed cavity (9). The exterior surfaces of the lateral walls (56) and the sensitive membrane (49) are exposed to the fluid pressure. The lateral walls (56) are designed to subject the sensitive membrane (49) to a compression stress transmitted by the opposite lateral walls (56) where said lateral walls (56) are connected to the sensitive membrane (49) such that the sensitive membrane (49) works in compression only. The MEMS chip (23) also comprises a stress detection circuit (31) to measure the compression state of the sensitive membrane (49) which is proportional to the...|
| Nail polish|| 20130146077 || 20130613 |
| This invention relates to nail coating compositions, to packages including the nail coating compositions, to methods of applying the nail coating composition to a nail and to a use of an additive compound to improve the properties of the nail coating composition of the present invention. In particular, the invention relates to nail coating compositions having improved chip resistance, good adhesion to the nail, a high gloss finish and a short dry-to-touch time.
| Chip card contact array arrangement|| 20130146670 || 20130613 |
| In various embodiments, a chip card contact array arrangement is provided, having a carrier, a plurality of contact arrays which are arranged on a first side of the carrier, an electrically conductive structure which is arranged on a second side of the carrier, which is arranged opposite the first side of the carrier, a first plated-through hole and a second plated-through hole, wherein the first plated-through hole is coupled to the electrically conductive structure, a connecting structure which is arranged on the first side of the carrier, wherein the connecting structure connects the first plated-through hole to the second plated-through hole, the connecting structure having a longitudinal extent which runs parallel to a direction in which a contact-connection device on a reading device is moved relative...|
| Booster antenna structure for a chip card|| 20130146671 || 20130613 |
| In various embodiments, a booster antenna structure for a chip card is provided, wherein the booster antenna structure may include a booster antenna; and an additional electrically conductive structure connected to the booster antenna.
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| Light emitting diode chip|| 20130146910 || 20130613 |
| A light emitting diode chip includes a semiconductor layer sequence, the semiconductor layer sequence having an active layer that generates electromagnetic radiation, wherein the light emitting diode chip has a radiation exit area at a front side. At a rear side lying opposite the radiation exit area, the light emitting diode chip has, at least in regions, a mirror layer containing silver. A functional layer that reduces corrosion and/or improves adhesion of the mirror layer is arranged on the mirror layer, wherein a material from which the functional layer is formed is also distributed in the entire mirror layer. The material of the functional layer has a concentration gradient in the mirror layer, wherein the concentration of the material of the functional layer in the mirror...|
| Electronic device|| 20130146912 || 20130613 |
| An electronic device including an insulating substrate, a plurality of conductive vias and a chip is provided. The insulating substrate has an upper surface and a lower surface opposite to each other. The conductive vias pass through the insulating substrate. The chip is disposed on the upper surface of the insulating substrate and includes a chip substrate, a semiconductor layer and a plurality of contacts. The semiconductor layer is located between the chip substrate and the contacts. The contacts are electrically connected to the conductive vias. The material of the insulating substrate and the material of the chip substrate are the same.
| Electronic device|| 20130146913 || 20130613 |
| An electronic device including an insulating substrate, a chip and a patterned conductive layer is provided. The insulating substrate has an upper surface and a lower surface opposite to each other. The chip is disposed above the upper surface of the insulating substrate. The patterned conductive layer is disposed between the upper surface of the insulating substrate and the chip. The chip is electrically connected to an external circuit via the patterned conductive layer. Heat generated by the chip is transferred to external surroundings via the patterned conductive layer and the insulating substrate.
| Light emitting device and fabricating method thereof|| 20130146921 || 20130613 |
| A light emitting device and a fabricating method thereof are described. The light emitting device includes a substrate, a light emitting chip, a tubular structure, and a fluorescent conversion layer. The tubular structure is formed on a surface of the substrate. The light emitting chip is disposed on the surface of the substrate and is surrounded by the tubular structure. The fluorescent conversion layer is disposed in the tubular structure and covers the light emitting chip. A ratio of a maximal vertical thickness and a maximal horizontal thickness of the fluorescent conversion layer at the light emitting chip is between 0.1 and 10. A distance for the light ray to pass through the fluorescent conversion layer is controlled by using the tubular structure, so as to...|
| Method for coating phosphor, apparatus to perform the method, and light emitting diode comprising phosphor coating layer|| 20130146927 || 20130613 |
| A method of forming a phosphor coating layer on a light emitting diode (LED) chip using electrophoresis includes separating phosphor particles in a suspension according to a particle size, and coating the phosphor particles on a surface of the LED chip by sequentially depositing the separated phosphor particles on the surface of the LED chip according to the particle size. An apparatus to form a phosphor coating layer on an LED chip includes an electrophoresis bath to accommodate a suspension containing phosphor particles separated into layers according to a particle size, and electrodes disposed inside the electrophoresis bath. The electrodes may include a cathode electrode on which the LED chip may be arranged, and an anode electrode.
| Light-emitting diode architectures for enhanced performance|| 20130146932 || 20130613 |
| The present invention relates to light-emitting diodes (LEDs), and related components, processes, systems, and methods. In certain embodiments, an LED that provides improved optical and thermal efficiency when used in optical systems with a non-rectangular input aperture (e.g., a circular aperture) is described. In some embodiments, the emission surface of the LED and/or an emitter output aperture can be shaped (e.g., in a non-rectangular shape) such that enhanced optical and thermal efficiencies are achieved. In addition, in some embodiments, chip designs and processes that may be employed in order to produce such devices are described.
| Light emitting diode chip, light emitting diode package structure, and method for forming the same|| 20130146936 || 20130613 |
| A light emitting diode chip, a light emitting diode package structure and a method for forming the same are provided. The light emitting diode chip includes a bonding layer, which has a plurality of voids, or a minimum horizontal distance between a surrounding boundary of the light emitting diode chip and the bonding layer is larger than O. The light emitting diode chip, the light emitting diode package structure and the method may improve the product yields and enhance the light emitting efficiency.
| Silicone adhesive for semiconductor element|| 20130146939 || 20130613 |
| A silicone adhesive for a semiconductor element that is suitable as a die bonding material for fixing a light emitting diode chip to a substrate. The adhesive includes (a) an addition reaction-curable silicone resin composition having a viscosity at 25° C. of not more than 100 Pa·s, and yielding a cured product upon heating at 150° C. for 3 hours that has a type D hardness prescribed in JIS K6253 of at least 30, (b) a white pigment powder having an average particle size of less than 1 μm, and (c) a white or colorless and transparent powder having an average particle size of at least 1 μm but less than 10 μm. The adhesive exhibits high levels of concealment, effectively reflects light emitted from the...|
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| Electronic chip having channels through which a heat transport coolant can flow, electronic components and communication arm incorporating said chip|| 20130146955 || 20130613 |
| The invention relates to an electronic chip, comprising: a semiconductor substrate (6) having an active area (8) formed by at least one P doped region and at least one N doped region which form one or more P-N junctions through which most of the useful current flows when said electronic chip is in a conductive state, and at least one channel (44) through which a heat transport coolant can flow, the channel(s) passing through at least said P or N doped region of the active area. Each channel (44) is rectilinear and passes through the substrate (6) in a direction which is collinear with a direction F to the nearest ±45°, where the direction F is perpendicular to the plane of the substrate.
| Device including two power semiconductor chips and manufacturing thereof|| 20130146991 || 20130613 |
| A device includes a first power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The device further includes a second power semiconductor chip with a first contact pad and a second contact pad on a first face and a third contact pad on the second face. The first and second power semiconductor chips are arranged one above another, and the first face of the first power semiconductor chip faces in the direction of the first face of the second power semiconductor chip. In addition, the first power semiconductor chip is located laterally at least partially outside of the outline of the second power semiconductor chip.
| Wafer scale image sensor package and optical mechanism including the same|| 20130147000 || 20130613 |
| There is provided an optical mechanism including a substrate, an image sensor chip, a light source, a blocking member and a securing member. The image sensor chip is attached to the substrate and has an active area. The light source is attached to the substrate. The blocking member covers the image sensor chip and has an opening to expose at least the active area of the image sensor chip. The securing member fits on the blocking member to secure the blocking member to the substrate.
| Wafer scale image sensor package and optical mechanism|| 20130147001 || 20130613 |
| There is provided an optical mechanism including a substrate, an image chip, a light source and a securing member. The image chip and the light source are attached to the substrate. The securing member is secured to the substrate and includes a first containing space for accommodating the light source, a second containing space for accommodating the image chip and a blocking region between the first containing space and the second containing space.
| Circuit board component shim structure|| 20130147012 || 20130613 |
| Various circuit boards and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an electrically non-functional component to a surface of a first circuit board. The electrically non-functional component has a first elevation. The surface of the circuit board is adapted to have a semiconductor chip mounted thereon. An electrically functional component is mounted to the surface inward from the electrically non-functional component. The electrically functional component has a second elevation less than the first elevation.
| Wafer level package having cylindrical capacitor and method of fabrication the same|| 20130147014 || 20130613 |
| Disclosed is a wafer level package having a cylindrical capacitor, which is capable of increasing electrostatic capacity thanks to the use of a cylindrical capacitor structure and which includes a wafer chip having a bonding pad formed thereon and an insulating layer formed thereon and exposing the bonding pad, a redistribution layer connected to the bonding pad and extending to one side of the insulating layer, a cylindrical outer electrode connected to the redistribution layer and having a center opening therein, a cylindrical inner electrode formed in the center opening of the outer electrode so as to be separated from the outer electrode, a dielectric layer formed between the outer electrode and the inner electrode, and a resin sealing portion formed on the insulating layer to...|
| Method of stacking flip-chip on wire-bonded chip|| 20130147025 || 20130613 |
| A first chip is mounted on a substrate and includes a plurality of bump pads located on an active surface of the first chip. A wire bonds a first bump pad to the substrate. An intermediate layer is disposed on a portion of the active surface of the first chip, and a via within the intermediate layer extends to a second bump pad. A second chip is disposed on the intermediate layer, and wherein the second chip includes a third bump pad located on an active surface of the second chip and aligned with the via formed in the intermediate layer. A corresponding bump is disposed on one or more of the second bump pad and the third bump pad, and within the via, wherein the...|
| Heat spreader for multiple chip systems|| 20130147028 || 20130613 |
| Various heat spreaders and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a heat spreader that has a surface adapted to establish thermal contact with a first semiconductor chip and a second semiconductor chip on a substrate. The surface includes a first portion adapted to thermally contact a solder-based thermal interface material and a second portion having an opening adapted to hold an organic thermal interface material.
| Ultra-small chip package and method for manufacturing the same|| 20130147029 || 20130613 |
| Some embodiments of the present disclosure provide the design and manufacture of an ultra-small chip assembly. The ultra-small chip assembly comprises a die, a plate-like back electrode disposed on the back-side of the die, and one or more plate-like positive electrodes disposed on the front-side of the die. The ultra-small chip assembly is configured such that one end of the plate-like back electrode extends beyond a first side of the die, and each of the one or more plate-like positive electrodes includes an end which extends beyond a second side of the die. By attaching both the plate-like back electrode and the plate-like positive electrodes on the surfaces of the die, and directly using the exposed ends of the plate-like electrodes as the lead-out electrodes for...|
| Semiconductor device including stacked semiconductor chips without occurring of crack|| 20130147038 || 20130613 |
| A device includes first and second semiconductor chips. The first semiconductor chip includes an edge defining a periphery of the first semiconductor chip. The second semiconductor chip is greater in size than the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip so that the second semiconductor chip hangs over from the edge of the first semiconductor chip. The second semiconductor chip includes a plurality of wiring patterns including a first wiring pattern that positions over the edge of the first semiconductor chip, an insulating film which covers the wiring patterns and which includes on or more holes that expose one or more the wiring patterns, and one or more bump electrodes formed on the one or more the wiring patterns....|
| Semiconductor device|| 20130147039 || 20130613 |
| A semiconductor device includes a wiring board that has a conductive pattern formed on at least one principal surface, and an IC chip that is mounted on the wiring board. The IC chip includes a plurality of electrodes to make conductor connection with the wiring board. The conductive pattern includes a lead line pattern and a heat dissipation pattern. The lead line pattern is connected with at least one of the plurality of electrodes through a conductor. The heat dissipation pattern is physically spaced from the IC chip and the lead line pattern and has a larger surface area than the lead line pattern. Further, the lead line pattern and the heat dissipation pattern are placed opposite to each other with a gap therebetween, and their...|
| Mems chip scale package|| 20130147040 || 20130613 |
| A flip-chip manufactured MEMS device. The device includes a substrate and a MEMS die. The substrate has a plurality of bumps, a plurality of connection points configured to electrically connect the MEMS device to another device, and a plurality of vias electrically connecting the bumps to the connections points. The MEMS die is attached to the substrate using flip-chip manufacturing techniques, but the MEMS die is not subjected to processing normally associated with creating bumps for flip-chip manufacturing.
| Stack package structure and fabrication method thereof|| 20130147041 || 20130613 |
| A stack package structure is provided, including: a substrate; an insulating layer formed on the substrate and having openings for exposing die attach pads and conductive pads of the substrate, respectively; a plurality of first and second conductive terminals formed on the insulating layer and electrically connected to the die attach pads and the conductive pads, respectively; a dielectric layer formed on the insulating layer and having a cavity for exposing the first conductive terminals and a plurality of openings exposing the second conductive terminals; copper pillars formed respectively in the openings of the dielectric layer; a semiconductor chip disposed in the cavity and electrically connected to the first conductive terminals; solder balls formed respectively on the copper pillars that are located proximate to the die...|
| Semiconductor device|| 20130147042 || 20130613 |
| A semiconductor device includes an insulating substrate including a first surface and an opposing second surface, and a semiconductor chip. The semiconductor chip is mounted over the first surface, includes signal electrodes, power-supply electrodes and ground electrodes, which connect to pads on the first surface of the insulating substrate. Lands provided on the second surface of the insulating substrate include signal lands, power-supply lands and ground lands through vias penetrate from the first surface to the second surface of the insulating substrate, and include signal vias electrically connected the signal connection pads to the signal lands, power-supply vias electrically connected the power-supply connection pads to the power-supply lands and ground vias electrically connected the ground connection pads to the ground lands. At least one of the...|
| Offset of contact opening for copper pillars in flip chip packages|| 20130147052 || 20130613 |
| An integrated circuit die has a dielectric layer positioned over all the contact pads on the integrated circuit die. Openings are provided in the dielectric layer over each of the contact pads of the integrated circuit die in order to permit electrical coupling to be made between the integrated circuit and circuit boards outside of the die. For those contact pads located in the central region of the die, the opening in the dielectric layer is in a central region of the contact pad. For those contact pads located in a peripheral region of the die, spaced adjacent the perimeter die, the opening in the dielectric layer is offset from the center of the contact pad and is positioned closer to the central region of the...|
| Chip package and chip package method|| 20130147058 || 20130613 |
| A chip package includes a substrate, a pad positioned on the substrate, a base board, at least one adhesive layer and at least one chip. The base board is positioned on the pad. At least one mounting hole is defined through the base board. The at least one adhesive layer is received in the at least one mounting hole. The at least one chip is received in the at least one mounting hole and adhere to the pad via the at least one adhesive layer.
| Chip-to-wafer bonding method and three-dimensional integrated semiconductor device|| 20130147059 || 20130613 |
| A chip-to-wafer bonding method and a three-dimensional integrated semiconductor device are provided. The method comprises providing a chip and a wafer having a bonding region of the same size and shape as the chip; preparing hydrophilic areas and hydrophobic areas on the chip; preparing in the bonding region hydrophilic areas and hydrophobic areas respectively corresponding to the hydrophilic and hydrophobic areas on the chip; adding a liquid drop onto the hydrophilic areas in the bonding region; and pre-aligning and placing the chip on the bonding region of the wafer, such that the hydrophilic areas on the chip each contacts the corresponding hydrophilic area in the bonding region via the liquid. The sum of perimeters of the hydrophilic areas on the chip is larger than a perimeter...|
| Method and apparatus to facilitate viewing television on a mobile device|| 20110016494 || 20110120 |
| An accessory to provide at least one of television and video streams to a mobile device is disclosed, comprising a circuit board having a semiconductor chipset, a tuner chipset and a host processor; a battery; and a connector capable of attaching the circuit board to a connector of the mobile device. Also, a method of viewing at least one of television and videos on a mobile device is described. The method includes detecting a digital television signal with a tuner chipset; transmitting a signal to a semiconductor chipset; demodulating and communicating a signal to a host processor; and communicating a signal to a mobile device for viewing.
| Method of performing static timing analysis considering abstracted cell's interconnect parasitics|| 20110016442 || 20110120 |
| An abstraction model supporting multiple hierarchical levels is inputted into a generalized static timing analysis of a hierarchical IC chip design to analyze and optimize the design of circuits integral to the chip containing a plurality of macro abstracts. An electrical network, synthesized for an internal abstract interconnect segment, is performed only once per macro and is applied to multiple instances of the macro abstract model in the IC chip design. The synthesized electrical network is a resistive capacitive or a resistive inductive capacitive network or a combination thereof. The synthesized electrical network is then used to match impulse response transfer functions of the network and the abstract interconnect segment's timing model. This network is stitched with the electrical parasitics of external interconnect segments connected to...|
| Scan-enabled method and system for testing a system-on-chip|| 20110016364 || 20110120 |
| Scan-enabled method and system for testing a system-on-chip (SoC). The method includes electronically determining a slack in a signal at each port of a core of the SoC. The SoC includes multiple cores. Each core includes input ports and output ports. The method also includes selecting flip-flops for each port if the slack does not exceed a slack threshold. Further, the method includes integrating a wrapper cell to each port for which the slack exceeds the slack threshold. Moreover, the method includes coupling integrated wrapper cells and selected flip-flops corresponding to the input ports to form at least one input scan chain for the core, and corresponding to the output ports to form at least one output scan chain for the core. The method also includes...|
| Chip lockout protection scheme for integrated circuit devices and insertion thereof|| 20110016326 || 20110120 |
| A system for implementing a chip lockout protection scheme for an IC device includes an on-chip password register that stores a password externally input by a user; an on-chip security block that generates a chip unlock signal, depending on whether the externally input password matches a correct password; an on-chip false data generator; an input protection scheme configured to gate the external data inputs to functional chip circuitry upon entry of the correct password; and an output protection scheme in communication configured to steer true chip data to external outputs of the IC device upon entry of the correct password, and to steer false data generated by the false data generator to the external outputs upon entry of an incorrect password. The false generated by the...|
| Rapid startup computer system and method|| 20110016270 || 20110120 |
| A computer system includes a north bridge chipset, a south bridge chipset, a memory, and a rapid startup apparatus. The rapid startup apparatus includes a DRAM module to install application programs or operation system programs, a battery, a control chip to control data reading and writing for the DRAM module, a PCI-E interface, and a switch circuit. The application programs or the operation system programs are loaded into the memory via the PCI-E interface, the south bridge chipset, and the north bridge chipset in series. The switch circuit processes voltage of the battery or the PCI-E interface and supply power to the DRAM module.
| Semiconductor device|| 20110016266 || 20110120 |
| On a single semiconductor package PK1, m semiconductor chips CP1 to CPm are mounted, and the semiconductor package PK1 has external terminals T shared by m pad electrodes PD1 to PDm of the m semiconductor chips CP1 to CPm. An electrostatic protection circuit CD is mounted on only one CPm of the m semiconductor chips CP1 to CPm.
| Storage and method for performing data backup using the storage|| 20110016262 || 20110120 |
| A method for performing data backup using a storage device starts a backup battery when an electronic device is powered off, reads data from a memory of the electronic device by a system on chip (SoC) of the storage device, and writes the data into a field programmable gate array (FPGA) of the storage device. The method further encodes the data by the FPGA, and stores the encoded data into a flash memory of the storage device.
| Multi-processor system and dynamic power saving method thereof|| 20110016251 || 20110120 |
| A multi-processor system and a dynamic power saving method thereof are provided. The multi-processor system includes a plurality of processors and a chipset. Each of the processors has a plurality of standard bus request pins and a specific bus request pin, and the standard bus request pins of each processor are alternately connected to the standard bus request pins of other processors respectively. The chipset is coupled to the specific bus request pins of the processors for detecting a control request signal on the specific bus request pins. When the chipset detects the control request signal, the chipset turns on an input buffer connected with the processors so that the processors can access data through the input buffer. When the chipset does not detect the control...|
| Method and system for addressing a plurality of ethernet controllers integrated into a single chip which utilizes a single bus interface|| 20110016245 || 20110120 |
| A method for processing network data is disclosed and may include receiving data via a single bus interface to which each of a plurality of Ethernet controllers are coupled, where the Ethernet controllers are integrated within a single chip. A particular one of the integrated Ethernet controllers may be identified based on information within the received data. The particular one of the integrated Ethernet controllers may be granted access to a shared resource within the single chip. The access to the shared resource may be granted using at least one semaphore register within the shared resource. The particular one of the integrated Ethernet controllers may be granted access to the single bus interface. The information may include a bus identifier, a bus device identifier and/or a...|
| Diagnosing system for diagnosing control device of vehicle-mounted equipment|| 20110015825 || 20110120 |
| A diagnosing system for diagnosing a control device of a vehicle-mounted equipment is provided, which has a chip of integrated circuit that stores a control program data for controlling the vehicle-mounted equipment, a control program data storage zone arranged in the chip and storing the control program data for controlling the vehicle-mounted equipment, a diagnosing data storage zone arranged in the chip and storing a diagnosing data that is provided by modifying the control program data and a data abnormality diagnosing section that detects an abnormality of the control program data by comparing the control program data with the diagnosing data.
| Architectures for an implantable medical device system|| 20110015705 || 20110120 |
| An improved architecture for an implantable medical device such as an implantable pulse generator (IPG) is disclosed. In one embodiment, the various functional blocks for the IPG are incorporated into a signal integrated circuit (IC). Each of the functional blocks communicate with each other, and with other off-chip devices if necessary, via a centralized bus governed by a communication protocol. To communicate with the bus and to adhere to the protocol, each circuit block includes bus interface circuitry adherent with that protocol. Because each block complies with the protocol, any given block can easily be modified or upgraded without affecting the design of the other blocks, facilitating debugging and upgrading of the IPG circuitry. Moreover, because the centralized bus can be taken off the integrated circuit,...|
| Means of tracking movement of bodies during medical treatment|| 20110015521 || 20110120 |
| Methods and systems enable accurate control of robotic treatments of internal features of a body by tracking movements of the exterior of the body. Such tracking enables programmed and automated or semi-automated surgical operations to compensate for movement of the patient's body during surgery. A tracking system that includes a marker, which may be disposable, that is attached to the body and accurately tracked in a three-dimensional coordinate system by a tracking system. Compensation for body movements may be accomplished by adjusting the movement or position of a surgical instrument, a surgical robot, a radiation source collimator and/or the operating room table. The markers may include a radiofrequency identifier (RFID) chip or memory chip that can be interrogated by the tracking system.
| Game betting device|| 20110014973 || 20110120 |
| The present application provides a game betting device, wherein each of antennas 21 belongs both two major groups, the major groups are further classified into a plurality of small groups, two major groups have different classifications of the small groups from each other, and at least one column or at least one row in the alignment of the betting regions includes a plurality of small groups included in an identical major group in a single column or row. The game betting device according to the present application makes it possible to read out a chip on a betting board in a short time.
| Rf reception system and integrated circuit with programmable filter and methods for use therewith|| 20110014888 || 20110120 |
| An integrated circuit includes an on-chip filter component that forms a programmable filter with the at least one off-chip filter component. An RF receiver generates inbound data in response to a received signal from the programmable filter.
| System and method for a single chip direct conversion transceiver in silicon|| 20110014880 || 20110120 |
| A direct conversion radio frequency (RF) transceiver integrated circuit (IC) is provided. The IC includes a local oscillator block, a receiver block, and a transmitter block disposed on a single silicon-based integrated circuit. Each of such blocks are connected to a ground plane that includes a metal located adjacent to each of such blocks, air gaps located between each section of the metal adjacent to such blocks, each section of the metal being connected to the adjacent section of metal in the group plane at a location on the edge of the ground plan corresponding to a point substantially equidistant from the two sections of metal. A system and method is provided for implementing a direct conversion integrated circuit architecture. A clock distribution system is provided,...|
| Convolutional impairment covariance estimation method and apparatus|| 20110014874 || 20110120 |
| Path delay information generated by a path searcher module of a wireless receiver is used to generate net channel coefficients for use in suppressing interference from a received signal. According to one embodiment, interference is suppressed from a signal transmitted over a communication channel including transmit and receive pulse shaping filters and a radio channel by generating net channel coefficients for the communication channel at processing delays such as G-Rake finger delays or chip equalizer tap delays. Medium channel coefficients are generated for the radio channel at estimated path delays as a function of the net channel coefficients. The net channel coefficients are regenerated at arbitrary delays as a function of the medium channel coefficients and an impairment covariance estimate is generated based at least in...|
| Vertically stackable sockets for chip modules|| 20110014802 || 20110120 |
| The socket system comprises a set of vertically-stackable sockets. A first socket mounts on a printed circuit board to receive a first chip module, and a second socket stacks on the first socket to receive a second chip module. The first socket includes a first set of embedded contacts to electrically connect the first chip module to the printed circuit board, and a second set of embedded contacts to electrically connect the second socket to the printed circuit board. The second socket includes a third set of embedded contacts to electrically connect the second chip module to the printed circuit board. System upgrades are enabled by replacing the chip modules.
| Method for processing a substrate, method for manufacturing a semiconductor chip, and method for manufacturing a semiconductor chip having a resin adhesive layer|| 20110014777 || 20110120 |
| A mask used when a semiconductor wafer is diced into individual semiconductor chips by plasma etching is formed as follows. First, a pattern of a liquid-repellent film is formed by printing a liquid-repellent liquid on the area to be etched on the rear surface of the semiconductor wafer. Next, a resin film thicker than the liquid-repellent film is formed in the area not having the liquid-repellent film by supplying a liquid resin to the rear surface on which the liquid-repellent pattern has been formed. Then, the resin film is cured to form the mask covering the area other than the area to be removed by the etching. This method allows the formation of an etching mask without using a high-cost method such as photolithography.
| Method for fabricating flip chip gallium nitride light emitting diode|| 20110014734 || 20110120 |
| The present invention discloses a method for fabricating a flip chip GaN LED, which has a predetermined region on an epitaxial layer for forming a first groove to expose a portion of the substrate, and another predetermined region on the epitaxial layer for forming a second groove to expose a portion of N type GaN Ohm contacting layer. On a side of the first groove, there are a translucent conducting layer, an N type electrode pad, a first isolation protection layer, a metallic reflection layer and a second isolation protection layer sequentially formed on the surface of a P type GaN Ohm contacting layer. On another side of the first groove, a translucent conducting layer, an N type electrode pad, a first isolation protection layer and...|
| Light-emitting module fabrication method|| 20110014732 || 20110120 |
| A light-emitting module fabrication method includes the steps of (a) forming component contacts and positive-bonding and negative-bonding contacts on a circuit layout on a substrate, (b) electrically bonding the pins of electronic components to the component contacts and P-electrode bonding pads and N-electrode bonding pads of light-emitting chips to the positive-bonding and negative-bonding contacts at the substrate, (c) employing a coating technique to cover light-emitting surfaces of each of the light-emitting chips with a respective phosphor layer, and (d) employing a curing technique to cure the phosphor layers.
| Thin film probe sheet and semiconductor chip inspection system|| 20110014727 || 20110120 |
| In the highly accurate thin film probe sheet which is used for the contact to electrode pads disposed in high density with narrow pitches resulting from the increase in integration degree of semiconductor chips and for the inspection of semiconductor chips, a large spatial region in which a metal film selectively removable relative to terminal metal is formed in advance is formed in the peripheral region around minute contact terminals having sharp tips and disposed in high density with narrow pitches equivalent to those of the electrode pads. Thus, occurrence of damage in an inspection process is significantly reduced, and an inspection device simultaneously achieving the miniaturization and the durability can be provided.
| Synthesis of peptide nucleic acids conjugated with amino acids and their application|| 20110014715 || 20110120 |
| This invention relates to a peptide nucleic acid (PNA) oligomer which is conjugated with one or more linear-type amino acid containing a plurality of alkyleneglycols and to a synthesis method thereof. In addition, this invention related to a linear amino acid spacer in a device for detection for detecting a target gene using the PNA oligomers which is fixed on a surface of a functionalized solid support. The linear amino acid spacer contains a plurality of alkyleneglycols and maintains enough space between the solid support and PNA oligomer in the device in order to prevent the interference of the interaction between the PNA oligomer and a target gene. Furthermore, this invention relates to a PNA array, a PNA chip and a gene diagnosis kit whereof sensitivity...|
| Reaction treatment apparatus and reaction treatment method|| 20110014619 || 20110120 |
| Provided is a reaction treatment apparatus in which, in a case of mixing a plurality of solutions in a microchip used in a biochemical reaction system, an electric field generation area for changing solute concentration distribution in the solutions is provided in a solution upstream fluid path. Diffusion between the solutions is accelerated by bringing an area with a high solute concentration into contact with another solution. This may shorten a time required for mixing the solutions.
| Microchip and method of manufacturing same|| 20110014422 || 20110120 |
| Provided are a microchip enabling accurate analysis by preventing a resin film from being deflected into a flow path groove to eliminate the stagnation of a liquid sample and a method of manufacturing the microchip. This microchip includes a flow path that is formed by joining a resin film onto the groove-formed surface of a resin substrate. The deflection angle of the resin film in the sectional surface of the flow path in the width direction is made to be 0 to less than 30° at respective positions of the flow path.
| Rotary cutting tool and cutting insert therefor|| 20110013995 || 20110120 |
| A cutting insert used in rotary cutting tools for performing turning spinning operations has an upper surface and an opposing base surface with a peripheral surface therebetween, the peripheral surface intersecting the upper surface to form a cutting edge. The cutting edge may be a continuous circular cutting edge. The upper surface has rotational asymmetry about an insert axis passing between the upper surface and the base surface, by virtue of having at least one spiral shaped protrusion with a chip deflection distance which continuously increases in a rotational direction about the insert axis for greater than 180°. The cutting insert is assembled to a cutting tool body having a shank portion and a cutting portion sharing a longitudinal axis, the insert axis being aligned with...|
| Image forming apparatus, process unit cartridge, and method of managing replacement life of process unit cartridge|| 20110013916 || 20110120 |
| An image forming apparatus includes: a process unit cartridge including an IC chip memory configured to store a set value table in which a set value as the replacement life of a process unit cartridge and a present value as the number of times of reuse are stored; a reader writer configured to read data from and write data in the IC chip memory; and a control unit configured to compare the set value and the present value readout from the IC chip memory and cause, when the present value exceeds the set value, a display unit to display indication that replacement is necessary.
| Command packets for personal video recorder|| 20110013887 || 20110120 |
| Command packets for a personal video recorder that provides for a transport stream (TS) that contains data and also includes a transport packet (TP)/TS formatted command packets. The TP/TS formatted command packet may be communicated between any number of devices, including multiple chips, multiple boards, and multiple processors. A decoder is able to decode the TP/TS formatted command packet and to perform the appropriate operation on data portions of the TS. When a TS is provided to a device not having the capability to perform the proper decoding of the TP/TS formatted command packet, that particular packet may be deemed as being unidentified (or unknown) adaptation field data. Alternatively, the packet may be identified as being corrupted data and/or irrelevant data.
| Method and system for pipelined processing in an integrated embedded image and video accelerator|| 20110013851 || 20110120 |
| A method and system for pipelined processing in an integrated embedded image and video accelerator is described. Aspects of a system for pipelined processing in an integrated embedded image and video accelerator may include circuitry that enables pipeline processing of video data within a single chip, wherein the pipeline processing may further include decoding of a block of video data while simultaneously inverse transforming a previously decoded block of video data. Aspects of the system may also include circuitry that enables transformation, within the single chip, of a block of said video data while simultaneously encoding, within said single chip, a previously transformed block of video data
| Mems microphone package and mehtod for making same|| 20110013787 || 20110120 |
| An exemplary micro-electro-mechanical systems (MEMS) microphone package includes a first substrate, a second substrate opposite to the first substrate, and a microphone chip disposed on the second substrate. First through holes are defined in the first substrate. Conductive material is disposed in each first through hole. A through hole is defined in the second substrate. Contact pads are disposed on the second substrate. Each contact pad connects the corresponding electrically conductive material in each first through hole. The microphone chip is surrounded by the contact pads. When sound waves transmit through the through hole in the second substrate to the microphone chip, the microphone chip converts sound into an electrical signal.
| Semiconductor laser device|| 20110013655 || 20110120 |
| In a semiconductor laser device a dual wavelength semiconductor laser chip is joined onto a submount, junction down, to reduce built-in stress produced between the laser chip and the submount and to decrease polarization angles of the two respective lasers. SnAg solder is used to join the dual wavelength semiconductor laser chip onto the submount. When joining, with respect to each of the two lasers, a ratio of a distance between the center line of a waveguide and an end, placed at a lateral side of the laser chip, of a portion joining the laser chip and the submount, to a distance between the center line of the waveguide and another end, placed toward the center of the laser chip, of the portion joining the laser...|
| System and method for an interactive broadband system-on-chip with a reconfigurable interface|| 20090328128 || 20091231 |
| A method and apparatus are disclosed, in an interactive broadband set-top box receiving broadband signals from a headend, to facilitate communications with an installed card within the set-top box using a single IC chip that processes the broadband signals. The single IC chip is configured to a PCMCIA PC-card mode such that PC card signals are multiplexed to certain I/O pins of the single IC chip. In the PCMCIA PC-card mode, the single IC chip attempts to detect the presence of and identify an installed card in the set-top box. If an installed card is present and is identified as a POD module, then the single IC chip is reconfigured from the PCMCIA PC-card mode to a POD mode such that POD-compatible signals are multiplexed to...|
| Distributed processing architecture with scalable processing layers|| 20090328048 || 20091231 |
| The present invention is a system on chip architecture having scalable, distributed processing and memory capabilities through a plurality of processing layers. In a preferred embodiment, a distributed processing layer processor comprises a plurality of processing layers, a processing layer controller, and a central direct memory access controller. The processing layer controller manages the scheduling of tasks and distribution of processing tasks to each processing layer. Within each processing layer, a plurality of pipelined processing units (PUs), specially designed for conducting a defined set of processing tasks, are in communication with a plurality of program memories and data memories. One application of the present invention is in a media gateway that is designed to enable the communication of media across circuit switched and packet switched networks....|
| Highly threaded static timer|| 20090327985 || 20091231 |
| Various methods and apparatus for executing a multithreaded algorithm that performs a static timing analysis of an integrated circuit chip (chip) include logic for traversing the chip to identify a plurality of components (cells or nodes) within a chip circuit of the chip. A waveform graph is defined for the identified nodes. One or more virtual graphs are generated from the waveform graph. The plurality of nodes in the one or more virtual graphs are processed using multiple threads to obtain quadruplet of time domain dataset values representing the different modes of propagation for each node. A timing check is performed at an end node of the virtual graphs using the quadruplet of time domain dataset values to determine any timing violation within the chip design.
| Predictive modeling of interconnect modules for advanced on-chip interconnect technology|| 20090327983 || 20091231 |
| A computer program product estimates performance of an interconnect structure of a semiconductor integrated circuit (IC). The program product includes code executing on a computer to calculate at least one electrical characteristic of the interconnect structure based on input data accounting for multiple layers of the interconnect structure. The electrical characteristics can be capacitance, resistance, and/or inductance. The capacitance may be based upon multiple components, including a fringe capacitance component, a terminal capacitance component, and a coupling capacitance component.
| Tachograph|| 20090327760 || 20091231 |
| A tachograph includes at least one chip card reading unit and, at least one chip card with secure memory. Secured data transmission can be fed to the at least one chip card reading unit. On the at least one chip card, at least one user-defined piece of identification information is securely stored which is independent of a specified piece of identification information for a specified operation of the tachograph. The tachograph is constructed so as to authenticate the at least one chip card in accordance with the at least one piece of user-defined identification information, and to read data securely from the at least one chip card and/or to store data securely on the at least one chip card.
| Enhancing security of a system via access by an embedded controller to a secure storage device|| 20090327678 || 20091231 |
| System and method for performing pre-boot security verification in a system that includes a host processor and memory, an embedded microcontroller with an auxiliary memory, e.g., an on-chip ROM, or memory controlled to prohibit user-tampering with the contents of the memory, and one or more pre-boot security components coupled to the embedded microcontroller. Upon power-up, but before host processor boot-up, the embedded microcontroller accesses the auxiliary memory and executes the program instructions to verify system security using the one or more pre-boot security components. The one or more pre-boot security components includes at least one identity verification component, e.g., a smart card, or a biometric sensor, e.g., a fingerprint sensor, a retinal scanner, and/or a voiceprint sensor, etc., and/or at least one system verification component, e.g.,...|
| Information handling system including a multiple compute element processor with distributed data on-ramp data-off ramp topology|| 20090327651 || 20091231 |
| A symmetric multi-processing (SMP) processor includes a primary interconnect trunk for communication of information between multiple compute elements situated along the primary interconnect trunk. The processor also includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The processor distributes data on-ramps and data off-ramps across the data lanes of a data trunk of the primary interconnect trunk to enable communication with compute elements and other structures both on-chip and off-chip.
| Circuit structure and method for digital integrated circuit performance screening|| 20090327620 || 20091231 |
| Disclosed is a semiconductor chip with a digital integrated circuit, such as a memory device (e.g., static random access memory (SRAM) arrays, dynamic random access memory (DRAM) arrays, content addressable memory (CAM) arrays, etc), that can be selectively operated in either a functional mode or in a performance screening mode. In the functional mode, a first signal supplied by an external signal generator is used to activate a first device in the circuit and, in response, a second device in the circuit outputs a data output signal. In the performance screening mode, a second signal is internally generated by an internal signal generator based on the data output signal. This second signal is then used to activate the first device in the circuit and, in response,...|
| Memory controller using time-staggered lockstep sub-channels with buffered memory|| 20090327596 || 20091231 |
| Memory control techniques for dual channel lockstep configurations are disclosed. In accordance with one example embodiment, a memory controller issues two burst-length 4 DRAM commands to two double-data-rate (DDR) DRAM sub-channels behind a memory buffer (e.g., FB-DIMM or buffer-on-board). The two commands are in time-staggered lockstep. The time-stagger allows data coming back from the two back-side DDR sub-channels to flow naturally on the host channel without conflict. Multiple DIMMs can be used to obtain chip-fail ECC capabilities and to reclaim at least some of the lost performance imposed by the burst-length of 4 s typically associated with dual channel lockstep memory controllers. The techniques can be implemented, for instance, with a buffered memory solution such as fully buffered DIMM (FB-DIMM) or buffer-on-board configurations.
| Detecting circuit for ieee 1394 device|| 20090327567 || 20091231 |
| An IEEE 1394 device detecting circuit includes a south bridge chip, a control device, an IEEE 1394 interface, and a resistor. The control device includes a power reset pin, a bus reset pin, and a cable power pin. The control device is connected to the south bridge chip through the bus reset pin, which is further connected to the power reset pin. The cable power pin is connected to a direct current power through the resistor. The control device is further connected to the IEEE 1394 interface, which is connected to an IEEE 1394 device.
| Mother-board|| 20090327559 || 20091231 |
| A mother-board includes a chipset, a switch, and first and second PCI Express X16 graphics interfaces. The switch has first and second switch circuits. The switch selectively turns on one of the first and second switch circuits according to a control signal. The first PCI Express X16 graphics interface has former eight lanes electrically connected to the chipset, and latter eight lanes selectively electrically connected to the chipset through the first switch circuit. The second PCI Express X16 graphics interface has former eight lanes selectively electrically connected to the chipset through the second switch circuit. When the first switch circuit is turned on, 16 lanes of the first PCI Express X16 graphics interface are electrically connected to the chipset. When the second switch circuit is turned...|
| System for and method of hand-off between different communication standards|| 20090327546 || 20091231 |
| An integrated chip for use in processing signals encoded in accordance with either one of at least two communication protocols comprises: reconfigurable architecture capable of being selectively arranged into different configurations, at least one configuration corresponding to each respective protocol so as to implement the functionality of the respective protocol with a predetermined complexity, and an intermediate configuration for implementing the hand-off between a first protocol and a second protocol. The intermediate configuration is arranged so as to simultaneously implement the basic functionality of both the first and second protocols during hand-off, and implementation of at least one of the protocols is of lesser complexity than of the corresponding predetermined complexity associated with separately implementing the other of the protocols. A wireless communication device which utilize...|
| Multiple die system status communication system|| 20090327539 || 20091231 |
| In one embodiment, the system status signal is arranged and configured as part of the data information content data packet structure carried between the suitably configured circuits. The system status signal comprises a collection of bit signals arranged and configured for indicating a status of a corresponding on-chip-interconnect access in the first of the suitably arranged circuits. The collection of bit signals in the second of the suitably arranged circuits are converted for updating in the second of the suitably arranged circuits the status change to the on-chip-interconnect accesses in the first of the suitably arranged circuits. The shared link is configured as a fragmented data interconnect link or as a high-speed synchronous serial interface link.
| Remote handler for off-chip microcontroller peripherals|| 20090327526 || 20091231 |
| A system for controlling a peripheral function, comprises a control device (100) having a programmable processing unit (110) programmable to generate a control command to initiate and control a desired peripheral function remote to the control device (100) and a first handling unit (130) configured by hardware means to convert a control command from the programmable processing unit (110) into a set of control parameters, and a peripheral device (200) having a peripheral function unit (250) configured by hardware means to perform the desired peripheral function based on the set of control parameters and a second handling unit (230) connected to the first handling unit (130) via a communications link (140, 240) and configured by hardware means to receive and detect the set of control parameters...|
| Non-optical mobile electronic transaction system, device and method therefor|| 20090327086 || 20091231 |
| Disclosed herein is a non-optical system, device and method for conducting electronic transactions utilizing a wireless communications device adapted to receive a transaction program and data. The device comprises memory storage for storing a transaction program, a microprocessor and a transponder chip. The microprocessor executes instructions contained within the transaction program to program a code segment on the transponder chip. The transponder chip transmits a signal representative of value upon detection of an activation signal. As disclosed herein, value is selected from the group consisting an identifier of a purchased good, an identifier of a purchased service, a coupon, a discount, a prepaid transaction, an electronic negotiable instrument, a sum from a credit account, and a sum from a debit account. The signal representative of value...|
| Software controlled lab-on-a-chip emulation|| 20090326903 || 20091231 |
| A software-controlled chemical process emulation system and environment having individually-addressable and/or group-addressable software-controlled chemical system processing modules, software-controlled chemical system handling modules, and related components. The software-controlled modules may be designed and interconnected to emulate various fixed, configurable, and reconfigurable “Lab-on-a-Chip” (“LoC”) devices. The software-controlled modules may be designed as separate units with well-defined ports and interfaces that can be used in the construction of larger systems. Alternatively, the software-controlled modules may be integrated into more complex subsystems that can be used in similar or other ways. These aspects may be used to design a LoC device, develop software for the operation of a LoC device, or may be used together with actual LoC devices as part of a larger system. Some applications may be used...|
| Integrated circuit design in optical shrink technology node|| 20090326873 || 20091231 |
| Disclosed is a system, method, and computer-readable medium for designing a circuit and/or IC chip to be provided using an optical shrink technology node. Initial design data may be provided in a first technology node and through the use of embedding scaling factors in one or more EDA tools of the design flow, a design (e.g., mask data) can be generated for the circuit in an optical shrink technology node. Examples of EDA tools in which embedded scaling factors may be provided are simulation models and extraction tools including LPE decks and RC extraction technology files.
| Multi-channel chemical transport bus for microfluidic and other applications|| 20090326720 || 20091231 |
| A controllable multiple-channel chemical transport bus routing and transport of fluids, gasses, aerosols, slurries and the like within a larger system. The system and methods are applicable for use in Lab-on-a-Chip (LoC) technology, and may be useful in the implementation of reconfigurable LoC devices. Routes through the bus are determined by control signals and/or sequences of control signals issued under algorithmic control. Several independent flows may occur simultaneously. Techniques for limiting cross-contamination are provided. Sensors may be placed at various locations along bus line segments and may be used in the control of measured flows or in clearing and/or cleaning operations. Adaptations of Clos, Banyan, and other related multi-stage architectures in the flow topology may also be accomplished.
| Fluidic capillary chip for regulating drug flow rates of infusion pumps|| 20090326517 || 20091231 |
| An erosion-resistant capillary chip for use with in an infusion pump that is made from a silicon substrate having a first surface that includes a micro groove etched therein and a glass plate laminated to the first surface. The glass plate covers the micro groove so that a micro fluid conduit is created. The glass plate includes an inlet bore that connects with the micro fluid conduit and the silicon substrate includes an outlet bore that connects with the micro fluid conduit so that a drug solution entering the inlet bore from the infusion pump may pass through the micro fluid conduit at a restricted flow rate to the outlet bore and thereafter to a target site of a patient. The micro groove includes a passivation...|
| System and method for visualizing tissue during ablation procedures|| 20090326320 || 20091231 |
| Systems for visualizing cardiac tissue during an ablation procedure are provided. In general, the systems include an imaging module configured to measure absorbance data at first and second wavelengths wherein the ratio of these absorbance values identifies the nature of the tissue (e.g., lesion, de novo tissue, etc.). The imaging module can also include a video system having at least two chips with corresponding bandpass filters centered at the first and second target wavelengths. The system can also include a processor and/or video monitor for combining the images produced by the various chips, determining treated and non-treated tissue based on the ratio of absorbance values at the target wavelengths, and displaying images of the treatment area. Methods of visualizing cardiac treatment areas during ablation procedures are...|
| Package and process for producing thermoplastic resin film|| 20090326160 || 20091231 |
| The compound is taken out of the bag and is then added to a thermoplastic resin which may be the same as or different from the thermoplastic resin as the main component of the bag to obtain a composition; and the composition is formed into a thermoplastic resin film. In this regard, no paper chip arises even if the bag containing the above-described compound is roughly opened with a cutter or the like, and thus, occurrence of fish eye gels in the film can be suppressed when the film is formed of the composition comprising the thermoplastic resin and the above-described compound.
| Auto-tuning system for an on-chip rf filter|| 20090325521 || 20091231 |
| A Radio Frequency Receiver on a Single Integrated Circuit (“RFSIC”) is described. The RFSIC may include a mixer, a phase-locked loop (“PLL”) in signal communication with the mixer, and an on-chip auto-tuned RF filter in signal communication with both the mixer and PPL, such that the same PLL simultaneously tunes the frequency of the VCO and the frequency response of the auto-tuned RF filter.
| Method for fine-pitch, low stress flip-chip interconnect|| 20090325348 || 20091231 |
| Attaching a semiconductor chip to a substrate by applying mechanical vibrations (150) to a polymeric compound (130) and the contacting areas (114, 124) of a first (113) and a second (121) metallic member immersed in the compound, while the two metallic members approach (140) each other until they touch. The mechanical vibration causes displacements of the first member relative to the second member, and the vibration includes displacements (150) oriented at right angles to the direction (140) of the approach. The polymeric compound (130) includes a non-conductive adhesive resin paste (NCP) and filler particles; the paste is deposited before the attaching step. The first member (113) is affixed to the chip and the second member (121) to the substrate.
| Semiconductor device and method of manufacturing the same|| 20090325346 || 20091231 |
| The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.
| Method of manufacturing layered chip package|| 20090325345 || 20091231 |
| A manufacturing method for a layered chip package including a stack of a plurality of layer portions includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure. The step of fabricating the layered substructure includes: fabricating a first and a second pre-polishing substructure; bonding the first pre-polishing substructure to a jig such that a first surface of the first pre-polishing substructure faces the jig; forming a first substructure by polishing a second surface of the first pre-polishing substructure; bonding the second pre-polishing substructure to the first substructure such that a...|
| Cellomics system|| 20090325215 || 20091231 |
| In labeling a cell, and separating and collecting the cell according to a degree of the labeling using a cell separator, effects on the cell is minimized and the use of the collected cell is facilitated, thereby, when labeling a cell, the cell is labeled in the state where interaction of each cell is retained. In the labeling, a specific labeling material present on a surface of a target cell is taken in the cell via a transporter, and the cell is dispersed one by one to separate the same with a cell separator. Immediately after the separation, the cell is put in a solution not containing the specific labeling substance to remove the specific labeling substance taken in the cell. This series of steps is...|
| Cheese products with form stability and deep-frying stability|| 20090324795 || 20091231 |
| The present invention relates to a novel cheese-containing heat-stable composition which can be fried. The composition can be produced using different cheese types and flavours. In addition to cheese, the use of maize and/or maize meal is essential in implementation of the invention. By varying the components, as required, products for different flavour directions, for example reduced-fat or else sweet or piquant etc., can be produced. The fried finished product can have the shape of chips and can also be used as a chip substitute. In the production, the components and the flavouring ingredients are melted in a suitable melting machine with intense stirring and brought into the desired shape. After cooling, a solid composition is formed which can then be fried and is heat stable.
| Fabrication of nio nanoparticles and chip-like nanoflakes by solvothermal technique|| 20090324486 || 20091231 |
| A method is disclosed for fabrication of NiO nanoparticles and NiO chip-like nanoflakes by solvothermal technique. Mixed organic alcohols were used as solvent to make a homogenous solution from a nickel containing salt (or complex) for production of NiO nanoparticles and chip-like nanoflakes. The solution was heated in a sealed flask sitting inside a warm furnace. The precipitate was filtered, rinsed, dried and calcined to produce nanoparticles or nanoflakes. The size of the particles was controllable by heating time and temperature. Similar procedures were used for production of both nanostructures except hydrogen peroxide addition to the initial solution for NiO chip-like nanoflakes fabrication.
| Splash guard of machine tool|| 20090324354 || 20091231 |
| A splash guard (25) of a machine tool for preventing chips generated when a workplace is machined by the machine tool or coolant from being scattered includes a rear cover (27) mounted on a rear of a bed (13) of the machine tool installed on the floor surface and defining a partition for a rear side of the machining area, and a front cover (29) defining a partition for a front side and lateral sides of the machining area. The front cover (29) is configured of a lower cover (31) placed on the bed (13) of the machine tool, and an upper cover (33) placed above the lower cover (31). The upper cover (33) has a plurality of legs (35) extending downward from the lower end...|
| Chio to chip optic alleys and method|| 20090324241 || 20091231 |
| A data link includes an ASIC. The data link includes a heat insulation layer in contact with the ASIC. The data link includes an optical transducer layer having a plurality of transducers, with each transducer of the plurality of transducers in communication with the ASIC. Each transducer converting optical signals to electrical signals or electrical signals to optical signals. The data link includes an optical waveguide layer having a plurality of waveguides for carrying optical signals. Each waveguide of the plurality of waveguides in optical communication with a transducer, the optical waveguide layer adjacent with the insulation layer. An apparatus for data. A method for transferring data.
|Method and structure for a pull test for controlled collapse chip connections and ball limiting metallurgy|| 20080313879 || 20081225 |
| A tensile strength testing structure for controlled collapse chip connections (C4) disposed above a substrate includes: a fixture base configured for positioning substrates with C4; a top fixture plate with through hole channels; test pins for insertion through the through hole channels; wherein dimensional tolerances of the substrates are accounted for with openings on at least two sides of the fixture base for positioning the substrates, and during alignment of the top fixture plate through hole channels with the C4 prior to securing the top fixture plate to the fixture base; wherein the test pins are strain hardened metal wires; wherein lower ends of the test pins are joined to the C4 during a solder reflow process; and wherein distal ends of the test pins are...|
|Apparatus and method for cutting produce in a continuous curl for the purpose of making a curly spiraled potato chip|| 20080314262 || 20081225 |
| An apparatus for manufacturing a curly sliced potato chip includes: a base frame; a cutting blade coupled to the base frame; and a rotatable threaded rod having a predetermined threaded pitch to which rod the potato is mounted. The rod is turned to rotate the potato while it is in a cutting position and to displace it toward or away from the cutting blade. A quick release engaging member has a threaded portion with a pitch compatible with the pitch of the rod. The member is fixed relative to the base frame and is selectively coupled with the threaded rod to selectively drive the potato mounted on the rod toward or away from the cutting blade as the rod is rotated. The potato is displaced toward...|
|Device for pressing on semiconductor chips arranged on a substrate|| 20080314264 || 20081225 |
| A device for pressing on semiconductor chips situated on a substrate comprises a substrate support and a tool movable in relation to the substrate support in a predetermined movement direction, which has multiple pressing plungers mounted so that they are displaceable in the movement direction of the tool for pressing on the semiconductor chips. The tool has a pressure chamber to which compressed air may be applied. All pressing plungers are situated along a straight line. Each of the pressing plungers has a bar running perpendicularly to the movement direction of the tool and perpendicularly to the cited straight line on its end facing toward the pressure chamber. Pistons are situated in the area between the pressure chamber and the pressing plungers, which are displaceable in...|
|Ic chip manufacturing method|| 20080314507 || 20081225 |
| The invention is a method for producing an IC chip, which comprises; at least a step 1 of fixing a wafer in a support plate by sticking the wafer to the gas generating agent-containing face of a pressure sensitive adhesive double-faced tape having a pressure sensitive adhesive layer containing a gas generating agent for generating a gas by light radiation in at least one face; a step 2 of grinding the wafer in a state of being fixed in the support plate through the pressure sensitive adhesive double-faced tape; a step 3 of radiating light to the pressure sensitive adhesive double-faced tape; and a step 4 of separating the pressure sensitive adhesive double-faced tape from the wafer, a gas releasing speed from the pressure sensitive adhesive...|
|Method and system for direct contact of hot liquor with wood chips in transfer circulation|| 20080314534 || 20081225 |
| A method for heating a chip slurry in a pulping system including an impregnation vessel and a chemical digesting vessel, the method including: impregnating chips in the impregnation vessel with a liquor; transporting the chips from the impregnation vessel to an upper elevation of the digester vessel; extracting liquor from a lower elevation of the digester vessel, wherein the extracted liquor has a temperature substantially higher than a temperature of the chips being transported to the upper elevation of the digester vessel, and adding extracted liquor from the lower elevation of the digester vessel to the chips being transported from the impregnation vessel to the digester vessel.
|Method and apparatus for chip cooling|| 20080314565 || 20081225 |
| In one embodiment, the invention is a method and apparatus for chip cooling. One embodiment of a system for cooling a heat-generating device, such as a semiconductor chip, includes a vaporization chamber for at least partially vaporizing a stream of liquid in a stream of a gas to produce a mixture of gas, vapor and liquid and a heat sink coupled to the vaporization chamber for transferring heat from the heat-generating device to the mixture.
|Parallel chip embedded printed circuit board and manufacturing method thereof|| 20080314621 || 20081225 |
| A parallel chip embedded printed circuit board and manufacturing method thereof are disclosed. With a method of manufacturing a parallel chip embedded printed circuit board, comprising: (a) forming a parallel chip by connecting in parallel a plurality of unit chips having electrodes or electrically connected members formed on the upper and lower surfaces thereof, using at least one conductive member; (b) joining an electrode on one side of the parallel chip to a first board; and (c) joining an electrode on the other side of the parallel chip to a second board, chips may be embedded in a printed circuit board at a low cost, as a plurality of unit chips can be embedded at once, and a mechanical drill or router can be used instead...|
|Electrophoretic separation of analytes by molecular mass|| 20080314751 || 20081225 |
| The present invention relates to a method and apparatus for the separation of analytes based on their molecular weight, by application of an electric field across a low-friction matrix that includes with a charged separation agent. The matrix comprises charged regions ordered in a monotonous sequence distributed throughout the matrix so as to generate a charge density gradient. When an external electric field is applied, the complex will move through the different charged regions and focusing of different analytes in different charge regions will occur. These systems are suitable for planar, capillary in-tube electrophoresis, as well as multi-channel arrays of capillaries filled with charge gradient gels, serial arrays of discrete compartments with charge density gradient, arrays in a chip format, pre-designed mass focusing arrays for specific...|
|Card data storage device with detector plate|| 20080314982 || 20081225 |
| The detector plate consists of a chip and a coupling loop inductively linked with the chip, wherein the coupling loop completely or partially surrounds an electrically non-conducting region of the card data storage device.
|Smart information carrier and production process therfor|| 20080314988 || 20081225 |
| A smart information carrier comprising a security element having two sides each side being laminated with at least one transparent polymer foil having a melting point higher than 150° C. so that the security element is surrounded by an edge at least 1 mm wide in which the at least one transparent polymer foil on each side of the security element are laminated to one another, the security element comprising an IC-module and a natural fibre-containing or synthetic fibre-containing continuous support exclusive of an antenna, the IC-module comprising an electronic chip and an antenna integrated therein, wherein the support is security printed on at least the side of the support nearer to the IC-module and the IC-module is at least substantially encapsulated with a transparent polymer...|
|Chip card and method for the production of a chip card|| 20080314990 || 20081225 |
| The invention pertains to a chip card and to a method for producing a chip card with a chip module that is contacted with an external contact arrangement arranged in the contact surface of a card body, as well as with an antenna device arranged in a card inlay, wherein the card inlay is initially produced in a first production device and the card inlay is subsequently provided with at least one respective external layer on both sides in a second production device, namely in such a way that the external contact arrangement arranged on the external contact side of the chip carrier is introduced into a recess of the assigned external layer, and wherein a connection between the card inlay and the external layers is...|
|Method for comminuting polymeric shaped articles by milling|| 20080315020 || 20081225 |
| The invention pertains to a method for comminuting a polymeric shaped article to particles having an average particle size smaller than 6 mm by using a grinding apparatus, characterized in that the shaped article prior to grinding is subjected to a milling step in a milling apparatus to substantially fully convert the shaped article into chips, after which the chips are fed into the grinding apparatus for further comminuting giving at least 25 wt. % less particles having a size less than 1 mm than obtained by the grinding step only.
|Analysis method of amino acid using mass spectrometer|| 20080315084 || 20081225 |
| A pretreatment method of samples, in which injections of samples are performed efficiently and precisely when amino acids are analyzed with a mass spectrometer, is provided. For the analysis method of samples including analyte comprising an amino acid, an amine and/or a peptide with mass spectrometry, the analyte is derivatized with a modification reagent, the derivative is subjected to a microchip electrophoresis, and then eluate from the microchip electrophoresis is introduced into a mass spectrometer.
|Method and apparatus for monitoring via's in a semiconductor fab|| 20080315195 || 20081225 |
| A method for monitoring a semiconductor fabrication process creates a wafer of semiconductor chips. Each chip has a one or more diodes. Each diode is addressable as part of an array, corresponds to a physical location of the chip, and is connected in series to a stack. The stack is composed of one ore more vertical interconnects and metal contacts. The diode and associated stack of vertical interconnects is addressed, and the current through each of the stacks of vertical interconnects in an array is measured.
|Technique for evaluating a fabrication of a die and wafer|| 20080315196 || 20081225 |
| The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter...|
|Semiconductor module|| 20080315215 || 20081225 |
| A semiconductor module (A1) comprises a semiconductor device (10) provided with a semiconductor chip, and a conductive cover (6) for electromagnetic shielding bonded to the semiconductor device (10) via an adhesive coat (8). The conductive cover (6) includes a surface facing the adhesive coat (8), and the surface is formed with a convex portion (6a) protruding toward the adhesive coat (8). Around the convex portion (6a), a space (7) is formed for filling in adhesive to form the adhesive coat (8).
|Cubic illuminators|| 20080315218 || 20081225 |
| An exemplary illuminator includes a first electrode, a second electrode, and a light-emitting chip. The light-emitting chip includes light-emitting layers arranged three-dimensionally. The first and second electrodes are configured for providing different voltages to the light-emitting chip, and the light-emitting chip is capable of emitting light simultaneously along all dimensional axes.
|Light-emitting diode arrangement|| 20080315227 || 20081225 |
| A light-emitting diode arrangement is disclosed, comprising at least one light-emitting diode (LED) chip with a radiation decoupling surface through which a large portion of the electromagnetic radiation generated in the LED chip exits in a main direction of emission; a housing laterally surrounding the LED chip; and a reflective optic disposed after the radiation decoupling surface in the main direction of emission. The LED arrangement is particularly well suited for use in devices such as camera-equipped cell phones, digital cameras or video cameras.
|Low profile side emitting led with window layer and phosphor layer|| 20080315228 || 20081225 |
| Low profile, side-emitting LEDs are described that generate white light, where all light is emitted within a relatively narrow angle generally parallel to the surface of the light-generating active layer. The LEDs enable the creation of very thin backlights for backlighting an LCD. In one embodiment, the LED emits blue light and is a flip chip with the n and p electrodes on the same side of the LED. Separately from the LED, a transparent wafer has deposited on it a red and green phosphor layer. The phosphor color temperature emission is tested, and the color temperatures vs. positions along the wafer are mapped. A reflector is formed over the transparent wafer. The transparent wafer is singulated, and the phosphor/window dice are matched with the blue...|
|Thin double-sided package substrate and manufacture method thereof|| 20080315239 || 20081225 |
| The present invention discloses a manufacture method for a thin double-sided package substrate, which includes steps: providing a carrier; respectively forming a first conductive layer and a second conductive layer on the upper and lower surfaces of the carrier; forming a through-hole penetrating the first conductive layer and the carrier but not penetrating the second conductive layer; setting a conductive element in the through-hole to electrically connect the first conductive layer with the second conductive layer; forming desired circuits on the first conductive layer and/or the second conductive layer; forming a first metal layer on the first conductive layer and/or the second conductive layer; and removing the carrier located in a predetermined region to form a chip receiving bay. The present invention also discloses a package...|
|Surface mountable chip|| 20080315241 || 20081225 |
| A surface mountable device having a circuit device and a base section. The circuit device includes top and bottom layers having a top contact and a bottom contact, respectively. The base section includes a substrate having a top base surface and a bottom base surface. The top base surface includes a top electrode bonded to the bottom contact, and the bottom base surface includes first and second bottom electrodes that are electrically isolated from one another. The top electrode is connected to the first bottom electrode, and the second bottom electrode is connected to the top contact by a vertical conductor. An insulating layer is bonded to a surface of the circuit device and covers a portion of a vertical surface of the bottom layer. The...|
|System, apparatus and method of selective laser repair for metal bumps of semiconductor device stack|| 20080315242 || 20081225 |
| Exemplary embodiments of the selective laser repair apparatus and method may allow the repair of metal bumps in a semiconductor device stack by applying a laser beam to a damaged and/or defective bump. Metal bumps may be repaired and individual chips and/or packages forming a device stack need not be separated. The operation of a control unit and a driving unit may position a laser unit such that a laser beam may be irradiated at the damaged and/or defective metal bump. An X-ray inspection unit may obtain information about the damaged and/or defective metal bump.
|Semiconductor device and power conversion device using the same|| 20080315257 || 20081225 |
| In a semiconductor device in which a diode and a high electron mobility transistor are incorporated in the same semiconductor chip, a compound semiconductor layer of the high electron mobility transistor is formed on a main surface (first main surface) of a semiconductor substrate of the diode, and an anode electrode of the diode is electrically connected to an anode region via a conductive material embedded in a via hole (hole) reaching a p+ region which is the anode region of the main surface of the semiconductor substrate from a main surface of the compound semiconductor layer.
|Packaged chip devices with atomic layer deposition protective films|| 20080315334 || 20081225 |
| A low-temperature inorganic dielectric ALD film (e.g., Al2O3 and TiO2) is deposited on a packaged or unpackaged chip device so as to coat the device including any exposed electrical contacts. Such a low-temperature ALD film generally can be deposited without damaging the packaged chip device. The ALD film is typically deposited at a sufficient thickness to provide desired qualities (e.g., hermeticity for the entire packaged chip device, passivation for the electrical contacts, biocompatibility, etc.) but still allow for electrical connections to be made to the electrical contacts (e.g., by soldering or otherwise) directly through the ALD film without having to expose the electrical contacts.
|Solid-state imaging device and method of fabricating the same|| 20080315340 || 20081225 |
| A solid-state imaging device includes a layer including an on-chip lens above a sensor section, and the layer including the on-chip lens is composed of an inorganic film which transmits ultraviolet light. The layer including the on-chip lens may further include a planarizing film located below the on-chip lens. A method of fabricating a solid-state imaging device includes the steps of forming a planarizing film composed of a first inorganic film, forming a second inorganic film on the planarizing film, forming a lens-shaped resist layer on the second inorganic film, and etching back the resist layer to form an on-chip lens composed of the second inorganic film. The first inorganic film constituting the planarizing film and the second inorganic film constituting the on-chip lens preferably transmit...|
|Empty vias for electromigration during electronic-fuse re-programming|| 20080315353 || 20081225 |
| The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to an e-fuse device including an opening, a first via and a second via in an interlayer dielectric, wherein the opening, the first via and the second via are connected to an interconnect below the interlayer dielectric; a dielectric layer that encloses the first via and the second via; and a metal layer over the dielectric layer, wherein the metal layer fills the opening with a metal, and wherein the first via and the second via are substantially empty to allow for electromigration of the interconnect during re-programming of the e-fuse device.
|Method for designing dummy pattern, exposure mask, semiconductor device, method for manufacturing semiconductor device, and storage medium|| 20080315365 || 20081225 |
| A method for designing a dummy pattern that is formed in a vacant section of a chip region before a semiconductor substrate including the chip region that has a device graphics data section in which a circuit element pattern is formed and the vacant section in which the circuit element pattern is not formed is planarized by a chemical mechanical polishing process, the method includes: setting an overall dummy section on the entire chip region; setting a mesh section on the entire overall dummy section; dividing the overall dummy section by the mesh section so that a plurality of rectangular dummy patterns is formed on the entire chip region after the mesh section is set; and removing or transforming a part of the rectangular dummy patterns,...|
|Semiconductor device and semiconductor package having the same|| 20080315369 || 20081225 |
| A semiconductor device having no voids and a semiconductor package using the same is described. The semiconductor device includes a semiconductor chip having a circuit section which is formed in a first area and a peripheral section which is formed in a second area defined around the first area, and an insulation layer covering the first and second areas and having at least one void removing part which extends from the first area to the second area to prevent a void from being formed.
|Methods and apparatus for emi shielding in multi-chip modules|| 20080315371 || 20081225 |
| Methods and structures provide a shielded multi-layer package for use with multi-chip modules and the like. A substrate (102) (e.g., chip carrier) has an adhesive layer (104), where electronic components (106, 108) are attached. An insulating layer (110) is formed over the plurality of electronic components, and a conductive encapsulant structure (115) is formed over the insulating layer. The adhesive layer is detached from the electronic components, and multi-layer circuitry (140) is formed over, and in electrical communication with, the plurality of electronic components. A shielding via (150) is formed through the multilayer circuitry such that it contacts the conductive encapsulant.
|Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system|| 20080315375 || 20081225 |
| Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through...|
|Assembling apparatus|| 20070294882 || 20071227 |
| An assembling apparatus is disclosed. The assembling apparatus includes a base, an assembling platform, and a driving part. The assembling platform and the driving part are fixed on the base. The assembling platform defines a receiving space for receiving a semiconductor chip module, a lever chamber for receiving clips of the semiconductor chip module, and a driving groove for connecting the receiving space and the lever chamber. The assembling platform further includes a lever bar removably placed in the lever chamber for expanding the clips. The driving part includes driving shafts. An end of each of the driving shafts is in the driving groove and is movable to pass through the lever chamber and reaches the receiving space. The assembling apparatus is used to assemble a...|
|Multilayer printed wiring board|| 20070295532 || 20071227 |
| A multilayer printed wiring board 10 includes: a build-up layer 30 that is formed on a core substrate 20 and has a conductor pattern 32 disposed on an upper surface; a low elastic modulus layer 40 that is formed on the build-up layer 30; lands 52 that are disposed on an upper surface of the low elastic modulus layer 40 and connected via solder bumps 66 to a IC chip 70; and conductor posts 50 that pass through the low elastic modulus layer 40 and electrically connect lands 52 with conductor patterns 32. The conductor posts 50 have the aspect ratio Rasp (height/minimum diameter) of not less than 4 and the minimum diameter exceeding 30 μm, and the aspect ratio Rasp of external conductor posts 50a,...|
|Apparatus for collecting and transporting coolant-lubricant contaminated with chips|| 20070295649 || 20071227 |
| An apparatus for collecting and transporting chip-contaminated coolant, including a trough-shaped channel arranged underneath or between machine tools and a filter apparatus or a recirculating pump station, with at least one opening being provided in a lower region of the channel. Above this opening is at least one fluid outlet, which is configured such that coolant or another fluid streaming through this opening and the fluid outlet accelerates the transport of liquid and/or solid materials in the channel.
|Wastebasket or bin having rocking springs at bottom|| 20070295736 || 20071227 |
| The paper shredder of this invention includes a machine body having cutting blades therein and a wastebasket or bin for containing paper chips, including a base provided beneath a wastebasket or bin; at least one support spring provided between the base and the wastebasket or bin to form an appropriate gap between the wastebasket or bin and the base, whereby when the user rocks the wastebasket or bin forwards and backwards, or sideways, chips in a chip mountain accumulated beneath the discharge port at the cutting blades can be spread outwards, to increase the space for receiving the paper chips in the wastebasket or bin, to prevent the “chip mountain” from impeding smooth falling of subsequent paper chips, thereby affecting overall operative functions of the paper...|
|Beverage dispenser with display and alarm|| 20070295748 || 20071227 |
| A measured quantity beverage dispenser that allows for numerous uses by using a disposable, replaceable pouch or cartridge prefilled with a specific quantity of beverage. The dispenser dispenses a unit measured quantity of beverage in response to activation of a trigger mechanism. An integrated circuit chip keeps track of the number of units dispensed and remaining and displays this information. An alarm alerts a user when the rate of dispensing falls below a certain preferred rate, e.g., 8 ounces every 20 seconds.
|Semiconductor device, manufacturing method and apparatus for the same|| 20070295786 || 20071227 |
| A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.
|Rocking wastebasket or bin for paper shredder|| 20070295842 || 20071227 |
| A rocking wastebasket or bin for paper shredder, including a machine body having cutting blades therein and a wastebasket or bin for containing paper chips, wherein the wastebasket or bin has a section of planar placement surface at a bottom thereof, and the planar placement surface is provided with arcuate faces between the planar placement surface and engagement portions at the bin walls, such that when the user rocks the wastebasket or bin forwards and backwards, or sideways, the chips in the chip mountain accumulated beneath the discharge port at the cutting blades can be spread outwards, so as to increase the space for receiving the paper chips in the wastebasket or bin, and to prevent the “chip mountain” from impeding smooth falling of subsequent paper...|
|Round undulating blade, blade module, and rotary assembly for shredder|| 20070295845 || 20071227 |
| The present invention relates to a round undulating blade for shredder, where a sheet metal is integrally formed into a round undulating blade to serve as the blades for constructing a blade module. The blade includes: a periphery; an undulating blade flank including at least two cambers having a first curvature and at least two cambers having a second curvature alternatively arranged with respect to the cambers having the first curvature; and hooked edges formed on the periphery of the cambers having the first curvature, wherein the undulating blade flank of the blade serves to cut paper along a longitudinal direction to form paper strips having double-tapering end, and the hooked edges serve to cut the strips along a horizontal direction into paper chips. These characteristics...|
|Semiconductor device structure for reducing mismatch effects|| 20070296013 || 20071227 |
| An integrated circuit chip includes a first electronic device, a second electronic device, and a common electrode feature. The first electronic device includes a first feature. The first electronic device has a first footprint area in a given layer. The second electronic device includes a second feature. The second electronic device has a second footprint area in the given layer. The first and second electronic devices are electrically matched. The common electrode feature is common to the first and second electronic devices. The common electrode is at least partially located in the given layer. More than a majority of the first footprint area overlaps with the second footprint area. A first spacing between the first feature and the common electrode feature is about the same as...|
|Integrated circuits having controlled inductances|| 20070296056 || 20071227 |
| An electronic device has a semiconductor chip (101) with a surface and an electric circuit including terminals on the surface. The circuit has a first (103) and a second terminal (104) with a metallurgical composition for wire bonding. The chip has a conductive wire (120) above the chip surface, which has a length and a first and a second end; the first end is attached to the first terminal and the second end to the second terminal. The wire is shaped to form at least one sequence of a concave and a convex portion. The sequence may be configured to form a loop, or multiple wire loops resulting in a spiraling wire coil. The number, shape, and spatial sequence of the loops control the electrical inductance...|
|3d electronic packaging structure having a conductive support substrate|| 20070296065 || 20071227 |
| The present invention provides a 3D electronic packaging unit having a conductive supporting substrate that can achieve multi-chip stacking through the signal contacts on the both sides of the unit. The packaging unit can be batched manufactured on wafers or substrates, and thus reduce the manufacturing cost of each individual packaging unit; moreover, the conductive supporting substrate can be utilized to provide signal transmission of the electronic elements, and the supporting substrate can be used as a ground terminal for the carried electronic elements to enhance electric performance of the electronic elements. The supporting substrate is also a good thermal conductor that can release effectively heat energy generated by the electronic elements and accumulated inside the package to the outside of the package along the substrate...|
|Bga semiconductor package and method of fabricating the same|| 20070296067 || 20071227 |
| A semiconductor package and a method of fabricating the same are provided. The semiconductor package includes a semiconductor chip and a circuit board. The semiconductor chip has a bond pad. The circuit board has a base substrate with a throughole, and a conductive film pattern placed on a sidewall of the throughole. The throughole is aligned with the bond pad to expose the bond pad. A connector located within the throughole electrically connects the conductive film pattern to the bond pad. A sealing layer covers the connector.
|In-situ monitoring and method to determine accumulated printed wiring board thermal and/or vibration stress fatigue using a mirrored monitor chip and continuity circuit|| 20070296068 || 20071227 |
| A monitoring system includes a monitor chip or chips soldered to a printed wiring board. By mirroring a function IC chip interface with the monitor chip, the consumed and remaining thermal/and or vibration-fatigue life of the function IC chip based on the life-environment actually experienced through monitoring of the monitor chip is readily determined. The monitor chip includes monitoring interconnections and/or circuitry which determines the number and/or location of failed-open solder terminations of the monitor chip.
|Semiconductor apparatus with decoupling capacitor|| 20070296069 || 20071227 |
| A lead frame type of semiconductor apparatus includes a die pad on which a semiconductor chip is mounted; ground terminals which are to be grounded; power supply terminals which are connected to a power supply; inner leads connected to the ground terminals and power supply terminals, in which a pair of adjacent inner leads for power supply terminal and ground terminal are extended inwardly; a chip capacitor mounting pad which is provided at inner ends of the extended inner leads; and a chip capacitor which is mounted on the chip capacitor mounting pad so that a decoupling capacitor is provided.
|Semiconductor package having functional and auxiliary leads, and process for fabricating it|| 20070296070 || 20071227 |
| A semiconductor package and a process for fabricating such a package are presented. The package has a substantially parallelepipedal block, made of an encapsulation material. Embedded within the block is at least one integrated-circuit chip and a leadframe having functional leads for electrical connection to said chip. These functional leads emerge on the outside of said block via at least one side and are intended to be connected to a printed-circuit board. The leadframe does not have functional leads on at least one of the other sides of said block. For that other side, the leadframe includes auxiliary leads for electrical connection to said chip which emerge on the outside of said block via at least one of the sides of this block which do not...|
|Semiconductor device and apparatus and method for manufacturing the same|| 20070296076 || 20071227 |
| The present invention provides a semiconductor device including: a semiconductor chip mounted on a substrate; a heat spreader provided above the semiconductor chip; and a sealing resin interposed between the semiconductor chip and the heat spreader and covering the semiconductor chip. The heat spreader is not in contact with any of the substrate and the semiconductor chip, and has an opening.
|Heat dissipating structure and method for fabricating the same|| 20070296079 || 20071227 |
| A heat sink package structure and a method for fabricating the same are disclosed. The method includes mounting and electrically connecting a semiconductor chip to a chip carrier, forming an interface layer or a second heat dissipating element having the interface layer on the semiconductor chip and installing a first heat dissipating element having a heat dissipating portion and a supporting portion onto the chip carrier. The method further includes forming openings corresponding to the semiconductor chip in the heat dissipating portion, and forming an encapsulant for covering the semiconductor chip, the interface layer or the second heat dissipating element, and the first heat dissipating element. A height is reserved on top of the interface layer for the formation of the encapsulant for covering the interface...|
|Semiconductor package and method of manufacturing the same|| 20070296081 || 20071227 |
| Disclosed is a semiconductor package and a method of manufacturing the same. The semiconductor package includes a semiconductor chip that includes metal pads provided on a predetermined area of an upper side of a semiconductor substrate, where element structures used to manufacture a semiconductor element are formed, and bump electrodes connected to the metal pads; and a passivation film that is provided on an entire surface of the semiconductor chip other than upper surface of the bump electrodes. Therefore, it is possible to avoid difficulties in performing an epoxy underfill process used in a conventional flip chip bonding, and complexity and high cost resulting from the use of a molding compound process and a solder ball process. It is also possible to prevent damages to the...|
|Semiconductor device and method for manufacturing semiconductor device|| 20070296087 || 20071227 |
| A semiconductor device includes a first semiconductor chip face-down mounted on a substrate, a second semiconductor chip face-up mounted on the first semiconductor chip, and an electromagnetic shielding plate interposed between the first semiconductor chip and the second semiconductor chip.
|Module composed of two light sources and generating tri-band white light with adjustable chromaticity diagram|| 20070296330 || 20071227 |
| The present invention relates to an improved structure of producing white light for LED, and the structure is a light emitting element composed of two chips of different color lights. The two chips are bonded with each other in series. In an epitaxial formation and manufacturing process, a first metal contact end is formed on the backside of the chip in the front and a second metal contact end is formed on the front side of the chip at the back, and the interfaces of the first and second contact ends are bonded by an eutectic solder, so that the two chips are electrically and mechanically coupled with each other. The invention simply uses a current to drive two chips to produce white light, and thus...|
|Switching regulator control circuit, current drive circuit, light emitting apparatus, and information terminal apparatus|| 20070296353 || 20071227 |
| A control circuit may include a first feedback input terminal which receives the cathode terminal voltage of light-emitting elements from a current driving circuit as a feedback signal. Such an arrangement controls the ON/OFF state of a switching element such that the cathode terminal voltage approaches a predetermined voltage. A second feedback input terminal may be included to receive the anode terminal voltage of the light-emitting elements as a feedback signal. Such an arrangement controls the ON/OFF state of the switching element such that the anode terminal voltage does not exceed a predetermined threshold voltage. A feedback output terminal may be included of the current driving circuit which allows the cathode terminal voltage of the light-emitting elements to be input to a control circuit for the...|
|Control method and control program for prober|| 20070296430 || 20071227 |
| To provide a control method and a control program of a prober that are capable of enhancing throughput. Chips are tested in step S2. In step S3, when the counted number Y of conforming chips has reached a predetermined number of conforming chips X which constitutes conditions for testing, the process advances to step S10. In step S10, testing of wafers taking place at that time is interrupted, and this wafer is stored in an output cassette OC1. In a subsequent step S11, the subsequent wafer is tested, and stored in the output cassette OC2 (step S12). When all wafers have been tested, the process advances to step S14, and testing of the lot is completed. As a result, wafers that remain untested and wafers that...|
|Semiconductor integrated circuit apparatus, measurement result management system, and management server|| 20070296440 || 20071227 |
| A semiconductor integrated circuit apparatus, and more particularly a technology for measuring and managing a physical amount of factors that exert an influence upon an operation of a semiconductor integrated circuit is provided; more particularly, a semiconductor integrated circuit that is an object of measurement, and a measurement circuit which measures a physical factor that exerts an influence upon the actual operation of the semiconductor integrated circuit, such as jitter or noise jitter, and noise of this semiconductor integrated circuit are provided on an identical chip; also, a measurement result of the measurement circuit of the present invention is analyzed, and is fed back to a circuit for adjusting the semiconductor integrated circuit that is the object of measurement.
|Semiconductor chip flipping assembly and apparatus for bonding semiconductor chip using the same|| 20070296445 || 20071227 |
| A semiconductor chip flipping assembly and an apparatus for bonding a semiconductor chip using the same are disclosed. In accordance with the semiconductor chip flipping assembly and the apparatus for bonding a semiconductor chip using the same, a front surface of a wafer is mounted in a wafer holder to face downward. Each of dies of the wafer is then pushed downward to a tray disposed therebelow, thereby eliminating a need for a separate flipping process of the semiconductor chip and two or more robot arms.
|Burn-in sorter and sorting method using the same|| 20070296448 || 20071227 |
| Provided is an apparatus for sorting burn-in tested packaged chips, including a DC test unit performing a DC test on packaged chips, a DC failure/loading head moving in a first direction to load packaged chips onto the DC test unit, and an inserting head moving in a second direction perpendicular to the first direction to transfer DC test-passed packaged chips from the DC test unit to a burn-in board, wherein the DC test unit is moved in the second direction, close to the DC failure/loading head when loading the packaged chips onto the DC test unit and close to the inserting head when transferring the packaged chips to the burn-in board, to sort burn-in tested packaged chips. The structure in which the DC test unit is...|
|Duplexer|| 20070296521 || 20071227 |
| The invention relates to a duplexer with a transmit-receive path, which branches on the output side into a receive path and a transmit path. The receive path is preferably designed on the input side for transmitting an asymmetric signal and on the output side for transmitting a symmetric signal. A receive filter, which operates with surface acoustic waves, is arranged in the receive path. A transmit filter, which operates with bulk acoustic waves, is arranged in the transmit path. The filters are preferably constructed as separate chips, which are mounted on a common carrier substrate.
|Chip type component and its manufacturing process|| 20070296542 || 20071227 |
| A chip-type component 11 includes an insulating chip substrate 12 whose upper surface is provided with a resistor element 13 and a cover coat 14 covering the resister film. At the opposite ends of the substrate, terminal electrode films 15, 16 are formed for the resistor element in a manner such that they extend onto the lower surface 12a of the insulating substrate. The lower surface 12a of the substrate is provided with an insulating projection 18 between the terminal electrode films, where the projection includes a peak portion 18a positioned at or near the center of the insulating substrate in a longitudinal direction along which the terminal electrode films are spaced from each other. This prevents the insulating substrate from breaking when the chip-type component...|
|Radio frequency identification tag and commodity|| 20070296555 || 20071227 |
| Disclosed herein is a radio frequency identification tag including, a substrate, an antenna provided at the substrate, the antenna formed by winding a conductor in a coil pattern around, and on a plane orthogonal to, a center axis of the substrate, the center axis extending in a direction parallel to the thickness direction of the substrate, a radio frequency identification chip attached to the substrate and operative to perform radiocommunication with a reader/writer apparatus through the antenna, and a package sealing the substrate and the antenna as well as the radio frequency identification chip therein, wherein a mark for specifying the center axis is formed on an outside surface where the package is exposed to the outside.
|Display panel module and radio frequency identification module applied thereto|| 20070296592 || 20071227 |
| A display panel module with a transparent radio frequency identification module is provided. The radio frequency identification module comprises a radio frequency identification chip and a transparent antenna electrically connected thereto. Since the antenna of the radio frequency identification module comprises transparent material, the antenna can be disposed on the surface of the display panel without views of the display panel being covered.
|Semiconductor device having a test-voltage generation circuit|| 20070296602 || 20071227 |
| A semiconductor device includes an internal power supply line, a first power supply circuit, and second power supply circuits. The first power supply circuit includes an ordinary-voltage generation circuit supplying an ordinary voltage to the internal power supply line during an ordinary operation, and a test-voltage generation circuit supplying a test voltage to the internal power supply line during a test operation. Each of the second power supply circuits includes only an ordinary-voltage generation circuit. The number of ordinary-voltage generation circuits is thereby larger than the number of test-voltage generation circuits. Therefore, the ordinary voltage such as the precharge potential can be stably supplied to the internal power supply line while suppressing an increase in chip area.
|Manufacturing method for a wireless communication device and manufacturing apparatus|| 20060288563 || 20061228 |
| A method for manufacturing wireless communication devices for use in tracking or identifying other items comprises a number of cutting techniques that allow the size of the antenna for the wireless communication device. Further, the chip for the wireless communication device is nested so as to be flush with the surface of the substrate of the wireless communication device. Rollers cut the tabs that form the antenna elements. In a first embodiment, a plurality of rollers are used, each on effecting a different cut whose position may be phased so as to shorten or lengthen the antenna element. In a second embodiment, the rollers are independently positionable to shorten or lengthen the antenna element.
|Pressure sensor|| 20060288793 || 20061228 |
| A pressure sensor for detecting a pressure and for outputting a signal based on the piezoresistance effect includes a substrate having a sensor chip on one side in a thin portion and a concave portion on another side, a piezo-resistor in the sensor chip, a pedestal being attached to the substrate and having a through hole for introducing the pressure to the sensor chip and a gel material filled in the concave portion and the through hole for protecting the sensor chip. A ratio of a diameter of the through hole to a thickness of the pedestal is substantially within a range between 1 and 3.
|Compressed coconut organic material smoking medium and fuel|| 20060288996 || 20061228 |
| SMOCONUT (with or without added wood chips) is produced by compressing processed coconut material into a compact solid dehydrated material. It is positioned primarily as smoking medium and alternative fuel for the following applications: COOKING, SMOKING and GRILLING OF FOOD. FUEL FOR WOOD FED FIREPLACE FUEL FOR WOOD FIRED BOILERS FUEL FOR KILNS FURNACES FUEL FOR ANY SIMILAR COOKING AND FUEL APPLICATIONS. SMOKING MEDIUM FOR AGRICULTURAL APPLICATIONS AS PEST CONTROL AND INSECT REPELLANT SMOKING MEDIUM FOR MEDICINAL APPLICATIONS
|Method for the manufacture of wood material boards in a pressing apparatus, and circulation apparatus for transport screens for the practice of the method|| 20060289105 || 20061228 |
| Method and apparatus for the production of wood material boards, such as chip boards or fiber boards, in a pressing apparatus with a single or multiple stage press and circulating carrier screens, with a loading basket for the carrier screens covered with mats of the material to be pressed, and an unloading basket for the carrier screens bearing the finished wood material boards, characterized in that the carrier screens are fed from the unloading basket in twos or more, the stripping devices separate the wood material boards alternately from the carrier screens, the carrier screens are brought back on separate conveyor lines to the screen entrance, and the carrier screens are introduced back into the screen entrance at one or more places.
|Method for bonding two solid planes via surface assembling of active functional groups|| 20060289115 || 20061228 |
| The present invention belongs to a bonding technical field of biochips or micromechanical electrical devices, more specifically, to a novel method for bonding two solid planes containing silicon, oxygen, metal or other elements at a moderate temperature via surface assembling of active functional groups. The method includes the steps of: (1) cleaning and hydroxylating solid planes of silicon plate, quartz or glass; (2) aminating a hydroxylated surfaces of the substrate; (3) forming a mono-layer or multi-layer assembled film with compound monomers having an active bi-functional or multi-functional group on an aminated substrate surface; and (4) contacting two solid planes with a assembled film having the same or different active functional groups on its surface tightly, and forming covalent bonds at an appropriate temperature, pressure and a...|
|Stacked microvias and method of manufacturing same|| 20060289202 || 20061228 |
| A flip chip package may include stacked vias in which the diameter D1 of the outermost via is less than the diameter D2 of the innermost via. The ratio D2/D1, for example, may be 1.5 to 2.
|Microchemical system|| 20060289309 || 20061228 |
| A microchemical system is disclosed that is capable of controlling the flow of a sample solution flowing through a channel in a microchip. In the microchemical system 1, a microchip 7 has therein a T-shaped channel 4 comprised of a main channel 2, a sub-channel 3, and a merging portion 4 where the main channel 2 and the sub-channel 3 merge together. Panel heaters 8 and 9 are installed in a position such as to be able to heat the interior of the sub-channel 3. The sub-channel 3 and the merging portion are subjected to hydrophobic modification treatment. Water is supplied into the main channel 2, and air is supplied into the sub-channel 3.
|Semiconductor memory card comprising semiconductor memory chip|| 20060289500 || 20061228 |
| A semiconductor memory card includes a circuit board and a cover case. The circuit board has a semiconductor memory chip on one surface and an electrode on the other surface. The cover case has a first storage section on one surface. The first storage section contains the semiconductor memory chip, and the circuit board is attached to the cover case by use of an adhesive material. A second storage section different from the first storage section is formed around the first storage section. The second storage section is located at a peripheral portion of the circuit board.
|Composite solder transfer moldplate structure and method of making same|| 20060289607 || 20061228 |
| A method for constructing a composite solder transfer moldplate for flip chip wafer bumping of a substrate, comprising the steps of coating at least one polymer layer onto a first side of a transparent plate, the plate having a thermal expansion coefficient similar to that of the substrate; and forming a multiplicity of cavities in a polymer layer on one side of the plate, each cavity being for receiving solder. A moldplate made by the method. The structure has required behavior through temperature excursions between room temperature and various solder molten temperatures.
|Portable electronic apparatus and data output method therefor|| 20060289656 || 20061228 |
| In an IC card, the value of a monitoring flag is set to an initial value which serves as a predetermined value when all processes corresponding to commands for outputting data are normally performed, in a memory of an IC chip. The value of the monitoring flag is set depending on the execution states of the various processes corresponding to the commands for outputting the data. When the processes prior to data output are completed, data to be output is masked on the basis of the value of the monitoring flag, and the masked data is output using a communication interface.
|Processor circuit and method of allocating a logic chip to a memory chip|| 20060289658 || 20061228 |
| A processor circuit includes a logic chip with a logic circuit and a non-volatile memory as well as a memory chip with a non-volatile memory. A key is stored in the non-volatile memory of the logic chip by using electronic fuses. Further, personalization information is stored, which signalizes that the logic chip is allocated to a memory chip. A chip identification encrypted with the key is stored in the memory chip at an ID memory area. During starting up the processor, it is first verified whether the encrypted logic chip identification stored in the memory chip is authentic or not. Thereby, a simple and inexpensive personalization of a memory chip to a logic chip can be obtain in order to ward off attacks with regard to...|
|Storage device|| 20060289659 || 20061228 |
| In a memory card including an IC card chip which can store and execute an application program, a flash memory chip which can store confidential data relating to the application program, and a controller chip which is connected to the chips, the IC card chip performs verification of a host apparatus, and the controller chip permits transmission of the confidential data between the flash memory chip and the host apparatus when the host apparatus is authenticated through the verification.
|Macro-placement designing apparatus, program product, and method considering density|| 20060289750 || 20061228 |
| According to an embodiment of the invention, a pattern density checking program product for causing a computer including a storage unit prestoring chip data about a pattern density check target chip and mask data of the chip to execute a pattern density checking process, includes: a first step of reading the mask data and creating a scribing frame model having a data ratio of a scribing frame corresponding to one density check target chip based on the mask data; and a second step of reading the chip data and executing a density check for one chip including the chip data and the scribing frame model.
|Optoelectronic semiconductor component with high light-emitting efficiency|| 20060289812 || 20061228 |
| An optoelectronic semiconductor component includes a housing including a light exit opening, a first semiconductor chip installed inside the housing for emitting light, and a second semiconductor chip located at a position inside the housing. A distance between the second semiconductor chip and the light exit opening is greater than a distance between the first semiconductor chip and the light exit opening.
|Systems and methods for thermal sensing|| 20060289862 || 20061228 |
| Systems and methods for positioning thermal sensors within an integrated circuit in a manner that provides useful thermal measurements corresponding to different parts of the integrated circuit. In one embodiment, an integrated circuit includes multiple, duplicate functional blocks. A separate thermal sensor is coupled to each of the duplicate functional blocks, preferably in the same relative location on each of the duplicate functional blocks, and preferably at a hotspot. One embodiment also includes thermal sensors on one or more functional blocks of other types in the integrated circuit. One embodiment includes a thermal sensor positioned at a cool spot, such as at the edge of the integrated circuit chip. Each of the thermal sensors may have ports to enable power and ground connections or data connections...|
|Light-emitting diode|| 20060289885 || 20061228 |
| A light-emitting diode (LED) is described. The light-emitting diode has a light-emitting diode chip and a package structure covering the light-emitting diode chip. A surface of the package structure has a pattern structure, in which the pattern structure includes a plurality of stria structures for controlling a light shape output by the light-emitting diode.
|Packaging of smd light emitting diodes|| 20060289888 || 20061228 |
| An SMD LED package with superior thermal dissipation capability is provided. The SMD LED package comprises a supporting block with circuit patterns and at least one LED attached to the supporting block. Wherein, circuit patterns of holes/vias, insulating layers, and conducting traces/pads are formed on and in the supporting block. The SMD LED packages can be further assembled to from a light module that allows emitted lights to travel in parallel with the mounting surface. The SMD manufacturing process is a mature production process and thus easy for mass production. Single or plural LED chips are mounted on a thermal conducting block that is disposed with patterns of conducting traces/pads and isolating dielectric layers. The side emitting characteristics of the present invention offers the advantage of...|
|Method for preparing light emitting diode device having heat dissipation rate enhancement|| 20060289892 || 20061228 |
| A method for fabricating an LED having section grown on a sapphire substrate, a boded structure, and a unit chip separated from the bonded structure. The method includes (a) bonding the section grown on a first surface of the sapphire substrate to a first surface of a first substrate with a first binder; (b) bonding a second surface of the first substrate to a first surface of a second substrate with a second binder; (c) removing the second substrate from a bonded structure obtained as a result of step (b) after polishing a second surface of the sapphire substrate; (d) separating the bonded structure into unit chips after the second substrate has been removed; and (e) bonding the second surface of the polished sapphire substrate provided...|
|Magnetic shielding of mram chips|| 20060289970 || 20061228 |
| An apparatus comprising a magnetically shielded MRAM chip and a method of manufacturing the same. The apparatus includes an MRAM module and a protective cover. The MRAM module includes a circuit board and a memory chip attached to the circuit board, the memory chip containing magnetoresistive random access memory (MRAM) cells. The protective cover includes a magnetic shielding material and at least partially encloses the memory chip. In another embodiment, the protective cover shields the memory chip without shielding at least a portion of the circuit board.
|Semiconductor device having firmly secured heat spreader|| 20060289971 || 20061228 |
| A semiconductor device comprising a leadframe (903), which has first (903a) and second (903b) surfaces, a planar pad (910) of a certain size, and a plurality of non-coplanar members (913) adjoining the pad. The device further has a heat spreader (920) with first (920a) and second (920b) surfaces, a planar pad of a size matching the leadframe pad size, and contours (922), into which the leadframe members are inserted so that the first spreader pad surface touches the second leadframe pad surface across the pad size. A semiconductor chip (904) is mounted on the first leadframe pad surface. Encapsulation material (930), preferably molding compound, covers the chip, but leaves the second spreader surface uncovered.
|Lead frame for semiconductor package|| 20060289973 || 20061228 |
| A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include recesses within the bottom surface thereof which create regions of reduced thickness. A semiconductor chip bonded to the chip mounting board may be electrically connected to leads of the lead frame and to the ground ring via conductive wires. Those conductive wires extending to the ground ring are bonded to the top surface thereof at locations which are not aligned with the recesses within the bottom surface, i.e., those regions of the ground ring of maximum thickness.
|Bridge modules for smart labels|| 20060289979 || 20061228 |
| The invention relates to module bridges for smart labels for positioning chip modules (5) on carries (12) and for the bridging connection of connection elements of the chip modules (5) to connection elements (11a, 11b) of antenna elements (11) arranged on or in the carriers (12), a plurality of module bridges (10) are arranged one behind the other on a carrier strip (1), wherein the carrier (1) has a plurality of depressions (2) arranged one behind the other for respectively receiving a chip module (5) assigned to a module bridge (10) and printed contact layers (7a, 7b), which cover the connection elements of the chip modules (5), with increased dimensions compared to the dimensions of the connection elements.
|Stacked memory card and method for manufacturing the same|| 20060289980 || 20061228 |
| A structure of stacked memory card, the structure includes a substrate, a lower chip, wires, adhered element, upper chip, and compound resin. The substrate has an upper surface formed with a plurality of first electrodes, and a lower surface. The B-stage glue is coated on the upper surface of the substrate. The lower chip is arranged on the upper surface of the substrate, and is located on the B-stage glue. The plurality of wires are electrically connected the lower chip to the first electrode of the substrate. The adhesive element includes adhesive agent and filling elements is coated on the lower chip. The upper chip is adhered on the lower chip by adhesive element, and is spaced with the lower chip through the filling element, then...|
|Apparatus and method for high density multi-chip structures|| 20060289990 || 20061228 |
| Devices and methods are described including a multi-chip assembly. Embodiments of multi-chip assemblies are provided that uses both lateral connection structures and through chip connection structures. One advantage of this design includes an increased number of possible connections. Another advantage of this design includes shorter distances for interconnection pathways, which improves device performance and speed.
|Multi-level interconnections for an integrated circuit chip|| 20060289994 || 20061228 |
| Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connection for the second contact vertically from the chip, overlapping the planes and fingers of the metallization layouts to the first and second elements and forming a pyramid or staircase of multilevel metallization layers to smooth diagonal current flow.
|Interconnection device including one or more embedded vias and method of producing the same|| 20060289995 || 20061228 |
| Briefly, some demonstrative embodiments of the present invention include an interconnection device, e.g., a Systems In Package (SIP) device, or Systems In Chip (SIC) device, including one or more embedded vias. Some demonstrative embodiments of the invention include a process to produce the interconnection device. Other embodiments are described and claimed.
|Semiconductor device and a method of manufacturing the same|| 20060289998 || 20061228 |
| A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.
|Semiconductor device|| 20060290004 || 20061228 |
| In the case where a first semiconductor chip 100 and a second semiconductor chip 200 are stacked, both the semiconductor chips 100 and 200 are connected using micro bumps, in which a circuit block in the first semiconductor chip and a circuit block in the second semiconductor chip are connected by the micro bumps, and the circuit block in the second semiconductor chip is also connected to the external electrode by the micro bumps through the first semiconductor chip. Further, micro bumps 121, 221 that connect circuit blocks 101, 102, 103, 104 and 210 of both the semiconductor chips 100, 200 and the micro bumps 122, 222 that connect the circuit block 210 in one chip 200 to an external electrode are arranged in different positions.
|Multi-chip device and method for producing a multi-chip device|| 20060290005 || 20061228 |
| The present invention relates to a multi-chip device comprising a substrate having a first surface on which a number of first contact elements is provided, a plurality of integrated circuit chips arranged in a chip stack which is arranged on a second surface of the substrate opposing the first surface, wherein each of the chips having a surface on which a number of second contact elements are provided, wherein a first one of the chips and the second contact elements thereon is arranged such that its second contact elements are uncovered by any of the chips or by the substrate and face towards the second surface of the substrate; and connecting elements which are arranged such as to connect at least one of the first contact...|
|Flip chip die assembly using thin flexible substrates|| 20060290007 || 20061228 |
| Apparatus and methods for flattening thin substrate surfaces by stretching thin flexible substrates to which ICs can be bonded. Various embodiments beneficially maintain the substrate flatness during the assembly process through singulation. According to one embodiment, the use of a window frame type component carrier allows processing of thin laminates and flex films through various manufacturing processes. The flexible substrate is bonded to a rigid carrier. The carrier is placed into a specialized fixture comprising a bottom plate and a top plate. The bottom plate with raised regions is created that allows the windowed region of the flex film to be pressed flat. After aligning the top plate, the bottom plate, and the middle structure, the plates are pressed together causing the raised regions to push...|