|| List of recent Chip-related patents
| Integrated circuit (ic) chip and method of verifying data thereof|
Provided are an ic chip and a method of verifying data thereof. The present invention verifies integrity of data by comparing an integrity verifying value generated from data using an integrity verifying value generating algorithm before a write operation for storing data in a storing unit is performed and an integrity verifying value generated from data stored in the storing unit using the integrity verifying value generating algorithm after the write operation is completed.
| Memory system and constructing method of virtual block|
According to one embodiment, a virtual block is constructed according to configuration conditions that, when a plurality of physical blocks included in the virtual block are selected, the sum of the number of physical block pairs and the number of single blocks allocated from the same memory chip to one virtual block is less than or equal to a first value.. .
| Semiconductor chip and semiconductor device|
When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy..
| System and memory module|
A system includes: a controller, a first memory module connected to the controller through a first data bus, and a second memory module connected to the controller through a second data bus, wherein the first memory module includes: first and second memory chips; a first data terminal connected to the first data bus, and a first switch unit that electrical connects the first data terminal with either the first memory chip and the second memory chip, and the second module includes: third and fourth memory chips; a second data terminal connected to the second data bus, and a second switch unit that switches over electrical connection of the second data terminal with either the third memory chip or the fourth memory chip.. .
| Dual-use light fixture having ac and dc leds|
A dual-use light fixture having ac and dc leds includes a heat-dissipating housing, a printed circuit board located on a first end of the heat-dissipating housing, ac and dc led chips located on the printed circuit board, and a power supply pedestal coupled to a second end of the heat-dissipating housing. The power supply pedestal includes an ac plug, a dc driving unit, and a thread connector.
| Low-height multilayer ceramic capacitor|
A low-height multilayer ceramic capacitor offering excellent flexure strength meets the condition “t11c<t12b,” where t11c represents the thickness of each protective dielectric layer provided on respective top and bottom sides of a dielectric chip, and t12b represents the thickness of a wraparound part of each external electrode provided at least part of both top and bottom faces of the dielectric chip.. .
| Light-emitting diode module and method for operating a light-emitting diode module|
In at least one embodiment of the led module (10), said led module comprises a first led chip (1) that is based on the alingan material system and designed to emit a first radiation type in the blue spectral range. Furthermore, the led module (10) comprises at least one second led chip (2) that is based on the ingaalp material system and designed to emit a second radiation type in the red spectral range.
| Method of manufacturing semiconductor device, and semiconductor device|
Provided is a semiconductor device with improved reliability. A logic chip (first semiconductor chip) and a laminated body (second semiconductor chip) are stacked in that order over a wiring substrate.
| Multi-chip semiconductor power device|
A semiconductor device includes a first semiconductor power chip mounted over a first carrier and a second semiconductor power chip mounted over a second carrier. The semiconductor device further includes a contact clip mounted over the first semiconductor power chip and on the second semiconductor power chip.
| Solid-state imaging device|
A solid-state imaging device includes a pixel chip, a logic chip and one or more shielding layers. The one or more shielding layers are arranged between or within the pixel chip and/or the logic chip to shield or reduce the effect of electromagnetic interference, radiation generated noise, or electromagnetic waves generated in one portion of the solid-state imaging device from affecting another portion of the solid-state imaging device..
| Booklet processing unit|
According to one embodiment, a booklet processing unit is disclosed. It includes a conveyance means for conveying a booklet containing an ic chip along a conveyance way; a printing means for printing a first particular information in the booklet; a recording means for recording a second particular information on the ic chip; a distinguishing means for distinguishing the quality of the printing state of the booklet and a recording state of the ic chip; and a marking means which moves a marking component and marks the booklet when the booklet is identified as being in a poor state by the distinguishing means such that the ic chip is avoided by the marking..
| Concentrating photovoltaic chip assembly, method for manufacturing the same, and concentrating photovoltaic assembly with same|
A concentrating photovoltaic chip assembly includes an upper lead frame, a lower lead frame for supporting electronic components, a photovoltaic chip for converting solar energy into electric energy, and a protective diode for protecting the photovoltaic chip from short-circuiting. A light inlet window is defined in the upper lead frame.
|Common template for electronic article|
One or more techniques or systems for incorporating a common template into a system on chip (soc) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor.
|Bus protocol checker, system on chip including the same, bus protocol checking method|
A system on chip (soc) includes a system bus; a plurality of intellectual properties (ips) outputting bus signals via the system bus; and one or more checkers disposed to correspond to at least some of the plurality of ips, wherein the checker includes: a first environment setting register for setting information about a check target and list, on which a bus protocol check operation will be performed, wherein the setting may be variable according to an access from outside via the system bus; and a check logic receiving the bus signal and performing a bus protocol check operation on a signal included in the bus signal according to the information set in the first environment setting register.. .
|Local repair signature handling for repairable memories|
A method is disclosed for independent repair signature load into a repairable memory within a chip set of a design without halting operation of other repairable memories within the design. At initial power up, the repair signature is received from nonvolatile memory and parallelly stored within a memory repair register and within a local memory repair shadow register.
|Phy based wake up from low power mode operation|
Apparatus and method for supplying electrical power to a device. A system on chip (soc) integrated circuit includes a first region having a processing core and a second region characterized as an always on domain (aod) power island having a power control block with an energy detector coupled to a host input line.
|Storing system data during low power mode operation|
Apparatus and method for operating a device in a low power mode. In accordance with some embodiments, the apparatus comprises a memory and a system on chip (soc) integrated circuit.
|Method of implementing magnetic random access memory (mram) for mobile system-on chip boot|
A method of booting a system on chip (soc) includes using an on-chip mram located in the soc, to store a boot software that includes a start-up software, boot loaders, and kernel and user-personalized information in an on-chip magnetic random access memory (mram) located in and residing on the same semiconductor as the soc. The method further includes directly executing the boot software from the on-chip mram by the soc and directly accessing the user-personalized information from the mram by the soc..
|Storage system and method of control for storage system|
The storage system includes a plurality of storage devices and a storage controller. The storage controller stores a data request quantity indicating the data quantity of write data written to the target area in a specific period, and estimates, based on the quantity of request data and relationship information received from storage devices, the estimated data quantity written to the nonvolatile semiconductor memory chips based on the write data written to the target area in the specific period.
|Non-volatile semiconductor storage apparatus|
According to one embodiment, apparatus includes non-volatile memory chips, and a first controller which executes processing for reading first valid data stored in a first storage region of a first non-volatile memory chip in the non-volatile memory chips, processing for storing the first valid data in a buffer memory, processing for writing the first valid data stored in the buffer memory in a second storage region of the first non-volatile memory chip, and processing for erasing data stored in the first storage region. Each of the non-volatile memory chips comprises erase blocks.
|Memory system, memory controller and method|
According to one embodiment, a memory system includes a plurality of non-volatile memory chips and a memory controller. The memory controller controls a read operation of the memory chips, and manages correspondence relation information between a logical address included in a read command and a physical address of the memory chip.
|Remote electromigration monitoring of electronic chips|
A method of remotely monitoring electromigration in an electronic chip includes sensing, at a first location, at least one temperature value of the electronic chip, sending the at least one temperature value to a remote monitoring system, accumulating a plurality of temperature values of the electronic chip at the monitoring system during a reporting period, calculating an electromigration life consumed (emlc) value of the electronic chip for the reporting period based on the plurality of temperature values, determining whether the emlc of the electronic chip is above a predetermined threshold, and providing a signal when the emlc of the electronic chip is above the predetermined threshold.. .
|Method for forming reram chips operating at low operating temperatures|
Forming a resistive memory structure at a temperature well above the operating temperature can reduce the forming voltage and create a defect distribution with higher stability and lower programming voltages. The forming temperature can be up to 200 c above the operating temperature.
|Method for forming biochips and biochips with non-organic landings for improved thermal budget|
The present disclosure provides biochips and methods of fabricating biochips. The method includes combining three portions: a transparent substrate, a first substrate with microfluidic channels therein, and a second substrate.
|System for high throughput sperm sorting|
This disclosure relates to a system for sorting sperm cells in a microfluidic chip. In particular, various features are incorporated into the system for aligning and orienting sperm in flow channels, as well as, for determining sperm orientation and measuring relative dna content for analysis and/or sorting..
|Device for high throughput sperm sorting|
This disclosure relates to a device in the form of a microfluidic chip. In particular, various features are incorporated into the microfluidic chip for aligning and orienting sperm in flow channels, as well as for separating selected subpopulations of sperm..
|Methods for high throughput sperm sorting|
This disclosure relates to methods for sorting sperm cells in a microfluidic chip. In particular, various steps are incorporated to align and orienting sperm in flow channels, as well as, to determining sperm orientation and measure relative dna content for analysis and/or sorting..
|Surface modification, functionalization and integration of microfluidics and biosensor to form a biochip|
The present disclosure provides methods of fabricating a biochip. The biochip includes a fluidic part, having through-substrate holes as inlets and outlets, and a sensing part bonded together using a bonding material.
|Optical waveguide network of an interconnecting ic module|
The subject matter disclosed herein relates to a photonic module comprising: a silicon-on-insulator (soi) wafer; one or more photonic components on the soi wafer; a plurality of metal pads to receive integrated circuit (ic) chips to be mounted on the soi wafer; silicon optical waveguides to transfer optical signals among terminals of individual the ic chips, wherein the silicon optical waveguides comprise portions of the soi wafer; and silica optical waveguides to transfer optical signals among terminals of different the ic chips.. .
|Photonic multi-chip module|
The subject matter disclosed herein relates to a photonic module comprising: a plurality of metal pads to receive cmos integrated circuit (ic) chips to be mounted on a silicon-on-insulator (soi) wafer; electrical interface circuits to receive electrical signals from the cmos ic chips and to modify the electrical signals; optical drivers to receive the modified electrical signals and to convert the modified electrical signals to optical signals; and a photonic layer on the soi wafer comprising silicon optical waveguides and silica optical waveguides to transmit or receive the optical signals for communication among the cmos ic chips.. .
|System and method for integrated circuit memory repair|
Memory blocks in an integrated circuit (ic) chip can be repaired by employing automated test equipment external to the ic chip to aid in burning fuses on the ic chip by encoding the fuses with binary-encoded numbers. Each binary-encoded number represents a bit position of each “1” bit of a repair control word corresponding to a defective memory location.
|Method for improving data retention of reram chips operating at low operating temperatures|
Programming a resistive memory structure at a temperature well above the operating temperature can create a defect distribution with higher stability, leading to a potential improvement of the retention time. The programming temperature can be up to 100 c above the operating temperature.
|Memory chip package, memory system having the same and driving method thereof|
A memory chip package includes memory chips stacked, electrically connected one another, and configured to input and output an optical signal through an optical line formed by a via penetrating the memory chips. The memory chips input and output optical signals with different wavelengths, and each of the memory chips has an optical-electrical converter configured to convert an optical signal with a corresponding wavelength into an electrical signal and to convert an electrical signal into an optical signal with the corresponding wavelength..
|Luminous element, bar-type luminous element and applications thereof|
A luminous element includes a heat dissipation plate, a body, a plurality of led chips, a first connector and a second connector. The heat dissipation plate includes a die-bonding area and a heat dissipation area opposite to the die-bonding area.
|Light-emitting device and lighting device provided with the same|
A light-emitting device capable of ensuring an electric connection between a light-emitting element and an electrode without generating any problem in practical use, by both connecting methods with a solder and a connector, and a lighting device provided with the light-emitting device are provided. The light-emitting device according to the present invention has a plurality of led chips, and a soldering electrode land and a connector connecting electrode land electrically connected to the chips, on a ceramic substrate.
|Light emitter components, systems, and related methods|
Light emitter components, systems, and related methods having improved optical efficiency and a lower manufacturing cost are disclosed. In one aspect, a light emitter component can include a substrate having an elongated body and first and second ends.
|Collapsible suspended lighting system|
A lighting system comprises a flexible support, such as a pair of fabric or web-like strips, and a plurality of tubular light sources supported by the flexible support. The flexible support may be hung from a support structure, and the tubular light sources will hang generally parallel to one another.
|Wavelength converting structure and manufacturing method thereof|
A wavelength converting structure suitable for covering a carrier carrying at least one light-emitting diode (led) chip is provided. The wavelength converting structure includes a base film and a fluorescent layer.
|System on chip, system including the same, and operating method thereof|
A method of operating a display system may include receiving an indication signal indicating a data update, receiving data, and updating a whole frame on the display with an image corresponding to the data based on the indication signal corresponding to a whole frame or updating a partial frame on the display with an image corresponding to the data based on the indication signal corresponding to a partial frame.. .
|Generating clock on demand|
A clock generation system for an integrated circuit (ic) chip (e.g., a microcontroller) is disclosed that allows digital blocks and other components in the ic chip to start and stop internal clocks dynamically on demand to reduce power consumption.. .
|Wafer level chip scale packaging intermediate structure apparatus and method|
Presented herein is a wlcsp intermediate structure and method forming the same, the method comprising forming a first redistribution layer (rdl) on a carrier, the first rdl having mounting pads disposed on the first rdl, and mounting interposer dies on a second side of the first rdl. A second rdl is formed over a second side of the interposer dies, the second rdl having a first side adjacent to the interposer dies, one or more lands disposed on the second rdl, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads.
|Chip package and method for manufacturing the same|
Various embodiments provide a chip package. The chip package may include a metallic chip carrier; at least one chip carried by the metallic chip carrier; encapsulation material encapsulating the at least one chip and the metallic chip carrier; and a plurality of redistribution layers disposed over the at least one chip opposite the metallic chip carrier, wherein at least one redistribution layer of the plurality of redistribution layers is electrically coupled with the at least one chip..
|Logic chip including embedded magnetic tunnel junctions|
An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (stt-mram) within a logic chip. The stt-mram includes a magnetic tunnel junction (mtj) with an upper mtj layer, lower mtj layer, and tunnel barrier directly contacting the upper mtj layer and the lower mtj layer; wherein the upper mtj layer includes an upper mtj layer sidewall and the lower mtj layer includes a lower mtj sidewall horizontally offset from the upper mtj layer.
|Logic chip including embedded magnetic tunnel junctions|
An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (stt-mram) within a logic chip. The stt-mram includes a magnetic tunnel junction (mtj) that has an upper mtj layer, a lower mtj layer, and a tunnel barrier directly contacting the upper mtj layer and the lower mtj layer; wherein the upper mtj layer includes an upper mtj layer sidewall and the lower mtj layer includes a lower mtj sidewall horizontally offset from the upper mtj layer.
|Phosphors for warm white emitters|
A method for fabricating light-emitting devices includes obtaining a plurality of light-emitting diode (led) chips fabricated to emit blue light and preparing a phosphor-containing material comprising a matrix material having dispersed therein a mixture of a red phosphor and a green phosphor in a fixed ratio to each other. The method also includes disposing different thicknesses of the phosphor-containing material on different ones of the led chips.
|Semiconductor light emitting device and method of manufacture|
A light-emitting diode (“led”) device has an led chip attached to a substrate. The terminals of the led chip are electrically coupled to leads of the led device.
|Ceramic based light emitting diode (led) devices and methods|
Light emitter devices, such as light emitting diode (led) devices and related methods are disclosed. A light emitter device includes a ceramic based substrate, at least one led chip disposed on the substrate, and a filling material.
|Semiconductor device and manufacturing method of the same|
A semiconductor device includes a die pad, an sic chip mounted on the die pad, a porous first sintered ag layer bonding the die pad and the sic chip, and a reinforcing resin portion covering a surface of the first sintered ag layer and formed in a fillet shape. The semiconductor device further includes a source lead electrically connected to a source electrode of the sic chip, a gate lead electrically connected to a gate electrode, a drain lead electrically connected to a drain electrode, and a sealing body which covers the sic chip, the first sintered ag layer, and a part of the die pad, and the reinforcing resin portion covers a part of a side surface of the sic chip..
|Method of manufacturing led module|
The present invention relates to a method of manufacturing an led module, which enhances heat dissipation efficiency of the led module through a configuration of installing a plurality of electrically separated conductive electrode plates to be close to each other on a same plane, stacking insulation layers on the top and bottom sides of the electrode plates, forming a plurality of ground holes on one side of the insulation layers to expose the electrode plates, and then grounding both electrodes of led chips to the separated electrode plates.. .
|Built-in-self-test (bist) test time reduction|
Aspects of the invention provide for reducing bist test time for a memory of an ic chip. In one embodiment, a bist architecture for reducing bist test time of a memory for an integrated circuit (ic) chip, the architecture comprising: a pair of latches for receiving bursts of data from a memory; a first compression stage for receiving a burst of data and compressing the burst of data into a plurality of latches; a second compression stage for comparing the compressed bursts of data with expected data; and a logic gate for determining whether there is a fail in the burst of data..
|System on chip fault detection|
The invention relates to a method for fault identification in a system-on-chip (soc) consisting of a number of ip cores, wherein each ip core is a fault containment unit, and where the ip cores communicate with one another by means of messages via a network-on-chip, and wherein an excellent ip core provides a trm (trusted resource monitor), wherein a faulty control message which is sent from one non-privileged ip core to another non-privileged ip core is identified and projected by an (independent) fault container unit, as a result of which this faulty control message cannot cause any failure of the message receiver.. .
|System-on-chip and method of operating the same|
A system on chip (soc) includes a central processing unit (cpu), an intellectual property (ip) block, and a memory management unit (mmu). The cpu is configured to set a prefetch direction corresponding to a working set of data.
|Transcoding on virtual machines using memory cards|
The present embodiments disclose techniques for transcoding media data using a virtualized network environment. This virtual environment may be hosted on one or more memory cards which each contain one or more memory chips.