|| List of recent Chip-related patents
|Built-in-self-test (bist) test time reduction|
Aspects of the invention provide for reducing bist test time for a memory of an ic chip. In one embodiment, a bist architecture for reducing bist test time of a memory for an integrated circuit (ic) chip, the architecture comprising: a pair of latches for receiving bursts of data from a memory; a first compression stage for receiving a burst of data and compressing the burst of data into a plurality of latches; a second compression stage for comparing the compressed bursts of data with expected data; and a logic gate for determining whether there is a fail in the burst of data..
|System on chip fault detection|
The invention relates to a method for fault identification in a system-on-chip (soc) consisting of a number of ip cores, wherein each ip core is a fault containment unit, and where the ip cores communicate with one another by means of messages via a network-on-chip, and wherein an excellent ip core provides a trm (trusted resource monitor), wherein a faulty control message which is sent from one non-privileged ip core to another non-privileged ip core is identified and projected by an (independent) fault container unit, as a result of which this faulty control message cannot cause any failure of the message receiver.. .
|System-on-chip and method of operating the same|
A system on chip (soc) includes a central processing unit (cpu), an intellectual property (ip) block, and a memory management unit (mmu). The cpu is configured to set a prefetch direction corresponding to a working set of data.
|Transcoding on virtual machines using memory cards|
The present embodiments disclose techniques for transcoding media data using a virtualized network environment. This virtual environment may be hosted on one or more memory cards which each contain one or more memory chips.
|Method of amplifying and labeling the mrna sample for mrna microarray|
Disclosed is method of amplifying and labeling mrna sample for the mrna microarray. The invention utilizes the specific synthesized single strand oligonucleotide (ssdna) poly-t to hybridize the complementary poly-a in the tail of the mrna; converts the hybridized mrna to the cdna; hybridizes the mrna detection probe on the mrna microarray chip with the cdna; amplifies the hybridized cdna through extending the polymer based on the ssdna; labels the amplified cdna by integrating the fluorescent modified nucleotide into the amplified duplex oligonucleotide during polymer extension; verifies the amplified labeled cdna through detecting the fluorescent signal.
|Dna photolithography with cinnamate crosslinkers|
The present invention relates generally to cinnamate crosslinkers. Specifically, the present invention relates to gels, biochips, and functionalized surfaces useful as probes, in assays, in gels, and for drug delivery, and methods of making the same using a newly-discovered crosslinking configuration..
|Silanol condensation catalyst, heat-curable silicone resin composition for sealing photosemiconductors and sealed photosemiconductor using same|
A silanol condensation catalyst including at least the zirconium metal salt expressed by formula (i) below (wherein n is an integer from 1 to 3; each r1 is a hydrocarbon group having from 1 to 16 carbons; and each r2 is a hydrocarbon group having from 1 to 18 carbons. A heat-curable silicone resin composition for sealing optical semiconductors includes 100 parts by mass of a polysiloxane containing two or more silanol groups in the molecule; from 0.1 to 2,000 parts by mass of a silane compound containing two or more alkoxy groups that are bonded to a silicon atom in the molecule; and a zirconium metal salt expressed by formula (i).
|Scalable biochip and method for making|
The present disclosure provides a biochip and methods of fabricating. The biochip includes a fluidic part and a sensing part bonded together using a polymer.
|Capture, purification, and release of biological substances using a surface coating|
This invention relates to a surface coating for capture circulating rare cells, comprising a nonfouling composition to prevent the binding of non-specific cells and adsorption of serum components; a bioactive composition for binding the biological substance, such as circulating tumor cells; with or without a linker composition that binds the nonfouling and bioactive compositions. The invention also provide a surface coating for capture and purification of a biological substance, comprising a releasable composition to release the non-specific cells and other serum components; a bioactive composition for binding the biological substance, such as circulating tumor cells; with or without a linker composition that binds the releasable and bioactive compositions.
|Reconfigurable noc for customizing traffic and optimizing performance after noc synthesis|
Systems and methods described herein are directed to solutions for network on chip (noc) interconnects that supports reconfigurability to support a variety of different traffic profiles each having different sets of traffic flows after the noc is designed and deployed in a soc. Reconfiguration of the noc to map and load a new traffic profile or change the currently mapped traffic profile is performed by an external optimization module which maps various transactions of a given traffic profile to the noc and reconfigure the noc hardware by loading the computed mapping information.
|Light emitting package and led bulb|
A light emitting package includes a metal plate, a plurality of led chips, a plurality of leads and a molding compound. The metal plate has a first surface and a second surface, and is bent into two chip mounting portions, wherein an inclination angle is between the chip mounting portions.
|System on chip having processing and graphics units|
System on chip comprising a general purpose processing element, a graphics processing unit and a display interface, supporting graphics visualization on mobile computing devices and on embedded systems.. .
|Memory chip testing system and connector thereof|
A memory chip testing system includes a computer, a rheostat, a voltmeter, and a connector. The computer includes a main board, a number of memory chip interfaces mounted on the main board.
|Chip carrier structure, chip package and method of manufacturing the same|
Various embodiments provide a chip carrier structure. The chip carrier structure may include a structured metallic chip carrier; encapsulating material at least partially filling the structure; wherein the main surfaces of the metallic chip carrier are free from the encapsulating material..
|Low voltage avalanche photodiode with re-entrant mirror for silicon based photonic integrated circuits|
A low voltage apd is disposed at an end of a waveguide extending laterally within a silicon device layer of a pic chip. The apd is disposed over an inverted re-entrant mirror co-located at the end of the waveguide to couple light by internal reflection from the waveguide to an under side of the apd.
|Light-emitting diode (led) package having flip-chip bonding structure|
A light-emitting diode (led) package includes a package substrate, a first electrode pad, a second electrode pad, an upper insulating layer and an led chip. The first electrode pad is disposed on an upper surface of the package substrate and includes a groove.
Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (pop) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length.
|Systems and methods for preventing data remanence in memory|
A system for preventing data remanence in memory is provided. The system includes a computing device, a memory chip coupled to the computing device and including memory, and a heater, the heater configured to prevent data remanence in a memory by providing heat to at least a portion of the memory.
|Chip-on-lead package and method of forming|
In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads.
|Semiconductor memory modules and methods of fabricating the same|
The inventive concept provides semiconductor memory modules and methods of fabricating the same. The semiconductor memory module may include a module board having a first surface and a second surface opposite to the first surface, and memory chips mounted directly on the module board by a flip-chip bonding method.
|Cutting insert with asymmetric chip former|
A cutting insert includes a top surface, a bottom surface and a plurality of peripheral side surfaces. The top and bottom surfaces and the side surfaces are joined to form rounded cutting corners.
|System and method for measuring thermal reliability of multi-chip modules|
Embodiments are provided herein for testing multichip module (mcm) thermal reliability. An embodiment method includes selecting a chip with higher thermal risk from a plurality of chips in the mcm, and measuring a plurality of predetermined temperature parameters associated with the selected chip.
|Semiconductor device having a control chip stacked with a controlled chip|
A semiconductor device includes a first controlled chip and a control chip stacked therewith. The first controlled chip includes a first circuit outputting a data signal in response to a synchronization signal, an input/output circuit outputting the data signal to a data terminal in synchronization with a delayed synchronization signal, and a replica circuit replicating an output circuit and outputting a replica signal to a first replica terminal in synchronization with the delayed synchronization signal.
|Wiring configuration of a bus system and power wires in a memory chip|
Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. The effective resistance on the power supply wires may be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires.
|Printed circuit board|
A printed circuit board includes an accommodating layer, chip capacitor devices accommodated in the accommodating layer, and a buildup structure formed on the accommodating layer such that the buildup structure covers the chip capacitor devices in the accommodating layer. The buildup structure has mounting conductor structures positioned to mount an ic chip device on a surface of the buildup structure such that the ic chip device is mounted directly over the chip capacitor devices, each of the chip capacitor devices has a dielectric body having a surface facing the buildup structure, a first electrode formed on the dielectric body and extending on the surface of the dielectric body, and a second electrode formed on the dielectric body and extending on the surface of the dielectric body, and the dielectric body is interposed between the first electrode and the second electrode..
|Method for manufacturing microfluidic chips, device for functionalizing microfluidic chips, microfluidic chip and device for holding a microfluidic chip|
The invention further relates to a microfluidic chip and a device for holding a microfluidic chip.. .
|Stack-type semiconductor package|
Provided is a stack-type semiconductor package comprising a first semiconductor package with a first package substrate and a logic chip mounted thereon, a second semiconductor package including a second package substrate disposed on the first semiconductor package and first and second memory chips stacked on the second package substrate, and connection pads disposed between the first and second package substrates to connect the first and second semiconductor packages electrically to each other. The first package substrate has first and second edges that are substantially perpendicular to each other.
|Semiconductor device and manufacturing method thereof|
As a display device has higher definition, the number of pixels is increased and thus, the number of gate lines and signal lines is increased. When the number of gate lines and signal lines is increased, it is difficult to mount ic chips including driver circuits for driving the gate lines and the signal lines by bonding or the like, whereby manufacturing cost is increased.
|Semiconductor memory device|
A crc code is generated from an original data, a bch code is generated with respect to the original data and the crc code, and the original data, the crc code, and the bch code are recorded in pages selected from different planes of a plurality of memory chips. An rs code is generated from the original data across pages, a crc code is generated with respect to the rs code, a bch code is generated with respect to the rs code and the crc code, and the rs code, the crc code, the bch code are recorded in a memory chip different from a memory chip including the original data.
|Data protection in near field communications (nfc) transactions|
Described herein are architectures, platforms and methods for protecting sensitive data that are utilized during near field communications (nfc) communications or transactions and more particularly, a system on chip (soc) microcontroller that is configured to control processing of the sensitive data during the nfc transactions is described. The sensitive data may include, but not limited to, personal information, financial information, or business identification numbers..
|Method for aligning a biochip|
A method of aligning a semiconductor chip includes forming a semiconductor chip with a light-activated circuit including at least one photosite, positioning the semiconductor chip relative to a device, and illuminating the positioned semiconductor chip. The method further includes generating an rf signal with an rf circuit based upon illumination of the at least one photosite, and determining the position of the photosite with respect to the device based upon the generated rf signal..
|Sample liquid injection jig set|
A liquid injecting jig is provided. The liquid injecting jig includes a jig configuration including a plurality of parts adapted to be in cooperative engagement so as to position a channel within the jig configuration, wherein the jig configuration is adapted to fit an opening through which the channel is adapted to be received so as to expose the channel from the jig configuration.
|Mimo-ofdm system for robust and efficient neuromorphic inter-device communication|
A multiple input multiple output (mimo) orthogonal frequency division multiplexing (ofdm) system for inter-device communication is described. Information data from each neuromorphic chip is coded and modulated, on the basis of destination, into different channels.
|Light emitting apparatus, and light irradiation apparatus provided with light emitting apparatus|
A light emitting device (1) includes (i) a surface-mounted light emitting section (10a), (ii) a lens section (30) which is provided on a light exit side of the surface-mount light emitting section (10a), and (iii) a frame section (40) which fixes a periphery of the lens section (30). In the surface-mounted light emitting section (10a), a resin layer (17) that contains a red fluorescent material (17b) covers at least one (1) blue led chip (14a).
|Thermal regulation for solid state memory|
A chassis for a storage system contains a digital chamber that houses conventional electronic components and a thermal chamber that houses non-volatile solid state memory such as flash memory. A temperature regulating system monitors temperature within the digital chamber to keep the components therein below their maximum junction temperature.
|Process control monitoring for biochips|
The present disclosure provides a biosensor device wafer testing and processing methods, system and apparatus. The biosensor device wafer includes device areas separated by scribe lines.
|Electronic device, package, electronic apparatus, and moving object|
A physical quantity sensor includes an ic chip and a package base mounted with the ic chip. The package base includes a first wiring layer provided with bonding pads connected to the ic chip via a bonding wire, a second wiring layer overlapping the first wiring layer in plan view, and an insulating layer provided between the first wiring layer and the second wiring layer.
|Light emitting device, light emitting element mounting method, and light emitting element mounter|
Disclosed is a light emitting device including: a light emitting element including an led chip and a phosphor layer provided at the light emitting side of the led chip; and a substrate on which the light emitting element is bonded by an adhesive material. The adhesive material is an anisotropic conductive material..
|Light emitting diode backlight module|
A light emitting diode (led) backlight module includes a transparent conductive substrate that has an electrode-bearing surface and a plurality of transparent conductive electrodes disposed on the electrode-bearing surface, an led chip that is welded on the transparent conductive electrodes by flip-chip packaging techniques, and a reflecting member that is spaced apart from and that corresponds in position to the led chip so as to reflect light generated from the led chip to the transparent conductive substrate.. .
|Light emitter components and methods having improved performance|
Light emitter components and methods having improved performance and related methods are disclosed. In one embodiment, a light emitter component can include a submount and at least one light emitting diode (led) chip disposed over the submount.
|Lighting device, backlight module and illumination module|
Various examples of a lighting device, backlight module and illumination module are described. A lighting device includes a carrier component, an led chip, a thermistor, and a plurality of metal wires.
|Sealed infrared imagers|
The architecture, design and fabrication of array of suspended micro-elements with individual seals are described. Read out integrated circuit is integrated monolithically with the suspended elements for low parasitics and high signal to noise ratio detection of changes of their electrical resistance.
|Method of designing & manufacturing an anti-counterfeiting rfid tag, the anti-counterfeiting rfid tag and the anti-counterfeiting package|
The invention relates to a method of designing & manufacturing anti-counterfeiting rfid tags, the anti-counterfeiting rfid tags obtained and the anti-counterfeiting package related. The invention belongs to application of radio frequency identification technology.
|Test control using existing ic chip pins|
An apparatus and method are provided for testing normal circuitry in an integrated circuit, the method including writing test protocols into a plurality of test registers using an enable pin and a switch pin in a first mode, storing a logic high signal in one of the plurality of test registers once the writing is completed, switching from the first mode to a second mode if the one of the plurality of test registers stores the logic high signal, and testing the normal circuitry using the enable pin and the switch pin in the second mode.. .
|Compression status bit cache and backing store|
One embodiment of the present invention sets forth a technique for increasing available storage space within compressed blocks of memory attached to data processing chips, without requiring a proportional increase in on-chip compression status bits. A compression status bit cache provides on-chip availability of compression status bits used to determine how many bits are needed to access a potentially compressed block of memory.
|Microfluidic interface for highly parallel addressing of sensing arrays|
Disclosed is a spotter device and methods for the formation of microassays, biochips, biosensors, and cell cultures. The spotter may be used to deposit highly concentrated spots of protein or other materials on a microarray slide, wafer, or other surface.
|Large receive offload functionality for a system on chip|
Various aspects provide large receive offload (lro) functionality for a system on chip (soc). A classifier engine is configured to classify one or more network packets received from a data stream as one or more network segments.
A plurality of memory chips each have an alert terminal that notifies the outside that the memory chip has detected a predetermined error. The plurality of memory chips are mounted on memory module 100.
A semiconductor device has a first controlled chip, including a first replica output circuit having the same configuration as a first output circuit, a first zq terminal connected to the first replica output circuit, a first through electrode connected to the first zq terminal, and a first control circuit which sets the impedance of the first replica output circuit. A control chip includes a second zq terminal connected to the first through electrode, a comparator circuit which compares a voltage of the second zq terminal with a reference voltage, and a second control circuit 123 which performs a process based on a comparison by the comparator circuit.
|Core module for wireless sensing system|
A core module of wireless sensing system is provided for receiving, processing and delivering environmental information, inclusive of a rf front-end circuit, a power control circuit, an analog front-end detection circuit and a baseband signal processor. A soc (system on chip) may be designed by including an electronic tag antenna, an impedance variation circuit and a sensor to form the wireless sensing system with the combination of a remote reader, such that the core module may be applied for wirelessly sensing the environmental information, such as physiological information of human heartbeat response, to achieve the effect of compactness, power saving and error detection..
|Millimeter wave wafer level chip scale packaging (wlcsp) device and related method|
Various embodiments include wafer level chip scale package (wlcsp) structures and methods of tuning such structures. In some embodiments, the wlcsp structure includes: a printed circuit board (pcb) trace connection including at least one pcb ground connection connected with a pcb ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the pcb ground plane; a signal ball contacting the signal pcb trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad..
|Led chip resistant to electrostatic discharge and led package including the same|
A light emitting diode chip and a light emitting diode package including the same. The light emitting diode chip includes a substrate, a light emitting diode section disposed on the substrate, an inverse parallel diode section disposed on the substrate and connected inversely parallel to the light emitting diode section.
An led module has an electrically insulating main body, a base surface and a mounting surface located opposite the base surface. A number of electrical connection contacts are arranged at the mounting surface.
|Led chip and method for manufacturing the same|
The invention provides a substrate structure used for manufacturing a light-emitting diode and a method for manufacturing the light-emitting diode. The substrate structure includes a substrate having a first surface and a second surface opposite to the first surface and a plurality of grooving structure formed on the first surface of the substrate.
A light-emitting device includes a plurality of led chips arranged in series and each including a chip substrate and a crystal layer including a light-emitting layer. One of the plurality of led chips is configured such that the chip substrate thereof includes a side surface facing another adjacent led chip of the plurality of led chips.
An led device is disclosed in which an led chip is encapsulated in a encapsulant. The led device includes an led chip mounted on a support and electrically connected and an encapsulant encapsulating the led chip, wherein the encapsulant is a transparent amorphous solid made of a metal oxide, and the solid contains as a major component at least one metal oxide selected from the group consisting of al2o3, mgo, zro, la2o3, ceo, y2o3, eu2o3, and sco..
|Multichip wafer level package (wlp) optical device|
Optical devices are described that integrate multiple heterogeneous components in a single, compact package. In one or more implementations, the optical devices include a carrier substrate having a surface that includes two or more cavities formed therein.
|Antenna, method of manufacturing the antenna, and wireless ic device|
An antenna includes first and second radiation portions including one lead wire that is folded back into a loop shape to define a folded-back portion and that includes a first power feed portion at a first end and a second power feed portion at a second end. The lead wire portion extending toward the folded-back portion and the lead wire portion extending through the folded-back portion are close enough to each other near each of the first and second power feed portions in the first and second radiation portions, respectively, to be electromagnetically coupled to each other.
|Geographic chip locator|
A system obtains and transmits and stores information, including location information of an article associated with a chip. The system may contain at least: an article intimately associated with an electromagnetically interrogatable chip; a hand-held information receiving and transmitting device that can interrogate the chip, the hand-held information receiving and transmitting device comprising an rfid and/or nfc reader to electromagnetically interrogate the chip; the chip containing communicable information relating to the article; a distal server in wireless two-way communication with the hand-held information receiving and transmitting device, the distal server capable of receiving, storing and transmitting information from the chip transmitted through the hand-held device.
|Application-specific led module and associated led point source luminaires|
Led downlight and other point source luminaires contain one or more application-specific led modules with integrated optical, mechanical, and heat dissipation systems; a fluted extruded metal housing acts as a heat sink as well as the luminaire housing containing the as-led module(s) or receiving a rotatable spherical housing that contains the as-led module, printed circuit board units, and wires; mounting brackets; and a remote led driver. The extruded aluminum housing (and heat sink) may be comprised of a single cylinder or multiple concentric cylinders.
|Light emitting device and display device|
There are provided a light-emitting device for use in a backlight unit of a display apparatus equipped with a display panel, which can be made lower in profile and is capable of applying light to the display panel with uniformity in the brightness of the display panel in the planar direction of the display panel, as well as a display apparatus equipped with the light-emitting device. A backlight unit includes a printed substrate, a plurality of light-emitting sections each having a base support, an led chip and a lens, and a reflective member surrounding the light-emitting section.
|Mtj three-axis magnetic field sensor and encapsulation method thereof|
The present invention discloses a mtj triaxial magnetic field sensor, comprising an x-axis bridge sensor that has a sensing direction along an x-axis, a y-axis bridge sensor that has a sensing direction along a y-axis, a z-axis sensor that has a sensing direction along a z-axis, and an asic chip connected with and matched to the x-axis, y-axis, and z-axis sensor chips. The z-axis sensor includes a substrate and mtj magnetoresistive elements deposited on the substrate.
|Light-emitting apparatus and method for manufacturing same|
A light-emitting apparatus including: a substrate; an led chip mounted on a first surface of the substrate; a fluorescent material-containing layer containing a first fluorescent material, which fluorescent material-containing layer is provided above the first surface of the substrate so as to cover the led chip; and a color-adjusting fluorescent layer that contains a second fluorescent material, which color-adjusting fluorescent material layer is formed in a layer provided on an outer side of the fluorescent material-containing layer in an emission direction, the color-adjusting fluorescent layer being formed in dots. Thus, the present invention provides a light-emitting apparatus and a method for manufacturing the same, each making it possible to carry out fine color adjustment so as to prevent a subtle color shift that occurs due to a factor such as a difference in concentration of a fluorescent material or the like..
|Solar powered ic chip|
A self-powered circuit package includes a substrate and an integrated circuit (ic). The ic is mounted on a surface of the substrate.
Provided is an rfid tag, wherein a communication distance of several centimeter or more can be secured and the cost of which can be reduced in comparison to conventional on-chip antennas, even when being compact in size (square shaped with a side of 1.9 to 13 mm). The rfid tag (80) comprises an antenna (20), an ic chip (30) connected to the antenna (20), and a sealing material (10) that seals the ic chip (30) and the antenna (20).
|Composite ic card|
Provided is a composite ic card including: a card base having a recess; an antenna sheet arranged inside the card base; an ic module arranged in the recess of the card base. The ic module includes an ic chip having a module substrate provided with an external terminal, and a first coupling coil.
|Magneto cyclist power sensor|
This device is a sensor whose output can be used for providing the cyclist with a display of the power he/she is delivering to the wheels of the bicycle while he/she is riding. It can also be used to determine bike gear selection and bike ground speed.