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Central Processing Unit patents



      
           
This page is updated frequently with new Central Processing Unit-related patent applications. Subscribe to the Central Processing Unit RSS feed to automatically get the update: related Central RSS feeds. RSS updates for this page: Central Processing Unit RSS RSS


Heat pipe assemblies

Dell ProductsL.p.

Heat pipe assemblies

Image forming apparatus, method for controlling image forming apparatus, and storage medium

Canon

Image forming apparatus, method for controlling image forming apparatus, and storage medium

Date/App# patent app List of recent Central Processing Unit-related patents
03/05/15
20150067450
 Solid state disk controller apparatus patent thumbnailnew patent Solid state disk controller apparatus
A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a cpu bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the cpu bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the cpu bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the cpu bus.. .
Samsung Electronics Co., Ltd.
03/05/15
20150067449
 Flash subsystem organized into pairs of upper and lower page locations patent thumbnailnew patent Flash subsystem organized into pairs of upper and lower page locations
A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (cpu), and a flash controller coupled to the cpu, the cpu being operable to pair a lower with an upper page.
Avalanche Technology, Inc.
03/05/15
20150067225
 Automatic communication and optimization of multi-dimensional arrays for many-core coprocessor using static compiler analysis patent thumbnailnew patent Automatic communication and optimization of multi-dimensional arrays for many-core coprocessor using static compiler analysis
There are provided source-to-source transformation methods for a multi-dimensional array and/or a multi-level pointer for a computer program. A method includes minimizing a number of holes for variable length elements for a given dimension of the array and/or pointer using at least two stride values included in stride buckets.
Nec Laboratories America, Inc.
03/05/15
20150062802
 Heat pipe assemblies patent thumbnailnew patent Heat pipe assemblies
Heat pipe assemblies for information handling systems (ihss). In some embodiments, an ihs may comprise a motherboard including a central processing unit (cpu); a cooling system coupled to the motherboard, the cooling system including a heat pipe, the cpu coupled to a first side of the heat pipe; and a daughterboard coupled to the motherboard and including a graphics processing unit (gpu) coupled to a second side of the heat pipe.
Dell Products, L.p.
03/05/15
20150062614
 Image forming apparatus,  controlling image forming apparatus, and storage medium patent thumbnailnew patent Image forming apparatus, controlling image forming apparatus, and storage medium
In an image forming apparatus in which a first board including a first central processing unit (cpu) and a second board including a second cpu communicate with each other to control image processing, a monitoring unit monitors whether processing executed by the second cpu is normal. If the monitoring unit determines that the processing executed by the second cpu is not normal, a notification unit notifies the first cpu.
Canon Kabushiki Kaisha
03/05/15
20150062133
 Using gpu for network packetization patent thumbnailnew patent Using gpu for network packetization
Information to be sent over a network, such as the ethernet, is packetized by using a graphics processing unit (gpu). The gpu performs packetization of data with much higher throughput than a typical central processing unit (cpu).
Barco, Inc.
03/05/15
20150061994
 Gesture recognition method and wearable apparatus patent thumbnailnew patent Gesture recognition method and wearable apparatus
A wearable apparatus includes a user interface, a motion sensor, a microprocessor and a central processing unit (cpu). In an operation mode, the motion sensor senses a current hand movement trajectory (hmt).
Wistron Corporation
03/05/15
20150061869
 Building intruder defensive shield patent thumbnailnew patent Building intruder defensive shield
This invention relates to a building intruder defensive shield system to deter, delay and distract intruders from causing damage or harm upon entering and roaming buildings. The defensive shield system includes a cold water supply plumbed to an expansion tank capable of pressurizing the water with a zone valve and nozzle.
02/26/15
20150058861
 Cpu scheduler configured to support latency sensitive virtual machines patent thumbnailCpu scheduler configured to support latency sensitive virtual machines
A host computer has one or more physical central processing units (cpus) that support the execution of a plurality of containers, where the containers each include one or more processes. Each process of a container is assigned to execute exclusively on a corresponding physical cpu when the corresponding container is determined to be latency sensitive.
Vmware, Inc.
02/26/15
20150058847
 Pass-through network interface controller configured to support latency sensitive virtual machines patent thumbnailPass-through network interface controller configured to support latency sensitive virtual machines
A host computer has a plurality of virtual machines executing therein under the control of a hypervisor, where the host also includes a physical network interface controller (nic). An interrupt controller detects an interrupt generated by the physical nic, where the interrupt corresponds to a virtual machine.
Vmware, Inc.
02/26/15
20150058846

Virtual machine monitor configured to support latency sensitive virtual machines


A host computer has a virtualization software that supports execution of a plurality of virtual machines, where the virtualization software includes a virtual machine monitor for each of the virtual machines, and where each virtual machine monitor emulates a virtual central processing unit (cpu) for a corresponding virtual machine. A virtual machine monitor halts execution of a virtual cpu of a virtual machine by receiving a first halt instruction from a corresponding virtual machine and determining whether the virtual machine is latency sensitive.
Vmware, Inc.
02/26/15
20150058666

System and treating server errors


An error handling system as applied to a server, the server comprising a central processing unit, the central processing unit configured to send a warning signal when the central processing unit generates an error. The error handling system includes a programmable logic device, a baseboard management controller coupled to a southbridge chip, and a basic input-output system coupled to the baseboard management controller.
Hon Hai Precision Industry Co., Ltd.
02/26/15
20150058665

Error correcting server


An error correcting system applied to a server, the server comprising a central processing unit, the central processing unit configured to send a warning signal when the central processing unit generates error. The error correcting system includes a programmable logic device, a baseboard management controller coupled to the programmable logic device, and a basic input output system coupled to the baseboard management controller.
Hon Hai Precision Industry Co., Ltd.
02/26/15
20150058660

Multimaster serial single-ended system fault recovery


A system to recover a multimaster serial single-ended bus and a faulted connected device includes a director device connected to the faulted connected device via the multimaster serial single-ended bus. The director device includes a central processing unit, a field programmable gate array, and a management module in communication with the faulted connected device, the management module configured to recover the faulted connected device and the multimaster serial single-ended bus.
International Business Machines Corporation
02/26/15
20150057004

System and downlink power optimization in a partitioned wireless backhaul network with out-of-neighborhood utility evaluation


A system and method for downlink power optimization in a partitioned wireless backhaul network with out-of-neighborhood utility evaluation is disclosed. The method comprises performing initial downlink power optimization for each neighborhood independently, considering only in-neighborhood utilities, by obtaining the transmit powers of all hubs and a utility performance of all served remote backhaul modules (rbms) in the neighborhood.
Blinq Wireless Inc.
02/26/15
20150055283

Electrical device


An electrical device includes a housing, a motherboard module and a holding assembly. The housing includes a top shell and a bottom shell which are assembled with each other.
Inventec (pudong) Technology Corporation
02/19/15
20150052536

Data processing method used in distributed system


Provided is a data processing method which can increase data processing speed without adding a new node to a distributed system. The data processing method may include: calculating a conversion number of cores corresponding to a number of processing blocks included in a graphics processing unit (gpu) of a node of a distributed system; calculating a adding up number of cores by adding up a number of cores included in a central processing unit (cpu) of the node of the distributed system and the conversion number of cores; splitting job data allocated to the node of the distributed system into a number of job units data equal to the adding up number of cores; and allocating a number of job units data equal to the number of cores included in the cpu to the cpu of the node of the distributed system and a number of job units data equal to the conversion number of cores to the gpu of the node of the distributed system..
Samsung Sds Co., Ltd.
02/19/15
20150052267

Enhanced data transfer in multi-cpu systems


A method implemented in a memory device, wherein the memory device comprises a first memory and a second memory, the method comprising receiving a direct memory access (dma) write request from a first central processing unit (cpu) in a first computing system, wherein the dma write request is for a plurality of bytes of data, in response to the dma write request receiving the plurality of bytes of data from a memory in the first computing system without processing by the first cpu, and storing the plurality of bytes of data in the first memory, and upon completion of the storing, sending an interrupt message to a second cpu in a second computing system, wherein the interrupt message is configured to interrupt processing of the second cpu and initiate transfer of the plurality of bytes of data to a memory in the second computing system.. .
Futurewei Technologies, Inc.
02/19/15
20150051026

Arcade basketball game with illuminated rim


An basketball arcade game is disclosed that includes a rim, a backboard, a ball sensor for the detection of balls that pass through the rim, a scoreboard for displaying a score relating to the game, a ball control access panel to permit and restrict access to balls that are used with said game, and a central processor that receives input from the ball sensor and provides output to the scoreboard, and the rim further includes a light source and a motor to laterally drive the rim which are both controlled by the central processing unit, and the rim may display light signals reflecting conditions of the game including bonus conditions and the time of play remaining.. .
Benchmark Entertainment, Lc
02/19/15
20150049159

Electronic television comprising mobile phone apparatus


A lcd television, led television, plasma television or other television system comprising a mobile phone having one or plurality of simsocket containing a plurality of pins, wherein input/output pin, clock pin, reset pin, vcc pin, ground pin are several respective pins of the said simsocket, and the said pins of one or plurality of simsocket are connected in parallel and the said plurality of simsockets for accepting plurality of simcards in order to operate the simcards selectively and/or simultaneously. The said plurality of simsocket are connected to the cpu (central processing unit) (14) in parallel and the said cpu (14) has a switching circuit and the said cpu (14) is connected to the one or plurality of simsocket through the switching circuit and the function of one or plurality of simsocket is operated by the cpu (14), switching circuit, and transreceivers (15).
02/12/15
20150047012

System and distributed multi-processing security gateway


A system and method for a distributed multi-processing security gateway establishes a host side session, selects a proxy network address for a server, uses the proxy network address to establish a server side session, receives a data packet, assigns a central processing unit core from a plurality of central processing unit cores in a multi-core processor of the security gateway to process the data packet, processes the data packet according to security policies, and sends the processed data packet. The proxy network address is selected such that a same central processing unit core is assigned to process data packets from the server side session and the host side session.
A10 Networks, Inc.
02/12/15
20150046759

Semiconductor integrated circuit device


A micro controller with fault detection function is provided, in which duplex processing by a program is realized without complicating the program. Peripheral circuits are provided with registers and execute processing based on a command.
Renesas Electronics Corporation
02/12/15
20150043162

Central processing unit casing


An electromagnetic interference (emi) shield for reducing the electromagnetic interference and substantially uniformly distribute heat is disclosed. The emi shield comprises a first layer configured to shield emi and a second layer configured to dissipate heat.
Wah Hong Industrial Corp.
02/12/15
20150043148

Server and heat dissipating assembly thereof


A server and a heat dissipating assembly thereof includes an airflow generating device, a central processing unit, several memory slots, a first cooling fin set, a second cooling fin set and a heat conductive member. The airflow generating device generates an airflow flowing along an airflow direction and is located at a front side of the central processing unit.
Inventec (pudong) Technology Corporation
02/12/15
20150043146

Server


A server includes a shell and at least one server assembly. The shell has a first accommodation space.
Inventec (pudong) Technology Corporation
02/12/15
20150043041

Mobile terminal, symbol sheet, assistance tool, image processing program, and image processing method


There is provided an imaging technology allowing easy acquisition/storing of image data drawn in an arbitrary area by a user, without the use of a dedicated document sheet, where a restriction is hardly imposed on a document sheet in terms of design. There are included a camera that images an imaging object to which a symbol sheet including a predetermined symbol is attached, a central processing unit that detects the predetermined symbol from an original image of the imaging object imaged by the camera, that recognizes a predetermined area calculated based on the predetermined symbol as an image acquisition area, and that extracts, and acquires as image data, an image in the image acquisition area, and image data storage unit that stores the image data..
King Jim Co., Ltd.
02/12/15
20150041595

Attitude and orbit control operating same


A hybrid network of kinematic sensors of an aocs, made up of a star sensor including an optical camera head, and a processing unit provided as the central master processing unit, and additional kinematic sensors, each made up of a sensor element and a processing unit connected to the central processing unit via a first bus. An additional processing unit is equivalent to the processing unit and is a redundant central processing unit.
Jena Optronik Gmbh
02/05/15
20150040131

Central processing unit resource allocation method and computing node


A method for allocating a central processing unit resource to a virtual machine, including determining, according to a change in the number of virtual machines in an advanced resource pool, the number of allocated physical cores in the advanced resource pool; and adjusting, according to the number of the allocated physical cores in the advanced resource pool, the number of allocated physical cores in a default resource pool, where the advanced resource pool and the default resource pool are resource pools that are obtained by dividing physical cores of a central processing unit according to service levels of the resource pools.. .
Huawei Technologies Co., Ltd.
02/05/15
20150039905

System for processing an encrypted instruction stream in hardware


A system and method of processing an encrypted instruction stream in hardware is disclosed. Main memory stores the encrypted instruction stream and unencrypted data.
Battelle Memorial Institute
02/05/15
20150039753

System and capacity planning for systems with multithreaded multicore multiprocessor resources


A method for expressing a hierarchy of scalabilities in complex systems, including a discrete event simulation and an analytic model, for analysis and prediction of the performance of multi-chip, multi-core, multi-threaded computer processors is provided. Further provided is a capacity planning tool for migrating data center systems from a source configuration which may include source systems with multithreaded, multicore, multichip central processing units to a destination configuration which may include destination systems with multithreaded, multicore and multichip central processing units, wherein the destination systems may be different than the source systems.
Ca, Inc.
02/05/15
20150035842

Dedicated voice/audio processing through a graphics processing unit (gpu) of a data processing device


A method includes providing an input port and/or an output port directly interfaced with a graphics processing unit (gpu) of a data processing device further including a central processing unit (cpu) to enable a corresponding reception of input data and/or rendering of output data therethrough. The method also includes implementing a voice/audio processing engine in the data processing device.
Nvidia Corporation
01/29/15
20150033041

Power supply circuit for central processing unit


A power supply circuit applied to a central processing unit (cpu) of a computer includes a pulse width modulation (pwm) controller, a control circuit, a first switch circuit, a second switch circuit, a first compensation circuit, a second compensation circuit, a first power circuit, and a second power circuit. When the computer is turned on, the pwm controller regulates duty cycles of pulse signals and outputs the regulated pulse signals to the first and second power circuits according to a first compensation signal, to provide a stable voltage to the cpu.
Hon Hai Precision Industry Co., Ltd.
01/29/15
20150033040

Power supply circuit for central processing unit


A power supply circuit for supplying power to a central processing unit (cpu) of a computer includes a pulse width modulation (pwm) controller, a control circuit, a switch circuit, a first current protection circuit, a second current protection circuit, a first power circuit, and a second power circuit. When the computer is turned on, a first current protection threshold is set by the pwm controller through the first current protection circuit.
Hon Hai Precision Industry Co., Ltd.
01/29/15
20150032932

Storage expansion apparatus and server


A storage expansion apparatus and a server, where the storage expansion apparatus includes a quick path interconnect (qpi) interface module, which communicates with a central processing unit (cpu) through a qpi bus; a peripheral component interconnect express (pcie) interface module, which communicates with the cpu through a pcie bus; an interface selecting module, connected to the qpi interface module and the pcie interface module separately; a home agent (ha) module, connected to the interface selecting module; and a memory controller engine (mceng) module, connected to the ha module and the interface selecting module separately. The storage expansion apparatus may serve as a cpu memory capacity expansion device, and may also serve as storage expansion hardware of storage input and output (to)..
Huawei Technologies Co., Ltd.
01/29/15
20150029662

Programmable controller component with assembly alignment features


A programmable logic controller (plc) assembly includes a bottom housing with a base, a first plurality of elongate alignment features extending from the bottom housing transverse to the base, and a first connection feature. The plc assembly includes a central processing unit with a circuit board and at least two receptacles therethrough configured to engage and slide along at least two of the first plurality of alignment features.
Rockwell Automation Technologies, Inc.
01/22/15
20150026520

Debugging circuit


A debugging circuit comprises a debugging interface, a switch unit coupled to the debugging interface, a controller coupled to the switch unit, a platform controller hub (pch), and a central processing unit (cpu). The pch and the cpu are coupled to the switch unit.
Hon Hai Precision Industry Co., Ltd.
01/22/15
20150026398

Mobile device and a controlling the mobile device


A mobile device including: a storage device; a system-on-chip (soc) including a central processing unit (cpu) and a memory interface configured to access the storage device in response to a request of the cpu; and a working memory including an input/output (i/o) scheduler and a device driver, the i/o scheduler configured to detect real time processing requests and store the real time processing requests in a sync queue, and detect non-real time processing requests and store the non-real time processing requests in an async queue, the device driver configured to adjust the performance of the mobile device based on the number of requests in the sync queue.. .
01/22/15
20150021598

Solid-state imaging device and semiconductor display device


A solid-state imaging device increases the sn ratio of a signal even when external light intensity is low. The solid-state imaging device includes a sensor circuit that includes a light-receiving element, a first transistor that controls connection between a first wiring and a node in which the amount of accumulated charge is determined by the amount of exposure to the light-receiving element, a second transistor whose on or off state is selected in accordance with the potential of the node, and a third transistor that controls connection between a second wiring and a third wiring together with the second transistor; a central processing unit that selects a first driving method or a second driving method in accordance with external light intensity; and a controller that controls a potential supplied to the gate of the first transistor in accordance with the first driving method or the second driving method..
Semiconductor Energy Laboratory Co., Ltd.
01/22/15
20150021478

Non-destructive sugar content measuring apparatus


A non-destructive sugar content measuring apparatus is provided and includes a measuring sensor portion for including a spectral sensor which receives a near infrared ray from the light which is reflected by the flesh fb of the fruit f of which the sugar content is measured, an led light source which has leds circularly arranged, an optical sensor which receives light reflected by a flesh of a fruit f, and a temperature sensor; a casing including a measuring sensor portion and has a panel portion which has a digital display for displaying a brix value as a digital value and operational switches, the panel portion and the operational switches being mounted on a front face thereof; a main circuit board pb for including a central processing unit (cpu) which is embedded in the casing and processes electric signals from the light sensor and performs a calculation and determination. .
Daesung Tech Co., Ltd.
01/22/15
20150021393

Currency keeper


An electronic safe which incorporates consumer programmable buttons, along with an on-board central processing unit.. .
The Gilbertson Group, Inc.
01/15/15
20150019883

Power supply circuit for central processing unit


A power supply circuit for a central processing unit (cpu) includes a comparing circuit, first to third switch circuits, first and second compensation circuits, a pulse width modulation (pwm) controller, a first power circuit connected to a first output pin of the pwm controller, and a second power circuit connected to a second output pin of the pwm controller. When a motherboard operates normally, the comparing circuit outputs a first control signal to control the first and third switch circuits to be turned on.
Hong Fu Jin Precision Industry (shenzhen) Co., Ltd.
01/15/15
20150019847

Programmable cpu register hardware context swap mechanism


A central processing unit (cpu) having an interrupt unit for interrupting execution of instructions, a plurality context defining register sets, wherein each set of registers having the same number of cpu registers, a switching unit for coupling a selected register set within the cpu, wherein the switching unit switches to a predetermined register set of the plurality of context defining register sets upon occurrence of an exception, and a control register configured to control selection of a register set of the plurality of context defining register initiated by an instruction and further operable to indicate a currently used context.. .
Microchip Technology Incorporated
01/15/15
20150019825

Sharing virtual memory-based multi-version data between the heterogeneous processors of a computer platform


A computer system may comprise a computer platform and input-output devices. The computer platform may include a plurality of heterogeneous processors comprising a central processing unit (cpu) and a graphics processing unit (gpu) and a shared virtual memory supported by a physical private memory space of at least one heterogeneous processor or a physical shared memory shared by the heterogeneous processor.
01/15/15
20150019798

Method and providing dual memory access to non-volatile memory


A method and system for providing a dual memory access to a non-volatile memory device using expended memory addresses are disclosed. The digital processing system such as a computer includes a non-volatile memory device, a peripheral bus, and a digital processing unit.
Cnexlabs, Inc.
01/15/15
20150019779

Microcomputer


To detect an abnormality in an interrupt control system without completely depending on dualization of a circuit, without the need to create a test pattern for a built-in self-test by spending time, and without considerably increasing an amount of power consumption. A test interrupt request is generated periodically using a timer or the like in an interrupt signal system from an interrupt controller to a central processing unit, the state of an interrupt request flag within the interrupt controller is checked in an interrupt processing routine, and in the case where it is detected that the same interrupt request flag is kept in a set state twice or more in succession, it is supposed that there is a high possibility that a failure has occurred in the interrupt signal system and it is considered that there is an abnormality..
Renesas Electronics Corporation
01/08/15
20150012736

Server and booting method


A server including a basic input output system (bios), a control unit and a plurality of central processing units (cpus), and a booting method are provided. The bios outputs a booting signal.
Inventec (pudong) Technology Corporation
01/08/15
20150011309

Qr code scoring system


A videogame, method, or system incorporates the use of a qr code which is produced by a central processing unit of a game, and is scanned by the player's or user's mobile communication device such as a smartphone. The smartphone's means for network connection to the internet is then used to communicate the game's data to a server associated with the game.
Raw Thrills, Inc.
01/08/15
20150010441

Electronic pregnancy test device


A handheld, readily portable, electronic pregnancy test device including a central processing unit in operational communication with a human chorionic gonadotropin hormone sensor able to detect a level of human chorionic gonadotropin in a blood sample disposed upon a test strip, said test strip loaded into the device through a test strip portal, wherein a pregnancy is verifiable and human chorionic gonadotropin doubling times are immediately calcuble whereby the health of the pregnancy is determinable absent direct medical assistance.. .
01/08/15
20150010148

Key management using security enclave processor


An soc implements a security enclave processor (sep). The sep may include a processor and one or more security peripherals.
Apple Inc.
01/08/15
20150009534

Operation apparatus, image forming apparatus, controlling operation apparatus, and storage medium


A multifunction peripheral (mfp) provided with an operation apparatus according to the present invention includes a liquid crystal display for displaying a preview image of a predetermined page of a file having a plurality of pages, a touch screen for detecting an operation pattern based on a user's touch operation performed on a display surface of the liquid crystal display, and a central processing unit (cpu) for switching the preview image to a preview image of another page of the file or a preview image of a predetermined page of another file according to the operation pattern detected by the touch screen while the preview image is being displayed.. .
Canon Kabushiki Kaisha
01/01/15
20150006953

System and a hardware shadow for a network element


A method and apparatus of a device that uses a hardware shadow for a central processing unit failover is described. In an exemplary embodiment, a device receives a signal that the active central processing unit has failed, where the active central processing unit controls the processing functions of the network element and the network element includes a hardware forwarding engine and a hardware shadow.
01/01/15
20150006871

Controlling access to storage in a computing device


In an embodiment, a computing device may include a control unit. The control unit may acquire a request from a central processing unit (cpu), contained in the computing device, that may be executing a basic input/output system (bios) associated with the computing device.
01/01/15
20150006782

Switching a computer system from a high performance mode to a low power mode


A computer system includes a first processor, a second processor, and a common memory connected to the second processor. The computer system is switched from a high performance mode, in which at least a portion of the first processor and at least a portion of components on the second processor are active, to a low power mode, in which at least a portion of the first processor is active and the components on the second processor are inactive.
Advanced Micro Devices, Inc.
01/01/15
20150006773

Control device and image forming apparatus


A control device includes an apparatus controller that is connected to at least one apparatus and includes a first memory which stores data for controlling the driving of the apparatus and data indicating a state of the apparatus and a reading and transmitting unit which reads each data item stored in the first memory and transmits the read data, a main controller that includes a central processing unit, a second memory, and a writing unit which writes the data transmitted from the apparatus controller to the second memory, and a full-duplex serial bus that connects the main controller and the apparatus controller. The reading and transmitting unit and the writing unit operate such that each data item stored in the first memory is read, transmitted, and stored in the second memory in a cycle equal to or less than a count cycle of a system timer..
Fuji Xerox Co., Ltd.
01/01/15
20150003238

System and management and control of communication channels


A system and method (here and after as the “inventive concept”) allows controlling and managing channels of communications between users. The invention includes a central processing unit which includes a software with a channel control algorithm that allocates available capacity of time between the users, i.e.


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Central Processing Unit topics: Central Processing Unit, Speech Recognition, User Interface, Storage Device, Alarm System, Constraints, Electronic Device, Embedded System, Application Program, Functional Specification, Control Flow, Application Programming Interface, Data Storage, Optical Fiber, Solid Structure

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