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Central Processing Unit patents

      

This page is updated frequently with new Central Processing Unit-related patent applications.




Date/App# patent app List of recent Central Processing Unit-related patents
08/18/16
20160241545 
 Method for managing access to protected computer resources patent thumbnailMethod for managing access to protected computer resources
A system for securing and tracking usage of transaction services or computer resources by a client computer from a first server computer, which includes clearinghouse means for storing identity data of the first server computer and the client computer(s); server software means and client software means adapted to forward its identity data and identity data of the client computer(s) to the clearinghouse means at the beginning of an operating session; and a hardware key connected to the client computer, the key being adapted to generate a digital identification as part of the identity data; wherein the hardware key is implemented using a hardware token access system, a magnetic card access system, a smart card access system, a biometric identification access system or a central processing unit with a unique embedded digital identification.. .
Prism Technologies Llc


08/18/16
20160240193 
 Clock switching in always-on component patent thumbnailClock switching in always-on component
In an embodiment, a system on a chip (soc) may include one or more central processing units (cpus), a memory controller, and a circuit configured to remain powered on when the rest of the soc is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern.
Apple Inc.


08/18/16
20160239376 
 Test case crash recovery patent thumbnailTest case crash recovery
A safe operating region of a complex integrated circuit may be determined by selecting an operating point for the integrated circuit (ic) at a first voltage and first frequency. A test program is executed by a central processing unit (cpu) comprised within the ic to test a portion of the ic.
Texas Instruments Incorporated


08/18/16
20160239266 
 Executing perform floating point operation instructions patent thumbnailExecuting perform floating point operation instructions
A method and system are disclosed for executing a machine instruction in a central processing unit. The method comprises the steps of obtaining a perform floating-point operation instruction; obtaining a test bit; and determining a value of the test bit.
International Business Machines Corporation


08/11/16
20160234317 
 Network interface device having general-purpose computing capability patent thumbnailNetwork interface device having general-purpose computing capability
Techniques for a network interface controller (nic) capable of performing general-purpose computing tasks without intervention from a central processing unit (cpu) are disclosed herein. The network interface controller includes a circuit board, a network interface, a computer bus interface and a processor.
Facebook, Inc.


08/11/16
20160232956 
 Semiconductor device, central processing unit, and electronic device patent thumbnailSemiconductor device, central processing unit, and electronic device
A novel semiconductor device, a semiconductor device with low power consumption, or a semiconductor device capable of retaining data for a long period is provided. The semiconductor device includes a first selection circuit connected to a plurality of first memory circuits, a second selection circuit connected to a plurality of second memory circuits, and a third selection circuit connected to a plurality of third memory circuits, thereby being capable of conducting power gating of each of the first memory circuits, each of the second memory circuits, or each of the third memory circuits separately.
Semiconductor Energy Laboratory Co., Ltd.


08/11/16
20160232707 
 Image processing method and apparatus, and computer device patent thumbnailImage processing method and apparatus, and computer device
Embodiments of the present invention disclose an image processing method and apparatus, and a computer device. The image processing method includes: receiving information sent by a central processing unit (cpu), about a scene within a preset range around a to-be-rendered target object; rendering the received scene to obtain scene depth parameters, where the scene is obtained through shooting by a camera located at a ray light source; rendering the to-be-rendered target object to obtain rendering depth parameters, where the to-be-rendered target object is obtained through shooting by a camera not located at a ray light source; calculating ambient occlusion (ao) maps of the to-be-rendered target object in directions of ray light sources according to the scene depth parameters and the rendering depth parameters; and overlaying the ao maps in the directions of the ray light sources, to obtain an output image..
Tencent Technology (shenzhen) Company Limited


08/11/16
20160232126 
 Expanded distribution unit patent thumbnailExpanded distribution unit
The invention relates to a method for processing real-time data in a distribution unit of a distributed computer system, the computer system comprising a plurality of node computers and distribution units, the distribution unit containing, in addition to a switching engine (se) and a switching memory (sm), one or more application computers each with one or more application central processing units and each with one or more application memories (am), wherein the switching engine of the distribution unit, when it receives, at one of its ports, a message intended for an application computer, forwards this message to the addressed application computer through a direct memory access (dma) unit that is arranged between the switching memory and the application memory of the addressed application computer and that is under the control of the switching engine. The invention also relates to an expanded distribution unit and a computer system with such expanded distribution units..
Fts Computertechnik Gmbh


08/11/16
20160232090 
 Crash-proof cache data protection method and system patent thumbnailCrash-proof cache data protection method and system
The inventions disclosed herein provide a crash-proof cache data protection method and system. The cache data backup steps include: when power interruption unexpectedly occur, a preselected central processing unit receiving an interrupt request signal; querying to obtain index nodes of block devices corresponding to logical volume management volumes; according to the index nodes, acquiring a page needing to be stored in a flash memory; acquiring a buffer head in the page, and storing information of the buffer head and buffer data corresponding to the buffer head into the flash memory, and generating backup data.
Beijing Fortunet Information & Technology Co., Ltd


08/11/16
20160232012 
 Multi-purpose power controller and method patent thumbnailMulti-purpose power controller and method
Described is a multi-purpose power controller and application specific standard product (assp) with improved block unification, reduced size and power, boot strapping, and power management. A multi-purpose field programmable non-volatile system power controller and assp initializing block may be embedded in a processor, such as a central processing unit (cpu), graphics processing unit (gpu), accelerated processing unit (apu), or other chipset.
Ati Technologies Ulc


08/11/16
20160231802 

Method and system control of a central processing unit (cpu) maximum power detector


A method and apparatus for system control of a central processing unit (cpu) maximum power detector are provided. In accordance with at least one embodiment, a decision is made as to whether a response of a maximum power detector of the cpu is to be altered.
Dell Products, Lp


08/11/16
20160231686 

Image forming apparatus, system including same, terminal apparatus included in system, and displaying limit information in image forming apparatus


An image forming apparatus is capable of setting a plurality of limiting conditions for each user. The image forming apparatus includes a hard disk drive (hdd) that stores a limiting condition set for each user, a touch panel that accepts input of an instruction from a user, a central processing unit (cpu) that determines whether a limiting condition is stored in the hdd in association with the user in response to the instruction from the user, and a display panel that displays limit information indicating details about limitation corresponding to the limiting condition in response to the cpu determining that the limiting condition is stored in the hdd..
Sharp Kabushiki Kaisha


08/04/16
20160225118 

Optimizing compilation of shaders


To optimize the compilation of shaders for execution within an application, a computer system discovers the context in which the shaders are executed. The application is compiled and executed on a target platform.
Microsoft Technology Licensing, Llc


08/04/16
20160224410 

Processing apparatus, memory-controlling apparatus, and control processing apparatus


In a processing apparatus according to an embodiment of the present invention, a central processing unit (cpu) outputs data, and a dual inline memory module (dimm) includes a plurality of dynamic random access memories (drams). Check bit generators generate error-checking codes for checking pieces of data output by the cpu, respectively.
Fujitsu Limited


08/04/16
20160224397 

Exploiting limited context streams


In one form, a data processing system includes volatile and non-volatile memory, a central processing unit, and at least one peripheral device. The central processing unit executes a selected one of a plurality of software applications as directed by an operating system by transferring the selected software application from the non-volatile memory to the volatile memory and executing instructions associated with the selected software application from the volatile memory.
Advanced Micro Devices, Inc.


08/04/16
20160224370 

Virtual machine monitor configured to support latency sensitive virtual machines


A host computer has a virtualization software that supports execution of a plurality of virtual machines, where the virtualization software includes a virtual machine monitor for each of the virtual machines, and where each virtual machine monitor emulates a virtual central processing unit (cpu) for a corresponding virtual machine. A virtual machine monitor halts execution of a virtual cpu of a virtual machine by receiving a first halt instruction from a corresponding virtual machine and determining whether the virtual machine is latency sensitive.
Vmware, Inc.


08/04/16
20160224362 

Delivering interrupts to virtual machines executing privileged virtual machine functions


Systems and methods for delivering certain types of interrupts to virtual machines executing privileged virtual machine functions. An example method may comprise: receiving, by a hypervisor being executed by a processing device of a host computer system, a request to send an interrupt to a virtual central processing unit (vcpu) of a virtual machine; responsive to detecting that the vcpu is executing a virtual machine (vm) function, monitoring the vcpu for completion of the vm function; and responsive to detecting that execution of the vm function is complete, delivering the interrupt to the vcpu..
Red Hat Israel, Ltd.


08/04/16
20160224258 

Generating computer programs for use with computers having processors with dedicated memory


To optimize utilization of such dedicated memory by a particular application, the application is executed with multiple permutations of placement of data in the dedicated memory. That application is executed on a target platform, and snapshots of the application during execution are captured on the target platform.
Microsoft Technology Licensing, Llc


08/04/16
20160224241 

Providing memory bandwidth compression using back-to-back read operations by compressed memory controllers (cmcs) in a central processing unit (cpu)-based system


Providing memory bandwidth compression using back-to-back read operations by compressed memory controllers (cmcs) in a central processing unit (cpu)-based system is disclosed. In this regard, in some aspects, a cmc is configured to receive a memory read request to a physical address in a system memory, and read a compression indicator (ci) for the physical address from error correcting code (ecc) bits of a first memory block in a memory line associated with the physical address.
Qualcomm Incorporated


08/04/16
20160220913 

Interactive toy


An interactive toy for a child, the interactive toy having a body, a central processing unit (cpu), a wireless communication module, a memory module, a batter module, and a plurality of input/output modules. The body has an ornamental exterior, at least one input button, and a perforated surface section.
Toymail Co., Llc


07/28/16
20160217845 

Information processing apparatus and information processing method


An information processing apparatus includes a memory that is volatile, a memory controller connected to the memory in an information exchangeable manner, and a clock enable (cke) controller. The cke controller controls a cke signal in response to a request for a proxy in self-refresh control, the cke signal being transmitted from the memory controller to the memory and being controlled to be kept low until cancellation of the proxy is requested.
Fuji Xerox Co., Ltd.


07/28/16
20160217105 

Systems and methods for transforming a central processing unit (cpu) socket into a memory and/or input/output (i/o) expander


Systems and methods for transforming a central processing unit (cpu) socket into a memory and/or input/output (i/o) expander. In an illustrative, non-limiting embodiment, an information handling system (ihs) may include a plurality of cpu sockets, each of the cpu sockets having one or more cores, and each of the one or more cores being associated with a respective one or more electronic circuits, the one or more electronic circuits including at least one of: a memory controller or an input/output (i/o) controller; and a basic input/output system (bios) circuit coupled to the plurality of cpu sockets, the bios circuit having access to program instructions that, upon execution by the bios, cause the ihs to: initialize the plurality of cpu sockets; and report an electronic circuit associated to a first core of a first cpu socket as being instead associated with a second core of a second cpu socket..
Dell Products, L.p.


07/28/16
20160217048 

Image forming apparatus which executes rebuild processes


An image forming apparatus comprises a first and a second hdds (hard disk drives), a raid (redundant arrays of inexpensive disks) controller to execute rebuilding processes in which data stored in the first hdd is copied to the second hdd restored, and a cpu (central processing unit). When there arises the necessity for accessing from the cpu to at least of the first and the second hdds, and the priority of data which is the object for access by the cpu is higher than the priority of data which is being processed under the rebuilding processes, the image forming apparatus stops the rebuilding processes.
Konica Minolta, Inc.


07/28/16
20160216783 

Signal-generating stylus, system, and method


A system and method may include a device including a user interface, a detector, and a central processing unit (cpu) in communication with the detector. The cpu controls operation of the device.
Lenovo (singapore) Pte. Ltd.


07/28/16
20160216752 

System on chip, managing power thereof, and electronic device


A system on chip includes an event manager configured to receive an event from an external source, an event analyzer configured to analyze the event received by the event manager to determine a voltage, a frequency, and power gating corresponding to the analyzed event, a power manager configured to set power on or off and to set a voltage, a clock manager configured to set a clock frequency, a power gating (pg) manager configured to set power gating, a main controller configured to include at least one modules and a central processing unit (cpu), and a wakeup controller configured to control the power manager, the clock manager, and the pg manager, to transmit power having a starting voltage and a clock signal having a starting clock frequency, and to transmit a power gating signal to apply power only to one of the at least one modules operating so as to start the main controller.. .
Samsung Electronics Co., Ltd.


07/28/16
20160216751 

Audio processing system


An audio processing system includes a first unit including a central processing unit (cpu) and a top domain. A system memory unit stores decoded audio data and a power management unit is configured to control power supply to the first unit and the system memory unit.
Samsung Electronics Co., Ltd.


07/28/16
20160216731 

Apparatus utilizing computer on package construction


Embodiments are generally directed to an apparatus utilizing computer on package construction. An embodiment of a computer includes a substrate; one or more semiconductor devices, the one or more semiconductor devices being direct chip attached to the substrate, the one or more semiconductor devices including a central processing unit (cpu); and one or more additional components installed on the substrate, wherein the computer excludes i/o components..
Intel Corporation


07/21/16
20160210840 

Comprehensive tsunami alert system via mobile devices


Embodiments of the present invention address deficiencies of the art in respect to navigation in gps-enabled mobile computing devices and provide a novel and non-obvious method, system and computer program product for location-based tsunami alerting navigational instructions in mobile computing devices. In an embodiment of the invention, a location-based tsunami alerting data processing system can be provided.
International Business Machines Corporation


07/21/16
20160210235 

Data processing system having combined memory block and stack package


A data processing system includes a central processing unit (cpu), a control block configured to interface with the cpu, a cache memory configured to interface with the control block and arranged to be spaced from the cpu by a first distance, and a combined memory block configured to interface with the control block, arranged to be spaced from the cpu by a second distance larger than the first distance, and configured of a working memory and a storage memory. The combined memory block is configured of a plurality of stacked memory layers, each configured of a plurality of variable resistance memory cells.
Sk Hynix Inc.


07/21/16
20160210170 

Computing cpu time usage of activities serviced by cpu


Processor(s) of a sampling profiler can identify an activity of multiple activities serviced by a central processing unit (cpu). Each activity can be performed by computing thread(s) of multiple computing threads executing various subroutines of a computer program.

07/21/16
20160210157 

Multimedia terminal for vehicle and data processing method thereof


A data processing method of a multimedia terminal for a vehicle includes booting, by an integration micom, a guest operation system according to a wakeup command received from a modem included in the multimedia terminal for the vehicle. The integration micom is physically independent from a main central processing unit (cpu).
Hyundai Motor Company


07/14/16
20160205011 

Method and device for testing link performance, logic processor and network processor


The disclosure discloses a method and device for testing link performance, a logic processor and a network processor (np). The method includes that: a first-type message is sent to an opposite node, and parameter information of the local node is acquired according to the first-type message; and a second-type message sent by the opposite node is received, and parameter information of the opposite node is acquired according to the second-type message, wherein a central processing unit (cpu) of the local node is capable of calculating link performance between the local node and the opposite node according to the parameter information of the local node and the parameter information of the opposite node.
Zte Corporation


07/14/16
20160203580 

Memory sharing via a unified memory architecture


A method and system for sharing memory between a central processing unit (cpu) and a graphics processing unit (gpu) of a computing device are disclosed herein. The method includes allocating a surface within a physical memory and mapping the surface to a plurality of virtual memory addresses within a cpu page table.
Intel Corporation


07/14/16
20160203284 

Mobile application for use with young patients who have a chronic illness


Systems for providing a chronically ill patient with medical alerts, pharmacological alerts and information are disclosed that includes: a mobile device comprising a gps receiver, a display, a microprocessor and a wireless communication transceiver, the mobile device programmed to process encrypted medical data, medical tags and medical information through an application; a server comprising a central processing unit, a memory, a clock and a server communication transceiver that receives input from the wireless communication transceiver of the mobile device, the memory having encrypted medical data, medical tags and medical information stored therein for a plurality of chronically ill patients, the central processing unit programmed to: receive encrypted medical data, medical tags and medical information from the mobile device; analyze the encrypted medical data, medical tags and medical information from the mobile device; generate a new set of unique and revised encrypted medical data, medical tags and medical information; provide the new set of unique and revised encrypted medical data, medical tags and medical information to the mobile device, wherein the mobile device updates the application with the unique and revised encrypted medical data, medical tags and medical information, which is then accessible by a user of the mobile device.. .
The Trustees Of The California State University Aka California State University San Marcos


07/07/16
20160197992 

File storage protocols header transformation in rdma operations


Various embodiments for efficient data transfer in a remote direct memory access (rdma) operation by a memory device. A file protocol header of the data is replaced with a block protocol header.
International Business Machines Corporation


07/07/16
20160196222 

Systems and methods for network i/o based interrupt steering


Systems and techniques for managing network processing on a central processing unit including multiple cores are described. Techniques may determine respective resource utilization for one or more processing cores.
Tuxera Corporation


06/30/16
20160192272 

Electronic device with wireless path selection capability


A portable encoded information reading (eir) terminal for incorporation in a data collection system can comprise a terminal module communicatively coupled to a wireless interface module via a wired interface. The terminal module can include a central processing unit (cpu), a memory, and an encoded information reading (eir) device.

06/30/16
20160188827 

Hybrid signal acquisition and system for combined electroencephalography and cardiac electrophysiology studies


In the present invention, a physiological data acquisition system for obtaining information on multiple physiological parameters from sensors operably connected to the system includes an amplifier configured to receive and output signals representative of the multiple physiological parameters in a temporally synchronized format and a central processing unit (cpu) operably connected to the hybrid amplifier to monitor the signals from the amplifier. The cpu is configured to provide a display of the synchronized signals for analysis of neurogenic conditions and to activate a recording of signals received for one physiological parameter based on a triggering event determined from signals received for another physiological parameter..

06/30/16
20160188520 

Electronic device and data transmission system


The present disclosure relates to an electronic device and a data transmission system. A first electronic device includes a micro universal serial bus (usb) interface, a central processing unit (cpu) and a diode, wherein a pull-circuit for an identity (id) pin of the cpu is coupled to a line between the id pin of the cpu and an id pin of the micro usb interface; the diode is coupled between the id pin of the cpu and the id pin of the micro usb interface, and is coupled between the pull-up circuit and the id pin of the micro usb interface; the diode has a conducting direction from the id pin of the cpu to the id of the micro usb interface.

06/30/16
20160188456 

Nvram-aware data processing system


In one form, a computer system includes a central processing unit, a memory controller coupled to the central processing unit and capable of accessing non-volatile random access memory (nvram), and an nvram-aware operating system. The nvram-aware operating system causes the central processing unit to selectively execute selected ones of a plurality of application programs, and is responsive to a predetermined operation to cause the central processing unit to execute a memory persistence procedure using the memory controller to access the nvram..

06/30/16
20160188371 

Application programming interfaces for data parallel computing on multiple processors


A method and an apparatus for a parallel computing program calling apis (application programming interfaces) in a host processor to perform a data processing task in parallel among compute units are described. The compute units are coupled to the host processor including central processing units (cpus) and graphic processing units (gpus).

06/30/16
20160187196 

Sensor for motion information, illumination information and proximity information, and operating central processing unit (cpu) using the sensor


A sensor configured for sensing motion information, illumination information, and proximity information is provided. The sensor includes a light sensing module configured to sense a change in an intensity of light, a filtering module configured to filter light incident to the light sensing module by using a plurality of filters, and a processor configured to process information associated with an intensity of light passing through the filters..

06/23/16
20160183374 

Cpu package substrates with removable memory mechanical interfaces


Configurable central processing unit (cpu) package substrates are disclosed. A package substrate is described that includes a processing device interface.

06/23/16
20160182851 

Systems and methods for automatic generation and consumption of hypermeetings


Provided a computer-implemented method for a meeting playback, the method being performed in connection with a computerized system incorporating a central processing unit, a display device and a memory, the computer-implemented method involving: generating a first user interface portion on the display device, the first user interface portion for displaying a first meeting; generating a second user interface portion on the display device, the second user interface portion for displaying a second meeting, wherein the first meeting is prior to the second meeting and wherein the first meeting and second meeting are linked together using at least one link; performing a playback of the second meeting in the second user interface portion; and during the playback of the second meeting, using the at least one link to perform a playback of at least a portion of the first meeting.. .

06/23/16
20160182529 

Systems and methods for secure location-based document viewing


A computer-implemented method, the method being performed in a computerized system incorporating a central processing unit, a localization signal receiver, a display and a memory, the computer-implemented method involving: receiving a request from a user for a content; receiving at least one localization signal using the localization signal receiver; determining a location based on the received localization signal; using a plurality of content access rules to determine whether the requested content is authorized to be accessed from the determined location; and providing content to the user only if the content is authorized to be accessed from the determined location.. .

06/23/16
20160180890 

Systems and methods for visualizing playback plans of hypermeetings


A computer-implemented method for visualizing a playback plan of a hypervideo, the hypervideo comprising a plurality of video segments from a plurality of videos linked together using a plurality of links, the method being performed in connection with a computerized system comprising a central processing unit, a display device and a memory, the computer-implemented method involving: generating the playback plan for an automated playback of the hypervideo, the automated playback comprising automatically following the plurality of links linking the plurality of video segments such that at least some of the plurality of video segments are played in a predetermined sequence, wherein the plurality of links are followed based on the playback plan; and generating a graphical user interface portion on the display device for visualizing the playback plan.. .

06/23/16
20160179744 

Computer system including cpu or peripheral bridge to communicate serial bits of peripheral component interconnect bus transaction and low voltage differential signal channel to convey the serial bits


A computer system has a computer with an integrated central processing unit and graphics subsystem in a single chip. The graphics subsystem directly couples to a unidirectional differential signal channel to output digital video data.

06/23/16
20160179708 

Information processing apparatus, information processing method, and non-transitory computer readable medium


An information processing apparatus includes first and second central processing units, a communication unit, and a memory. The first and second central processing units operate based on first and second operating systems, respectively.

06/23/16
20160179484 

Code generating method, compiler, scheduling method, scheduling apparatus and scheduling system


A code generating method, a compiler, a scheduling method, an apparatus and a scheduling system where the generated code is an executable code and applied to a heterogeneous system, and the heterogeneous system includes an accelerated processor and a central processing unit (cpu) and the code generating method includes acquiring, by a compiler, resource information of the accelerated processor and resource information of the cpu in order to generate an operable platform list, identifying, by the compiler, accelerable code from first user code, embedding, by the compiler, a hook function and an exception handling function before the accelerable code to form second user code, and compiling, by the compiler, the second user code to obtain the executable code and the executable code generated may automatically implement proper scheduling of processors during execution.. .

06/23/16
20160179293 

Systems and methods for plan-based hypervideo playback


Provided is a computer-implemented method for a playback of a hypervideo, the hypervideo including multiple video segments from a multiple videos linked together using links, the method being performed in connection with a computerized system incorporating a central processing unit, a display device and a memory, the computer-implemented method involving: generating a user interface portion on the display device for the playback of the hypervideo; and performing the playback of the hypervideo in the generated user interface portion by automatically following the plurality of links linking the plurality of video segments such that at least some of the plurality of video segments are played in a predetermined sequence; wherein the plurality of links are followed based on a playback plan. The playback plan may include at least one rule for following the multiple links linking the video segments during the playback of the hypervideo..

06/23/16
20160179156 

Hybrid power management approach


Methods and apparatus to provide a hybrid power management approach are described. Some embodiments redefine the interface to power control unit (pcu) allowing a hybrid implementation where software running on cpu (central processing unit, also referred to herein interchangeably as “processor”) cores performs more of the work for power management, enabling the pcu to remain as a simple or regular microcontroller.

06/23/16
20160178481 

Method for estimating the reliability of measurements by wheel sensors of a vehicle and system for its application


A method and system for evaluating the reliability of data supplied by multi-function wfc sensors of tires of wheels of a vehicle for targeted applications, on the basis of the irregularities of the road, which use displacement data sent from the road handling adaptation equipment of the vehicle, enabling the variations in the road condition to be reflected. The system includes equipment for monitoring the wheel displacement data for adapting it to the variations of profile of the road on which it is traveling, in order to maintain a stable body position.

06/23/16
20160175976 

Systems and methods for determining a weld torch location


A welding system having a modulation circuit, a weld torch, and a sensor system is provided. The modulation circuit configured to modulate a welding current with a randomized signal to generate a modulated welding current.

06/23/16
20160175191 

Spectral electrotherapy device and controlling the same


A spectral electrotherapy device and a method of controlling the same are introduced, wherein a central processing unit provides a control signal for controlling the switching operation of an output driver to generate output voltage, thereby controlling output features of the spectral electrotherapy device. The control signal provided by the central processing unit to a switching unit uses central frequency f0 as a standard to thereby define the bandwidth of the central frequency f0 with difference Δf and define the points in time of the next change in the central frequency f0 and the difference Δf with first and second time intervals t1, t2, respectively.

06/16/16
20160173950 

Third witness video participation system and method


A video recording and law enforcement corroboration process. A video feed is established between a law enforcement officer and a perpetrator, initiated by either party.
Virtual Health Systems Corporation


06/16/16
20160173896 

Methods and decoding video using re-ordered motion vector buffer


Methods and apparatus for decoding video are presented herein. The methods and apparatus may comprise a host processor, such as a central processing unit (cpu), programmed to execute a software driver that causes the host processor to generate a motion compensation command for a plurality of cores of a massively parallel processor, such as a graphics processing unit (gpu), to provide motion compensation for encoded video.
Advanced Micro Devices, Inc.


06/16/16
20160172055 

Combined rank and linear address incrementing utility for computer memory test operations


Embodiments include a combined rank and linear memory address incrementing utility. An aspect includes an address incrementing utility suitable for implementation within a memory controller as an integrated subsystem of a central processing unit (cpu) chip.
International Business Machines Corporation


06/16/16
20160171131 

Methods, systems, and computer readable media for utilizing parallel adaptive rectangular decomposition (ard) to perform acoustic simulations


Methods, systems, and computer readable media for utilizing parallel adaptive rectangular decomposition (ard) to perform acoustic simulations are disclosed herein. According to one method, the method includes assigning, to each of a plurality of processors in a central processing unit (cpu) cluster, ard processing responsibilities associated with one or more of a plurality of partitions of an acoustic space and determining, by each processor, pressure field data corresponding to the one or more assigned partitions.
The University Of North Carolina At Chapel Hill


06/16/16
20160170912 

Safely discovering secure monitors and hypervisor implementations in systems operable at multiple hierarchical privilege levels


In a computer system operable at multiple hierarchical privilege levels, a “wait-for-event” (wfe) communication channel between components operating at different privilege levels is established. Initially, a central processing unit (cpu) is configured to to “trap” wfe instructions issued by a client, such as an operating system, operating at one privilege level to an agent, such as a hypervisor, operating at a more privileged level.
Vmware, Inc.


06/16/16
20160170816 

Creating a communication channel between different privilege levels using wait-for-event instruction in systems operable at multiple hierarchical privilege levels


In a computer system operable at multiple hierarchical privilege levels, a “wait-for-event” (wfe) communication channel between components operating at different privilege levels is established. Initially, a central processing unit (cpu) is configured to to “trap” wfe instructions issued by a client, such as an operating system, operating at one privilege level to an agent, such as a hypervisor, operating at a more privileged level.
Vmware, Inc.


06/16/16
20160170679 

Secondary cpu mmu initialization using page fault exception


In a computer system with multiple central processing units (cpus), initialization of a memory management unit (mmu) for a secondary cpu is performed using an exception generated by the mmu. In general, this technique leverages the exception handling features of the secondary cpu to switch the cpu from executing secondary cpu initialization code with the mmu “off” to executing secondary cpu initialization code with the mmu “on.” advantageously, in contrast to conventional techniques for mmu initialization, this exception-based technique does not require identity mapping of the secondary cpu initialization code to ensure proper execution of the secondary cpu initialization code..
Vmware, Inc.


06/16/16
20160166148 

Visualization of a development and escalation of a patient monitor alarm


In the present invention, a monitoring device for providing information on data obtained from sensors operably connected to the device includes a central processing unit configured to receive incoming data signals from a sensor concerning a physiological parameter and to compare the incoming data signals to predetermined alarm criteria for the physiological parameter to determine an alarm condition. The device also includes a display operably connected to the central processing unit and having a display screen with a display area configured to visually represent the incoming data signals concerning the physiological parameter relating to a determined alarm condition on a portion of the display area in a visually distinct manner from a remainder of the display area to visually illustrate an escalation effect..
General Electric Company


06/09/16
20160165085 

Information processing apparatus and image forming apparatus


An information processing apparatus includes a first central processing unit, a second central processing unit, and a returning unit. The first central processing unit has a normal operating state and a power-saving state in which power consumption is lower than in the normal operating state.
Fuji Xerox Co., Ltd.


06/09/16
20160164910 

Processing preventing packet attack


A processing method and apparatus for preventing a packet attack. A network protocol negotiation status of a port of a network device is monitored; a port that succeeds in network protocol negotiation is set to a trusted port, a protocol packet is selected, according to a first access control list (acl), from packets received by the trusted port, and a rate at which the protocol packet is sent to a central processing unit (cpu) is limited to a first committed access rate (car); a port that fails in network protocol negotiation is set to an untrusted port, a protocol packet is selected, according to a second acl, from packets received by the untrusted port, and a rate at which the protocol packet is sent to the cpu is limited to a second car.
Huawei Technologies Co., Ltd.


06/09/16
20160162336 

Cpu scheduler configured to support latency sensitive virtual machines


A host computer has one or more physical central processing units (cpus) that support the execution of a plurality of containers, where the containers each include one or more processes. Each process of a container is assigned to execute exclusively on a corresponding physical cpu when the corresponding container is determined to be latency sensitive.
Vmware, Inc.


06/09/16
20160162294 

Reconfigurable processors and methods for collecting computer program instruction execution statistics


Reconfigurable processors and methods for collecting computer program instruction execution statistics are disclosed. According to an aspect, a method includes providing a reconfigurable processor configured to execute a set of central processing unit (cpu) instructions that each have a function.
Lenovo Enterprise Solutions (singapore) Pte. Ltd.


06/09/16
20160162061 

Low latency inking


This disclosure generally provides an input device that includes a by-pass path for improving latency between a touch controller and a display driver. In one embodiment, the by-pass path directly connects the touch controller and display driver, thereby by-passing a host processor (e.g., a central processing unit (cpu) or graphic processing unit (gpu)) in the input device.
Synaptics Incorporated


06/09/16
20160161995 

Socket and adapter


A motherboard can include a socket coupled to a cable. The motherboard can also include an adapter coupled to a central processing unit (cpu).
Hewlett-packard Development Company, L.p.


06/02/16
20160156697 

Communication terminal product supporting interactive association system


A communication terminal product supports a mobile communication technology system and supports transmit-receive of a multimedia information signal of the interactive interconnected system. The interactive interconnected system comprises an electronic reading device and an electronic transmitter-receiver.

06/02/16
20160155209 

Graphics processing unit and device including the same


A graphics processing unit (gpu) for determining whether to perform tessellation on a first model according to a control of a central processing unit (cpu) is provided. The gpu reads the first model from a memory, which stores prepared models having different complexities; calculates a complexity of the first model; compares the calculated complexity with a reference complexity; and determines whether to perform a tessellation operation on the first model according to a comparison result..

06/02/16
20160154806 

Print job archives that are optimized for server hardware


Systems and methods are provided for generating a print job archive optimized for searching by a specific server. The system includes a memory and an indexing controller.
Ricoh Company, Ltd.


06/02/16
20160154735 

Electronic device and controlling shareable cache memory thereof


An electronic device and a method for controlling a sharable cache memory of the electronic device are provided. The electronic device includes a central processing unit including at least one core processor, at least one module, and a sharable cache memory including a controller, wherein the controller enables the sharable cache memory as a cache memory of the central processing unit if the central processing unit is in a working mode, and wherein the controller enables the sharable cache memory as a buffer of at least one of modules if at least one core processor of the central processing unit is transitioned to a sleep mode..
Samsung Electronics Co., Ltd.


06/02/16
20160154661 

Systems and methods for virtual machine attribution with hardware information


Systems and methods for virtual machine (vm) attribution with hardware information. In an illustrative, non-limiting embodiment, an information handling system (ihs) may include a central processing unit (cpu) and a memory coupled to the cpu, the memory having program instructions stored thereon that, upon execution by the cpu, cause the ihs to: provide a management console configured to manage a plurality of hypervisors, each hypervisor configured to be executed in a different one of a plurality of physical servers distinct from the ihs, each hypervisor further configured to create and run at least one virtual machine (vm); identify, via the management console, a hardware capability of a given one of the plurality of physical servers; and assign the vm, by the management console, to the given physical server in response to the identification of the hardware capability..
Dell Products, L.p.


06/02/16
20160154597 

Backup of volatile memory to persistent storage


Approaches for automatically backing up data from volatile memory to persistent storage in the event of a power outage, blackout or other such failure are described. The approaches can be implemented on a computing device that includes a motherboard, central processing unit (cpu) a main power source, volatile memory (e.g., random access memory (ram)), an alternate power source and circuitry (e.g., a specialized application-specific integrated circuit (asic)) for performing the backup of volatile memory to a persistent storage device.
Amazon Technologies, Inc.


06/02/16
20160154422 

Motherboard with a hole


A printed circuit board (pcb) can include a central processing unit (cpu) installed on a first surface of the pcb. The pcb can also include a cable routed on a second surface of the pcb parallel to the first surface.
Hewlett-packard Development Company, L.p.


05/26/16
20160150471 

Electricity saving terminal device, and terminal device


Disclosed are a power saving method for a terminal device and the terminal device thereof, wherein the method includes: a terminal device enabling a power saving mode and obtaining an adjusted central processing unit (cpu) clock speed set by a user and an adjusted screen resolution set by the user; if the terminal device obtains the adjusted cpu clock speed set by the user, the terminal device adjusting the cpu to operate according to the adjusted cpu clock speed set by the user; if the terminal device obtains the adjusted screen resolution set by the user, the terminal device adjusting a screen display according to the adjusted screen resolution set by the user. The embodiment of the present document saves the power consumption of a terminal device by downsizing the screen display and/or reducing the cpu clock speed, thereby effectively reducing power consumption of the terminal device..
Zte Corporation


05/26/16
20160150080 

A url transmission system and means thereof


The present invention provides a uniform resource locator (url) transmission system for displaying at least one predetermined url comprising: (a) a smart phone having a phone call recognition system for recognizing and transmitting caller identification information; and, (b) a base station comprising a central processing unit (cpu) for transmitting telecommunication signals formatted as an active message. The cpu includes a computer readable medium containing instructions for automatically converting the recognized caller identification information to the active message, and instructions for automatically associating the active message to at least one predetermined url associated with the receiver of the caller's transmission..

05/26/16
20160149932 

Monitoring use of a sensor of a computing device


Monitoring use of a sensor of a computing device. A sensor obtains information from an environment of the computing device.
International Business Machines Corporation


05/26/16
20160148395 

Paintbrush and liquid simulation


Paintbrush and liquid simulation techniques are described. In one or more implementations, input is received to perform brush strokes with a virtual paintbrush on a virtual canvas.
Adobe Systems Incorporated


05/26/16
20160147673 

Microcomputer and controlling memory access


A memory control system includes a memory connected to a memory bus, the memory including a plurality of access areas, a memory controller connected to the memory bus, a plurality of registers corresponding to the plurality of access areas, each of the plurality of registers configured to set an access permission or prohibition for a corresponding access area, a cpu (central processing unit) configured to issue a first access request for accessing one of the plurality of access areas, and a memory access controller configured to determine whether an access to the memory is permissible or prohibited using the first access request and the plurality of registers, the memory access controller outputting a second access request in accordance with a determination result.. .
Renesas Electronics Corporation


05/26/16
20160147653 

Filtering multiple in-memory trace buffers for event ranges before dumping from memory


A method for filtering multiple in-memory trace buffers for event ranges is provided. The method includes allocating a plurality of main trace buffers, based on the number of central processing units (cpu) participating in a trace.
International Business Machines Corporation


05/26/16
20160146777 

Integrated user interface for status and control of a submersible multi-parameter sonde


Provided are multi-parameter sonde systems having a unique integrated user interface for ease of set-up and control, service and maintenance, even in the field and without accessory controllers. The necessary components, such as central processing unit, display and accelerometer are positioned in a water-tight housing, with the display configured for convenient observability and readability.
In-situ, Inc.


05/19/16
20160143041 

Multimode wireless terminal


Embodiments of the present invention provide a multimode wireless terminal, including a general-purpose central processing unit, a reconfigurable baseband processing module, a reconfigurable intermediate radio frequency module, and a reconfigurable antenna module, terminal is applicable to various network environments.. .
Huawei Technologies Co., Ltd.


05/19/16
20160140057 

Semiconductor device and encryption key writing method


A semiconductor device includes a central processing unit (cpu), a first memory which stores a plurality of split keys, a second memory which stores an encryption code as at least one of an encrypted instruction and encrypted data, the plurality of split keys including an encryption key for decrypting the encryption code, and a decrypter which reads the encryption code from the second memory, decrypts the encryption code with the use of the encryption key, and supplies the decrypted encryption code to the cpu. The second memory stores an encryption key reading program which is executed by the cpu to restore the encryption key and to supply the encryption key to the decrypter, by reading and reconfiguring the split keys stored in the first memory in a distributed manner..
Renesas Electronics Corporation


05/19/16
20160139669 

Device for intuitive dexterous touch and feel interaction in virtual worlds


A device for dexterous interaction in a virtual world in disclosed. The device includes a housing including a plurality of buttons and a plurality of vibration elements each associated with at least one of the plurality of buttons.
Thika Holdings Llc


05/19/16
20160139583 

Motor selection device


A motor selection device includes a computer including a storage device and a calculation device. The storage device stores data of acceleration time, constant speed time, deceleration time, stop time, maximum output torque for each motor, dynamic friction torque, and constant load torque.
Nsk Ltd.


05/19/16
20160139273 

Wireless devices and systems for tracking patients and methods for using the like


Disclosed are apparatuses, systems, and methods for tracking patients that suffer from dementia. The disclosed apparatus is a wearable device capable of micro-tracking through bluetooth low energy technology and capable of macro-tracking through gps technology.

05/12/16
20160134652 

Method for recognizing disguised malicious document


A method for recognizing disguised malicious document, carried out by a computer system including a central processing unit (cpu), a memory, and a database storing rules for defining executable file and non-executable file, comprising steps of: receiving a static file through a network and an input/out interface; scanning the static file for a file header to determine if it is a non-executable file; analyzing file body of the non-executable file to locate components of an executable file and mark these positions; extracting components of the executable file from the non-executable file; concatenating the extracted components in accordance with a default rule or a heuristic rule to form a new file; and obtaining a new file that is executable, such that the received static file is a non-executable file having an embedded executable file, thus labeling the static file as a disguised malicious document.. .
Verint Systems Ltd.


05/12/16
20160132861 

Method, device and secure element for conducting a secured financial transaction on a device


A device and a secure element for conducting a secured financial transaction are disclosed. The device comprises a central processing unit; a communication interface for establishing a communication between the device and a financial institution related to a financial account; an interface for acquiring data relating to the financial account; the secure element for processing at least a portion of the data relating to the financial account acquired by the interface; and control logic for acquiring a purchase amount to be debited from the financial account and for obtaining a transaction authorization from the financial institution related to the financial account, the transaction authorization being based, at least partially, on data processed solely by the secure element independently of data processed by the central processing unit.
Mobeewave, Inc.


05/12/16
20160132389 

Solid state disk controller apparatus


A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a cpu bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the cpu bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the cpu bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the cpu bus.. .
Samsung Electronics Co., Ltd.


05/12/16
20160132100 

Data processing device and data processing system


A data processing device includes a first power-on reset circuit, a second power-on reset circuit with a higher power consumption and a higher reset voltage accuracy than said first power-on reset circuit, a low voltage detect circuit, a storage unit storing information for determining whether to keep said second power-on reset circuit and said low voltage detect circuit in an active state or an inactive state, a central processing unit initialized in a response to respective outputs of said first and second power-on reset circuits and setting said information in said storage unit, and a power supply node providing a power to the data processing device.. .
Renesas Electronics Corporation




Central Processing Unit topics: Central Processing Unit, Speech Recognition, User Interface, Storage Device, Alarm System, Constraints, Electronic Device, Embedded System, Application Program, Functional Specification, Control Flow, Application Programming Interface, Data Storage, Optical Fiber, Solid Structure

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