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Central Processing Unit patents



      
           
This page is updated frequently with new Central Processing Unit-related patent applications. Subscribe to the Central Processing Unit RSS feed to automatically get the update: related Central RSS feeds. RSS updates for this page: Central Processing Unit RSS RSS


User datagram protocol (udp) packet migration in a virtual machine (vm) migration

User datagram protocol (udp) packet migration in a virtual machine (vm) migration

User datagram protocol (udp) packet migration in a virtual machine (vm) migration

User datagram protocol (udp) packet migration in a virtual machine (vm) migration

User datagram protocol (udp) packet migration in a virtual machine (vm) migration

Techniques and configurations for communication between devices

Date/App# patent app List of recent Central Processing Unit-related patents
12/11/14
20140366162
 Starvationless kernel-aware distributed scheduling of software licenses patent thumbnailStarvationless kernel-aware distributed scheduling of software licenses
Methods, systems, and apparatuses for implementing shared-license software management are provided. Shared-license software management may be performed by generating a request for a license for running a process of a shared-license software application.
12/11/14
20140366029
 User datagram protocol (udp) packet migration in a virtual machine (vm) migration patent thumbnailUser datagram protocol (udp) packet migration in a virtual machine (vm) migration
Embodiments of the invention relate to receiving, by a first processor comprising a processing device, an indication that a migration of a virtual machine from the first processor to a second processor is to occur. The first processor transmits user datagram protocol (udp) packets intended for the virtual machine to the second processor based on the indication.
12/11/14
20140366028
 User datagram protocol (udp) packet migration in a virtual machine (vm) migration patent thumbnailUser datagram protocol (udp) packet migration in a virtual machine (vm) migration
Embodiments of the invention relate to receiving, by a first processor comprising a processing device, an indication that a migration of a virtual machine from the first processor to a second processor is to occur. The first processor transmits user datagram protocol (udp) packets intended for the virtual machine to the second processor based on the indication.
12/11/14
20140365832
 Techniques and configurations for communication between devices patent thumbnailTechniques and configurations for communication between devices
Techniques and configurations are disclosed herein for communication between devices. In some embodiments, a bus for communication between first and second devices may include a transmit buffer and one or more processing devices.
12/11/14
20140364223
 System and method for improving the graphics performance of hosted applications patent thumbnailSystem and method for improving the graphics performance of hosted applications
An application/game server comprising a central processing unit to process application/video game program code and a graphics processing unit (gpu) to process graphics commands and generate a series of video frames for the application/video game; one or more back buffers to store video frames as the video frames are being created in response to the execution of the graphics commands; a front buffer-outputting the video frame for display one scan line at a time at a designated scan out frequency, a subset of scan lines stored in the front buffer being associated with a vertical blanking interval (vbi); and a frame processing module to begin copying a newly completed frame from the back buffer to the front buffer before the video data for a prior video frame stored in the front buffer has not been fully scanned out.. .
12/11/14
20140364079
 Method and apparatus for advanced topology (at) policy management for direct communication between wireless transmit/receive units (wtrus) patent thumbnailMethod and apparatus for advanced topology (at) policy management for direct communication between wireless transmit/receive units (wtrus)
A method and apparatus for advanced topology (at) policy management for direct communication between wireless transmit/receive units (wtrus) is described. A wtru configured to communicate directly with at least one other wtru in an at mode of operation includes a memory, a central processing unit and an at policy unit that is separate from the cpu.
12/11/14
20140362745
 Central processing unit and methods for supporting coordinated multipoint transmission in an lte network patent thumbnailCentral processing unit and methods for supporting coordinated multipoint transmission in an lte network
Embodiments of a central processing unit and methods for supporting coordinated multi-point (comp) transmissions in a 3gpp lte network with non-ideal backhaul links are generally described herein. In some embodiments, the cpu may be arranged for scheduling and assigning resources for subordinate enhanced node bs (enbs) over the backhaul links for comp transmissions.
12/11/14
20140362576
 Computer architecture patent thumbnailComputer architecture
An internal component and external interface arrangement for a cylindrical compact computing system is described that includes at least a structural heat sink having triangular shape disposed within a cylindrical volume defined by a cylindrical housing. A computing engine having a generally triangular shape is described having internal components that include a graphics processing unit (gpu) board, a central processing unit (cpu) board, an input/output (i/o) interface board, an interconnect board, and a power supply unit (psu)..
12/11/14
20140362214
 Apparatus and method for processing image signal patent thumbnailApparatus and method for processing image signal
An apparatus and a method are arranged to process an image signal including: a central processing unit (cpu) which outputs a digital image corresponding to an input image from an image collection apparatus to an image display apparatus; a controller, or micom, which monitors an operation state of the cpu, and outputs a control signal depending on occurrence of an error in the cpu; and an image switch which switches an image output mode to one of a digital image mode and an analog image mode according to the control signal which is output through the micom in an input terminal of the cpu.. .
12/11/14
20140362093
 Graphics effect data structure and method of use thereof patent thumbnailGraphics effect data structure and method of use thereof
A graphics effect data structure and method of use thereof. One embodiment of the graphics effect data structure is embodied in an effect processing system, including: (1) a memory configured to store an effect data structure that describes a graphics effect implemented by a plurality of passes and shader code modules contained in the effect data structure, (2) a graphics processing unit (gpu) operable to render the graphics effect according to a shader program based on the shader code modules, assembled according to the plurality of passes, and (3) a central processing unit (cpu) configured to execute an application that employs the graphics effect and to gain access to the effect data structure during run time, at which time the shader program is passed to the gpu for processing..
12/11/14
20140361893
Computer input/output interface
An internal component and external interface arrangement for a cylindrical compact computing system is described that includes at least a structural heat sink having triangular shape disposed within a cylindrical volume defined by a cylindrical housing. A computing engine having a generally triangular shape is described having internal components that include a graphics processing unit (gpu) board, a central processing unit (cpu) board, an input/output (i/o) interface board, an interconnect board, and a power supply unit (psu)..
12/11/14
20140361671
Computer internal architecture
An internal component and external interface arrangement for a cylindrical compact computing system is described that includes at least a structural heat sink having triangular shape disposed within a cylindrical volume defined by a cylindrical housing. A computing engine having a generally triangular shape is described having internal components that include a graphics processing unit (gpu) board, a central processing unit (cpu) board, an input/output (i/o) interface board, an interconnect board, and a power supply unit (psu)..
12/04/14
20140359312
Power on with near field communication
A system for powering up a computer having a central processing unit (cpu), which cpu includes an operating system (os), when the cpu is in an sx state in which the (os) is not powered up. There is a near field communication (nfc) detector for detecting an nfc signal, and an embedded controller physically separate from said cpu, the embedded controller responsive to the nfc signal and adapted to power up the cpu out of said sx state..
12/04/14
20140359191
Adc sequencing
A device comprises a central processing unit (cpu) and a memory configured for storing memory descriptors. The device also includes an analog-to-digital converter controller (adc controller) configured for managing an analog-to-digital converter (adc) using the memory descriptors.
12/04/14
20140359180
Method for providing a generic interface and microcontroller having a generic interface
A microcontroller for a control unit, in particular for a vehicle control unit, includes a central processing unit (cpu), at least one interface-unspecific input module, at least one interface-unspecific output module, at least one routing unit and at least one arithmetic unit for processing interface-specific information. The microcontroller is configurable in such a way that the at least one interface-unspecific input module, the at least one interface-unspecific output module, the at least one routing unit and the at least one arithmetic unit for processing interface-specific information fulfill functions corresponding to one of multiple serial interfaces, in particular of spi, uart, lin, can, psi5, flexray, sent, ic2, msc or ethernet.
12/04/14
20140359179
Method for providing a generic interface and microcontroller having a generic interface
A microcontroller for a control unit, in particular for a vehicle control unit, includes a central processing unit (cpu), at least one interface-unspecific input module, at least one interface-unspecific output module, at least one routing unit and at least one arithmetic unit for processing interface-specific information. The microcontroller is configurable in such a way that the at least one interface-unspecific input module, the at least one interface-unspecific output module, the at least one routing unit and the at least one arithmetic unit for processing interface-specific information fulfill functions corresponding to one of multiple serial interfaces, in particular of spi, uart, lin, can, psi5, flexray, sent, ic2, msc or ethernet..
12/04/14
20140359178
Method for providing a generic interface and microcontroller having a generic interface
A microcontroller for a control unit or a vehicle control unit, includes a central processing unit (cpu), at least one interface-unspecific input module, at least one interface-unspecific output module, at least one routing unit and at least one arithmetic unit for processing interface-specific information. The microcontroller is configurable so that the at least one interface-unspecific input module, the at least one interface-unspecific output module, the at least one routing unit and the at least one arithmetic unit for processing interface-specific information fulfill the functions corresponding to one of multiple serial interfaces, in particular of spi, uart, lin, can, psi5, flexray, sent or ethernet.
12/04/14
20140357195
Encoded information reading terminal with wireless path selecton capability
A portable encoded information reading (eir) terminal for incorporation in a data collection system can comprise a terminal module communicatively coupled to a wireless interface module via a wired interface. The terminal module can include a central processing unit (cpu), a memory, and an encoded information reading (eir) device.
11/27/14
20140351810
Management of supervisor mode execution protection (smep) by a hypervisor
Approaches for enabling supervisor mode execution protection (smep) for a guest operating system which does not support smep. A guest operating system (os), which does not support smep, is executed within a virtual machine.
11/27/14
20140351466
Host/client system having a scalable serial bus interface
According to one exemplary embodiment, a system is provided. The system includes a system bridge, a host module including a central processing unit (cpu) coupled to the system bridge, a scalable serial bus coupled to the system bridge, a client controller coupled to the system bridge via the scalable serial bus, and first and second clients coupled to the client controller.
11/27/14
20140351316
System and method for securing web services
A method and system for securing web services on one or more server computers by one or more client computers, the computers connected to one or more networks through one or more network interfaces, each computer having one or more memories and one or more central processing units (cpus), the system comprising one or more logical expressions that define constraints on one or more service releases; a gateway process receiving service request messages from one or more of the clients for i) identifying the service request message, ii) processing the service request message in accordance with one or more of the logical expressions associated with the requested service and iii) providing access to the requested service if the constraints are satisfied. The system includes an agent process associated with one or more the clients, for receiving service request messages from an associated client, the message destined for a requested service and applying to the received request message one or more of a subset of the logical expressions associated with the requested service for forwarding to the gateway process..
11/27/14
20140350783
System and method for display of information using a vehicle-mount computer
A system and method display information using a vehicle-mount computer. The system includes: (i) a computer touch screen for inputting and displaying information; (ii) a motion detector for detecting vehicle motion; and (iii) a vehicle-mount computer in communication with the computer touch screen and the motion detector.
11/27/14
20140350782
System and method for display of information using a vehicle-mount computer
A system and method displays information using a vehicle-mount computer. The system includes (i) a computer touch screen for inputting and displaying information; (ii) a motion detector for detecting vehicle motion; (iii) a proximity sensor for detecting proximity to an item; and (vi) a vehicle-mount computer in communication with the computer touch screen, the motion detector, and proximity sensor, the vehicle-mount computer including a central processing unit and memory.
11/27/14
20140350739
Sensors for power distribution network and electrical grid monitoring system associated therewith
A network of sensors is associated with a power distribution network. Sensors are positioned at each connecting line in the vicinity of each node of the power distribution network.
11/27/14
20140348182
Time synchronization between nodes of a switched interconnect fabric
A data processing node includes a local clock, a slave port and a time synchronization module. The slave port enables the data processing node to be connected through a node interconnect structure to a parent node having time-based functionality thereof that is operating in accordance with a fabric time of the node interconnect structure.
11/27/14
20140347372
Load balancing between general purpose processors and graphics processors
Disclosed are various embodiments for facilitating load balancing between central processing units (cpus) and graphics processing units (gpus). A request is obtained to execute a first application in one or more computing devices.
11/27/14
20140347371
Graphics processing using dynamic resources
A system has a central processing unit (cpu) and a graphics processing unit (gpu) that includes one or more registers. The gpu can change a resource descriptor in one of the gpu's registers.
11/20/14
20140344590
Electronic device and power management method
An electronic device includes a central processing unit (cpu), a plurality of power driving circuits, and a control unit. The control unit includes a microcontroller and a storage electronically connected to the microcontroller, the microcontroller is electronically connected to the cpu and the power driving circuits.
11/20/14
20140340260
Digital beamforming antenna and datalink array
A method and system for beamforming a multi-element array using time delays is provided. The array includes transmit array elements and receive array elements.
11/13/14
20140337969
Portable computer and operating method thereof
A portable computer and an operating method thereof are provided. The portable computer comprises an input device, a power button, a non-volatile memory, a central processing unit (cpu), an embedded controller (ec), and a chipset.
11/13/14
20140337858
Apparatus and method for adaptive context switching scheduling scheme for fast block input and output
Provided is a method and apparatus for an adaptive context switching for a fast block input/output. The adaptive context switching method may include: requesting, by a process, an input/output device to perform an input/output of data; comparing a central processing unit (cpu) effectiveness based on whether the context switching is performed; and performing the input/output through the context switching to a driver context of the input/output device, or directly performing, by the process, the input/output based on a comparison result of the cpu effectiveness..
11/13/14
20140337313
Executing database queries using multiple processors
A system and a method are disclosed for efficiently executing database queries using a computing device that includes a central processing unit (cpu) and a processing unit based on single instruction multiple thread (simt) architecture, for example, a gpu. A query engine determines a target processing unit to execute a database query based on factors including the type and amount of data processed by the query, the complexity of the query, and the current load on the processing units.
11/13/14
20140337286
Systems and methods for construction field management and operations with building information modeling
The invention generally relates to systems and methods for construction field management and operations with building information modeling. In certain embodiments, the invention provides systems for construction field management and operations, that include a central processing unit (cpu), and storage coupled to the cpu for storing instructions that when executed by the cpu cause the cpu to: encode and map data structures and data sets received from building information modeling software; select particular data structures and data sets relevant to at least one person associated with a construction project; transmit the selected data structures and data sets to a user terminal operated by the person; receive inputs made by the person to the selected data structures and data sets; and synchronize and update the data structures and data sets received from building information modeling software based on the inputs received from the person..
11/13/14
20140336989
Mobile device and microcontroller unit
A microcontroller unit (mcu) characterized by including a buffer is provided. The mcu is a part of a mobile device.
11/13/14
20140334545
Hybrid video encoder apparatus and methods
Methods and apparatus for video processing are disclosed. In one embodiment the work of processing of different types of video frames is allocated between a plurality of computing resources.
11/13/14
20140334486
System and method for broadcasting data to multiple hardware forwarding engines
A method and apparatus of a device that broadcasts data to multiple hardware forwarding engines is described. In an exemplary embodiment, a central processing unit of the device receives the data to broadcast to the plurality of hardware forwarding engines.
11/13/14
20140333638
Power-efficient nested map-reduce execution on a cloud of heterogeneous accelerated processing units
An approach and a method for efficient execution of nested map-reduce framework workloads to take advantage of the combined execution of central processing units (cpus) and graphics processing units (gpus) and lower latency of data access in accelerated processing units (apus) is described. In embodiments, metrics are generated to determine whether a map or reduce function is more efficiently processed on a cpu or a gpu.
11/06/14
20140330451
Apparatus for managing reflecting plate for fruit tree and method using the same
An apparatus and a method for managing a reflecting plate for a fruit tree are disclosed. The apparatus for managing a reflecting plate for a fruit tree includes: a solar sensor configured to sense the amount of sunlight; a fruit-tree database configured to store therein types and locations of fruit trees grown in a growing area; a wireless communication unit configured to perform communications with a robot for moving a reflecting plate for a fruit tree and with the reflecting plate via a wireless communication network; and a central processing unit configured to control the robot so that it installs the reflecting plate in the growing area and to control a reflection angle at which the sunlight is reflected in the reflecting plate, based on at least one of the amount of sunlight, the types and locations..
11/06/14
20140328013
Music book
A portable computer unlike conventional computers in that it has no computer base. It functions as and resembles a book.
11/06/14
20140327569
Radar weather detection for a wind turbine
A radar system for a wind turbine is provided. The radar system comprises a first radar unit (42) and a control unit (41) arranged to receive an output from the radar unit, the control unit comprising a central processing unit.
10/30/14
20140325189
Query sampling information instruction
A measurement sampling facility takes snapshots of the central processing unit (cpu) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the cpu. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof.
10/30/14
20140325180
Electronic system, central processing unit expansion apparatus, portable electronic apparatus and processing method
An electronic system includes a central processing unit (cpu) expansion apparatus and a portable electronic apparatus. The cpu expansion apparatus has a first cpu connector and a first cpu.
10/30/14
20140324698
Method, device, add-on and secure element for conducting a secured financial transaction on a device
A device, an add-on and a secure element for conducting a secured financial transaction are disclosed. The device comprises a central processing unit; a communication interface for establishing a communication between the device and a financial institution related to a financial account; an interface for acquiring data relating to the financial account; the secure element for processing at least a portion of the data relating to the financial account acquired by the interface; and control logic for acquiring a purchase amount to be debited from the financial account and for obtaining a transaction authorization from the financial institution related to the financial account, the transaction authorization being based, at least partially, on data processed solely by the secure element independently of data processed by the central processing unit.
10/30/14
20140324233
Fluid control device
The present invention is intended to inhibit a communication program from crashing in the case where a power source is turned off while writing or rewriting of a measurement control program from an external device is performed by a communication part, and includes: a first recording part for storing the communication program for controlling the communication part; a second recording part for storing a measurement control program for controlling the measurement control part; and a central processing unit. In this configuration, the communication program stored in the first recording part is configured to be unrewritable by the central processing unit and the measurement control program stored in the second recording part is configured to be rewritable by the central processing unit..
10/30/14
20140321529
Video encoding and/or decoding method and video encoding and/or decoding apparatus
Disclosed is a video processing apparatus. The video processing apparatus includes a video central processing unit to communicate with a host and to parse parameter information or slice header information from video data input from the host, and a plurality of video processing units to process a video based on the parsed information according to control by the central video processing unit, wherein the video central processing unit determines an entry point of a video bitstream to be allocated to each of the video processing units in view of a number of pixels to be processed by each video processing unit..
10/30/14
20140321457
Packet handler for high speed data networks
An improved packet handler for voip cable modems and other high-speed digital devices includes a direct communication link via hardware among internal processing components. Incoming and outgoing digital information packets are filtered into mac packets, voice pdu packets, and non-voice pdu packets, such that priority can be given to relaying voice packets and minimizing potential voice delay within the cable network.
10/30/14
20140320523
Tessellation of two-dimensional curves using a graphics pipeline
Methods, systems, and computer-storage media for efficiently tessellating two dimensional (2-d) curves using a graphics pipeline running on a graphics processing unit (gpu) are provided. A central processing unit (cpu) converts a geometry having one or more 2-d curves into an intermediate tessellation having at least one bezier fan with a fan origin and four control points.
10/23/14
20140317325
Warning track interruption facility
A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources.
10/23/14
20140313214
Subbuffer objects
A method and an apparatus for a parallel computing program using subbuffers to perform a data processing task in parallel among heterogeneous compute units are described. The compute units can include a heterogeneous mix of central processing units (cpus) and graphic processing units (gpus).
10/23/14
20140313136
Systems and methods for finger pose estimation on touchscreen devices
Described are systems and methods for estimating finger pose of a user during a tactile input event. In one implementation, the system incorporates: a touch-sensitive display device configured to detect a tactile event and to determine a contact point of an object and the touch-sensitive display device, the contact point associated with the tactile event; a camera configured to capture an image of an area proximal to the surface of the touch-sensitive display device; and a central processing unit configured, in response to the detection of the tactile event, to determine information on a pose of the object based on the captured image and the determined contact point..
10/16/14
20140310808
Detection of stealthy malware activities with traffic causality and scalable triggering relation discovery
A computer system for distinguishing user-initiated network traffic from malware-initiated network traffic comprising at least one central processing unit (cpu) and a memory communicatively coupled to the cpu. The memory includes a program code executable by the cpu to monitor individual network events to determine for an individual network event whether the event has a legitimate root-trigger.
10/16/14
20140310695
Identification and translation of program code executable by a graphical processing unit (gpu)
A device receives program code, and receives size/type information associated with inputs to the program code. The device determines, prior to execution of the program code and based on the input size/type information, a portion of the program code that is executable by a graphical processing unit (gpu), and determines, prior to execution of the program code and based on the input size/type information, a portion of the program code that is executable by a central processing unit (cpu).
10/16/14
20140310490
Heterogeneous memory die stacking for energy efficient computing
Methods and apparatus to provide heterogeneous memory die stacking for energy efficient computing are described. In one embodiment, a phase change memory with switch (pcms) die is coupled to a dynamic random access memory (dram) die and a central processing unit (cpu) die.
10/16/14
20140310475
Atomic execution over accesses to multiple memory locations in a multiprocessor system
A method and central processing unit supporting atomic access of shared data by a sequence of memory access operations. A processor status flag is reset.
10/16/14
20140306971
Intra-frame timestamps for tile-based rendering
This disclosure describes techniques for supporting intra-frame timestamps in a graphics system that performs tile-based rendering. The techniques for supporting intra-frame timestamps may involve generating a timestamp value that is indicative of a point in time based on a plurality of per-bin timestamp values that are generated by a graphics processing unit (gpu) while performing tile-based rendering for a graphics frame.
10/09/14
20140304712
Method for operating task and electronic device thereof
A method and a device for operation a task in an electronic device are provided. The method for operating a task in an electronic device includes generating at least one task on a protocol layer basis based on a work to process, executing at least one task generated on a layer basis through at least one central processing unit (cpu), determining whether a workload to process is changed, and changing, if the workload to process is changed, a workload of the executing of the at least one task..
10/09/14
20140304460
Multiprocessor system with independent direct access to bulk solid state memory resources
A system includes a collection of central processing units, where each central processing unit is connected to at least one other central processing unit and a root path into at least 10 tera bytes of solid state memory resources. Each central processing unit directly accesses solid state memory resources without swapping solid state memory contents into main memory..
10/09/14
20140301199
Methods, systems, and computer program products for processing a packet
A system for processing a packet may include, for each of a network interface controller and a central processing unit, a measurement of the processing time, a determination of the amount of energy consumed to process a unit of information in the packet, and a measurement of the load. A user may provide the system with signals to perform networking processes for the packet in a manner to reduce the processing time of the system or in a manner to reduce the amount of energy consumed by the system for processing the packet.
10/09/14
20140298902
System and method for environmental measurements
A system for conducting measurements in an environment of a fluid containment and for displaying said measurements in real time is disclosed. The system contains a plurality of sensors including a distance sensor, a gyroscope and optionally a rainfall gauge and a methane sensor.
10/02/14
20140298336
Central processing unit, information processing apparatus, and intra-virtual-core register value acquisition method
To provide a new operation verification method for an information processing flow, a central processing unit capable of building a plurality of virtual cores on a physical core includes: an element or part for executing, on an own virtual core, or causing another virtual core on the same physical core to execute, a reference instruction of directly referring to a current register value used by an arbitrary virtual core from the another virtual core without influence on an execution context of the arbitrary virtual core; and an element or part for switching a permission or authorization for executing the reference instruction of referring to the register value among the plurality of virtual cores.. .
10/02/14
20140298059
Electronic apparatus and associated power management method
An electronic apparatus is provided. The electronic apparatus includes a dynamic random access memory (dram), a power integrated circuit (ic), and a central processing unit (cpu).
10/02/14
20140298040
Systems, methods and apparatuses for secure storage of data using a security-enhancing chip
A computer processor and a security enhancing chip may be provided. In one aspect, the computer processor may comprise a storage for storing an encryption key, a central processing unit (cpu) configured to execute one or more software programs, and a circuit configured to calculate a hash function to generate a hash value for data loaded into the computer processor and generate an authentication token for a request initiated by a software program running on the cpu.
10/02/14
20140297963
Processing device
When an invalidation request is inputted from another processing device, a cache controller registers a set of an invalidation request address which the invalidation request has and an identifier of the other processing device which outputted the invalidation request in an invalidation history table. When a central processing unit attempts to read data at a first address not stored in a cache memory, if the first address is registered in the invalidation history table, the cache controller outputs a coherent read request containing the first address to the other processing device indicated by the identifier of the other processing device which outputted the invalidation request corresponding to the first address, or if the first address is not registered in the invalidation history table, the cache controller outputs a coherent read request containing the first address to all other processing devices..
10/02/14
20140297958
System and method for updating an instruction cache following a branch instruction in a semiconductor device
A semiconductor device includes a memory for storing a plurality of instructions therein, an instruction queue which temporarily stores the instructions fetched from the memory therein, a central processing unit which executes the instruction supplied from the instruction queue, an instruction cache which stores therein the instructions executed in the past by the central processing unit, and a control circuit which controls fetching of each instruction. When the central processing unit executes a branch instruction, and an instruction of a branch destination is being in the instruction cache and an instruction following the instruction of the branch destination is stored in the instruction queue, the control circuit causes the instruction queue to fetch the instruction of the branch destination from the instruction cache and causes the instruction queue not to fetch the instruction following the instruction of the branch destination..
10/02/14
20140297918
Buffer cache apparatus, journaling file system and journaling method for incorporating journaling features within non-volatile buffer cache
Disclosed herein are a buffer cache apparatus, a journaling file system, and a journaling method capable of incorporating journaling features based on nonvolatile memory. The buffer cache apparatus provides a data buffering function between a central processing unit (cpu) and storage.
10/02/14
20140294240
Driver recognition system and recognition method for vehicle
A driver recognition system for a vehicle includes a camera taking an image of a driver's foot, and a central processing unit receiving image information from the camera, analyzing the image information, and delivering a signal in accordance with an analyzed result. A control unit is installed to receive the signal delivered from the central processing unit and output a control command so as to set a driving environment and a driving mode in accordance with the received signal.


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Central Processing Unit topics: Central Processing Unit, Speech Recognition, User Interface, Storage Device, Alarm System, Constraints, Electronic Device, Embedded System, Application Program, Functional Specification, Control Flow, Application Programming Interface, Data Storage, Optical Fiber, Solid Structure

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