|| List of recent Central Processing Unit-related patents
| Electronic device and power management method|
An electronic device includes a central processing unit (cpu), a plurality of power driving circuits, and a control unit. The control unit includes a microcontroller and a storage electronically connected to the microcontroller, the microcontroller is electronically connected to the cpu and the power driving circuits.
| Digital beamforming antenna and datalink array|
A method and system for beamforming a multi-element array using time delays is provided. The array includes transmit array elements and receive array elements.
|Portable computer and operating method thereof|
A portable computer and an operating method thereof are provided. The portable computer comprises an input device, a power button, a non-volatile memory, a central processing unit (cpu), an embedded controller (ec), and a chipset.
|Apparatus and method for adaptive context switching scheduling scheme for fast block input and output|
Provided is a method and apparatus for an adaptive context switching for a fast block input/output. The adaptive context switching method may include: requesting, by a process, an input/output device to perform an input/output of data; comparing a central processing unit (cpu) effectiveness based on whether the context switching is performed; and performing the input/output through the context switching to a driver context of the input/output device, or directly performing, by the process, the input/output based on a comparison result of the cpu effectiveness..
|Executing database queries using multiple processors|
A system and a method are disclosed for efficiently executing database queries using a computing device that includes a central processing unit (cpu) and a processing unit based on single instruction multiple thread (simt) architecture, for example, a gpu. A query engine determines a target processing unit to execute a database query based on factors including the type and amount of data processed by the query, the complexity of the query, and the current load on the processing units.
|Systems and methods for construction field management and operations with building information modeling|
The invention generally relates to systems and methods for construction field management and operations with building information modeling. In certain embodiments, the invention provides systems for construction field management and operations, that include a central processing unit (cpu), and storage coupled to the cpu for storing instructions that when executed by the cpu cause the cpu to: encode and map data structures and data sets received from building information modeling software; select particular data structures and data sets relevant to at least one person associated with a construction project; transmit the selected data structures and data sets to a user terminal operated by the person; receive inputs made by the person to the selected data structures and data sets; and synchronize and update the data structures and data sets received from building information modeling software based on the inputs received from the person..
|Mobile device and microcontroller unit|
A microcontroller unit (mcu) characterized by including a buffer is provided. The mcu is a part of a mobile device.
|Hybrid video encoder apparatus and methods|
Methods and apparatus for video processing are disclosed. In one embodiment the work of processing of different types of video frames is allocated between a plurality of computing resources.
|System and method for broadcasting data to multiple hardware forwarding engines|
A method and apparatus of a device that broadcasts data to multiple hardware forwarding engines is described. In an exemplary embodiment, a central processing unit of the device receives the data to broadcast to the plurality of hardware forwarding engines.
|Power-efficient nested map-reduce execution on a cloud of heterogeneous accelerated processing units|
An approach and a method for efficient execution of nested map-reduce framework workloads to take advantage of the combined execution of central processing units (cpus) and graphics processing units (gpus) and lower latency of data access in accelerated processing units (apus) is described. In embodiments, metrics are generated to determine whether a map or reduce function is more efficiently processed on a cpu or a gpu.
|Apparatus for managing reflecting plate for fruit tree and method using the same|
An apparatus and a method for managing a reflecting plate for a fruit tree are disclosed. The apparatus for managing a reflecting plate for a fruit tree includes: a solar sensor configured to sense the amount of sunlight; a fruit-tree database configured to store therein types and locations of fruit trees grown in a growing area; a wireless communication unit configured to perform communications with a robot for moving a reflecting plate for a fruit tree and with the reflecting plate via a wireless communication network; and a central processing unit configured to control the robot so that it installs the reflecting plate in the growing area and to control a reflection angle at which the sunlight is reflected in the reflecting plate, based on at least one of the amount of sunlight, the types and locations..
A portable computer unlike conventional computers in that it has no computer base. It functions as and resembles a book.
|Radar weather detection for a wind turbine|
A radar system for a wind turbine is provided. The radar system comprises a first radar unit (42) and a control unit (41) arranged to receive an output from the radar unit, the control unit comprising a central processing unit.
|Query sampling information instruction|
A measurement sampling facility takes snapshots of the central processing unit (cpu) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the cpu. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof.
|Electronic system, central processing unit expansion apparatus, portable electronic apparatus and processing method|
An electronic system includes a central processing unit (cpu) expansion apparatus and a portable electronic apparatus. The cpu expansion apparatus has a first cpu connector and a first cpu.
|Method, device, add-on and secure element for conducting a secured financial transaction on a device|
A device, an add-on and a secure element for conducting a secured financial transaction are disclosed. The device comprises a central processing unit; a communication interface for establishing a communication between the device and a financial institution related to a financial account; an interface for acquiring data relating to the financial account; the secure element for processing at least a portion of the data relating to the financial account acquired by the interface; and control logic for acquiring a purchase amount to be debited from the financial account and for obtaining a transaction authorization from the financial institution related to the financial account, the transaction authorization being based, at least partially, on data processed solely by the secure element independently of data processed by the central processing unit.
|Fluid control device|
The present invention is intended to inhibit a communication program from crashing in the case where a power source is turned off while writing or rewriting of a measurement control program from an external device is performed by a communication part, and includes: a first recording part for storing the communication program for controlling the communication part; a second recording part for storing a measurement control program for controlling the measurement control part; and a central processing unit. In this configuration, the communication program stored in the first recording part is configured to be unrewritable by the central processing unit and the measurement control program stored in the second recording part is configured to be rewritable by the central processing unit..
|Video encoding and/or decoding method and video encoding and/or decoding apparatus|
Disclosed is a video processing apparatus. The video processing apparatus includes a video central processing unit to communicate with a host and to parse parameter information or slice header information from video data input from the host, and a plurality of video processing units to process a video based on the parsed information according to control by the central video processing unit, wherein the video central processing unit determines an entry point of a video bitstream to be allocated to each of the video processing units in view of a number of pixels to be processed by each video processing unit..
|Packet handler for high speed data networks|
An improved packet handler for voip cable modems and other high-speed digital devices includes a direct communication link via hardware among internal processing components. Incoming and outgoing digital information packets are filtered into mac packets, voice pdu packets, and non-voice pdu packets, such that priority can be given to relaying voice packets and minimizing potential voice delay within the cable network.
|Tessellation of two-dimensional curves using a graphics pipeline|
Methods, systems, and computer-storage media for efficiently tessellating two dimensional (2-d) curves using a graphics pipeline running on a graphics processing unit (gpu) are provided. A central processing unit (cpu) converts a geometry having one or more 2-d curves into an intermediate tessellation having at least one bezier fan with a fan origin and four control points.
|Warning track interruption facility|
A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources.
A method and an apparatus for a parallel computing program using subbuffers to perform a data processing task in parallel among heterogeneous compute units are described. The compute units can include a heterogeneous mix of central processing units (cpus) and graphic processing units (gpus).
|Systems and methods for finger pose estimation on touchscreen devices|
Described are systems and methods for estimating finger pose of a user during a tactile input event. In one implementation, the system incorporates: a touch-sensitive display device configured to detect a tactile event and to determine a contact point of an object and the touch-sensitive display device, the contact point associated with the tactile event; a camera configured to capture an image of an area proximal to the surface of the touch-sensitive display device; and a central processing unit configured, in response to the detection of the tactile event, to determine information on a pose of the object based on the captured image and the determined contact point..
|Detection of stealthy malware activities with traffic causality and scalable triggering relation discovery|
A computer system for distinguishing user-initiated network traffic from malware-initiated network traffic comprising at least one central processing unit (cpu) and a memory communicatively coupled to the cpu. The memory includes a program code executable by the cpu to monitor individual network events to determine for an individual network event whether the event has a legitimate root-trigger.
|Identification and translation of program code executable by a graphical processing unit (gpu)|
A device receives program code, and receives size/type information associated with inputs to the program code. The device determines, prior to execution of the program code and based on the input size/type information, a portion of the program code that is executable by a graphical processing unit (gpu), and determines, prior to execution of the program code and based on the input size/type information, a portion of the program code that is executable by a central processing unit (cpu).
|Heterogeneous memory die stacking for energy efficient computing|
Methods and apparatus to provide heterogeneous memory die stacking for energy efficient computing are described. In one embodiment, a phase change memory with switch (pcms) die is coupled to a dynamic random access memory (dram) die and a central processing unit (cpu) die.
|Atomic execution over accesses to multiple memory locations in a multiprocessor system|
A method and central processing unit supporting atomic access of shared data by a sequence of memory access operations. A processor status flag is reset.
|Intra-frame timestamps for tile-based rendering|
This disclosure describes techniques for supporting intra-frame timestamps in a graphics system that performs tile-based rendering. The techniques for supporting intra-frame timestamps may involve generating a timestamp value that is indicative of a point in time based on a plurality of per-bin timestamp values that are generated by a graphics processing unit (gpu) while performing tile-based rendering for a graphics frame.
|Method for operating task and electronic device thereof|
A method and a device for operation a task in an electronic device are provided. The method for operating a task in an electronic device includes generating at least one task on a protocol layer basis based on a work to process, executing at least one task generated on a layer basis through at least one central processing unit (cpu), determining whether a workload to process is changed, and changing, if the workload to process is changed, a workload of the executing of the at least one task..
|Multiprocessor system with independent direct access to bulk solid state memory resources|
A system includes a collection of central processing units, where each central processing unit is connected to at least one other central processing unit and a root path into at least 10 tera bytes of solid state memory resources. Each central processing unit directly accesses solid state memory resources without swapping solid state memory contents into main memory..
|Methods, systems, and computer program products for processing a packet|
A system for processing a packet may include, for each of a network interface controller and a central processing unit, a measurement of the processing time, a determination of the amount of energy consumed to process a unit of information in the packet, and a measurement of the load. A user may provide the system with signals to perform networking processes for the packet in a manner to reduce the processing time of the system or in a manner to reduce the amount of energy consumed by the system for processing the packet.
|System and method for environmental measurements|
A system for conducting measurements in an environment of a fluid containment and for displaying said measurements in real time is disclosed. The system contains a plurality of sensors including a distance sensor, a gyroscope and optionally a rainfall gauge and a methane sensor.
|Central processing unit, information processing apparatus, and intra-virtual-core register value acquisition method|
To provide a new operation verification method for an information processing flow, a central processing unit capable of building a plurality of virtual cores on a physical core includes: an element or part for executing, on an own virtual core, or causing another virtual core on the same physical core to execute, a reference instruction of directly referring to a current register value used by an arbitrary virtual core from the another virtual core without influence on an execution context of the arbitrary virtual core; and an element or part for switching a permission or authorization for executing the reference instruction of referring to the register value among the plurality of virtual cores.. .
|Electronic apparatus and associated power management method|
An electronic apparatus is provided. The electronic apparatus includes a dynamic random access memory (dram), a power integrated circuit (ic), and a central processing unit (cpu).
|Systems, methods and apparatuses for secure storage of data using a security-enhancing chip|
A computer processor and a security enhancing chip may be provided. In one aspect, the computer processor may comprise a storage for storing an encryption key, a central processing unit (cpu) configured to execute one or more software programs, and a circuit configured to calculate a hash function to generate a hash value for data loaded into the computer processor and generate an authentication token for a request initiated by a software program running on the cpu.
When an invalidation request is inputted from another processing device, a cache controller registers a set of an invalidation request address which the invalidation request has and an identifier of the other processing device which outputted the invalidation request in an invalidation history table. When a central processing unit attempts to read data at a first address not stored in a cache memory, if the first address is registered in the invalidation history table, the cache controller outputs a coherent read request containing the first address to the other processing device indicated by the identifier of the other processing device which outputted the invalidation request corresponding to the first address, or if the first address is not registered in the invalidation history table, the cache controller outputs a coherent read request containing the first address to all other processing devices..
|System and method for updating an instruction cache following a branch instruction in a semiconductor device|
A semiconductor device includes a memory for storing a plurality of instructions therein, an instruction queue which temporarily stores the instructions fetched from the memory therein, a central processing unit which executes the instruction supplied from the instruction queue, an instruction cache which stores therein the instructions executed in the past by the central processing unit, and a control circuit which controls fetching of each instruction. When the central processing unit executes a branch instruction, and an instruction of a branch destination is being in the instruction cache and an instruction following the instruction of the branch destination is stored in the instruction queue, the control circuit causes the instruction queue to fetch the instruction of the branch destination from the instruction cache and causes the instruction queue not to fetch the instruction following the instruction of the branch destination..
|Buffer cache apparatus, journaling file system and journaling method for incorporating journaling features within non-volatile buffer cache|
Disclosed herein are a buffer cache apparatus, a journaling file system, and a journaling method capable of incorporating journaling features based on nonvolatile memory. The buffer cache apparatus provides a data buffering function between a central processing unit (cpu) and storage.
|Driver recognition system and recognition method for vehicle|
A driver recognition system for a vehicle includes a camera taking an image of a driver's foot, and a central processing unit receiving image information from the camera, analyzing the image information, and delivering a signal in accordance with an analyzed result. A control unit is installed to receive the signal delivered from the central processing unit and output a control command so as to set a driving environment and a driving mode in accordance with the received signal.
|Memory bitcell clusters employing localized generation of complementary bitlines to reduce memory area, and related systems and methods|
Embodiments disclosed include memory bitcell clusters employing localized generation of complementary bitlines to reduce memory area. The memory bitcell clusters disclosed may be static random access memory (sram) used as central processing unit (cpu) register files.
|Microcontroller and method of controlling the same|
A microcontroller includes a cpu (central processing unit), a data input unit, and an oscillator that supplies a clock signal in response to operational modes of the microcontroller. The operational modes include a stop mode, a snooze mode and a run mode, in the stop mode, the oscillator and the cpu are stopped, in the run mode, the cpu and the data input unit operate using the clock signal supplied from the oscillator, and in the snooze mode, the oscillator starts and supplies the clock signal to the data input unit when the data input unit receives first data, and the microcontroller switches to the run mode after the data input unit receives second data using the clock signal..
|Methods and apparatuses for switch power down|
The discussion makes reference to methods and apparatuses for message-driven switch power, power control, and central processing unit (cpu)-assisted full switch power-down. The link layer in computer networking can be used to save power in switching elements..
|Gpu and encoding apparatus for virtual machine environments|
A system encodes an image for a remote client. A graphics processor unit (gpu) renders an image in response to graphics commands received from a central processing unit (cpu) virtual machine.
|Method for reducing effective raw bit error rate in multi-level cell nand flash memory|
A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (cpu), and a flash controller coupled to the cpu, the cpu being operable to pair a lower with an upper page.
|Method and system for key performance indicators elicitation with incremental data decycling for database management system|
A method for processing signals from a data server system including generating, by a monitoring module on a monitoring facility, a plurality of frequency data items, where the monitoring facility comprises a central processing unit, obtaining, by the monitoring module, a first signal value from the data server system, where the signal value is a measurement of an element of the data server system, and calculating a plurality of fit errors for the plurality of frequency data items using the first signal value. The method further includes selecting a frequency data item of the plurality of frequency data items with a lowest fit error to obtain a selected frequency data item, removing a cyclic component of the first signal value using the selected frequency data item to obtain a first processed signal value, and displaying the first processed signal value on a graph..
|Determine voltage supplied to a core|
Techniques for determining the voltage to be supplied to a core of a central processing unit are provided. A core of a central processing unit is monitored for errors.
|Systems, methods and apparatuses for using a secure non-volatile storage with a computer processor|
The systems, methods and apparatuses described herein provide a system for accessing data stored securely external of a computer processor. In one aspect, the computer processor may comprise a central processing unit (cpu) and a memory controller.
|Use case based reconfiguration of co-processor cores for general purpose processors|
A wireless mobile device includes a configurable co-processor core(s). The wireless mobile device also includes a multi-core central processing unit coupled to a memory and the configurable co-processor core(s).
|Dual boot panel swap mechanism|
A central processing unit with dual boot capabilities is disclosed comprising an instruction memory further comprising a first and second memory area which are configured to be individually programmable, wherein first and second memory area can be assigned to an active memory from which instructions are executed and an inactive memory, respectively. The instruction set for the central processing unit comprises a dedicated instruction that allows to perform a swap from the an active memory area to an inactive memory area, wherein the swap is performed by executing the dedicated instruction in the active memory followed by a program flow change instruction in the active memory, whereupon the inactive memory becomes the new active memory and the active memory becomes the new inactive memory and execution of instructions continues in the new active memory..
|Eliminating redundant synchronization barriers in instruction processing circuits, and related processor systems, methods, and computer-readable media|
Embodiments disclosed herein include eliminating redundant synchronization barriers from execution pipelines in instruction processing circuits. Related processor systems, methods, and computer-readable media are also disclosed.
|Opportunistic migration of memory pages in a unified virtual memory system|
Techniques are disclosed for transitioning a memory page between memories in a virtual memory subsystem. A unified virtual memory (uvm) driver detects a page fault in response to a memory access request associated with a first memory page, where a local page table does not include an entry corresponding to a virtual memory address included in the memory access request.
|Managing wait states for memory access|
A latch signal is received from a non-volatile memory device that is indicative of a current access time for the non-volatile memory device. The access time represents an amount of time required for the non-volatile memory device to make data available responsive to a request for data.
|Self-organizing disk (sod)|
System and methods for storage object distribution using a universal distributed storage (uds) system. An embodiment uds includes server nodes and a header server in communication with the server nodes.
|Method employing at least one central processing unit (cpu)|
The invention relates to a method which employs at least one cpu (10, 12, 14, 16) that has at least one network interface (18, 20, 22, 24) and one messaging program (26, 28, 30, 32), which receives a message (34) with a message text (36) and a file attachment (38) via the network interface (18, 20, 22, 24) in at least one operating condition. According to the invention, the messaging program (26, 28, 30, 32) automatically saves the file attachment (38), separately from the message text (36) of the message (34), at a memory location that is based upon the path information (40) of the message (34)..
|Motor vehicle lift control system|
An automatic motor vehicle lift control system responds to a motor vehicle wheelie event when a motor vehicle front lifts off from an operating surface. It functions to reduce power output from an engine of a vehicle in wheelie to prevent an accident.
|Reduced central processing unit load and memory usage battery state of charge calculation|
A vehicle having a battery pack with cells grouped into subsets and at least one controller programmed to charge and discharge the battery pack is disclosed. A control output is generated based on a pack state of charge derived from each cell's initial state of charge at vehicle activation and an electric charge accumulated or spent by less than all of the cells of each of the subsets since vehicle activation.
|Systems and methods for predicting impact of a catheter on curvature of a vessel|
The invention generally relates to systems and methods for predicting impact of a catheter on curvature of a vessel. In certain aspects, the invention provides a system for predicting impact of a catheter on curvature of a vessel.
|Device configuration for supporting a patient oxygenation test|
A physiological monitor device includes a central processing unit (cpu) that is configured to control operation of the device, a display screen, and one or more computer readable data storage media storing software instructions that, when executed by the cpu, cause the device to: create or modify a patient profile, select a patient test, store one or more test parameters selected or entered for the patient test, store one or more thresholds selected or entered for at least one of the test parameters, store one or more instructions for the patient, start the test, display test results while the test is in progress, determine whether any of the test parameters exceed limits set by the one or more thresholds, take one or more actions when it is determined that one or more of the test parameters exceed the limits set by the one or more thresholds, provide a summary and analysis of the test results, and send the test results to a computing device.. .
|System for cooling multiple in-line central processing units in a confined enclosure|
A system for cooling multiple in-line cpus in a confined enclosure is provided. In an embodiment, the system may include a front cpu and a front heat sink that may be coupled to the front cpu.
|Apparatus and method for testing working voltage of cpu|
An apparatus for testing working voltage of a central processing unit (cpu) includes a programmable logic device (pld) having a dummy load, a voltage regulating controller, a cpu socket and a south bridge. The cpu socket is electrically connected to the voltage regulating controller via a series voltage identification (svid) bus.
An electronic lock is disclosed, which generally comprises a main lock body, a control mechanism being cooperatively connected with the main lock body, and at least one portable communication device. The control mechanism includes a connection interface connecting to the main lock body, a central processing unit connecting to the connection interface, a communication unit connecting to the central processing unit, and a power supply unit connecting to the central processing unit.
|User authorization and presence detection in isolation from interference from and control by host central processing unit and operating system|
An embodiment may include circuitry to be included, at least in part, in a host. The host may include at least one host central processing unit (cpu) to execute, at least in part, at least one host operating system (os).
|Data security method and electronic device implementing the same|
A method and an apparatus that may safely secure data in an electronic device including a computing resource, that is, software (for example, an operating system) and hardware (for example, a memory and a central processing unit (cpu)) for operating the electronic device are provided. The method includes receiving a request for an application key from a data generation application or a proxy application that executes encryption of data in place of the data generation application, generating an application key using an application identification (id) corresponding to the data generation application and a security key stored in a secure area of the electronic device, in response to the request, and encrypting data using the generated application key..
|System-on-chip and method of operating the same|
A system on chip (soc) includes a central processing unit (cpu), an intellectual property (ip) block, and a memory management unit (mmu). The cpu is configured to set a prefetch direction corresponding to a working set of data.