|| List of recent Central Processing Unit-related patents
|User authorization and presence detection in isolation from interference from and control by host central processing unit and operating system|
An embodiment may include circuitry to be included, at least in part, in a host. The host may include at least one host central processing unit (cpu) to execute, at least in part, at least one host operating system (os).
|Data security method and electronic device implementing the same|
A method and an apparatus that may safely secure data in an electronic device including a computing resource, that is, software (for example, an operating system) and hardware (for example, a memory and a central processing unit (cpu)) for operating the electronic device are provided. The method includes receiving a request for an application key from a data generation application or a proxy application that executes encryption of data in place of the data generation application, generating an application key using an application identification (id) corresponding to the data generation application and a security key stored in a secure area of the electronic device, in response to the request, and encrypting data using the generated application key..
|System-on-chip and method of operating the same|
A system on chip (soc) includes a central processing unit (cpu), an intellectual property (ip) block, and a memory management unit (mmu). The cpu is configured to set a prefetch direction corresponding to a working set of data.
|Enhanced dump data collection from hardware fail modes|
An approach is provided for collecting data for diagnosing a failure of a computer hardware device. After an indication of the failure of the computer hardware device that results in a full system crash is received, an address translation table of a central processing unit of the computer hardware device is collected.
|Multi-level cpu high current protection|
Methods and apparatus relating to multi-level cpu (central processing unit) high current protection are described. In one embodiment, different workloads may be assigned different license types and/or weights based on micro-architectural events (such as uop (micro-operation) types and sizes) and/or data types.
|Extensible firmware interface external graphic card, mainframe system, and extensible firmware interface bios booting method|
A central processing unit of a mainframe system is configured to load a physical graphic card driver into a memory of the mainframe system for performing a display function when the mainframe system is not connected to an extensible firmware interface (efi) external graphic card. The central processing unit is further configured to load a virtual graphic card driver into the memory of the mainframe system for performing the display function when the mainframe system is connected to the efi external display card..
|Multi-core processor, controlling method thereof and computer system with such processor|
A multi-core processor includes m cores. If the multi-core processor is operated under a non-multiprocessing support operating system, only a single core is configured as a central processing unit and n cores are configured as co-processors, wherein m and n are positive integers, and n is smaller than m..
|Configuration snooping bridge|
Systems and methods for configuration snooping are provided. A bridge identifies an initialization message of a central processing unit (cpu) for a device that is downstream of a primary interface of the bridge.
|Integrity checking and selective deduplication based on network parameters|
An approach for managing a data package is provided. Network utilization is determined to exceed a threshold.
|System for real time continuous data processing for investment portfolios|
A real time continuous data inputting, processing, scanning and displaying system for financial data and inputting variable boundaries of data for a variety of desired data characteristics. The process displays when the data characteristics fall outside their respective variable boundaries.
|Acoustic sensor apparatus and acoustic camera for using mems microphone array|
An acoustic camera for using a mems microphone array comprises: an acoustic sensor apparatus (30) comprising a print circuit board (20) on which the plural of mems microphone (10) are mounted, to send signals for the detected sound to a data collection unit (40); a data collection unit (40) connected to the acoustic sensor apparatus (30), which samples analog signals related to sound transmitted from the acoustic sensor apparatus (30) to transform into digital signals and transmit them to the central processing unit (40); a central processing unit (50) connected to the data collection unit (40), which calculates noise level based on digital signals related to sound transmitted from the data collection unit (40); and a display unit (60) which is connected to the central processing unit (50), which displays in color the noise level calculated at the central processing unit.. .
|Image subsystem and image processing system including the same|
An image processing system includes a hardware block and a central processing unit (cpu). The hardware block receives a first image and generates a first feature value and a first segmented image from the first image.
|Fine-grained cpu-gpu synchronization using full/empty bits|
A heterogeneous computing system includes a central processing unit (cpu) and a graphics processing unit (gpu). The cpu and the gpu are synchronized using a data-based synchronization scheme, wherein offloading of a kernel from the cpu to the gpu is coordinated based upon the data associated with the kernel transferred between the cpu and the gpu.
|Pulse transponder countermeasure|
A pulse transponder countermeasure device, comprising: a central processing unit (cpu); an optical receiver adapted to receive detection signals from a speed measuring device; at least one optical transmitter adapted to transmit jamming signals to the speed measuring device; at least one software controlled driver configured to drive the optical transmitter and memory storing a database of measuring devices signature signals and reflective signals, the cpu configured to identify the speed measuring device in its database according to the received detection signal's signature and calculate a response time for sending a jamming signal to the speed measuring device so as to change the speed perceived by the speed measurement device.. .
|Password audit system|
A password audit system is provided for determining the strength of user passwords in a computer system, application or network to which users have access via a user identification and password. The password audit system may include: an interface for establishing a data connection between the password audit system and the computer system, application or network, configured to retrieve cipher text user passwords stored thereon; a central processing unit, configured to successively generate different plain text passwords, encode them into corresponding cipher text passwords, and compare the encoded cipher text passwords to a given one of the retrieved cipher text passwords, until a match is found or a predetermined time has elapsed; and data storage means for storing data relating to the strength of the user passwords, the strength being dependent on the employed method to generate the different plain text passwords and/or the time needed to find a match..
|Application programming interfaces for data parallel computing on multiple processors|
A method and an apparatus for a parallel computing program calling apis (application programming interfaces) in a host processor to perform a data processing task in parallel among compute units are described. The compute units are coupled to the host processor including central processing units (cpus) and graphic processing units (gpus).
|Managing the translation look-aside buffer (tlb) of an emulated machine|
A mechanism is provided for managing the translation look-aside buffer (tlb) of an emulated computer, in which an extension to the tlb is provided so as to improve virtual address translation capacity for the emulated central processing unit (cpu).. .
A graphics system may include one or more processing units for processing a current display frame, each processing unit including a plurality of parameter registers for storing parameter settings used in processing the current display frame. A parameter buffer in the graphics system may store frame packets, with each frame packet containing information corresponding to parameter settings to be used for at least one display frame.
|System for transferring the operation of a device to an external apparatus|
A system and method for transferring the operation of an image device to an external apparatus includes an image device, the image device transmitting an image to a liquid crystal display (lcd) via a signal transmission; a central processing unit (cpu), the cpu being built in the image device and installed with a software driver program, the software driver program enabling the cpu to magnify and display the image on the lcd via the signal transmission; and a keyboard, the keyboard being connected with the cpu for controlling the software driver program installed in the cpu, the cursor of the keyboard being displayed at a relative position of the image, the keyboard being adapted for direct operating on the image corresponding to the operation of the image device. The present invention is convenient in use, quick and easy for operation, and convenient for portability..
|Dynamic allocation of computing resources in remote gaming environment|
Embodiments of the present invention monitor and dynamically allocate computing resources to game sessions running within a game service. A game service provides a remote gaming environments to which users connect over a wide area network, such as the internet.
|System and method for managing continued attention to distance-learning content|
Management of a user's continued attention to distance learning content using a general purpose computer having a central processing unit, an operating system configured to run multiple program applications concurrently, and a player suitable for presenting the distance learning content. A distance learning module comprises code executable on the central processing unit, as one of the multiple program applications.
|Method and device for controlling uplink power|
The present invention proposes a method and device for controlling uplink power. A central processing unit firstly determines a path loss generation mode for a user equipment according to a predetermined rule and then transmits an instruction to the user equipment, the instruction including the determined path loss generation mode so that the user equipment determines uplink power of fee user equipment according to the path loss generation mode.
|Magnetoresistive detection system and method for detection of magnetic image of bank notes|
A system and method for obtaining a fill image of a bank note being processed. At least one magnetoresistive detector is employed to obtain line-scan sensings of a bank note as the note passes.
|Computer system having voice-control function and voice-control method|
The invention discloses a computer system having voice-control function. The computer system includes a voice-recognition module, a shared memory, a microcontroller, a power-management module and a central processing unit.
A computer system is disclosed. The computer system comprises a near field communication (nfc) tag and a computer.
|System and method for virtual hardware memory protection|
A memory protection unit including hardware logic. The hardware logic receives a transaction from a virtual central processing unit (cpu) directed at a bus slave, the transaction being associated with a virtual cpu identification (id), wherein the virtual cpu is implemented on a physical cpu.
|Method and apparatus for rapid data distribution|
A method and an apparatus for rapid data distribution, the method includes: sending, by a central processing unit, data description information to a rapid forwarding module, where the data description information includes an address and length information of data requested by a user; reading, by the rapid forwarding module according to the data description information, the data requested by the user and forwarding the data requested by the user to a network interface controller; and sending, by the network interface controller, the data requested by the user to the user. By using the method provided in the present invention, after services are increased, only the network interface controller and a storage device need to be added, and cost for the memory and the central processing unit does not need to be increased..
|System and method for monitoring operation of an autonomous robot|
A system and method for monitoring operation of an autonomous robot. In one aspect, the invention can be a method comprising: defining, with a central processing unit of the autonomous robot, a perimeter of an area of confinement; storing the perimeter of the area of confinement within a memory device of the autonomous robot as map data; transmitting the map data from a transceiver of the autonomous robot to a server; overlaying, by the server, the area of confinement onto a satellite image corresponding to a geographic location that includes the area of confinement to create a visual representation of the area of confinement overlaid onto the satellite image; transmitting, from the server to an external device, the visual representation of the area of confinement overlaid onto the satellite image; and displaying, on a display, the visual representation of the area of confinement overlaid onto the satellite image..
|Processors including key management circuits and methods of operating key management circuits|
A system on chip includes a central processing unit and a key manager coupled to the central processing unit. The key manager includes a random number generator configured to generate a key and a key memory configured to store the key and a user setting value associated with the key..
|System on chip for updating partial frame of image and method of operating the same|
A system on chip (soc) and a method of operating the same are provided. The soc includes a central processing unit (cpu) controlling a memory operation and a display operation on a current frame of an image based on generation of the image and an interrupt signal; an image generator requesting data of the current frame from a memory according to control of the cpu; a ud unit determining whether the current frame is updated, detecting whether an update region is a partial frame based on virtual addresses included in a request of the image generator, and outputting the interrupt signal corresponding to the update region to the cpu; a memory controller storing the update region in the memory according to the control of the cpu; and a display controller accessing the memory and outputting the update region to a display device according to the control of the cpu..
|System and method for image processing|
A system and method for image processing are provided. The system comprises a main computing device and a secondary computing device.
|Attack resistant computer system|
A computer system where a second, dedicated processor (sometimes called an spu, to distinguish from the central processing unit (cpu)) has logic to manage and control an intrusion detection hardware set and an intrusion response hardware set. The intrusion response hardware detects physical intrusions (for example, cryogenic attacks), and the response hardware set responds in various ways to attempt to protect the sensitive data in a volatile memory from the detected physical intrusion.
|Parallel processing with proactive solidarity cells|
A method and apparatus for processing information in parallel uses autonomous computer processing cells to perform tasks needed by a central processing unit. Each cell in the system is connected through a switching fabric, which facilitates connections for data transfer and arbitration between all system resources.
|Method for processing sound data and circuit therefor|
A sound data processing apparatus includes a central processing unit for controlling predetermined processing in the apparatus, a rewritable ram, a decoder performing the decoding processing for sound data, and an interface unit for being fitted with an external memory. The sound data processing apparatus reads a driver from the external memory mounted in the interface unit and stores the read driver into the ram, and reads the sound data from the external memory with the driver and processes the read sound data.
|Physiologic change sensor probe|
Embodiments of the present invention are directed to a temperature sensing device that can comprise an elastic ring structure. The temperature sensing device can further comprise a transducer device, such as a temperature sensor, and a microprocessor, memory and wireless transmitter.
|Switch with dual-function management port|
Communication apparatus includes a switch, which includes switching logic, multiple ports for connection to a network, and a management port, and which is configured to assign both a first link-layer address and a second link-layer address to the management port. A host processor includes a memory and a central processing unit (cpu), which is configured to run software implementing a management agent for managing functions of the switch.
|Vehicle wireless router|
A vehicle wireless router includes a printed circuit board, a cigarette lighter port, a central processing unit, a network module and an antenna unit. The printed circuit board is electrically connected to the cigarette lighter port, the central processing unit, the network module and the antenna unit.
|Storage device and motherboard for supporting the storage device|
A motherboard assembly includes a motherboard and a storage device. The motherboard includes an expansion slot, a platform controller hub (pch), a power circuit, a central processing unit (cpu), and a switch unit.
|Devices and methods for controlling the heating and cooling of water in beverage dispensers|
Bottled water dispensers are disclosed that include a cabinet having an exterior portion and an interior portion. The interior portion of the cabinet is configured to house a water bottle in an upright position.
|Apparatus and method for memory-hierarchy aware producer-consumer instructions|
An apparatus and method are described for efficiently transferring data from a producer core to a consumer core within a central processing unit (cpu). For example, one embodiment of a method comprises: a method for transferring a chunk of data from a producer core of a central processing unit (cpu) to consumer core of the cpu, comprising: writing data to a buffer within the producer core of the cpu until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the fill buffer to a cache accessible by both the producer core and the consumer core; and upon the consumer core detecting that data is available in the cache, providing the data to the consumer core from the cache upon receipt of a read signal from the consumer core..
|Processor with tightly coupled smart memory unit|
An information processor includes a central processing unit core and a direct memory access unit connected to the central processing unit core. The information processor further includes at least one tightly coupled smart memory unit connected to the central processing unit core.
|Isolating resources and performance in a database management system|
Techniques for tenant performance isolation in a multiple-tenant database management system are described. These techniques may include providing a reservation of server resources.
|Digital advertising cellular display system|
A digital advertising cellular display system comprising a retail outlet having at least one location for displaying goods and services for purchase, at least one electronic display means located proximal the location for displaying goods and services with electronic display means displaying consumer information images, videos, and audios therefrom, a central processing unit located in each of said electronic display means, and at least one offsite control center in wireless communication with the electronic display means for transferring control information and product and services advertisement and product and services information between the offsite control center and the electronic display means.. .
|Using graphics processing units in control and/or data processing systems|
A graphics processing unit (gpu) can be used in control and/or data processing systems that require high speed data processing with low input/output latency (i.e., fast transfers into and out of the gpu). Data and/or control information can be transferred directly to and/or from the gpu without involvement of a central processing unit (cpu) or a host memory.
|Direct link synchronization communication between co-processors|
Systems, apparatus, articles, and methods are described including operations to communicate synchronization notifications between a co-processor graphic data producer and a co-processor graphic data consumer via a direct link without passing such communications through the central processing unit.. .
|Information input unit, information input method, and computer program|
A central processing unit (cpu) monitors whether a predetermined event (pressing of a sleep release button, an incoming call, an alarm ring sound, or the like) is generated. When the predetermined event is generated, a sensitivity detection unit sets a sensitivity threshold value for input detection to a threshold value of a high-sensitivity mode, and the cpu displays a screen corresponding to the event.
|Software update methodology|
Software update information is communicated to a network appliance either across a network or from a local memory device. The software update information includes kernel data, application data, or indicator data.
|Error protection for a data bus|
A system for providing error detection or correction on a data bus includes one or more caches coupled to a central processing unit and to a hub by one or more buses. The system also includes a plurality of arrays, each array disposed on one of the buses.
|Single microcontroller based management of multiple compute nodes|
An apparatus for compute module management is described herein. The apparatus includes a host system and a logic solution.
|Central processing unit socket assembly|
A central processing unit socket assembly includes a socket mounted on a circuit board, a locking apparatus, and a cover. The cover includes a main plate, a resilient first locking portion formed on a first end of a first surface of the main plate, a second locking portion formed on a second end of the first surface of the main plate opposite to the first locking portion, and a number of connecting pins protruding out from a second surface of the main plate opposite to the first surface of the main plate.
|Method for power management and an electronic system using the same|
A power-management method is provided, and the power-management method includes setting a central processing unit in a first low-power state when receiving a second low-power state request requiring the central processing unit to enter the second low-power state, obtaining first idle periods of the peripheral modules respectively to determine a second idle period according to the first idle periods of the peripheral modules, determining whether the peripheral modules have not sent a data-access request during the second idle period, setting the central processing unit in the second low-power state when the peripheral modules have not sent the data-access request during the second idle period, wherein each first idle period is an interval period between two data transmissions of each peripheral module.. .
|System and method for providing power savings in a processor environment|
Particular embodiments described herein can offer a method that includes powering down a root port; initiating a first downstream cycle by a central processing unit (cpu) to the root port; identifying a power up activity for the cpu; and triggering an exit flow for a power state in conjunction with sending a second downstream cycle to the root port. In more particular embodiments, the triggering of the exit flow for the power state and the sending of the second downstream cycle to the root port occurs in a substantially parallel fashion.
|Controller, data storage device and data storage system having the controller, and data processing method|
A controller, a data storage device and a data storage system including the controller, and a data processing method are provided. The controller may process a plurality of instructions in parallel by including a plurality of address translation central processing units (cpus) in a multi-channel parallel array structure, thereby improving the performance of a semiconductor memory system..
|Processor module, micro-server, and method of using processor module|
A processor module includes at least one storage device, at least one central processing unit (cpu) that uses a preset interface, and a module controller to relay a connection between a common interface bus formed on the based board and an interface used by the cpu.. .
|System and method for incipient drive of slow charger for a vehicle with electric motor|
Disclosed herein is a system and method for incipient drive of a slow charger for a vehicle. Specifically, an incipient drive entry of the slow charger used when a battery is charged in an electric vehicle (ev) or a plug-in hybrid electric vehicle (phev) may be performed.
|Noise cancelling headphone|
A noise cancelling headphone includes a headphone body, a audio player and a central processing unit. The headphone body includes a headband, a first speaker unit and a second speaker unit.
|Graphic processor based accelerator system and method|
An accelerator system is implemented on an expansion card comprising a printed circuit board having (a) one or more graphics processing units (gpu), (b) two or more associated memory banks (logically or physically partitioned), (c) a specialized controller, and (d) a local bus providing signal coupling compatible with the pci industry standards (this includes but is not limited to pci-express, pci-x, usb 2.0, or functionally similar technologies). The controller handles most of the primitive operations needed to set up and control gpu computation.
|Apparatus and method for memory-hierarchy aware producer-consumer instruction|
An apparatus and method are described for efficiently transferring data from a core of a central processing unit (cpu) to a graphics processing unit (gpu). For example, one embodiment of a method comprises: writing data to a buffer within the core of the cpu until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the gpu; setting an indication to indicate to the gpu that data is available in the cache; and upon the gpu detecting the indication, providing the data to the gpu from the cache upon receipt of a read signal from the gpu..
|Offloading tessellation from a graphics processor to a central processing unit|
In accordance with some embodiments, tessellation may be implemented in part on a central processing unit and in part on a graphics processing unit. The part that may be performed on a central processing unit may be a pre-computation stage in which the possible combinations of vertex stitching are computed and stored as a bit mask in a bidirectional array.
|Terminal and method for executing application in same|
The present invention relates to a terminal and a method for executing an application in the same, including the steps of: confirming the weight of the application when a code of the application to be executed is inputted; calculating an allocation index using the confirmed weight; selecting a processing device for executing the application between a central processing unit and a graphics processing unit through the calculated application index; and executing the application through the selected processing device. Accordingly, the present invention determines whether the execution of the application is assigned to the central processing unit or the graphics processing unit according to the weight designated by the user.
|System and method for debugging an executing general-purpose computing on graphics processing units (gpgpu) application|
A system and method for debugging an executing program. The method includes executing a general-purpose computing on graphics processing units (gpgpu) program.
|System, method and computer readable medium for offloaded computation of distributed application protocols within a cluster of data processing nodes|
A data processing node includes a management environment, an application environment, and a shared memory segment (sms). The management environment includes at least one management services daemon (msd) running on one or more dedicated management processors thereof.
|Lighting controller with integrated wide area network interface|
The present disclosure is directed to a photo controller. In one embodiment, the photo controller includes a central processing unit (cpu), a local area connection (lan) interface in communication with the cpu, a wide area network (wan) interface in communication with the cpu and an electrical power control component in communication with the cpu to control a lighting device..
|Protection circuit for central processing unit|
A protection circuit for a central processing unit (cpu) includes a power circuit, two comparators, a number of resistors, a thermistor, and an electronic switch. A non-inverting input terminal of the comparator is coupled to a first power terminal.
|Method and apparatus for image capture in transmitter of wireless communications system|
A method for capturing an image in a transmitter of a wireless communications system, the method comprising controlling a graphic processing unit (gpu) of a graphic card to move frames corresponding to the image from a graphic card frame buffer to a buffer which is accessible by a central processing unit (cpu) of the transmitter when a specified condition is detected; controlling the gpu to release a control for the frames to the cpu; encoding the frames in the buffer which is accessible by the cpu; and transmitting the encoded frames to a receiver of the wireless communications system; wherein the graphic card is connected to the transmitter.. .
|Hardware management interface|
A management controller of a computing device is identified on a network and queried for attributes of the computing device. The management controller is securely implemented in hardware of the computing device and is independent of a central processing unit (cpu) of the computing device.
|Hardware management interface|
A management controller of a computing device is identified, the first management controller implemented in hardware of the first computing device and independent of a central processing unit (cpu) of the computing device. The management controller is queried for attributes of the computing device.
|Load balancing method for multicore mobile terminal|
Methods and apparatus are provided for load-balancing in a portable terminal having a plurality of central processing units (cpus). A utilization is calculated for each of the plurality of cpus, when a state of a task is changed.
|Proxy queue pair for offloading|
A method for offloading includes a host channel adapter (hca) receiving a first work request identifying a queue pair (qp), making a first determination that the qp is a proxy qp, and offloading the first work request to a proxy central processing unit (cpu) based on the first determination and based on the first work request satisfying a filter criterion. The hca further receives a second work request identifying the qp, processes the second work request without offloading based on the qp being a proxy qp and based on the first work request failing to satisfy the filter criterion.
|System and method for dynamically controlling a plurality of cores in a multicore central processing unit based on tempature|
A method of controlling power within a multicore central processing unit (cpu) is disclosed. The method may include monitoring a die temperature, determining a degree of parallelism within a workload of the cpu, and powering one or more cores of the cpu up or down based on the degree of parallelism, the die temperature, or a combination thereof..
|Heterogeneous multiprocessor design for power-efficient and area-efficient computing|
A technique for managing processor cores within a multi-core central processing unit (cpu) provides efficient power and resource utilization over a wide workload range. The cpu comprises at least one core designed for low power operation and at least one core designed for high performance operation.
|Communication traffic processing architectures and methods|
Communication traffic processing architectures and methods are disclosed. Processing load on main central processing units (cpus) can be alleviated by offloading data processing tasks to separate hardware..