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Central Processing Unit patents



      

This page is updated frequently with new Central Processing Unit-related patent applications.




Date/App# patent app List of recent Central Processing Unit-related patents
06/23/16
20160183374 
 Cpu package substrates with removable memory mechanical interfaces patent thumbnailCpu package substrates with removable memory mechanical interfaces
Configurable central processing unit (cpu) package substrates are disclosed. A package substrate is described that includes a processing device interface.

06/23/16
20160182851 
 Systems and methods for automatic generation and consumption of hypermeetings patent thumbnailSystems and methods for automatic generation and consumption of hypermeetings
Provided a computer-implemented method for a meeting playback, the method being performed in connection with a computerized system incorporating a central processing unit, a display device and a memory, the computer-implemented method involving: generating a first user interface portion on the display device, the first user interface portion for displaying a first meeting; generating a second user interface portion on the display device, the second user interface portion for displaying a second meeting, wherein the first meeting is prior to the second meeting and wherein the first meeting and second meeting are linked together using at least one link; performing a playback of the second meeting in the second user interface portion; and during the playback of the second meeting, using the at least one link to perform a playback of at least a portion of the first meeting.. .

06/23/16
20160182529 
 Systems and methods for secure location-based document viewing patent thumbnailSystems and methods for secure location-based document viewing
A computer-implemented method, the method being performed in a computerized system incorporating a central processing unit, a localization signal receiver, a display and a memory, the computer-implemented method involving: receiving a request from a user for a content; receiving at least one localization signal using the localization signal receiver; determining a location based on the received localization signal; using a plurality of content access rules to determine whether the requested content is authorized to be accessed from the determined location; and providing content to the user only if the content is authorized to be accessed from the determined location.. .

06/23/16
20160180890 
 Systems and methods for visualizing playback plans of hypermeetings patent thumbnailSystems and methods for visualizing playback plans of hypermeetings
A computer-implemented method for visualizing a playback plan of a hypervideo, the hypervideo comprising a plurality of video segments from a plurality of videos linked together using a plurality of links, the method being performed in connection with a computerized system comprising a central processing unit, a display device and a memory, the computer-implemented method involving: generating the playback plan for an automated playback of the hypervideo, the automated playback comprising automatically following the plurality of links linking the plurality of video segments such that at least some of the plurality of video segments are played in a predetermined sequence, wherein the plurality of links are followed based on the playback plan; and generating a graphical user interface portion on the display device for visualizing the playback plan.. .

06/23/16
20160179744 
 Computer system including cpu or peripheral bridge to communicate serial bits of peripheral component interconnect bus transaction and low voltage differential signal channel to convey the serial bits patent thumbnailComputer system including cpu or peripheral bridge to communicate serial bits of peripheral component interconnect bus transaction and low voltage differential signal channel to convey the serial bits
A computer system has a computer with an integrated central processing unit and graphics subsystem in a single chip. The graphics subsystem directly couples to a unidirectional differential signal channel to output digital video data.

06/23/16
20160179708 
 Information processing apparatus, information processing method, and non-transitory computer readable medium patent thumbnailInformation processing apparatus, information processing method, and non-transitory computer readable medium
An information processing apparatus includes first and second central processing units, a communication unit, and a memory. The first and second central processing units operate based on first and second operating systems, respectively.

06/23/16
20160179484 
 Code generating method, compiler, scheduling method, scheduling apparatus and scheduling system patent thumbnailCode generating method, compiler, scheduling method, scheduling apparatus and scheduling system
A code generating method, a compiler, a scheduling method, an apparatus and a scheduling system where the generated code is an executable code and applied to a heterogeneous system, and the heterogeneous system includes an accelerated processor and a central processing unit (cpu) and the code generating method includes acquiring, by a compiler, resource information of the accelerated processor and resource information of the cpu in order to generate an operable platform list, identifying, by the compiler, accelerable code from first user code, embedding, by the compiler, a hook function and an exception handling function before the accelerable code to form second user code, and compiling, by the compiler, the second user code to obtain the executable code and the executable code generated may automatically implement proper scheduling of processors during execution.. .

06/23/16
20160179293 
 Systems and methods for plan-based hypervideo playback patent thumbnailSystems and methods for plan-based hypervideo playback
Provided is a computer-implemented method for a playback of a hypervideo, the hypervideo including multiple video segments from a multiple videos linked together using links, the method being performed in connection with a computerized system incorporating a central processing unit, a display device and a memory, the computer-implemented method involving: generating a user interface portion on the display device for the playback of the hypervideo; and performing the playback of the hypervideo in the generated user interface portion by automatically following the plurality of links linking the plurality of video segments such that at least some of the plurality of video segments are played in a predetermined sequence; wherein the plurality of links are followed based on a playback plan. The playback plan may include at least one rule for following the multiple links linking the video segments during the playback of the hypervideo..

06/23/16
20160179156 
 Hybrid power management approach patent thumbnailHybrid power management approach
Methods and apparatus to provide a hybrid power management approach are described. Some embodiments redefine the interface to power control unit (pcu) allowing a hybrid implementation where software running on cpu (central processing unit, also referred to herein interchangeably as “processor”) cores performs more of the work for power management, enabling the pcu to remain as a simple or regular microcontroller.

06/23/16
20160178481 
 Method for estimating the reliability of measurements by wheel sensors of a vehicle and system for its application patent thumbnailMethod for estimating the reliability of measurements by wheel sensors of a vehicle and system for its application
A method and system for evaluating the reliability of data supplied by multi-function wfc sensors of tires of wheels of a vehicle for targeted applications, on the basis of the irregularities of the road, which use displacement data sent from the road handling adaptation equipment of the vehicle, enabling the variations in the road condition to be reflected. The system includes equipment for monitoring the wheel displacement data for adapting it to the variations of profile of the road on which it is traveling, in order to maintain a stable body position.

06/23/16
20160175976 

Systems and methods for determining a weld torch location


A welding system having a modulation circuit, a weld torch, and a sensor system is provided. The modulation circuit configured to modulate a welding current with a randomized signal to generate a modulated welding current.

06/23/16
20160175191 

Spectral electrotherapy device and controlling the same


A spectral electrotherapy device and a method of controlling the same are introduced, wherein a central processing unit provides a control signal for controlling the switching operation of an output driver to generate output voltage, thereby controlling output features of the spectral electrotherapy device. The control signal provided by the central processing unit to a switching unit uses central frequency f0 as a standard to thereby define the bandwidth of the central frequency f0 with difference Δf and define the points in time of the next change in the central frequency f0 and the difference Δf with first and second time intervals t1, t2, respectively.

06/16/16
20160173950 

Third witness video participation system and method


A video recording and law enforcement corroboration process. A video feed is established between a law enforcement officer and a perpetrator, initiated by either party.
Virtual Health Systems Corporation


06/16/16
20160173896 

Methods and decoding video using re-ordered motion vector buffer


Methods and apparatus for decoding video are presented herein. The methods and apparatus may comprise a host processor, such as a central processing unit (cpu), programmed to execute a software driver that causes the host processor to generate a motion compensation command for a plurality of cores of a massively parallel processor, such as a graphics processing unit (gpu), to provide motion compensation for encoded video.
Advanced Micro Devices, Inc.


06/16/16
20160172055 

Combined rank and linear address incrementing utility for computer memory test operations


Embodiments include a combined rank and linear memory address incrementing utility. An aspect includes an address incrementing utility suitable for implementation within a memory controller as an integrated subsystem of a central processing unit (cpu) chip.
International Business Machines Corporation


06/16/16
20160171131 

Methods, systems, and computer readable media for utilizing parallel adaptive rectangular decomposition (ard) to perform acoustic simulations


Methods, systems, and computer readable media for utilizing parallel adaptive rectangular decomposition (ard) to perform acoustic simulations are disclosed herein. According to one method, the method includes assigning, to each of a plurality of processors in a central processing unit (cpu) cluster, ard processing responsibilities associated with one or more of a plurality of partitions of an acoustic space and determining, by each processor, pressure field data corresponding to the one or more assigned partitions.
The University Of North Carolina At Chapel Hill


06/16/16
20160170912 

Safely discovering secure monitors and hypervisor implementations in systems operable at multiple hierarchical privilege levels


In a computer system operable at multiple hierarchical privilege levels, a “wait-for-event” (wfe) communication channel between components operating at different privilege levels is established. Initially, a central processing unit (cpu) is configured to to “trap” wfe instructions issued by a client, such as an operating system, operating at one privilege level to an agent, such as a hypervisor, operating at a more privileged level.
Vmware, Inc.


06/16/16
20160170816 

Creating a communication channel between different privilege levels using wait-for-event instruction in systems operable at multiple hierarchical privilege levels


In a computer system operable at multiple hierarchical privilege levels, a “wait-for-event” (wfe) communication channel between components operating at different privilege levels is established. Initially, a central processing unit (cpu) is configured to to “trap” wfe instructions issued by a client, such as an operating system, operating at one privilege level to an agent, such as a hypervisor, operating at a more privileged level.
Vmware, Inc.


06/16/16
20160170679 

Secondary cpu mmu initialization using page fault exception


In a computer system with multiple central processing units (cpus), initialization of a memory management unit (mmu) for a secondary cpu is performed using an exception generated by the mmu. In general, this technique leverages the exception handling features of the secondary cpu to switch the cpu from executing secondary cpu initialization code with the mmu “off” to executing secondary cpu initialization code with the mmu “on.” advantageously, in contrast to conventional techniques for mmu initialization, this exception-based technique does not require identity mapping of the secondary cpu initialization code to ensure proper execution of the secondary cpu initialization code..
Vmware, Inc.


06/16/16
20160166148 

Visualization of a development and escalation of a patient monitor alarm


In the present invention, a monitoring device for providing information on data obtained from sensors operably connected to the device includes a central processing unit configured to receive incoming data signals from a sensor concerning a physiological parameter and to compare the incoming data signals to predetermined alarm criteria for the physiological parameter to determine an alarm condition. The device also includes a display operably connected to the central processing unit and having a display screen with a display area configured to visually represent the incoming data signals concerning the physiological parameter relating to a determined alarm condition on a portion of the display area in a visually distinct manner from a remainder of the display area to visually illustrate an escalation effect..
General Electric Company


06/09/16
20160165085 

Information processing apparatus and image forming apparatus


An information processing apparatus includes a first central processing unit, a second central processing unit, and a returning unit. The first central processing unit has a normal operating state and a power-saving state in which power consumption is lower than in the normal operating state.
Fuji Xerox Co., Ltd.


06/09/16
20160164910 

Processing preventing packet attack


A processing method and apparatus for preventing a packet attack. A network protocol negotiation status of a port of a network device is monitored; a port that succeeds in network protocol negotiation is set to a trusted port, a protocol packet is selected, according to a first access control list (acl), from packets received by the trusted port, and a rate at which the protocol packet is sent to a central processing unit (cpu) is limited to a first committed access rate (car); a port that fails in network protocol negotiation is set to an untrusted port, a protocol packet is selected, according to a second acl, from packets received by the untrusted port, and a rate at which the protocol packet is sent to the cpu is limited to a second car.
Huawei Technologies Co., Ltd.


06/09/16
20160162336 

Cpu scheduler configured to support latency sensitive virtual machines


A host computer has one or more physical central processing units (cpus) that support the execution of a plurality of containers, where the containers each include one or more processes. Each process of a container is assigned to execute exclusively on a corresponding physical cpu when the corresponding container is determined to be latency sensitive.
Vmware, Inc.


06/09/16
20160162294 

Reconfigurable processors and methods for collecting computer program instruction execution statistics


Reconfigurable processors and methods for collecting computer program instruction execution statistics are disclosed. According to an aspect, a method includes providing a reconfigurable processor configured to execute a set of central processing unit (cpu) instructions that each have a function.
Lenovo Enterprise Solutions (singapore) Pte. Ltd.


06/09/16
20160162061 

Low latency inking


This disclosure generally provides an input device that includes a by-pass path for improving latency between a touch controller and a display driver. In one embodiment, the by-pass path directly connects the touch controller and display driver, thereby by-passing a host processor (e.g., a central processing unit (cpu) or graphic processing unit (gpu)) in the input device.
Synaptics Incorporated


06/09/16
20160161995 

Socket and adapter


A motherboard can include a socket coupled to a cable. The motherboard can also include an adapter coupled to a central processing unit (cpu).
Hewlett-packard Development Company, L.p.


06/02/16
20160156697 

Communication terminal product supporting interactive association system


A communication terminal product supports a mobile communication technology system and supports transmit-receive of a multimedia information signal of the interactive interconnected system. The interactive interconnected system comprises an electronic reading device and an electronic transmitter-receiver.

06/02/16
20160155209 

Graphics processing unit and device including the same


A graphics processing unit (gpu) for determining whether to perform tessellation on a first model according to a control of a central processing unit (cpu) is provided. The gpu reads the first model from a memory, which stores prepared models having different complexities; calculates a complexity of the first model; compares the calculated complexity with a reference complexity; and determines whether to perform a tessellation operation on the first model according to a comparison result..

06/02/16
20160154806 

Print job archives that are optimized for server hardware


Systems and methods are provided for generating a print job archive optimized for searching by a specific server. The system includes a memory and an indexing controller.
Ricoh Company, Ltd.


06/02/16
20160154735 

Electronic device and controlling shareable cache memory thereof


An electronic device and a method for controlling a sharable cache memory of the electronic device are provided. The electronic device includes a central processing unit including at least one core processor, at least one module, and a sharable cache memory including a controller, wherein the controller enables the sharable cache memory as a cache memory of the central processing unit if the central processing unit is in a working mode, and wherein the controller enables the sharable cache memory as a buffer of at least one of modules if at least one core processor of the central processing unit is transitioned to a sleep mode..
Samsung Electronics Co., Ltd.


06/02/16
20160154661 

Systems and methods for virtual machine attribution with hardware information


Systems and methods for virtual machine (vm) attribution with hardware information. In an illustrative, non-limiting embodiment, an information handling system (ihs) may include a central processing unit (cpu) and a memory coupled to the cpu, the memory having program instructions stored thereon that, upon execution by the cpu, cause the ihs to: provide a management console configured to manage a plurality of hypervisors, each hypervisor configured to be executed in a different one of a plurality of physical servers distinct from the ihs, each hypervisor further configured to create and run at least one virtual machine (vm); identify, via the management console, a hardware capability of a given one of the plurality of physical servers; and assign the vm, by the management console, to the given physical server in response to the identification of the hardware capability..
Dell Products, L.p.


06/02/16
20160154597 

Backup of volatile memory to persistent storage


Approaches for automatically backing up data from volatile memory to persistent storage in the event of a power outage, blackout or other such failure are described. The approaches can be implemented on a computing device that includes a motherboard, central processing unit (cpu) a main power source, volatile memory (e.g., random access memory (ram)), an alternate power source and circuitry (e.g., a specialized application-specific integrated circuit (asic)) for performing the backup of volatile memory to a persistent storage device.
Amazon Technologies, Inc.


06/02/16
20160154422 

Motherboard with a hole


A printed circuit board (pcb) can include a central processing unit (cpu) installed on a first surface of the pcb. The pcb can also include a cable routed on a second surface of the pcb parallel to the first surface.
Hewlett-packard Development Company, L.p.


05/26/16
20160150471 

Electricity saving terminal device, and terminal device


Disclosed are a power saving method for a terminal device and the terminal device thereof, wherein the method includes: a terminal device enabling a power saving mode and obtaining an adjusted central processing unit (cpu) clock speed set by a user and an adjusted screen resolution set by the user; if the terminal device obtains the adjusted cpu clock speed set by the user, the terminal device adjusting the cpu to operate according to the adjusted cpu clock speed set by the user; if the terminal device obtains the adjusted screen resolution set by the user, the terminal device adjusting a screen display according to the adjusted screen resolution set by the user. The embodiment of the present document saves the power consumption of a terminal device by downsizing the screen display and/or reducing the cpu clock speed, thereby effectively reducing power consumption of the terminal device..
Zte Corporation


05/26/16
20160150080 

A url transmission system and means thereof


The present invention provides a uniform resource locator (url) transmission system for displaying at least one predetermined url comprising: (a) a smart phone having a phone call recognition system for recognizing and transmitting caller identification information; and, (b) a base station comprising a central processing unit (cpu) for transmitting telecommunication signals formatted as an active message. The cpu includes a computer readable medium containing instructions for automatically converting the recognized caller identification information to the active message, and instructions for automatically associating the active message to at least one predetermined url associated with the receiver of the caller's transmission..

05/26/16
20160149932 

Monitoring use of a sensor of a computing device


Monitoring use of a sensor of a computing device. A sensor obtains information from an environment of the computing device.
International Business Machines Corporation


05/26/16
20160148395 

Paintbrush and liquid simulation


Paintbrush and liquid simulation techniques are described. In one or more implementations, input is received to perform brush strokes with a virtual paintbrush on a virtual canvas.
Adobe Systems Incorporated


05/26/16
20160147673 

Microcomputer and controlling memory access


A memory control system includes a memory connected to a memory bus, the memory including a plurality of access areas, a memory controller connected to the memory bus, a plurality of registers corresponding to the plurality of access areas, each of the plurality of registers configured to set an access permission or prohibition for a corresponding access area, a cpu (central processing unit) configured to issue a first access request for accessing one of the plurality of access areas, and a memory access controller configured to determine whether an access to the memory is permissible or prohibited using the first access request and the plurality of registers, the memory access controller outputting a second access request in accordance with a determination result.. .
Renesas Electronics Corporation


05/26/16
20160147653 

Filtering multiple in-memory trace buffers for event ranges before dumping from memory


A method for filtering multiple in-memory trace buffers for event ranges is provided. The method includes allocating a plurality of main trace buffers, based on the number of central processing units (cpu) participating in a trace.
International Business Machines Corporation


05/26/16
20160146777 

Integrated user interface for status and control of a submersible multi-parameter sonde


Provided are multi-parameter sonde systems having a unique integrated user interface for ease of set-up and control, service and maintenance, even in the field and without accessory controllers. The necessary components, such as central processing unit, display and accelerometer are positioned in a water-tight housing, with the display configured for convenient observability and readability.
In-situ, Inc.


05/19/16
20160143041 

Multimode wireless terminal


Embodiments of the present invention provide a multimode wireless terminal, including a general-purpose central processing unit, a reconfigurable baseband processing module, a reconfigurable intermediate radio frequency module, and a reconfigurable antenna module, terminal is applicable to various network environments.. .
Huawei Technologies Co., Ltd.


05/19/16
20160140057 

Semiconductor device and encryption key writing method


A semiconductor device includes a central processing unit (cpu), a first memory which stores a plurality of split keys, a second memory which stores an encryption code as at least one of an encrypted instruction and encrypted data, the plurality of split keys including an encryption key for decrypting the encryption code, and a decrypter which reads the encryption code from the second memory, decrypts the encryption code with the use of the encryption key, and supplies the decrypted encryption code to the cpu. The second memory stores an encryption key reading program which is executed by the cpu to restore the encryption key and to supply the encryption key to the decrypter, by reading and reconfiguring the split keys stored in the first memory in a distributed manner..
Renesas Electronics Corporation


05/19/16
20160139669 

Device for intuitive dexterous touch and feel interaction in virtual worlds


A device for dexterous interaction in a virtual world in disclosed. The device includes a housing including a plurality of buttons and a plurality of vibration elements each associated with at least one of the plurality of buttons.
Thika Holdings Llc


05/19/16
20160139583 

Motor selection device


A motor selection device includes a computer including a storage device and a calculation device. The storage device stores data of acceleration time, constant speed time, deceleration time, stop time, maximum output torque for each motor, dynamic friction torque, and constant load torque.
Nsk Ltd.


05/19/16
20160139273 

Wireless devices and systems for tracking patients and methods for using the like


Disclosed are apparatuses, systems, and methods for tracking patients that suffer from dementia. The disclosed apparatus is a wearable device capable of micro-tracking through bluetooth low energy technology and capable of macro-tracking through gps technology.

05/12/16
20160134652 

Method for recognizing disguised malicious document


A method for recognizing disguised malicious document, carried out by a computer system including a central processing unit (cpu), a memory, and a database storing rules for defining executable file and non-executable file, comprising steps of: receiving a static file through a network and an input/out interface; scanning the static file for a file header to determine if it is a non-executable file; analyzing file body of the non-executable file to locate components of an executable file and mark these positions; extracting components of the executable file from the non-executable file; concatenating the extracted components in accordance with a default rule or a heuristic rule to form a new file; and obtaining a new file that is executable, such that the received static file is a non-executable file having an embedded executable file, thus labeling the static file as a disguised malicious document.. .
Verint Systems Ltd.


05/12/16
20160132861 

Method, device and secure element for conducting a secured financial transaction on a device


A device and a secure element for conducting a secured financial transaction are disclosed. The device comprises a central processing unit; a communication interface for establishing a communication between the device and a financial institution related to a financial account; an interface for acquiring data relating to the financial account; the secure element for processing at least a portion of the data relating to the financial account acquired by the interface; and control logic for acquiring a purchase amount to be debited from the financial account and for obtaining a transaction authorization from the financial institution related to the financial account, the transaction authorization being based, at least partially, on data processed solely by the secure element independently of data processed by the central processing unit.
Mobeewave, Inc.


05/12/16
20160132389 

Solid state disk controller apparatus


A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a cpu bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the cpu bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the cpu bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the cpu bus.. .
Samsung Electronics Co., Ltd.


05/12/16
20160132100 

Data processing device and data processing system


A data processing device includes a first power-on reset circuit, a second power-on reset circuit with a higher power consumption and a higher reset voltage accuracy than said first power-on reset circuit, a low voltage detect circuit, a storage unit storing information for determining whether to keep said second power-on reset circuit and said low voltage detect circuit in an active state or an inactive state, a central processing unit initialized in a response to respective outputs of said first and second power-on reset circuits and setting said information in said storage unit, and a power supply node providing a power to the data processing device.. .
Renesas Electronics Corporation


05/05/16
20160127806 

Multimedia information signal supporting interactive association system


The invention relates to a multimedia information signal supporting an interactive interconnected system. The multimedia information signal is formed by associated data and media information data synthesis, and the interactive interconnected system comprises an electronic reading device and an electronic transmitter-receiver.

05/05/16
20160127805 

Audio information signal supporting interaction association system


The invention relates to an information association technology supporting a cross-media product, in particular to an audio information signal supporting an interactive interconnected system. The signal is formed by audio data and associated data synthesis.

05/05/16
20160125565 

Asynchronous method and apparatus to support real-time processing and data movement


An asynchronous medical image processing system is described that includes a real-time controller connectable to a medical imaging device, a graphics processing unit (gpu) connectable to a display device, and a central processing unit (cpu) that executes an operating system and related application(s). The real-time controller is directly connected to a memory of the gpu and performs respective operations asynchronously with respect to the cpu.
Toshiba Medical Systems Corporation


05/05/16
20160125090 

Print media product supporting interactive association system


A plane media product supporting an interactive interconnected system supports transmit-receive of a multimedia information signal. The interactive interconnected system comprises an electronic reading device and an electronic transmitter-receiver.

05/05/16
20160124774 

Cluster resource management in a virtualized computing environment


Techniques for managing computing resources in a cluster are disclosed. In one embodiment, a method includes identifying a virtual machine requiring additional memory.
Vmware, Inc.


05/05/16
20160124770 

Transportation network micro-simulation pre-emptive decomposition


In a parallel computing method performed by a parallel computing system comprising a plurality of central processing units (cpus), a main process executes. Tasks are executed in parallel with the main process on cpus not used in executing the main process.
Xerox Corporation


05/05/16
20160124652 

Methods and systems for determining hardware sizing for storage array systems


Methods and systems for enabling sizing of storage array resources are provided. Resources of a storage array can include, for example, cache, memory, ssd cache, central processing unit (cpu), storage capacity, number of hard disk drives (hdd), etc.
Nimble Storage, Inc.


04/28/16
20160119571 

Closed caption-support content receiving apparatus and display apparatus, system having the same, and closed caption-providing method thereof


Disclosed are a closed caption-support content receiving apparatus and display apparatus, a system having the same, and a closed caption-providing method thereof, which can provide closed-caption data (ccd) suitable for a display apparatus such as a mobile device, a digital television (tv), etc. Based on characteristic information of the display apparatus even though the display apparatus is not able to display the received closed-caption data.
Samsung Electronics Co., Ltd.


04/28/16
20160117940 

Method, system, and treating a communication disorder


A system, method, and apparatus for treating a communication disorder includes a user input assembly, a central processing unit configured to analyze data entered into the input assembly, and a user output assembly configured to generate a report reflecting the analysis of the data.. .
Lingraphicare America Incorporated


04/28/16
20160117498 

Computing platform security methods and apparatus


Computing platform security methods and apparatus are disclosed. An example apparatus includes a security application to configure a security task, the security task to detect a malicious element on a computing platform, the computing platform including a central processing unit and a graphics processing unit; and an offloader to determine whether the central processing unit or the graphics processing unit is to execute the security task; and when the graphics processing unit is to execute the security task, offload the security task to the graphics processing unit for execution..
Intel Corporation


04/28/16
20160117497 

Computing platform security methods and apparatus


Computing platform security methods and apparatus are disclosed. An example apparatus includes a security application to configure a security task, the security task to detect a malicious element on a computing platform, the computing platform including a central processing unit and a graphics processing unit; and an offloader to determine whether the central processing unit or the graphics processing unit is to execute the security task; and when the graphics processing unit is to execute the security task, offload the security task to the graphics processing unit for execution..
Intel Corporation


04/28/16
20160117277 

Collaborative hardware interaction by multiple entities using a shared queue


A method for interaction by a central processing unit (cpu) and peripheral devices in a computer includes allocating, in a memory, a work queue for controlling a first peripheral device of the computer. The cpu prepares a work request for insertion in the allocated work queue, the work request specifying an operation for execution by the first peripheral device.
Mellanox Technologies Ltd.


04/28/16
20160117192 

Controlling execution of threads in a multi-threaded processor


Execution of threads in a processor core is controlled. The processor core supports simultaneous multi-threading (smt) such that there can be effectively multiple logical central processing units (cpus) operating simultaneously on the same physical processor hardware.
International Business Machines Corporation


04/28/16
20160117191 

Controlling execution of threads in a multi-threaded processor


Execution of threads in a processor core is controlled. The processor core supports simultaneous multi-threading (smt) such that there can be effectively multiple logical central processing units (cpus) operating simultaneously on the same physical processor hardware.
International Business Machines Corporation


04/28/16
20160117071 

Computer system for automatic organization, indexing and viewing of information from multiple sources


A computer data processing system including a central processing unit configured with an integrated computer control software system for the management of data objects including dynamic and automatic organization, linking, finding, cross-referencing, viewing and retrieval of multiple objects regardless of nature or source. The system provides an underlying component architecture having an object-oriented database structure and a metadata database structure which stores only one instance of each object while linking the object to multiple collections and domains for grouping into and retrieval from any of the collections.

04/28/16
20160116571 

Device for warning of radar traps


The invention relates to a device for warning of radar traps or speed radar signals, comprising a radar detection antenna, a central processing unit, which is connected to the radar detection antenna, an alert device or unit, which is connected to the central processing unit and which is designed for delivering an alarm, wherein the central processing unit is designed for determining at least one characteristic of the signal received by the radar detection antenna and for causing the alert device to deliver an alarm or suppress the delivery of an alarm in dependence on least one determined characteristic.. .

04/28/16
20160116511 

Current sensing device and method


A current sensing apparatus includes: a temperature sensor configured to sense a temperature of a power converter; a current sensing unit configured to sense an input current of the power converter; and a central processing unit (cpu) configured to control an operation of the power converter in response to the sensed temperature of the power converter and the sensed input current of the power converter. The cpu includes a compensation unit configured to store, upon receiving an indication of the sensed temperature of the power converter from the temperature sensor, an operation voltage of at least one diode included in the current sensing unit in a map, and to compensate for an error of a sensing current based on the stored operation voltage when the current sensing unit senses the input current..
Hyundai Motor Company


04/28/16
20160116303 

Systems and methods for resource consumption analytics


The systems and methods described herein are directed to resource monitoring and resource consumption analytics. Resource usage is tracked through a gateway device monitoring resources using remote input sensors, and usage data is transmitted to a central processing unit whereby the data is interpreted and compared with usage over time and site conditions such as weather.
Hydro-care International Inc.


04/21/16
20160112060 

Analog-to-digital conversion with micro-coded sequencer


A micro-coded sequencer controls complex conversion sequences independent of a central processing unit (cpu). Micro-coding provides for easily adding new process steps and/or updating existing process steps.

04/21/16
20160110992 

Condition responsive indication assembly and method


A communications assembly includes a central processing unit and a plurality of hardhat assemblies. The central processing unit transmits central signals and receives remote communications from the hardhat assemblies.

04/21/16
20160110532 

User authorization and presence detection in isolation from interference from and control by host central processing unit and operating system


An embodiment may include circuitry to be included, at least in part, in a host. The host may include at least one host central processing unit (cpu) to execute, at least in part, at least one host operating system (os).

04/21/16
20160110225 

System and improving memory usage in virtual machines


An apparatus includes at least one processor executing a method for managing memory among a plurality of concurrently-running virtual machines, and a non-transitory memory device that stores a set of computer readable instructions for implementing and executing said memory management method. A memory optimization mechanism can reduce a memory usage of a virtual machine at a cost of increasing a central processing unit (cpu) usage.

04/21/16
20160106173 

Condition responsive indication assembly and method


A communications assembly includes a central processing unit and a plurality of portable communication assemblies. The central processing unit transmits central signals and for receiving remote communications from the portable communications assemblies.

04/14/16
20160105539 

Vehicle interface docking system for dsrc-equipped user devices in a vehicle


A vehicle interface docking system for dedicated short range communication equipped user device in a vehicle. The vehicle interface docking system includes a cradle mount mountable to the vehicle within line of sight of an operator.

04/14/16
20160105146 

Input power capacity detector embodying a measuring the maximum power (pmax) available from a photo voltaic panel or array of photo voltaic panels without requirement that a connected ac powered device draws power at the time of measurement


A method of measuring the maximum power available from a photo voltaic array without the requirement of connected ac devices drawing power at time of measurement. Such a method allows for the design of systems which may prevent the unnecessary or potentially damaging startup of said ac devices at times at which power is not sufficient to power them safely.

04/14/16
20160103723 

System-on-chip verification


Disclosed herein are method, system and computer program product embodiments for improving the verification process of a system on chip (soc). An embodiment operates by employing an active interconnect (aic) between a processing subsystem (e.g., a central processing unit or cpu) and a plurality of peripherals, wherein the processing subsystem is linked to a plurality of applications via a plurality of drivers, and implementing a common set of software codes by at least one of the applications for a software development process and a hardware verification process.

04/14/16
20160103718 

Method and message interactive processing


Provided are a message interaction processing method and device. The method includes: a first buffer with a preset size is applied for to a central processing unit (cpu) and/or a chip; and message interaction is performed between the cpu and the chip through the first buffer, wherein the first buffer is used for storing at least two messages.

04/14/16
20160103426 

Clock


An electronic clock operable to provide the time of day and further being configured to provide a visual effect. The clock includes a housing having a plurality of walls, top and bottom formed to create an interior volume.

04/07/16
20160098295 

Increased cache performance with multi-level queues of complete tracks


Exemplary method, system, and computer program product embodiments for increased cache performance using multi-level queues by a processor device. The method includes distributing to each one of a plurality of central processing units (cpus) workload operations for creating complete tracks from partial tracks, creating sub-queues of the complete tracks for distributing to each one of the cpus, and creating demote scan tasks based on workload of the cpus.
International Business Machines Corporation


04/07/16
20160098200 

In-memory popcount support for real time analytics


A processing-in-memory (pim) model in which computations related to the popcount and logical bitwise operations are implemented within a memory module and not within a host central processing unit (cpu). The in-memory executions thus eliminate the need to shift data from large bit vectors throughout the entire system.

03/31/16
20160094854 

Processing parameters for operations on blocks while decoding images


To decode encoded video using a computer with a central processing unit and a graphics processing unit as a coprocessor, parameters applied to blocks of intermediate image data are transferred from the central processing unit to the graphics processing unit. When the operation being performed applies to a small portion of the blocks of intermediate image data, then the central processing unit can transfer to the graphics processing unit the parameters for only those blocks to which the operation applies.
Microsoft Corporation


03/31/16
20160092328 

Memory device test apparatus and method


Disclosed herein are a method and an apparatus for shortening a data comparison test time by using peer-to-peer transfers between peripheral component interconnect express (pcie) endpoints when testing solid state drive (ssd) devices. A memory device test apparatus performing a data comparison test of a memory device mounted in a downstream port of a peripheral component interconnect express (pcie) switch by performing a writing process and a reading-back process by a control of a host central processing unit (cpu) includes: a comparison test unit (fpga) connected to the downstream port of the pcie switch, performing peer-to-peer communication with the memory device to supply write data to the memory device and receive read-back data from the memory device, and performing the data comparison test..
Tanisys Technology, Inc.


03/31/16
20160092270 

Algorithm for faster convergence through affinity override


A method is implemented by a network device having a symmetric multi-processing (smp) architecture. The method improves response time for processes implementing routing algorithms in a network.
Telefonaktiebolaget L M Ericsson (publ)




Central Processing Unit topics: Central Processing Unit, Speech Recognition, User Interface, Storage Device, Alarm System, Constraints, Electronic Device, Embedded System, Application Program, Functional Specification, Control Flow, Application Programming Interface, Data Storage, Optical Fiber, Solid Structure

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