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Cells patents



      

This page is updated frequently with new Cells-related patent applications.




Date/App# patent app List of recent Cells-related patents
06/16/16
20160174282 
 Systems and methods providing improved success rate for rrc connection reestablishments patent thumbnailSystems and methods providing improved success rate for rrc connection reestablishments
Systems and methods that provide improved success rates for connection reestablishments in a cellular communications system are disclosed. Embodiments of a radio access node in a cellular communications system enabling connection reestablishment for a wireless device to a target cell controlled by the radio access node are disclosed.
Telefonaktiebolaget L M Ericsson (publ)


06/16/16
20160174269 
 Methods and  device to device communication patent thumbnailMethods and device to device communication
Systems and techniques for managing collisions in discovery of device to device communication capable devices. Depending on whether collision probability is high or low, collision avoidance, or collision detection, may be performed.
Nokia Technoloies Oy


06/16/16
20160174259 
 Preemptive retransmissions on listen-before-talk cells patent thumbnailPreemptive retransmissions on listen-before-talk cells
Systems and methods are described herein relating to preemptive retransmission of a transport block in successive subframes on, e.g., a listen-before-talk (lbt) cell. Embodiments of a method of operation of a radio node of a cellular communications network are disclosed.
Telefonaktiebolaget L M Ericsson (publ)


06/16/16
20160174169 
 Radio base station, user terminal and radio communication method patent thumbnailRadio base station, user terminal and radio communication method
The present invention is designed to allow user terminals to detect small cells in the off state efficiently when the small cells are switched on and off dynamically. A radio base station that switches between a continuous transmission state and a discontinuous transmission state dynamically, has a power control section that executes power control so that the transmission power of a reference signal for cell detection that is transmitted in the discontinuous transmission state is lower than the transmission power of a reference signal that is transmitted in the continuous transmission state..
Ntt Docomo, Inc.


06/16/16
20160174166 
 Radio base station apparatus, and transmission power determination method patent thumbnailRadio base station apparatus, and transmission power determination method
A radio base station apparatus including a function for determining a transmission power, including: a neighbor cell detection unit configured to detect a neighbor cell that interferes with a target cell that the radio base station apparatus can form; a received power measurement unit configured to measure, for each neighbor cell detected by the neighbor cell detection unit, a received power from the neighbor cell; and a transmission power determination unit configured to calculate, for each band part that overlaps with a transmission band of the radio base station apparatus in transmission bands of each neighbor cell, a sum of received powers for neighbor cells having transmission bands each including the band part, and to determine an interference amount in the target cell based on the sum of received powers so as to determine the transmission power by using the interference amount.. .
Ntt Docomo, Inc.


06/16/16
20160174126 
 Procedure for formulating a signal to interference plus noise ratio patent thumbnailProcedure for formulating a signal to interference plus noise ratio
A method and system for formulating an sink metric for cells using only the existing rsrp and rsrq measurements. With this method and system side information is exchanged between enbs of an e-utran using the x2 interface where the x2 interface carries the x2 application protocol (x2ap).
Blackberry Limited


06/16/16
20160174091 
 Signal measurement method and apparatus patent thumbnailSignal measurement method and apparatus
The present invention provides a signal measurement method and apparatus, where the method includes: receiving, by user equipment ue, a measurement configuration message sent by a base station, where the measurement configuration message is used to indicate a reference signal type; performing, by the ue according to the reference signal type indicated by the measurement configuration message, signal quality measurement on a cell to obtain a measurement result; and sending, by the ue, the measurement result to the base station. The method provided in embodiments of the present invention is used to resolve a technical problem in the prior art that normal communication of ue cannot be ensured because rsrp and/or rsrq of neighboring cells cannot be measured based on an existing reference signal when the neighboring cells use different carrier types..
Huawei Technologies Co., Ltd.


06/16/16
20160174082 
 Method and  reducing cell identifier conflicts when deploying a new cell into a telecommunications network patent thumbnailMethod and reducing cell identifier conflicts when deploying a new cell into a telecommunications network
The telecommunications network, which includes a plurality of existing cells each having an assigned identifier from a set of identifiers, calculates a value for each existing cell, wherein the value represents the likelihood of an identifier conflict if a new cell is deployed near that existing cell. The value may therefore provide a network operator with an indication of the likelihood of an identifier conflict if a new cell is deployed in a particular area, such that the network operator may proactively avoid identifier conflicts..
Telefonaktiebolaget L M Ericsson (publ)


06/16/16
20160173289 
 Physically uncloneable function device using mram patent thumbnailPhysically uncloneable function device using mram
In some examples, a first delay path and a second delay path may each be configured to receive a signal as an input signal at the same time, propagate the input a plurality of mram cells, and output the propagated input signal for an arbiter. The arbiter may be configured to output a response value based at least in part on a relative order of arrival of the propagated input signals from the first and second delay paths..
Honeywell International Inc.


06/16/16
20160173269 
 Digital to analog converter cell for signed operation patent thumbnailDigital to analog converter cell for signed operation
A communication system receives an inputs signal and generates a converted output signal. A control signal selectively activates one or more source cells among an array of cells.
Intel Corporation


06/16/16
20160173264 

Interference management for adaptive tdd with frequency domain separations


A method of wireless communications includes adapting to downlink/uplink resource allocations. In particular, the downlink/uplink communications may be adjusted according to time division duplexed (tdd) configurations of serving and neighbor cells..
Qualcomm Incorporated


06/16/16
20160173233 

Transmitter and transmitting and receiver and receiving


A transmitter transmits data using orthogonal frequency division, ofdm, symbols. The transmitter comprising a forward error correction encoder configured to encode the data to form forward error correction encoded frames of encoded data cells, a service frame builder configured to form a service frame for transmission comprising a plurality of forward error correction encoded frames, a convolutional interleaver comprising a plurality of delay portions and configured to convolutionally interleave the data cells of the service frames, a modulation symbol mapper configured to map the interleaved and encoded data cells of the service frames onto modulation cells, and a modulator configured to modulate the sub-carriers of one or more ofdm symbols with the modulation cells.
Sony Corporation


06/16/16
20160173104 

Programmable forwarding plane


A forwarding plane comprising a scalable array of field programmable gate array (fpga) devices, a memory bank, fpga data and transport network ports, and an array interconnect. The scalable array is configured to execute a networking application source code partitioned as computing elements executed by the fpga devices with a uniform global memory address space.
Scientific Concepts International Corporation


06/16/16
20160173103 

Space-multiplexing dram-based reconfigurable logic


According to one general aspect, an apparatus may include a random access memory array that, in turn, includes a reconfigurable look-up table. The reconfigurable look-up table may include memory cells configured to simultaneously store a plurality of look-up tables, wherein each look-up table is associated with a respective logic function.
Samsung Electronics Co., Ltd.


06/16/16
20160173102 

Dram-based reconfigurable logic


According to one general aspect, an apparatus may include a memory array comprising a plurality of memory sub-arrays. At least one of the sub-arrays may be arranged as a reconfigurable look-up table.

06/16/16
20160173101 

Reconfigurable logic architecture


According to one general aspect, an apparatus may include a plurality of stacked integrated circuit dies. The dies may include a memory cell die configured to store data in a random access fashion.
Samsung Electronics Co., Ltd.


06/16/16
20160173069 

Voltage-controlled ring oscillator with delay line


The invention relates to a multi-phase oscillator for generating multiple phase-shifted oscillator signals including: a ring oscillator having a number of concatenated oscillator delay cells which are interconnected to generate an oscillator signal, wherein phase-shifted oscillator signals are generated between the oscillator delay cells; a phase-blending unit configured to receive two phase-shifted oscillator signals and to generate a mid-phase oscillator signal whose phase shift is between the shifts of the two phase-shifted oscillator signals; and an interpolator delay line having a number of concatenated interpolator delay cells to generate further phase-shifted oscillator signals.. .
International Business Machines Corporation


06/16/16
20160172991 

Converter arrangement


A converter arrangement comprises first and second modular multilevel converters, each of the modular multilevel converters comprises two converter branches. Each converter branch comprises a plurality of series-connected converter cells.
Abb Technology Ag


06/16/16
20160172871 

Wireless power transmitter


A wireless power transmitter according to an embodiment includes a coil and a capacitor which resonate with a wireless power receiver. The coil includes a plurality of cell groups and a core which connects the cell groups with each other.
Lg Innotek Co., Ltd.


06/16/16
20160172863 

Smart junction box for photovoltaic solar power modules with novel power supply circuits and related operation


A smart junction box for a photovoltaic solar power module, and related method of operation. The junction box includes a plurality of active bypass circuits for protecting the solar cells from reverse bias, a novel power supply circuit in several embodiments that can operate with input voltages of either positive or negative polarity, a capacitor for storing and supplying energy, and a master control circuit.
Sunfield Semiconductor Inc.


06/16/16
20160172822 

Optically-induced charge separation and induced magnetism in dielectrics for optical energy conversion and intense magnetic field generation


Schemes are described to produce quasi-static charge separation, terahertz radiation, and programmable magnetic field generation using linearly-polarized light in unbiased, transparent insulators. The methods exploit a recently-observed magneto-electric optical nonlinearity that produces intense magnetization in undoped, homogeneous dielectrics.
The Regents Of The University Of Michigan


06/16/16
20160172721 

Power storage apparatus and electric vehicle


A power storage apparatus, electric device, electric vehicle, and power system are disclosed. In an example embodiment, a power storage apparatus includes a battery block comprising a plurality of battery cells and an isolating unit that enables wireless information transfer regarding battery information of the battery block..
Sony Corporation


06/16/16
20160172715 

Secondary battery pack


Provided is a secondary battery pack including a plurality of secondary battery modules including a plurality of secondary battery cells stacked in parallel to each other in a vertical direction, a cover, and a switch installed at an upper side of the one end in the horizontal direction of the cover, a housing, a power relay assembly (pra) including a relay electrically connected to the secondary battery cells and switches, for transmitting charging power supplied from the outside to the secondary battery cells when the relay is in a close state and changing the relay to an open state when the switch is pushed according to pressure applied to an upper side from a lower surface of the cover, and a battery management system (bms) for controlling the power relay assembly (pra).. .
Ski Innovation Co., Ltd.


06/16/16
20160172713 

Methods for joining ceramic and metallic structures


A method for joining a ceramic component to a metallic component is described. At least one initial layer of an active metal is applied to one of the joining surfaces, by a cold spray technique.
General Electric Company


06/16/16
20160172703 

Fuel cell stack assembly


A fuel cell stack assembly (101) comprising a fuel cell stack (102) comprising one or more fuel cells and a retaining member (100) comprising a first engaging region (104) that engages a first end face (110) of the fuel cell stack (102), a second engaging region (106) that engages a second opposing end face (112) of the fuel cell stack (102, and a joining region (108) configured to bias the first engaging region (104) towards the second engaging region (106). The retaining member (106) defines a fluid chamber (118) for communicating a fluid to or from the fuel cell stack (102)..
Intelligent Energy Limited


06/16/16
20160172687 

Oxide-coated metal catalyst for composite electrode and preparing composite electrode using the same


Disclosed are an oxide-coated metal catalyst for a composite electrode and a method for preparing a composite electrode using the same. The metal catalyst includes oxide particles applied thereto, wherein the oxide particles are applied so as not to overlap one another or are applied as an independent separate layer, and the oxide particles are nanograins having a diameter of 1-500 nm.
Global Frontier Center For Multiscale Energy Systems


06/16/16
20160172684 

Solid oxide fuel cell manufacturing solid oxide fuel cell


The invention provides a solid oxide fuel cell having a cathode which uses a material that exhibits minimal variation in the linear expansion coefficient and has superior conductivity and catalytic activity, and also provides a manufacturing method for the solid oxide fuel cell. The solid oxide fuel cell has single fuel cells comprising an anode, a solid electrolyte membrane and a cathode, wherein at least a portion of the cathode comprises a perovskite oxide represented by lay(ni1-xfex)o3 (wherein 0.1≦x≦0.5 and 0.95≦y<1) as the main component..
Mitsubishi Hitachi Power Systems, Ltd.


06/16/16
20160172683 

Impregnation process using a bio-templating nano-catalyst incorporation into the electrodes of solid-state electrochemical cells


A process for incorporating a nanocatalyst on the surface of and within the pores of an electrode comprising subjecting an electrode to a singular template impregnation to form a treated electrode having a bio-template layer; and then subjecting the treated electrode to a singular nano-catalyst impregnation for tethering the nano-catalyst to the treated electrode; and then removing the bio-template layer by performing thermolysis upon the treated electrode for forming a nano-catalyst bonded on the surface and within the pores of the electrode. A modified electrode or product made by this process is provided..
West Virginia University


06/16/16
20160172676 

Metal hydride compositions and lithium ion batteries


Heterogeneous metal hydride (mh) compositions comprising a main region comprising a first metal hydride and a secondary region comprising one or more additional components selected from the group consisting of second metal hydrides, metals, metal alloys and further metal compounds are suitable as anode materials for lithium ion cells. The first metal hydride is for example mgh2.
Basf Corporation


06/16/16
20160172669 

Metal hydride compositions and lithium ion batteries


Heterogeneous metal hydride (mh) compositions comprising a main region comprising a first metal hydride and a secondary region comprising one or more additional components selected from the group consisting of second metal hydrides, metals, metal alloys and further metal compounds are suitable as anode materials for lithium ion cells. The first metal hydride is for example mgh2.
Basf Corporation


06/16/16
20160172668 

Lithium oxyhalide electrochemical cell with carbon monofluoride


The present invention relates to an oxyhalide electrochemical cell comprising an anode of a group ia metal and a cathode of a composite material prepared from a first electrochemically active carbonaceous material and a second electrochemically non-active carbonaceous material. The cathode material of the present invention provides increased discharge capacity compared to traditional lithium oxyhalide cells.
Electrochem Solutions, Inc.


06/16/16
20160172654 

Battery module assembly having communication terminals of bms protruding from front thereof


Disclosed herein is a battery module assembly having unit modules, each of which is configured to have a structure in which unit cells are loaded on a cartridge in a state in which the unit cells are electrically connected to each other via busbars, the battery module assembly including two or more sub-modules arranged in a lateral direction while being spaced apart from each other, each of the sub-modules including two or more unit modules that are stacked in a height direction from the ground, a battery management system (bms) mounted in a space defined between the sub-modules, the bms being provided at one side thereof with communication terminals, a base plate on which the sub-modules and the bms are loaded, side cover plates mounted at sides of the sub-modules, a top cover plate loaded on top surfaces of the sub-modules, the top cover plate being coupled to the sub-modules and to the side cover plates by fastening, and a front cover plate mounted at fronts of the sub-modules, the front cover plate being coupled to the sub-modules, the base plate, and the side cover plates, the front cover plate being provided with through holes, through which the communication terminals are exposed.. .
Lg Chem, Ltd.


06/16/16
20160172653 

Battery containment


A battery housing for lithium ion cells includes a plurality of cell modules, having a plurality of cells between a top conductive plate and a bottom conductive plate and attached to a conductive plate by tabs attached to similarly polarized ends of each of the cells in the module to define a parallel connection between all of the cells in the module. A battery housing stacks the modules to define a series connection between the charge plates, and electrically couples adjacent stacks with a common charge plate to define a series connection between each of the stacks.
Nec Energy Solutions, Inc.


06/16/16
20160172652 

Battery wiring module


A battery wiring module is to be combined with a battery module including a plurality of battery cells stacked in a state of being alternatively reversed so that a positive electrode terminal and a negative electrode terminal are adjoined between the adjacent battery cells. The battery wiring module is provided with a plurality of linear conductors which are arranged at an interval, a plurality of bus bars which are arranged at an interval along to at least one side of the plurality of linear conductors so that each of the plurality of bus bars electrically connects the positive electrode terminal and the negative electrode terminal adjacent to each other, and an insulation resin part including both a covering part for covering an outer periphery of the plurality of linear conductors and a bus bar connection part..
Yazaki Corporation


06/16/16
20160172651 

Battery wiring module and battery wiring module manufacturing method


A battery wiring module is to be combined with a battery module including a plurality of battery cells stacked in a state of being alternatively reversed so that a positive electrode terminal and a negative electrode terminal are adjoined between the adjacent battery cells. The battery wiring module is provided with a plurality of linear conductors which are arranged in parallel at an interval, a plurality of bus bars which are arranged at a predetermined interval along to at least one side of the plurality of linear conductors, and an insulation resin part which integrally covers both an outer periphery of the plurality of linear conductors and side edges of the plurality of bus bars adjacent to the linear conductors..
Yazaki Corporation


06/16/16
20160172649 

Battery pack interconnection system


A battery pack assembly has a plurality of interconnected battery cells and is suitable for use in an electric vehicle or a hybrid electric vehicle. The assembly includes a first battery cell having a first terminal and a second battery cell having a second terminal electrically interconnected by a bus bar formed of a conductive material and attached to the first terminal and the second terminal.
Delphi Technologies, Inc.


06/16/16
20160172647 

Assembled battery


An assembled battery includes a plurality of battery cells, a bus bar that electrically connects the battery cells with each other, and a circuit board that is electrically connected with the battery cells. The bus bar has a first connection part that is electrically connected with the battery cells, and a second connection part that is electrically connected with a connection part of the circuit board via a conductive adhesive.
Toyota Jidosha Kabushiki Kaisha


06/16/16
20160172642 

Battery module system


A battery is provided comprising a plurality of cylindrical type cells. Three cylindrical cells may be arranged in a triangular configuration with an electrical isolation spacer positioned between the three cylindrical cells, and a casing may be wrapped around the cells to restrict relative movement of the cells forming a cell group.
A123 Systems, Llc


06/16/16
20160172635 

Battery cell having a prismatic or cylindrical housing, battery module and motor vehicle


A battery cell, preferably a lithium ion battery cell, includes a prismatic or cylindrical housing with two opposite sides. The first side of the two opposite sides of the housing is partially or completely at cathode potential.
Samsung Sdi Co., Ltd.


06/16/16
20160172587 

Memory cells, integrated devices, and methods of forming memory cells


Some embodiments include integrated devices, such as memory cells. The devices may include chalcogenide material, an electrically conductive material over the chalcogenide material, and a thermal sink between the electrically conductive material and the chalcogenide material.
Micron Technology, Inc.


06/16/16
20160172521 

Solar concentrator with microreflectors


A solar concentrator for a solar panel that has a transparent substrate with photovoltaic cells arranged spaced apart in contact with the bottom of the substrate. Microreflectors arranged between the photovoltaic cells and in contact with the bottom of the substrate receive a portion of the sunlight incident upon the solar panel and direct the sunlight portion back through the substrate.
Corning Incorporated


06/16/16
20160172520 

Solar cell module


A solar cell module includes a solar cell string including solar cells disposed in an arrangement direction and at least two wiring members provided to extend along the arrangement direction in order to electrically connect the solar cells. The at least two wiring members include a first wiring member disposed at a first position where a distance between the solar cells adjacent to each other is short and a second wiring member disposed at a second position where the distance between the solar cells adjacent to each other is long.
Panasonic Intellectual Property Management Co., Ltd.


06/16/16
20160172519 

Electrode soldering a back contact solar module


An electrode soldering method for a back contact solar module is to place a curved solder part on two electrode solder pads of two solar cells on a substrate respectively, and to solder the curved solder part on the electrode solder pads. The curved solder part includes a curved portion between the two electrode solder pads.
Au Optronics Corp.


06/16/16
20160172516 

Thick damage buffer for foil-based metallization of solar cells


Approaches for the foil-based metallization of solar cells and the resulting solar cells are described. A method involves patterning a first surface of a metal foil to provide a plurality of alternating grooves and ridges in the metal foil.

06/16/16
20160172512 

Laminated backplane for solar cells


A back contact solar cell structure having a light receiving frontside and a metallized backside of on-cell patterned base and emitter metallization electrically connected to base and emitter regions on a back contact solar cell semiconductor substrate. A backplane laminate layer made of resin and fibers and having a coefficient of thermal expansion relatively matched to the back contact solar cell semiconductor substrate is attached to the on-cell base and emitter metallization and to portions of the back contact solar cell semiconductor substrate not covered by the on-cell base and emitter metallization..
Solexel, Inc.


06/16/16
20160172510 

Photovoltaic module


The invention relates to bifacial solar cells and a photovoltaic module comprising several bifacial solar cells and an electrical connecting structure, through which the solar cells are electrically connected. The solar cells are configured rectangular with an aspect ratio different from one.
Solarworld Innovations Gmbh


06/16/16
20160172494 

Memory cell array and cell structure thereof


A memory device includes a substrate and a memory array. The substrate has a continuous active region.
Taiwan Semiconductor Manufacturing Company Limited


06/16/16
20160172457 

Methods of fabricating silicon nanowires and devices containing silicon nanowires


The present disclosure also relates to lithium ion batteries, thermoelectric materials, solar cells, chemical and biological sensors, and drug delivery devices containing silicon nanowires. .

06/16/16
20160172375 

Methods for cell boundary encroachment and semiconductor devices implementing the same


A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner.
Tela Innovations, Inc.


06/16/16
20160172290 

Interposer with lattice construction and embedded conductive metal structures


A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material.
International Business Machines Corporation


06/16/16
20160172288 

Interposer with lattice construction and embedded conductive metal structures


A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material.
International Business Machines Corporation


06/16/16
20160172059 

Apparatus for boosting source-line voltage to reduce leakage in resistive memories


Described is an apparatus comprising a leakage tracker to track leakage of a column of resistive memory cells; and a circuit for adjusting voltage on a sourceline (sl) of the column of resistive memory cells. Described is also an apparatus comprising: a memory array having rows and columns of resistive memory cells; a leakage tracker to track leakage current of a column of resistive memory cells associated with the memory array; and a circuit, coupled to the leakage tracker, for adaptively boosting voltage on a sl of the column of resistive memory cells during read operation..
Intel Corporation


06/16/16
20160172056 

Semiconductor device


A semiconductor device includes a memory array including a plurality of memory blocks, wherein the memory blocks are grouped into sub-block groups, and the sub-block groups are grouped into main block groups; an operation circuit suitable for performing a read operation and a test read operation on memory cells included in the memory block; and a read counter suitable for counting a first number of read operations for each word line in the respective main block groups and a second number of read operations for the respective sub-block groups.. .
Sk Hynix Inc.


06/16/16
20160172053 

Otp memory capable of performing multi-programming and semiconductor memory device including the same


A one-time programmable (otp) memory capable of performing a multi-programming and a semiconductor memory device including the otp memory are disclosed. The otp memory includes a plurality of fuse cells in which two or more fuse cells are programmed at a time.
Samsung Electronics Co., Ltd.


06/16/16
20160172052 

Memory array with read only cells having multiple states and programming thereof


A read only memory (rom) having a first row of rom cells, a first conductive line along the first row of rom cells, and a second conductive line along the first row of rom cells. The rom cells of the first row of rom cells are selectively coupled during programming to the first conductive line and the second conductive line so that in a first mode of the rom the first row of rom cells provide a first combination of logic highs and logic lows and in a second mode of the memory the first row of rom cells provide a second combination of logic highs and lows independent of the first combination of logic highs and logic lows..
Freescale Semiconductor, Inc.


06/16/16
20160172051 

Temperature compensation management in solid-state memory


Systems and methods are disclosed for programming data in a non-volatile memory array are disclosed. A data storage device includes a non-volatile memory array including a plurality of non-volatile memory cells and a controller configured to receive a signal indicating a temperature of at least a portion of the data storage device.
Western Digital Technologies, Inc.


06/16/16
20160172050 

Semiconductor memory device and operating method thereof


A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program pulse applying operation and a verify operation on the memory cell array, a pass/fail check circuit performing a pass/fail check operation on a program operation including the program pulse applying operation and the verify operation, and a control logic controlling the peripheral circuit and the pass/fall check circuit to perform the pass/fail check operation during the program pulse applying operation.. .
Sk Hynix Inc.


06/16/16
20160172048 

Semiconductor memory device


A semiconductor memory device is provided. The semiconductor memory device includes memory strings including drain-side memory cells connected between a bit line and a pipe transistor, and source-side memory cells connected between the pipe transistor and a source line, and a peripheral circuit suitable for applying a pipe gate voltage to a pipe gate of the pipe transistor before applying pass voltages to turn on non-selected memory cells among the drain-side memory cells and the source-side memory cells during a read operation..
Sk Hynix Inc.


06/16/16
20160172047 

Semiconductor device and operating method thereof


A semiconductor device includes a memory array including memory blocks; and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the program loop is performed by controlling a target threshold voltage value of the selection transistors based on a difference between a cell current value of the selected memory block and a reference cell current value.. .
Sk Hynix Inc.


06/16/16
20160172046 

Storage devices and methods of operating storage devices


A storage device includes a nonvolatile memory having a plurality of memory cells and a memory controller to control the nonvolatile memory. The operating method of the storage device includes reading previously programmed memory cells among the memory cells of the nonvolatile memory and determining a time after erase of the previously programmed memory cells, programming selected memory cells of the nonvolatile memory, and programming meta data including a time after erase of the selected memory cells, based on the determined time after erase of the previously programmed memory cells..
Samsung Electronics Co., Ltd.


06/16/16
20160172044 

Method to recover cycling damage and improve long term data retention


Techniques for reversing damage caused by program-erase cycles in charge-trapping memory to improve long term data retention. A recovery process improves the data retention of a block of memory cells by programming the memory cells to a relatively high threshold voltage and enforcing a time period of several minutes or hours in which the memory cells are inactive and remain at the relatively high vth levels.
Sandisk Technologies Inc.


06/16/16
20160172041 

Sequential write and sequential write verify in memory device


Some embodiments include apparatuses and methods for performing a first stage of an operation of storing information in a first memory cell and a second memory cell, and performing a second stage of the operation after the first stage to determine whether each of the first and second memory cells reaches a target state. The first memory cell is included in a first memory cell string coupled to a data line through a first select transistor.
Micron Technology, Inc.


06/16/16
20160172039 

Semiconductor memory device and operating the same


A semiconductor memory device and a method of operating the same are provided. The device includes a memory cell array including a plurality of memory cells is arranged in a plurality of columns, a peripheral circuit configured to program selected memory cells of the memory cells when a program operation is performed, and a control logic configured to control the peripheral circuit during the program operation.
Sk Hynix Inc.


06/16/16
20160172038 

Converting an xy tcam to a value tcam


Approaches for an integrated circuit ternary content addressable memory (tcam) are provided. A system includes an array of xy tcam cells and respective translation circuits connected to respective pairs of the xy tcam cells.
Globalfoundries Inc.


06/16/16
20160172036 

Memory cell with retention using resistive memory


Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: a memory element including cross-coupled cells having a first node and a second node; a first transistor coupled to the first node; a second transistor coupled to the second node; and a resistive memory element coupled to the first and second transistors..

06/16/16
20160172032 

Semiconductor memory device and controlling semiconductor memory device


According to one embodiment, a semiconductor memory device includes a cell array including a plurality of memory cells, a reference circuit, a sense amplifier for sensing a read current flowing through the memory cell, and a reference current flowing through the reference circuit, a write driver for writing data to the memory cell, a sub cell area including the cell array, the sense amplifier, and the write driver, a memory area including a plurality of sub cell areas, and a control circuit for supplying first write data to the sub cell area including the sense amplifier which performs a first read operation of supplying the read current to a selected memory cell without supplying the reference current.. .
Kabushiki Kaisha Toshiba


06/16/16
20160172031 

Memory systems and memory programming methods


Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a memory array comprising a plurality of memory cells individually configured to have a plurality of different memory states, access circuitry configured to apply signals to the memory cells to program the memory cells to the different memory states, and a controller to configured to control the access circuitry to apply a first of the signals to one of the memory cells to program the one memory cell from a first memory state to a second memory state different than the first memory state, to determine that the one memory cell failed to place into the second memory state as a result of the application of the first signal, and to control the access circuitry to apply a second signal to the one memory cell to program the one memory cell from the first memory state to the second memory state as a result of the determination, wherein the first and second signals have a different electrical characteristic..
Micron Technology, Inc.


06/16/16
20160172030 

Methods, articles and devices for pulse adjustments to program a memory cell


Embodiments disclosed herein may relate to adjusting an aspect of a programming pulse for one or more memory cells, such as based at least in part on one or more detected programmed resistance values for the one or more memory cells.. .
Micron Technology, Inc.


06/16/16
20160172029 

Nonvolitile memory refresh


A system and method of refreshing a nonvolatile memory having memory cells. The method includes identifying one or more of the memory cells that do not satisfy a data retention test; remapping the one or more identified memory cells from original memory addresses to spare memory addresses; and refreshing the identified memory cells..
Infineon Technologies Ag


06/16/16
20160172027 

Polymer memory


A integrated circuit device with a polymer memory array includes active circuits formed in lower layers of a multi-level interconnect structure and a semiconductor substrate and also includes an array of polymer memory cells formed in an upper interconnect level having a plurality of cell node electrodes and source line electrodes for the polymer memory array, each polymer memory cell including a passive layer having at least one conductivity-facilitating compound that is formed on top and sidewall surfaces of a source line electrode, and an active layer having an impedance state that can change that is formed on top and sidewall surfaces of an adjacent cell node electrode with sufficient thickness to make direct physical contact with the passive layer.. .
Conversant Intellectual Property Management Inc.


06/16/16
20160172026 

Semiconductor memory devices having separate sensing circuits and related sensing methods


A sensing circuit of a semiconductor memory device is provided which includes a bit line having a first edge and a second edge, a sensing line, a current supply unit, and a sense amplifier. A plurality of memory cells is connected between the first edge and the second edge.

06/16/16
20160172025 

Access signal adjustment circuits and methods for memory cells in a cross-point array


Systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and an access signal generator.
Unity Semiconductor Corporation


06/16/16
20160172024 

Non-volatile sram with multiple storage states


Technologies are generally described herein for a non-volatile static random access memory device with multiple storage states. In some examples, the multi-storage state non-volatile random access memory device has two or more memory cells.
Empire Technology Development Llc


06/16/16
20160172023 

Semiconductor memory device for stably reading and writing data


In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column.
Renesas Electronics Corporation


06/16/16
20160172015 

Apparatuses and methods for performing logical operations using sensing circuitry


The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array.
Micron Technology, Inc.


06/16/16
20160171890 

Device for detecting proximity of a vehicle and system for monitoring parking spaces of a parking lot


A device for detecting proximity adapted to monitor a parking space, which has relatively small dimensions, is autonomous from the energy point of view even when positioned in the middle of the parking space and does not require the provision of stations outside the parking space to be supplied by photovoltaic cells. The architecture of the device is organized in such a way as to be able to keep almost all its components turned off, which are all turned on only when there is the need to detect whether the parking space is occupied or free and only for the time strictly needed to perform this operation.
Kiunsys S.r.i.


06/16/16
20160171149 

Methods and automated design of semiconductor photonic devices


A photonic design automation (pda) tool to facilitate design of semiconductor photonic devices is described. In one example, the pda tool includes a process design library including one or more photonics parameterized cells (pcells), a plurality of processor-executable photonics design functions including a design rule check (drc) violation removal function, and a semiconductor technology-dependent parameter file including a plurality of design rules that define allowed semiconductor design patterns to be converted to a plurality of semiconductor fabrication mask designs in a first semiconductor technology.





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