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Cache-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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Synchronizing video signals using cached key frames
Getgo, Inc.
June 14, 2018 - N°20180167631

A technique for synchronizing video receivers with a video stream already in progress includes caching a key frame in a transport protocol component of a video communication system and providing the key frame on demand to any receiver attempting to join the stream and/or to rejoin the stream after an error, such as a dropped packet. Once a receiver ...
User device ad-hoc distributed caching of content
Verizon Patent And Licensing Inc.
June 14, 2018 - N°20180167486

A device receives a user election of participation in a distributed cache service, and receives user selection of one or more devices, that are each associated with the user, to register with the distributed cache service as participant nodes. The device determines an amount of available storage offered to the cache service for each of the one or more participant ...
Cache proxy for a network management information base
Arris Enterprises Llc
June 14, 2018 - N°20180167485

In one embodiment, a proxy forwards a first request from a manager for an object in a management information base to an agent in a network device, the object describing a characteristic of the network device. The proxy receives the object from the agent and categorizes the object in a category of a plurality of categories based on a characteristic ...
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Computer-implemented method, apparatus, and computer-readable medium for processing named entity queries using a cached functionality ...
Verisign, Inc.
June 14, 2018 - N°20180167353

The present disclosure relates to a computer-implemented method for responding to a query request from a requester using information supplied by an authoritative name server. The computer-implemented method can include obtaining, by a dns resolution server, a query for a named resource from a requester, wherein the query comprises information comprising contextual information related to the requester.
Application identification cache
Hewlett Packard Enterprise Development Lp
June 14, 2018 - N°20180167319

In some examples, a method includes parsing a packet received by the network device to identify a packet header value of the packet and performing a lookup into an application identification cache using the packet header value to identify the packet as part of a traffic flow of a particular application.. .
Method and apparatus for rendering object using mipmap including plurality of textures
Samsung Electronics Co., Ltd.
June 14, 2018 - N°20180165869

A method and an apparatus for rendering an object by using a mipmap including n+1 textures having resolutions that are reduced from level 0 to level n are provided. The object may be rendered by obtaining a coordinate of a pixel to be rendered, obtaining an index value related to the obtained coordinate, determining availability of a cached texel with respect ...
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Techniques for tiling compute work with graphics work
Nvidia Corporation
June 14, 2018 - N°20180165787

A device driver is configured to identify a group of compute shaders to be executed in multiple traversals of a graphics processing pipeline. Each such compute shader accesses a compute tile of data having particular dimensions.
Method and apparatus for obtaining data based on location information
Tencent Technology (shenzhen) Company Limited
June 14, 2018 - N°20180165293

A method and an apparatus for obtaining data, based on location information, are provided. The method includes receiving, from a user terminal, a first query request that is used to obtain object information, the first query request carrying location information of the user terminal, and querying, in response to a cache area being not empty, the cache area for hotspot ...
Efficiently storing intialization vectors
Hewlett Packard Enterprise Development Lp
June 14, 2018 - N°20180165225

Examples relate to efficient storage of initialization vectors in a system. One example facilitates determining an initialization vector for use in encrypting a first cache line of a first page of memory, wherein determining the initialization vector comprises concatenating a page-level counter with a first set of hierarchical counters.
Invalidating reads for cache utilization in processors
Intel Corporation
June 14, 2018 - N°20180165222

In an embodiment, a processor for invalidating cache entries comprises: at least one processing unit; a processor cache; and direct cache unit. The direct cache unit is to receive, from a first device, a direct read request for data in a first cache entry in the processor cache; determine whether the direct read request is an invalidating read request; in ...
No allocate cache policy
Advanced Micro Devices, Inc.
June 14, 2018 - N°20180165221

A system and method for efficiently performing data allocation in a cache memory are described. A lookup is performed in a cache responsive to detecting an access request.
Expiring virtual content from a cache in a virtual universe
International Business Machines Corporation
June 14, 2018 - N°20180165220

Approaches for expiring cached virtual content in a virtual universe are provided. In one approach, there is an expiration tool, including an identification component configured to identify virtual content associated with an avatar in the virtual universe, an analysis component configured to analyze a behavior of the avatar in a region of the virtual universe, the behavior indicating a likely ...
Multi-level cache with associativity collision compensation
Intel Corporation
June 14, 2018 - N°20180165217

In an embodiment, a processor includes at least one core and a first cache memory including a first plurality of sets having a first plurality of cache lines and associated metadata to store address information, recency information and a first indicator to indicate whether the cache line is associated with an oversubscribed set of a second cache memory. A first ...
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Dynamic cache bypassing
Advanced Micro Devices, Inc.
June 14, 2018 - N°20180165214

A processing system fills a memory access request for data from a processor core by bypassing a cache when a write congestion condition is detected, and when transferring the data to the cache would cause eviction of a dirty cache line. The cache is bypassed by transferring the requested data to the processor core or to a different cache.
Method and apparatus for memory consistency using cache coherency protocols
Intel Corporation
June 14, 2018 - N°20180165213

A request is received from a first node over a communication fabric, the request to acquire an access right of a cache line for accessing data stored in a memory location of a memory, the first node being one of a plurality of nodes sharing the memory. In response to the request, a second node is determined based on the ...
High-performance instruction cache system and method
Shanghai Xin Hao Micro Electronics Co. Ltd.
June 14, 2018 - N°20180165212

A high-performance instruction cache method based on extracting instruction information and store in a track table. The method enables reading of all levels of cache, including the last level cache, without performing tag matching.
System and method for store streaming detection and handling
Samsung Electronics Co., Ltd.
June 14, 2018 - N°20180165211

According to one general aspect, an apparatus may include a load/store circuit and a region size detection circuit. The load/store circuit may be configured to issue a plurality of store instructions to store data in a memory system.
Methods, systems and apparatus for predicting the way of a set associative cache
Intel Corporation
June 14, 2018 - N°20180165206

A method for predicting a way of a set associative shadow cache is disclosed. As a part of a method, a request to fetch a first far taken branch instruction of a first cache line from an instruction cache is received, and responsive to a hit in the instruction cache, a predicted way is selected from a way array using ...
Opportunistic increase of ways in memory-side cache
Intel Corporation
June 14, 2018 - N°20180165205

A processor includes a processor core and a cache controller coupled to the processor core. The cache controller is to allocate, for a memory, a plurality of cache entries in a cache, wherein the processor core is to: detect an amount of the memory installed in a computing system and, responsive to detecting less than a maximum allowable amount of ...
Programmable memory prefetcher
Intel Corporation
June 14, 2018 - N°20180165204

A processor may include a programmable hardware prefetch engine and a prefetch engine control register. The processor may include circuitry to receive, during execution of an application, a first instruction for configuring the prefetch engine for prefetching multiple cache lines to be accessed in the future, at predictable locations, by the application; to store, in the prefetch engine control register, ...
Tag and data organization in large memory caches
Advanced Micro Devices, Inc.
June 14, 2018 - N°20180165202

A data processing system includes a processor and a cache controller coupled to the processor, and adapted to be coupled to a memory. The cache controller uses the memory to form a pseudo direct mapped cache having a plurality of groups of pages.
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