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Cache-related patent applications - as published by the U.S. Patent and Trademark Office (USPTO).


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Subtitle switching method and device
Shenzhen Tcl Digital Technology Ltd.
December 07, 2017 - N°20170353770

Disclosed are a subtitle switching method and device, the method comprising the following steps: receiving a subtitle switching instruction input by a user; acquiring to-be-switched subtitle data corresponding to the subtitle switching instruction and stored in a corresponding preset buffer area and a present time stamp of video and audio data currently being played; and outputting and displaying subtitle data ...
Routing vault access requests in a dispersed storage network
International Business Machines Corporation
December 07, 2017 - N°20170353580

A method for execution by a dispersed storage and task (dst) execution unit that includes a processor includes receiving a vault access request indicating a first one of a plurality of vaults. Processing unit options data that indicates a set of dst processing units is generated based on an access cache that includes a plurality of access entries, where each ...
Cached data expiration and refresh
Home Box Office, Inc.
December 07, 2017 - N°20170353577

The described technology is directed towards maintaining a cache of data items, with cached data items having current value subsets and next value subsets. The cache is accessed for data item requests, to return a cache miss if a requested data item is not cached, to return data from the current value subset if not expired, to return data from ...
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Caching for unique combination reads in a dispersed storage network
International Business Machines Corporation
December 07, 2017 - N°20170353575

A method includes receiving a first access request that indicates a first data object stored as encoded slices in a plurality of storage units. A first desired slice set is selected, based on the requesting module, that includes a first subset of encoded slices of the first data object. Absent slice data is generated based on searching a local cache, ...
System and method for mobile platform cache using mobile devices
Gm Global Technology Operations Llc
December 07, 2017 - N°20170353574

A system and method that enables large content data transfers to mobile platforms is provided. The mobile platform cache system and method provided build a cache suitable for large content data transfers using the available storage capacity of one or more frequently used, existing mobile devices. The provided mobile cache system and method prioritize available free or low cost communication ...
Network caching of outbound content from endpoint device to prevent unauthorized extraction
At&t Intellectual Property I, L.p.
December 07, 2017 - N°20170353501

Methods, computer-readable media and devices are disclosed for storing content from an endpoint device in a network cache. For example, a processor receives a security policy for the endpoint device defining a type of content for storing in the network cache, and determines that traffic from the endpoint device includes content of the content type for storing in the network ...
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Performing database operations using a vectorized approach or a non-vectorized approach
Oracle International Corporation
December 07, 2017 - N°20170351670

Techniques for performing database operations using vectorized instructions are provided. In one technique, it is determined whether to perform a database operation using one or more vectorized instructions or without using any vectorized instructions. This determination may comprise estimating a first cost of performing the database operation using one or more vectorized instructions and estimating a second cost of performing ...
Transaction processing method, processing node, central node, and cluster
Huawei Technologies Co., Ltd.
December 07, 2017 - N°20170351667

The disclosure discloses a transaction processing method, a processing node, and a central node. The method includes: receiving, by the processing node in the cluster, global snapshot information according to a preset time interval, where the global snapshot information includes a transaction identifier of a running transaction in a cluster; storing the received global snapshot information in a cache; and ...
Multi-level data cache and storage on a memory bus
Fusion Memory
December 07, 2017 - N°20170351626

This invention provides a system having a processor assembly interconnected to a memory bus and a memory-storage combine, interconnected to the memory bus. The memory-storage combine is adapted to allow access, through the memory bus, a combination of random access memory (ram) based data storage and non-volatile mass data storage. A controller is arranged to address the both ram based ...
Caching framework for big-data engines in the cloud
Qubole Inc
December 07, 2017 - N°20170351620

The present invention is generally directed to a caching framework that provides a common abstraction across one or more big data engines, comprising a cache filesystem including a cache filesystem interface used by applications to access cloud storage through a cache subsystem, the cache filesystem interface in communication with a big data engine extension and a cache manager; the big ...
Demote scan processing to demote tracks from cache
International Business Machines Corporation
December 07, 2017 - N°20170351619

Provided are a computer program product, system, and method demote scan processing to demote tracks from cache. Tracks in the storage stored in the cache are indicated in a cache list. The cache list is scanned to determine unmodified tracks to initiate to demote. In response to processing an indicated modified track in the cache list while scanning the cache ...
Invoking demote threads on processors to demote tracks indicated in demote ready lists from a ...
International Business Machines Corporation
December 07, 2017 - N°20170351618

Provided are a computer program product, system, and method for invoking demote threads on processors to demote tracks from a cache. A plurality of demote ready lists indicate tracks eligible to demote from the cache. In response to determining that a number of free cache segments in the cache is below a free cache segment threshold, a determination is made ...
Cache management
International Business Machines Corporation
December 07, 2017 - N°20170351615

It is determined that a cache operation relating to the transfer of data between a cache memory and a data storage system is required. A state of a utilization model is received, the utilization model including requirements for utilization of resources of the data storage system over a time period, and the state indicating a cost of resource utilization associated ...
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Preservation of modified cache data in local non-volatile storage following a failover
International Business Machines Corporation
December 07, 2017 - N°20170351613

A dual-server based storage system maintains a first cache and a first non-volatile storage (nvs) in a first server, and a second cache and a second nvs in a second server, where data in the first cache is also written in the second nvs and data in the second cache is also written in the first nvs. In response to ...
Data processing method and device in cache coherence directory architecture
National University Of Singapore
December 07, 2017 - N°20170351612

The embodiment of the disclosure discloses a data processing method and device in a cache coherence directory architecture. The method includes that allocating a tag entry in a tag array for a data block; allocating a data entry in a data array for the data block when the data block is actively shared; and de-allocating the data entry when the ...
Invoking input/output (i/o) threads and demote threads on processors to demote tracks from ...
International Business Machines Corporation
December 07, 2017 - N°20170351611

Provided are a computer program product, system, and method for invoking input/output (i/o) threads and demote threads on processors to demote tracks from a cache. An input/output (i/o) thread, executed by a processor, processes i/o requests directed to tracks from the storage stored in the cache. A demote thread, executed by the processor, processes a ...
Modulization of cache structure in microprocessor
Synopsys, Inc.
December 07, 2017 - N°20170351610

Embodiments of the present disclosure support implementation of a level-1 (l1) cache in a microprocessor based on independently accessed data and tag arrays. Presented implementations of l1 cache do not require any stall pipeline mechanism for stalling execution of instructions, leading to improved microprocessor performance. A data array in the cache is interfaced with one or more data index queues ...
Storage drive dependent track removal in a cache for storage
International Business Machines Corporation
December 07, 2017 - N°20170351609

In one embodiment, storage drive dependent track removal processing logic performs destage tasks for tracks cached in a cache as a function of whether the storage drive is classified as a fast class or as slow class of storage drives, for example. In one embodiment, a destage task configured for a slow class storage drive, transfers an entry for a ...
Managing a redundant computerized database using a replicated database cache
International Business Machines Corporation
December 07, 2017 - N°20170351584

Data in a database cache in memory of an operating database server is copied to memory of a standby database server, without requiring synchronization between the operating server and the standby server. If the operating server fails, the database is recovered to a consistent state in the standby server using a sequential database log and the copied data in the ...
Live migration of virtual machine
Alibaba Group Holding Limited
December 07, 2017 - N°20170351556

A method for live migration of a virtual machine includes receiving a data packet that is sent to a migrated virtual machine on the source physical machine in a stage when the migrated virtual machine is suspended, and caching the received data packet; and sending the cached data packet to the migrated virtual machine on the destination physical machine after ...
Instruction and logic for total store elimination
Intel Corporation
December 07, 2017 - N°20170351516

A processor includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, and a binary translator. The binary translator includes circuitry to identify a redundant store in the instruction stream, mark the start and end of a region of the instruction stream with the redundant ...
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