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Arrays patents

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Parallel configuration of a reconfigurable instruction cell array

Mirrored data storage with improved data reliability

Hierarchically divided signal path for characterizing integrated circuits

Date/App# patent app List of recent Arrays-related patents
 Reduced uncorrectable memory errors patent thumbnailReduced uncorrectable memory errors
Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively..
 Parallel configuration of a reconfigurable instruction cell array patent thumbnailParallel configuration of a reconfigurable instruction cell array
A reconfigurable instruction cell array (rica) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in a latch array for the switch box.
 Mirrored data storage with improved data reliability patent thumbnailMirrored data storage with improved data reliability
A plurality of arrays of storage devices, each providing dual storage device redundancy, is provided. The plurality of arrays of storage devices includes a plurality of mirrored sets of primary storage devices, each including an even number of at least two or more primary storage devices.
 Hierarchically divided signal path for characterizing integrated circuits patent thumbnailHierarchically divided signal path for characterizing integrated circuits
An apparatus includes an output pad, a plurality of arrays of test devices, a hierarchy of selection devices, and address logic. The hierarchy of selection devices includes a plurality of levels coupled between the output pad and the arrays of test devices.
 Viral nanoarrys and sensors comprising the same patent thumbnailViral nanoarrys and sensors comprising the same
The present invention provides arrays comprising polypeptides associated with viruses that are immobilized to an electrode in a directional orientation such that the surface area of the electrode and the sensitivity of the electrode is increased. The invention also provides for methods of diagnosing and/or prognosing a certain disease or disorder through contacting a sample from a patient with an array comprising the polypeptides associated with viruses..
 Protein arrays patent thumbnailProtein arrays
Protein arrays are provided comprising single domain antibodies obtainable from camelidae which are capable of detecting even minor changes in the expression of proteins in cell and tissue extracts and having an optimal signal to noise ratio by removing non-informative abundant proteins from said cell or tissue extracts.. .
 Methods of using hur-associated biomarkers to facilitate the diagnosis of, monitoring the disease status of, and the progression of treatment of breast cancers patent thumbnailMethods of using hur-associated biomarkers to facilitate the diagnosis of, monitoring the disease status of, and the progression of treatment of breast cancers
The present invention relates to methods of identifying gene targets, including methods of using ribonucleoprotein (rnp) immunoprecipitation-microarrays to identify cancer gene targets, such as subsets of rnp-associated mrnas in breast cancer cell lines. Also presented, are ribonucleotide binding protein-associated biomarkers, panels or sets of ribonucleotide binding protein-associated biomarkers, methods and compositions comprising ribonucleotide-binding protein, associated nucleotides, nucleotide arrays, and kits, plus methods of using hur-associated biomarkers to facilitate the diagnosis of, monitoring the disease status of, and the progression of treatment of breast cancers to facilitate the diagnosis of and monitoring the disease status or progression of treatment of breast cancers, including drug-resistant breast cancers..
 Metal oxide nanorod arrays on monolithic substrates patent thumbnailMetal oxide nanorod arrays on monolithic substrates
A metal oxide nanorod array structure according to embodiments disclosed herein includes a monolithic substrate having a surface and multiple channels, an interface layer bonded to the surface of the substrate, and a metal oxide nanorod array coupled to the substrate surface via the interface layer. The metal oxide can include ceria, zinc oxide, tin oxide, alumina, zirconia, cobalt oxide, and gallium oxide.
 Memories with memory arrays extending in opposite directions from a semiconductor and their formation patent thumbnailMemories with memory arrays extending in opposite directions from a semiconductor and their formation
Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor.
 Dose and location controlled drug/gene/particle delivery to individual cells by nanoelectroporation patent thumbnailDose and location controlled drug/gene/particle delivery to individual cells by nanoelectroporation
A simple and low cost method of producing sealed arrays of laterally ordered nanochannels interconnected to microchannels of tunable size, over large surface areas, is disclosed. The method incorporates dna combing and subsequent imprinting.
Codebook enchancement for long term evolution (lte)
Multiple input multiple output systems using a transmit precoder codebook designed for a four-transmitter (4tx) antenna configuration are described. The 4tx antenna configuration is an attractive option for base stations in cellular network environments and it is desirable to use a transmitter precoder codebook that provides sufficient granularity in typical operating scenarios, and to address various antenna configurations.
Dual-port semiconductor memory and first in first out (fifo) memory having electrically floating body transistor
Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region.
Stable sram cell
Sram cells and sram cell arrays are described. In one embodiment, an sram cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value.
Stable sram cell
Sram cells and sram cell arrays are described. In one embodiment, an sram cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value.
Beacon with illuminated leds array boards connected
A signal lighting beacon for a vehicle has a base and a plurality of led arrays mounted on the base. The led arrays are arranged to direct light signals outward in multiple different radial directions.
Display device including a multifunctional and communicating surface
The invention relates to a display device including a plurality of pixels forming an image, and an optical plate arranged opposite the image and having transparency areas configured to allow the light from the pixels to at least partially pass therethrough. The optical plate further includes at least one array of functional elements corresponding to an electronic and/or mechanical function.
Composites for antennas and other applications
Composite material, devices incorporating the composite material and methods of forming the composite material are provided. The composite material includes interstitial material that has at least one of a select relative permittivity property value and a select relative permeability property value.
Slim triple band antenna array for cellular base stations
The present invention refers to a triple-band antenna array for cellular base stations operating at a first frequency band and at a second frequency band within a first frequency range, and also at a third frequency band within a second frequency range. Said triple-band antenna array comprises a first set of radiating elements operating at the first frequency band, a second set of radiating elements operating at the second frequency band, a third set of radiating elements operating at both the third and the first frequency bands, and a fourth set of radiating elements operating at both the third and the second frequency bands.
High degree of freedom array
An array of elements suitable for adaptive processing in an extreme jammed environment comprised of a plurality of smaller sub-arrays of element clusters that have natural orthogonal spatial modes of excitation, wherein the improvement comprises sub-arrays with spatial orthogonality of feed modes, cross-sub-array combination to maximize pre-processing sub-array spacing and diversity of relative configuration, a high-input analog nuller used on the pre-processing sub-array therein, a high-input analog nuller is used to null a dominant jamming signal, possibly exceeding normal communication signal levels, so that the sub-array processed signals could then be fed to an antenna processor with simultaneous beam steering and null steering.. .
Devices and methods for measurement of magnetic characteristics of mram wafers using magnetoresistive test strips
Methods for testing magnetoresistance of test devices with layer stacks, such as mtjs, fabricated on a wafer are described. The test devices can be fabricated along with arrays of similarly structured memory cells on a production wafer to allow in-process testing.
Nanolens arrays in nanopillar optoelectronic devices
An optoelectronic device includes: (1) a top transparent electrode; (2) a bottom electrode spaced apart from the top transparent electrode; and (3) nanopillars arranged between the top transparent electrode and the bottom electrode such that each of the nanopillars includes a top end electrically connected to the top transparent electrode and a bottom end electrically connected to the bottom electrode. The top transparent electrode is shaped to provide optical elements each arranged to couple light into or out of a respective one of the nanopillars..
Memory arrays and methods of forming the same
Memory arrays and methods of forming the same are provided. One example method of forming a memory array can include forming a conductive material in a number of vias and on a substrate structure, the conductive material to serve as a number of conductive lines of the array and coupling the number of conductive lines to the array circuitry..
Method and apparatus for orienting arrays of mechanically linked heliostats for focusing the incident sunlight on a stationary object
The present invention is a method and apparatus for periodic orientation of arrays of mechanically linked heliostats positioned on rotatable shafts such that incident sunlight is focused on a stationary object. In each altitudinal orientation a minuscule predefined push is given by an actuator and the time interval between each altitudinal orientation is 2×(t2−t1)/n.
System and method for multiplexed and buffered miniaturized sensor arrays
A miniature pressure scanning system includes a plurality of miniature pressure sensors where each pressure sensors includes at least one sensor output for providing an analog output signal indicative of a detected pressure on a body, and each pressure sensor output has an associated output impedance; a plurality of buffers, each buffer electrically connected to the output port of a corresponding one of the pressure sensors, and configured to reduce the associated output impedance of the corresponding sensor output coupled thereto, and further configured to provide at an output of the buffer the analog output pressure signal from the pressure sensor; and a multiplexer coupled downstream of the plurality of buffers and configured to multiplex the buffered analog output pressure signals to output a multiplexed analog signal representing the detected pressures.. .
Systems and methods for self-referenced detection and imaging of sample arrays
A system for detecting an array of samples having detectable samples and at least one reference sample is provided. The system comprises an electromagnetic radiation source, a sensing surface comprising a plurality of sample fields, wherein the plurality of sample fields comprise at least one reference field, a phase difference generator configured to introduce differences in pathlengths of one or more samples in the array of samples, and an imaging spectrometer configured to image one or more samples in the array of samples..
Methods of macromolecular analysis using nanochannel arrays
Methods of analyzing features such as the physical size of macromolecules or biomarkers along large genomic dna molecules were disclosed as wen as the devices for carrying out such high throughput analysis in a massively parallel fashion. Methods of fabricating such devices are also disclosed..
Sudoku arrays
Provided herein is technology relating to generating a sudoku array and particularly, but not exclusively, to methods and systems for generating a sudoku array for a puzzle or for encrypting data.. .
Vertical bit line non-volatile memory systems and methods of fabrication
Three-dimensional (3d) non-volatile memory arrays having a vertically-oriented thin film transistor (tft) select device and methods of fabricating such a memory are described. The vertically-oriented tft may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line.
Drug delivery by carbon nanotube arrays
The invention generally relates to carbon nanotube based drug delivery methods, devices, and compositions. More particularly, the invention relates to controlled drug delivery using anchored carbon nanotube arrays..
Image guided radiotherapy with dual source and dual detector arrays tetrahedron beam computed tomography
A radiation treatment and imaging system for emitting a radiation treatment beam and x-ray imaging beams towards an object. The system includes an x-ray source and a collimator, first and second detectors, and a linear accelerator that delivers radiation beams to an object.
Effective prediction using partition coding
The way of predicting a current block by assigning constant partition values to the partitions of a bi-partitioning of a block is quite effective, especially in case of coding sample arrays such as depth/disparity maps where the content of these sample arrays is mostly composed of plateaus or simple connected regions of similar value separated from each other by steep edges. The transmission of such constant partition values would, however, still need a considerable amount of side information which should be avoided.
High-power, phase-locked, laser arrays
High-power, phased-locked, laser arrays as disclosed herein utilize a system of optical elements that may be external to the laser oscillator array. Such an external optical system may achieve mutually coherent operation of all the emitters in a laser array, and coherent combination of the output of all the lasers in the array into a single beam.
Vcsel pumped fiber optic gain systems
Optical pump modules comprising vcsel and vcsel array devices provide high optical power for configuring fiber optic gain systems such as fiber laser and fiber amplifier particularly suited for high power operation. Pump modules may be constructed using two reflector or three reflector vcsel devices optionally integrated with microlens arrays and other optical components, to couple high power pump beams to a fiber output port.
Semiconductor storage device and testing method
A plurality of writing circuits respectively writes data to a plurality of memory cell arrays and a redundant cell array. A holding circuit, which is arranged for each memory cell array, holds data input as a storage target.
Multi-die memory device
A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays.
Sunlight redirecting mirror arrays
Sunlight redirector (30) incorporates closely proximate mirror arrays (32, 34) having parallel, uniformly spaced, longitudinal mirror segments (38, 44). Prismatic sheet (36) is positioned behind and closely proximate second array (34).
Image sensor pixels with self-aligned lateral anti-blooming structures
Pixels for solid-state cmos image sensor arrays may be provided that have a lateral blooming control structure incorporated in them. The lateral blooming control structure is built as a separate structure from the charge transfer gate and it is fabricated in a self-aligned manner, which is particularly suitable for incorporating into small size pixels.
Gnss antennas
A global navigation satellite system (gnss) antenna system includes interference mitigation and multipath canceling. Multiple ports or phased arrays of antennas can be provided.
Data conversion with redundant split-capacitor arrangement
Representative implementations of devices and techniques provide analog to digital conversion of time-discrete analog inputs. A redundant split-capacitor arrangement using a successive approximation technique can provide a fast and power efficient adc.
Hydromotive machine
Hydromotive machines, e.g. Hydroturbines and pumps with integral low head loss shut off valves are described.
Field effect transistor devices
A memcapacitor device includes a pair of opposing conductive electrodes. A semiconductive material including mobile dopants within a dielectric and a mobile dopant barrier dielectric material are received between the pair of opposing conductive electrodes.
Arrays of nonvolatile memory cells and methods of forming arrays of nonvolatile memory cells
An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first plurality of horizontally oriented first electrode lines and a second plurality of horizontally oriented second electrode lines crossing relative to the first electrode lines.
Apparatus for the passage and conveyance of compressible material
An apparatus (10) for the passage and conveyance of compressible material, the apparatus (10) comprising at least two arrays (14) of substantially parallel first screw conveyors (16) each arranged at an outlet (56) of a vessel (12) from which the material is to be conveyed such that the material is conveyed to respective second screw conveyors (18) arranged in generally transverse relation thereto, wherein the material to be conveyed bears directly on the first screw conveyors (16) from above and does not bear directly on the second screw conveyors (18). A method for the passage and conveyance of compressible material is also described..
System and method for resource sharing across multi-cloud arrays
A system for resource sharing across multi-cloud storage arrays includes a plurality of storage arrays and a cloud array storage (cas) application. The plurality of storage resources are distributed in one or more cloud storage arrays, and each storage resource comprises a unique object identifier that identifies location and structure of the corresponding storage resource at a given point-in-time.
Cross-point resistive-based memory architecture
A plurality of addressable memory tiles each comprise one or more cross-point arrays. Each array comprises a plurality of non-volatile resistance-change memory cells.
Delivery system for hollow microneedle arrays
The present disclosure relates to systems and methods for delivering microneedles to a patient's skin. In one aspect, the present disclosure provides a system for delivering a microneedle array to a patient's skin surface, the system comprising: a delivery apparatus including a housing; and an infusion device detachably received in the housing..
Excitation schemes for low-cost transducer arrays
A device images time-wise in parallel using transducer elements of a group (428, 432, 436, 440). In some embodiments, the elements are of a current group and imaging is time-wise sequential by group.
Device and method for cell-exclusion patterning
This disclosure relates to devices and methods for cell-exclusion patterning. Specifically, this disclosure provides a device and method to exclude cells in selected areas during cell seeding and create cell-free arrays that can be used for cell migration and related studies and assays..
Ultra-sensitive detection of molecules on single molecule arrays
The present invention relates to systems and methods for detecting analyte molecules or particles in a fluid sample and in some cases, determining a measure of the concentration of the molecules or particles in the fluid sample. Methods of the present invention may comprise immobilizing a plurality of analyte molecules or particles to form a plurality of complexes, releasing at least a portion of some of the plurality of complexes, determining at least a portion of the plurality of complexes released, and determining a measure of the concentration of the analyte molecules or particles in a fluid sample..
Method for identifying cells based on dna replication domain timing profiles
Methods for identifying and/or distinguishing a homogeneous population of cells based on their replication domain timing profile using high resolution genomic arrays or sequencing procedures are provided. These methods may be used to compare the replication timing profile for a population of cells to another replication timing profile(s), a replication timing fingerprint, and/or one or more informative segments of a replication timing fingerprint, which may be simultaneously or previously determined and/or contained in a database, to determine whether there is a match between them.
Multi-array antenna
In one example, the present disclosure describes an antenna system with at least two linear antenna arrays, each having a plurality of antenna elements. Each array is designed to transmit and receive signals from different respective spectrum bands.
Method and apparatus for calibrating multiple antenna arrays
A method includes transmitting a calibration command to multiple antenna arrays. Each antenna array includes a plurality of antenna elements, a plurality of transmitter and receiver channels, and a calibration circuit comprising a calibration receiver and a calibration transmitter.
Positive tone organic solvent developed chemically amplified resist
Provided is a method for developing positive-tone chemically amplified resists with an organic developer solvent having at least one polyhydric alcohol, such as ethylene glycol and/or glycerol, alone or in combination with an additional organic solvent, such as isopropyl alcohol, and/or water. The organic solvent developed positive tone resists described herein are useful for lithography pattern forming processes; for producing semiconductor devices, such as integrated circuits (ic); and for applications where basic solvents are not suitable, such as the fabrication of chips patterned with arrays of biomolecules or deprotection applications that do not require the presence of acid moieties..
System and method for preventing cavitation in controlled-frequency marine seismic source arrays
There is provided herein a method of seismic acquisition that utilizes an arrangement of marine sources where each source is positioned at a water depth shallow enough for the surface ghost notch to fall at a frequency greater than or equal to the maximum radiated frequency of interest. If the marine seismic source has a ratio of signal bandwidth to maximum frequency that is less than one half, then it is possible to deploy it at a greater depth at which ghost notches fall below and above its frequency band but not in it.
Semiconductor memory and memory system including the semiconductor memory
A memory system is provided which includes multiple semiconductor memories having arrays of memory cells and a memory controller configured to provide an address in common to the multiple memories. First and second addresses corresponding to first and second rows of memory cells in first and second memories are selected according to the address in common.
Memory device and memory system including the same
A memory device may be provided which includes a memory cell array including a plurality of sub arrays each sub array having a plurality of memory cells connected to bit lines; an address buffer configured to receive a row address and a column address; and a column decoder configured to receive the column address from the address buffer and, for each of the sub arrays, to select a column selection line corresponding to the column address, from among a plurality of column selection lines, based on different offset values applied to the sub arrays, respectively. The selected column selection lines correspond to bit lines having different physical locations, respectively, according to the different offset values..
Memory system
A memory system according to the embodiment comprises a cell array of unit cell arrays each including memory cells; and an access circuit, wherein the memory cell changes from a first resistance state to a second resistance state on application of a first polarity voltage, and changes from the second resistance state to the first resistance state on application of a second polarity voltage, the access circuit provides the first and second lines connected to an access-targeted memory cell with access potentials, and brings at least one of the first and second lines connected to an access-untargeted memory cell into a floating state to make access to the access-targeted memory cell, the unit cell array includes first spare lines to provide redundancy for the first lines, and an alignment of the first lines includes a certain number of the first spare lines arranged in a certain cycle.. .
Memory elements and cross point switches and arrays for same using nonvolatile nanotube blocks
Under one aspect, a covered nanotube switch includes: (a) a nanotube element including an unaligned plurality of nanotubes, the nanotube element having a top surface, a bottom surface, and side surfaces; (b) first and second terminals in contact with the nanotube element, wherein the first terminal is disposed on and substantially covers the entire top surface of the nanotube element, and wherein the second terminal contacts at least a portion of the bottom surface of the nanotube element; and (c) control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube element can switch between a plurality of electronic states in response to a corresponding plurality of electrical stimuli applied by the control circuitry to the first and second terminals.
Natural light interferometer
Disclosed is a natural light interferometer. The interferometer measures the amplitude and phase distribution of a coherent or incoherent electromagnetic signal, including natural light.
Full-frame, programmable hyperspectral imager
A programmable, many-band spectral imager based on addressable spatial light modulators (aslms), such as micro-mirror-, micro-shutter- or liquid-crystal arrays, is described. Capable of collecting at once, without scanning, a complete two-dimensional spatial image with aslm spectral processing applied simultaneously to the entire image, the invention employs optical assemblies wherein light from all image points is forced to impinge at the same angle onto the dispersing element, eliminating interplay between spatial position and wavelength.
Cartridge, liquid supply system, and liquid ejection apparatus
A cartridge configured to be mounted to a liquid ejection apparatus that has an electrical connection portion and an engagement portion, and having an engaging portion for engaging the engagement portion and a plurality of electrodes for connecting to the connection portion. The electrodes have contact portions for contacting the connection portion, with a first group of a plurality of the contact portions constituting a first array whose contact portions are aligned in an x-axis direction intersecting a mounting direction of the cartridge, and a second group of the plurality of the contact portions constituting a second array whose contact portions are aligned in the x-axis direction.
Open end antenna, antenna array, and related system and method
A system includes an antenna array and a transceiver configured to communicate wirelessly via the antenna array. The antenna array includes a substrate having first and second ground plates.
Apparatus and method for locating, tracking, controlling and recognizing tagged objects using active rfid technology
A real-time automated data security system protects both data and devices from loss, theft, and unauthorized access or activity. A miniature active rfid circuit is embodied in tags, area tags, controllers, usb sticks and a universal interface software for computers (i.e., java), smart phones, and gateway boxes written to interface with the system.
Test apparatus having a probe card and connector mechanism
A test apparatus for testing a semiconductor device includes a circuit board having a contact pattern on one side and an opening therethrough, and a probe card supporting a probe needle array. The probe needle array is insertable into the opening of the circuit board and is configured to probe a device under test.
Maximizing power output of solar panel arrays
A system for generating electric power includes a first dc source, a second dc source and a shared optimizer. The first dc source provides a first voltage across a first node and a second node, while the second dc source provides a second voltage across the second node and a third node.
Method and apparatus for fluting a web in the machine direction
A forming device for gathering the width of a traveling web is disclosed. The forming device includes opposing arrays of flute-forming bars that can be interlaced to define therebetween a longitudinal flute-forming labyrinth effective to reduce the width of a web traveling therethrough by a preselected take-up ratio.
Semiconductor chip and semiconductor device
Provided is a semiconductor chip that is flip-chip mounted where an inner chip pad array and an outer chip pad array, which are arranged on an inner side and an outer side of io cells in a staggered manner, are arranged to be spaced away from each other by a predetermined gap or greater. The predetermined gap represents a gap where one via can be arranged between an inner substrate pad array and an outer substrate pad array on a substrate which faces and is connected to the inner chip pad array and the outer chip pad array.
Device and method for localized force sensing
A device and method for operating a capacitive input device configured to sense input objects and their applied force in a sensing region, the device including a pliable component having an input surface and characterized by a bending stiffness, and first and second arrays of sensor electrodes. The input device further includes a third array of sensor electrodes and a spacing layer disposed between the third array.
Load balancer for parallel processors
Invented systems and methods provide a scalable architecture and hardware logic algorithms for intelligent, realtime load balancing of incoming processing work load among instances of a number of application programs hosted on parallel arrays of manycore processors, which can be dynamically shared among the hosted applications according to incoming processing data load variations for each of the application instances as well as the processing capacity entitlements of the individual applications.. .
Masking power usage of co-processors on field-programmable gate arrays
Technologies are generally described for masking power usage of co-processors on field-programmable gate arrays. In some examples, one or more moat brick circuits may be implemented around a co-processor loaded on a held-programmable gate array (fpga).
Decentralized input/output resource management
A shared input/output (io) resource is managed in a decentralized manner. Each of multiple hosts having io access to the shared resource, computes an average latency value that is normalized with respect to average io request sizes, and stores the computed normalized latency value for later use.

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