|| List of recent Arithmetic-related patents
| Data integrated analysis system|
A generation technique and an analysis technique of a large number of explanatory variables to derive effective measures by using various data are provided. Specifically, a factor which lurks in a large amount of data and affects business performance is identified by automatically generating a large number of explanatory variables and performing correlation analysis between the explanatory variables and an objective variable.
| Ceramic assembled board, method of manufacturing the same, ceramic substrate and ceramic circuit substrate|
A ceramic assembled board is formed by cutting continuous dividing grooves on one or both of the surfaces of a sintered ceramic board by way of laser machining to produce a large number of circuit substrates and at least one of the continuous grooves has a largest depth section and a smallest depth section with a depth difference Δd of 10 μm≦Δd≦50 μm. A ceramic substrate is produced by dividing the ceramic assembled board and at least one of its lateral surfaces is a surface formed by dividing the ceramic assembled board along the continuous grooves, the arithmetic mean roughness ra2 of the machined surfaces of the continuous grooves being smaller than the arithmetic mean roughness ra1 of the surfaces of broken sections with regard to the arithmetic mean roughness ra of the lateral surfaces..
| Optical module used in optical communication systems, method of updating firmware of optical module used in optical communication systems, and trouble tracing system|
An optical module includes: an optical device driven by a driving voltage; an arithmetic processing chip including an arithmetic processing circuit that operates according to predetermined firmware and generates an electrical control signal indicating a magnitude of the driving voltage; a voltage generating unit provided outside the arithmetic processing chip, and including an input terminal that receives the control signal from the arithmetic processing chip and an output terminal that provides the driving voltage of a magnitude corresponding to the control signal to the optical device; and a voltage holding unit that holds an output voltage from the output terminal of the voltage generating unit at a constant voltage regardless of an operation state of the arithmetic processing circuit, when the firmware is updated.. .
| Method for coding video quantization parameter and method for decoding video quantization parameter|
A video quantization parameter encoder includes: a prediction unit 11 for generating a predicted quantization parameter from a past reconstructed quantization parameter; a computing unit 12 for generating a delta quantization parameter from a quantization parameter and the predicted quantization parameter; and quantization parameter encoding means 13 for binary arithmetic encoding a first bin indicating whether or not the delta quantization parameter is significant, a second bin indicating whether the delta quantization parameter is positive or negative, and other bins indicating an absolute value of the delta quantization parameter, in the case where the delta quantization parameter is significant.. .
| Low power context adaptive binary arithmetic decoder engine|
A technique for decoding data within a context-based adaptive binary arithmetic coding (cabac) stream processes one or more bins of compressed data based on video format parameters associated with the stream. A configurable cabac decoder circuit cascades one or more instances of cabac bin decoder logic to operate properly within a timing constrain established by a decoder clock frequency.
| Packet processors and packet filter processes, circuits, devices, and systems|
A packet filter (2500) for incoming communications packets includes extractor circuitry (2510) operable to extract data from a packet, and packet processor circuitry (2520) operable to concurrently mask (3010) the packet data from the extractor circuitry (2510), perform an arithmetic/logic operation (3020) on the packet to supply a packet drop signal (drop), and perform a conditional limit operation and a conditional jump operation (3030).. .
| Method for calculating spacing ratio of interferometer array antenna for direction finder|
A method for calculating a spacing between antenna elements of an interferometer array antenna includes setting an azimuth of an instantaneous field of view and a distance between phase differences, and obtaining the number of phase difference lines and phase difference vectors with respect to the phase differences of the signals output in a phase comparator of a direction finder, performing a modular arithmetic for the phase difference vectors to obtain phase difference matrixes, obtaining a transformation matrix for linearly transforming the phase difference matrixes and performing the linear transformation using the transformation matrix, calculating a distance between the phase differences on a new axis generated by the linear transformation, and calculating an antenna spacing as an array spacing of the array antenna, the antenna spacing meeting that the distance between the phase differences is greater than a desired distance between phase differences.. .
| Current sensor|
A current sensor of the present invention includes a mounting unit including a disposition region in which a current path is disposed, a pair of magnetic detection elements disposed in the mounting unit so as to sandwich therebetween the disposition region, and an arithmetic circuit performing an arithmetic operation on the current value of the current path on the basis of the detection values of the pair of magnetic detection elements. The pair of magnetic detection elements is disposed on sides opposite to each other with respect to a virtual line passing through the gravity center of the current path in cross-sectional view of the current path, and individually has sensitivity axes parallel to a direction perpendicular to the direction of a current conducted through the current path and the direction of the virtual line..
| Solar cell element and method for manufacturing same|
A solar cell element having a transparent substrate body, a naxag1-x, layer, a zno layer, a transparent conductive layer, and a photoelectric conversion layer including an n-type semiconductor layer and a p-type semiconductor layer. The transparent substrate body, the naxag1-x layer, the zno layer, the transparent conductive layer, and the photoelectric conversion layer are stacked in this order, x represents a value of not less than 0.001 and not more than 0.02, the naxag1-x layer has a thickness of 2-15.2 nanometers, and the zno layer has an arithmetical mean roughness of not less than 20-750 nanometers.
|Arithmetic operation in a data processing system|
An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively.
|Golf swing analyzing apparatus and method of analyzing golf swing|
An aspect of the invention relates to a golf swing analyzing apparatus, comprising: an arithmetic section operating to use the output of an inertial sensor to calculate bending moment acting on the golf club, the inertial sensor being attached to the golf club.. .
|Golf swing analyzing apparatus and method of analyzing golf swing|
An aspect of the invention relates to a golf swing analyzing apparatus, comprising: an arithmetic section operating to process the output of a first inertial sensor and the output of a second inertial sensor to calculate a relative angle between a forearm of a golfer and a golf club, the first inertial sensor being attached to a portion of the upper body of the golfer, the second inertial sensor being attached to the golf club.. .
|Golf swing analyzing apparatus and method of analyzing golf swing|
An aspect of the invention relates to a golf swing analyzing apparatus, comprising: a first arithmetic section operating to use an output from a first inertial sensor and an output from a second inertial sensor to calculate a first energy amount, the first inertial sensor being attached to a portion of an upper body of a golfer, the second inertial sensor being attached to a golf club, the first energy amount being generated in the upper body of the golfer; a second arithmetic section operating to use the output from the first inertial sensor and the output from the second inertial sensor to calculate a second energy amount transferred to the golf club from the upper body of the golfer; and a processing section calculating an energy transferring ratio of an energy transferred from the upper body of the golfer to the golf club based on a ratio of the second energy amount to the first energy amount.. .
|Size measurement apparatus and size measurement method|
A size measurement apparatus includes: a first light emitter unit for widely emitting light to an imaging area which may include an object; a second light emitter unit for locally emitting light to a part of the imaging area; an image taking unit for obtaining a range image which contains distance information on a pixel-by-pixel basis, with pixels being arranged two-dimensionally, the distance information being calculated based on a measured time value which is a time for the light emitted from the light emitter units to travel back as a reflected light; and an arithmetic control unit for controlling light emission from the light emitter units, and for calculating size information of the object based on a synthesized range image obtained by synthesizing a range image obtained during light emission from the first light emitter unit and a range image obtained during light emission from the second light emitter unit.. .
|Device and method for measurement of ultrasonic transit times|
A device for measurement of ultrasonic wave transit times of an ultrasonic flow sensor consists of: 1) a synchronization signal generator, 2) a reference pulse generator, 3) a sine wave generator, 4) an analog signal amplifier, 5) a comparator, 6) a plurality of latch circuits, 7) a digital adder, 8) an integrator, 9) an a/d converter, 10) a master counter, 11) a plurality of edge counters, and 12) an arithmetic circuit. The device measures the ultrasonic wave transit times using a method of averaging the ultrasonic wave arriving times at different measuring points (triggering point).
|Electronic device including mind-map user interface and method for manipulating mind-map using the same|
An electronic device includes a display, at least one processor, a memory, and a mind-map user interface stored in the memory, executed by the processor, and configured to create or edit a plurality of topic objects which are formed of user-entered input data and connected to each other in a hierarchical tree structure. The processor is configured to display on the display the plurality of topic objects distributed in the hierarchical tree structure when the mind-map user interface is executed.
|Variable clocked serial array processor|
A serial array processor may have an execution unit, which is comprised of a multiplicity of single bit arithmetic logic units (alus), and which may perform parallel operations on a subset of all the words in memory by serially accessing and processing them, one bit at a time, while an instruction unit of the processor is pre-fetching the next instruction, a word at a time, in a manner orthogonal to the execution unit.. .
|Hardening of direct anonymous attestation from side-channel attack|
Various embodiments are generally directed to hardening the performance of calculations of a digital signature system for authenticating computing devices against side-channel attacks. An apparatus comprises a processor circuit and an interface operative to communicatively couple the processor circuit to a network; a storage communicatively coupled to the processor circuit and arranged to store instructions operative on the processor circuit to digitally sign a message to create a first signature using a modular arithmetic operation arranged to compensate for a value of a variable greater than a modulus without use of a branching instruction; and transmit the first signature to a verifying server via the network.
|Information processing device, method for controlling information processing device|
An information processing device includes a plurality of arithmetic processing devices, a plurality of storage devices, a connection section that connects a first arithmetic processing device to a first storage device and a second storage device which are duplexed and a control section that causes, when the performance of the second storage device is reduced, the connection section to cut out the second storage device whose performance has been reduced from the first arithmetic processing device and the first storage device, causes to duplex a third storage device with the first storage device, causes the connection section to connect the first storage device and the third storage device which have been duplexed to the first arithmetic processing device and to connect a second arithmetic processing device to the second storage device that has been cut out, and causes the second arithmetic processing device to initialize the second storage device.. .
|Processing with compact arithmetic processing element|
A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“lphdr arithmetic”). Such a processor or other device may, for example, be implemented on a single chip.
|Twin clutch controlling apparatus|
A twin clutch controlling apparatus wherein an interposition of a manual operation into an automatic control clutch can be executed smoothly. The twin clutch controlling apparatus includes an amt controlling unit for controlling a shift actuator and a clutch actuator, and a shift pedal p for carrying out a shifting request to the amt controlling unit.
|Twin clutch controlling apparatus|
A twin clutch controlling apparatus wherein a clutch lever is operated during a deceleration operation in which an auto mode (auto) is selected, then a shift down action from a gear position “n-2” at which a driving force can be transmitted only by one of an odd number stage side clutch cl1 and an even number stage side clutch cl2 to another position “1-2” at which the transmission gear for transmitting a driving force is switched in response to switching control of the clutch is carried out in response to the operation of the clutch lever. After the shift down action, if re-connection of the clutch is to be carried out by the clutch lever, then the clutch (cl1, cl2) on the side to be driven in response to a manual operation clutch capacity arithmetic operation value (tqcltmt) is determined in response to a vehicle speed v..
|Twin clutch controlling apparatus|
A twin clutch controlling apparatus including a shift motor for carrying out a smooth changeover of a shift stage of a multi-speed transmission having a plurality of gear trains between a main shaft and a countershaft, a twin clutch configured from an odd number stage side clutch and an even number stage side clutch, a clutch actuator for controlling the twin clutch, and a manual operation clutch capacity arithmetic operation section for arithmetically operating, based on an operational amount of a clutch lever, a manual operation clutch capacity arithmetic operation value (tqc1tmt) corresponding to the manual operation. The twin clutch controlling apparatus further includes a manual operation clutch decision section for determining with a clutch capacity of which one of the odd number stage side clutch or the even number stage side clutch the manual operation clutch capacity arithmetic operation value (tqc1tmt) is to be interlocked..
|Twin clutch controlling apparatus|
A twin clutch controlling apparatus includes a clutch actuator for controlling a twin clutch tcl, and a manual operation clutch capacity arithmetic operation section for converting an operation amount of a clutch lever l into an electric signal to arithmetically operate a manual operation clutch capacity arithmetic operation value (tqc1tmt) corresponding to the manual operation. The twin clutch controlling apparatus is configured so as to accept a changeover from an auto mode to a temp mode in response to an operation of the clutch lever l.
|Twin clutch controlling apparatus|
A twin clutch controlling apparatus includes an atm control unit for controlling a shift actuator and a clutch actuator and a shift pedal p for carrying out shifting request to the atm control unit. When a shifting request by the shift pedal p is issued, the atm control unit drives the shift actuator to change over the shift stage to a next stage gear irrespective of an operational amount of a clutch lever l and then causes the manual operation clutch capacity arithmetic operation value (tqcltmt) to correspond to a clutch capacity corresponding to the next stage gear using an operational amount of the clutch lever l that exceeds a predetermined value as a trigger.
|Substrate, method for producing same, heat-releasing substrate, and heat-releasing module|
The invention provides a substrate, including: a metal foil; a polyimide resin layer having an average thickness of from 3 μm to 25 μm, the polyimide resin layer being disposed on a surface of the metal foil having an arithmetic average roughness (ra) of 0.3 μm or less and a maximum roughness (rmax) of 2.0 μm or less; and an adhesive layer having an average thickness of from 5 μm to 25 μm, the adhesive layer being disposed on the polyimide resin layer.. .
|Controlling power supply in arithmetic processing circuit|
An arithmetic processing circuit includes a plurality of arithmetic processing units, a plurality of selector circuits each configured to select one of a plurality of power supplies that are fewer than the arithmetic processing units and to connect the selected power supply to a corresponding one of the arithmetic processing units, and a power supply control circuit configured to variably control an output voltage of at least one of the plurality of power supplies.. .
|Information processing apparatus and instruction offloading method|
In general, according to one embodiment, an information processing apparatus includes an issuer and a communicator. The issuer issues an offload instruction corresponding to a first process executed in company with a first identifier capable of uniquely specifying a resource of a first arithmetic operation device.
|Memory location determining device, memory location determining method, data structure, memory, access device, and memory access method|
A memory location determining device determines memory locations for storing m pieces of compressed data each of which is compressed from one of m pieces of n-bit data. For each piece of compressed data, the memory location determining device performs a first arithmetic operation on an address value of a corresponding piece of n-bit data, and determines to store x bits of the piece of compressed data and a flag indicating whether or not the piece of compressed data exceeds x bits at a location indicated by the result value of the first arithmetic operation.
|Arithmetic processing unit, information processing device, and arithmetic processing unit control method|
An l2 cache control unit searches for a cache memory according to a memory access request which is provided from a request storage unit 0 through a cpu core unit, and retains in request storage units 1 and 2 the memory access request that has a cache mistake that has occurred. A bank abort generation unit counts, for each bank, the number of memory access requests to the main storage device, and instructs the l2 cache control unit to interrupt access when any of the number of counted memory access requests exceeds a specified value.
|Device with capability of processing fft radix 2 butterfly operation and operation method thereof|
The disclosure provides a device with a capability of processing a fast fourier transform algorithm (fft) radix 2 butterfly operation and an operation method thereof, the device at least includes a latch, a complex multiplier, a complex adder-subtractor, a switch and a complex conjugate arithmetic logical unit (alu). The complex operation unit of the disclosure has a simple structure.
|Arithmetic processing apparatus and an arithmetic processing method|
A first normalization circuit (120) performs a first normalization, in which a plurality pieces of data, which have a common exponent and which are either fixed-point number representation data or mantissa portion data of block floating-point number representation, are inputted in each of a plurality of cycles and the plurality of pieces of data inputted in each of the plurality of cycles are respectively normalized with the common exponent on the basis of a maximum exponent for the plurality of pieces of data inputted in a corresponding one of the plurality of cycle. A rounding circuit (130) outputs a plurality of pieces of rounded data which are obtained by reducing a bit width of respective one of the plurality of pieces of data on which the first normalization is performed.
|Injection device, molding machine, and method for controlling injection device|
An injection device is provided with a stationary-side frame supporting a barrel, a movable-side frame rotatably supporting a screw, a pair of ball screws, and injection drive mechanisms includes servomotors configured to rotate the ball screws. A force detector such as a load cell and the like is disposed between the first ball screw and the movable-side frame.
|Controller support device, controller support program to be executed in said device, and recording medium storing said program|
A controller support program causes an arithmetic unit to execute total execution time acquisition processing of acquiring a total execution time and output processing of outputting the total execution time. The total execution time is an elapsed time until execution of a control program is ended in an execution cycle since the execution cycle is started when a controller executes the control program according to an execution priority and the execution cycle, and the total execution time is also a time measured in the controller or a time estimated in a controller support device..
Resin compositions which contain an epoxy resin, an alkoxy oligomer, and an inorganic filler provide insulating layers that have a surface with not only low arithmetic mean roughness but also low root mean square roughness in a wet roughening step and that are capable of forming thereon a plated conductive layer having a sufficient peel strength that can be formed while maintaining the glass transition temperature and thermal expansion coefficient.. .
|3d vision processing|
Methods and apparatuses are described for processing 3d vision algorithms. A 3d vision processor device comprises one or more 3d vision processing cores.
|Image coding method, image coding apparatus, image decoding method and image decoding apparatus|
An image coding method including: binarizing last position information to generate (i) a binary signal which includes a first signal having a length smaller than or equal to a predetermined maximum length and does not include a second signal or (ii) a binary signal which includes the first signal having the predetermined maximum length and the second signal; first coding for arithmetically coding each of binary symbols included in the first signal using a context switched among a plurality of contexts according to a bit position of the binary symbol; and second coding for arithmetically coding the second signal using a fixed probability when the binary signal includes the second signal, wherein in the first coding, a binary symbol at a last bit position of the first signal is arithmetically coded using a context exclusive to the last bit position, when the first signal has the predetermined maximum length.. .
|Context derivation for context-adaptive, multi-level significance coding|
A device for coding video data includes a video coder configured to code first significance information for transform coefficients associated with residual data, wherein the first significance information indicates if a first sub-block comprises at least one non-zero coefficient, wherein the first sub-block is a sub-block of an entire transform block; and, code second significance information, wherein the second significance information indicates if a second sub-block comprises at least one non-zero coefficient, wherein the second sub-block is a sub-block of the first sub-block, wherein coding the second significance information comprises performing an arithmetic coding operation on the second significance information, wherein a context for the arithmetic coding operation is determined based on one or more neighboring sub-blocks of a same size as the first sub-block.. .
|Conductive substrate and touch panel comprising same|
The invention relates to a conducting substrate and a touch panel comprising the same. A conducting substrate according to one embodiment of the invention comprises at least one base material and at least one conductive pattern on the base material, wherein the arithmetic average roughness height (ra) of the surface of the conductive pattern is 0.1-0.3 μm.
|Efficient and scalable cyclic redundancy check circuit using galois-field arithmetic|
Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using galois-field arithmetic.. .
|Semiconductor integrated circuit and compiler|
A semiconductor integrated circuit includes: a floating point arithmetic unit that includes circuit resources over which power saving control is performed, and executes a floating point arithmetic operation; a power-control instruction control unit that receives a pre-access instruction corresponding to a floating point arithmetic operation instruction, and invalidates stepwise the power saving control over the circuit resources included in the floating point arithmetic unit to operate a part of the circuit resources in the floating point arithmetic unit; and a control unit that causes the floating point arithmetic unit to execute the floating point arithmetic operation, wherein before execution of the floating point arithmetic operation in the floating point arithmetic unit, power consumption is previously increased by the pre-access instruction.. .
|Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry|
Digital signal processing (“dsp”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) dsp operations if desired. These dsp blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect).
|Distribution analysis device|
A distribution analysis device analyzes a distribution of a field having a property satisfying the laplace equation, and includes: an obtainment unit that obtains measurement data indicating the distribution of the field measured through a sensor sensing area, the sensor sensing area being an area that moves in a measurement area where the distribution of the field is measured and being an area in which the field is sensed as an aggregate; and a calculation unit that calculates analysis data indicating the distribution of the field with a higher resolution than the measurement data, using an arithmetic expression that is obtained by deriving a solution of the laplace equation using a boundary condition that an integral of the solution of the laplace equation in a finite interval corresponding to a size of the sensor sensing area matches the measurement data.. .
|Multilayer resin sheet, resin sheet laminate, cured multilayer resin sheet and method for producing same, multilayer resin sheet with metal foil, and semiconductor device|
The invention provides a multilayer resin sheet that includes: a resin composition layer that includes a thermosetting resin and a filler; and an adhesive layer that is disposed on at least one surface of the resin composition layer, the adhesive layer having an arithmetic average surface roughness ra of 1.5 μm or less at a surface that does not face the resin composition layer.. .
|Simplifiication of pic_order_cnt_lsb calculation in hm8|
The specification and calculation of picordercntmsb in wd8 is simplified without changing the semantics in wd8. Four arithmetic-logic operations are removed, and the implicit assumption that the subtraction in the calculation is based on unsigned integer arithmetic in hm8 is removed.
|Wet paper web transfer belt, papermaking system and papermaking method|
A wet paper web transfer belt for transferring a wet paper web includes a wet paper web contacting surface for carrying the wet paper web. The wet paper web contacting surface is constituted by a resin layer.
|Thermal flow sensor and method of generating flow rate detection signal by the thermal flow sensor|
Provided is a thermal flow sensor capable of obtaining a flow rate detection signal that differs depending on a flow direction of a fluid, with a simple configuration and at low cost. The thermal flow sensor includes: a bridge circuit (1) for outputting a flow rate detection signal (vm); a fluid direction detection circuit (2) for outputting a fluid direction detection signal (vd); and an arithmetic circuit (3, 4, 6) configured to: generate a first output signal (vqf) and a second output signal (vqr) based on the flow rate detection signal (vm) and the fluid direction detection signal (vd); and select the first output signal (vqf) when the fluid direction detection signal (vd) shows normal flow and select the second output signal (vqr) when the fluid direction detection signal (vd) shows reverse flow, to thereby output a flow rate detection signal (vout)..
|Galois field arithmatic operation circuit and memory device|
A galois field arithmetic operation circuit substituting (2̂m−1) elements (m is an integer) expressed by m bits of galois field gf(2̂m) includes: a base calculation unit configured to calculate m linear independent elements out of the (2am−1) elements; and a linear development unit configured to calculate the remaining (2̂m−1−m) elements not included in the m linear independent elements by combination of the m linear independent elements respectively. The galois field arithmetic operation circuit may be included in a memory device or other system..
|Multithreaded processor architecture with operational latency hiding|
A method and processor architecture for achieving a high level of concurrency and latency hiding in an “infinite-thread processor architecture” with a limited number of hardware threads is disclosed. A preferred embodiment defines “fork” and “join” instructions for spawning new context-switched threads.
|Number representation and memory system for arithmetic|
A method, device and system for representing numbers in a computer including storing a floating-point number m in a computer memory; representing the floating-point number m as an interval with lower and upper bounds a and b when it is accessed by using at least two floating-point numbers in the memory; and then representing m as an interval with lower and upper bounds a and b when it is used in a calculation by using at least three floating-point numbers in the memory. Calculations are performed using the interval and when the data is written back to the memory it may be stored as an interval if the size of the interval is significant, i.e.
|Architecture guided optimal system precision definition algorithm for custom integrated circuit|
Systems and methods are disclosed to automatically determine an optimal number format representation for a model or code to be implemented in a custom integrated circuit (ic) by determining a ratio of dynamic range to static range in the model or code, and selecting a floating point or a fixed point number representation based on the ratio; determining the optimal number representation format based on a cost function that includes hardware area and power cost associated with a predetermined bit precision arithmetic; automatically generating a processor architecture customized to the optimal number representation format; and synthesizing the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.. .
|Carrier for developing an electrostatic latent image, developer and image forming apparatus|
A carrier for developing an electrostatic latent image of the present invention includes a core material and a coating layer which coats the core material, wherein the coating layer includes a resin and fine particles, wherein the coating layer has an average layer thickness difference of 0.02 μm to 3.0 μm, and wherein the carrier for developing an electrostatic latent image has an arithmetic mean surface roughness ra1 of 0.5 μm to 0.9 μm.. .
|Constant-temperature piezoelectric oscillator and method of manufacturing the same|
A constant-temperature piezoelectric oscillator includes: a piezoelectric vibrator; an oscillation circuit; a frequency voltage control circuit; a temperature control section; and an arithmetic circuit, wherein the temperature control section includes a temperature-sensitive element, a heating element, and a temperature control circuit, the frequency voltage control circuit includes a voltage-controlled capacitance circuit capable of varying the capacitance value in accordance with the voltage, and a compensation voltage generation circuit, and the arithmetic circuit makes the compensation voltage generation circuit generate a voltage for compensating a frequency deviation due to a temperature difference between zero temperature coefficient temperature tp of the piezoelectric vibrator and setting temperature tov of the temperature control section based on a frequency-temperature characteristic compensation amount approximate formula adapted to compensate the frequency deviation, and then applies the voltage to the voltage-controlled capacitance circuit to compensate the frequency.. .
|Optical sensor device|
An optical sensor device includes a light emitter for emitting, to a living body, lights having two wavelengths and blinking at a predetermined frequency, and a light receiver for receiving the lights from the living body. The light receiver outputs first and second detection signals corresponding to the respective wavelengths.
|Apparatus and method for checking decoded data, apparatus and method for decoding, and receiving terminal|
The present disclosure provides an apparatus and a method for checking decoded data, an apparatus and a method for decoding, and a receiving terminal. The apparatus for checking decoded data includes: an arithmetic unit to perform a check computation on decoded bits output from decoders in every clock cycle to obtain a computation result, where the check computation is performed by: denoting each decoded bit as a polynomial, computing the sum of the polynomials and performing polynomial modular arithmetic on the sum; and an output unit configured to output a check result, where the check result is the sum of the computation results in all the clock cycles during a decoding process.
|Modified condition/decision coverage test case automation|
This embodiment relates to software verification and in particular to automatic generation of modified condition/decision coverage (mc/dc) tests scenarios. A system and method for reducing modified condition/decision coverage (mc/dc) test scenarios is described along with selection of test data automatically for an input boolean expression.
|Central processing unit and arithmetic unit|
There is a need to provide a central processing unit capable of improving the resistance to power analysis attack without changing programs, lowering clock frequencies, and greatly redesigning a central processing unit of the related art. In a central processing unit, an arithmetic unit is capable of performing arithmetic operation using data irrelevant to data stored in a register group.
|Processor, information processing apparatus, and control method of processor|
A processor is includes cache memory; an arithmetic processing section that a load request loading an object data stored at a memory to the cache memory; a cache control part patent a process corresponding to the received load request; a memory management part which requests the object data corresponding to the request from the cache control part and header information containing information indicating whether or not the object data is a latest for the memory, and receives the header information responded by the memory; and a data management part that manages a write control of the data to the cache memory, and receives the object data responded by the memory based on the request. The requested data is transmitted from the memory to the data management part held by a cpu node without being intervened by the memory management part..
|Storage virtualization in a block-level storage system|
A data storage system that stores data has a logical address space divided into ordered areas and unordered areas. Retrieval of storage system metadata for a logical address is based on whether the address is located in an ordered area or an unordered area.
|Laminate and method of producing laminate|
A laminate according to an embodiment of the present invention includes: a resin substrate; a polyvinyl alcohol-based resin layer formed on one side of the resin substrate; and an antistatic layer formed on another side of the resin substrate and comprising a binder resin and a conductive material. The binder resin includes a polyurethane-based resin; the antistatic layer has an arithmetic average surface roughness ra of 10 nm or more; and the conductive material includes a conductive polymer..
|Resin film and method of producing resin film|
A resin film according to an embodiment of the present invention includes: a substrate film; and an antistatic layer formed on one side of the substrate film and including a binder resin and a conductive material. The binder resin includes a polyurethane-based resin; the antistatic layer has an arithmetic average surface roughness ra of 10 nm or more; and the conductive material includes a conductive polymer..
|Image processing device and recording medium storing program|
Image data in which persons are captured is accumulated in association with information indicating dates of taking the image data, the image data is subjected to person recognition processing for recognizing the captured persons, and image data in which a person of interest is captured is extracted. Actual age information of the person of interest for each piece of the extracted image data is obtained, and estimated age information of the person of interest which estimated age information is obtained by estimating the age of the captured person of interest from the image data is obtained.
|Decoding method for decoding an incoming bitstream and method for performing the same|
There is disclosed a decoding method for decoding an incoming bitstream entropy-encoded according to an encoding method based on either of arithmetic encoding algorithm and non-arithmetic encoding algorithm, the incoming bitstream including syntax elements. The decoding method includes a first converting step of converting the incoming bitstream into an intermediate bitstream according to the encoding method, the first converting being capable of being omitted, a buffering step of selecting, according to the encoding method, either the intermediate bitstream or the incoming bitstream to store the selected bitstream onto a memory, and a second converting step of reading the selected bitstream from the memory to convert the read bitstream into syntax elements, the read bitstream being either the intermediate bitstream or the incoming bitstream..
|Optical body, display device, input device, and electronic device|
An optical body has an anti-reflection function and can be produced without repeating sequential coating to stack a low refractive index layer and a high refractive index layer. The optical body having an anti-reflection function includes a minute concave-convex surface having fluctuations.
|Stereoscopic moving picture generating apparatus and stereoscopic moving picture generating method|
A stereoscopic picture generating apparatus comprising: a storage unit to get stored with a first image containing partial images and a second image containing partial images corresponding respectively to the partial images contained in the first image; and an arithmetic unit to extract a first position defined as an existing position of a first partial image contained in the first image and a second position defined as an existing position of a second partial image contained in the first image, to calculate a first differential quantity defined as a difference between the first position and the second position, to calculate a third position defined as a new existing position of a third partial image contained in the second image that corresponds to the first partial image based on the first differential quantity, and to generate a third image based on the third position of the third partial image.. .
|Integrated circuit apparatus, three-dimensional integrated circuit, three-dimensional processor device, and process scheduler, with configuration taking account of heat|
The present invention provides a three-dimensional integrated circuit wherein generation of hot spot which makes a high temperature part as a result of intensively generated heat can be suppressed in. The integrated circuit apparatus comprises: a first circuit made of a memory circuit, a second circuit made of an arithmetic circuit, and a control circuit.
|Arithmetic circuit for performing division based on restoring division|
An arithmetic circuit for performing division based on restoring division includes an intermediate remainder register configured to store an intermediate remainder, a quotient prediction circuit configured to perform, based on information about two most significant digits of the intermediate remainder and a most significant digit of a divisor, quotient prediction having lower precision than a highest precision obtainable from the information, thereby generating a prediction result, a fixed-value multiplication circuit configured to output one or more n-th (n: integer) multiples of the divisor selected in response to the prediction result, one or more subtracters configured to subtract, from the intermediate remainder, the one or more n-th multiples of the divisor output from the fixed-value multiplication circuit, and a partial quotient calculating circuit configured to obtain a partial quotient in response to one or more carry-out bits of one or more subtractions performed by the one or more subtracters.. .
|Arithmetic circuit for calculating correction value|
An arithmetic circuit for calculating a correction value for a result of an arithmetic operation that is an addition or subtraction performed with respect to a first floating-point number and a second floating-point number smaller than the first floating-point number. The arithmetic circuit includes a generation unit configured to generate a significand of a normalized correction value for the result of the arithmetic operation and an exponent of the normalized correction value based on the sign, the significand, and the exponent of the second floating-point number when a difference between a result of subtracting the leading zero count of the significand of the first floating-point number from the corresponding exponent and a result of subtracting a leading zero count of the significand of the second floating-point number from the corresponding exponent is larger than or equal to a second predetermined value..
|Dividing device and dividing method|
A dividing device includes: shifting circuits which left-shift the mantissa parts of the dividend and the divisor by a first and a second count values; a digit number arithmetic circuit which calculates a quotient digit number expected value based on the first count value and the second count value; a dividing circuit which outputs a quotient and a remainder in sequence on a digit-by-digit basis based on the mantissa parts of the dividend and the divisor left-shifted by the shifting circuits; a subtracting circuit which subtracts an exponent part of the floating-point number being the divisor from an exponent part of the floating-point number being the dividend to output a resultant value; and a control circuit which outputs a mantissa part and an exponent part of a floating-point number being a quotient.. .