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Address Space patents



      
           
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Date/App# patent app List of recent Address Space-related patents
04/17/14
20140108890
 Accessing data stored in a dispersed storage memory patent thumbnailnew patent Accessing data stored in a dispersed storage memory
A method begins by a processing module forward error correction (fec) encoding data to produce fec encoded data and dividing the fec encoded data into a set of fec encoded words. The method continues with the processing module generating integrity information based on the data and generating a word name for an fec encoded word of the set of fec encoded words.
04/17/14
20140108885
 High reliability memory controller patent thumbnailnew patent High reliability memory controller
An integrated circuit includes a memory having an address space and a memory controller coupled to the memory for accessing the address space in response to received memory accesses. The memory controller further accesses a plurality of data elements in a first portion of the address space, and reliability data corresponding to the plurality of data elements in a second portion of the address space..
04/17/14
20140108767
 Method and system for extending virtual address space of process performed in operating system patent thumbnailnew patent Method and system for extending virtual address space of process performed in operating system
A method of extending a virtual address space of a process executed in an operating system includes selecting a virtual address range included in a virtual address space corresponding to the process and the number of a plurality of extended virtual address ranges, extending and thereby setting the virtual address space to a multi-virtual address space based on the selected virtual address range and the selected number of the plurality of extended virtual address ranges, and providing the multi-virtual address space to the process.. .
04/10/14
20140101405
 Reducing cold tlb misses in a heterogeneous computing system patent thumbnailReducing cold tlb misses in a heterogeneous computing system
Methods and apparatuses are provided for avoiding cold translation lookaside buffer (tlb) misses in a computer system. A typical system is configured as a heterogeneous computing system having at least one central processing unit (cpu) and one or more graphic processing units (gpus) that share a common memory address space.
04/10/14
20140101403
 Application-managed translation cache patent thumbnailApplication-managed translation cache
Mechanisms are provided, in a data processing system, for accessing a memory location in a physical memory of the data processing system. With these mechanisms, a request is received from an application to access a memory location specified by an effective address in an application address space.
04/10/14
20140101400
 Store peripheral component interconnect (pci) function controls instruction patent thumbnailStore peripheral component interconnect (pci) function controls instruction
An instruction is provided that includes an opcode field to identify a store instruction to store in a designated location current values of operational parameters of an adapter function of an adapter; a first field to identify a location, the contents of which include a function handle identifying a handle of the adapter function for which the store instruction is being performed, and an indication of an address space associated with the adapter function identified by the function handle to which the store instruction applies; and a second field to identify the designated location of where a result of the store instruction is to be stored. Execution of the instruction includes obtaining information from a function information block associated with the adapter function; and copying the information from the function information block into the designated location, based on completion of one or more validity checks with one or more predefined results..
04/10/14
20140101376
 Apparatus, system, and method for conditional and atomic storage operations patent thumbnailApparatus, system, and method for conditional and atomic storage operations
An apparatus, system, and method are disclosed for implementing conditional storage operations. Storage clients access and allocate portions of an address space of a non-volatile storage device.
04/10/14
20140101375
 Apparatus, system, and method for allocating storage patent thumbnailApparatus, system, and method for allocating storage
An apparatus, system, and method are disclosed for allocating non-volatile storage. The storage device may present a logical address, which may exceed a physical storage capacity of the device.
04/03/14
20140096254
 Efficient data transfer in a virus co-processing system patent thumbnailEfficient data transfer in a virus co-processing system
Circuits and methods are provided for detecting, identifying and/or removing undesired content. According to one embodiment, a method for virus co-processing is provided.
04/03/14
20140096148
 Fast remote procedure call patent thumbnailFast remote procedure call
A method for performing a remote procedure call between an application processor and a digital signal processor within a computing device. The computing device may compile interface description language data to generate stub software that executes on the application processor and skel software that executes on the digital signal processor.
04/03/14
20140095942
Providing service address space for diagnostics collection
A method and system are provided for providing a service address space for diagnostics collection. The method includes: providing a service co-processor attached to a main processor, wherein the service co-processor maintains an independent copy of the main processor's address space in the form of a service address space; and updating the service address space by receiving storage update packets from the main processor and applying the storage update packets to the service address space..
04/03/14
20140095651
Memory bus protocol to enable clustering between nodes of distinct physical domain address spaces
A system and method for transferring data and messages between nodes in a cluster is disclosed. Each node in the cluster is a separate physical domain but is connected to other nodes in the cluster through point-to-point high speed links.
03/27/14
20140089585
Hierarchy memory management
In one embodiment, a storage system comprises: a first type interface being operable to communicate with a server using a remote memory access; a second type interface being operable to communicate with the server using a block i/o (input/output) access; a memory; and a controller being operable to manage (1) a first portion of storage areas of the memory to allocate for storing data, which is to be stored in a physical address space managed by an operating system on the server and which is sent from the server via the first type interface, and (2) a second portion of the storage areas of the memory to allocate for caching data, which is sent from the server to a logical volume of the storage system via the second type interface and which is to be stored in a storage device of the storage system corresponding to the logical volume.. .
03/27/14
20140089572
Distributed page-table lookups in a shared-memory system
The disclosed embodiments provide a system that performs distributed page-table lookups in a shared-memory multiprocessor system with two or more nodes, where each of these nodes includes a directory controller that manages a distinct portion of the system's address space. During operation, a first node receives a request for a page-table entry that is located at a physical address that is managed by the first node.
03/27/14
20140089444
Methods, apparatus and systems for facilitating rdma operations with reduced doorbell rings
Methods, apparatus and systems for reducing usage of doorbell rings in connection with rdma operations. A portion of system memory is employed as a memory-mapped input/output (mmio) address space configured to be accessed via a hardware networking device.
03/20/14
20140082313
Storage class memory evacuation
Embodiments relate to methods, systems and computer program products for evacuating a portion of a storage class memory. Upon receiving a request to evacuate the portion of the storage class memory a determination is made if the requested evacuation will result in a storage shortage.
03/06/14
20140068182
Storage virtualization in a block-level storage system
A data storage system that stores data has a logical address space divided into ordered areas and unordered areas. Retrieval of storage system metadata for a logical address is based on whether the address is located in an ordered area or an unordered area.
03/06/14
20140068152
Method and system for storage address re-mapping for a multi-bank memory device
A method and system for storage address re-mapping in a multi-bank memory is disclosed. The method includes allocating logical addresses in blocks of clusters and re-mapping logical addresses into storage address space, where short runs of host data dispersed in logical address space are mapped in a contiguous manner into megablocks in storage address space.
03/06/14
20140068138
Embedded processor with virtualized security controls using guest identifications, a common kernel address space and operational permissions
A method includes assigning unique guest identifications to different guests, specifying an address region and permissions for the different guests and controlling a guest jump from one physical memory segment to a second physical memory segment through operational permissions defined in a root memory management unit that supports guest isolation and protection.. .
02/27/14
20140059273
Host apparatus and memory device
According to one embodiment, a host apparatus is capable of accessing memory device. The host apparatus includes application software, a dedicated file system, and an interface circuit.
02/27/14
20140059234
Switch management system and method
Methods and systems for managing a service provider switch are provided. According to one embodiment, a method is provided for provisioning a switch with a network-based managed internet protocol (ip) service.
02/20/14
20140049551
Shared virtual memory
A method and system for shared virtual memory between a central processing unit (cpu) and a graphics processing unit (gpu) of a computing device are disclosed herein. The method includes allocating a surface within a system memory.
02/20/14
20140049550
Shared virtual memory
Embodiments of the invention provide a programming model for cpu-gpu platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices.
02/13/14
20140047419
Handling pointers in program code in a system that supports multiple address spaces
Some embodiments include a processing subsystem that compiles program code to generate compiled program code. In these embodiments, while compiling the program code, the processing subsystem first identifies a pointer in the program code that points to an unspecified address space.
02/13/14
20140047293
Semiconductor circuit and methodology for in-system scan testing
A semiconductor circuit comprising a digital circuit portion, which comprises a combinatorial logic block. The semiconductor circuit further comprises a scan chain for loading and applying a predefined digital test pattern to inputs of the combinatorial logic block.
02/13/14
20140047229
Using a trusted platform module for boot policy and secure firmware
Embodiments of apparatuses and methods for using a trusted platform module for boot policy and secure firmware are disclosed. In one embodiment, a trusted platform module includes a non-volatile memory, a port, and a mapping structure.
02/13/14
20140047204
Providing service address space for diagnostics collection
A method and system are provided for providing a service address space for diagnostics collection. The system includes: a service co-processor attached to a main processor, wherein the service co-processor maintains an independent copy of the main processor's address space in the form of a service address space; and a storage update receiving component for updating the service address space by receiving storage update packets from the main processor and applying these to the service address space.
02/06/14
20140040565
Shared memory space in a unified memory model
Methods and systems are provided for mapping a memory instruction to a shared memory address space in a computer arrangement having a cpu and an apd. A method includes receiving a memory instruction that refers to an address in the shared memory address space, mapping the memory instruction based on the address to a memory resource associated with either the cpu or the apd, and performing the memory instruction based on the mapping..
02/06/14
20140040431
Systems and methods for an opc ua server
A system includes an opc ua server having a memory configured to provide an address space arranged into a plurality of reference nodes, in which each reference node is associated with data stored in a data source. The system further includes a processor configured to receive an opc ua client request for the data associated with a particular reference node.
01/30/14
20140032697
Storage system with multicast dma and unified address space
A system and method for clients, a control module, and storage modules to participate in a unifed address space in order to and read and write data efficiently using direct-memory access. The method for reading data includes determining a first location in a first memory to write a first copy of the data, a second location in a second memory to write a second copy of the data, where the first memory is located in a first storage module including a first persistent storage and the second memory is located in a second storage module including a second persistent storage.
01/30/14
20140029621
Method for learning media access control address, network device, and system
Embodiments of the present invention provide a method for learning a media access control address, a network device and a system. The method includes: generating a key value according to a key field of a received packet, and obtaining an index value corresponding to the key value according to the key value; performing a linear random iteration on the index value according to a preset number of iterations; searching, according to an iteration index value obtained during a first iteration, in a mac address pool for a mac address corresponding to the iteration index value obtained during the first iteration; and learning a mac address of the packet according to a search result.
01/23/14
20140025872
Systems and methods for contextual storage
A storage layer presents logical address space of a non-volatile storage device. The storage layer maintains logical interfaces to the non-volatile storage device, which may include arbitrary, any-to-any mappings between logical identifiers and storage resources.
01/23/14
20140025852
Configurable response generator for varied regions of system address space
A bus interconnect for interconnecting one or more master devices with one or more slave devices in a system includes at least one slave interface module adapted for communicating with a corresponding one of the master devices and at least one master interface module adapted for communicating with a corresponding one of the slave devices. The bus interconnect further includes a configurable response module coupled with the slave interface module.
01/23/14
20140023081
Method and apparatus for transporting ethernet services
Frames of customer traffic may be encapsulated by adding mac-in-mac (mim) encapsulation fields for transportation of the frames over a portion of provider network. The mim encapsulated traffic may be further encapsulated using vpls by adding vpls encapsulation fields for transportation of the frames over another portion of the provider network.
01/23/14
20140023078
Method and apparatus for transporting ethernet services
Frames of customer traffic may be encapsulated by adding mac-in-mac (mim) encapsulation fields for transportation of the frames over a portion of provider network. The mim encapsulated traffic may be further encapsulated using vpls by adding vpls encapsulation fields for transportation of the frames over another portion of the provider network.
01/16/14
20140019800
Inadvertent freed storage recovery
An abnormal termination recovery is performed where storage is referenced shortly after the storage has been freed. More specifically, when storage is freed, and that storage is accessed, an abnormal termination error (e.g., a page translation exception event) occurs due to referencing storage that has not been obtained.
01/16/14
20140019711
Dispersed storage network virtual address space
A dispersed storage network utilizes a virtual address space to store data. The dispersed storage network includes a dispersed storage device for receiving a request relating to a data object stored in the dispersed storage network and determining a virtual memory address assigned to the data object.
01/16/14
20140019706
System and method of logical object management
A virtual allocation unit is allocated in a virtual address space corresponding to a filesystem, in response to an allocation requirement, related to a logical object in the filesystem. The size of the virtual allocation unit is determined in accordance with the current physical size of the logical object.
01/16/14
20140019691
System, method, and computer program product for invalidatng cache lines
A system, method, and computer program product are provided for invalidating cache lines. In use, one or more cache lines that hold data from within a region of a memory address space are invalidated..
01/09/14
20140013045
Non-volatile ram disk
A method and system are disclosed. In one embodiment the method includes allocating several memory locations within a phase change memory and switch (pcms) memory to be utilized as a random access memory (ram) disk.
01/02/14
20140006746
Virtual memory address range register
Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware.
01/02/14
20140006483
Systems and methods for multi-context media control and playback
A method for controlling media presentation is disclosed. In some implementations, the method is performed at a first electronic device having one or more processors and memory storing one or more programs for execution by the one or more processors.
01/02/14
20140002701
Pixel and method for feedback based resetting of a pixel
A storage system, a non-transitory computer readable medium and a method for pre-fetching. The method may include presenting, by a storage system and to at least one host computer, a logical address space; determining, by a fetch module, to fetch a certain data portion from a data storage device to a cache memory of the storage system; determining, by a pre-fetch module, whether to pre-fetch at least one additional data portion from at least one data storage device to the cache memory based upon at least one characteristic of a mapping tree that maps one or more contiguous ranges of addresses related to the logical address space and one or more contiguous ranges of addresses related to the physical address space; and pre-fetching the at least one additional data portions if it is determined to pre-fetch the at least one additional data portions..
12/26/13
20130346634
Semiconductor device and data processing system
The semiconductor device employs, in order to allow other external devices to directly access resources it possesses in its own address space, in an external interface circuit, external terminals which input a part of the address signal required for access from outside, a supplementary register which supplements the upper portion of address information that has been input from the external terminals, a mode register accessible from outside, and an address control circuit which generates an address signal to access the address space in a form based on information input from the external terminals, required supplementary information, and mode information of the mode register.. .
12/26/13
20130346618
Method and apparatus for ip commissioning and decommissioning in orchestrated computing environments
A server computer (ipcds) for commissioning/decommissioning ip resources to server instances (si) provisioned using an orchestration solution. The server and client computers constitute a client-server architecture.
12/19/13
20130339565
Method, device and system for aggregation of shared address devices
Techniques and mechanisms for managing resources of an aggregate device which spans multiple physical devices of a computer platform. In an embodiment, an aggregation device coupled to a host bus of the computer platform receives resource information generated by a pre-boot software process of the computer platform.
12/12/13
20130332700
Cloud storage arrangement and method of operating thereof
There is provided a storage arrangement and a method of operating thereof. The storage arrangement comprises a first storage system and one or more second storage systems operatively coupled to the first storage system.
12/12/13
20130329599
Method of network connectivity analyses and system thereof
There are provided network analyzer and method of analyzing connectivity between a source and a destination. The method comprises: upon obtaining a partial topological network model comprising at least one cloud, generating the one or more paths between the source and the destination, specifying the cloud as a source point of the one or more paths if at least one source network address belongs to the cloud address space and specifying the cloud as a destination point of the one or more paths between the source and the destination if at least one destination network address belongs to the cloud address space.
12/12/13
20130329482
High bandwidth memory interface
A memory module that includes a buffer and a plurality of synchronous memory devices. The memory module also includes bidirectional bus lines, and each of the synchronous memory devices has bidirectional data terminals.
12/12/13
20130328895
Graphics library extensions
Methods for enabling graphics features in processors are described herein. Methods are provided to enable trinary built-in functions in the shader, allow separation of the graphics processor's address space from the requirement that all textures must be physically backed, enable use of a sparse buffer allocated in virtual memory, allow a reference value used for stencil test to be generated and exported from a fragment shader, provide support for use specific operations in the stencil buffers, allow capture of multiple transform feedback streams, allow any combination of streams for rasterization, allow a same set of primitives to be used with multiple transform feedback streams as with a single stream, allow rendering to be directed to layered framebuffer attachments with only a vertex and fragment shader present, and allow geometry to be directed to one of an array of several independent viewport rectangles without a geometry shader..
12/05/13
20130326124
Power management architecture based on micro/processor architecture with embedded and external nvm
A control unit for power supply circuits of points of load (pol) of an electronic system includes a means for autonomous customization by the customer-user of the original control program residing in the rom of the device, as well as configuration of control parameters of the pol. Microprocessor architecture of the device includes a dedicated logic block and a rewritable non-volatile memory coupled to the data bus of the device or to an auxiliary bus thereof, thus providing a means for software extension of the power supply circuits.
11/28/13
20130318308
Scalable cache coherence for a network on a chip
Maintaining cache coherence in a system-on-a-chip with both multiple cache coherent master ip cores (ccms) and non-cache coherent master ip cores (ncms). A plug-in cache coherence manager (cm), coherence logic in agents, and an interconnect are used for the soc to provide a scalable cache coherence scheme that scales to an amount of ccms in the soc.
11/21/13
20130311761
Intelligently loading legacy option roms in a computing system
Intelligently loading legacy option roms in a computing system, including: generating, by a legacy option rom manager, an inventory for the computing system, wherein the inventory for the computing system identifies one or more devices in the computing system; determining, by the legacy option rom manager for each option rom available for loading, whether a device supported by the option rom is included in the inventory for the computing system; responsive to determining that the device supported by the option rom is not included in the inventory for the computing system, preventing the option rom from being loaded into an option rom address space; and responsive to determining that the device supported by the option rom is included in the inventory for the computing system, enabling the option rom to be loaded into the option rom address space.. .
11/21/13
20130311748
System and method for storing data in a virtualized memory system with destructive reads
A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur.
11/21/13
20130311707
Storage control apparatus and storage control method
A storage control apparatus comprises a storage unit, an association unit, and an execution unit. The storage unit stores association information showing multiple physical chunks which are configured in a physical address space of a nonvolatile semiconductor memory, multiple logical storage areas which are configured in a logical address space of the nonvolatile semiconductor memory, multiple logical chunks which are respectively associated with the multiple physical chunks, and an association between a logical storage area and a logical chunk.
11/21/13
20130310000
Communication systems and methods
Disclosed are communication systems and methods. According to an exemplary method, there is a step of receiving a first message from a first mobile device via a first short range base station following a first protocol, such as wimax or lte, for example.
11/14/13
20130305105
Deterministic data verification in storage controller
Exemplary method, system, and computer program embodiments for performing deterministic data verification by a storage controller are provided. Each of a plurality of concurrent write tasks is configured to be placed in a plurality of overlapping data storage ranges by performing at least one of: implementing a data generation function for generating pseudo-random data using a data seed, and generating a range map, the range map utilized as a lookup data structure to verify a chronological order for performing the plurality of concurrent write tasks, wherein a data address space is first designated in the range map as undetermined.
11/14/13
20130305013
Microprocessor that makes 64-bit general purpose registers available in msr address space while operating in non-64-bit mode
A microprocessor includes hardware registers that instantiate the ia-32 architecture edx and eax gprs and hardware registers that instantiate the intel 64 architecture r8-r15 gprs. The microprocessor associates with each of the r8-r15 gprs a respective unique msr address.
10/31/13
20130290759
Enhanced system sleep state support in servers using non-volatile random access memory
A non-volatile random access memory (nvram) is used in a computer system to enhance support to sleep states. The computer system includes a processor, a non-volatile random access memory (nvram) that is byte-rewritable and byte-erasable, and power management (pm) module.
10/31/13
20130290753
Memory column drowsy control
In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array.
10/31/13
20130290662
Information security techniques including detection, interdiction and/or mitigation of memory injection attacks
Methods of detecting malicious code injected into memory of a computer system are disclosed. The memory injection detection methods may include enumerating memory regions of an address space in memory of computer system to create memory region address information.
10/31/13
20130287026
Extension of logical networks across layer 3 virtual private networks
A method of manages a set of managed forwarding elements that forward data between machines. The method configures (1) a first managed forwarding element to operate in a first network that uses first and second address spaces that at least partially overlap with each other, (2) a second managed forwarding element to operate in a second network that uses the first address space, and (3) a third managed forwarding element to operate in a third network that uses the second address space.
10/17/13
20130275735
Apparatus, system, and method for persistent user-level thread
Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space.
10/17/13
20130275707
Address space management while switching optically-connected memory
Memory is dynamically switched through the optical-switching fabric using at least one communication pattern to transfer memory space in the memory blades from one processor to an alternative processor in the processor blades without physically copying data in the memory to the processors. Various communication patterns for the dynamically switching are supported..
10/17/13
20130275704
Address space management while switching optically-connected memory
A remote processor is signaled for receiving a remote machine memory address (rmma) space that contains data to be transferred. The rmma space is mapped to a free portion of a system memory address (sma) space of the remote processor.
10/17/13
20130275656
Apparatus, system, and method for key-value pool identifier encoding
Apparatuses, systems, and methods are disclosed for a key-value store. A method includes encoding a key of a key-value pair into a logical address of a sparse logical address space for a non-volatile medium.
10/17/13
20130275608
Network-layer protocol substituting ipv6
A new network layer protocol with ipv4 compatibility is proposed. Use the existing internet as the prototype to build network blocks of the same size.
10/17/13
20130275447
Method of migrating stored data and system thereof
There is provided a storage system and a method of moving a source data portion from a source logical volume to a destination logical volume. The method comprises: configuring a source mapping data structure to comprise an entry indicative of mapping between logical addresses corresponding to source data portion and addresses corresponding to source data portion and related to a physical address space; and, responsive to a move command, providing an atomic operation comprising configuring a destination mapping data structure to comprise an entry associated with said at least one destination range and comprising a reference to said entry in the source mapping data structure; and configuring said at least one entry in the source mapping data structure dssrc to bear an indication that said one or more contiguous ranges of addresses corresponding to said source data portion in the source logical volume vsrc are unavailable to a client..
10/17/13
20130272308
Method and apparatus for transporting ethernet services
Frames of customer traffic may be encapsulated by adding mac-in-mac (mim) encapsulation fields for transportation of the frames over a portion of provider network. The mim encapsulated traffic may be further encapsulated using vpls by adding vpls encapsulation fields for transportation of the frames over another portion of the provider network.
10/10/13
20130268947
Automatically deriving a command for starting a program in an operating system of a computer
A method, apparatus and program product for automatically deriving a command for starting a program in an operating system of a computer, the method comprising the steps of: identifying an address space provided by an operating system; identifying a program in the address space; searching data logged by the operating system as a result of processing the identified program to identify a start command for initiating processing of the identified program; and outputting the identified start command.. .
10/10/13
20130268730
Grid storage system and method of operating thereof
A method of operating a storage system includes: configuring the address space so that each lba is assigned to at least two servers among a plurality of at least three servers in a control grid: to a primary server with a primary responsibility for handling requests corresponding to said lba, and to a secondary server with a secondary responsibility for handling requests corresponding to said lba. In response to a request corresponding to a certain lba range, generating by a data server having primary responsibility over the certain lba range, a primary cache object; identifying a data server configured as a secondary data server with regard to the certain lba range; and generating a redundancy cache object corresponding to the primary cache object only at the identified secondary data server, the redundancy cache object to be used by the identified secondary data server when taking the primary responsibility..
10/10/13
20130268728
Apparatus and method for implementing a multi-level memory hierarchy having different operating modes
A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, pcms memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” higher performance memory devices such as dram placed in front of the far memory and are used to mask some of the performance limitations of the far memory.


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Address Space topics: Address Space, Computer System, Logical Address, Operating System, Ip Address, The Operating System, Virtual Private Network, Granularity, Volatile Memory, Atomic Operation, Random Access, Power Management, Encapsulation, Ethernet Services, Contiguous

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