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This page is updated frequently with new Address Space-related patent applications. Subscribe to the Address Space RSS feed to automatically get the update: related Address RSS feeds. RSS updates for this page: Address Space RSS RSS


Coherent attached processor proxy supporting coherence state update in presence of dispatched master

Coherent attached processor proxy supporting coherence state update in presence of dispatched master

Method and system for improving the data security of cloud computing

Date/App# patent app List of recent Address Space-related patents
08/21/14
20140237157
 System and method for providing an address cache for memory map learning patent thumbnailSystem and method for providing an address cache for memory map learning
A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system provides a one-hot address cache comprising a plurality of one-hot addresses and a host interface to a host memory controller of a host system.
08/14/14
20140229685
 Coherent attached processor proxy supporting coherence state update in presence of dispatched master patent thumbnailCoherent attached processor proxy supporting coherence state update in presence of dispatched master
A coherent attached processor proxy (capp) of a primary coherent system receives a memory access request specifying a target address in the primary coherent system from an attached processor (ap) external to the primary coherent system. The capp includes a capp directory of contents of a cache memory in the ap that holds copies of memory blocks belonging to a coherent address space of the primary coherent system.
08/14/14
20140229684
 Coherent attached processor proxy supporting coherence state update in presence of dispatched master patent thumbnailCoherent attached processor proxy supporting coherence state update in presence of dispatched master
A coherent attached processor proxy (capp) of a primary coherent system receives a memory access request specifying a target address in the primary coherent system from an attached processor (ap) external to the primary coherent system. The capp includes a capp directory of contents of a cache memory in the ap that holds copies of memory blocks belonging to a coherent address space of the primary coherent system.
08/07/14
20140223576
 Method and system for improving the data security of cloud computing patent thumbnailMethod and system for improving the data security of cloud computing
A method and system for improving the data security of cloud computing comprising: users establishing an index information table for physical lun devices available to cloud computing service instances, and setting mapping rules of virtual lba address space for virtual lun devices and physical lba address space for data storage according to the index information table; according to the mapping rules, users establishing and saving a mapping relationship between virtual lba address space and physical lba address space for data storage; according to the mapping relationship, acquiring storage position information of actual data mapping to the virtual lba address space pointed by read/write requests, and completing i/o redirection. The system includes an establishment module, setting module, establishment and saving module, and redirection module.
08/07/14
20140223089
 Method and device for storing data in a flash memory using address mapping for supporting various block sizes patent thumbnailMethod and device for storing data in a flash memory using address mapping for supporting various block sizes
The present invention relates to a method and device for storing data in a flash memory using address mapping for supporting various block sizes. A storage device determines the size of a block that a host system uses on the basis of the size of data that the host system requests and uses the determined block size as a mapping unit.
08/07/14
20140223083
 Zone-based defragmentation methods and user devices using the same patent thumbnailZone-based defragmentation methods and user devices using the same
A defragmentation method of a user device which includes a host and a nonvolatile storage device includes: determining whether fragments of a first file stored at the nonvolatile storage device are in a same logical address zone; and executing defragmentation on the fragments of the first file if the fragments of the first file are in different logical address zones by moving the fragments of the first file to a logical address space corresponding to at least one of the different logical address zones.. .
07/31/14
20140211847
 Video encoding system and method patent thumbnailVideo encoding system and method
A video processing method for a video image consisting of a plurality of units includes: generating a plurality of information types of at least a first unit and a second unit neighbouring the first unit; and storing the plurality of information types of the first unit in a first continuous address space in a buffer and storing the plurality of information types of the second unit in a second continuous address space in the buffer, wherein the first continuous address space is adjacent to the second continuous address space. The plurality of information types of the first and second units are required for coding a specific unit, and the order of the stored plurality of information types of the first and second units is manipulated in each of the first and second continuous address spaces..
07/24/14
20140208064
 Virtual memory management system with reduced latency patent thumbnailVirtual memory management system with reduced latency
A computer system using virtual memory provides hybrid memory access either through a conventional translation between virtual memory and physical memory using a page table possibly with a translation lookaside buffer, or a high-speed translation using a fixed offset value between virtual memory and physical memory. Selection between these modes of access may be encoded into the address space of virtual memory eliminating the need for a separate tagging operation of specific memory addresses..
07/24/14
20140208062
 Storage address space to nvm address, span, and length mapping/converting patent thumbnailStorage address space to nvm address, span, and length mapping/converting
Storage address space to nvm address, span, and length mapping/converting is performed by a controller for a solid-state storage system that includes a mapping function to convert a logical block address from a host to an address of a smallest read unit of the nvm. The mapping function provides span and length information corresponding to the logical block address.
07/24/14
20140208061
 Locating data in non-volatile memory patent thumbnailLocating data in non-volatile memory
Systems and methods presented herein provide for locating data in non-volatile memory by decoupling a mapping unit size from restrictions such as the maximum size of a reducible unit to provide efficient mapping of larger mapping units. In one embodiment, a method comprises mapping a logical page address in a logical block address space to a read unit address and a number of read units in the non-volatile memory.
07/24/14
20140208059
Highly configurable memory architecture for partitioned global address space memory systems
A system and method for identifying from an address an appropriate target node and a location in that node that holds desired data related to that address is provided. The system and method includes a logical address generator that generates a logical address.
07/24/14
20140208034
System and method for efficient paravirtualized os process switching
The exemplary embodiments described herein relate to systems and methods for improved process switching of a paravirtualized guest with a software-based memory management unit (“mmu”). One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, resulting in a performance of the following: create a plurality of new processes for each of a plurality of virtual environments, each of the virtual environments assigned one of a plurality of address space identifiers (“asids”) stored in a cache memory, perform a process switch to one of the virtual environments thereby designating the one of the virtual environments as the active virtual environment, determine whether the active virtual environment has exhausted each of the asids, and flush a cache memory when it is determined that the active virtual environment has exhausted each of the asids..
07/24/14
20140204098
System, method, and computer program product for graphics processing unit (gpu) demand paging
A system, method, and computer program product are provided for gpu demand paging. In operation, input data is addressed in terms of a virtual address space.
07/17/14
20140201305
Network overlay system and method using offload processors
A memory bus connected module, connectable to a first virtual switch for providing input-output (io) virtualization services is disclosed. The module can include a second virtual switch coupled to the first virtual switch via a memory bus connection, a plurality of offload processors coupled to the memory bus connection, and at least one memory unit connected to, and separately addressable by, the multiple offload processors, and configured to receive data directed to a specific memory address space for processing by at least one of the offload processors..
07/10/14
20140196148
Methods and systems for preventing security breaches
A security payload is attached to a received binary executable file. The security payload is adapted to intercept application programming interface (api) calls to system resources from the binary executable file via export address redirection back to the security payload.
07/10/14
20140195765
Implementing user mode foreign device attachment to memory channel
A method, system and computer program product are provided for implementing attachment of a user mode foreign device to a memory channel in a computer system. A user mode foreign device is attached to the memory channel using memory mapping of device registers and device buffers to the processor address space.
07/10/14
20140195716
Method and apparatus for dynamically allocating memory address space between physical memories
A memory address space for each of a plurality of physical memories in a microprocessor-based system is allocated prior to knowing the desired logical size of at least one of the physical memories. At least two of the allocated memory address spaces overlap at least a portion of each other.
07/03/14
20140189434
System and method for achieving high performance data flow among user space processes in storage systems
Fault isolation capabilities made available by user space can be provided for a embedded network storage system without sacrificing efficiency. By giving user space processes direct access to specific devices (e.g., network interface cards and storage adapters), processes in a user space can initiate input/output requests without issuing system calls (and entering kernel mode).
07/03/14
20140189422
Information processing apparatus and stored information analyzing method
An information processing apparatus includes: a dividing unit that divides a storage region in accordance with storage region management information, the storage region management information and type information; a setting unit that selects a first division region from division regions indicative of the divided storage region and that puts the first division region in a stand-by state; a detecting unit that detects an abnormality in information processing when the information processing is performed using a second division region of the division regions; a controlling unit that puts the second division region in the stand-by state and that causes the first division region, which has been in the stand-by state, to recover; and an analyzing unit that adds the second division region that is in the stand-by state to a physical address space, and that analyzes information stored in the second division region.. .
07/03/14
20140189286
Wear leveling with marching strategy
A method for managing utilization of a memory including a physical address space comprises mapping logical addresses of data objects to locations within the physical address space, and defining a plurality of address segments in the space as an active window. The method comprises allowing writes of data objects having logical addresses mapped to locations within the plurality of address segments in the active window.
07/03/14
20140189216
Apparatus, system, and method for conditional and atomic storage operations
An apparatus, system, and method are disclosed for implementing conditional storage operations. Storage clients access and allocate portions of an address space of a non-volatile storage device.
07/03/14
20140189197
Sharing serial peripheral interface flash memory in a multi-node server system on chip platform environment
Methods and apparatus related to sharing serial peripheral interface (spi) flash memory in a multi-node server soc (system on chip) platform environment are described. In one embodiment, multi-port non-volatile memory is shared by a plurality of system on chip (soc) devices.
07/03/14
20140189159
Methods, systems, and computer program products for identifying a protocol address in a scope-specific address space
Methods and systems are described for identifying a protocol address in a scope-specific address space. First address information is detected identifying a first-second protocol address identifying, according to a network protocol, a second node to a first node in the network and/or a second-first protocol address identifying, according to the protocol, the first node to the second node.
07/03/14
20140189153
Methods, systems, and computer program products for routing based on a scope-specific address
Methods and systems are described for routing based on a scope-specific address space. In an aspect, data is received data, from a previous node by a current node via a previous network interface operatively coupling the current node to a network, in a data unit that is specified according to a network protocol and that includes address information.
06/19/14
20140173628
Dynamic device virtualization
A system and method for providing dynamic device virtualization is herein disclosed. According to one embodiment, the computer-implemented method includes providing a device virtualization via context switching between a guest user process and a host.
06/19/14
20140173171
System and method to create a non-volatile bootable ram disk
A manufacturing testing system includes an information handling system, a ram memory device including a reserved physical ram address space, non-volatile bootable disk, and a header for the reserved physical ram address space. The head may include a non-volatile bootable disk signature, a start physical address, a length of reserved space, and a processor..
06/19/14
20140173014
Communication protocol placement into switch memory
Direct memory transfer of data from the memory of a server to a memory of a switch. A server identifies a block of data in the memory of the server and a corresponding memory address space in the server.
06/19/14
20140168227
System and method for versioning buffer states and graphics processing unit incorporating the same
A system and method for versioning states of a buffer. In one embodiment, the system includes: (1) a page table lookup and coalesce circuit operable to provide a page table directory request for a translatable virtual address of the buffer to a page table stored in a virtual address space and (2) a page directory processing circuit associated with the page table lookup and coalesce circuit and operable to provide a translated virtual address based on the virtual address and a page table load response received from the page table..
06/12/14
20140164789
Authenticating microcode patches with external encryption engine
A single or multicore processor having a separate hardware cryptographic engine (hce) for microcode patch updates is presented. Microcode in each core is modified to utilize the hce for patch updates.
06/12/14
20140164730
System and methods for managing storage space allocation
A request for obtaining a space allocation descriptor is received by a block control layer of a storage system. The space allocation descriptor is indicative of one or more logical blocks free for allocation within a range of logical addresses.
06/12/14
20140164718
Methods and apparatus for sharing memory between multiple processes of a virtual machine
Methods and apparatus for sharing memory between multiple processes of a virtual machine are disclosed. A hypervisor associates a plurality of guest user memory regions with a first domain and assigns each associated user process an address space identifier to protect the different user memory regions from the different user processes.
06/05/14
20140156921
Methods for writing data to non-volatile memory-based mass storage devices
Methods of operating a non-volatile solid state memory-based mass storage device having at least one non-volatile memory component. In one aspect of the invention, the one or more memory components define a memory space partitioned into user memory and over-provisioning pools based on a p/e cycle count stored in a block information record.
05/29/14
20140149977
Assigning a virtual processor architecture for the lifetime of a software application
A method, system and computer-usable medium are disclosed for managing virtual processor operations. A dynamic loader receives a request to initiate the creation of a new process, followed by a virtual processor being assigned to an isolated execution environment.
05/29/14
20140149818
Diagnostic testing for a double-pumped memory array
A semiconductor chip and method for diagnostic testing of combinational logic in a logic and array system including logic built in self test (lbist) diagnostics are provided. The semiconductor chip includes a logic and array system, an lbist system, a clocking module, and an addressing module.
05/29/14
20140149817
Diagnostic testing for a double-pumped memory array
A semiconductor chip and method for diagnostic testing of combinational logic in a logic and array system including logic built in self test (lbist) diagnostics are provided. The semiconductor chip includes a logic and array system, an lbist system, a clocking module, and an addressing module.
05/29/14
20140148129
Wifi fixed wireless personal services
A method of providing access for wireless terminals to a packet core network. The method comprises attaching an access point to said packet core network via a cellular radio access network, defining a subnet associated with an internet protocol (ip) address space, and configuring said access point as a router of the subnet.
05/22/14
20140143483
Memory management schemes for non-volatile memory devices
A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory.
05/22/14
20140143482
Memory management schemes for non-volatile memory devices
A method includes storing data in a non-volatile memory that includes multiple memory blocks. At least first and second regions are defined in the non-volatile memory.
05/22/14
20140143474
Flexible wear management for non-volatile memory
Systems and methods of memory cell wear management that can achieve a more uniform distribution of write cycles across a memory cell address space. The systems and methods allow physical addresses of memory cells subjected to a high number of write cycles to be swapped with physical addresses of memory cells subjected to a lower number of write cycles.
05/22/14
20140143368
Distributed symmetric multiprocessing computing architecture
Example embodiments of the present invention includes systems and methods for implementing a scalable symmetric multiprocessing (shared memory) computer architecture using a network of homogeneous multi-core servers. The level of processor and memory performance achieved is suitable for running applications that currently require cache coherent shared memory mainframes and supercomputers.
05/15/14
20140136738
Emulated legacy bus operation over a bit-serial bus
Legacy bus operations, such as x86 i/o instructions having an address space separate from memory address space, are supported in a system in which i/o devices are coupled to a microcontroller connected via an spi bus or other bit-serial bus. Each legacy bus operation is recognized and trapped by an interface controller, such as a south-bridge controller, which maps the trapped legacy bus operation into a corresponding bit-serial bus transaction, and transacts this corresponding bit-serial bus transaction on the bit-serial bus.
05/08/14
20140129797
Configurable i/o address translation data structure
In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (tces) that translate addresses from an input/output (i/o) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing tce data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of tces, and a number of levels in the tce data structure is retained.
05/08/14
20140129795
Configurable i/o address translation data structure
In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (tces) that translate addresses from an input/output (i/o) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing tce data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of tces, and a number of levels in the tce data structure is retained.
05/01/14
20140123146
Efficient memory virtualization in multi-threaded processing units
A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (asid) to each task and constructing each virtual memory access request to include both a virtual address and the asid. During virtual to physical address translation, the asid selects a corresponding page table, which includes virtual to physical address mappings for the asid and associated task.
05/01/14
20140123145
Efficient memory virtualization in multi-threaded processing units
A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (asid) to each task and constructing each virtual memory access request to include both a virtual address and the asid. During virtual to physical address translation, the asid selects a corresponding page table, which includes virtual to physical address mappings for the asid and associated task.
05/01/14
20140122830
Operational efficiency of virtual tlbs
Various mechanisms are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (tlb) in a virtual machine environment. For example, one mechanism fills in entries in a shadow page table (spt) and additionally, speculatively fills in other entries in the spt based on various heuristics.
05/01/14
20140122829
Efficient memory virtualization in multi-threaded processing units
A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (asid) to each task and constructing each virtual memory access request to include both a virtual address and the asid. During virtual to physical address translation, the asid selects a corresponding page table, which includes virtual to physical address mappings for the asid and associated task.
04/24/14
20140115292
Dynamic obfuscation of heap memory allocations
Techniques, methods, systems, and computer-readable media for allocating and managing dynamically obfuscated heap memory allocations are described. In one embodiment a memory manager in a data processing system contains an addressor, to determine a first address of a program object in a first memory address space, and one or more encoders, to abstract memory access to the program object using the first address such that layout of the object data in the first address space differs from the layout of the object in a second address space.
04/24/14
20140115276
Intraprocedural privatization for shared array references within partitioned global address space (pgas) languages
Partitioned global address space (pgas) programming language source code is retrieved by an executed pgas compiler. At least one shared memory array access indexed by an affine expression that includes a distinct thread identifier that is constant and different for each of a group of program execution threads targeted to execute the pgas source code is identified within the pgas source code.
04/24/14
20140115088
Communication protocol placement into switch memory
Direct memory transfer of data from the memory of a server to a memory of a switch. A server identifies a block of data in the memory of the server and a corresponding memory address space in the server.
04/17/14
20140108890
Accessing data stored in a dispersed storage memory
A method begins by a processing module forward error correction (fec) encoding data to produce fec encoded data and dividing the fec encoded data into a set of fec encoded words. The method continues with the processing module generating integrity information based on the data and generating a word name for an fec encoded word of the set of fec encoded words.
04/17/14
20140108885
High reliability memory controller
An integrated circuit includes a memory having an address space and a memory controller coupled to the memory for accessing the address space in response to received memory accesses. The memory controller further accesses a plurality of data elements in a first portion of the address space, and reliability data corresponding to the plurality of data elements in a second portion of the address space..
04/17/14
20140108767
Method and system for extending virtual address space of process performed in operating system
A method of extending a virtual address space of a process executed in an operating system includes selecting a virtual address range included in a virtual address space corresponding to the process and the number of a plurality of extended virtual address ranges, extending and thereby setting the virtual address space to a multi-virtual address space based on the selected virtual address range and the selected number of the plurality of extended virtual address ranges, and providing the multi-virtual address space to the process.. .
04/10/14
20140101405
Reducing cold tlb misses in a heterogeneous computing system
Methods and apparatuses are provided for avoiding cold translation lookaside buffer (tlb) misses in a computer system. A typical system is configured as a heterogeneous computing system having at least one central processing unit (cpu) and one or more graphic processing units (gpus) that share a common memory address space.
04/10/14
20140101403
Application-managed translation cache
Mechanisms are provided, in a data processing system, for accessing a memory location in a physical memory of the data processing system. With these mechanisms, a request is received from an application to access a memory location specified by an effective address in an application address space.
04/10/14
20140101400
Store peripheral component interconnect (pci) function controls instruction
An instruction is provided that includes an opcode field to identify a store instruction to store in a designated location current values of operational parameters of an adapter function of an adapter; a first field to identify a location, the contents of which include a function handle identifying a handle of the adapter function for which the store instruction is being performed, and an indication of an address space associated with the adapter function identified by the function handle to which the store instruction applies; and a second field to identify the designated location of where a result of the store instruction is to be stored. Execution of the instruction includes obtaining information from a function information block associated with the adapter function; and copying the information from the function information block into the designated location, based on completion of one or more validity checks with one or more predefined results..
04/10/14
20140101376
Apparatus, system, and method for conditional and atomic storage operations
An apparatus, system, and method are disclosed for implementing conditional storage operations. Storage clients access and allocate portions of an address space of a non-volatile storage device.
04/10/14
20140101375
Apparatus, system, and method for allocating storage
An apparatus, system, and method are disclosed for allocating non-volatile storage. The storage device may present a logical address, which may exceed a physical storage capacity of the device.
04/03/14
20140096254
Efficient data transfer in a virus co-processing system
Circuits and methods are provided for detecting, identifying and/or removing undesired content. According to one embodiment, a method for virus co-processing is provided.
04/03/14
20140096148
Fast remote procedure call
A method for performing a remote procedure call between an application processor and a digital signal processor within a computing device. The computing device may compile interface description language data to generate stub software that executes on the application processor and skel software that executes on the digital signal processor.
04/03/14
20140095942
Providing service address space for diagnostics collection
A method and system are provided for providing a service address space for diagnostics collection. The method includes: providing a service co-processor attached to a main processor, wherein the service co-processor maintains an independent copy of the main processor's address space in the form of a service address space; and updating the service address space by receiving storage update packets from the main processor and applying the storage update packets to the service address space..
04/03/14
20140095651
Memory bus protocol to enable clustering between nodes of distinct physical domain address spaces
A system and method for transferring data and messages between nodes in a cluster is disclosed. Each node in the cluster is a separate physical domain but is connected to other nodes in the cluster through point-to-point high speed links.
03/27/14
20140089585
Hierarchy memory management
In one embodiment, a storage system comprises: a first type interface being operable to communicate with a server using a remote memory access; a second type interface being operable to communicate with the server using a block i/o (input/output) access; a memory; and a controller being operable to manage (1) a first portion of storage areas of the memory to allocate for storing data, which is to be stored in a physical address space managed by an operating system on the server and which is sent from the server via the first type interface, and (2) a second portion of the storage areas of the memory to allocate for caching data, which is sent from the server to a logical volume of the storage system via the second type interface and which is to be stored in a storage device of the storage system corresponding to the logical volume.. .
03/27/14
20140089572
Distributed page-table lookups in a shared-memory system
The disclosed embodiments provide a system that performs distributed page-table lookups in a shared-memory multiprocessor system with two or more nodes, where each of these nodes includes a directory controller that manages a distinct portion of the system's address space. During operation, a first node receives a request for a page-table entry that is located at a physical address that is managed by the first node.
03/27/14
20140089444
Methods, apparatus and systems for facilitating rdma operations with reduced doorbell rings
Methods, apparatus and systems for reducing usage of doorbell rings in connection with rdma operations. A portion of system memory is employed as a memory-mapped input/output (mmio) address space configured to be accessed via a hardware networking device.
03/20/14
20140082313
Storage class memory evacuation
Embodiments relate to methods, systems and computer program products for evacuating a portion of a storage class memory. Upon receiving a request to evacuate the portion of the storage class memory a determination is made if the requested evacuation will result in a storage shortage.
03/06/14
20140068182
Storage virtualization in a block-level storage system
A data storage system that stores data has a logical address space divided into ordered areas and unordered areas. Retrieval of storage system metadata for a logical address is based on whether the address is located in an ordered area or an unordered area.
03/06/14
20140068152
Method and system for storage address re-mapping for a multi-bank memory device
A method and system for storage address re-mapping in a multi-bank memory is disclosed. The method includes allocating logical addresses in blocks of clusters and re-mapping logical addresses into storage address space, where short runs of host data dispersed in logical address space are mapped in a contiguous manner into megablocks in storage address space.
03/06/14
20140068138
Embedded processor with virtualized security controls using guest identifications, a common kernel address space and operational permissions
A method includes assigning unique guest identifications to different guests, specifying an address region and permissions for the different guests and controlling a guest jump from one physical memory segment to a second physical memory segment through operational permissions defined in a root memory management unit that supports guest isolation and protection.. .
02/27/14
20140059273
Host apparatus and memory device
According to one embodiment, a host apparatus is capable of accessing memory device. The host apparatus includes application software, a dedicated file system, and an interface circuit.
02/27/14
20140059234
Switch management system and method
Methods and systems for managing a service provider switch are provided. According to one embodiment, a method is provided for provisioning a switch with a network-based managed internet protocol (ip) service.


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Address Space topics: Address Space, Computer System, Logical Address, Operating System, Ip Address, The Operating System, Virtual Private Network, Granularity, Volatile Memory, Atomic Operation, Random Access, Power Management, Encapsulation, Ethernet Services, Contiguous

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